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2016-11-16UefiCpuPkg/MpInitLib: Update AP information when BSP switchedJeff Fan
When BSP switched, we need to update some AP information. For example, ApStartupSignalBuffer and ApTopOfStack. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-11-16UefiCpuPkg/MpInitLib: Program AP stack in fixed addressJeff Fan
Currently, MpInitLib will program AP stack in dynamic address. Each processor will calculate its stack address by adding stack size based on the last stack address. That means AP may have the different stack address everytime it is wakeup by INIT-SIPI-SIPI. When all APs have wakeup to execute AP task, each each has been assigned one stack address. Once the timeout happened on some of APs, BSP will send INIT- SIPI-SIPI to wake up APs. We need to re-assign stack for APs. Based on the current implementation, we might assign one stack address used by other APs. It will cause the unexpected stack overlapped issue. This fix changed the stack assignment policy. We will record the stack address assigned to AP at first time AP wakeup. When AP failed on AP task, BSP could reassigned the same stack for it. Getting initial APIC ID in assembly code could help AP to get saved its stack address. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-11-16UefiCpuPkg/MpInitLib: Add InitFlag and CpuInfo in MP_CPU_EXCHANGE_INFOJeff Fan
Cc: Feng Tian <feng.tian@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-11-16UefiCpuPkg/MpInitLib: Remove CPU information from CPU_AP_DATAJeff Fan
Some CPU information (InitialApicId/ApicId/Health) are duplicated in CPU_AP_DATA and CPU_INFO_IN_HOB. This update is to remove the ones from CPU_AP_DATA and update MpInitLib to consume the ones from CPU_INFO_IN_HOB. V2: Fixed potential un-initialized variable issue. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-11-16UefiCpuPkg/MpInitLib: Force sending INIT-SIPI-SIPI to reset APsJeff Fan
If BSP found APs timeout happened when AP executing AP task, BSP will reset APs by WakeUpAP(). However, if ApLoopMode is ApMwaitLoop or ApRunLoop, WakeUpAp() will try to write semaphore in memory to wake up AP. It cannot wake up APs actually if APs still executing AP task. This fix is to set ApInitReconfig flag to force BSP to send INIT-SIPI-SIPI to wake up APs. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-11-16UefiCpuPkg/MpInitLib: Fixed offset error on Cr3LocationJeff Fan
Cr3Location offset value should be 0x34 not 0x3C. Cc: Feng Tian <feng.tian@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-11-16UefiCpuPkg/PiSmmCpuDxeSmm: Free SmramRanges to save SMM spaceJeff Fan
Cc: Zeng Star <star.zeng@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Zeng Star <star.zeng@intel.com>
2016-11-15UefiCpuPkg/PiSmmCpuDxeSmm: Decrease mNumberToFinish in AP safe codeJeff Fan
We will put APs into hlt-loop in safe code. But we decrease mNumberToFinish before APs enter into the safe code. Paolo pointed out this gap. This patch is to move mNumberToFinish decreasing to the safe code. It could make sure BSP could wait for all APs are running in safe code. https://bugzilla.tianocore.org/show_bug.cgi?id=216 Reported-by: Paolo Bonzini <pbonzini@redhat.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
2016-11-15UefiCpuPkg/PiSmmCpuDxeSmm: Place AP to 32bit protected mode on S3 pathJeff Fan
On S3 path, we may transfer to long mode (if DXE is long mode) to restore CPU contexts with CR3 = SmmS3Cr3 (in SMM). AP will execute hlt-loop after CPU contexts restoration. Once one NMI or SMI happens, APs may exit from hlt state and execute the instruction after HLT instruction. If APs are running on long mode, page table is required to fetch the instruction. However, CR3 pointer to page table in SMM. APs will crash. This fix is to disable long mode on APs and transfer to 32bit protected mode to execute hlt-loop. Then CR3 and page table will no longer be required. https://bugzilla.tianocore.org/show_bug.cgi?id=216 Reported-by: Laszlo Ersek <lersek@redhat.com> Analyzed-by: Paolo Bonzini <pbonzini@redhat.com> Analyzed-by: Laszlo Ersek <lersek@redhat.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
2016-11-15UefiCpuPkg/PiSmmCpuDxeSmm: Put AP into safe hlt-loop code on S3 pathJeff Fan
On S3 path, we will wake up APs to restore CPU context in PiSmmCpuDxeSmm driver. However, we place AP in hlt-loop under 1MB space borrowed after CPU restoring CPU contexts. In case, one NMI or SMI happens, APs may exit from hlt state and execute the instruction after HLT instruction. But the code under 1MB is no longer safe at that time. This fix is to allocate one ACPI NVS range to place the AP hlt-loop code. When CPU finished restoration CPU contexts, AP will execute in this ACPI NVS range. https://bugzilla.tianocore.org/show_bug.cgi?id=216 v2: 1. Make stack alignment per Laszlo's comment. 2. Trim whitespace at end of end. 3. Update year mark in file header. Reported-by: Laszlo Ersek <lersek@redhat.com> Analyzed-by: Paolo Bonzini <pbonzini@redhat.com> Analyzed-by: Laszlo Ersek <lersek@redhat.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
2016-11-14UefiCpuPkg/DxeMpLib: Place APs to suitable state on Legacy OS bootJeff Fan
Currently, DxeMpLib only places APs into specified c-state in Exit Boot Service callback function for UEFI OS boot. We need to put APs into specified c-state for legacy OS boot also. https://bugzilla.tianocore.org/show_bug.cgi?id=210 Cc: Laszlo Ersek <lersek@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-11-14UefiCpuPkg/DxeMpLib: Rename MpInitExitBootServicesCallback()Jeff Fan
Rename MpInitExitBootServicesCallback() to MpInitChangeApLoopCallback() because it will not only be invoked on Exit Boot Service Event, but also will be invoked on Legacy Ready To Boot Event. https://bugzilla.tianocore.org/show_bug.cgi?id=210 Cc: Laszlo Ersek <lersek@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-11-11UefiCpuPkg/DxeMpLib: Allocate below 4GB mem for AsmRelocateApLoopFuncJeff Fan
Current implementation just allocates reserve memory for AsmRelocateApLoopFunc. It not be safe because APs will be placed into 32bit protected mode on long mode DXE. This reserve memory must be located below 4GB memory. This fix is to allocate < 4GB memory for AsmRelocateApLoopFunc. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com> [lersek@redhat.com: strip whitespace at EOL] Signed-off-by: Laszlo Ersek <lersek@redhat.com>
2016-11-09UefiCpuPkg/MpInitLib: Do not wakeup AP if only one processor supportedJeff Fan
If MaxLogicalProcessorNumber is only 1, we needn't to wake up APs at all and needn't to register callback functions. It could improve boot performance on single supported system. https://bugzilla.tianocore.org/show_bug.cgi?id=204 Cc: Feng Tian <feng.tian@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-11-09UefiCpuPkg: Display new stack base and sizeJeff Fan
Dump new stack base and size information could help developer to narrow down stack crash issue. Cc: Feng Tian <feng.tian@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-11-08UefiCpuPkg/MicrocodeUpdate: Add Microcode FMP build sampleJiewen Yao
This folder provides the sample build for Microcode FMP. The DSC/FDF is to convert the Microcode binary/text to Microcode FMP. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Chao Zhang <chao.b.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-11-08UefiCpuPkg/MicrocodeUpdate: Add MicrocodeUpdate component.Jiewen Yao
MicrocodeUpdate supports update Microcode region via UEFI FMP capsule. MicrocodeUpdate SetImage() will perform the Microcode version, ProcessorSignature/ProcessorFlag, and try to load microcode. If and only if the Microcode is loaded successfully, and new Microcode will be updated to system flash region. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Chao Zhang <chao.b.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-11-08UefiCpuPkg/MicrocodeFlashAccessLib: Add NULL MicrocodeFlashAccessLib.Jiewen Yao
Add NULL instance to pass build. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Chao Zhang <chao.b.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-11-08UefiCpuPkg/UefiCpuPkg.dec: Add Microcode capsule related definition.Jiewen Yao
1) Add Microcode capsule related GUID. gMicrocodeFmpImageTypeIdGuid 2) Add Microcode capsule related library. MicrocodeFlashAccessLib Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Chao Zhang <chao.b.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-11-08UefiCpuPkg/Include: Add MicrocodeFlashAccessLib header.Jiewen Yao
This library is used to abstract microcode flash region access. This library is consumed by a microcode capsule update module. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Chao Zhang <chao.b.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-11-08UefiCpuPkg/Include: Add Microcode FMP definition.Jiewen Yao
It defined ImageTypeId for Microcode. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Chao Zhang <chao.b.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-11-08UefiCpuPkg/UefiCpuPkg.dsc: Add MicrocodeCapsule related component.Jiewen Yao
Add Microcode capsule related component to check build. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Chao Zhang <chao.b.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-11-03UefiCpuPkg PeiCpuExceptionHandlerLib: Add the missing nasm files in INFLiming Gao
All CpuExceptionHandlerLib library instances use nasm source files. Cc: Reviewed-by: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-11-02UefiCpuPkg/LocalApicLib: Add EFIAPI for GetProcessorLocationByApicId()Jeff Fan
We need to add EFIAPI for all interface service including library API. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Leo Duran <leo.duran@amd.com> Cc: Michael Kinney <Michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <Michael.d.kinney@intel.com> Reviewed-by: Leo Duran <leo.duran@amd.com>
2016-11-02UefiCpuPkg/LocalApicLib: Rename GetProcessorLocation()Jeff Fan
GetProcessorLocation() is too generic and will conflict with the API defined in Galileo Board Software Package v1.0.0. This update is just to rename GetProcessorLocation() to one specific name GetProcessorLocationByApicId(). Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Leo Duran <leo.duran@amd.com> Cc: Michael Kinney <Michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <Michael.d.kinney@intel.com> Reviewed-by: Leo Duran <leo.duran@amd.com>
2016-11-01UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib libraryLeo Duran
1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver. 2) Remove ExtractProcessorLocation() from MpInitLib library. 3) Add GetProcessorLocation() to BaseXApicLib and BaseXApicX2ApicLib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> Signed-off-by: Michael Kinney <Michael.d.kinney@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael Kinney <Michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-10-24UefiCpuPkg: Fix typos in commentsGary Lin
- excute -> execute - Retrive -> Retrieve - possilbe -> possible - CONTINOUS -> CONTINUOUS - storgage -> storage - allcated -> allocated - triggerred -> triggered - paramter -> parameter - perodically -> periodically - retore -> restore v2: - ruturn -> return Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gary Lin <glin@suse.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-10-18UefiCpuPkg/Cpuid: Remove wrong while-loop check after for-loopJeff Fan
while-loop check should not co-exist with for-loop. This should be typo when we check-in the original code. We should keep one loop only. This issue caused CLANG38 build failure reported by https://tianocore.acgmultimedia.com/show_bug.cgi?id=148 Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Liming Gao <liming.gao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-09-21UefiCpuPkg/SecCore: SecPlatformInformation(2) are optional PPIsJeff Fan
Currently, this is ASSERT() if neither SecPlatformInformation2 nor SecPlatformInformation PPIs are found. This is not correct. Per PI specification both of them are optional PPI. Platform may not install them. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-09-21UefiCpuPkg/SecCore: Fix comment typoJeff Fan
Revert SecPlatformInformation2 and SecPlatformInformation in two comment blocks. And correct the words. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-09-14UefiCpuPkg/SecCore: Re-install SEC platform information(2) PPIJeff Fan
In SecTemporaryRamDone(), we will build one privated GUIDed-HOB to save CPU BIST Data and re-install SEC platform information(2) PPI. Then other PEI drivers could get CPU BIST data from the private GUIDed-HOB by new installed PPI. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-14UefiCpuPkg/SecCore: Abstract worker function GetBistFromHob()Jeff Fan
Abstract one worker function to get CPU BIST from the GUIDed-HOB. Add SecPlatformInformationBist() and SecPlatformInformation2Bist() to invoke GetBistFromHob(). Add in/out for parameter in function header. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-14UefiCpuPkg/SecCore: Add SecBist.cJeff Fan
Add SecBist.c and copy GetBistInfoFromPpi() and SecPlatformInformation2() from UefiCpuPkg/CpuMpPei/CpuBist.c. And update SecMain.c, SecMain.inf and UefiCpuPkg.dsc accordinlgy to pass build. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-14UefiCpuPkg/CpuMpPei: Build GUIDed-HOB to store all CPU BIST DataJeff Fan
Build gEfiSecPlatformInformation2PpiGuid GUIDed-HOB to store all CPU BIST data that could be used not only by SecPlatformInformation2(), but also by CPU MP Dxe driver to get CPU BIST data. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-14UefiCpuPkg/CpuMpPei: Fix BistData ouput errorJeff Fan
ProcessorInfo.ProcessorId is UINT64 type even it's valid value is UINT32. Use %x only output the low 4 bytes and keep the high 4 bytes in stack that will be output as the second parameter BistData. Typecast ProcessorInfo.ProcessorId to UINT32 could make BistData output correctly. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-14UefiCpuPkg/CpuMpPei: Add parameter BistInformationSizeJeff Fan
Add one OPTIONAL parameter BistInformationSize for GetBistInfoFromPpi(). Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-14UefiCpuPkg/CpuDxe: Fix duplicated status code reportJeff Fan
If CPU Bist data is not zero, we will report Status code. But there is one bug that will report each processor's status code duplicated with NumberOfData times. This fix is to exchange the loop order on NumberOfData and mNumberOfProcessors. It could make sure the report status code only once for each processor. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-08UefiCpuPkg/XeonPhiMsr.h: add MSR reference from SDM in commentJeff Fan
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08UefiCpuPkg/XeonE7Msr.h: add MSR reference from SDM in commentJeff Fan
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08UefiCpuPkg/XeonDMsr.h: add MSR reference from SDM in commentJeff Fan
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08UefiCpuPkg/Xeon5600Msr.h: add MSR reference from SDM in commentJeff Fan
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08UefiCpuPkg/SkylakeMsr.h: add MSR reference from SDM in commentJeff Fan
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08UefiCpuPkg/SilvermontMsr.h: add MSR reference from SDM in commentJeff Fan
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08UefiCpuPkg/SandyBridgeMsr.h: add MSR reference from SDM in commentJeff Fan
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08UefiCpuPkg/PentiumMsr.h: add MSR reference from SDM in commentJeff Fan
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08UefiCpuPkg/PentiumMMsr.h: add MSR reference from SDM in commentJeff Fan
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08UefiCpuPkg/Pentium4Msr.h: add MSR reference from SDM in commentJeff Fan
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08UefiCpuPkg/P6Msr.h: add MSR reference from SDM in commentJeff Fan
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08UefiCpuPkg/NehalemMsr.h: add MSR reference from SDM in commentJeff Fan
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08UefiCpuPkg/IvyBridgeMsr.h: add MSR reference from SDM in commentJeff Fan
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-08 04:36:29 +0000