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2016-02-25UefiCpuPkg/CpuS3DataDxe: Add more detailed description on GUID in INFJeff Fan
Add the GUID gEfiEndOfDxeEventGroupGuid usage description in more details in INF file. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19100 6f19259b-4bc3-4df7-8a09-765794883524 (cherry picked from commit 69206a0664cc5a67766ed7cf91c85cfcb45c18b5)
2016-02-25UefiCpuPkg/PiSmmCpu: Always set WP in CR0Yao, Jiewen
So that we can use write-protection for code later. It is REPOST. It includes suggestion from Michael Kinney <michael.d.kinney@intel.com>: - "For IA32 assembly, can we combine into a single OR instruction that sets both page enable and WP?" - "For X64, does it make sense to use single OR instruction instead of 2 BTS instructions as well?" Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> Suggested-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Cc: "Fan, Jeff" <jeff.fan@intel.com> Cc: "Kinney, Michael D" <michael.d.kinney@intel.com> Cc: "Laszlo Ersek" <lersek@redhat.com> Cc: "Paolo Bonzini" <pbonzini@redhat.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19068 6f19259b-4bc3-4df7-8a09-765794883524 (cherry picked from commit 53ba3fb8aaf91df4a65244480deb6fa60968c146)
2016-02-25UefiCpuPkg/PiSmmCpu: Always set RW+P bit for page table by defaultYao, Jiewen
So that we can use write-protection for code later. This is REPOST. It includes the bug fix from "Paolo Bonzini" <pbonzini@redhat.com>: Title: fix generation of 32-bit PAE page tables "Bits 1 and 2 are reserved in 32-bit PAE Page Directory Pointer Table Entries (PDPTEs); see Table 4-8 in the SDM. With VMX extended page tables, the processor notices and fails the VM entry as soon as CR0.PG is set to 1." And thanks "Laszlo Ersek" <lersek@redhat.com> to validate the fix. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> Signed-off-by: "Paolo Bonzini" <pbonzini@redhat.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Cc: "Fan, Jeff" <jeff.fan@intel.com> Cc: "Kinney, Michael D" <michael.d.kinney@intel.com> Cc: "Laszlo Ersek" <lersek@redhat.com> Cc: "Paolo Bonzini" <pbonzini@redhat.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19067 6f19259b-4bc3-4df7-8a09-765794883524 (cherry picked from commit 881520ea6778953c57d975ca2a9cf3f2114f99c4)
2016-02-25UefiCpuPkg/PiSmmCpu: Update function call for 2 new APIs.Yao, Jiewen
All page table allocation will use AllocatePageTableMemory(). Add SmmCpuFeaturesCompleteSmmReadyToLock() to PerformRemainingTasks() and PerformPreTasks(). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> Reviewed-by: "Kinney, Michael D" <michael.d.kinney@intel.com> Cc: "Fan, Jeff" <jeff.fan@intel.com> Cc: "Kinney, Michael D" <michael.d.kinney@intel.com> Cc: "Laszlo Ersek" <lersek@redhat.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18981 6f19259b-4bc3-4df7-8a09-765794883524 (cherry picked from commit 21c1719318056691a3e5901c6e28e5ba2b70afe2)
2016-02-25UefiCpuPkg/PiSmmCpu: Add NULL func for 2 new APIs in SmmCpuFeaturesLib.Yao, Jiewen
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> Reviewed-by: "Kinney, Michael D" <michael.d.kinney@intel.com> Cc: "Fan, Jeff" <jeff.fan@intel.com> Cc: "Kinney, Michael D" <michael.d.kinney@intel.com> Cc: "Laszlo Ersek" <lersek@redhat.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18980 6f19259b-4bc3-4df7-8a09-765794883524 (cherry picked from commit b095a5403b1dd2ad7af153069f3729716a864e80)
2016-02-25UefiCpuPkg/PiSmmCpu: Add 2 APIs in SmmCpuFeaturesLib.Yao, Jiewen
SmmCpuFeaturesCompleteSmmReadyToLock() is a hook point to allow CPU specific code to do more registers setting after the gEfiSmmReadyToLockProtocolGuid notification is completely processed. SmmCpuFeaturesAllocatePageTableMemory() is an API to allow CPU to allocate a specific region for storing page tables. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> Reviewed-by: "Kinney, Michael D" <michael.d.kinney@intel.com> Cc: "Fan, Jeff" <jeff.fan@intel.com> Cc: "Kinney, Michael D" <michael.d.kinney@intel.com> Cc: "Laszlo Ersek" <lersek@redhat.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18979 6f19259b-4bc3-4df7-8a09-765794883524 (cherry picked from commit e3840072cd932fc1c9fc48510866534297a58dd2)
2016-02-24Allocate Tile size based on Page.Yao, Jiewen
We had better separate code from data in tile in page level, so that other program may use page level protection on that. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> Reviewed-by: "Kinney, Michael D" <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18957 6f19259b-4bc3-4df7-8a09-765794883524 (cherry picked from commit ae82a30bee2c8a4630389699391ce02a63e9a464)
2016-02-24UefiCpuPkg/CpuS3DataDxe: Add module to initialize ACPI_CPU_DATA for S3Michael Kinney
This module initializes the ACPI_CPU_DATA structure and registers the address of this structure in the PcdCpuS3DataAddress PCD. This is a generic/simple version of this module. It does not provide a machine check handler or CPU register initialization tables for ACPI S3 resume. It also only supports the number of CPUs reported by the MP Services Protocol, so this module does not support hot plug CPUs. This module can be copied into a CPU specific package and customized if these additional features are required. This patch series is in response to the OvmfPkg patch series from Laszlo Ersek that enables SMM on OVMF. The v4 version of the patch series from Laszlo includes an OVMF specific CPU module to initialize the ACPI_CPU_DATA structure. This proposed patch series replaces the patches listed below. [PATCH v4 27/41] OvmfPkg: add skeleton QuarkPort/CpuS3DataDxe [PATCH v4 28/41] OvmfPkg: QuarkPort/CpuS3DataDxe: fill in ACPI_CPU_DATA.StartupVector [PATCH v4 29/41] OvmfPkg: QuarkPort/CpuS3DataDxe: handle IDT, GDT and MCE in ACPI_CPU_DATA [PATCH v4 30/41] OvmfPkg: QuarkPort/CpuS3DataDxe: handle StackAddress and StackSize [PATCH v4 31/41] OvmfPkg: import CpuConfigLib header from Quark_EDKII_v1.1.0/IA32FamilyCpuBasePkg [PATCH v4 32/41] OvmfPkg: QuarkPort/CpuS3DataDxe: fill in ACPI_CPU_DATA.NumberOfCpus [PATCH v4 33/41] OvmfPkg: QuarkPort/CpuS3DataDxe: fill in ACPI_CPU_DATA.MtrrTable [PATCH v4 34/41] OvmfPkg: QuarkPort/CpuS3DataDxe: handle register tables in ACPI_CPU_DATA [PATCH v4 35/41] OvmfPkg: port CpuS3DataDxe to X64 patch originally authored by Paolo Bonzini [PATCH v4 36/41] OvmfPkg: build QuarkPort/CpuS3DataDxe for -D SMM_REQUIRE Cc: Laszlo Ersek <lersek@redhat.com> Cc: "Yao, Jiewen" <jiewen.yao@intel.com> Cc: "Fan, Jeff" <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18951 6f19259b-4bc3-4df7-8a09-765794883524 (cherry picked from commit bfec5efa56cae21ea8a1bb52cd7701749d43d70a)
2016-02-24UefiCpuPkg/Include: Expand description of AcpiCpuData.h structuresMichael Kinney
Provide a more detailed description of each field of the ACPI_CPU_DATA and CPU_REGISTER_TABLE structures. Cc: Laszlo Ersek <lersek@redhat.com> Cc: "Yao, Jiewen" <jiewen.yao@intel.com> Cc: "Fan, Jeff" <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18950 6f19259b-4bc3-4df7-8a09-765794883524 (cherry picked from commit af381fda9b63f548a1b9f71bac3d4721f1fd8db4)
2016-02-24Move SmmDebug feature from ASM to C.Yao, Jiewen
SmmDebug feature is implemented in ASM, which is not easy to maintain. So we move it to C function. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> Reviewed-by: "Kinney, Michael D" <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18946 6f19259b-4bc3-4df7-8a09-765794883524 (cherry picked from commit f45f2d4ad4d803eb33c608bca8242992f1841fec)
2016-02-24Move RestoreSmmConfigurationInS3 function to PerformPreTasks().Yao, Jiewen
In this way, we can centralize the silicon configuration in PerformRemainingTasks()/PerformPreTasks() function. If there are more features need to be configured, they can put in PerformRemainingTasks()/PerformPreTasks() only. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> Reviewed-by: "Kinney, Michael D" <michael.d.kinney@intel.com> Reviewed-by: "Laszlo Ersek" <lersek@redhat.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18938 6f19259b-4bc3-4df7-8a09-765794883524 (cherry picked from commit 9f419739d1ae849e0c4d75a131502f9367ca4a7d)
2016-02-24Eliminate EFI_IMAGE_MACHINE_TYPE_SUPPORTED.Yao, Jiewen
Move Gdt initialization from InitializeMpServiceData() to CPU Arch specific function. We create SmmFuncsArch.c for hold CPU specific function, so that EFI_IMAGE_MACHINE_TYPE_SUPPORTED(EFI_IMAGE_MACHINE_X64) can be removed. For IA32 version, we always allocate new page for GDT entry, for easy maintenance. For X64 version, we fixed TssBase in GDT entry to make sure TSS data is correct. Remove TSS fixup for GDT in ASM file. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> Reviewed-by: "Fan, Jeff" <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18937 6f19259b-4bc3-4df7-8a09-765794883524 (cherry picked from commit fe5f19494353421d3382f32f31a627e09724bbb2)
2016-02-24Correct TSS segment.Yao, Jiewen
TSS segment should use (SIZE - 1) as limit, and do not set G bit (highest bit of LimitHigh) because limit means byte count. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> Reviewed-by: "Fan, Jeff" <jeff.fan@intel.com> Reviewed-by: "Kinney, Michael D" <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18935 6f19259b-4bc3-4df7-8a09-765794883524 (cherry picked from commit 20ab326972339d16d7e95d94f9d7710cae1ae75f)
2016-02-24UefiCpuPkg/CpuDxe: Don't use gBS->StallJordan Justen
The CpuDxe driver may run before the gEfiMetronomeArchProtocolGuid protocol is installed. gBS->Stall does not work until this arch protocol is installed. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18914 6f19259b-4bc3-4df7-8a09-765794883524 (cherry picked from commit f73dd6f5bb31aed6097bcb4991fc04b542fc3911)
2016-02-24UefiCpuPkg BaseXApic(X2)Lib: Add ASSERT if local APIC not software enabledHao Wu
Add an ASSERT in GetApicTimerState() to check if the local APIC is software enabled. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18595 6f19259b-4bc3-4df7-8a09-765794883524 (cherry picked from commit 6d72ff7d9daf7efae5243e9c00a281b350fc0f95)
2016-02-24UefiCpuPkg: Add ASSERT to handle local APIC not config properlyHao Wu
When the local APIC is not configurated properly, function GetApicTimerInitCount() in LocalApicLib may return zero, which will lead to a divide by zero exception in SecPeiDxeTimerLibUefiCpu. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18594 6f19259b-4bc3-4df7-8a09-765794883524 (cherry picked from commit f17e2f8c9e1a34c3707f93ca373a79f14927f7b1)
2015-12-24UefiCpuPkg/PiSmmCpuDxeSmm: Correct CPUID leaf used to detect SMM modeMichael Kinney
Use Bit 29 of CPUID leaf CPUID_EXTENDED_CPU_SIG (0x80000001) to determine the SMM save state mode. The previous version of this code used CPUID leaf CPUID_VERSION_INFO (0x00000001). (Sync patch r19503 from main trunk.) Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19505 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-18UefiCpuPkg/CpuMpPei: Remove un-used AsmCliHltLoop()Jeff Fan
(Sync patch r19347 from main trunk.) Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19364 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-18UefiCpuPkg/CpuMpPei: Wake up APs by proper methodJeff Fan
If ApLoopMode is ApInHltLoop, BSP will send INIT-SIPI-SIPI to wake up APs. If ApLoopMode is ApInMwaitLoop or ApInRunLoop, BSP will write one semaphore to wake up APs. (Sync patch r19346 from main trunk.) Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19363 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-18UefiCpuPkg/CpuMpPei: Place APs in proper loop mode after AP executionJeff Fan
After AP function is executed, we will place AP in proper loop mode. Because AP maybe waken up by SMI or other reasons. We need to read signature in monitor buffer to check if APs is waken up by BSP. If it is not waken up by BSP, we will continue to place them into proper loop mode. (Sync patch r19345 from main trunk.) Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19362 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-18UefiCpuPkg/CpuMpPei: Prepare for monitor bufferJeff Fan
Get AP loop mode to prepare for the monitor buffer required for ApInMwaitLoop and ApInRunLoop. (Sync patch r19344 from main trunk.) Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19361 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-18UefiCpuPkg/CpuMpPei: Add GetApLoopMode() to get AP loop modeJeff Fan
Add GetApLoopMode() that will get PCD PcdCpuApLoopMode firstly. If it is ApInMwaitLoop, we will check if MONITOR/MWAIT feature supported by CPUID. If MONITOR/MWAIT feature is not supported, force AP loop mode to ApInHltLoop. GetApLoopMode() also return the largest line size required. (Sync patch r19343 from main trunk.) Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19360 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-18UefiCpuPkg: Add PCD PcdCpuApTargetCstateJeff Fan
This new PCD is used to specify the AP C-state value by MWAIT instruction. More deeper C-state means more longer latency time when APs exiting from MWAIT state. Platforms need to balance the performance and power saving to find the proper C-state for APs. Also, some processor may not ready for the deepest C-state at the beginning. Platform also could choose the proper chance to place AP into the deeper C-state by set this PCD before hand-off to OS. (Sync patch r19342 from main trunk.) Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19359 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-18UefiCpuPkg: Add PCD PcdCpuApLoopModeJeff Fan
This new PCD is used to specify the AP loop mode during POST phase. The value 1 means we will place AP in the Hlt-Loop state by HLT instruction. BSP need to send INIT-SIPI-SIPI to wake up APs. The value 2 means we will place AP in the deepest C-state by MWAIT instruction. BSP need to modify the monitor buffer by MONITOR instruction to wake up APs. The value 3 means we will place AP in the Run-loop state. APs are running. BSP need to write one semaphore to wake up APs. (Sync patch r19341 from main trunk.) Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19358 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-18UefiCpuPkg/CpuMpPei: Fix pack(1) issue on x64 archJeff Fan
Packing alignment for MP_CPU_EXCHANGE_INFO should be 1. This should be typo when check-in CpuMpPei driver. IA32 arch MP_CPU_EXCHANGE_INFO is luckly pack(1). It leads CpuMpPei x64 version hung. (Sync patch r19340 from main trunk.) Contributed-under: TianoCore Contribution Agreement 1.0 Reported-by: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19357 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-11UefiCpuPkg/UefiCpuPkg.uni: Fix one typoJeff Fan
'.' should be '_'. (Sync patch r19226 from main trunk.) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Shumin Qiu <shumin.qiu@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19227 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-10UefiCpuPkg/MtrrLib:Initialize local variables before use themJeff Fan
(Sync patch r19183 from main trunk.) Cc: Shumin Qiu <shumin.qiu@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Shumin Qiu <shumin.qiu@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19211 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-10UefiCpuPkg/UefiCpuPkg.uni: Add PcdCpuNumberOfReservedVariableMtrrsJeff Fan
(Sync patch r19182 from main trunk.) Cc: Shumin Qiu <shumin.qiu@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Shumin Qiu <shumin.qiu@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19210 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-10UefiCpuPkg/MtrrLib: Add MtrrSetMemoryAttributeInMtrrSettings()Michael Kinney
Add new API MtrrSetMemoryAttributeInMtrrSettings() in MtrrLib. Platform could use this API to set MTRR setting into local MTRR settings buffer instead of MTRRs. At last, platform could use MtrrSetAllMtrrs() to set the MTRR settings into MTRRs totally. It could improve MTRRs programming performance obviously, specially when platform is going to program a set of MTRRs. (Sync patch r19162 from main trunk.) Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19206 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-10UefiCpuPkg/MtrrLib: Add MtrrDebugPrintAllMtrrsWorker()Michael Kinney
MtrrDebugPrintAllMtrrsWorker() provides the capability to dump the MTRR setting from MTRRs or the input MTRR settings buffer. (Sync patch r19161 from main trunk.) Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19205 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-10UefiCpuPkg/MtrrLib: Add worker functions to access MTRRs or variableMichael Kinney
Add worker functions that could access MTRRs or MTRR settings in input buffer. (Sync patch r19160 from main trunk.) Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19204 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-10UefiCpuPkg/MtrrLib: Print MTRR settings when set fixed/variable MTRRsMichael Kinney
(Sync patch r19159 from main trunk.) Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19203 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-10UefiCpuPkg/MtrrLib: Reduce hardware init when program variable MTRRsMichael Kinney
When MtrrSetMemoryAttribute() programs variable MTRRs, it may disable/enable cache and disable/enable MTRRs several times. This updating tries to do operation in local variable and does the hardware initialization one time only. (Sync patch r19158 from main trunk.) Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19202 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-10UefiCpuPkg/MtrrLib: Reduce hardware init when program fixed MTRRsMichael Kinney
When MtrrSetMemoryAttribute() programs fixed MTRRs, it may disable/enable cache and disable/enable MTRRs several times. This updating tries to do operation in local variable and does the hardware initialization one time only. (Sync patch r19157 from main trunk.) Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19201 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-10UefiCpuPkg/MtrrLib: Add MtrrGetMemoryAttributeInVariableMtrrWorker ()Michael Kinney
Add function to shadow the content of variable MTRRs into an internal array: VariableMtrr. And used MtrrGetMemoryAttributeInVariableMtrrWorker() in other functions. (Sync patch r19156 from main trunk.) Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19200 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-10UefiCpuPkg/MtrrLib: Make use of worker functions to get MTRRs countMichael Kinney
Try to make use of worker functions to get MTRRs count. It could avoid invoking IsMtrrSupported() for many times. (Sync patch r19155 from main trunk.) Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19199 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-10UefiCpuPkg/MtrrLib: Adjust functions orderMichael Kinney
Only adjust functions order and there is no any real functionality impact. (Sync patch r19154 from main trunk.) Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19198 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-10UefiCpuPkg/MtrrLib: Add worker functions not invoke IsMtrrSupported()Michael Kinney
Abstract some worker functions not to invoke IsMtrrSupported(). They could be used by other functions to reduce the number of invoking times on IsMtrrSupported(). (Sync patch r19153 from main trunk.) Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19197 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-10UefiCpuPkg/MtrrLib: Fix some typo and clean up code formatMichael Kinney
Fixed some typo. Removed some trailing spaces and TAB key. Clean up code format. (Sync patch r19152 from main trunk.) Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19196 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-10UefiCpuPkg/MtrrLib: Add PCD PcdCpuNumberOfReservedVariableMtrrsJeff Fan
Current MtrrLib reserves 2 variable MTRRs for some legacy OS boot (CSM boots) may require some MTRRs to be reserved for OS use. But UEFI OS boot will not use MTRRs. Per Scott's suggestion in link: http://article.gmane.org/gmane.comp.bios.edk2.devel/4099 Add one PCD PcdCpuNumberOfReservedVariableMtrrs to specify the number of variable MTRRs reserved for OS use. Setting its default value to 2 is for back-compatibility. (Sync patch r19151 from main trunk.) Cc: Scott Duplichan <scott@notabs.org> Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Suggested-by: Scott Duplichan <scott@notabs.org> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19195 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-08UefiCpuPkg/CpuMpPei: Add missing point at function headerJeff Fan
(Sync patch r19165 from main trunk.) Cc: Qiu Shumin <shumin.qiu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Qiu Shumin <shumin.qiu@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19167 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-02UefiCpuPkg/CpuMpPei: Fix typo and add some commentsJeff Fan
(Sync patch r19090 from main trunk.) Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19096 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-02UefiCpuPkg/CpuMpPei: Save/Restore CRx/DRx register for APs waking upJeff Fan
PeiStartupAllAPs()/PeiStartupThisAP() will send INIT-SIPI-SIPI to wakeup APs to execute AP function. However, some registers will be reset after APs received INIT IPI. We need to restore some registers (For example, CRx/DRx) manually after APs wakeup. (Sync patch r19089 from main trunk.) Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19095 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-02UefiCpuPkg/CpuMpPei: Sync BSP's CRx to APs when initializationJeff Fan
Save BSP's volatile register and sync CRx register to APs when AP 1st wake up. (Sync patch r19088 from main trunk.) Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19094 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-02UefiCpuPkg/CpuMpPei: Set AP state to CpuStateIdle after initializationJeff Fan
(Sync patch r19087 from main trunk.) Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19093 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-02UefiCpuPkg/CpuMpPei: Add CPU_VOLATILE_REGISTERS & worker functionsJeff Fan
Add CPU_VOLATILE_REGISTERS definitions for CRx and DRx required to be restored after APs received INIT IPI. Add worker functions SaveVolatileRegisters()/RestoreVolatileRegisters() used to save/restore CRx and DRx. It also check if Debugging Extensions supported or not. (Sync patch r19086 from main trunk.) Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19092 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-02UefiCpuPkg/CpuMpPei: Exchange whole CPU data in SortApicId()Jeff Fan
Current implementation only exchanges the APIC ID and BIST, this updating is to exchange all CPU data. (Sync patch r19085 from main trunk.) Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19091 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-25UefiCpuPkg/CpuMpPei: Enable x2APIC mode on BSP/APsJeff Fan
If x2APIC flag is set, enable x2APIC mode on all APs and BSP. Before we wakeup APs to enable x2APIC mode, we should wait all APs have finished initialization. (Sync patch r18934 from main trunk.) Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@18942 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-25UefiCpuPkg/CpuMpPei: Set X2APIC flag if one x2APIC ID larger than 254Jeff Fan
If there are any logical processor reporting an APIC ID of 255 or greater, set X2ApicEnable flag. GetInitialApicId() will return x2APIC ID if CPUID leaf B supported. (Sync patch r18933 from main trunk.) Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@18941 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-20UefiCpuPkg/SmmFeatureLib: Check SmmFeatureControl by Code_Access_ChkJeff Fan
Bit SMM_Code_Access_Chk (SMM-RO) in MSR_SMM_MCA_CAP is defined in SDM. If set to 1 indicates that the SMM code access restriction is supported and the MSR_SMM_FEATURE_CONTROL is supported. If this bit is not set, we needn't to access register SmmFetureControl. Otherwise, #GP exception may happen. We need to check if SmmFeatureControl support or not by checking SMM_Code_Access_Chk (SMM-RO) in MSR_SMM_MCA_CAP. Because MSR_SMM_MCA_CAP is SMM-RO register, we should move this check from SmmCpuFeaturesLibConstructor (non-SMM) to SmmCpuFeaturesInitializeProcessor (SMM). (Sync patch r18906 from main trunk.) Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@18913 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-08 00:08:30 +0000