From 1a434a6017ccae26a3eec032764bd06461a29ceb Mon Sep 17 00:00:00 2001 From: Jiewen Yao Date: Mon, 28 Aug 2017 09:37:58 +0800 Subject: new policy design for silicon. Cc: Michael A Kubacki Cc: Amy Chan Cc: Chasel Chiu Cc: Brett Wang Cc: Daocheng Bu Cc: Isaac W Oram Cc: Rangasai V Chaganty Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao Reviewed-by: Michael A Kubacki Reviewed-by: Amy Chan --- .../DxeSiliconPolicyInitLib/DxePolicyInit.c | 86 +++ .../DxeSiliconPolicyInitLib/DxeSaPolicyInit.h | 56 ++ .../DxeSiliconPolicyInitLib.inf | 74 +++ .../PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c | 366 ----------- .../PeiFspPolicyInitLib/PeiFspMePolicyInitLib.c | 129 ---- .../PeiFspPolicyInitLib/PeiFspMiscUpdInitLib.c | 56 -- .../PeiFspPolicyInitLib/PeiFspPchPolicyInitLib.c | 713 --------------------- .../PeiFspPolicyInitLib/PeiFspPolicyInitLib.c | 146 ----- .../PeiFspPolicyInitLib/PeiFspPolicyInitLib.h | 179 ------ .../PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf | 146 ----- .../PeiFspPolicyInitLib/PeiFspSaPolicyInitLib.c | 578 ----------------- .../PeiFspPolicyInitLib/PeiFspSiPolicyInitLib.c | 51 -- .../Library/PeiFspPolicyInitLib/PeiPolicyInit.c | 47 -- .../Library/PeiFspPolicyInitLib/PeiPolicyInit.h | 24 - .../Library/PeiFspPolicyInitLib/PeiPolicyInitLib.h | 37 -- .../PeiFspPolicyInitLib/PeiPolicyInitPreMem.c | 48 -- .../Library/PeiFspPolicyInitLib/PeiSiPolicyInit.h | 24 - .../PeiSiliconPolicyInitLib/PeiPolicyInit.c | 93 +++ .../PeiSiliconPolicyInitLib/PeiPolicyInit.h | 24 + .../PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c | 93 +++ .../PeiSiliconPolicyInitLib/PeiSiPolicyInit.h | 24 + .../PeiSiliconPolicyInitLib.inf | 61 ++ .../PeiFspCpuPolicyInitLib.c | 366 +++++++++++ .../PeiFspMePolicyInitLib.c | 129 ++++ .../PeiFspMiscUpdInitLib.c | 56 ++ .../PeiFspPchPolicyInitLib.c | 713 +++++++++++++++++++++ .../PeiFspPolicyInitLib.c | 212 ++++++ .../PeiFspPolicyInitLib.h | 179 ++++++ .../PeiFspSaPolicyInitLib.c | 578 +++++++++++++++++ .../PeiFspSiPolicyInitLib.c | 51 ++ .../PeiSiliconPolicyInitLibFsp/PeiPolicyInit.c | 47 ++ .../PeiSiliconPolicyInitLibFsp/PeiPolicyInit.h | 24 + .../PeiSiliconPolicyInitLibFsp/PeiPolicyInitLib.h | 37 ++ .../PeiPolicyInitPreMem.c | 48 ++ .../PeiSiliconPolicyInitLibFsp/PeiSiPolicyInit.h | 24 + .../PeiSiliconPolicyInitLibFsp.inf | 146 +++++ 36 files changed, 3121 insertions(+), 2544 deletions(-) create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/DxeSiliconPolicyInitLib/DxePolicyInit.c create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/DxeSiliconPolicyInitLib/DxeSaPolicyInit.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/DxeSiliconPolicyInitLib/DxeSiliconPolicyInitLib.inf delete mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c delete mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspMePolicyInitLib.c delete mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspMiscUpdInitLib.c delete mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspPchPolicyInitLib.c delete mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.c delete mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.h delete mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf delete mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspSaPolicyInitLib.c delete mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspSiPolicyInitLib.c delete mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiPolicyInit.c delete mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiPolicyInit.h delete mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiPolicyInitLib.h delete mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiPolicyInitPreMem.c delete mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiSiPolicyInit.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.c create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSiPolicyInit.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSiliconPolicyInitLib.inf create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspCpuPolicyInitLib.c create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspMePolicyInitLib.c create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspMiscUpdInitLib.c create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspPchPolicyInitLib.c create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspPolicyInitLib.c create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspPolicyInitLib.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspSaPolicyInitLib.c create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspSiPolicyInitLib.c create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiPolicyInit.c create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiPolicyInit.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiPolicyInitLib.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiPolicyInitPreMem.c create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiPolicyInit.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/DxeSiliconPolicyInitLib/DxePolicyInit.c b/Silicon/Intel/KabylakeSiliconPkg/Library/DxeSiliconPolicyInitLib/DxePolicyInit.c new file mode 100644 index 0000000000..ac870bee84 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/DxeSiliconPolicyInitLib/DxePolicyInit.c @@ -0,0 +1,86 @@ +/** @file + This file is SampleCode for Intel PEI Platform Policy initialization. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include "DxeSaPolicyInit.h" + +/** + Performs silicon late policy initialization. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a protocol, etc. + + The returned data must be used as input data for SiliconPolicyDoneLate(), + and SiliconPolicyUpdateLib.SiliconPolicyUpdateLate(). + + In FSP or non-FSP path, the input policy could be NULL. + The return data is the initialized policy. + + @param[in, out] Policy Pointer to policy. + + @return the initialized policy. +**/ +VOID * +EFIAPI +SiliconPolicyInitLate ( + IN OUT VOID *Policy + ) +{ + EFI_STATUS Status; + SA_POLICY_PROTOCOL *SaPolicy; + + ASSERT (Policy == NULL); + + // + // Call CreateSaDxeConfigBlocks to create & initialize platform policy structure + // and get all Intel default policy settings. + // + Status = CreateSaDxeConfigBlocks(&SaPolicy); + DEBUG((DEBUG_INFO, "SaPolicy->TableHeader.NumberOfBlocks = 0x%x\n ", SaPolicy->TableHeader.NumberOfBlocks)); + ASSERT_EFI_ERROR(Status); + + return SaPolicy; +} + +/* + The silicon late policy is finalized. + Silicon code can do initialization based upon the policy data. + + The input Policy must be returned by SiliconPolicyInitLate(). + + @param[in] Policy Pointer to policy. + + @retval EFI_SUCCESS The policy is handled consumed by silicon code. +*/ +EFI_STATUS +EFIAPI +SiliconPolicyDoneLate ( + IN VOID *Policy + ) +{ + EFI_STATUS Status; + SA_POLICY_PROTOCOL *SaPolicy; + + SaPolicy = Policy; + + // + // Install SaInstallPolicyProtocol. + // While installed, RC assumes the Policy is ready and finalized. So please + // update and override any setting before calling this function. + // + Status = SaInstallPolicyProtocol (gImageHandle, SaPolicy); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/DxeSiliconPolicyInitLib/DxeSaPolicyInit.h b/Silicon/Intel/KabylakeSiliconPkg/Library/DxeSiliconPolicyInitLib/DxeSaPolicyInit.h new file mode 100644 index 0000000000..ebc5023f7b --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/DxeSiliconPolicyInitLib/DxeSaPolicyInit.h @@ -0,0 +1,56 @@ +/** @file + Header file for the SaPolicyInitDxe Driver. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _SA_POLICY_INIT_DXE_H_ +#define _SA_POLICY_INIT_DXE_H_ + +#include +#include +#include +#include +#include +#include + +#include + + +/** + SA DXE Policy Driver Entry Point \n + - Introduction \n + System Agent DXE drivers behavior can be controlled by platform policy without modifying reference code directly. + Platform policy Protocol is initialized with default settings in this funciton. + This policy Protocol has to be initialized prior to System Agent initialization DXE drivers execution. + + - @pre + - Runtime variable service should be ready if policy initialization required. + + - @result + SA_POLICY_PROTOCOL will be installed successfully and ready for System Agent reference code use. + + - Porting Recommendations \n + Policy should be initialized basing on platform design or user selection (like BIOS Setup Menu) + + @param[in] ImageHandle - Image handle of this driver. + + @retval EFI_SUCCESS Initialization complete. + @exception EFI_UNSUPPORTED The chipset is unsupported by this driver. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver. + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. +**/ +EFI_STATUS +EFIAPI +SaPolicyInitDxe ( + IN EFI_HANDLE ImageHandle + ); + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/DxeSiliconPolicyInitLib/DxeSiliconPolicyInitLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/DxeSiliconPolicyInitLib/DxeSiliconPolicyInitLib.inf new file mode 100644 index 0000000000..fbce84e78f --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/DxeSiliconPolicyInitLib/DxeSiliconPolicyInitLib.inf @@ -0,0 +1,74 @@ +### @file +# Library functions for Fsp Policy Initialization Library. +# +# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = DxeSiliconPolicyInitLib + FILE_GUID = 80920B16-7778-4793-878E-4555F68BDC69 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = SiliconPolicyInitLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 +# + +################################################################################ +# +# Sources Section - list of files that are required for the build to succeed. +# +################################################################################ + +[Sources] + DxePolicyInit.c + +################################################################################ +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +################################################################################ + +[Packages] + MdePkg/MdePkg.dec + KabylakeSiliconPkg/SiPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + IoLib + MemoryAllocationLib + DxeSaPolicyLib + MmPciLib + PcdLib + UefiBootServicesTableLib + ConfigBlockLib + +[Protocols] + gSaPolicyProtocolGuid ## CONSUMES + +[Guids] + gMiscDxeConfigGuid + + diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c deleted file mode 100644 index 282f774831..0000000000 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c +++ /dev/null @@ -1,366 +0,0 @@ -/** @file - Implementation of Fsp PCH Policy Initialization. - -Copyright (c) 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include - -#include - -#include -#include -#include -#include -#include -#include -#include - -/** - Performs FSP CPU PEI Policy initialization. - - @param[in][out] FspmUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspCpuPolicyInitPreMem ( - IN OUT FSPM_UPD *FspmUpd - ) -{ - EFI_STATUS Status; - SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; - CPU_OVERCLOCKING_PREMEM_CONFIG *CpuOverClockingPreMemConfig; - CPU_CONFIG_LIB_PREMEM_CONFIG *CpuConfigLibPreMemConfig; - DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SiCpuPolicy Pre-Mem Start\n")); - - // - // Locate SiPreMemPolicyPpi - // - SiPreMemPolicyPpi = NULL; - Status = PeiServicesLocatePpi ( - &gSiPreMemPolicyPpiGuid, - 0, - NULL, - (VOID **) &SiPreMemPolicyPpi - ); - if (EFI_ERROR (Status)) { - return EFI_NOT_FOUND; - } - - Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuOverclockingPreMemConfigGuid, (VOID *) &CpuOverClockingPreMemConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuConfigLibPreMemConfigGuid, (VOID *) &CpuConfigLibPreMemConfig); - ASSERT_EFI_ERROR (Status); - /// - ///Test RC Policies - /// - - /// - /// - DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SiCpuPolicy Pre-Mem End\n")); - - // - // Overclocking PreMem policies - // - FspmUpd->FspmConfig.OcSupport = (UINT8) CpuOverClockingPreMemConfig->OcSupport; - FspmUpd->FspmConfig.OcLock = (UINT8) CpuOverClockingPreMemConfig->OcLock; - FspmUpd->FspmConfig.CoreMaxOcRatio = (UINT8) CpuOverClockingPreMemConfig->CoreMaxOcRatio; - FspmUpd->FspmConfig.CoreVoltageMode = (UINT8) CpuOverClockingPreMemConfig->CoreVoltageMode; - FspmUpd->FspmConfig.RingMinOcRatio = (UINT8) CpuOverClockingPreMemConfig->RingMinOcRatio; - FspmUpd->FspmConfig.RingMaxOcRatio = (UINT8) CpuOverClockingPreMemConfig->RingMaxOcRatio; - FspmUpd->FspmConfig.CoreVoltageOverride = (UINT16) CpuOverClockingPreMemConfig->CoreVoltageOverride; - FspmUpd->FspmConfig.CoreVoltageAdaptive = (UINT16) CpuOverClockingPreMemConfig->CoreVoltageAdaptive; - FspmUpd->FspmConfig.CoreVoltageOffset = (UINT16) CpuOverClockingPreMemConfig->CoreVoltageOffset; - FspmUpd->FspmConfig.CorePllVoltageOffset = (UINT8) CpuOverClockingPreMemConfig->CorePllVoltageOffset; - FspmUpd->FspmConfig.GtPllVoltageOffset = (UINT8) CpuOverClockingPreMemConfig->GtPllVoltageOffset; - FspmUpd->FspmConfig.RingPllVoltageOffset = (UINT8) CpuOverClockingPreMemConfig->RingPllVoltageOffset; - FspmUpd->FspmConfig.SaPllVoltageOffset = (UINT8) CpuOverClockingPreMemConfig->SaPllVoltageOffset; - FspmUpd->FspmConfig.McPllVoltageOffset = (UINT8) CpuOverClockingPreMemConfig->McPllVoltageOffset; - FspmUpd->FspmConfig.Avx2RatioOffset = (UINT8) CpuOverClockingPreMemConfig->Avx2RatioOffset; - FspmUpd->FspmConfig.BclkAdaptiveVoltage = (UINT8) CpuOverClockingPreMemConfig->BclkAdaptiveVoltage; - - // - // Cpu Config Lib policies - // - FspmUpd->FspmConfig.HyperThreading = (UINT8) CpuConfigLibPreMemConfig->HyperThreading; - FspmUpd->FspmConfig.BootFrequency = (UINT8) CpuConfigLibPreMemConfig->BootFrequency; - FspmUpd->FspmConfig.ActiveCoreCount = (UINT8) CpuConfigLibPreMemConfig->ActiveCoreCount; - FspmUpd->FspmConfig.JtagC10PowerGateDisable = (UINT8) CpuConfigLibPreMemConfig->JtagC10PowerGateDisable; - FspmUpd->FspmConfig.FClkFrequency = (UINT8) CpuConfigLibPreMemConfig->FClkFrequency; - FspmUpd->FspmConfig.BistOnReset = (UINT8) CpuConfigLibPreMemConfig->BistOnReset; - FspmUpd->FspmConfig.VmxEnable = (UINT8) CpuConfigLibPreMemConfig->VmxEnable; - FspmUpd->FspmConfig.CpuRatioOverride = (UINT8) CpuConfigLibPreMemConfig->CpuRatioOverride; - FspmUpd->FspmConfig.CpuRatio = (UINT8) CpuConfigLibPreMemConfig->CpuRatio; - FspmUpd->FspmConfig.PeciSxReset = (UINT8) CpuConfigLibPreMemConfig->PeciSxReset; - FspmUpd->FspmConfig.PeciC10Reset = (UINT8) CpuConfigLibPreMemConfig->PeciC10Reset; - - return EFI_SUCCESS; -} - -/** - This routine is used to search SMRAM and get SmramCpuData point. - - @retval SmramCpuData - The pointer of CPU information in SMRAM. - @retval NULL - Unable to find the CPU information. - **/ - -STATIC -SMRAM_CPU_DATA * -GetSmmCpuData( - VOID - ) -{ - UINT32 Address; - SMRAM_CPU_DATA *SmramCpuData; - EFI_PEI_HOB_POINTERS Hob; - EFI_STATUS Status; - UINT32 TsegBase = 0; - UINT32 TsegSize = 0; - - // - // Find TSEG Base using Fsp Resource Descriptor - // - - Status = PeiServicesGetHobList ((VOID **) &Hob.Raw); - while (!END_OF_HOB_LIST (Hob)) { - if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { - if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) - && (Hob.ResourceDescriptor->PhysicalStart >= BASE_1MB) - && (Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor->ResourceLength <= BASE_4GB) - && (CompareGuid (&Hob.ResourceDescriptor->Owner, &gFspReservedMemoryResourceHobTsegGuid))) { - - TsegBase = (UINT32)Hob.ResourceDescriptor->PhysicalStart; - TsegSize = (UINT32)Hob.ResourceDescriptor->ResourceLength; - DEBUG((DEBUG_INFO, "Found gFspReservedMemoryResourceHobTsegGuid\n")); - break; - } - } - Hob.Raw = GET_NEXT_HOB (Hob); - } - - - /// - /// Search SMRAM on page alignment for the SMMNVS signature - /// - if(TsegBase && TsegSize ){ - for (Address = (TsegBase + TsegSize - EFI_PAGE_SIZE); Address >= TsegBase; Address -= EFI_PAGE_SIZE ) { - SmramCpuData = (SMRAM_CPU_DATA *) (UINTN) Address; - if (CompareGuid(&SmramCpuData->HeaderGuid, &gSmramCpuDataHeaderGuid)) { - return SmramCpuData; - } - } - } - - DEBUG((DEBUG_WARN, "SmramCpuData not found\n")); - return NULL; -} - -/** - Performs FSP CPU PEI Policy post memory initialization. - - @param[in][out] FspsUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspCpuPolicyInit ( - IN OUT FSPS_UPD *FspsUpd - ) -{ - EFI_STATUS Status; - SI_POLICY_PPI *SiPolicyPpi; - CPU_CONFIG *CpuConfig; - CPU_POWER_MGMT_BASIC_CONFIG *CpuPowerMgmtBasicConfig; - CPU_POWER_MGMT_CUSTOM_CONFIG *CpuPowerMgmtCustomConfig; - CPU_TEST_CONFIG *CpuTestConfig; - CPU_POWER_MGMT_TEST_CONFIG *CpuPowerMgmtTestConfig; - UINTN Index; - SMRAM_CPU_DATA *SmramCpuData; - UINT32 S3BspMtrrTablePointer; - UINT32 CpuS3ResumeDataPointer; - EFI_BOOT_MODE BootMode; - - DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SiCpuPolicy\n")); - // - // Locate gSiPolicyPpiGuid - // - SiPolicyPpi = NULL; - Status = PeiServicesLocatePpi ( - &gSiPolicyPpiGuid, - 0, - NULL, - (VOID **) &SiPolicyPpi - ); - if (EFI_ERROR (Status)) { - return EFI_NOT_FOUND; - } - - Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuConfigGuid, (VOID *) &CpuConfig); - ASSERT_EFI_ERROR (Status); - - Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtBasicConfigGuid, (VOID *) &CpuPowerMgmtBasicConfig); - ASSERT_EFI_ERROR (Status); - - Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtCustomConfigGuid, (VOID *) &CpuPowerMgmtCustomConfig); - ASSERT_EFI_ERROR (Status); - - Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuTestConfigGuid, (VOID *) &CpuTestConfig); - ASSERT_EFI_ERROR (Status); - - Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtTestConfigGuid, (VOID *) &CpuPowerMgmtTestConfig); - ASSERT_EFI_ERROR (Status); - // - // Production RC Policies - // - - CopyMem ((VOID *)&(FspsUpd->FspsConfig.CpuConfig), (VOID *)&(((CPU_CONFIG_UNION *)CpuConfig)->CpuConfigFsp.Data), sizeof (UINT32)); - FspsUpd->FspsConfig.MicrocodePatchAddress = CpuConfig->MicrocodePatchAddress; - - FspsUpd->FspsConfig.TurboMode = (UINT8) CpuPowerMgmtBasicConfig->TurboMode; - - /// - ///Test RC Policies - /// - FspsUpd->FspsTestConfig.MlcStreamerPrefetcher = (UINT8) CpuTestConfig->MlcStreamerPrefetcher; - FspsUpd->FspsTestConfig.MlcSpatialPrefetcher = (UINT8) CpuTestConfig->MlcSpatialPrefetcher; - FspsUpd->FspsTestConfig.MonitorMwaitEnable = (UINT8) CpuTestConfig->MonitorMwaitEnable; - FspsUpd->FspsTestConfig.DebugInterfaceEnable = (UINT8) CpuTestConfig->DebugInterfaceEnable; - FspsUpd->FspsTestConfig.DebugInterfaceLockEnable = (UINT8) CpuTestConfig->DebugInterfaceLockEnable; - FspsUpd->FspsTestConfig.ApIdleManner = (UINT8) CpuTestConfig->ApIdleManner; - FspsUpd->FspsTestConfig.ApHandoffManner = (UINT8) CpuTestConfig->ApHandoffManner; - FspsUpd->FspsTestConfig.ProcTraceOutputScheme = (UINT8) CpuTestConfig->ProcTraceOutputScheme; - FspsUpd->FspsTestConfig.ProcTraceEnable = (UINT8) CpuTestConfig->ProcTraceEnable; - FspsUpd->FspsTestConfig.ProcTraceMemSize = (UINT8) CpuTestConfig->ProcTraceMemSize; - FspsUpd->FspsTestConfig.VoltageOptimization = (UINT8) CpuTestConfig->VoltageOptimization; - - - FspsUpd->FspsTestConfig.OneCoreRatioLimit = (UINT8) CpuPowerMgmtBasicConfig->OneCoreRatioLimit; - FspsUpd->FspsTestConfig.TwoCoreRatioLimit = (UINT8) CpuPowerMgmtBasicConfig->TwoCoreRatioLimit; - FspsUpd->FspsTestConfig.ThreeCoreRatioLimit = (UINT8) CpuPowerMgmtBasicConfig->ThreeCoreRatioLimit; - FspsUpd->FspsTestConfig.FourCoreRatioLimit = (UINT8) CpuPowerMgmtBasicConfig->FourCoreRatioLimit; - FspsUpd->FspsTestConfig.FiveCoreRatioLimit = (UINT8) CpuPowerMgmtBasicConfig->FiveCoreRatioLimit; - FspsUpd->FspsTestConfig.SixCoreRatioLimit = (UINT8) CpuPowerMgmtBasicConfig->SixCoreRatioLimit; - FspsUpd->FspsTestConfig.SevenCoreRatioLimit = (UINT8) CpuPowerMgmtBasicConfig->SevenCoreRatioLimit; - FspsUpd->FspsTestConfig.EightCoreRatioLimit = (UINT8) CpuPowerMgmtBasicConfig->EightCoreRatioLimit; - FspsUpd->FspsTestConfig.Hwp = (UINT8) CpuPowerMgmtBasicConfig->Hwp; - FspsUpd->FspsTestConfig.HdcControl = (UINT8) CpuPowerMgmtBasicConfig->HdcControl; - FspsUpd->FspsTestConfig.PowerLimit1Time = (UINT8) CpuPowerMgmtBasicConfig->PowerLimit1Time; - FspsUpd->FspsTestConfig.PowerLimit2 = (UINT8) CpuPowerMgmtBasicConfig->PowerLimit2; - FspsUpd->FspsTestConfig.TurboPowerLimitLock = (UINT8) CpuPowerMgmtBasicConfig->TurboPowerLimitLock; - FspsUpd->FspsTestConfig.PowerLimit3Time = (UINT8) CpuPowerMgmtBasicConfig->PowerLimit3Time; - FspsUpd->FspsTestConfig.PowerLimit3DutyCycle = (UINT8) CpuPowerMgmtBasicConfig->PowerLimit3DutyCycle; - FspsUpd->FspsTestConfig.PowerLimit3Lock = (UINT8) CpuPowerMgmtBasicConfig->PowerLimit3Lock; - FspsUpd->FspsTestConfig.PowerLimit4Lock = (UINT8) CpuPowerMgmtBasicConfig->PowerLimit4Lock; - FspsUpd->FspsTestConfig.TccActivationOffset = (UINT8) CpuPowerMgmtBasicConfig->TccActivationOffset; - FspsUpd->FspsTestConfig.TccOffsetClamp = (UINT8) CpuPowerMgmtBasicConfig->TccOffsetClamp; - FspsUpd->FspsTestConfig.TccOffsetLock = (UINT8) CpuPowerMgmtBasicConfig->TccOffsetLock; - FspsUpd->FspsTestConfig.PowerLimit1 = (UINT32) (CpuPowerMgmtBasicConfig->PowerLimit1 * 125); - FspsUpd->FspsTestConfig.PowerLimit2Power = (UINT32) (CpuPowerMgmtBasicConfig->PowerLimit2Power * 125); - FspsUpd->FspsTestConfig.PowerLimit3 = (UINT32) (CpuPowerMgmtBasicConfig->PowerLimit3 * 125); - FspsUpd->FspsTestConfig.PowerLimit4 = (UINT32) (CpuPowerMgmtBasicConfig->PowerLimit4 * 125); - FspsUpd->FspsTestConfig.TccOffsetTimeWindowForRatl = (UINT32) CpuPowerMgmtBasicConfig->TccOffsetTimeWindowForRatl; - - FspsUpd->FspsTestConfig.NumberOfEntries = (UINT8) CpuPowerMgmtCustomConfig->CustomRatioTable.NumberOfEntries; - FspsUpd->FspsTestConfig.Custom1PowerLimit1Time = (UINT8) CpuPowerMgmtCustomConfig->CustomConfigTdpTable[0].CustomPowerLimit1Time; - FspsUpd->FspsTestConfig.Custom2PowerLimit1Time = (UINT8) CpuPowerMgmtCustomConfig->CustomConfigTdpTable[1].CustomPowerLimit1Time; - FspsUpd->FspsTestConfig.Custom3PowerLimit1Time = (UINT8) CpuPowerMgmtCustomConfig->CustomConfigTdpTable[2].CustomPowerLimit1Time; - FspsUpd->FspsTestConfig.Custom1TurboActivationRatio = (UINT8) CpuPowerMgmtCustomConfig->CustomConfigTdpTable[0].CustomTurboActivationRatio; - FspsUpd->FspsTestConfig.Custom2TurboActivationRatio = (UINT8) CpuPowerMgmtCustomConfig->CustomConfigTdpTable[1].CustomTurboActivationRatio; - FspsUpd->FspsTestConfig.Custom3TurboActivationRatio = (UINT8) CpuPowerMgmtCustomConfig->CustomConfigTdpTable[2].CustomTurboActivationRatio; - FspsUpd->FspsTestConfig.ConfigTdpLock = (UINT8) CpuPowerMgmtCustomConfig->ConfigTdpLock; - FspsUpd->FspsTestConfig.ConfigTdpBios = (UINT8) CpuPowerMgmtCustomConfig->ConfigTdpBios; - FspsUpd->FspsTestConfig.MaxRatio = (UINT16) CpuPowerMgmtCustomConfig->CustomRatioTable.MaxRatio; - for (Index = 0; Index < CpuPowerMgmtCustomConfig->CustomRatioTable.NumberOfEntries; Index++) { - FspsUpd->FspsTestConfig.StateRatio[Index] = (UINT16) CpuPowerMgmtCustomConfig->CustomRatioTable.StateRatio[Index]; - } - FspsUpd->FspsTestConfig.Custom1PowerLimit1 = (UINT32) (CpuPowerMgmtCustomConfig->CustomConfigTdpTable[0].CustomPowerLimit1 * 125); - FspsUpd->FspsTestConfig.Custom1PowerLimit2 = (UINT32) (CpuPowerMgmtCustomConfig->CustomConfigTdpTable[0].CustomPowerLimit2 * 125); - FspsUpd->FspsTestConfig.Custom2PowerLimit1 = (UINT32) (CpuPowerMgmtCustomConfig->CustomConfigTdpTable[1].CustomPowerLimit1 * 125); - FspsUpd->FspsTestConfig.Custom2PowerLimit2 = (UINT32) (CpuPowerMgmtCustomConfig->CustomConfigTdpTable[1].CustomPowerLimit2 * 125); - FspsUpd->FspsTestConfig.Custom3PowerLimit1 = (UINT32) (CpuPowerMgmtCustomConfig->CustomConfigTdpTable[2].CustomPowerLimit1 * 125); - FspsUpd->FspsTestConfig.Custom3PowerLimit2 = (UINT32) (CpuPowerMgmtCustomConfig->CustomConfigTdpTable[2].CustomPowerLimit2 * 125); - - FspsUpd->FspsTestConfig.Eist = (UINT8) CpuPowerMgmtTestConfig->Eist; - FspsUpd->FspsTestConfig.EnergyEfficientPState = (UINT8) CpuPowerMgmtTestConfig->EnergyEfficientPState; - FspsUpd->FspsTestConfig.EnergyEfficientTurbo = (UINT8) CpuPowerMgmtTestConfig->EnergyEfficientTurbo; - FspsUpd->FspsTestConfig.TStates = (UINT8) CpuPowerMgmtTestConfig->TStates; - FspsUpd->FspsTestConfig.BiProcHot = (UINT8) CpuPowerMgmtTestConfig->BiProcHot; - FspsUpd->FspsTestConfig.DisableProcHotOut = (UINT8) CpuPowerMgmtTestConfig->DisableProcHotOut; - FspsUpd->FspsTestConfig.ProcHotResponse = (UINT8) CpuPowerMgmtTestConfig->ProcHotResponse; - FspsUpd->FspsTestConfig.DisableVrThermalAlert = (UINT8) CpuPowerMgmtTestConfig->DisableVrThermalAlert; - FspsUpd->FspsTestConfig.AutoThermalReporting = (UINT8) CpuPowerMgmtTestConfig->AutoThermalReporting; - FspsUpd->FspsTestConfig.ThermalMonitor = (UINT8) CpuPowerMgmtTestConfig->ThermalMonitor; - FspsUpd->FspsTestConfig.Cx = (UINT8) CpuPowerMgmtTestConfig->Cx; - FspsUpd->FspsTestConfig.PmgCstCfgCtrlLock = (UINT8) CpuPowerMgmtTestConfig->PmgCstCfgCtrlLock; - FspsUpd->FspsTestConfig.C1e = (UINT8) CpuPowerMgmtTestConfig->C1e; - FspsUpd->FspsTestConfig.PkgCStateDemotion = (UINT8) CpuPowerMgmtTestConfig->PkgCStateDemotion; - FspsUpd->FspsTestConfig.PkgCStateUnDemotion = (UINT8) CpuPowerMgmtTestConfig->PkgCStateUnDemotion; - FspsUpd->FspsTestConfig.CStatePreWake = (UINT8) CpuPowerMgmtTestConfig->CStatePreWake; - FspsUpd->FspsTestConfig.TimedMwait = (UINT8) CpuPowerMgmtTestConfig->TimedMwait; - FspsUpd->FspsTestConfig.CstCfgCtrIoMwaitRedirection = (UINT8) CpuPowerMgmtTestConfig->CstCfgCtrIoMwaitRedirection; - FspsUpd->FspsTestConfig.PkgCStateLimit = (UINT8) CpuPowerMgmtTestConfig->PkgCStateLimit; - FspsUpd->FspsTestConfig.CstateLatencyControl0TimeUnit = (UINT8) CpuPowerMgmtTestConfig->CstateLatencyControl0TimeUnit; - FspsUpd->FspsTestConfig.CstateLatencyControl1TimeUnit = (UINT8) CpuPowerMgmtTestConfig->CstateLatencyControl1TimeUnit; - FspsUpd->FspsTestConfig.CstateLatencyControl2TimeUnit = (UINT8) CpuPowerMgmtTestConfig->CstateLatencyControl2TimeUnit; - FspsUpd->FspsTestConfig.CstateLatencyControl3TimeUnit = (UINT8) CpuPowerMgmtTestConfig->CstateLatencyControl3TimeUnit; - FspsUpd->FspsTestConfig.CstateLatencyControl4TimeUnit = (UINT8) CpuPowerMgmtTestConfig->CstateLatencyControl4TimeUnit; - FspsUpd->FspsTestConfig.CstateLatencyControl5TimeUnit = (UINT8) CpuPowerMgmtTestConfig->CstateLatencyControl5TimeUnit; - FspsUpd->FspsTestConfig.PpmIrmSetting = (UINT8) CpuPowerMgmtTestConfig->PpmIrmSetting; - FspsUpd->FspsTestConfig.ProcHotLock = (UINT8) CpuPowerMgmtTestConfig->ProcHotLock; - FspsUpd->FspsTestConfig.RaceToHalt = (UINT8) CpuPowerMgmtTestConfig->RaceToHalt; - FspsUpd->FspsTestConfig.ConfigTdpLevel = (UINT8) CpuPowerMgmtTestConfig->ConfigTdpLevel; - FspsUpd->FspsTestConfig.CstateLatencyControl0Irtl = (UINT16) CpuPowerMgmtTestConfig->CstateLatencyControl0Irtl; - FspsUpd->FspsTestConfig.CstateLatencyControl1Irtl = (UINT16) CpuPowerMgmtTestConfig->CstateLatencyControl1Irtl; - FspsUpd->FspsTestConfig.CstateLatencyControl2Irtl = (UINT16) CpuPowerMgmtTestConfig->CstateLatencyControl2Irtl; - FspsUpd->FspsTestConfig.CstateLatencyControl3Irtl = (UINT16) CpuPowerMgmtTestConfig->CstateLatencyControl3Irtl; - FspsUpd->FspsTestConfig.CstateLatencyControl4Irtl = (UINT16) CpuPowerMgmtTestConfig->CstateLatencyControl4Irtl; - FspsUpd->FspsTestConfig.CstateLatencyControl5Irtl = (UINT16) CpuPowerMgmtTestConfig->CstateLatencyControl5Irtl; - - Status = PeiServicesGetBootMode(&BootMode); - if ((Status == EFI_SUCCESS) && (BootMode == BOOT_ON_S3_RESUME)) { - SmramCpuData = GetSmmCpuData(); - if (SmramCpuData != NULL) { - S3BspMtrrTablePointer = (UINT32) AllocateZeroPool(SmramCpuData->S3BspMtrrTableSize); //Add Null terminator - FspsUpd->FspsConfig.CpuS3ResumeMtrrData = S3BspMtrrTablePointer; - FspsUpd->FspsConfig.CpuS3ResumeMtrrDataSize = (UINT16) SmramCpuData->S3BspMtrrTableSize; - // - // Copy BSP MTRR table to UPD. - // - CopyMem((VOID*) S3BspMtrrTablePointer, - (UINT8 *) SmramCpuData + SmramCpuData->S3BspMtrrTableOffset, - SmramCpuData->S3BspMtrrTableSize); - - CpuS3ResumeDataPointer = (UINT32) AllocateZeroPool(SmramCpuData->CpuPrivateDataSize); - FspsUpd->FspsTestConfig.CpuS3ResumeData = CpuS3ResumeDataPointer; - FspsUpd->FspsTestConfig.CpuS3ResumeDataSize = (UINT16) SmramCpuData->CpuPrivateDataSize; - // - // Copy CPU_PRIVATE_DATA to UPD. - // - CopyMem((VOID*) CpuS3ResumeDataPointer, - (UINT8 *) SmramCpuData + SmramCpuData->CpuPrivateDataOffset, - SmramCpuData->CpuPrivateDataSize); - } else { - //@todo Check if an assert can be handled cleanly - DEBUG((DEBUG_WARN, "Unable to initialize S3 data\n")); - } - - } - /// - /// - return EFI_SUCCESS; -} diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspMePolicyInitLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspMePolicyInitLib.c deleted file mode 100644 index d97bf8be57..0000000000 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspMePolicyInitLib.c +++ /dev/null @@ -1,129 +0,0 @@ -/** @file - Implementation of Fsp Me Policy Initialization. - -Copyright (c) 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include - -#include - -/** - Performs FSP ME PEI Policy pre mem initialization. - - @param[in][out] FspmUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspMePolicyInitPreMem ( - IN OUT FSPM_UPD *FspmUpd - ) -{ - EFI_STATUS Status; - SI_PREMEM_POLICY_PPI *SiPreMemPolicy; - ME_PEI_PREMEM_CONFIG *MePeiPreMemConfig; - - DEBUG ((DEBUG_INFO, "PeiFspMePolicyInitPreMem\n")); - - // - // Locate gSiPreMemPolicyPpi - // - SiPreMemPolicy = NULL; - Status = PeiServicesLocatePpi ( - &gSiPreMemPolicyPpiGuid, - 0, - NULL, - (VOID **) &SiPreMemPolicy - ); - if (EFI_ERROR (Status)) { - return EFI_NOT_FOUND; - } - - Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gMePeiPreMemConfigGuid, (VOID *) &MePeiPreMemConfig); - ASSERT_EFI_ERROR (Status); - - FspmUpd->FspmConfig.HeciTimeouts = (UINT8) MePeiPreMemConfig->HeciTimeouts; - - // - // Test policies - // - FspmUpd->FspmTestConfig.DidInitStat = (UINT8) MePeiPreMemConfig->DidInitStat; - FspmUpd->FspmTestConfig.DisableCpuReplacedPolling = (UINT8) MePeiPreMemConfig->DisableCpuReplacedPolling; - FspmUpd->FspmTestConfig.SendDidMsg = (UINT8) MePeiPreMemConfig->SendDidMsg; - FspmUpd->FspmTestConfig.DisableHeciRetry = (UINT8) MePeiPreMemConfig->DisableHeciRetry; - FspmUpd->FspmTestConfig.DisableMessageCheck = (UINT8) MePeiPreMemConfig->DisableMessageCheck; - FspmUpd->FspmTestConfig.SkipMbpHob = (UINT8) MePeiPreMemConfig->SkipMbpHob; - - FspmUpd->FspmTestConfig.HeciCommunication2 = (UINT8) MePeiPreMemConfig->HeciCommunication2; - FspmUpd->FspmTestConfig.KtDeviceEnable = (UINT8) MePeiPreMemConfig->KtDeviceEnable; - FspmUpd->FspmTestConfig.IderDeviceEnable = (UINT8) MePeiPreMemConfig->IderDeviceEnable; - - - FspmUpd->FspmConfig.Heci1BarAddress = MePeiPreMemConfig->Heci1BarAddress; - FspmUpd->FspmConfig.Heci2BarAddress = MePeiPreMemConfig->Heci2BarAddress; - FspmUpd->FspmConfig.Heci3BarAddress = MePeiPreMemConfig->Heci3BarAddress; - - return EFI_SUCCESS; -} - -/** - Performs FSP ME PEI Policy initialization. - - @param[in][out] FspsUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspMePolicyInit ( - IN OUT FSPS_UPD *FspsUpd - ) -{ - EFI_STATUS Status; - SI_POLICY_PPI *SiPolicyPpi; - ME_PEI_CONFIG *MePeiConfig; - - DEBUG ((DEBUG_INFO, "PeiFspMePolicyInit \n")); - // - // Locate gSiPolicyPpiGuid - // - SiPolicyPpi = NULL; - Status = PeiServicesLocatePpi ( - &gSiPolicyPpiGuid, - 0, - NULL, - (VOID **) &SiPolicyPpi - ); - if (EFI_ERROR (Status)) { - return EFI_NOT_FOUND; - } - - Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gMePeiConfigGuid, (VOID *) &MePeiConfig); - ASSERT_EFI_ERROR (Status); - - FspsUpd->FspsConfig.Heci3Enabled = (UINT8) MePeiConfig->Heci3Enabled; - FspsUpd->FspsConfig.MeUnconfigOnRtcClear = (UINT8) MePeiConfig->MeUnconfigOnRtcClear; - FspsUpd->FspsConfig.MeUnconfigIsValid = (UINT8) MePeiConfig->MeUnconfigIsValid; - - // - // Test policies - // - FspsUpd->FspsTestConfig.EndOfPostMessage = (UINT8) MePeiConfig->EndOfPostMessage; - FspsUpd->FspsTestConfig.DisableD0I3SettingForHeci = (UINT8) MePeiConfig->DisableD0I3SettingForHeci; - - return EFI_SUCCESS; -} diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspMiscUpdInitLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspMiscUpdInitLib.c deleted file mode 100644 index b9329e4c8a..0000000000 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspMiscUpdInitLib.c +++ /dev/null @@ -1,56 +0,0 @@ -/** @file - Implementation of Fsp Misc UPD Initialization. - -Copyright (c) 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include - -#include -#include -#include -#include - -/** - Performs FSP Misc UPD initialization. - - @param[in][out] FspmUpd Pointer to FSPM_UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. -**/ -EFI_STATUS -EFIAPI -PeiFspMiscUpdInitPreMem ( - IN OUT FSPM_UPD *FspmUpd - ) -{ - EFI_STATUS Status; - - // - // Locate system configuration variable - // - FspmUpd->FspmArchUpd.StackBase = (VOID *)(UINTN)(PcdGet32(PcdTemporaryRamBase) + PcdGet32(PcdTemporaryRamSize) - (PcdGet32(PcdFspTemporaryRamSize) + PcdGet32(PcdFspReservedBufferSize))); - FspmUpd->FspmArchUpd.StackSize = PcdGet32(PcdFspTemporaryRamSize); - - Status = PeiServicesGetBootMode (&(FspmUpd->FspmArchUpd.BootMode)); - if (EFI_ERROR (Status)) { - FspmUpd->FspmArchUpd.BootMode = BOOT_WITH_FULL_CONFIGURATION; - } - - FspmUpd->FspmArchUpd.BootLoaderTolumSize = 0x0; - - // - // Initialize S3 Data variable (S3DataPtr). It may be used for warm and fast boot paths. - // - FspmUpd->FspmArchUpd.NvsBufferPtr = NULL; - - return EFI_SUCCESS; -} diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspPchPolicyInitLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspPchPolicyInitLib.c deleted file mode 100644 index 3f7e297c0b..0000000000 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspPchPolicyInitLib.c +++ /dev/null @@ -1,713 +0,0 @@ -/** @file - Implementation of Fsp PCH Policy Initialization. - -Copyright (c) 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include - -#include -#include -#include - -/** - Performs FSP PCH PEI Policy pre mem initialization. - - @param[in][out] FspmUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspPchPolicyInitPreMem ( - IN OUT FSPM_UPD *FspmUpd - ) -{ - EFI_STATUS Status; - UINTN Index; - SI_PREMEM_POLICY_PPI *SiPreMemPolicy; - PCH_TRACE_HUB_PREMEM_CONFIG *TraceHubPreMemConfig; - PCH_SMBUS_PREMEM_CONFIG *SmbusPreMemConfig; - PCH_DCI_PREMEM_CONFIG *DciPreMemConfig; - PCH_HPET_PREMEM_CONFIG *HpetPreMemConfig; - PCH_HSIO_PCIE_PREMEM_CONFIG *HsioPciePreMemConfig; - PCH_HSIO_SATA_PREMEM_CONFIG *HsioSataPreMemConfig; - PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig; - PCH_HSIO_PREMEM_CONFIG *HsioPreMemConfig; - PCH_LPC_PREMEM_CONFIG *LpcPreMemConfig; - PCH_GENERAL_PREMEM_CONFIG *PchGeneralPreMemConfig; - PCH_WDT_PREMEM_CONFIG *WdtPreMemConfig; - - DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP UpdatePeiPchPolicyPreMem\n")); - // - // Locate PchPreMemPolicyPpi - // - SiPreMemPolicy = NULL; - Status = PeiServicesLocatePpi ( - &gSiPreMemPolicyPpiGuid, - 0, - NULL, - (VOID **) &SiPreMemPolicy - ); - if (EFI_ERROR (Status)) { - return EFI_NOT_FOUND; - } - - Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gTraceHubPreMemConfigGuid, (VOID *) &TraceHubPreMemConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gSmbusPreMemConfigGuid, (VOID *) &SmbusPreMemConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gDciPreMemConfigGuid, (VOID *) &DciPreMemConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gHpetPreMemConfigGuid, (VOID *) &HpetPreMemConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gHsioPciePreMemConfigGuid, (VOID *) &HsioPciePreMemConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gHsioSataPreMemConfigGuid, (VOID *) &HsioSataPreMemConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gHsioPreMemConfigGuid, (VOID *) &HsioPreMemConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gLpcPreMemConfigGuid, (VOID *) &LpcPreMemConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gPchGeneralPreMemConfigGuid, (VOID *) &PchGeneralPreMemConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gWatchDogPreMemConfigGuid, (VOID *) &WdtPreMemConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gPcieRpPreMemConfigGuid, (VOID *) &PcieRpPreMemConfig); - ASSERT_EFI_ERROR (Status); - // - // Update PCIE RP policies - // - FspmUpd->FspmConfig.PcieRpEnableMask = PcieRpPreMemConfig->RpEnabledMask & ((1 << KBL_PCH_H_PCIE_MAX_ROOT_PORTS) - 1); - - // - // Update TraceHub policies - // - FspmUpd->FspmConfig.EnableTraceHub = ((UINT8)TraceHubPreMemConfig->EnableMode == 0) ? 0 : 1; - FspmUpd->FspmConfig.TraceHubMemReg0Size = (UINT32)TraceHubPreMemConfig->MemReg0Size; - FspmUpd->FspmConfig.TraceHubMemReg1Size = (UINT32)TraceHubPreMemConfig->MemReg1Size; - - // - // Update Smbus policies - // - FspmUpd->FspmConfig.SmbusEnable = (UINT8)SmbusPreMemConfig->Enable; - FspmUpd->FspmConfig.SmbusArpEnable = (UINT8)SmbusPreMemConfig->ArpEnable; - FspmUpd->FspmTestConfig.SmbusDynamicPowerGating = (UINT8)SmbusPreMemConfig->DynamicPowerGating; - FspmUpd->FspmTestConfig.SmbusSpdWriteDisable = (UINT8)SmbusPreMemConfig->SpdWriteDisable; - FspmUpd->FspmConfig.PchSmbusIoBase = (UINT16)SmbusPreMemConfig->SmbusIoBase; - FspmUpd->FspmConfig.PchNumRsvdSmbusAddresses = (UINT8)SmbusPreMemConfig->NumRsvdSmbusAddresses; - FspmUpd->FspmConfig.RsvdSmbusAddressTablePtr = (UINT32)SmbusPreMemConfig->RsvdSmbusAddressTable; - - // - // Update Dci policies - // - FspmUpd->FspmTestConfig.PchDciEn = (UINT8)DciPreMemConfig->DciEn; - - // - // Update HPET policies - // - FspmUpd->FspmConfig.PchHpetEnable = (UINT8)HpetPreMemConfig->Enable; - FspmUpd->FspmConfig.PchHpetBdfValid = (UINT8)HpetPreMemConfig->BdfValid; - FspmUpd->FspmConfig.PchHpetBusNumber = (UINT8)HpetPreMemConfig->BusNumber; - FspmUpd->FspmConfig.PchHpetDeviceNumber = (UINT8)HpetPreMemConfig->DeviceNumber; - FspmUpd->FspmConfig.PchHpetFunctionNumber = (UINT8)HpetPreMemConfig->FunctionNumber; - FspmUpd->FspmConfig.PchHpetBase = (UINT32)HpetPreMemConfig->Base; - - // - // Update HSIO PCIE policies - // - FspmUpd->FspmConfig.PchPmPciePllSsc = (UINT8)HsioPciePreMemConfig->PciePllSsc; - for (Index = 0; Index < KBL_PCH_H_PCIE_MAX_ROOT_PORTS; Index ++) { - FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable; - FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle; - FspmUpd->FspmConfig.PchPcieHsioTxGen1DownscaleAmpEnable[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DownscaleAmpEnable; - FspmUpd->FspmConfig.PchPcieHsioTxGen1DownscaleAmp[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DownscaleAmp; - FspmUpd->FspmConfig.PchPcieHsioTxGen2DownscaleAmpEnable[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DownscaleAmpEnable; - FspmUpd->FspmConfig.PchPcieHsioTxGen2DownscaleAmp[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DownscaleAmp; - FspmUpd->FspmConfig.PchPcieHsioTxGen3DownscaleAmpEnable[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen3DownscaleAmpEnable; - FspmUpd->FspmConfig.PchPcieHsioTxGen3DownscaleAmp[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen3DownscaleAmp; - FspmUpd->FspmConfig.PchPcieHsioTxGen1DeEmphEnable[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DeEmphEnable; - FspmUpd->FspmConfig.PchPcieHsioTxGen1DeEmph[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DeEmph; - FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph3p5Enable[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph3p5Enable; - FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph3p5[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph3p5; - FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph6p0Enable[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph6p0Enable; - FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph6p0[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph6p0; - } - - // - // Update HSIO SATA policies - // - for (Index = 0; Index < PCH_MAX_SATA_PORTS; Index ++) { - FspmUpd->FspmConfig.PchSataHsioRxGen1EqBoostMagEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen1EqBoostMagEnable; - FspmUpd->FspmConfig.PchSataHsioRxGen1EqBoostMag[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen1EqBoostMag; - FspmUpd->FspmConfig.PchSataHsioRxGen2EqBoostMagEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen2EqBoostMagEnable; - FspmUpd->FspmConfig.PchSataHsioRxGen2EqBoostMag[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen2EqBoostMag; - FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEnable; - FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag; - FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmpEnable; - FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp; - FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmpEnable; - FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp; - FspmUpd->FspmConfig.PchSataHsioTxGen3DownscaleAmpEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DownscaleAmpEnable; - FspmUpd->FspmConfig.PchSataHsioTxGen3DownscaleAmp[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DownscaleAmp; - FspmUpd->FspmConfig.PchSataHsioTxGen1DeEmphEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DeEmphEnable; - FspmUpd->FspmConfig.PchSataHsioTxGen1DeEmph[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DeEmph; - FspmUpd->FspmConfig.PchSataHsioTxGen2DeEmphEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DeEmphEnable; - FspmUpd->FspmConfig.PchSataHsioTxGen2DeEmph[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DeEmph; - FspmUpd->FspmConfig.PchSataHsioTxGen3DeEmphEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DeEmphEnable; - FspmUpd->FspmConfig.PchSataHsioTxGen3DeEmph[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DeEmph; - } - - // - // Update HSIO policies - // - FspmUpd->FspmTestConfig.ChipsetInitMessage = (UINT8)HsioPreMemConfig->ChipsetInitMessage; - FspmUpd->FspmTestConfig.BypassPhySyncReset = (UINT8)HsioPreMemConfig->BypassPhySyncReset; - - // - // Update LPC policies - // - FspmUpd->FspmConfig.PchLpcEnhancePort8xhDecoding = (UINT8)LpcPreMemConfig->EnhancePort8xhDecoding; - - // - // Update Pch General Premem policies - // - FspmUpd->FspmConfig.PchAcpiBase = (UINT16)PchGeneralPreMemConfig->AcpiBase; - FspmUpd->FspmConfig.PchPort80Route = (UINT8)PchGeneralPreMemConfig->Port80Route; - - // - // Update Wdt policies - // - FspmUpd->FspmTestConfig.WdtDisableAndLock = (UINT8)WdtPreMemConfig->DisableAndLock; - - - return EFI_SUCCESS; -} - -/** - Performs FSP PCH PEI Policy initialization. - - @param[in][out] FspsUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspPchPolicyInit ( - IN OUT FSPS_UPD *FspsUpd - ) -{ - EFI_STATUS Status; - UINTN Index; - SI_POLICY_PPI *SiPolicy; - PCH_LAN_CONFIG *LanConfig; - PCH_HDAUDIO_CONFIG *HdAudioConfig; - PCH_SCS_CONFIG *ScsConfig; - PCH_ISH_CONFIG *IshConfig; - PCH_SPI_CONFIG *SpiConfig; - PCH_SATA_CONFIG *SataConfig; - PCH_USB_CONFIG *UsbConfig; - PCH_SERIAL_IO_CONFIG *SerialIoConfig; - PCH_INTERRUPT_CONFIG *InterruptConfig; - PCH_LOCK_DOWN_CONFIG *LockDownConfig; - PCH_CIO2_CONFIG *Cio2Config; - PCH_PCIE_CONFIG *PcieRpConfig; - PCH_DMI_CONFIG *DmiConfig; - PCH_FLASH_PROTECTION_CONFIG *FlashProtectionConfig; - PCH_IOAPIC_CONFIG *IoApicConfig; - PCH_P2SB_CONFIG *P2sbConfig; - PCH_GENERAL_CONFIG *PchGeneralConfig; - PCH_PM_CONFIG *PmConfig; - PCH_PORT61H_SMM_CONFIG *Port61hConfig; - PCH_LPC_SIRQ_CONFIG *PchSerialIrqConfig; - PCH_THERMAL_CONFIG *PchThermalConfig; - - DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP UpdatePeiPchPolicy\n")); - // - // Locate SiPolicyPpi - // - SiPolicy = NULL; - Status = PeiServicesLocatePpi ( - &gSiPolicyPpiGuid, - 0, - NULL, - (VOID **) &SiPolicy - ); - if (EFI_ERROR (Status)) { - return EFI_NOT_FOUND; - } - - Status = GetConfigBlock ((VOID *) SiPolicy, &gLanConfigGuid, (VOID *) &LanConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPolicy, &gHdAudioConfigGuid, (VOID *) &HdAudioConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPolicy, &gScsConfigGuid, (VOID *) &ScsConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPolicy, &gIshConfigGuid, (VOID *) &IshConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPolicy, &gSpiConfigGuid, (VOID *) &SpiConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPolicy, &gSataConfigGuid, (VOID *) &SataConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPolicy, &gUsbConfigGuid, (VOID *) &UsbConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPolicy, &gSerialIoConfigGuid, (VOID *) &SerialIoConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPolicy, &gInterruptConfigGuid, (VOID *) &InterruptConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPolicy, &gLockDownConfigGuid, (VOID *) &LockDownConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPolicy, &gCio2ConfigGuid, (VOID *) &Cio2Config); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPolicy, &gPcieRpConfigGuid, (VOID *) &PcieRpConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPolicy, &gDmiConfigGuid, (VOID *) &DmiConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPolicy, &gFlashProtectionConfigGuid, (VOID *) &FlashProtectionConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPolicy, &gIoApicConfigGuid, (VOID *) &IoApicConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPolicy, &gP2sbConfigGuid, (VOID *) &P2sbConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPolicy, &gPchGeneralConfigGuid, (VOID *) &PchGeneralConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPolicy, &gPmConfigGuid, (VOID *) &PmConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPolicy, &gPort61ConfigGuid, (VOID *) &Port61hConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPolicy, &gSerialIrqConfigGuid, (VOID *) &PchSerialIrqConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPolicy, &gThermalConfigGuid, (VOID *) &PchThermalConfig); - ASSERT_EFI_ERROR (Status); - // - // Update LAN policies - // - FspsUpd->FspsConfig.PchLanEnable = (UINT8)LanConfig->Enable; - FspsUpd->FspsConfig.PchLanLtrEnable = (UINT8)LanConfig->LtrEnable; - FspsUpd->FspsConfig.PchLanK1OffEnable = (UINT8)LanConfig->K1OffEnable; - FspsUpd->FspsConfig.PchLanClkReqSupported = (UINT8)LanConfig->ClkReqSupported; - FspsUpd->FspsConfig.PchLanClkReqNumber = (UINT8)LanConfig->ClkReqNumber; - - // - // Update HDA policies - // - FspsUpd->FspsConfig.PchHdaEnable = (UINT8)HdAudioConfig->Enable; - FspsUpd->FspsConfig.PchHdaDspEnable = (UINT8)HdAudioConfig->DspEnable; - FspsUpd->FspsConfig.PchHdaIoBufferOwnership = (UINT8)HdAudioConfig->IoBufferOwnership; - - FspsUpd->FspsConfig.PchHdaPme = (UINT8)HdAudioConfig->Pme; - FspsUpd->FspsConfig.PchHdaIoBufferVoltage = (UINT8)HdAudioConfig->IoBufferVoltage; - FspsUpd->FspsConfig.PchHdaVcType = (UINT8)HdAudioConfig->VcType; - FspsUpd->FspsConfig.PchHdaLinkFrequency = (UINT8)HdAudioConfig->HdAudioLinkFrequency; - FspsUpd->FspsConfig.PchHdaIDispLinkFrequency = (UINT8)HdAudioConfig->IDispLinkFrequency; - FspsUpd->FspsConfig.PchHdaIDispLinkTmode = (UINT8)HdAudioConfig->IDispLinkTmode; - FspsUpd->FspsConfig.PchHdaDspUaaCompliance = (UINT8)HdAudioConfig->DspUaaCompliance; - FspsUpd->FspsConfig.PchHdaIDispCodecDisconnect = (UINT8)HdAudioConfig->IDispCodecDisconnect; - FspsUpd->FspsConfig.PchHdaDspEndpointDmic = (UINT8)HdAudioConfig->DspEndpointDmic; - FspsUpd->FspsConfig.PchHdaDspEndpointBluetooth = (UINT8)HdAudioConfig->DspEndpointBluetooth; - FspsUpd->FspsConfig.PchHdaDspEndpointI2s = (UINT8)HdAudioConfig->DspEndpointI2s; - FspsUpd->FspsConfig.PchHdaDspFeatureMask = (UINT32)HdAudioConfig->DspFeatureMask; - FspsUpd->FspsTestConfig.PchHdaResetWaitTimer = (UINT16)HdAudioConfig->ResetWaitTimer; - FspsUpd->FspsConfig.PchHdaVerbTableEntryNum = HdAudioConfig->VerbTableEntryNum; - FspsUpd->FspsConfig.PchHdaVerbTablePtr = HdAudioConfig->VerbTablePtr; - - // - // Update CIO2 policies - // - FspsUpd->FspsConfig.PchCio2Enable = (UINT8)Cio2Config->DeviceEnable; - FspsUpd->FspsConfig.PchSkyCamPortATermOvrEnable = (UINT8)Cio2Config->SkyCamPortATermOvrEnable; - FspsUpd->FspsConfig.PchSkyCamPortBTermOvrEnable = (UINT8)Cio2Config->SkyCamPortBTermOvrEnable; - FspsUpd->FspsConfig.PchSkyCamPortCTermOvrEnable = (UINT8)Cio2Config->SkyCamPortCTermOvrEnable; - FspsUpd->FspsConfig.PchSkyCamPortDTermOvrEnable = (UINT8)Cio2Config->SkyCamPortDTermOvrEnable; - FspsUpd->FspsConfig.PchSkyCamPortATrimEnable = (UINT8)Cio2Config->PortATrimEnable; - FspsUpd->FspsConfig.PchSkyCamPortBTrimEnable = (UINT8)Cio2Config->PortBTrimEnable; - FspsUpd->FspsConfig.PchSkyCamPortCTrimEnable = (UINT8)Cio2Config->PortCTrimEnable; - FspsUpd->FspsConfig.PchSkyCamPortDTrimEnable = (UINT8)Cio2Config->PortDTrimEnable; - FspsUpd->FspsConfig.PchSkyCamPortACtleEnable = (UINT8)Cio2Config->PortACtleEnable; - FspsUpd->FspsConfig.PchSkyCamPortBCtleEnable = (UINT8)Cio2Config->PortBCtleEnable; - FspsUpd->FspsConfig.PchSkyCamPortCDCtleEnable = (UINT8)Cio2Config->PortCDCtleEnable; - FspsUpd->FspsConfig.PchSkyCamPortACtleCapValue = (UINT8)Cio2Config->PortACtleCapValue; - FspsUpd->FspsConfig.PchSkyCamPortBCtleCapValue = (UINT8)Cio2Config->PortBCtleCapValue; - FspsUpd->FspsConfig.PchSkyCamPortCDCtleCapValue = (UINT8)Cio2Config->PortCDCtleCapValue; - FspsUpd->FspsConfig.PchSkyCamPortACtleResValue = (UINT8)Cio2Config->PortACtleResValue; - FspsUpd->FspsConfig.PchSkyCamPortBCtleResValue = (UINT8)Cio2Config->PortBCtleResValue; - FspsUpd->FspsConfig.PchSkyCamPortCDCtleResValue = (UINT8)Cio2Config->PortCDCtleResValue; - FspsUpd->FspsConfig.PchSkyCamPortAClkTrimValue = (UINT8)Cio2Config->PortAClkTrimValue; - FspsUpd->FspsConfig.PchSkyCamPortBClkTrimValue = (UINT8)Cio2Config->PortBClkTrimValue; - FspsUpd->FspsConfig.PchSkyCamPortCClkTrimValue = (UINT8)Cio2Config->PortCClkTrimValue; - FspsUpd->FspsConfig.PchSkyCamPortDClkTrimValue = (UINT8)Cio2Config->PortDClkTrimValue; - FspsUpd->FspsConfig.PchSkyCamPortADataTrimValue = (UINT16)Cio2Config->PortADataTrimValue; - FspsUpd->FspsConfig.PchSkyCamPortBDataTrimValue = (UINT16)Cio2Config->PortBDataTrimValue; - FspsUpd->FspsConfig.PchSkyCamPortCDDataTrimValue = (UINT16)Cio2Config->PortCDDataTrimValue; - - // - // Update SCS policies - // - FspsUpd->FspsConfig.ScsEmmcEnabled = (UINT8)ScsConfig->ScsEmmcEnabled; - FspsUpd->FspsConfig.ScsEmmcHs400Enabled = (UINT8)ScsConfig->ScsEmmcHs400Enabled; - FspsUpd->FspsConfig.ScsSdCardEnabled = (UINT8)ScsConfig->ScsSdSwitch == 0 ? 0 : 1; - FspsUpd->FspsConfig.PchScsEmmcHs400TuningRequired = (UINT8)ScsConfig->ScsEmmcHs400TuningRequired; - FspsUpd->FspsConfig.PchScsEmmcHs400DllDataValid = (UINT8)ScsConfig->ScsEmmcHs400DllDataValid; - FspsUpd->FspsConfig.PchScsEmmcHs400RxStrobeDll1 = (UINT8)ScsConfig->ScsEmmcHs400RxStrobeDll1; - FspsUpd->FspsConfig.PchScsEmmcHs400TxDataDll = (UINT8)ScsConfig->ScsEmmcHs400TxDataDll; - FspsUpd->FspsConfig.PchScsEmmcHs400DriverStrength = (UINT8)ScsConfig->ScsEmmcHs400DriverStrength; - - // - // Update ISH policies - // - FspsUpd->FspsConfig.PchIshEnable = (UINT8)IshConfig->Enable; - FspsUpd->FspsConfig.PchIshSpiGpioAssign = (UINT8)IshConfig->SpiGpioAssign; - FspsUpd->FspsConfig.PchIshUart0GpioAssign = (UINT8)IshConfig->Uart0GpioAssign; - FspsUpd->FspsConfig.PchIshUart1GpioAssign = (UINT8)IshConfig->Uart1GpioAssign; - FspsUpd->FspsConfig.PchIshI2c0GpioAssign = (UINT8)IshConfig->I2c0GpioAssign; - FspsUpd->FspsConfig.PchIshI2c1GpioAssign = (UINT8)IshConfig->I2c1GpioAssign; - FspsUpd->FspsConfig.PchIshI2c2GpioAssign = (UINT8)IshConfig->I2c2GpioAssign; - FspsUpd->FspsConfig.PchIshGp0GpioAssign = (UINT8)IshConfig->Gp0GpioAssign; - FspsUpd->FspsConfig.PchIshGp1GpioAssign = (UINT8)IshConfig->Gp1GpioAssign; - FspsUpd->FspsConfig.PchIshGp2GpioAssign = (UINT8)IshConfig->Gp2GpioAssign; - FspsUpd->FspsConfig.PchIshGp3GpioAssign = (UINT8)IshConfig->Gp3GpioAssign; - FspsUpd->FspsConfig.PchIshGp4GpioAssign = (UINT8)IshConfig->Gp4GpioAssign; - FspsUpd->FspsConfig.PchIshGp5GpioAssign = (UINT8)IshConfig->Gp5GpioAssign; - FspsUpd->FspsConfig.PchIshGp6GpioAssign = (UINT8)IshConfig->Gp6GpioAssign; - FspsUpd->FspsConfig.PchIshGp7GpioAssign = (UINT8)IshConfig->Gp7GpioAssign; - FspsUpd->FspsConfig.PchIshPdtUnlock = (UINT8)IshConfig->PdtUnlock; - - // - // Update SPI policies - // - FspsUpd->FspsConfig.ShowSpiController = (UINT8)SpiConfig->ShowSpiController; - - // - // Update PCIE RP RootPort policies - // - for (Index = 0; Index < KBL_PCH_H_PCIE_MAX_ROOT_PORTS; Index ++) { - FspsUpd->FspsConfig.PcieRpHotPlug[Index] = (UINT8)PcieRpConfig->RootPort[Index].HotPlug; - FspsUpd->FspsConfig.PcieRpPmSci[Index] = (UINT8)PcieRpConfig->RootPort[Index].PmSci; - FspsUpd->FspsConfig.PcieRpExtSync[Index] = (UINT8)PcieRpConfig->RootPort[Index].ExtSync; - FspsUpd->FspsConfig.PcieRpTransmitterHalfSwing[Index] = (UINT8)PcieRpConfig->RootPort[Index].TransmitterHalfSwing; - FspsUpd->FspsConfig.PcieRpClkReqSupport[Index] = (UINT8)PcieRpConfig->RootPort[Index].ClkReqSupported; - FspsUpd->FspsConfig.PcieRpClkReqNumber[Index] = (UINT8)PcieRpConfig->RootPort[Index].ClkReqNumber; - FspsUpd->FspsConfig.PcieRpClkReqDetect[Index] = (UINT8)PcieRpConfig->RootPort[Index].ClkReqDetect; - FspsUpd->FspsConfig.PcieRpAdvancedErrorReporting[Index] = (UINT8)PcieRpConfig->RootPort[Index].AdvancedErrorReporting; - FspsUpd->FspsConfig.PcieRpUnsupportedRequestReport[Index] = (UINT8)PcieRpConfig->RootPort[Index].UnsupportedRequestReport; - FspsUpd->FspsConfig.PcieRpFatalErrorReport[Index] = (UINT8)PcieRpConfig->RootPort[Index].FatalErrorReport; - FspsUpd->FspsConfig.PcieRpNoFatalErrorReport[Index] = (UINT8)PcieRpConfig->RootPort[Index].NoFatalErrorReport; - FspsUpd->FspsConfig.PcieRpCorrectableErrorReport[Index] = (UINT8)PcieRpConfig->RootPort[Index].CorrectableErrorReport; - FspsUpd->FspsConfig.PcieRpSystemErrorOnFatalError[Index] = (UINT8)PcieRpConfig->RootPort[Index].SystemErrorOnFatalError; - FspsUpd->FspsConfig.PcieRpSystemErrorOnNonFatalError[Index] = (UINT8)PcieRpConfig->RootPort[Index].SystemErrorOnNonFatalError; - FspsUpd->FspsConfig.PcieRpSystemErrorOnCorrectableError[Index] = (UINT8)PcieRpConfig->RootPort[Index].SystemErrorOnCorrectableError; - FspsUpd->FspsConfig.PcieRpMaxPayload[Index] = (UINT8)PcieRpConfig->RootPort[Index].MaxPayload; - FspsUpd->FspsConfig.PcieRpDeviceResetPadActiveHigh[Index] = (UINT8)PcieRpConfig->RootPort[Index].DeviceResetPadActiveHigh; - FspsUpd->FspsConfig.PcieRpPcieSpeed[Index] = (UINT8)PcieRpConfig->RootPort[Index].PcieSpeed; - FspsUpd->FspsConfig.PcieRpGen3EqPh3Method[Index] = (UINT8)PcieRpConfig->RootPort[Index].Gen3EqPh3Method; - FspsUpd->FspsConfig.PcieRpPhysicalSlotNumber[Index] = (UINT8)PcieRpConfig->RootPort[Index].PhysicalSlotNumber; - FspsUpd->FspsConfig.PcieRpCompletionTimeout[Index] = (UINT8)PcieRpConfig->RootPort[Index].CompletionTimeout; - FspsUpd->FspsConfig.PcieRpDeviceResetPad[Index] = (UINT32)PcieRpConfig->RootPort[Index].DeviceResetPad; - FspsUpd->FspsConfig.PcieRpAspm[Index] = (UINT8)PcieRpConfig->RootPort[Index].Aspm; - FspsUpd->FspsConfig.PcieRpL1Substates[Index] = (UINT8)PcieRpConfig->RootPort[Index].L1Substates; - FspsUpd->FspsConfig.PcieRpLtrEnable[Index] = (UINT8)PcieRpConfig->RootPort[Index].LtrEnable; - FspsUpd->FspsConfig.PcieRpLtrConfigLock[Index] = (UINT8)PcieRpConfig->RootPort[Index].LtrConfigLock; - FspsUpd->FspsTestConfig.PcieRpLtrMaxSnoopLatency[Index] = (UINT16)PcieRpConfig->RootPort[Index].LtrMaxSnoopLatency; - FspsUpd->FspsTestConfig.PcieRpLtrMaxNoSnoopLatency[Index] = (UINT16)PcieRpConfig->RootPort[Index].LtrMaxNoSnoopLatency; - - FspsUpd->FspsTestConfig.PcieRpSnoopLatencyOverrideMode[Index] = (UINT8)PcieRpConfig->RootPort[Index].SnoopLatencyOverrideMode; - FspsUpd->FspsTestConfig.PcieRpSnoopLatencyOverrideMultiplier[Index] = (UINT8)PcieRpConfig->RootPort[Index].SnoopLatencyOverrideMultiplier; - FspsUpd->FspsTestConfig.PcieRpSnoopLatencyOverrideValue[Index] = (UINT16)PcieRpConfig->RootPort[Index].SnoopLatencyOverrideValue; - - FspsUpd->FspsTestConfig.PcieRpNonSnoopLatencyOverrideMode[Index] = (UINT8)PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideMode; - FspsUpd->FspsTestConfig.PcieRpNonSnoopLatencyOverrideMultiplier[Index] = (UINT8)PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideMultiplier; - FspsUpd->FspsTestConfig.PcieRpNonSnoopLatencyOverrideValue[Index] = (UINT16)PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideValue; - - FspsUpd->FspsTestConfig.PcieRpSlotPowerLimitScale[Index] = (UINT8)PcieRpConfig->RootPort[Index].SlotPowerLimitScale; - FspsUpd->FspsTestConfig.PcieRpSlotPowerLimitValue[Index] = (UINT16)PcieRpConfig->RootPort[Index].SlotPowerLimitValue; - FspsUpd->FspsTestConfig.PcieRpUptp[Index] = (UINT8)PcieRpConfig->RootPort[Index].Uptp; - FspsUpd->FspsTestConfig.PcieRpDptp[Index] = (UINT8)PcieRpConfig->RootPort[Index].Dptp; - } - - // - // Update PCIE RP EqPh3LaneParam policies - // - for (Index = 0; Index < KBL_PCH_H_PCIE_MAX_ROOT_PORTS; Index ++) { - FspsUpd->FspsConfig.PcieEqPh3LaneParamCm[Index] = (UINT8)PcieRpConfig->EqPh3LaneParam[Index].Cm; - FspsUpd->FspsConfig.PcieEqPh3LaneParamCp[Index] = (UINT8)PcieRpConfig->EqPh3LaneParam[Index].Cp; - } - - // - // Update PCIE RP SwEqCoeffList policies - // - for (Index = 0; Index < PCH_PCIE_SWEQ_COEFFS_MAX; Index ++) { - FspsUpd->FspsConfig.PcieSwEqCoeffListCm[Index] = (UINT8)PcieRpConfig->SwEqCoeffList[Index].Cm; - FspsUpd->FspsConfig.PcieSwEqCoeffListCp[Index] = (UINT8)PcieRpConfig->SwEqCoeffList[Index].Cp; - } - - // - // Update PCIE RP policies - // - FspsUpd->FspsTestConfig.PcieEnablePort8xhDecode = (UINT8)PcieRpConfig->EnablePort8xhDecode; - FspsUpd->FspsTestConfig.PchPciePort8xhDecodePortIndex = (UINT8)PcieRpConfig->PchPciePort8xhDecodePortIndex; - FspsUpd->FspsConfig.PcieDisableRootPortClockGating = (UINT8)PcieRpConfig->DisableRootPortClockGating; - FspsUpd->FspsConfig.PcieEnablePeerMemoryWrite = (UINT8)PcieRpConfig->EnablePeerMemoryWrite; - FspsUpd->FspsConfig.PcieAllowNoLtrIccPllShutdown = (UINT8)PcieRpConfig->AllowNoLtrIccPllShutdown; - FspsUpd->FspsConfig.PcieComplianceTestMode = (UINT8)PcieRpConfig->ComplianceTestMode; - FspsUpd->FspsConfig.PcieRpFunctionSwap = (UINT8)PcieRpConfig->RpFunctionSwap; - FspsUpd->FspsConfig.PcieDetectTimeoutMs = (UINT16)PcieRpConfig->DetectTimeoutMs; - FspsUpd->FspsConfig.PchPcieDeviceOverrideTablePtr = PcieRpConfig->PcieDeviceOverrideTablePtr; - - // - // Update Sata Policies - // - FspsUpd->FspsConfig.SataEnable = (UINT8)SataConfig->Enable; - FspsUpd->FspsTestConfig.SataTestMode = (UINT8)SataConfig->TestMode; - FspsUpd->FspsConfig.SataSalpSupport = (UINT8)SataConfig->SalpSupport; - FspsUpd->FspsConfig.SataPwrOptEnable = (UINT8)SataConfig->PwrOptEnable; - FspsUpd->FspsConfig.EsataSpeedLimit = (UINT8)SataConfig->EsataSpeedLimit; - FspsUpd->FspsConfig.SataMode = (UINT8)SataConfig->SataMode; - FspsUpd->FspsConfig.SataSpeedLimit = (UINT8)SataConfig->SpeedLimit; - - for (Index = 0; Index < PCH_MAX_SATA_PORTS; Index++) { - FspsUpd->FspsConfig.SataPortsEnable[Index] = (UINT8)SataConfig->PortSettings[Index].Enable; - FspsUpd->FspsConfig.SataPortsHotPlug[Index] = (UINT8)SataConfig->PortSettings[Index].HotPlug; - FspsUpd->FspsConfig.SataPortsInterlockSw[Index] = (UINT8)SataConfig->PortSettings[Index].InterlockSw; - FspsUpd->FspsConfig.SataPortsExternal[Index] = (UINT8)SataConfig->PortSettings[Index].External; - FspsUpd->FspsConfig.SataPortsSpinUp[Index] = (UINT8)SataConfig->PortSettings[Index].SpinUp; - FspsUpd->FspsConfig.SataPortsSolidStateDrive[Index] = (UINT8)SataConfig->PortSettings[Index].SolidStateDrive; - FspsUpd->FspsConfig.SataPortsDevSlp[Index] = (UINT8)SataConfig->PortSettings[Index].DevSlp; - FspsUpd->FspsConfig.SataPortsEnableDitoConfig[Index] = (UINT8)SataConfig->PortSettings[Index].EnableDitoConfig; - FspsUpd->FspsConfig.SataPortsDmVal[Index] = (UINT8)SataConfig->PortSettings[Index].DmVal; - FspsUpd->FspsConfig.SataPortsDitoVal[Index] = (UINT16)SataConfig->PortSettings[Index].DitoVal; - FspsUpd->FspsConfig.SataPortsZpOdd[Index] = (UINT8)SataConfig->PortSettings[Index].ZpOdd; - } - - FspsUpd->FspsConfig.SataRstRaidAlternateId = (UINT8)SataConfig->Rst.RaidDeviceId; - FspsUpd->FspsConfig.SataRstRaid0 = (UINT8)SataConfig->Rst.Raid0; - FspsUpd->FspsConfig.SataRstRaid1 = (UINT8)SataConfig->Rst.Raid1; - FspsUpd->FspsConfig.SataRstRaid10 = (UINT8)SataConfig->Rst.Raid10; - FspsUpd->FspsConfig.SataRstRaid5 = (UINT8)SataConfig->Rst.Raid5; - FspsUpd->FspsConfig.SataRstIrrt = (UINT8)SataConfig->Rst.Irrt; - FspsUpd->FspsConfig.SataRstOromUiBanner = (UINT8)SataConfig->Rst.OromUiBanner; - FspsUpd->FspsConfig.SataRstOromUiDelay = (UINT8)SataConfig->Rst.OromUiDelay; - FspsUpd->FspsConfig.SataRstHddUnlock = (UINT8)SataConfig->Rst.HddUnlock; - FspsUpd->FspsConfig.SataRstLedLocate = (UINT8)SataConfig->Rst.LedLocate; - FspsUpd->FspsConfig.SataRstIrrtOnly = (UINT8)SataConfig->Rst.IrrtOnly; - FspsUpd->FspsConfig.SataRstSmartStorage = (UINT8)SataConfig->Rst.SmartStorage; - FspsUpd->FspsConfig.SataRstOptaneMemory = (UINT8)SataConfig->Rst.OptaneMemory; - - for (Index = 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) { - FspsUpd->FspsConfig.SataRstPcieEnable[Index] = (UINT8)SataConfig->RstPcieStorageRemap[Index].Enable; - FspsUpd->FspsConfig.SataRstPcieStoragePort[Index] = (UINT8)SataConfig->RstPcieStorageRemap[Index].RstPcieStoragePort; - FspsUpd->FspsConfig.SataRstPcieDeviceResetDelay[Index] = (UINT8)SataConfig->RstPcieStorageRemap[Index].DeviceResetDelay; - } - - // - // Update USB policies - // - FspsUpd->FspsConfig.PchDisableComplianceMode = (UINT8)UsbConfig->DisableComplianceMode; - for (Index = 0; Index < PCH_MAX_USB2_PORTS; Index++) { - FspsUpd->FspsConfig.PortUsb20Enable[Index] = (UINT8)UsbConfig->PortUsb20[Index].Enable; - FspsUpd->FspsConfig.Usb2OverCurrentPin[Index] = (UINT8)UsbConfig->PortUsb20[Index].OverCurrentPin; - FspsUpd->FspsConfig.Usb2AfePetxiset[Index] = (UINT8)UsbConfig->PortUsb20[Index].Afe.Petxiset; - FspsUpd->FspsConfig.Usb2AfeTxiset[Index] = (UINT8)UsbConfig->PortUsb20[Index].Afe.Txiset; - FspsUpd->FspsConfig.Usb2AfePredeemp[Index] = (UINT8)UsbConfig->PortUsb20[Index].Afe.Predeemp; - FspsUpd->FspsConfig.Usb2AfePehalfbit[Index] = (UINT8)UsbConfig->PortUsb20[Index].Afe.Pehalfbit; - } - for (Index = 0; Index < PCH_MAX_USB3_PORTS; Index++) { - FspsUpd->FspsConfig.PortUsb30Enable[Index] = (UINT8)UsbConfig->PortUsb30[Index].Enable; - FspsUpd->FspsConfig.Usb3OverCurrentPin[Index] = (UINT8)UsbConfig->PortUsb30[Index].OverCurrentPin; - FspsUpd->FspsConfig.Usb3HsioTxDeEmphEnable[Index] = (UINT8)UsbConfig->PortUsb30[Index].HsioTxDeEmphEnable; - FspsUpd->FspsConfig.Usb3HsioTxDeEmph[Index] = (UINT8)UsbConfig->PortUsb30[Index].HsioTxDeEmph; - FspsUpd->FspsConfig.Usb3HsioTxDownscaleAmpEnable[Index] = (UINT8)UsbConfig->PortUsb30[Index].HsioTxDownscaleAmpEnable; - FspsUpd->FspsConfig.Usb3HsioTxDownscaleAmp[Index] = (UINT8)UsbConfig->PortUsb30[Index].HsioTxDownscaleAmp; - } - FspsUpd->FspsConfig.SsicPortEnable = (UINT8)UsbConfig->SsicConfig.SsicPort[0].Enable; - FspsUpd->FspsConfig.XdciEnable = (UINT8)UsbConfig->XdciConfig.Enable; - - // - // Update SerialIo policies - // - for (Index = 0; Index < PCH_SERIALIO_MAX_CONTROLLERS; Index++) { - FspsUpd->FspsConfig.SerialIoDevMode[Index] = (UINT8)SerialIoConfig->DevMode[Index]; - } - for (Index = 0; Index < PCH_SERIALIO_MAX_I2C_CONTROLLERS; Index++) { - FspsUpd->FspsConfig.SerialIoI2cVoltage[Index] = (UINT8)SerialIoConfig->I2cVoltage[Index]; - } - for (Index = 0; Index < PCH_SERIALIO_MAX_SPI_CONTROLLERS; Index++) { - FspsUpd->FspsConfig.SerialIoSpiCsPolarity[Index] = (UINT8)SerialIoConfig->SpiCsPolarity[Index]; - } - for (Index = 0; Index < PCH_SERIALIO_MAX_UART_CONTROLLERS; Index++) { - FspsUpd->FspsConfig.SerialIoUartHwFlowCtrl[Index] = (UINT8)SerialIoConfig->UartHwFlowCtrl[Index]; - } - FspsUpd->FspsConfig.SerialIoGpio = (UINT8)SerialIoConfig->Gpio; - FspsUpd->FspsConfig.SerialIoDebugUartNumber = (UINT8)SerialIoConfig->DebugUartNumber; - FspsUpd->FspsConfig.SerialIoEnableDebugUartAfterPost = (UINT8)SerialIoConfig->EnableDebugUartAfterPost; - - // - // Update Interrupt policies - // - FspsUpd->FspsConfig.DevIntConfigPtr = (UINT32)InterruptConfig->DevIntConfig; - FspsUpd->FspsConfig.NumOfDevIntConfig = InterruptConfig->NumOfDevIntConfig; - for (Index = 0; Index < PCH_MAX_PXRC_CONFIG; Index ++) { - FspsUpd->FspsConfig.PxRcConfig[Index] = (UINT8)InterruptConfig->PxRcConfig[Index]; - } - FspsUpd->FspsConfig.GpioIrqRoute = (UINT8)InterruptConfig->GpioIrqRoute; - FspsUpd->FspsConfig.SciIrqSelect = (UINT8)InterruptConfig->SciIrqSelect; - FspsUpd->FspsConfig.TcoIrqSelect = (UINT8)InterruptConfig->TcoIrqSelect; - FspsUpd->FspsConfig.TcoIrqEnable = (UINT8)InterruptConfig->TcoIrqEnable; - - // - // Update LockDown policies - // - FspsUpd->FspsTestConfig.PchLockDownRtcLock = (UINT8)LockDownConfig->RtcLock; - FspsUpd->FspsTestConfig.PchLockDownGlobalSmi = (UINT8)LockDownConfig->GlobalSmi; - FspsUpd->FspsTestConfig.PchLockDownBiosInterface = (UINT8)LockDownConfig->BiosInterface; - FspsUpd->FspsConfig.PchLockDownBiosLock = (UINT8)LockDownConfig->BiosLock; - FspsUpd->FspsConfig.PchLockDownSpiEiss = (UINT8)LockDownConfig->SpiEiss; - - // - // Update Dmi policies - // - FspsUpd->FspsConfig.PchDmiAspm = (UINT8)DmiConfig->DmiAspm; - FspsUpd->FspsConfig.PchPwrOptEnable = (UINT8)DmiConfig->PwrOptEnable; - if (DmiConfig->LegacyIoLowLatency) { - FspsUpd->FspsConfig.PchDmiAspm = 0; - FspsUpd->FspsConfig.PchLegacyIoLowLatency = TRUE; - } - - // - // Update Flash Protection policies - // - for (Index = 0; Index < PCH_FLASH_PROTECTED_RANGES; Index ++) { - FspsUpd->FspsConfig.PchWriteProtectionEnable[Index] = (UINT8)FlashProtectionConfig->ProtectRange[Index].WriteProtectionEnable; - FspsUpd->FspsConfig.PchReadProtectionEnable[Index] = (UINT8)FlashProtectionConfig->ProtectRange[Index].ReadProtectionEnable; - FspsUpd->FspsConfig.PchProtectedRangeLimit[Index] = (UINT16)FlashProtectionConfig->ProtectRange[Index].ProtectedRangeLimit; - FspsUpd->FspsConfig.PchProtectedRangeBase[Index] = (UINT16)FlashProtectionConfig->ProtectRange[Index].ProtectedRangeBase; - } - - // - // Update IO Apic policies - // - FspsUpd->FspsConfig.PchIoApicBdfValid = (UINT8)IoApicConfig->BdfValid; - FspsUpd->FspsConfig.PchIoApicBusNumber = (UINT8)IoApicConfig->BusNumber; - FspsUpd->FspsConfig.PchIoApicDeviceNumber = (UINT8)IoApicConfig->DeviceNumber; - FspsUpd->FspsConfig.PchIoApicFunctionNumber = (UINT8)IoApicConfig->FunctionNumber; - FspsUpd->FspsConfig.PchIoApicEntry24_119 = (UINT8)IoApicConfig->IoApicEntry24_119; - FspsUpd->FspsConfig.Early8254ClockGatingEnable = (UINT8)IoApicConfig->Early8254ClockGatingEnable; - FspsUpd->FspsConfig.PchIoApicId = (UINT8)IoApicConfig->IoApicId; - FspsUpd->FspsConfig.PchIoApicRangeSelect = (UINT8)IoApicConfig->ApicRangeSelect; - - // - // Update P2sb policies - // - FspsUpd->FspsTestConfig.PchSbiUnlock = (UINT8)P2sbConfig->SbiUnlock; - FspsUpd->FspsTestConfig.PchSbAccessUnlock = (UINT8)P2sbConfig->SbAccessUnlock; - - // - // Update Pch General policies - // - FspsUpd->FspsConfig.PchSubSystemVendorId = (UINT16)PchGeneralConfig->SubSystemVendorId; - FspsUpd->FspsConfig.PchSubSystemId = (UINT16)PchGeneralConfig->SubSystemId; - FspsUpd->FspsConfig.PchCrid = (UINT8)PchGeneralConfig->Crid; - - // - // Update Pm policies - // - FspsUpd->FspsConfig.PchPmPmeB0S5Dis = (UINT8)PmConfig->WakeConfig.PmeB0S5Dis; - FspsUpd->FspsConfig.PchPmWolEnableOverride = (UINT8)PmConfig->WakeConfig.WolEnableOverride; - FspsUpd->FspsConfig.PchPmPcieWakeFromDeepSx = (UINT8)PmConfig->WakeConfig.PcieWakeFromDeepSx; - FspsUpd->FspsConfig.PchPmWoWlanEnable = (UINT8)PmConfig->WakeConfig.WoWlanEnable; - FspsUpd->FspsConfig.PchPmWoWlanDeepSxEnable = (UINT8)PmConfig->WakeConfig.WoWlanDeepSxEnable; - FspsUpd->FspsConfig.PchPmLanWakeFromDeepSx = (UINT8)PmConfig->WakeConfig.LanWakeFromDeepSx; - - FspsUpd->FspsConfig.PchPmDeepSxPol = (UINT8)PmConfig->PchDeepSxPol; - FspsUpd->FspsConfig.PchPmSlpS3MinAssert = (UINT8)PmConfig->PchSlpS3MinAssert; - FspsUpd->FspsConfig.PchPmSlpS4MinAssert = (UINT8)PmConfig->PchSlpS4MinAssert; - FspsUpd->FspsConfig.PchPmSlpSusMinAssert = (UINT8)PmConfig->PchSlpSusMinAssert; - FspsUpd->FspsConfig.PchPmSlpAMinAssert = (UINT8)PmConfig->PchSlpAMinAssert; - - FspsUpd->FspsConfig.PchPmLpcClockRun = (UINT8)PmConfig->LpcClockRun; - FspsUpd->FspsConfig.PchPmSlpStrchSusUp = (UINT8)PmConfig->SlpStrchSusUp; - FspsUpd->FspsConfig.PchPmSlpLanLowDc = (UINT8)PmConfig->SlpLanLowDc; - FspsUpd->FspsConfig.PchPmPwrBtnOverridePeriod = (UINT8)PmConfig->PwrBtnOverridePeriod; - FspsUpd->FspsTestConfig.PchPmDisableEnergyReport = (UINT8)PmConfig->DisableEnergyReport; - FspsUpd->FspsConfig.PchPmDisableDsxAcPresentPulldown = (UINT8)PmConfig->DisableDsxAcPresentPulldown; - FspsUpd->FspsTestConfig.PchPmPmcReadDisable = (UINT8)PmConfig->PmcReadDisable; - FspsUpd->FspsConfig.PchPmDisableNativePowerButton = (UINT8)PmConfig->DisableNativePowerButton; - FspsUpd->FspsConfig.PchPmSlpS0Enable = (UINT8)PmConfig->SlpS0Enable; - FspsUpd->FspsConfig.PchPmSlpS0VmEnable = (UINT8)PmConfig->SlpS0VmEnable; - FspsUpd->FspsConfig.PchPmMeWakeSts = (UINT8)PmConfig->MeWakeSts; - FspsUpd->FspsConfig.PchPmWolOvrWkSts = (UINT8)PmConfig->WolOvrWkSts; - FspsUpd->FspsConfig.EnableTcoTimer = (UINT8)PmConfig->EnableTcoTimer; - FspsUpd->FspsConfig.PchPmPwrCycDur = (UINT8)PmConfig->PchPwrCycDur; - - // - // Update Port61h policies - // - FspsUpd->FspsConfig.PchPort61hEnable = (UINT8)Port61hConfig->Enable; - - // - // Update Pch Serial IRQ policies - // - FspsUpd->FspsConfig.PchSirqEnable = (UINT8)PchSerialIrqConfig->SirqEnable; - FspsUpd->FspsConfig.PchSirqMode = (UINT8)PchSerialIrqConfig->SirqMode; - FspsUpd->FspsConfig.PchStartFramePulse = (UINT8)PchSerialIrqConfig->StartFramePulse; - - // - // Update Pch Thermal policies - // - FspsUpd->FspsConfig.PchThermalDeviceEnable = (UINT8)PchThermalConfig->ThermalDeviceEnable; - FspsUpd->FspsConfig.PchTsmicLock = (UINT8)PchThermalConfig->TsmicLock; - - FspsUpd->FspsConfig.PchT0Level = (UINT16)PchThermalConfig->TTLevels.T0Level; - FspsUpd->FspsConfig.PchT1Level = (UINT16)PchThermalConfig->TTLevels.T1Level; - FspsUpd->FspsConfig.PchT2Level = (UINT16)PchThermalConfig->TTLevels.T2Level; - FspsUpd->FspsConfig.PchTTEnable = (UINT8)PchThermalConfig->TTLevels.TTEnable; - FspsUpd->FspsConfig.PchTTState13Enable = (UINT8)PchThermalConfig->TTLevels.TTState13Enable; - FspsUpd->FspsConfig.PchTTLock = (UINT8)PchThermalConfig->TTLevels.TTLock; - FspsUpd->FspsConfig.TTSuggestedSetting = (UINT8)PchThermalConfig->TTLevels.SuggestedSetting; - FspsUpd->FspsConfig.TTCrossThrottling = (UINT8)PchThermalConfig->TTLevels.PchCrossThrottling; - - FspsUpd->FspsConfig.PchDmiTsawEn = (UINT8)PchThermalConfig->DmiHaAWC.DmiTsawEn; - FspsUpd->FspsConfig.DmiSuggestedSetting = (UINT8)PchThermalConfig->DmiHaAWC.SuggestedSetting; - FspsUpd->FspsConfig.DmiTS0TW = (UINT8)PchThermalConfig->DmiHaAWC.TS0TW; - FspsUpd->FspsConfig.DmiTS1TW = (UINT8)PchThermalConfig->DmiHaAWC.TS1TW; - FspsUpd->FspsConfig.DmiTS2TW = (UINT8)PchThermalConfig->DmiHaAWC.TS2TW; - FspsUpd->FspsConfig.DmiTS3TW = (UINT8)PchThermalConfig->DmiHaAWC.TS3TW; - - FspsUpd->FspsConfig.SataP0T1M = (UINT8)PchThermalConfig->SataTT.P0T1M; - FspsUpd->FspsConfig.SataP0T2M = (UINT8)PchThermalConfig->SataTT.P0T2M; - FspsUpd->FspsConfig.SataP0T3M = (UINT8)PchThermalConfig->SataTT.P0T3M; - FspsUpd->FspsConfig.SataP0TDisp = (UINT8)PchThermalConfig->SataTT.P0TDisp; - FspsUpd->FspsConfig.SataP1T1M = (UINT8)PchThermalConfig->SataTT.P1T1M; - FspsUpd->FspsConfig.SataP1T2M = (UINT8)PchThermalConfig->SataTT.P1T2M; - FspsUpd->FspsConfig.SataP1T3M = (UINT8)PchThermalConfig->SataTT.P1T3M; - FspsUpd->FspsConfig.SataP1TDisp = (UINT8)PchThermalConfig->SataTT.P1TDisp; - FspsUpd->FspsConfig.SataP0Tinact = (UINT8)PchThermalConfig->SataTT.P0Tinact; - FspsUpd->FspsConfig.SataP0TDispFinit = (UINT8)PchThermalConfig->SataTT.P0TDispFinit; - FspsUpd->FspsConfig.SataP1Tinact = (UINT8)PchThermalConfig->SataTT.P1Tinact; - FspsUpd->FspsConfig.SataP1TDispFinit = (UINT8)PchThermalConfig->SataTT.P1TDispFinit; - FspsUpd->FspsConfig.SataThermalSuggestedSetting = (UINT8)PchThermalConfig->SataTT.SuggestedSetting; - - FspsUpd->FspsConfig.PchMemoryThrottlingEnable = (UINT8)PchThermalConfig->MemoryThrottling.Enable; - FspsUpd->FspsConfig.PchMemoryPmsyncEnable[0] = (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[0].PmsyncEnable; - FspsUpd->FspsConfig.PchMemoryPmsyncEnable[1] = (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[1].PmsyncEnable; - FspsUpd->FspsConfig.PchMemoryC0TransmitEnable[0] = (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[0].C0TransmitEnable; - FspsUpd->FspsConfig.PchMemoryC0TransmitEnable[1] = (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[1].C0TransmitEnable; - FspsUpd->FspsConfig.PchMemoryPinSelection[0] = (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[0].PinSelection; - FspsUpd->FspsConfig.PchMemoryPinSelection[1] = (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[1].PinSelection; - - FspsUpd->FspsConfig.PchTemperatureHotLevel = (UINT16)PchThermalConfig->PchHotLevel; - - - return EFI_SUCCESS; -} diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.c deleted file mode 100644 index fb868e693b..0000000000 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.c +++ /dev/null @@ -1,146 +0,0 @@ -/** @file - Instance of Fsp Policy Initialization Library. - -Copyright (c) 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include - -/** - Performs FSPM UPD Policy initialization. - - Value of FspmUpd has been initialized by FSP binary default value. - Only a subset of FspmUpd needs to be updated for different silicon sku. - - @param[in, out] FspmUpd Pointer to FSPM UPD data. -**/ -VOID -EFIAPI -FspmPolicyInit ( - IN OUT VOID *FspmUpd - ) -{ - FSPM_UPD *FspmUpdDataPtr; - EFI_STATUS Status; - - FspmUpdDataPtr = FspmUpd; - - // - // Initialize Intel PEI Platform Policy - // - PeiPolicyInitPreMem (); - - // - // SI Pei Fsp Policy Initialization - // - Status = PeiFspSiPolicyInitPreMem (FspmUpdDataPtr); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_WARN, "ERROR - SI Pei Fsp Policy in Pre-Memory Initialization fail, Status = %r\n", Status)); - } - - // - // PCH Pei Fsp Policy Initialization - // - Status = PeiFspPchPolicyInitPreMem (FspmUpdDataPtr); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_WARN, "ERROR - PCH Pei Fsp Policy in Pre-Memory Initialization fail, Status = %r\n", Status)); - } - - // - // Cpu Pei Fsp Policy Initialization - // - Status = PeiFspCpuPolicyInitPreMem (FspmUpdDataPtr); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_WARN, "ERROR - CPU Pei Fsp Policy in Pre-Memory Initialization fail, Status = %r\n", Status)); - } - - - // - // ME Pei Fsp Policy Initialization - // - Status = PeiFspMePolicyInitPreMem (FspmUpdDataPtr); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_WARN, "ERROR - ME Pei Fsp Policy in Pre-Memory Initialization fail, Status = %r\n", Status)); - } - - // - // SystemAgent Pei Fsp Policy Initialization - // - Status = PeiFspSaPolicyInitPreMem (FspmUpdDataPtr); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_WARN, "ERROR - SystemAgent Pei Fsp Policy in Pre-Memory Initialization fail, Status = %r\n", Status)); - } - - // - // Other Upd Initialization - // - Status = PeiFspMiscUpdInitPreMem (FspmUpdDataPtr); - -} - -/** - Performs FSPS UPD Policy initialization. - - Value of FspsUpd has been initialized by FSP binary default value. - Only a subset of FspsUpd needs to be updated for different silicon sku. - - @param[in, out] FspsUpd Pointer to FSPS UPD data. -**/ -VOID -EFIAPI -FspsPolicyInit ( - IN OUT VOID *FspsUpd - ) -{ - FSPS_UPD *FspsUpdDataPtr; - EFI_STATUS Status; - - FspsUpdDataPtr = FspsUpd; - - // - // Initialize Intel PEI Platform Policy - // - PeiPolicyInit (); - - // - // PCH Pei Fsp Policy Initialization - // - Status = PeiFspPchPolicyInit (FspsUpdDataPtr); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_WARN, "ERROR - PCH Pei Fsp Policy iInitialization fail, Status = %r\n", Status)); - } - - // - // ME Pei Fsp Policy Initialization - // - Status = PeiFspMePolicyInit (FspsUpdDataPtr); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_WARN, "ERROR - ME Pei Fsp Policy Initialization fail, Status = %r\n", Status)); - } - - // - // SystemAgent Pei Fsp Policy Initialization - // - Status = PeiFspSaPolicyInit (FspsUpdDataPtr); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_WARN, "ERROR - SystemAgent Pei Fsp Policy Initialization fail, Status = %r\n", Status)); - } - - - // - // Cpu Pei Fsp Policy Initialization - // - Status = PeiFspCpuPolicyInit (FspsUpdDataPtr); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_WARN, "ERROR - CPU Pei Fsp Policy Initialization fail, Status = %r\n", Status)); - } - -} diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.h b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.h deleted file mode 100644 index a17b642a1d..0000000000 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.h +++ /dev/null @@ -1,179 +0,0 @@ -/** @file - Internal header file for Fsp Policy Initialization Library. - -Copyright (c) 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#ifndef _PEI_FSP_POLICY_INIT_LIB_H_ -#define _PEI_FSP_POLICY_INIT_LIB_H_ - -#include - -#include -#include -#include -#include "PeiPolicyInitLib.h" - -#include -#include -#include - -/** - Performs FSP SI PEI Policy initialization. - - @param[in][out] FspmUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspSiPolicyInitPreMem ( - IN OUT FSPM_UPD *FspmUpd - ); - -/** - Performs FSP PCH PEI Policy pre mem initialization. - - @param[in][out] FspmUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspPchPolicyInitPreMem ( - IN OUT FSPM_UPD *FspmUpd - ); - -/** - Performs FSP PCH PEI Policy initialization. - - @param[in][out] FspsUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspPchPolicyInit ( - IN OUT FSPS_UPD *FspsUpd - ); - -/** - Performs FSP CPU PEI Policy initialization. - - @param[in][out] FspmUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspCpuPolicyInitPreMem ( - IN OUT FSPM_UPD *FspmUpd - ); - - -/** - Performs FSP ME PEI Policy pre mem initialization. - - @param[in][out] FspmUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspMePolicyInitPreMem ( - IN OUT FSPM_UPD *FspmUpd - ); - -/** - Performs FSP ME PEI Policy initialization. - - @param[in][out] FspsUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspMePolicyInit ( - IN OUT FSPS_UPD *FspsUpd - ); - -/** - Performs FSP SA PEI Policy initialization in pre-memory. - - @param[in][out] FspmUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspSaPolicyInitPreMem ( - IN OUT FSPM_UPD *FspmUpd - ); - -/** - Performs FSP SA PEI Policy initialization. - - @param[in][out] FspsUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspSaPolicyInit ( - IN OUT FSPS_UPD *FspsUpd - ); - - -/** - Performs FSP CPU PEI Policy post memory initialization. - - @param[in][out] FspsUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspCpuPolicyInit ( - IN OUT FSPS_UPD *FspsUpd - ); - -/** - Performs FSP Misc UPD initialization. - - @param[in][out] FspmUpd Pointer to FSPM_UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. -**/ -EFI_STATUS -EFIAPI -PeiFspMiscUpdInitPreMem ( - IN OUT FSPM_UPD *FspmUpd - ); - -#endif // _PEI_FSP_POLICY_INIT_LIB_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf deleted file mode 100644 index 5a77bfb34a..0000000000 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf +++ /dev/null @@ -1,146 +0,0 @@ -### @file -# Library functions for Fsp Policy Initialization Library. -# -# Copyright (c) 2017, Intel Corporation. All rights reserved.
-# -# This program and the accompanying materials are licensed and made available under -# the terms and conditions of the BSD License which accompanies this distribution. -# The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -## - -################################################################################ -# -# Defines Section - statements that will be processed to create a Makefile. -# -################################################################################ -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = PeiFspPolicyInitLib - FILE_GUID = 2CB87D67-D1A4-4CD3-8CD7-91A1FA1DF6E0 - MODULE_TYPE = BASE - VERSION_STRING = 1.0 - LIBRARY_CLASS = FspPolicyInitLib - -# -# The following information is for reference only and not required by the build tools. -# -# VALID_ARCHITECTURES = IA32 -# - -################################################################################ -# -# Sources Section - list of files that are required for the build to succeed. -# -################################################################################ - -[Sources] - PeiFspPolicyInitLib.c - PeiFspSiPolicyInitLib.c - PeiFspPchPolicyInitLib.c - PeiFspCpuPolicyInitLib.c - PeiFspMePolicyInitLib.c - PeiFspSaPolicyInitLib.c - PeiFspMiscUpdInitLib.c - - PeiPolicyInitPreMem.c - PeiPolicyInit.c - PeiPolicyInit.h - -################################################################################ -# -# Package Dependency Section - list of Package files that are required for -# this module. -# -################################################################################ - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - IntelFsp2Pkg/IntelFsp2Pkg.dec - KabylakeSiliconPkg/SiPkg.dec - KabylakeFspBinPkg/KabylakeFspBinPkg.dec - -[LibraryClasses] - BaseMemoryLib - DebugLib - IoLib - PeiServicesLib - PcdLib - SmbusLib - MmPciLib - ConfigBlockLib - MemoryAllocationLib - DebugPrintErrorLevelLib - -[Pcd] - gSiPkgTokenSpaceGuid.PcdTsegSize ## CONSUMES - gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress ## CONSUMES - gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES - gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES - gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES - gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CONSUMES - -[Ppis] - gSiPolicyPpiGuid ## CONSUMES - gSiPreMemPolicyPpiGuid ## CONSUMES - -[Guids] - gTraceHubPreMemConfigGuid ## CONSUMES - gSmbusPreMemConfigGuid ## CONSUMES - gDciPreMemConfigGuid ## CONSUMES - gHpetPreMemConfigGuid ## CONSUMES - gHsioPciePreMemConfigGuid ## CONSUMES - gHsioSataPreMemConfigGuid ## CONSUMES - gHsioPreMemConfigGuid ## CONSUMES - gPcieRpPreMemConfigGuid ## CONSUMES - gLpcPreMemConfigGuid ## CONSUMES - gPchGeneralPreMemConfigGuid ## CONSUMES - gWatchDogPreMemConfigGuid ## CONSUMES - gLanConfigGuid ## CONSUMES - gPcieRpConfigGuid ## CONSUMES - gSataConfigGuid ## CONSUMES - gHdAudioConfigGuid ## CONSUMES - gCio2ConfigGuid ## CONSUMES - gScsConfigGuid ## CONSUMES - gIshConfigGuid ## CONSUMES - gSpiConfigGuid ## CONSUMES - gSataConfigGuid ## CONSUMES - gUsbConfigGuid ## CONSUMES - gSerialIoConfigGuid ## CONSUMES - gInterruptConfigGuid ## CONSUMES - gLockDownConfigGuid ## CONSUMES - gSaMiscPeiPreMemConfigGuid ## PRODUCES - gMemoryConfigGuid ## CONSUMES - gMemoryConfigNoCrcGuid ## CONSUMES - gGraphicsPeiConfigGuid ## CONSUMES - gMePeiPreMemConfigGuid ## CONSUMES - gMePeiConfigGuid ## CONSUMES - gAmtPeiConfigGuid ## CONSUMES - gDmiConfigGuid ## CONSUMES - gFlashProtectionConfigGuid ## CONSUMES - gIoApicConfigGuid ## CONSUMES - gPmConfigGuid ## CONSUMES - gP2sbConfigGuid ## CONSUMES - gPchGeneralConfigGuid ## CONSUMES - gPort61ConfigGuid ## CONSUMES - gSerialIrqConfigGuid ## CONSUMES - gThermalConfigGuid ## CONSUMES - gCpuSecurityPreMemConfigGuid ## CONSUMES - gCpuTxtPreMemConfigGuid ## CONSUMES - gCpuConfigGuid ## CONSUMES - gBiosGuardConfigGuid ## CONSUMES - gCpuOverclockingPreMemConfigGuid ## CONSUMES - gCpuConfigLibPreMemConfigGuid ## CONSUMES - gCpuSgxConfigGuid ## CONSUMES - gCpuPowerMgmtBasicConfigGuid ## CONSUMES - gCpuPowerMgmtCustomConfigGuid ## CONSUMES - gCpuTestConfigGuid ## CONSUMES - gCpuPidTestConfigGuid ## CONSUMES - gCpuPowerMgmtTestConfigGuid ## CONSUMES - gSmramCpuDataHeaderGuid ## CONSUMES - gFspReservedMemoryResourceHobTsegGuid ## CONSUMES diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspSaPolicyInitLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspSaPolicyInitLib.c deleted file mode 100644 index 3d218f8ba9..0000000000 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspSaPolicyInitLib.c +++ /dev/null @@ -1,578 +0,0 @@ -/** @file - Implementation of Fsp SA Policy Initialization. - -Copyright (c) 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#define MAX_SPD_PAGE_COUNT (2) -#define MAX_SPD_PAGE_SIZE (256) -#define MAX_SPD_SIZE (MAX_SPD_PAGE_SIZE * MAX_SPD_PAGE_COUNT) -#define SPD_PAGE_ADDRESS_0 (0x6C) -#define SPD_PAGE_ADDRESS_1 (0x6E) -#define SPD_DDR3_SDRAM_TYPE_OFFSET (0x02) -#define SPD_DDR3_SDRAM_TYPE_NUMBER (0x0B) -#define SPD_DDR4_SDRAM_TYPE_NUMBER (0x0C) -#define SPD_LPDDR3_SDRAM_TYPE_NUMBER (0xF1) -#define SPD_JEDEC_LPDDR3_SDRAM_TYPE_NUMBER (0x0F) -#define XMP_ID_STRING (0x4A0C) -#define SPD3_MANUF_START (117) -#define SPD3_MANUF_END (127) -#define SPD4_MANUF_START (320) -#define SPD4_MANUF_END (328) -#define SPDLP_MANUF_START (320) -#define SPDLP_MANUF_END (328) - -GLOBAL_REMOVE_IF_UNREFERENCED const SPD_OFFSET_TABLE mSpdDdr3Table[] = { - { 0, 1, (1 << SpdCold),}, - { 2, 2, (1 << SpdCold) | (1 << SpdFast),}, - { 3, 41, (1 << SpdCold),}, - { 60, 63, (1 << SpdCold),}, - { SPD3_MANUF_START, SPD3_MANUF_END, (1 << SpdCold) | (1 << SpdFast),}, - { 128, 145, (1 << SpdCold),}, -#ifdef SUPPORT_SPD_CRC - { 39, 59, (1 << SpdCold),}, - { 64, 125, (1 << SpdCold),}, -#endif - { 176, 179, (1 << SpdCold),}, - { 180, 184, (1 << SpdCold),}, - { 185, 215, (1 << SpdCold),}, - { 220, 250, (1 << SpdCold),}, -}; - -GLOBAL_REMOVE_IF_UNREFERENCED const SPD_OFFSET_TABLE mSpdDdr4Table[] = { - { 0, 1, (1 << SpdCold),}, - { 2, 2, (1 << SpdCold) | (1 << SpdFast),}, - { 3, 40, (1 << SpdCold),}, - { 117, 131, (1 << SpdCold),}, - { SPD4_MANUF_START, SPD4_MANUF_END, (1 << SpdCold) | (1 << SpdFast),}, - { 329, 348, (1 << SpdCold),}, -#ifdef SUPPORT_SPD_CRC - { 32, 119, (1 << SpdCold),}, - { 126, 255, (1 << SpdCold),}, - { 349, 383, (1 << SpdCold),}, -#endif - { 384, 387, (1 << SpdCold),}, - { 388, 389, (1 << SpdCold),}, - { 393, 431, (1 << SpdCold),}, - { 440, 478, (1 << SpdCold),}, -}; - -GLOBAL_REMOVE_IF_UNREFERENCED const SPD_OFFSET_TABLE mSpdLpddrTable[] = { - { 0, 1, (1 << SpdCold),}, - { 2, 2, (1 << SpdCold) | (1 << SpdFast),}, - { 3, 32, (1 << SpdCold),}, - { 120, 130, (1 << SpdCold),}, - { SPDLP_MANUF_START, SPDLP_MANUF_END, (1 << SpdCold) | (1 << SpdFast),}, - { 329, 348, (1 << SpdCold),}, -#ifdef SUPPORT_SPD_CRC - { 31, 121, (1 << SpdCold),}, - { 126, 255, (1 << SpdCold),}, - { 349, 383, (1 << SpdCold),}, -#endif - { 384, 387, (1 << SpdCold),}, - { 388, 389, (1 << SpdCold),}, - { 393, 431, (1 << SpdCold),}, - { 440, 478, (1 << SpdCold),}, -}; - - -/** - Read the SPD data over the SMBus, at the specified SPD address, starting at - the specified starting offset and read the given amount of data. - - @param[in] SpdAddress - SPD SMBUS address - @param[in, out] Buffer - Buffer to store the data. - @param[in] Start - Starting SPD offset - @param[in] Size - The number of bytes of data to read and also the size of the buffer. - @param[in, out] Page - The final page that is being pointed to. - - @retval EFI_SUCCESS if the read is successful, otherwise error status. -**/ -static -EFI_STATUS -InternalDoSpdRead ( - IN const UINT8 SpdAddress, - IN OUT UINT8 *const Buffer, - IN const UINT16 Start, - IN UINT16 Size, - IN OUT UINT8 *const Page - ) -{ - EFI_STATUS EfiStatus; - BOOLEAN PageUpdate; - UINT16 Count; - UINT16 Index; - - EfiStatus = EFI_DEVICE_ERROR; - if ((Buffer != NULL) && (Start < MAX_SPD_SIZE) && ((Start + Size) < MAX_SPD_SIZE)) { - Count = 0; - PageUpdate = FALSE; - while (Size--) { - Index = Start + Count; - if ((Index / MAX_SPD_PAGE_SIZE) != *Page) { - *Page = (UINT8) (Index / MAX_SPD_PAGE_SIZE); - PageUpdate = TRUE; - } - Index %= MAX_SPD_PAGE_SIZE; - if (PageUpdate == TRUE) { - PageUpdate = FALSE; - SmBusWriteDataByte ((*Page == 0) ? SPD_PAGE_ADDRESS_0 : SPD_PAGE_ADDRESS_1, 0, &EfiStatus); - } - Buffer[Count] = SmBusReadDataByte (SpdAddress | ((UINT32) Index << 8), &EfiStatus); - if (EFI_SUCCESS != EfiStatus) { - Buffer[Count] = 0; - break; - } - Count++; - } - EfiStatus = EFI_SUCCESS; - } - return (EfiStatus); -} - -/** - See if there is valid XMP SPD data. - - @param[in] Debug - Mrc debug structure. - @param[in, out] Spd - Mrc SPD structure. - @param[in] XmpStart - The current offset in the SPD. - - @retval TRUE if valid, FALSE in not. -**/ -static -BOOLEAN -InternalVerifyXmp ( - IN OUT MrcSpd *const Spd, - IN const UINT16 XmpStart - ) -{ - SPD_EXTREME_MEMORY_PROFILE_HEADER *Header1; - SPD_EXTREME_MEMORY_PROFILE_HEADER_2_0 *Header2; - BOOLEAN Xmp; - - Xmp = FALSE; - - switch (((UINT8 *)Spd)[2]) { - case SPD_DDR3_SDRAM_TYPE_NUMBER: - Header1 = &Spd->Ddr3.Xmp.Header; - if (XmpStart == ((UINT32) (Header1) - (UINT32) Spd)) { - Xmp = TRUE; - if ((Header1->XmpRevision.Data & 0xFE) == 0x12) { - return (TRUE); - } else { - Header1->XmpId = 0; - Header1->XmpOrgConf.Data = 0; - Header1->XmpRevision.Data = 0; - } - } - break; - case SPD_DDR4_SDRAM_TYPE_NUMBER: - Header2 = &Spd->Ddr4.EndUser.Xmp.Header; - if (XmpStart == ((UINT32) (Header2) - (UINT32) Spd)) { - Xmp = TRUE; - if ((Header2->XmpRevision.Data) == 0x20) { - return (TRUE); - } else { - Header2->XmpId = 0; - Header2->XmpOrgConf.Data = 0; - Header2->XmpRevision.Data = 0; - } - } - break; - case SPD_JEDEC_LPDDR3_SDRAM_TYPE_NUMBER: - case SPD_LPDDR3_SDRAM_TYPE_NUMBER: - return (TRUE); - default: - return (FALSE); - } - if (!Xmp) { - return (TRUE); - } - return (FALSE); -} - -/** - Read the SPD data over the SMBus, at the given SmBus SPD address and copy the data to the data structure. - The SPD data locations read is controlled by the current boot mode. - - @param[in] BootMode - The current MRC boot mode. - @param[in] Address - SPD SmBus address offset. - @param[in] Buffer - Buffer that contains the data read from the SPD. - @param[in] SpdDdr3Table - Indicates which SPD bytes to read. - @param[in] SpdDdr3TableSize - Size of SpdDdr3Table in bytes. - @param[in] SpdDdr4Table - Indicates which SPD bytes to read. - @param[in] SpdDdr4TableSize - Size of SpdDdr4Table in bytes. - @param[in] SpdLpddrTable - Indicates which SPD bytes to read. - @param[in] SpdLpddrTableSize - Size of SpdLpddrTable in bytes. - - @retval TRUE if the read is successful, otherwise FALSE on error. -**/ -BOOLEAN -InternalGetSpdData ( - IN SPD_BOOT_MODE BootMode, - IN UINT8 Address, - IN OUT UINT8 *Buffer, - IN UINT8 *SpdDdr3Table, - IN UINT32 SpdDdr3TableSize, - IN UINT8 *SpdDdr4Table, - IN UINT32 SpdDdr4TableSize, - IN UINT8 *SpdLpddrTable, - IN UINT32 SpdLpddrTableSize - ) -{ - const SPD_OFFSET_TABLE *Tbl; - const SPD_OFFSET_TABLE *TableSelect; - EFI_STATUS Status; - UINT32 Byte; - UINT32 Stop; - UINT8 Page; - - Page = (UINT8) (~0); - Status = InternalDoSpdRead (Address, &Buffer[SPD_DDR3_SDRAM_TYPE_OFFSET], 2, 1, &Page); - if (EFI_SUCCESS == Status) { - switch (Buffer[SPD_DDR3_SDRAM_TYPE_OFFSET]) { - case SPD_DDR3_SDRAM_TYPE_NUMBER: - case SPD_LPDDR3_SDRAM_TYPE_NUMBER: - default: - TableSelect = (SPD_OFFSET_TABLE *) SpdDdr3Table; - Stop = (SpdDdr3TableSize / sizeof (SPD_OFFSET_TABLE)); - break; - case SPD_DDR4_SDRAM_TYPE_NUMBER: - TableSelect = (SPD_OFFSET_TABLE *) SpdDdr4Table; - Stop = (SpdDdr4TableSize / sizeof (SPD_OFFSET_TABLE)); - break; - case SPD_JEDEC_LPDDR3_SDRAM_TYPE_NUMBER: - TableSelect = (SPD_OFFSET_TABLE *) SpdLpddrTable; - Stop = (SpdLpddrTableSize / sizeof (SPD_OFFSET_TABLE)); - break; - } - for (Byte = 0; (EFI_SUCCESS == Status) && (Byte < Stop); Byte++) { - Tbl = &TableSelect[Byte]; - if ((1 << BootMode) & Tbl->BootMode) { - Status = InternalDoSpdRead (Address, &Buffer[Tbl->Start], Tbl->Start, Tbl->End - Tbl->Start + 1, &Page); - if (Status == EFI_SUCCESS) { - if (SpdCold == BootMode) { - if (FALSE == InternalVerifyXmp ((MrcSpd *) Buffer, Tbl->Start)) { - break; - } - } - } else { - break; - } - } - } - } - - return ((EFI_SUCCESS == Status) ? TRUE : FALSE); -} - -/** - Initialize the Smbus PPI and program the Smbus BAR - - @retval EFI_SUCCESS The function completes successfully - @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database -**/ -EFI_STATUS -InternalInitializePchSmbus ( - VOID - ) -{ - UINTN SmbusRegBase; - SmbusRegBase = MmPciBase ( - DEFAULT_PCI_BUS_NUMBER_PCH, - PCI_DEVICE_NUMBER_PCH_SMBUS, - PCI_FUNCTION_NUMBER_PCH_SMBUS - ); - - /// - /// Since PEI has no PCI enumerator, set the BAR & I/O space enable ourselves - /// - MmioAndThenOr32 (SmbusRegBase + R_PCH_SMBUS_BASE, B_PCH_SMBUS_BASE_BAR, PcdGet16 (PcdSmbusBaseAddress)); - - MmioOr8 (SmbusRegBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_IO_SPACE); - - /// - /// Reset the SMBus host controller - /// - MmioOr8 (SmbusRegBase + R_PCH_SMBUS_HOSTC, B_PCH_SMBUS_HOSTC_SSRESET); - - /// - /// Enable the SMBus host controller - /// - MmioAndThenOr8 ( - SmbusRegBase + R_PCH_SMBUS_HOSTC, - (UINT8)(~(B_PCH_SMBUS_HOSTC_SMI_EN | B_PCH_SMBUS_HOSTC_I2C_EN)), - B_PCH_SMBUS_HOSTC_HST_EN - ); - - /// - /// Clear Status Register before anyone uses the interfaces - /// - IoWrite8 (PcdGet16(PcdSmbusBaseAddress) + R_PCH_SMBUS_HSTS, B_PCH_SMBUS_HSTS_ALL); - - return EFI_SUCCESS; -} - -/** - Update Spd Data - - @param[in][out] FspmUpd Pointer to FSP UPD Data. - @param[in] MemConfigNoCrc Pointer to Mem Config No Crc. - @param[in] MiscPeiPreMemConfig Pointer to Misc Config. - - @retval EFI_SUCCESS The function completes successfully - @retval Other The function fail -**/ -VOID -EFIAPI -InternalUpdateSpdData ( - IN OUT FSPM_UPD *FspmUpd, - IN MEMORY_CONFIG_NO_CRC *MemConfigNoCrc, - IN SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig - ) -{ - UINT8 Socket; - UINT8 *SpdData; - - InternalInitializePchSmbus (); - - DEBUG ((DEBUG_INFO, "Updating UPD:Memory Spd Pointers...\n")); - if (FspmUpd == NULL || MemConfigNoCrc == NULL) { - DEBUG ((DEBUG_ERROR, "EFI_INVALID_PARAMETER.\n")); - DEBUG ((DEBUG_ERROR, "Fail to access SPD from SiPolicyPpi\n")); - return; - } - - if (*((UINT32 *)MiscPeiPreMemConfig->SpdAddressTable) != 0x0) { - // - // Update MemConfigNoCrc->SpdData->SpdData - // - for (Socket = 0; Socket < SA_MC_MAX_SOCKETS; Socket++) { - SpdData = (UINT8 *)((UINT32)MemConfigNoCrc->SpdData->SpdData + (Socket * SA_MC_MAX_SPD_SIZE)); - InternalGetSpdData ( - 0, - MiscPeiPreMemConfig->SpdAddressTable[Socket], - (UINT8 *)SpdData, - (UINT8 *)&mSpdDdr3Table, - sizeof(mSpdDdr3Table), - (UINT8 *)&mSpdDdr4Table, - sizeof(mSpdDdr4Table), - (UINT8 *)&mSpdLpddrTable, - sizeof(mSpdLpddrTable) - ); - } - } - - FspmUpd->FspmConfig.MemorySpdPtr00 = (UINT32)MemConfigNoCrc->SpdData->SpdData; - FspmUpd->FspmConfig.MemorySpdPtr01 = (UINT32)MemConfigNoCrc->SpdData->SpdData + (1 * SA_MC_MAX_SPD_SIZE); - FspmUpd->FspmConfig.MemorySpdPtr10 = (UINT32)MemConfigNoCrc->SpdData->SpdData + (2 * SA_MC_MAX_SPD_SIZE); - FspmUpd->FspmConfig.MemorySpdPtr11 = (UINT32)MemConfigNoCrc->SpdData->SpdData + (3 * SA_MC_MAX_SPD_SIZE); - - DEBUG ((DEBUG_INFO, "UPD:MemorySpdPtr Updated\n")); -} - -/** - Performs FSP SA PEI Policy initialization in pre-memory. - - @param[in][out] FspmUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspSaPolicyInitPreMem ( - IN OUT FSPM_UPD *FspmUpd - ) -{ - EFI_STATUS Status; - SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; - MEMORY_CONFIGURATION *MemConfig; - MEMORY_CONFIG_NO_CRC *MemConfigNoCrc; - SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; - - // - // Locate SiPreMemPolicyPpi - // - SiPreMemPolicyPpi = NULL; - MiscPeiPreMemConfig = NULL; - MemConfig = NULL; - MemConfigNoCrc = NULL; - - - Status = PeiServicesLocatePpi( - &gSiPreMemPolicyPpiGuid, - 0, - NULL, - (VOID **) &SiPreMemPolicyPpi - ); - ASSERT_EFI_ERROR (Status); - if (EFI_ERROR (Status) == FALSE) { - Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gMemoryConfigNoCrcGuid, (VOID *) &MemConfigNoCrc); - ASSERT_EFI_ERROR (Status); - Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gMemoryConfigGuid, (VOID *) &MemConfig); - ASSERT_EFI_ERROR (Status); - } - - // - // Update UPD:DqPinsInterleaved - // - FspmUpd->FspmConfig.DqPinsInterleaved = (UINT8)MemConfig->DqPinsInterleaved; - - // - // Update UPD:DqPinsInterleaved - // - FspmUpd->FspmConfig.CaVrefConfig = MemConfig->CaVrefConfig; - - // - // Update UPD:MemorySpdPtrXX - // - InternalUpdateSpdData (FspmUpd, MemConfigNoCrc, MiscPeiPreMemConfig); - - // - // Update UPD:MemorySpdDataLen - // - FspmUpd->FspmConfig.MemorySpdDataLen = SA_MC_MAX_SPD_SIZE; - - // - // Update UPD:PlatformMemorySize - // - // - // @todo: This value is used since #183932. Revisit. - // - FspmUpd->FspmConfig.PlatformMemorySize = MemConfigNoCrc->PlatformMemorySize; - FspmUpd->FspmConfig.SaGv = MemConfig->SaGv; - FspmUpd->FspmConfig.RMT = (UINT8) MemConfig->RMT; - FspmUpd->FspmConfig.DdrFreqLimit = MemConfig->DdrFreqLimit; - - FspmUpd->FspmConfig.SpdProfileSelected = MemConfig->SpdProfileSelected; - FspmUpd->FspmConfig.VddVoltage = MemConfig->VddVoltage; - FspmUpd->FspmConfig.RefClk = MemConfig->RefClk; - FspmUpd->FspmConfig.Ratio = MemConfig->Ratio; - FspmUpd->FspmConfig.OddRatioMode = (UINT8) MemConfig->OddRatioMode; - FspmUpd->FspmConfig.tCL = (UINT8) MemConfig->tCL; - FspmUpd->FspmConfig.tCWL = (UINT8) MemConfig->tCWL; - FspmUpd->FspmConfig.tFAW = MemConfig->tFAW; - FspmUpd->FspmConfig.tRAS = MemConfig->tRAS; - FspmUpd->FspmConfig.tRCDtRP = (UINT8) MemConfig->tRCDtRP; - FspmUpd->FspmConfig.tREFI = MemConfig->tREFI; - FspmUpd->FspmConfig.tRFC = MemConfig->tRFC; - FspmUpd->FspmConfig.tRRD = (UINT8) MemConfig->tRRD; - FspmUpd->FspmConfig.tRTP = (UINT8) MemConfig->tRTP; - FspmUpd->FspmConfig.tWR = (UINT8) MemConfig->tWR; - FspmUpd->FspmConfig.tWTR = (UINT8) MemConfig->tWTR; - FspmUpd->FspmConfig.NModeSupport = MemConfig->NModeSupport; - FspmUpd->FspmConfig.DllBwEn0 = MemConfig->DllBwEn0; - FspmUpd->FspmConfig.DllBwEn1 = MemConfig->DllBwEn1; - FspmUpd->FspmConfig.DllBwEn2 = MemConfig->DllBwEn2; - FspmUpd->FspmConfig.DllBwEn3 = MemConfig->DllBwEn3; - FspmUpd->FspmConfig.EvLoader = (UINT8) MemConfig->EvLoader; - - // - // Update UPD:SmramMask - // - if (MemConfig != NULL) { - FspmUpd->FspmConfig.SmramMask = MemConfig->SmramMask; - } - - return EFI_SUCCESS; -} - -/** - Performs FSP SA PEI Policy initialization. - - @param[in][out] FspsUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspSaPolicyInit ( - IN OUT FSPS_UPD *FspsUpd - ) -{ - EFI_STATUS Status; - SI_POLICY_PPI *SiPolicyPpi; - GRAPHICS_PEI_CONFIG *GtConfig; - VTD_CONFIG *Vtd; - // - // Locate SiPolicyPpi - // - SiPolicyPpi = NULL; - Status = PeiServicesLocatePpi( - &gSiPolicyPpiGuid, - 0, - NULL, - (VOID **)&SiPolicyPpi - ); - if ((Status == EFI_SUCCESS) && (SiPolicyPpi != NULL)) { - GtConfig = NULL; - Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid, (VOID *) &GtConfig); - ASSERT_EFI_ERROR (Status); - - Vtd = NULL; - Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gVtdConfigGuid, (VOID *) &Vtd); - ASSERT_EFI_ERROR (Status); - - } - - DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP UpdatePeiSaPolicy\n")); - if (GtConfig != NULL) { - // - // For FSP, FspsUpd->FspsConfig.PeiGraphicsPeimInit is always enabled as default. - // - FspsUpd->FspsConfig.PeiGraphicsPeimInit = (UINT8) GtConfig->PeiGraphicsPeimInit; // SA: InternalOnly: For Internal validation we still need to enable both Enable/Disable Cases - - // - // Update UPD: VBT & LogoPtr - // - FspsUpd->FspsConfig.GraphicsConfigPtr = (UINT32) GtConfig->GraphicsConfigPtr; - DEBUG(( DEBUG_INFO, "VbtPtr from GraphicsPeiConfig is 0x%x\n", FspsUpd->FspsConfig.GraphicsConfigPtr)); - - FspsUpd->FspsConfig.LogoPtr = (UINT32) GtConfig->LogoPtr; - FspsUpd->FspsConfig.LogoSize = GtConfig->LogoSize; - DEBUG(( DEBUG_INFO, "LogoPtr from PeiFspSaPolicyInit GraphicsPeiConfig is 0x%x\n", FspsUpd->FspsConfig.LogoPtr)); - DEBUG(( DEBUG_INFO, "LogoSize from PeiFspSaPolicyInit GraphicsPeiConfig is 0x%x\n", FspsUpd->FspsConfig.LogoSize)); - - - - } - if (Vtd != NULL) { - FspsUpd->FspsConfig.X2ApicOptOut = (UINT8) Vtd->X2ApicOptOut; - FspsUpd->FspsConfig.VtdBaseAddress[0] = Vtd->BaseAddress[0]; - FspsUpd->FspsConfig.VtdBaseAddress[1] = Vtd->BaseAddress[1]; - FspsUpd->FspsTestConfig.VtdDisable = (UINT8) Vtd->VtdDisable; - } - return EFI_SUCCESS; -} diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspSiPolicyInitLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspSiPolicyInitLib.c deleted file mode 100644 index 49601b1496..0000000000 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspSiPolicyInitLib.c +++ /dev/null @@ -1,51 +0,0 @@ -/** @file - Implementation of Fsp SI Policy Initialization. - -Copyright (c) 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include -#include - -/** - Performs FSP SI PEI Policy initialization. - - @param[in][out] FspmUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspSiPolicyInitPreMem ( - IN OUT FSPM_UPD *FspmUpd - ) -{ - EFI_STATUS Status; - SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; - - // - // Locate SiPolicyPpi - // - SiPreMemPolicyPpi = NULL; - Status = PeiServicesLocatePpi ( - &gSiPreMemPolicyPpiGuid, - 0, - NULL, - (VOID **) &SiPreMemPolicyPpi - ); - if (EFI_ERROR (Status)) { - return EFI_NOT_FOUND; - } - - return EFI_SUCCESS; -} diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiPolicyInit.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiPolicyInit.c deleted file mode 100644 index abed092c46..0000000000 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiPolicyInit.c +++ /dev/null @@ -1,47 +0,0 @@ -/** @file - This file is SampleCode for Intel PEI Platform Policy initialization. - -Copyright (c) 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include "PeiPolicyInit.h" - -/** - Initialize Intel PEI Platform Policy - -**/ -VOID -EFIAPI -PeiPolicyInit ( - VOID - ) -{ - EFI_STATUS Status; - SI_POLICY_PPI *SiPolicyPpi; - - // - // Call SiCreateConfigBlocks to initialize Silicon Policy structure - // and get all Intel default policy settings. - // - Status = SiCreateConfigBlocks (&SiPolicyPpi); - ASSERT_EFI_ERROR (Status); - if (EFI_ERROR(Status)) { - return; - } - - // - // Install SiPolicyPpi. - // While installed, RC assumes the Policy is ready and finalized. So please - // update and override any setting before calling this function. - // - Status = SiInstallPolicyPpi (SiPolicyPpi); - ASSERT_EFI_ERROR (Status); -} diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiPolicyInit.h b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiPolicyInit.h deleted file mode 100644 index e85724411a..0000000000 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiPolicyInit.h +++ /dev/null @@ -1,24 +0,0 @@ -/** @file - Header file for the PolicyInitPei PEIM. - -Copyright (c) 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#ifndef _PEI_POLICY_INIT_H_ -#define _PEI_POLICY_INIT_H_ - -#include -#include -#include - -#include "PeiSiPolicyInit.h" - -#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiPolicyInitLib.h b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiPolicyInitLib.h deleted file mode 100644 index b5a7f4eef3..0000000000 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiPolicyInitLib.h +++ /dev/null @@ -1,37 +0,0 @@ -/** @file - Header file for the PolicyInitPei Library. - -Copyright (c) 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#ifndef _POLICY_INIT_PEI_LIB_H_ -#define _POLICY_INIT_PEI_LIB_H_ - -/** - Initialize Intel PEI Platform Policy - -**/ -VOID -EFIAPI -PeiPolicyInitPreMem ( - VOID - ); - -/** - Initialize Intel PEI Platform Policy - -**/ -VOID -EFIAPI -PeiPolicyInit ( - VOID - ); -#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiPolicyInitPreMem.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiPolicyInitPreMem.c deleted file mode 100644 index 35baba3183..0000000000 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiPolicyInitPreMem.c +++ /dev/null @@ -1,48 +0,0 @@ -/** @file - This file is SampleCode for Intel PEI Platform Policy initialization. - -Copyright (c) 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include "PeiPolicyInit.h" - -/** - Initialize Intel PEI Platform Policy - -**/ -VOID -EFIAPI -PeiPolicyInitPreMem ( - VOID - ) -{ - EFI_STATUS Status; - SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; - - DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Start in Pre-Memory...\n")); - // - // Call SiCreatePreMemConfigBlocks to initialize platform policy structure - // and get all intel default policy settings. - // - Status = SiCreatePreMemConfigBlocks (&SiPreMemPolicyPpi); - ASSERT_EFI_ERROR (Status); - - // - // Install SiPreMemPolicyPpi. - // While installed, RC assumes the Policy is ready and finalized. So please - // update and override any setting before calling this function. - // - Status = SiPreMemInstallPolicyPpi (SiPreMemPolicyPpi); - ASSERT_EFI_ERROR (Status); - - - DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in Pre-Memory\n")); -} diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiSiPolicyInit.h b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiSiPolicyInit.h deleted file mode 100644 index 4f4a80b9ae..0000000000 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiSiPolicyInit.h +++ /dev/null @@ -1,24 +0,0 @@ -/** @file - Header file for the PeiSiPolicyInit - -Copyright (c) 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#ifndef _SI_POLICY_INIT_PEI_H_ -#define _SI_POLICY_INIT_PEI_H_ - -#include -#include -#include -#include -#include - -#endif // _SI_POLICY_INIT_PEI_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.c new file mode 100644 index 0000000000..c3a96e5ad2 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.c @@ -0,0 +1,93 @@ +/** @file + This file is SampleCode for Intel PEI Platform Policy initialization. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "PeiPolicyInit.h" + +/** + Performs silicon post-mem policy initialization. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a PPI, etc. + + The returned data must be used as input data for SiliconPolicyDonePostMem(), + and SiliconPolicyUpdateLib.SiliconPolicyUpdatePostMem(). + + 1) In FSP path, the input Policy should be FspsUpd. + Value of FspsUpd has been initialized by FSP binary default value. + Only a subset of FspsUpd needs to be updated for different silicon sku. + The return data is same FspsUpd. + + 2) In non-FSP path, the input policy could be NULL. + The return data is the initialized policy. + + @param[in, out] Policy Pointer to policy. + + @return the initialized policy. +**/ +VOID * +EFIAPI +SiliconPolicyInitPostMem ( + IN OUT VOID *Policy + ) +{ + EFI_STATUS Status; + SI_POLICY_PPI *SiPolicyPpi; + + DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Start in Post-Memory...\n")); + + ASSERT (Policy == NULL); + + // + // Call SiCreateConfigBlocks to initialize Silicon Policy structure + // and get all Intel default policy settings. + // + Status = SiCreateConfigBlocks (&SiPolicyPpi); + ASSERT_EFI_ERROR (Status); + + return SiPolicyPpi; +} + +/* + The silicon post-mem policy is finalized. + Silicon code can do initialization based upon the policy data. + + The input Policy must be returned by SiliconPolicyInitPostMem(). + + @param[in] Policy Pointer to policy. + + @retval EFI_SUCCESS The policy is handled consumed by silicon code. +*/ +EFI_STATUS +EFIAPI +SiliconPolicyDonePostMem ( + IN VOID *Policy + ) +{ + EFI_STATUS Status; + SI_POLICY_PPI *SiPolicyPpi; + + SiPolicyPpi = Policy; + + // + // Install SiPolicyPpi. + // While installed, RC assumes the Policy is ready and finalized. So please + // update and override any setting before calling this function. + // + Status = SiInstallPolicyPpi (SiPolicyPpi); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in Post-Memory\n")); + + return Status; +} diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.h b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.h new file mode 100644 index 0000000000..e85724411a --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInit.h @@ -0,0 +1,24 @@ +/** @file + Header file for the PolicyInitPei PEIM. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PEI_POLICY_INIT_H_ +#define _PEI_POLICY_INIT_H_ + +#include +#include +#include + +#include "PeiSiPolicyInit.h" + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c new file mode 100644 index 0000000000..c402dee3a4 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c @@ -0,0 +1,93 @@ +/** @file + This file is SampleCode for Intel PEI Platform Policy initialization. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "PeiPolicyInit.h" + +/** + Performs silicon pre-mem policy initialization. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a PPI, etc. + + The returned data must be used as input data for SiliconPolicyDonePreMem(), + and SiliconPolicyUpdateLib.SiliconPolicyUpdatePreMem(). + + 1) In FSP path, the input Policy should be FspmUpd. + Value of FspmUpd has been initialized by FSP binary default value. + Only a subset of FspmUpd needs to be updated for different silicon sku. + The return data is same FspmUpd. + + 2) In non-FSP path, the input policy could be NULL. + The return data is the initialized policy. + + @param[in, out] Policy Pointer to policy. + + @return the initialized policy. +**/ +VOID * +EFIAPI +SiliconPolicyInitPreMem ( + IN OUT VOID *Policy + ) +{ + EFI_STATUS Status; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + + DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Start in Pre-Memory...\n")); + + ASSERT (Policy == NULL); + + // + // Call SiCreatePreMemConfigBlocks to initialize platform policy structure + // and get all intel default policy settings. + // + Status = SiCreatePreMemConfigBlocks (&SiPreMemPolicyPpi); + ASSERT_EFI_ERROR (Status); + + return SiPreMemPolicyPpi; +} + +/* + The silicon pre-mem policy is finalized. + Silicon code can do initialization based upon the policy data. + + The input Policy must be returned by SiliconPolicyInitPreMem(). + + @param[in] Policy Pointer to policy. + + @retval EFI_SUCCESS The policy is handled consumed by silicon code. +*/ +EFI_STATUS +EFIAPI +SiliconPolicyDonePreMem ( + IN VOID *Policy + ) +{ + EFI_STATUS Status; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + + SiPreMemPolicyPpi = Policy; + + // + // Install SiPreMemPolicyPpi. + // While installed, RC assumes the Policy is ready and finalized. So please + // update and override any setting before calling this function. + // + Status = SiPreMemInstallPolicyPpi (SiPreMemPolicyPpi); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in Pre-Memory\n")); + + return Status; +} diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSiPolicyInit.h b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSiPolicyInit.h new file mode 100644 index 0000000000..4f4a80b9ae --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSiPolicyInit.h @@ -0,0 +1,24 @@ +/** @file + Header file for the PeiSiPolicyInit + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SI_POLICY_INIT_PEI_H_ +#define _SI_POLICY_INIT_PEI_H_ + +#include +#include +#include +#include +#include + +#endif // _SI_POLICY_INIT_PEI_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSiliconPolicyInitLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSiliconPolicyInitLib.inf new file mode 100644 index 0000000000..ac37f17eae --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSiliconPolicyInitLib.inf @@ -0,0 +1,61 @@ +### @file +# Library functions for Policy Initialization Library. +# +# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiSiliconPolicyInitLib + FILE_GUID = 80920B16-7778-4793-878E-4555F68BDC69 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = SiliconPolicyInitLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 +# + +################################################################################ +# +# Sources Section - list of files that are required for the build to succeed. +# +################################################################################ + +[Sources] + PeiPolicyInitPreMem.c + PeiPolicyInit.c + PeiPolicyInit.h + +################################################################################ +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +################################################################################ + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + KabylakeSiliconPkg/SiPkg.dec + +[LibraryClasses] + SiPolicyLib + DebugLib + PeiServicesLib diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspCpuPolicyInitLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspCpuPolicyInitLib.c new file mode 100644 index 0000000000..282f774831 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspCpuPolicyInitLib.c @@ -0,0 +1,366 @@ +/** @file + Implementation of Fsp PCH Policy Initialization. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +/** + Performs FSP CPU PEI Policy initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspCpuPolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + EFI_STATUS Status; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + CPU_OVERCLOCKING_PREMEM_CONFIG *CpuOverClockingPreMemConfig; + CPU_CONFIG_LIB_PREMEM_CONFIG *CpuConfigLibPreMemConfig; + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SiCpuPolicy Pre-Mem Start\n")); + + // + // Locate SiPreMemPolicyPpi + // + SiPreMemPolicyPpi = NULL; + Status = PeiServicesLocatePpi ( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPreMemPolicyPpi + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuOverclockingPreMemConfigGuid, (VOID *) &CpuOverClockingPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuConfigLibPreMemConfigGuid, (VOID *) &CpuConfigLibPreMemConfig); + ASSERT_EFI_ERROR (Status); + /// + ///Test RC Policies + /// + + /// + /// + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SiCpuPolicy Pre-Mem End\n")); + + // + // Overclocking PreMem policies + // + FspmUpd->FspmConfig.OcSupport = (UINT8) CpuOverClockingPreMemConfig->OcSupport; + FspmUpd->FspmConfig.OcLock = (UINT8) CpuOverClockingPreMemConfig->OcLock; + FspmUpd->FspmConfig.CoreMaxOcRatio = (UINT8) CpuOverClockingPreMemConfig->CoreMaxOcRatio; + FspmUpd->FspmConfig.CoreVoltageMode = (UINT8) CpuOverClockingPreMemConfig->CoreVoltageMode; + FspmUpd->FspmConfig.RingMinOcRatio = (UINT8) CpuOverClockingPreMemConfig->RingMinOcRatio; + FspmUpd->FspmConfig.RingMaxOcRatio = (UINT8) CpuOverClockingPreMemConfig->RingMaxOcRatio; + FspmUpd->FspmConfig.CoreVoltageOverride = (UINT16) CpuOverClockingPreMemConfig->CoreVoltageOverride; + FspmUpd->FspmConfig.CoreVoltageAdaptive = (UINT16) CpuOverClockingPreMemConfig->CoreVoltageAdaptive; + FspmUpd->FspmConfig.CoreVoltageOffset = (UINT16) CpuOverClockingPreMemConfig->CoreVoltageOffset; + FspmUpd->FspmConfig.CorePllVoltageOffset = (UINT8) CpuOverClockingPreMemConfig->CorePllVoltageOffset; + FspmUpd->FspmConfig.GtPllVoltageOffset = (UINT8) CpuOverClockingPreMemConfig->GtPllVoltageOffset; + FspmUpd->FspmConfig.RingPllVoltageOffset = (UINT8) CpuOverClockingPreMemConfig->RingPllVoltageOffset; + FspmUpd->FspmConfig.SaPllVoltageOffset = (UINT8) CpuOverClockingPreMemConfig->SaPllVoltageOffset; + FspmUpd->FspmConfig.McPllVoltageOffset = (UINT8) CpuOverClockingPreMemConfig->McPllVoltageOffset; + FspmUpd->FspmConfig.Avx2RatioOffset = (UINT8) CpuOverClockingPreMemConfig->Avx2RatioOffset; + FspmUpd->FspmConfig.BclkAdaptiveVoltage = (UINT8) CpuOverClockingPreMemConfig->BclkAdaptiveVoltage; + + // + // Cpu Config Lib policies + // + FspmUpd->FspmConfig.HyperThreading = (UINT8) CpuConfigLibPreMemConfig->HyperThreading; + FspmUpd->FspmConfig.BootFrequency = (UINT8) CpuConfigLibPreMemConfig->BootFrequency; + FspmUpd->FspmConfig.ActiveCoreCount = (UINT8) CpuConfigLibPreMemConfig->ActiveCoreCount; + FspmUpd->FspmConfig.JtagC10PowerGateDisable = (UINT8) CpuConfigLibPreMemConfig->JtagC10PowerGateDisable; + FspmUpd->FspmConfig.FClkFrequency = (UINT8) CpuConfigLibPreMemConfig->FClkFrequency; + FspmUpd->FspmConfig.BistOnReset = (UINT8) CpuConfigLibPreMemConfig->BistOnReset; + FspmUpd->FspmConfig.VmxEnable = (UINT8) CpuConfigLibPreMemConfig->VmxEnable; + FspmUpd->FspmConfig.CpuRatioOverride = (UINT8) CpuConfigLibPreMemConfig->CpuRatioOverride; + FspmUpd->FspmConfig.CpuRatio = (UINT8) CpuConfigLibPreMemConfig->CpuRatio; + FspmUpd->FspmConfig.PeciSxReset = (UINT8) CpuConfigLibPreMemConfig->PeciSxReset; + FspmUpd->FspmConfig.PeciC10Reset = (UINT8) CpuConfigLibPreMemConfig->PeciC10Reset; + + return EFI_SUCCESS; +} + +/** + This routine is used to search SMRAM and get SmramCpuData point. + + @retval SmramCpuData - The pointer of CPU information in SMRAM. + @retval NULL - Unable to find the CPU information. + **/ + +STATIC +SMRAM_CPU_DATA * +GetSmmCpuData( + VOID + ) +{ + UINT32 Address; + SMRAM_CPU_DATA *SmramCpuData; + EFI_PEI_HOB_POINTERS Hob; + EFI_STATUS Status; + UINT32 TsegBase = 0; + UINT32 TsegSize = 0; + + // + // Find TSEG Base using Fsp Resource Descriptor + // + + Status = PeiServicesGetHobList ((VOID **) &Hob.Raw); + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) + && (Hob.ResourceDescriptor->PhysicalStart >= BASE_1MB) + && (Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor->ResourceLength <= BASE_4GB) + && (CompareGuid (&Hob.ResourceDescriptor->Owner, &gFspReservedMemoryResourceHobTsegGuid))) { + + TsegBase = (UINT32)Hob.ResourceDescriptor->PhysicalStart; + TsegSize = (UINT32)Hob.ResourceDescriptor->ResourceLength; + DEBUG((DEBUG_INFO, "Found gFspReservedMemoryResourceHobTsegGuid\n")); + break; + } + } + Hob.Raw = GET_NEXT_HOB (Hob); + } + + + /// + /// Search SMRAM on page alignment for the SMMNVS signature + /// + if(TsegBase && TsegSize ){ + for (Address = (TsegBase + TsegSize - EFI_PAGE_SIZE); Address >= TsegBase; Address -= EFI_PAGE_SIZE ) { + SmramCpuData = (SMRAM_CPU_DATA *) (UINTN) Address; + if (CompareGuid(&SmramCpuData->HeaderGuid, &gSmramCpuDataHeaderGuid)) { + return SmramCpuData; + } + } + } + + DEBUG((DEBUG_WARN, "SmramCpuData not found\n")); + return NULL; +} + +/** + Performs FSP CPU PEI Policy post memory initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspCpuPolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ) +{ + EFI_STATUS Status; + SI_POLICY_PPI *SiPolicyPpi; + CPU_CONFIG *CpuConfig; + CPU_POWER_MGMT_BASIC_CONFIG *CpuPowerMgmtBasicConfig; + CPU_POWER_MGMT_CUSTOM_CONFIG *CpuPowerMgmtCustomConfig; + CPU_TEST_CONFIG *CpuTestConfig; + CPU_POWER_MGMT_TEST_CONFIG *CpuPowerMgmtTestConfig; + UINTN Index; + SMRAM_CPU_DATA *SmramCpuData; + UINT32 S3BspMtrrTablePointer; + UINT32 CpuS3ResumeDataPointer; + EFI_BOOT_MODE BootMode; + + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SiCpuPolicy\n")); + // + // Locate gSiPolicyPpiGuid + // + SiPolicyPpi = NULL; + Status = PeiServicesLocatePpi ( + &gSiPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPolicyPpi + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuConfigGuid, (VOID *) &CpuConfig); + ASSERT_EFI_ERROR (Status); + + Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtBasicConfigGuid, (VOID *) &CpuPowerMgmtBasicConfig); + ASSERT_EFI_ERROR (Status); + + Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtCustomConfigGuid, (VOID *) &CpuPowerMgmtCustomConfig); + ASSERT_EFI_ERROR (Status); + + Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuTestConfigGuid, (VOID *) &CpuTestConfig); + ASSERT_EFI_ERROR (Status); + + Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtTestConfigGuid, (VOID *) &CpuPowerMgmtTestConfig); + ASSERT_EFI_ERROR (Status); + // + // Production RC Policies + // + + CopyMem ((VOID *)&(FspsUpd->FspsConfig.CpuConfig), (VOID *)&(((CPU_CONFIG_UNION *)CpuConfig)->CpuConfigFsp.Data), sizeof (UINT32)); + FspsUpd->FspsConfig.MicrocodePatchAddress = CpuConfig->MicrocodePatchAddress; + + FspsUpd->FspsConfig.TurboMode = (UINT8) CpuPowerMgmtBasicConfig->TurboMode; + + /// + ///Test RC Policies + /// + FspsUpd->FspsTestConfig.MlcStreamerPrefetcher = (UINT8) CpuTestConfig->MlcStreamerPrefetcher; + FspsUpd->FspsTestConfig.MlcSpatialPrefetcher = (UINT8) CpuTestConfig->MlcSpatialPrefetcher; + FspsUpd->FspsTestConfig.MonitorMwaitEnable = (UINT8) CpuTestConfig->MonitorMwaitEnable; + FspsUpd->FspsTestConfig.DebugInterfaceEnable = (UINT8) CpuTestConfig->DebugInterfaceEnable; + FspsUpd->FspsTestConfig.DebugInterfaceLockEnable = (UINT8) CpuTestConfig->DebugInterfaceLockEnable; + FspsUpd->FspsTestConfig.ApIdleManner = (UINT8) CpuTestConfig->ApIdleManner; + FspsUpd->FspsTestConfig.ApHandoffManner = (UINT8) CpuTestConfig->ApHandoffManner; + FspsUpd->FspsTestConfig.ProcTraceOutputScheme = (UINT8) CpuTestConfig->ProcTraceOutputScheme; + FspsUpd->FspsTestConfig.ProcTraceEnable = (UINT8) CpuTestConfig->ProcTraceEnable; + FspsUpd->FspsTestConfig.ProcTraceMemSize = (UINT8) CpuTestConfig->ProcTraceMemSize; + FspsUpd->FspsTestConfig.VoltageOptimization = (UINT8) CpuTestConfig->VoltageOptimization; + + + FspsUpd->FspsTestConfig.OneCoreRatioLimit = (UINT8) CpuPowerMgmtBasicConfig->OneCoreRatioLimit; + FspsUpd->FspsTestConfig.TwoCoreRatioLimit = (UINT8) CpuPowerMgmtBasicConfig->TwoCoreRatioLimit; + FspsUpd->FspsTestConfig.ThreeCoreRatioLimit = (UINT8) CpuPowerMgmtBasicConfig->ThreeCoreRatioLimit; + FspsUpd->FspsTestConfig.FourCoreRatioLimit = (UINT8) CpuPowerMgmtBasicConfig->FourCoreRatioLimit; + FspsUpd->FspsTestConfig.FiveCoreRatioLimit = (UINT8) CpuPowerMgmtBasicConfig->FiveCoreRatioLimit; + FspsUpd->FspsTestConfig.SixCoreRatioLimit = (UINT8) CpuPowerMgmtBasicConfig->SixCoreRatioLimit; + FspsUpd->FspsTestConfig.SevenCoreRatioLimit = (UINT8) CpuPowerMgmtBasicConfig->SevenCoreRatioLimit; + FspsUpd->FspsTestConfig.EightCoreRatioLimit = (UINT8) CpuPowerMgmtBasicConfig->EightCoreRatioLimit; + FspsUpd->FspsTestConfig.Hwp = (UINT8) CpuPowerMgmtBasicConfig->Hwp; + FspsUpd->FspsTestConfig.HdcControl = (UINT8) CpuPowerMgmtBasicConfig->HdcControl; + FspsUpd->FspsTestConfig.PowerLimit1Time = (UINT8) CpuPowerMgmtBasicConfig->PowerLimit1Time; + FspsUpd->FspsTestConfig.PowerLimit2 = (UINT8) CpuPowerMgmtBasicConfig->PowerLimit2; + FspsUpd->FspsTestConfig.TurboPowerLimitLock = (UINT8) CpuPowerMgmtBasicConfig->TurboPowerLimitLock; + FspsUpd->FspsTestConfig.PowerLimit3Time = (UINT8) CpuPowerMgmtBasicConfig->PowerLimit3Time; + FspsUpd->FspsTestConfig.PowerLimit3DutyCycle = (UINT8) CpuPowerMgmtBasicConfig->PowerLimit3DutyCycle; + FspsUpd->FspsTestConfig.PowerLimit3Lock = (UINT8) CpuPowerMgmtBasicConfig->PowerLimit3Lock; + FspsUpd->FspsTestConfig.PowerLimit4Lock = (UINT8) CpuPowerMgmtBasicConfig->PowerLimit4Lock; + FspsUpd->FspsTestConfig.TccActivationOffset = (UINT8) CpuPowerMgmtBasicConfig->TccActivationOffset; + FspsUpd->FspsTestConfig.TccOffsetClamp = (UINT8) CpuPowerMgmtBasicConfig->TccOffsetClamp; + FspsUpd->FspsTestConfig.TccOffsetLock = (UINT8) CpuPowerMgmtBasicConfig->TccOffsetLock; + FspsUpd->FspsTestConfig.PowerLimit1 = (UINT32) (CpuPowerMgmtBasicConfig->PowerLimit1 * 125); + FspsUpd->FspsTestConfig.PowerLimit2Power = (UINT32) (CpuPowerMgmtBasicConfig->PowerLimit2Power * 125); + FspsUpd->FspsTestConfig.PowerLimit3 = (UINT32) (CpuPowerMgmtBasicConfig->PowerLimit3 * 125); + FspsUpd->FspsTestConfig.PowerLimit4 = (UINT32) (CpuPowerMgmtBasicConfig->PowerLimit4 * 125); + FspsUpd->FspsTestConfig.TccOffsetTimeWindowForRatl = (UINT32) CpuPowerMgmtBasicConfig->TccOffsetTimeWindowForRatl; + + FspsUpd->FspsTestConfig.NumberOfEntries = (UINT8) CpuPowerMgmtCustomConfig->CustomRatioTable.NumberOfEntries; + FspsUpd->FspsTestConfig.Custom1PowerLimit1Time = (UINT8) CpuPowerMgmtCustomConfig->CustomConfigTdpTable[0].CustomPowerLimit1Time; + FspsUpd->FspsTestConfig.Custom2PowerLimit1Time = (UINT8) CpuPowerMgmtCustomConfig->CustomConfigTdpTable[1].CustomPowerLimit1Time; + FspsUpd->FspsTestConfig.Custom3PowerLimit1Time = (UINT8) CpuPowerMgmtCustomConfig->CustomConfigTdpTable[2].CustomPowerLimit1Time; + FspsUpd->FspsTestConfig.Custom1TurboActivationRatio = (UINT8) CpuPowerMgmtCustomConfig->CustomConfigTdpTable[0].CustomTurboActivationRatio; + FspsUpd->FspsTestConfig.Custom2TurboActivationRatio = (UINT8) CpuPowerMgmtCustomConfig->CustomConfigTdpTable[1].CustomTurboActivationRatio; + FspsUpd->FspsTestConfig.Custom3TurboActivationRatio = (UINT8) CpuPowerMgmtCustomConfig->CustomConfigTdpTable[2].CustomTurboActivationRatio; + FspsUpd->FspsTestConfig.ConfigTdpLock = (UINT8) CpuPowerMgmtCustomConfig->ConfigTdpLock; + FspsUpd->FspsTestConfig.ConfigTdpBios = (UINT8) CpuPowerMgmtCustomConfig->ConfigTdpBios; + FspsUpd->FspsTestConfig.MaxRatio = (UINT16) CpuPowerMgmtCustomConfig->CustomRatioTable.MaxRatio; + for (Index = 0; Index < CpuPowerMgmtCustomConfig->CustomRatioTable.NumberOfEntries; Index++) { + FspsUpd->FspsTestConfig.StateRatio[Index] = (UINT16) CpuPowerMgmtCustomConfig->CustomRatioTable.StateRatio[Index]; + } + FspsUpd->FspsTestConfig.Custom1PowerLimit1 = (UINT32) (CpuPowerMgmtCustomConfig->CustomConfigTdpTable[0].CustomPowerLimit1 * 125); + FspsUpd->FspsTestConfig.Custom1PowerLimit2 = (UINT32) (CpuPowerMgmtCustomConfig->CustomConfigTdpTable[0].CustomPowerLimit2 * 125); + FspsUpd->FspsTestConfig.Custom2PowerLimit1 = (UINT32) (CpuPowerMgmtCustomConfig->CustomConfigTdpTable[1].CustomPowerLimit1 * 125); + FspsUpd->FspsTestConfig.Custom2PowerLimit2 = (UINT32) (CpuPowerMgmtCustomConfig->CustomConfigTdpTable[1].CustomPowerLimit2 * 125); + FspsUpd->FspsTestConfig.Custom3PowerLimit1 = (UINT32) (CpuPowerMgmtCustomConfig->CustomConfigTdpTable[2].CustomPowerLimit1 * 125); + FspsUpd->FspsTestConfig.Custom3PowerLimit2 = (UINT32) (CpuPowerMgmtCustomConfig->CustomConfigTdpTable[2].CustomPowerLimit2 * 125); + + FspsUpd->FspsTestConfig.Eist = (UINT8) CpuPowerMgmtTestConfig->Eist; + FspsUpd->FspsTestConfig.EnergyEfficientPState = (UINT8) CpuPowerMgmtTestConfig->EnergyEfficientPState; + FspsUpd->FspsTestConfig.EnergyEfficientTurbo = (UINT8) CpuPowerMgmtTestConfig->EnergyEfficientTurbo; + FspsUpd->FspsTestConfig.TStates = (UINT8) CpuPowerMgmtTestConfig->TStates; + FspsUpd->FspsTestConfig.BiProcHot = (UINT8) CpuPowerMgmtTestConfig->BiProcHot; + FspsUpd->FspsTestConfig.DisableProcHotOut = (UINT8) CpuPowerMgmtTestConfig->DisableProcHotOut; + FspsUpd->FspsTestConfig.ProcHotResponse = (UINT8) CpuPowerMgmtTestConfig->ProcHotResponse; + FspsUpd->FspsTestConfig.DisableVrThermalAlert = (UINT8) CpuPowerMgmtTestConfig->DisableVrThermalAlert; + FspsUpd->FspsTestConfig.AutoThermalReporting = (UINT8) CpuPowerMgmtTestConfig->AutoThermalReporting; + FspsUpd->FspsTestConfig.ThermalMonitor = (UINT8) CpuPowerMgmtTestConfig->ThermalMonitor; + FspsUpd->FspsTestConfig.Cx = (UINT8) CpuPowerMgmtTestConfig->Cx; + FspsUpd->FspsTestConfig.PmgCstCfgCtrlLock = (UINT8) CpuPowerMgmtTestConfig->PmgCstCfgCtrlLock; + FspsUpd->FspsTestConfig.C1e = (UINT8) CpuPowerMgmtTestConfig->C1e; + FspsUpd->FspsTestConfig.PkgCStateDemotion = (UINT8) CpuPowerMgmtTestConfig->PkgCStateDemotion; + FspsUpd->FspsTestConfig.PkgCStateUnDemotion = (UINT8) CpuPowerMgmtTestConfig->PkgCStateUnDemotion; + FspsUpd->FspsTestConfig.CStatePreWake = (UINT8) CpuPowerMgmtTestConfig->CStatePreWake; + FspsUpd->FspsTestConfig.TimedMwait = (UINT8) CpuPowerMgmtTestConfig->TimedMwait; + FspsUpd->FspsTestConfig.CstCfgCtrIoMwaitRedirection = (UINT8) CpuPowerMgmtTestConfig->CstCfgCtrIoMwaitRedirection; + FspsUpd->FspsTestConfig.PkgCStateLimit = (UINT8) CpuPowerMgmtTestConfig->PkgCStateLimit; + FspsUpd->FspsTestConfig.CstateLatencyControl0TimeUnit = (UINT8) CpuPowerMgmtTestConfig->CstateLatencyControl0TimeUnit; + FspsUpd->FspsTestConfig.CstateLatencyControl1TimeUnit = (UINT8) CpuPowerMgmtTestConfig->CstateLatencyControl1TimeUnit; + FspsUpd->FspsTestConfig.CstateLatencyControl2TimeUnit = (UINT8) CpuPowerMgmtTestConfig->CstateLatencyControl2TimeUnit; + FspsUpd->FspsTestConfig.CstateLatencyControl3TimeUnit = (UINT8) CpuPowerMgmtTestConfig->CstateLatencyControl3TimeUnit; + FspsUpd->FspsTestConfig.CstateLatencyControl4TimeUnit = (UINT8) CpuPowerMgmtTestConfig->CstateLatencyControl4TimeUnit; + FspsUpd->FspsTestConfig.CstateLatencyControl5TimeUnit = (UINT8) CpuPowerMgmtTestConfig->CstateLatencyControl5TimeUnit; + FspsUpd->FspsTestConfig.PpmIrmSetting = (UINT8) CpuPowerMgmtTestConfig->PpmIrmSetting; + FspsUpd->FspsTestConfig.ProcHotLock = (UINT8) CpuPowerMgmtTestConfig->ProcHotLock; + FspsUpd->FspsTestConfig.RaceToHalt = (UINT8) CpuPowerMgmtTestConfig->RaceToHalt; + FspsUpd->FspsTestConfig.ConfigTdpLevel = (UINT8) CpuPowerMgmtTestConfig->ConfigTdpLevel; + FspsUpd->FspsTestConfig.CstateLatencyControl0Irtl = (UINT16) CpuPowerMgmtTestConfig->CstateLatencyControl0Irtl; + FspsUpd->FspsTestConfig.CstateLatencyControl1Irtl = (UINT16) CpuPowerMgmtTestConfig->CstateLatencyControl1Irtl; + FspsUpd->FspsTestConfig.CstateLatencyControl2Irtl = (UINT16) CpuPowerMgmtTestConfig->CstateLatencyControl2Irtl; + FspsUpd->FspsTestConfig.CstateLatencyControl3Irtl = (UINT16) CpuPowerMgmtTestConfig->CstateLatencyControl3Irtl; + FspsUpd->FspsTestConfig.CstateLatencyControl4Irtl = (UINT16) CpuPowerMgmtTestConfig->CstateLatencyControl4Irtl; + FspsUpd->FspsTestConfig.CstateLatencyControl5Irtl = (UINT16) CpuPowerMgmtTestConfig->CstateLatencyControl5Irtl; + + Status = PeiServicesGetBootMode(&BootMode); + if ((Status == EFI_SUCCESS) && (BootMode == BOOT_ON_S3_RESUME)) { + SmramCpuData = GetSmmCpuData(); + if (SmramCpuData != NULL) { + S3BspMtrrTablePointer = (UINT32) AllocateZeroPool(SmramCpuData->S3BspMtrrTableSize); //Add Null terminator + FspsUpd->FspsConfig.CpuS3ResumeMtrrData = S3BspMtrrTablePointer; + FspsUpd->FspsConfig.CpuS3ResumeMtrrDataSize = (UINT16) SmramCpuData->S3BspMtrrTableSize; + // + // Copy BSP MTRR table to UPD. + // + CopyMem((VOID*) S3BspMtrrTablePointer, + (UINT8 *) SmramCpuData + SmramCpuData->S3BspMtrrTableOffset, + SmramCpuData->S3BspMtrrTableSize); + + CpuS3ResumeDataPointer = (UINT32) AllocateZeroPool(SmramCpuData->CpuPrivateDataSize); + FspsUpd->FspsTestConfig.CpuS3ResumeData = CpuS3ResumeDataPointer; + FspsUpd->FspsTestConfig.CpuS3ResumeDataSize = (UINT16) SmramCpuData->CpuPrivateDataSize; + // + // Copy CPU_PRIVATE_DATA to UPD. + // + CopyMem((VOID*) CpuS3ResumeDataPointer, + (UINT8 *) SmramCpuData + SmramCpuData->CpuPrivateDataOffset, + SmramCpuData->CpuPrivateDataSize); + } else { + //@todo Check if an assert can be handled cleanly + DEBUG((DEBUG_WARN, "Unable to initialize S3 data\n")); + } + + } + /// + /// + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspMePolicyInitLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspMePolicyInitLib.c new file mode 100644 index 0000000000..d97bf8be57 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspMePolicyInitLib.c @@ -0,0 +1,129 @@ +/** @file + Implementation of Fsp Me Policy Initialization. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include + +#include + +/** + Performs FSP ME PEI Policy pre mem initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspMePolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + EFI_STATUS Status; + SI_PREMEM_POLICY_PPI *SiPreMemPolicy; + ME_PEI_PREMEM_CONFIG *MePeiPreMemConfig; + + DEBUG ((DEBUG_INFO, "PeiFspMePolicyInitPreMem\n")); + + // + // Locate gSiPreMemPolicyPpi + // + SiPreMemPolicy = NULL; + Status = PeiServicesLocatePpi ( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPreMemPolicy + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gMePeiPreMemConfigGuid, (VOID *) &MePeiPreMemConfig); + ASSERT_EFI_ERROR (Status); + + FspmUpd->FspmConfig.HeciTimeouts = (UINT8) MePeiPreMemConfig->HeciTimeouts; + + // + // Test policies + // + FspmUpd->FspmTestConfig.DidInitStat = (UINT8) MePeiPreMemConfig->DidInitStat; + FspmUpd->FspmTestConfig.DisableCpuReplacedPolling = (UINT8) MePeiPreMemConfig->DisableCpuReplacedPolling; + FspmUpd->FspmTestConfig.SendDidMsg = (UINT8) MePeiPreMemConfig->SendDidMsg; + FspmUpd->FspmTestConfig.DisableHeciRetry = (UINT8) MePeiPreMemConfig->DisableHeciRetry; + FspmUpd->FspmTestConfig.DisableMessageCheck = (UINT8) MePeiPreMemConfig->DisableMessageCheck; + FspmUpd->FspmTestConfig.SkipMbpHob = (UINT8) MePeiPreMemConfig->SkipMbpHob; + + FspmUpd->FspmTestConfig.HeciCommunication2 = (UINT8) MePeiPreMemConfig->HeciCommunication2; + FspmUpd->FspmTestConfig.KtDeviceEnable = (UINT8) MePeiPreMemConfig->KtDeviceEnable; + FspmUpd->FspmTestConfig.IderDeviceEnable = (UINT8) MePeiPreMemConfig->IderDeviceEnable; + + + FspmUpd->FspmConfig.Heci1BarAddress = MePeiPreMemConfig->Heci1BarAddress; + FspmUpd->FspmConfig.Heci2BarAddress = MePeiPreMemConfig->Heci2BarAddress; + FspmUpd->FspmConfig.Heci3BarAddress = MePeiPreMemConfig->Heci3BarAddress; + + return EFI_SUCCESS; +} + +/** + Performs FSP ME PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspMePolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ) +{ + EFI_STATUS Status; + SI_POLICY_PPI *SiPolicyPpi; + ME_PEI_CONFIG *MePeiConfig; + + DEBUG ((DEBUG_INFO, "PeiFspMePolicyInit \n")); + // + // Locate gSiPolicyPpiGuid + // + SiPolicyPpi = NULL; + Status = PeiServicesLocatePpi ( + &gSiPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPolicyPpi + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gMePeiConfigGuid, (VOID *) &MePeiConfig); + ASSERT_EFI_ERROR (Status); + + FspsUpd->FspsConfig.Heci3Enabled = (UINT8) MePeiConfig->Heci3Enabled; + FspsUpd->FspsConfig.MeUnconfigOnRtcClear = (UINT8) MePeiConfig->MeUnconfigOnRtcClear; + FspsUpd->FspsConfig.MeUnconfigIsValid = (UINT8) MePeiConfig->MeUnconfigIsValid; + + // + // Test policies + // + FspsUpd->FspsTestConfig.EndOfPostMessage = (UINT8) MePeiConfig->EndOfPostMessage; + FspsUpd->FspsTestConfig.DisableD0I3SettingForHeci = (UINT8) MePeiConfig->DisableD0I3SettingForHeci; + + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspMiscUpdInitLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspMiscUpdInitLib.c new file mode 100644 index 0000000000..b9329e4c8a --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspMiscUpdInitLib.c @@ -0,0 +1,56 @@ +/** @file + Implementation of Fsp Misc UPD Initialization. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include + +#include +#include +#include +#include + +/** + Performs FSP Misc UPD initialization. + + @param[in][out] FspmUpd Pointer to FSPM_UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. +**/ +EFI_STATUS +EFIAPI +PeiFspMiscUpdInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + EFI_STATUS Status; + + // + // Locate system configuration variable + // + FspmUpd->FspmArchUpd.StackBase = (VOID *)(UINTN)(PcdGet32(PcdTemporaryRamBase) + PcdGet32(PcdTemporaryRamSize) - (PcdGet32(PcdFspTemporaryRamSize) + PcdGet32(PcdFspReservedBufferSize))); + FspmUpd->FspmArchUpd.StackSize = PcdGet32(PcdFspTemporaryRamSize); + + Status = PeiServicesGetBootMode (&(FspmUpd->FspmArchUpd.BootMode)); + if (EFI_ERROR (Status)) { + FspmUpd->FspmArchUpd.BootMode = BOOT_WITH_FULL_CONFIGURATION; + } + + FspmUpd->FspmArchUpd.BootLoaderTolumSize = 0x0; + + // + // Initialize S3 Data variable (S3DataPtr). It may be used for warm and fast boot paths. + // + FspmUpd->FspmArchUpd.NvsBufferPtr = NULL; + + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspPchPolicyInitLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspPchPolicyInitLib.c new file mode 100644 index 0000000000..3f7e297c0b --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspPchPolicyInitLib.c @@ -0,0 +1,713 @@ +/** @file + Implementation of Fsp PCH Policy Initialization. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include + +#include +#include +#include + +/** + Performs FSP PCH PEI Policy pre mem initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspPchPolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + EFI_STATUS Status; + UINTN Index; + SI_PREMEM_POLICY_PPI *SiPreMemPolicy; + PCH_TRACE_HUB_PREMEM_CONFIG *TraceHubPreMemConfig; + PCH_SMBUS_PREMEM_CONFIG *SmbusPreMemConfig; + PCH_DCI_PREMEM_CONFIG *DciPreMemConfig; + PCH_HPET_PREMEM_CONFIG *HpetPreMemConfig; + PCH_HSIO_PCIE_PREMEM_CONFIG *HsioPciePreMemConfig; + PCH_HSIO_SATA_PREMEM_CONFIG *HsioSataPreMemConfig; + PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig; + PCH_HSIO_PREMEM_CONFIG *HsioPreMemConfig; + PCH_LPC_PREMEM_CONFIG *LpcPreMemConfig; + PCH_GENERAL_PREMEM_CONFIG *PchGeneralPreMemConfig; + PCH_WDT_PREMEM_CONFIG *WdtPreMemConfig; + + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP UpdatePeiPchPolicyPreMem\n")); + // + // Locate PchPreMemPolicyPpi + // + SiPreMemPolicy = NULL; + Status = PeiServicesLocatePpi ( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPreMemPolicy + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gTraceHubPreMemConfigGuid, (VOID *) &TraceHubPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gSmbusPreMemConfigGuid, (VOID *) &SmbusPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gDciPreMemConfigGuid, (VOID *) &DciPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gHpetPreMemConfigGuid, (VOID *) &HpetPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gHsioPciePreMemConfigGuid, (VOID *) &HsioPciePreMemConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gHsioSataPreMemConfigGuid, (VOID *) &HsioSataPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gHsioPreMemConfigGuid, (VOID *) &HsioPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gLpcPreMemConfigGuid, (VOID *) &LpcPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gPchGeneralPreMemConfigGuid, (VOID *) &PchGeneralPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gWatchDogPreMemConfigGuid, (VOID *) &WdtPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gPcieRpPreMemConfigGuid, (VOID *) &PcieRpPreMemConfig); + ASSERT_EFI_ERROR (Status); + // + // Update PCIE RP policies + // + FspmUpd->FspmConfig.PcieRpEnableMask = PcieRpPreMemConfig->RpEnabledMask & ((1 << KBL_PCH_H_PCIE_MAX_ROOT_PORTS) - 1); + + // + // Update TraceHub policies + // + FspmUpd->FspmConfig.EnableTraceHub = ((UINT8)TraceHubPreMemConfig->EnableMode == 0) ? 0 : 1; + FspmUpd->FspmConfig.TraceHubMemReg0Size = (UINT32)TraceHubPreMemConfig->MemReg0Size; + FspmUpd->FspmConfig.TraceHubMemReg1Size = (UINT32)TraceHubPreMemConfig->MemReg1Size; + + // + // Update Smbus policies + // + FspmUpd->FspmConfig.SmbusEnable = (UINT8)SmbusPreMemConfig->Enable; + FspmUpd->FspmConfig.SmbusArpEnable = (UINT8)SmbusPreMemConfig->ArpEnable; + FspmUpd->FspmTestConfig.SmbusDynamicPowerGating = (UINT8)SmbusPreMemConfig->DynamicPowerGating; + FspmUpd->FspmTestConfig.SmbusSpdWriteDisable = (UINT8)SmbusPreMemConfig->SpdWriteDisable; + FspmUpd->FspmConfig.PchSmbusIoBase = (UINT16)SmbusPreMemConfig->SmbusIoBase; + FspmUpd->FspmConfig.PchNumRsvdSmbusAddresses = (UINT8)SmbusPreMemConfig->NumRsvdSmbusAddresses; + FspmUpd->FspmConfig.RsvdSmbusAddressTablePtr = (UINT32)SmbusPreMemConfig->RsvdSmbusAddressTable; + + // + // Update Dci policies + // + FspmUpd->FspmTestConfig.PchDciEn = (UINT8)DciPreMemConfig->DciEn; + + // + // Update HPET policies + // + FspmUpd->FspmConfig.PchHpetEnable = (UINT8)HpetPreMemConfig->Enable; + FspmUpd->FspmConfig.PchHpetBdfValid = (UINT8)HpetPreMemConfig->BdfValid; + FspmUpd->FspmConfig.PchHpetBusNumber = (UINT8)HpetPreMemConfig->BusNumber; + FspmUpd->FspmConfig.PchHpetDeviceNumber = (UINT8)HpetPreMemConfig->DeviceNumber; + FspmUpd->FspmConfig.PchHpetFunctionNumber = (UINT8)HpetPreMemConfig->FunctionNumber; + FspmUpd->FspmConfig.PchHpetBase = (UINT32)HpetPreMemConfig->Base; + + // + // Update HSIO PCIE policies + // + FspmUpd->FspmConfig.PchPmPciePllSsc = (UINT8)HsioPciePreMemConfig->PciePllSsc; + for (Index = 0; Index < KBL_PCH_H_PCIE_MAX_ROOT_PORTS; Index ++) { + FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable; + FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle; + FspmUpd->FspmConfig.PchPcieHsioTxGen1DownscaleAmpEnable[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DownscaleAmpEnable; + FspmUpd->FspmConfig.PchPcieHsioTxGen1DownscaleAmp[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DownscaleAmp; + FspmUpd->FspmConfig.PchPcieHsioTxGen2DownscaleAmpEnable[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DownscaleAmpEnable; + FspmUpd->FspmConfig.PchPcieHsioTxGen2DownscaleAmp[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DownscaleAmp; + FspmUpd->FspmConfig.PchPcieHsioTxGen3DownscaleAmpEnable[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen3DownscaleAmpEnable; + FspmUpd->FspmConfig.PchPcieHsioTxGen3DownscaleAmp[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen3DownscaleAmp; + FspmUpd->FspmConfig.PchPcieHsioTxGen1DeEmphEnable[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DeEmphEnable; + FspmUpd->FspmConfig.PchPcieHsioTxGen1DeEmph[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DeEmph; + FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph3p5Enable[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph3p5Enable; + FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph3p5[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph3p5; + FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph6p0Enable[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph6p0Enable; + FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph6p0[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph6p0; + } + + // + // Update HSIO SATA policies + // + for (Index = 0; Index < PCH_MAX_SATA_PORTS; Index ++) { + FspmUpd->FspmConfig.PchSataHsioRxGen1EqBoostMagEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen1EqBoostMagEnable; + FspmUpd->FspmConfig.PchSataHsioRxGen1EqBoostMag[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen1EqBoostMag; + FspmUpd->FspmConfig.PchSataHsioRxGen2EqBoostMagEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen2EqBoostMagEnable; + FspmUpd->FspmConfig.PchSataHsioRxGen2EqBoostMag[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen2EqBoostMag; + FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEnable; + FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag; + FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmpEnable; + FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp; + FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmpEnable; + FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp; + FspmUpd->FspmConfig.PchSataHsioTxGen3DownscaleAmpEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DownscaleAmpEnable; + FspmUpd->FspmConfig.PchSataHsioTxGen3DownscaleAmp[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DownscaleAmp; + FspmUpd->FspmConfig.PchSataHsioTxGen1DeEmphEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DeEmphEnable; + FspmUpd->FspmConfig.PchSataHsioTxGen1DeEmph[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DeEmph; + FspmUpd->FspmConfig.PchSataHsioTxGen2DeEmphEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DeEmphEnable; + FspmUpd->FspmConfig.PchSataHsioTxGen2DeEmph[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DeEmph; + FspmUpd->FspmConfig.PchSataHsioTxGen3DeEmphEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DeEmphEnable; + FspmUpd->FspmConfig.PchSataHsioTxGen3DeEmph[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DeEmph; + } + + // + // Update HSIO policies + // + FspmUpd->FspmTestConfig.ChipsetInitMessage = (UINT8)HsioPreMemConfig->ChipsetInitMessage; + FspmUpd->FspmTestConfig.BypassPhySyncReset = (UINT8)HsioPreMemConfig->BypassPhySyncReset; + + // + // Update LPC policies + // + FspmUpd->FspmConfig.PchLpcEnhancePort8xhDecoding = (UINT8)LpcPreMemConfig->EnhancePort8xhDecoding; + + // + // Update Pch General Premem policies + // + FspmUpd->FspmConfig.PchAcpiBase = (UINT16)PchGeneralPreMemConfig->AcpiBase; + FspmUpd->FspmConfig.PchPort80Route = (UINT8)PchGeneralPreMemConfig->Port80Route; + + // + // Update Wdt policies + // + FspmUpd->FspmTestConfig.WdtDisableAndLock = (UINT8)WdtPreMemConfig->DisableAndLock; + + + return EFI_SUCCESS; +} + +/** + Performs FSP PCH PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspPchPolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ) +{ + EFI_STATUS Status; + UINTN Index; + SI_POLICY_PPI *SiPolicy; + PCH_LAN_CONFIG *LanConfig; + PCH_HDAUDIO_CONFIG *HdAudioConfig; + PCH_SCS_CONFIG *ScsConfig; + PCH_ISH_CONFIG *IshConfig; + PCH_SPI_CONFIG *SpiConfig; + PCH_SATA_CONFIG *SataConfig; + PCH_USB_CONFIG *UsbConfig; + PCH_SERIAL_IO_CONFIG *SerialIoConfig; + PCH_INTERRUPT_CONFIG *InterruptConfig; + PCH_LOCK_DOWN_CONFIG *LockDownConfig; + PCH_CIO2_CONFIG *Cio2Config; + PCH_PCIE_CONFIG *PcieRpConfig; + PCH_DMI_CONFIG *DmiConfig; + PCH_FLASH_PROTECTION_CONFIG *FlashProtectionConfig; + PCH_IOAPIC_CONFIG *IoApicConfig; + PCH_P2SB_CONFIG *P2sbConfig; + PCH_GENERAL_CONFIG *PchGeneralConfig; + PCH_PM_CONFIG *PmConfig; + PCH_PORT61H_SMM_CONFIG *Port61hConfig; + PCH_LPC_SIRQ_CONFIG *PchSerialIrqConfig; + PCH_THERMAL_CONFIG *PchThermalConfig; + + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP UpdatePeiPchPolicy\n")); + // + // Locate SiPolicyPpi + // + SiPolicy = NULL; + Status = PeiServicesLocatePpi ( + &gSiPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPolicy + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + Status = GetConfigBlock ((VOID *) SiPolicy, &gLanConfigGuid, (VOID *) &LanConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPolicy, &gHdAudioConfigGuid, (VOID *) &HdAudioConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPolicy, &gScsConfigGuid, (VOID *) &ScsConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPolicy, &gIshConfigGuid, (VOID *) &IshConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPolicy, &gSpiConfigGuid, (VOID *) &SpiConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPolicy, &gSataConfigGuid, (VOID *) &SataConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPolicy, &gUsbConfigGuid, (VOID *) &UsbConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPolicy, &gSerialIoConfigGuid, (VOID *) &SerialIoConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPolicy, &gInterruptConfigGuid, (VOID *) &InterruptConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPolicy, &gLockDownConfigGuid, (VOID *) &LockDownConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPolicy, &gCio2ConfigGuid, (VOID *) &Cio2Config); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPolicy, &gPcieRpConfigGuid, (VOID *) &PcieRpConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPolicy, &gDmiConfigGuid, (VOID *) &DmiConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPolicy, &gFlashProtectionConfigGuid, (VOID *) &FlashProtectionConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPolicy, &gIoApicConfigGuid, (VOID *) &IoApicConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPolicy, &gP2sbConfigGuid, (VOID *) &P2sbConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPolicy, &gPchGeneralConfigGuid, (VOID *) &PchGeneralConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPolicy, &gPmConfigGuid, (VOID *) &PmConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPolicy, &gPort61ConfigGuid, (VOID *) &Port61hConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPolicy, &gSerialIrqConfigGuid, (VOID *) &PchSerialIrqConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPolicy, &gThermalConfigGuid, (VOID *) &PchThermalConfig); + ASSERT_EFI_ERROR (Status); + // + // Update LAN policies + // + FspsUpd->FspsConfig.PchLanEnable = (UINT8)LanConfig->Enable; + FspsUpd->FspsConfig.PchLanLtrEnable = (UINT8)LanConfig->LtrEnable; + FspsUpd->FspsConfig.PchLanK1OffEnable = (UINT8)LanConfig->K1OffEnable; + FspsUpd->FspsConfig.PchLanClkReqSupported = (UINT8)LanConfig->ClkReqSupported; + FspsUpd->FspsConfig.PchLanClkReqNumber = (UINT8)LanConfig->ClkReqNumber; + + // + // Update HDA policies + // + FspsUpd->FspsConfig.PchHdaEnable = (UINT8)HdAudioConfig->Enable; + FspsUpd->FspsConfig.PchHdaDspEnable = (UINT8)HdAudioConfig->DspEnable; + FspsUpd->FspsConfig.PchHdaIoBufferOwnership = (UINT8)HdAudioConfig->IoBufferOwnership; + + FspsUpd->FspsConfig.PchHdaPme = (UINT8)HdAudioConfig->Pme; + FspsUpd->FspsConfig.PchHdaIoBufferVoltage = (UINT8)HdAudioConfig->IoBufferVoltage; + FspsUpd->FspsConfig.PchHdaVcType = (UINT8)HdAudioConfig->VcType; + FspsUpd->FspsConfig.PchHdaLinkFrequency = (UINT8)HdAudioConfig->HdAudioLinkFrequency; + FspsUpd->FspsConfig.PchHdaIDispLinkFrequency = (UINT8)HdAudioConfig->IDispLinkFrequency; + FspsUpd->FspsConfig.PchHdaIDispLinkTmode = (UINT8)HdAudioConfig->IDispLinkTmode; + FspsUpd->FspsConfig.PchHdaDspUaaCompliance = (UINT8)HdAudioConfig->DspUaaCompliance; + FspsUpd->FspsConfig.PchHdaIDispCodecDisconnect = (UINT8)HdAudioConfig->IDispCodecDisconnect; + FspsUpd->FspsConfig.PchHdaDspEndpointDmic = (UINT8)HdAudioConfig->DspEndpointDmic; + FspsUpd->FspsConfig.PchHdaDspEndpointBluetooth = (UINT8)HdAudioConfig->DspEndpointBluetooth; + FspsUpd->FspsConfig.PchHdaDspEndpointI2s = (UINT8)HdAudioConfig->DspEndpointI2s; + FspsUpd->FspsConfig.PchHdaDspFeatureMask = (UINT32)HdAudioConfig->DspFeatureMask; + FspsUpd->FspsTestConfig.PchHdaResetWaitTimer = (UINT16)HdAudioConfig->ResetWaitTimer; + FspsUpd->FspsConfig.PchHdaVerbTableEntryNum = HdAudioConfig->VerbTableEntryNum; + FspsUpd->FspsConfig.PchHdaVerbTablePtr = HdAudioConfig->VerbTablePtr; + + // + // Update CIO2 policies + // + FspsUpd->FspsConfig.PchCio2Enable = (UINT8)Cio2Config->DeviceEnable; + FspsUpd->FspsConfig.PchSkyCamPortATermOvrEnable = (UINT8)Cio2Config->SkyCamPortATermOvrEnable; + FspsUpd->FspsConfig.PchSkyCamPortBTermOvrEnable = (UINT8)Cio2Config->SkyCamPortBTermOvrEnable; + FspsUpd->FspsConfig.PchSkyCamPortCTermOvrEnable = (UINT8)Cio2Config->SkyCamPortCTermOvrEnable; + FspsUpd->FspsConfig.PchSkyCamPortDTermOvrEnable = (UINT8)Cio2Config->SkyCamPortDTermOvrEnable; + FspsUpd->FspsConfig.PchSkyCamPortATrimEnable = (UINT8)Cio2Config->PortATrimEnable; + FspsUpd->FspsConfig.PchSkyCamPortBTrimEnable = (UINT8)Cio2Config->PortBTrimEnable; + FspsUpd->FspsConfig.PchSkyCamPortCTrimEnable = (UINT8)Cio2Config->PortCTrimEnable; + FspsUpd->FspsConfig.PchSkyCamPortDTrimEnable = (UINT8)Cio2Config->PortDTrimEnable; + FspsUpd->FspsConfig.PchSkyCamPortACtleEnable = (UINT8)Cio2Config->PortACtleEnable; + FspsUpd->FspsConfig.PchSkyCamPortBCtleEnable = (UINT8)Cio2Config->PortBCtleEnable; + FspsUpd->FspsConfig.PchSkyCamPortCDCtleEnable = (UINT8)Cio2Config->PortCDCtleEnable; + FspsUpd->FspsConfig.PchSkyCamPortACtleCapValue = (UINT8)Cio2Config->PortACtleCapValue; + FspsUpd->FspsConfig.PchSkyCamPortBCtleCapValue = (UINT8)Cio2Config->PortBCtleCapValue; + FspsUpd->FspsConfig.PchSkyCamPortCDCtleCapValue = (UINT8)Cio2Config->PortCDCtleCapValue; + FspsUpd->FspsConfig.PchSkyCamPortACtleResValue = (UINT8)Cio2Config->PortACtleResValue; + FspsUpd->FspsConfig.PchSkyCamPortBCtleResValue = (UINT8)Cio2Config->PortBCtleResValue; + FspsUpd->FspsConfig.PchSkyCamPortCDCtleResValue = (UINT8)Cio2Config->PortCDCtleResValue; + FspsUpd->FspsConfig.PchSkyCamPortAClkTrimValue = (UINT8)Cio2Config->PortAClkTrimValue; + FspsUpd->FspsConfig.PchSkyCamPortBClkTrimValue = (UINT8)Cio2Config->PortBClkTrimValue; + FspsUpd->FspsConfig.PchSkyCamPortCClkTrimValue = (UINT8)Cio2Config->PortCClkTrimValue; + FspsUpd->FspsConfig.PchSkyCamPortDClkTrimValue = (UINT8)Cio2Config->PortDClkTrimValue; + FspsUpd->FspsConfig.PchSkyCamPortADataTrimValue = (UINT16)Cio2Config->PortADataTrimValue; + FspsUpd->FspsConfig.PchSkyCamPortBDataTrimValue = (UINT16)Cio2Config->PortBDataTrimValue; + FspsUpd->FspsConfig.PchSkyCamPortCDDataTrimValue = (UINT16)Cio2Config->PortCDDataTrimValue; + + // + // Update SCS policies + // + FspsUpd->FspsConfig.ScsEmmcEnabled = (UINT8)ScsConfig->ScsEmmcEnabled; + FspsUpd->FspsConfig.ScsEmmcHs400Enabled = (UINT8)ScsConfig->ScsEmmcHs400Enabled; + FspsUpd->FspsConfig.ScsSdCardEnabled = (UINT8)ScsConfig->ScsSdSwitch == 0 ? 0 : 1; + FspsUpd->FspsConfig.PchScsEmmcHs400TuningRequired = (UINT8)ScsConfig->ScsEmmcHs400TuningRequired; + FspsUpd->FspsConfig.PchScsEmmcHs400DllDataValid = (UINT8)ScsConfig->ScsEmmcHs400DllDataValid; + FspsUpd->FspsConfig.PchScsEmmcHs400RxStrobeDll1 = (UINT8)ScsConfig->ScsEmmcHs400RxStrobeDll1; + FspsUpd->FspsConfig.PchScsEmmcHs400TxDataDll = (UINT8)ScsConfig->ScsEmmcHs400TxDataDll; + FspsUpd->FspsConfig.PchScsEmmcHs400DriverStrength = (UINT8)ScsConfig->ScsEmmcHs400DriverStrength; + + // + // Update ISH policies + // + FspsUpd->FspsConfig.PchIshEnable = (UINT8)IshConfig->Enable; + FspsUpd->FspsConfig.PchIshSpiGpioAssign = (UINT8)IshConfig->SpiGpioAssign; + FspsUpd->FspsConfig.PchIshUart0GpioAssign = (UINT8)IshConfig->Uart0GpioAssign; + FspsUpd->FspsConfig.PchIshUart1GpioAssign = (UINT8)IshConfig->Uart1GpioAssign; + FspsUpd->FspsConfig.PchIshI2c0GpioAssign = (UINT8)IshConfig->I2c0GpioAssign; + FspsUpd->FspsConfig.PchIshI2c1GpioAssign = (UINT8)IshConfig->I2c1GpioAssign; + FspsUpd->FspsConfig.PchIshI2c2GpioAssign = (UINT8)IshConfig->I2c2GpioAssign; + FspsUpd->FspsConfig.PchIshGp0GpioAssign = (UINT8)IshConfig->Gp0GpioAssign; + FspsUpd->FspsConfig.PchIshGp1GpioAssign = (UINT8)IshConfig->Gp1GpioAssign; + FspsUpd->FspsConfig.PchIshGp2GpioAssign = (UINT8)IshConfig->Gp2GpioAssign; + FspsUpd->FspsConfig.PchIshGp3GpioAssign = (UINT8)IshConfig->Gp3GpioAssign; + FspsUpd->FspsConfig.PchIshGp4GpioAssign = (UINT8)IshConfig->Gp4GpioAssign; + FspsUpd->FspsConfig.PchIshGp5GpioAssign = (UINT8)IshConfig->Gp5GpioAssign; + FspsUpd->FspsConfig.PchIshGp6GpioAssign = (UINT8)IshConfig->Gp6GpioAssign; + FspsUpd->FspsConfig.PchIshGp7GpioAssign = (UINT8)IshConfig->Gp7GpioAssign; + FspsUpd->FspsConfig.PchIshPdtUnlock = (UINT8)IshConfig->PdtUnlock; + + // + // Update SPI policies + // + FspsUpd->FspsConfig.ShowSpiController = (UINT8)SpiConfig->ShowSpiController; + + // + // Update PCIE RP RootPort policies + // + for (Index = 0; Index < KBL_PCH_H_PCIE_MAX_ROOT_PORTS; Index ++) { + FspsUpd->FspsConfig.PcieRpHotPlug[Index] = (UINT8)PcieRpConfig->RootPort[Index].HotPlug; + FspsUpd->FspsConfig.PcieRpPmSci[Index] = (UINT8)PcieRpConfig->RootPort[Index].PmSci; + FspsUpd->FspsConfig.PcieRpExtSync[Index] = (UINT8)PcieRpConfig->RootPort[Index].ExtSync; + FspsUpd->FspsConfig.PcieRpTransmitterHalfSwing[Index] = (UINT8)PcieRpConfig->RootPort[Index].TransmitterHalfSwing; + FspsUpd->FspsConfig.PcieRpClkReqSupport[Index] = (UINT8)PcieRpConfig->RootPort[Index].ClkReqSupported; + FspsUpd->FspsConfig.PcieRpClkReqNumber[Index] = (UINT8)PcieRpConfig->RootPort[Index].ClkReqNumber; + FspsUpd->FspsConfig.PcieRpClkReqDetect[Index] = (UINT8)PcieRpConfig->RootPort[Index].ClkReqDetect; + FspsUpd->FspsConfig.PcieRpAdvancedErrorReporting[Index] = (UINT8)PcieRpConfig->RootPort[Index].AdvancedErrorReporting; + FspsUpd->FspsConfig.PcieRpUnsupportedRequestReport[Index] = (UINT8)PcieRpConfig->RootPort[Index].UnsupportedRequestReport; + FspsUpd->FspsConfig.PcieRpFatalErrorReport[Index] = (UINT8)PcieRpConfig->RootPort[Index].FatalErrorReport; + FspsUpd->FspsConfig.PcieRpNoFatalErrorReport[Index] = (UINT8)PcieRpConfig->RootPort[Index].NoFatalErrorReport; + FspsUpd->FspsConfig.PcieRpCorrectableErrorReport[Index] = (UINT8)PcieRpConfig->RootPort[Index].CorrectableErrorReport; + FspsUpd->FspsConfig.PcieRpSystemErrorOnFatalError[Index] = (UINT8)PcieRpConfig->RootPort[Index].SystemErrorOnFatalError; + FspsUpd->FspsConfig.PcieRpSystemErrorOnNonFatalError[Index] = (UINT8)PcieRpConfig->RootPort[Index].SystemErrorOnNonFatalError; + FspsUpd->FspsConfig.PcieRpSystemErrorOnCorrectableError[Index] = (UINT8)PcieRpConfig->RootPort[Index].SystemErrorOnCorrectableError; + FspsUpd->FspsConfig.PcieRpMaxPayload[Index] = (UINT8)PcieRpConfig->RootPort[Index].MaxPayload; + FspsUpd->FspsConfig.PcieRpDeviceResetPadActiveHigh[Index] = (UINT8)PcieRpConfig->RootPort[Index].DeviceResetPadActiveHigh; + FspsUpd->FspsConfig.PcieRpPcieSpeed[Index] = (UINT8)PcieRpConfig->RootPort[Index].PcieSpeed; + FspsUpd->FspsConfig.PcieRpGen3EqPh3Method[Index] = (UINT8)PcieRpConfig->RootPort[Index].Gen3EqPh3Method; + FspsUpd->FspsConfig.PcieRpPhysicalSlotNumber[Index] = (UINT8)PcieRpConfig->RootPort[Index].PhysicalSlotNumber; + FspsUpd->FspsConfig.PcieRpCompletionTimeout[Index] = (UINT8)PcieRpConfig->RootPort[Index].CompletionTimeout; + FspsUpd->FspsConfig.PcieRpDeviceResetPad[Index] = (UINT32)PcieRpConfig->RootPort[Index].DeviceResetPad; + FspsUpd->FspsConfig.PcieRpAspm[Index] = (UINT8)PcieRpConfig->RootPort[Index].Aspm; + FspsUpd->FspsConfig.PcieRpL1Substates[Index] = (UINT8)PcieRpConfig->RootPort[Index].L1Substates; + FspsUpd->FspsConfig.PcieRpLtrEnable[Index] = (UINT8)PcieRpConfig->RootPort[Index].LtrEnable; + FspsUpd->FspsConfig.PcieRpLtrConfigLock[Index] = (UINT8)PcieRpConfig->RootPort[Index].LtrConfigLock; + FspsUpd->FspsTestConfig.PcieRpLtrMaxSnoopLatency[Index] = (UINT16)PcieRpConfig->RootPort[Index].LtrMaxSnoopLatency; + FspsUpd->FspsTestConfig.PcieRpLtrMaxNoSnoopLatency[Index] = (UINT16)PcieRpConfig->RootPort[Index].LtrMaxNoSnoopLatency; + + FspsUpd->FspsTestConfig.PcieRpSnoopLatencyOverrideMode[Index] = (UINT8)PcieRpConfig->RootPort[Index].SnoopLatencyOverrideMode; + FspsUpd->FspsTestConfig.PcieRpSnoopLatencyOverrideMultiplier[Index] = (UINT8)PcieRpConfig->RootPort[Index].SnoopLatencyOverrideMultiplier; + FspsUpd->FspsTestConfig.PcieRpSnoopLatencyOverrideValue[Index] = (UINT16)PcieRpConfig->RootPort[Index].SnoopLatencyOverrideValue; + + FspsUpd->FspsTestConfig.PcieRpNonSnoopLatencyOverrideMode[Index] = (UINT8)PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideMode; + FspsUpd->FspsTestConfig.PcieRpNonSnoopLatencyOverrideMultiplier[Index] = (UINT8)PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideMultiplier; + FspsUpd->FspsTestConfig.PcieRpNonSnoopLatencyOverrideValue[Index] = (UINT16)PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideValue; + + FspsUpd->FspsTestConfig.PcieRpSlotPowerLimitScale[Index] = (UINT8)PcieRpConfig->RootPort[Index].SlotPowerLimitScale; + FspsUpd->FspsTestConfig.PcieRpSlotPowerLimitValue[Index] = (UINT16)PcieRpConfig->RootPort[Index].SlotPowerLimitValue; + FspsUpd->FspsTestConfig.PcieRpUptp[Index] = (UINT8)PcieRpConfig->RootPort[Index].Uptp; + FspsUpd->FspsTestConfig.PcieRpDptp[Index] = (UINT8)PcieRpConfig->RootPort[Index].Dptp; + } + + // + // Update PCIE RP EqPh3LaneParam policies + // + for (Index = 0; Index < KBL_PCH_H_PCIE_MAX_ROOT_PORTS; Index ++) { + FspsUpd->FspsConfig.PcieEqPh3LaneParamCm[Index] = (UINT8)PcieRpConfig->EqPh3LaneParam[Index].Cm; + FspsUpd->FspsConfig.PcieEqPh3LaneParamCp[Index] = (UINT8)PcieRpConfig->EqPh3LaneParam[Index].Cp; + } + + // + // Update PCIE RP SwEqCoeffList policies + // + for (Index = 0; Index < PCH_PCIE_SWEQ_COEFFS_MAX; Index ++) { + FspsUpd->FspsConfig.PcieSwEqCoeffListCm[Index] = (UINT8)PcieRpConfig->SwEqCoeffList[Index].Cm; + FspsUpd->FspsConfig.PcieSwEqCoeffListCp[Index] = (UINT8)PcieRpConfig->SwEqCoeffList[Index].Cp; + } + + // + // Update PCIE RP policies + // + FspsUpd->FspsTestConfig.PcieEnablePort8xhDecode = (UINT8)PcieRpConfig->EnablePort8xhDecode; + FspsUpd->FspsTestConfig.PchPciePort8xhDecodePortIndex = (UINT8)PcieRpConfig->PchPciePort8xhDecodePortIndex; + FspsUpd->FspsConfig.PcieDisableRootPortClockGating = (UINT8)PcieRpConfig->DisableRootPortClockGating; + FspsUpd->FspsConfig.PcieEnablePeerMemoryWrite = (UINT8)PcieRpConfig->EnablePeerMemoryWrite; + FspsUpd->FspsConfig.PcieAllowNoLtrIccPllShutdown = (UINT8)PcieRpConfig->AllowNoLtrIccPllShutdown; + FspsUpd->FspsConfig.PcieComplianceTestMode = (UINT8)PcieRpConfig->ComplianceTestMode; + FspsUpd->FspsConfig.PcieRpFunctionSwap = (UINT8)PcieRpConfig->RpFunctionSwap; + FspsUpd->FspsConfig.PcieDetectTimeoutMs = (UINT16)PcieRpConfig->DetectTimeoutMs; + FspsUpd->FspsConfig.PchPcieDeviceOverrideTablePtr = PcieRpConfig->PcieDeviceOverrideTablePtr; + + // + // Update Sata Policies + // + FspsUpd->FspsConfig.SataEnable = (UINT8)SataConfig->Enable; + FspsUpd->FspsTestConfig.SataTestMode = (UINT8)SataConfig->TestMode; + FspsUpd->FspsConfig.SataSalpSupport = (UINT8)SataConfig->SalpSupport; + FspsUpd->FspsConfig.SataPwrOptEnable = (UINT8)SataConfig->PwrOptEnable; + FspsUpd->FspsConfig.EsataSpeedLimit = (UINT8)SataConfig->EsataSpeedLimit; + FspsUpd->FspsConfig.SataMode = (UINT8)SataConfig->SataMode; + FspsUpd->FspsConfig.SataSpeedLimit = (UINT8)SataConfig->SpeedLimit; + + for (Index = 0; Index < PCH_MAX_SATA_PORTS; Index++) { + FspsUpd->FspsConfig.SataPortsEnable[Index] = (UINT8)SataConfig->PortSettings[Index].Enable; + FspsUpd->FspsConfig.SataPortsHotPlug[Index] = (UINT8)SataConfig->PortSettings[Index].HotPlug; + FspsUpd->FspsConfig.SataPortsInterlockSw[Index] = (UINT8)SataConfig->PortSettings[Index].InterlockSw; + FspsUpd->FspsConfig.SataPortsExternal[Index] = (UINT8)SataConfig->PortSettings[Index].External; + FspsUpd->FspsConfig.SataPortsSpinUp[Index] = (UINT8)SataConfig->PortSettings[Index].SpinUp; + FspsUpd->FspsConfig.SataPortsSolidStateDrive[Index] = (UINT8)SataConfig->PortSettings[Index].SolidStateDrive; + FspsUpd->FspsConfig.SataPortsDevSlp[Index] = (UINT8)SataConfig->PortSettings[Index].DevSlp; + FspsUpd->FspsConfig.SataPortsEnableDitoConfig[Index] = (UINT8)SataConfig->PortSettings[Index].EnableDitoConfig; + FspsUpd->FspsConfig.SataPortsDmVal[Index] = (UINT8)SataConfig->PortSettings[Index].DmVal; + FspsUpd->FspsConfig.SataPortsDitoVal[Index] = (UINT16)SataConfig->PortSettings[Index].DitoVal; + FspsUpd->FspsConfig.SataPortsZpOdd[Index] = (UINT8)SataConfig->PortSettings[Index].ZpOdd; + } + + FspsUpd->FspsConfig.SataRstRaidAlternateId = (UINT8)SataConfig->Rst.RaidDeviceId; + FspsUpd->FspsConfig.SataRstRaid0 = (UINT8)SataConfig->Rst.Raid0; + FspsUpd->FspsConfig.SataRstRaid1 = (UINT8)SataConfig->Rst.Raid1; + FspsUpd->FspsConfig.SataRstRaid10 = (UINT8)SataConfig->Rst.Raid10; + FspsUpd->FspsConfig.SataRstRaid5 = (UINT8)SataConfig->Rst.Raid5; + FspsUpd->FspsConfig.SataRstIrrt = (UINT8)SataConfig->Rst.Irrt; + FspsUpd->FspsConfig.SataRstOromUiBanner = (UINT8)SataConfig->Rst.OromUiBanner; + FspsUpd->FspsConfig.SataRstOromUiDelay = (UINT8)SataConfig->Rst.OromUiDelay; + FspsUpd->FspsConfig.SataRstHddUnlock = (UINT8)SataConfig->Rst.HddUnlock; + FspsUpd->FspsConfig.SataRstLedLocate = (UINT8)SataConfig->Rst.LedLocate; + FspsUpd->FspsConfig.SataRstIrrtOnly = (UINT8)SataConfig->Rst.IrrtOnly; + FspsUpd->FspsConfig.SataRstSmartStorage = (UINT8)SataConfig->Rst.SmartStorage; + FspsUpd->FspsConfig.SataRstOptaneMemory = (UINT8)SataConfig->Rst.OptaneMemory; + + for (Index = 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) { + FspsUpd->FspsConfig.SataRstPcieEnable[Index] = (UINT8)SataConfig->RstPcieStorageRemap[Index].Enable; + FspsUpd->FspsConfig.SataRstPcieStoragePort[Index] = (UINT8)SataConfig->RstPcieStorageRemap[Index].RstPcieStoragePort; + FspsUpd->FspsConfig.SataRstPcieDeviceResetDelay[Index] = (UINT8)SataConfig->RstPcieStorageRemap[Index].DeviceResetDelay; + } + + // + // Update USB policies + // + FspsUpd->FspsConfig.PchDisableComplianceMode = (UINT8)UsbConfig->DisableComplianceMode; + for (Index = 0; Index < PCH_MAX_USB2_PORTS; Index++) { + FspsUpd->FspsConfig.PortUsb20Enable[Index] = (UINT8)UsbConfig->PortUsb20[Index].Enable; + FspsUpd->FspsConfig.Usb2OverCurrentPin[Index] = (UINT8)UsbConfig->PortUsb20[Index].OverCurrentPin; + FspsUpd->FspsConfig.Usb2AfePetxiset[Index] = (UINT8)UsbConfig->PortUsb20[Index].Afe.Petxiset; + FspsUpd->FspsConfig.Usb2AfeTxiset[Index] = (UINT8)UsbConfig->PortUsb20[Index].Afe.Txiset; + FspsUpd->FspsConfig.Usb2AfePredeemp[Index] = (UINT8)UsbConfig->PortUsb20[Index].Afe.Predeemp; + FspsUpd->FspsConfig.Usb2AfePehalfbit[Index] = (UINT8)UsbConfig->PortUsb20[Index].Afe.Pehalfbit; + } + for (Index = 0; Index < PCH_MAX_USB3_PORTS; Index++) { + FspsUpd->FspsConfig.PortUsb30Enable[Index] = (UINT8)UsbConfig->PortUsb30[Index].Enable; + FspsUpd->FspsConfig.Usb3OverCurrentPin[Index] = (UINT8)UsbConfig->PortUsb30[Index].OverCurrentPin; + FspsUpd->FspsConfig.Usb3HsioTxDeEmphEnable[Index] = (UINT8)UsbConfig->PortUsb30[Index].HsioTxDeEmphEnable; + FspsUpd->FspsConfig.Usb3HsioTxDeEmph[Index] = (UINT8)UsbConfig->PortUsb30[Index].HsioTxDeEmph; + FspsUpd->FspsConfig.Usb3HsioTxDownscaleAmpEnable[Index] = (UINT8)UsbConfig->PortUsb30[Index].HsioTxDownscaleAmpEnable; + FspsUpd->FspsConfig.Usb3HsioTxDownscaleAmp[Index] = (UINT8)UsbConfig->PortUsb30[Index].HsioTxDownscaleAmp; + } + FspsUpd->FspsConfig.SsicPortEnable = (UINT8)UsbConfig->SsicConfig.SsicPort[0].Enable; + FspsUpd->FspsConfig.XdciEnable = (UINT8)UsbConfig->XdciConfig.Enable; + + // + // Update SerialIo policies + // + for (Index = 0; Index < PCH_SERIALIO_MAX_CONTROLLERS; Index++) { + FspsUpd->FspsConfig.SerialIoDevMode[Index] = (UINT8)SerialIoConfig->DevMode[Index]; + } + for (Index = 0; Index < PCH_SERIALIO_MAX_I2C_CONTROLLERS; Index++) { + FspsUpd->FspsConfig.SerialIoI2cVoltage[Index] = (UINT8)SerialIoConfig->I2cVoltage[Index]; + } + for (Index = 0; Index < PCH_SERIALIO_MAX_SPI_CONTROLLERS; Index++) { + FspsUpd->FspsConfig.SerialIoSpiCsPolarity[Index] = (UINT8)SerialIoConfig->SpiCsPolarity[Index]; + } + for (Index = 0; Index < PCH_SERIALIO_MAX_UART_CONTROLLERS; Index++) { + FspsUpd->FspsConfig.SerialIoUartHwFlowCtrl[Index] = (UINT8)SerialIoConfig->UartHwFlowCtrl[Index]; + } + FspsUpd->FspsConfig.SerialIoGpio = (UINT8)SerialIoConfig->Gpio; + FspsUpd->FspsConfig.SerialIoDebugUartNumber = (UINT8)SerialIoConfig->DebugUartNumber; + FspsUpd->FspsConfig.SerialIoEnableDebugUartAfterPost = (UINT8)SerialIoConfig->EnableDebugUartAfterPost; + + // + // Update Interrupt policies + // + FspsUpd->FspsConfig.DevIntConfigPtr = (UINT32)InterruptConfig->DevIntConfig; + FspsUpd->FspsConfig.NumOfDevIntConfig = InterruptConfig->NumOfDevIntConfig; + for (Index = 0; Index < PCH_MAX_PXRC_CONFIG; Index ++) { + FspsUpd->FspsConfig.PxRcConfig[Index] = (UINT8)InterruptConfig->PxRcConfig[Index]; + } + FspsUpd->FspsConfig.GpioIrqRoute = (UINT8)InterruptConfig->GpioIrqRoute; + FspsUpd->FspsConfig.SciIrqSelect = (UINT8)InterruptConfig->SciIrqSelect; + FspsUpd->FspsConfig.TcoIrqSelect = (UINT8)InterruptConfig->TcoIrqSelect; + FspsUpd->FspsConfig.TcoIrqEnable = (UINT8)InterruptConfig->TcoIrqEnable; + + // + // Update LockDown policies + // + FspsUpd->FspsTestConfig.PchLockDownRtcLock = (UINT8)LockDownConfig->RtcLock; + FspsUpd->FspsTestConfig.PchLockDownGlobalSmi = (UINT8)LockDownConfig->GlobalSmi; + FspsUpd->FspsTestConfig.PchLockDownBiosInterface = (UINT8)LockDownConfig->BiosInterface; + FspsUpd->FspsConfig.PchLockDownBiosLock = (UINT8)LockDownConfig->BiosLock; + FspsUpd->FspsConfig.PchLockDownSpiEiss = (UINT8)LockDownConfig->SpiEiss; + + // + // Update Dmi policies + // + FspsUpd->FspsConfig.PchDmiAspm = (UINT8)DmiConfig->DmiAspm; + FspsUpd->FspsConfig.PchPwrOptEnable = (UINT8)DmiConfig->PwrOptEnable; + if (DmiConfig->LegacyIoLowLatency) { + FspsUpd->FspsConfig.PchDmiAspm = 0; + FspsUpd->FspsConfig.PchLegacyIoLowLatency = TRUE; + } + + // + // Update Flash Protection policies + // + for (Index = 0; Index < PCH_FLASH_PROTECTED_RANGES; Index ++) { + FspsUpd->FspsConfig.PchWriteProtectionEnable[Index] = (UINT8)FlashProtectionConfig->ProtectRange[Index].WriteProtectionEnable; + FspsUpd->FspsConfig.PchReadProtectionEnable[Index] = (UINT8)FlashProtectionConfig->ProtectRange[Index].ReadProtectionEnable; + FspsUpd->FspsConfig.PchProtectedRangeLimit[Index] = (UINT16)FlashProtectionConfig->ProtectRange[Index].ProtectedRangeLimit; + FspsUpd->FspsConfig.PchProtectedRangeBase[Index] = (UINT16)FlashProtectionConfig->ProtectRange[Index].ProtectedRangeBase; + } + + // + // Update IO Apic policies + // + FspsUpd->FspsConfig.PchIoApicBdfValid = (UINT8)IoApicConfig->BdfValid; + FspsUpd->FspsConfig.PchIoApicBusNumber = (UINT8)IoApicConfig->BusNumber; + FspsUpd->FspsConfig.PchIoApicDeviceNumber = (UINT8)IoApicConfig->DeviceNumber; + FspsUpd->FspsConfig.PchIoApicFunctionNumber = (UINT8)IoApicConfig->FunctionNumber; + FspsUpd->FspsConfig.PchIoApicEntry24_119 = (UINT8)IoApicConfig->IoApicEntry24_119; + FspsUpd->FspsConfig.Early8254ClockGatingEnable = (UINT8)IoApicConfig->Early8254ClockGatingEnable; + FspsUpd->FspsConfig.PchIoApicId = (UINT8)IoApicConfig->IoApicId; + FspsUpd->FspsConfig.PchIoApicRangeSelect = (UINT8)IoApicConfig->ApicRangeSelect; + + // + // Update P2sb policies + // + FspsUpd->FspsTestConfig.PchSbiUnlock = (UINT8)P2sbConfig->SbiUnlock; + FspsUpd->FspsTestConfig.PchSbAccessUnlock = (UINT8)P2sbConfig->SbAccessUnlock; + + // + // Update Pch General policies + // + FspsUpd->FspsConfig.PchSubSystemVendorId = (UINT16)PchGeneralConfig->SubSystemVendorId; + FspsUpd->FspsConfig.PchSubSystemId = (UINT16)PchGeneralConfig->SubSystemId; + FspsUpd->FspsConfig.PchCrid = (UINT8)PchGeneralConfig->Crid; + + // + // Update Pm policies + // + FspsUpd->FspsConfig.PchPmPmeB0S5Dis = (UINT8)PmConfig->WakeConfig.PmeB0S5Dis; + FspsUpd->FspsConfig.PchPmWolEnableOverride = (UINT8)PmConfig->WakeConfig.WolEnableOverride; + FspsUpd->FspsConfig.PchPmPcieWakeFromDeepSx = (UINT8)PmConfig->WakeConfig.PcieWakeFromDeepSx; + FspsUpd->FspsConfig.PchPmWoWlanEnable = (UINT8)PmConfig->WakeConfig.WoWlanEnable; + FspsUpd->FspsConfig.PchPmWoWlanDeepSxEnable = (UINT8)PmConfig->WakeConfig.WoWlanDeepSxEnable; + FspsUpd->FspsConfig.PchPmLanWakeFromDeepSx = (UINT8)PmConfig->WakeConfig.LanWakeFromDeepSx; + + FspsUpd->FspsConfig.PchPmDeepSxPol = (UINT8)PmConfig->PchDeepSxPol; + FspsUpd->FspsConfig.PchPmSlpS3MinAssert = (UINT8)PmConfig->PchSlpS3MinAssert; + FspsUpd->FspsConfig.PchPmSlpS4MinAssert = (UINT8)PmConfig->PchSlpS4MinAssert; + FspsUpd->FspsConfig.PchPmSlpSusMinAssert = (UINT8)PmConfig->PchSlpSusMinAssert; + FspsUpd->FspsConfig.PchPmSlpAMinAssert = (UINT8)PmConfig->PchSlpAMinAssert; + + FspsUpd->FspsConfig.PchPmLpcClockRun = (UINT8)PmConfig->LpcClockRun; + FspsUpd->FspsConfig.PchPmSlpStrchSusUp = (UINT8)PmConfig->SlpStrchSusUp; + FspsUpd->FspsConfig.PchPmSlpLanLowDc = (UINT8)PmConfig->SlpLanLowDc; + FspsUpd->FspsConfig.PchPmPwrBtnOverridePeriod = (UINT8)PmConfig->PwrBtnOverridePeriod; + FspsUpd->FspsTestConfig.PchPmDisableEnergyReport = (UINT8)PmConfig->DisableEnergyReport; + FspsUpd->FspsConfig.PchPmDisableDsxAcPresentPulldown = (UINT8)PmConfig->DisableDsxAcPresentPulldown; + FspsUpd->FspsTestConfig.PchPmPmcReadDisable = (UINT8)PmConfig->PmcReadDisable; + FspsUpd->FspsConfig.PchPmDisableNativePowerButton = (UINT8)PmConfig->DisableNativePowerButton; + FspsUpd->FspsConfig.PchPmSlpS0Enable = (UINT8)PmConfig->SlpS0Enable; + FspsUpd->FspsConfig.PchPmSlpS0VmEnable = (UINT8)PmConfig->SlpS0VmEnable; + FspsUpd->FspsConfig.PchPmMeWakeSts = (UINT8)PmConfig->MeWakeSts; + FspsUpd->FspsConfig.PchPmWolOvrWkSts = (UINT8)PmConfig->WolOvrWkSts; + FspsUpd->FspsConfig.EnableTcoTimer = (UINT8)PmConfig->EnableTcoTimer; + FspsUpd->FspsConfig.PchPmPwrCycDur = (UINT8)PmConfig->PchPwrCycDur; + + // + // Update Port61h policies + // + FspsUpd->FspsConfig.PchPort61hEnable = (UINT8)Port61hConfig->Enable; + + // + // Update Pch Serial IRQ policies + // + FspsUpd->FspsConfig.PchSirqEnable = (UINT8)PchSerialIrqConfig->SirqEnable; + FspsUpd->FspsConfig.PchSirqMode = (UINT8)PchSerialIrqConfig->SirqMode; + FspsUpd->FspsConfig.PchStartFramePulse = (UINT8)PchSerialIrqConfig->StartFramePulse; + + // + // Update Pch Thermal policies + // + FspsUpd->FspsConfig.PchThermalDeviceEnable = (UINT8)PchThermalConfig->ThermalDeviceEnable; + FspsUpd->FspsConfig.PchTsmicLock = (UINT8)PchThermalConfig->TsmicLock; + + FspsUpd->FspsConfig.PchT0Level = (UINT16)PchThermalConfig->TTLevels.T0Level; + FspsUpd->FspsConfig.PchT1Level = (UINT16)PchThermalConfig->TTLevels.T1Level; + FspsUpd->FspsConfig.PchT2Level = (UINT16)PchThermalConfig->TTLevels.T2Level; + FspsUpd->FspsConfig.PchTTEnable = (UINT8)PchThermalConfig->TTLevels.TTEnable; + FspsUpd->FspsConfig.PchTTState13Enable = (UINT8)PchThermalConfig->TTLevels.TTState13Enable; + FspsUpd->FspsConfig.PchTTLock = (UINT8)PchThermalConfig->TTLevels.TTLock; + FspsUpd->FspsConfig.TTSuggestedSetting = (UINT8)PchThermalConfig->TTLevels.SuggestedSetting; + FspsUpd->FspsConfig.TTCrossThrottling = (UINT8)PchThermalConfig->TTLevels.PchCrossThrottling; + + FspsUpd->FspsConfig.PchDmiTsawEn = (UINT8)PchThermalConfig->DmiHaAWC.DmiTsawEn; + FspsUpd->FspsConfig.DmiSuggestedSetting = (UINT8)PchThermalConfig->DmiHaAWC.SuggestedSetting; + FspsUpd->FspsConfig.DmiTS0TW = (UINT8)PchThermalConfig->DmiHaAWC.TS0TW; + FspsUpd->FspsConfig.DmiTS1TW = (UINT8)PchThermalConfig->DmiHaAWC.TS1TW; + FspsUpd->FspsConfig.DmiTS2TW = (UINT8)PchThermalConfig->DmiHaAWC.TS2TW; + FspsUpd->FspsConfig.DmiTS3TW = (UINT8)PchThermalConfig->DmiHaAWC.TS3TW; + + FspsUpd->FspsConfig.SataP0T1M = (UINT8)PchThermalConfig->SataTT.P0T1M; + FspsUpd->FspsConfig.SataP0T2M = (UINT8)PchThermalConfig->SataTT.P0T2M; + FspsUpd->FspsConfig.SataP0T3M = (UINT8)PchThermalConfig->SataTT.P0T3M; + FspsUpd->FspsConfig.SataP0TDisp = (UINT8)PchThermalConfig->SataTT.P0TDisp; + FspsUpd->FspsConfig.SataP1T1M = (UINT8)PchThermalConfig->SataTT.P1T1M; + FspsUpd->FspsConfig.SataP1T2M = (UINT8)PchThermalConfig->SataTT.P1T2M; + FspsUpd->FspsConfig.SataP1T3M = (UINT8)PchThermalConfig->SataTT.P1T3M; + FspsUpd->FspsConfig.SataP1TDisp = (UINT8)PchThermalConfig->SataTT.P1TDisp; + FspsUpd->FspsConfig.SataP0Tinact = (UINT8)PchThermalConfig->SataTT.P0Tinact; + FspsUpd->FspsConfig.SataP0TDispFinit = (UINT8)PchThermalConfig->SataTT.P0TDispFinit; + FspsUpd->FspsConfig.SataP1Tinact = (UINT8)PchThermalConfig->SataTT.P1Tinact; + FspsUpd->FspsConfig.SataP1TDispFinit = (UINT8)PchThermalConfig->SataTT.P1TDispFinit; + FspsUpd->FspsConfig.SataThermalSuggestedSetting = (UINT8)PchThermalConfig->SataTT.SuggestedSetting; + + FspsUpd->FspsConfig.PchMemoryThrottlingEnable = (UINT8)PchThermalConfig->MemoryThrottling.Enable; + FspsUpd->FspsConfig.PchMemoryPmsyncEnable[0] = (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[0].PmsyncEnable; + FspsUpd->FspsConfig.PchMemoryPmsyncEnable[1] = (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[1].PmsyncEnable; + FspsUpd->FspsConfig.PchMemoryC0TransmitEnable[0] = (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[0].C0TransmitEnable; + FspsUpd->FspsConfig.PchMemoryC0TransmitEnable[1] = (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[1].C0TransmitEnable; + FspsUpd->FspsConfig.PchMemoryPinSelection[0] = (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[0].PinSelection; + FspsUpd->FspsConfig.PchMemoryPinSelection[1] = (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[1].PinSelection; + + FspsUpd->FspsConfig.PchTemperatureHotLevel = (UINT16)PchThermalConfig->PchHotLevel; + + + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspPolicyInitLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspPolicyInitLib.c new file mode 100644 index 0000000000..d15e3f9083 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspPolicyInitLib.c @@ -0,0 +1,212 @@ +/** @file + Instance of Fsp Policy Initialization Library. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include + +/** + Performs silicon pre-mem policy initialization. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a PPI, etc. + + The returned data must be used as input data for SiliconPolicyDonePreMem(), + and SiliconPolicyUpdateLib.SiliconPolicyUpdatePreMem(). + + 1) In FSP path, the input Policy should be FspmUpd. + Value of FspmUpd has been initialized by FSP binary default value. + Only a subset of FspmUpd needs to be updated for different silicon sku. + The return data is same FspmUpd. + + 2) In non-FSP path, the input policy could be NULL. + The return data is the initialized policy. + + @param[in, out] Policy Pointer to policy. + + @return the initialized policy. +**/ +VOID * +EFIAPI +SiliconPolicyInitPreMem ( + IN OUT VOID *FspmUpd + ) +{ + FSPM_UPD *FspmUpdDataPtr; + EFI_STATUS Status; + + FspmUpdDataPtr = FspmUpd; + + // + // Initialize Intel PEI Platform Policy + // + PeiPolicyInitPreMem (); + + // + // SI Pei Fsp Policy Initialization + // + Status = PeiFspSiPolicyInitPreMem (FspmUpdDataPtr); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "ERROR - SI Pei Fsp Policy in Pre-Memory Initialization fail, Status = %r\n", Status)); + } + + // + // PCH Pei Fsp Policy Initialization + // + Status = PeiFspPchPolicyInitPreMem (FspmUpdDataPtr); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "ERROR - PCH Pei Fsp Policy in Pre-Memory Initialization fail, Status = %r\n", Status)); + } + + // + // Cpu Pei Fsp Policy Initialization + // + Status = PeiFspCpuPolicyInitPreMem (FspmUpdDataPtr); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "ERROR - CPU Pei Fsp Policy in Pre-Memory Initialization fail, Status = %r\n", Status)); + } + + + // + // ME Pei Fsp Policy Initialization + // + Status = PeiFspMePolicyInitPreMem (FspmUpdDataPtr); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "ERROR - ME Pei Fsp Policy in Pre-Memory Initialization fail, Status = %r\n", Status)); + } + + // + // SystemAgent Pei Fsp Policy Initialization + // + Status = PeiFspSaPolicyInitPreMem (FspmUpdDataPtr); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "ERROR - SystemAgent Pei Fsp Policy in Pre-Memory Initialization fail, Status = %r\n", Status)); + } + + // + // Other Upd Initialization + // + Status = PeiFspMiscUpdInitPreMem (FspmUpdDataPtr); + + return FspmUpd; +} + +/* + The silicon pre-mem policy is finalized. + Silicon code can do initialization based upon the policy data. + + The input Policy must be returned by SiliconPolicyInitPreMem(). + + @param[in] Policy Pointer to policy. + + @retval EFI_SUCCESS The policy is handled consumed by silicon code. +*/ +EFI_STATUS +EFIAPI +SiliconPolicyDonePreMem ( + IN OUT VOID *FspmUpd + ) +{ + return EFI_SUCCESS; +} + +/** + Performs silicon post-mem policy initialization. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a PPI, etc. + + The returned data must be used as input data for SiliconPolicyDonePostMem(), + and SiliconPolicyUpdateLib.SiliconPolicyUpdatePostMem(). + + 1) In FSP path, the input Policy should be FspsUpd. + Value of FspsUpd has been initialized by FSP binary default value. + Only a subset of FspsUpd needs to be updated for different silicon sku. + The return data is same FspsUpd. + + 2) In non-FSP path, the input policy could be NULL. + The return data is the initialized policy. + + @param[in, out] Policy Pointer to policy. + + @return the initialized policy. +**/ +VOID * +EFIAPI +SiliconPolicyInitPostMem ( + IN OUT VOID *FspsUpd + ) +{ + FSPS_UPD *FspsUpdDataPtr; + EFI_STATUS Status; + + FspsUpdDataPtr = FspsUpd; + + // + // Initialize Intel PEI Platform Policy + // + PeiPolicyInit (); + + // + // PCH Pei Fsp Policy Initialization + // + Status = PeiFspPchPolicyInit (FspsUpdDataPtr); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "ERROR - PCH Pei Fsp Policy iInitialization fail, Status = %r\n", Status)); + } + + // + // ME Pei Fsp Policy Initialization + // + Status = PeiFspMePolicyInit (FspsUpdDataPtr); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "ERROR - ME Pei Fsp Policy Initialization fail, Status = %r\n", Status)); + } + + // + // SystemAgent Pei Fsp Policy Initialization + // + Status = PeiFspSaPolicyInit (FspsUpdDataPtr); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "ERROR - SystemAgent Pei Fsp Policy Initialization fail, Status = %r\n", Status)); + } + + + // + // Cpu Pei Fsp Policy Initialization + // + Status = PeiFspCpuPolicyInit (FspsUpdDataPtr); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "ERROR - CPU Pei Fsp Policy Initialization fail, Status = %r\n", Status)); + } + + return FspsUpd; +} + +/* + The silicon post-mem policy is finalized. + Silicon code can do initialization based upon the policy data. + + The input Policy must be returned by SiliconPolicyInitPostMem(). + + @param[in] Policy Pointer to policy. + + @retval EFI_SUCCESS The policy is handled consumed by silicon code. +*/ +EFI_STATUS +EFIAPI +SiliconPolicyDonePostMem ( + IN OUT VOID *FspsUpd + ) +{ + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspPolicyInitLib.h b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspPolicyInitLib.h new file mode 100644 index 0000000000..a17b642a1d --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspPolicyInitLib.h @@ -0,0 +1,179 @@ +/** @file + Internal header file for Fsp Policy Initialization Library. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PEI_FSP_POLICY_INIT_LIB_H_ +#define _PEI_FSP_POLICY_INIT_LIB_H_ + +#include + +#include +#include +#include +#include "PeiPolicyInitLib.h" + +#include +#include +#include + +/** + Performs FSP SI PEI Policy initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSiPolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ); + +/** + Performs FSP PCH PEI Policy pre mem initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspPchPolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ); + +/** + Performs FSP PCH PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspPchPolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ); + +/** + Performs FSP CPU PEI Policy initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspCpuPolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ); + + +/** + Performs FSP ME PEI Policy pre mem initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspMePolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ); + +/** + Performs FSP ME PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspMePolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ); + +/** + Performs FSP SA PEI Policy initialization in pre-memory. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSaPolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ); + +/** + Performs FSP SA PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSaPolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ); + + +/** + Performs FSP CPU PEI Policy post memory initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspCpuPolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ); + +/** + Performs FSP Misc UPD initialization. + + @param[in][out] FspmUpd Pointer to FSPM_UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. +**/ +EFI_STATUS +EFIAPI +PeiFspMiscUpdInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ); + +#endif // _PEI_FSP_POLICY_INIT_LIB_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspSaPolicyInitLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspSaPolicyInitLib.c new file mode 100644 index 0000000000..3d218f8ba9 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspSaPolicyInitLib.c @@ -0,0 +1,578 @@ +/** @file + Implementation of Fsp SA Policy Initialization. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#define MAX_SPD_PAGE_COUNT (2) +#define MAX_SPD_PAGE_SIZE (256) +#define MAX_SPD_SIZE (MAX_SPD_PAGE_SIZE * MAX_SPD_PAGE_COUNT) +#define SPD_PAGE_ADDRESS_0 (0x6C) +#define SPD_PAGE_ADDRESS_1 (0x6E) +#define SPD_DDR3_SDRAM_TYPE_OFFSET (0x02) +#define SPD_DDR3_SDRAM_TYPE_NUMBER (0x0B) +#define SPD_DDR4_SDRAM_TYPE_NUMBER (0x0C) +#define SPD_LPDDR3_SDRAM_TYPE_NUMBER (0xF1) +#define SPD_JEDEC_LPDDR3_SDRAM_TYPE_NUMBER (0x0F) +#define XMP_ID_STRING (0x4A0C) +#define SPD3_MANUF_START (117) +#define SPD3_MANUF_END (127) +#define SPD4_MANUF_START (320) +#define SPD4_MANUF_END (328) +#define SPDLP_MANUF_START (320) +#define SPDLP_MANUF_END (328) + +GLOBAL_REMOVE_IF_UNREFERENCED const SPD_OFFSET_TABLE mSpdDdr3Table[] = { + { 0, 1, (1 << SpdCold),}, + { 2, 2, (1 << SpdCold) | (1 << SpdFast),}, + { 3, 41, (1 << SpdCold),}, + { 60, 63, (1 << SpdCold),}, + { SPD3_MANUF_START, SPD3_MANUF_END, (1 << SpdCold) | (1 << SpdFast),}, + { 128, 145, (1 << SpdCold),}, +#ifdef SUPPORT_SPD_CRC + { 39, 59, (1 << SpdCold),}, + { 64, 125, (1 << SpdCold),}, +#endif + { 176, 179, (1 << SpdCold),}, + { 180, 184, (1 << SpdCold),}, + { 185, 215, (1 << SpdCold),}, + { 220, 250, (1 << SpdCold),}, +}; + +GLOBAL_REMOVE_IF_UNREFERENCED const SPD_OFFSET_TABLE mSpdDdr4Table[] = { + { 0, 1, (1 << SpdCold),}, + { 2, 2, (1 << SpdCold) | (1 << SpdFast),}, + { 3, 40, (1 << SpdCold),}, + { 117, 131, (1 << SpdCold),}, + { SPD4_MANUF_START, SPD4_MANUF_END, (1 << SpdCold) | (1 << SpdFast),}, + { 329, 348, (1 << SpdCold),}, +#ifdef SUPPORT_SPD_CRC + { 32, 119, (1 << SpdCold),}, + { 126, 255, (1 << SpdCold),}, + { 349, 383, (1 << SpdCold),}, +#endif + { 384, 387, (1 << SpdCold),}, + { 388, 389, (1 << SpdCold),}, + { 393, 431, (1 << SpdCold),}, + { 440, 478, (1 << SpdCold),}, +}; + +GLOBAL_REMOVE_IF_UNREFERENCED const SPD_OFFSET_TABLE mSpdLpddrTable[] = { + { 0, 1, (1 << SpdCold),}, + { 2, 2, (1 << SpdCold) | (1 << SpdFast),}, + { 3, 32, (1 << SpdCold),}, + { 120, 130, (1 << SpdCold),}, + { SPDLP_MANUF_START, SPDLP_MANUF_END, (1 << SpdCold) | (1 << SpdFast),}, + { 329, 348, (1 << SpdCold),}, +#ifdef SUPPORT_SPD_CRC + { 31, 121, (1 << SpdCold),}, + { 126, 255, (1 << SpdCold),}, + { 349, 383, (1 << SpdCold),}, +#endif + { 384, 387, (1 << SpdCold),}, + { 388, 389, (1 << SpdCold),}, + { 393, 431, (1 << SpdCold),}, + { 440, 478, (1 << SpdCold),}, +}; + + +/** + Read the SPD data over the SMBus, at the specified SPD address, starting at + the specified starting offset and read the given amount of data. + + @param[in] SpdAddress - SPD SMBUS address + @param[in, out] Buffer - Buffer to store the data. + @param[in] Start - Starting SPD offset + @param[in] Size - The number of bytes of data to read and also the size of the buffer. + @param[in, out] Page - The final page that is being pointed to. + + @retval EFI_SUCCESS if the read is successful, otherwise error status. +**/ +static +EFI_STATUS +InternalDoSpdRead ( + IN const UINT8 SpdAddress, + IN OUT UINT8 *const Buffer, + IN const UINT16 Start, + IN UINT16 Size, + IN OUT UINT8 *const Page + ) +{ + EFI_STATUS EfiStatus; + BOOLEAN PageUpdate; + UINT16 Count; + UINT16 Index; + + EfiStatus = EFI_DEVICE_ERROR; + if ((Buffer != NULL) && (Start < MAX_SPD_SIZE) && ((Start + Size) < MAX_SPD_SIZE)) { + Count = 0; + PageUpdate = FALSE; + while (Size--) { + Index = Start + Count; + if ((Index / MAX_SPD_PAGE_SIZE) != *Page) { + *Page = (UINT8) (Index / MAX_SPD_PAGE_SIZE); + PageUpdate = TRUE; + } + Index %= MAX_SPD_PAGE_SIZE; + if (PageUpdate == TRUE) { + PageUpdate = FALSE; + SmBusWriteDataByte ((*Page == 0) ? SPD_PAGE_ADDRESS_0 : SPD_PAGE_ADDRESS_1, 0, &EfiStatus); + } + Buffer[Count] = SmBusReadDataByte (SpdAddress | ((UINT32) Index << 8), &EfiStatus); + if (EFI_SUCCESS != EfiStatus) { + Buffer[Count] = 0; + break; + } + Count++; + } + EfiStatus = EFI_SUCCESS; + } + return (EfiStatus); +} + +/** + See if there is valid XMP SPD data. + + @param[in] Debug - Mrc debug structure. + @param[in, out] Spd - Mrc SPD structure. + @param[in] XmpStart - The current offset in the SPD. + + @retval TRUE if valid, FALSE in not. +**/ +static +BOOLEAN +InternalVerifyXmp ( + IN OUT MrcSpd *const Spd, + IN const UINT16 XmpStart + ) +{ + SPD_EXTREME_MEMORY_PROFILE_HEADER *Header1; + SPD_EXTREME_MEMORY_PROFILE_HEADER_2_0 *Header2; + BOOLEAN Xmp; + + Xmp = FALSE; + + switch (((UINT8 *)Spd)[2]) { + case SPD_DDR3_SDRAM_TYPE_NUMBER: + Header1 = &Spd->Ddr3.Xmp.Header; + if (XmpStart == ((UINT32) (Header1) - (UINT32) Spd)) { + Xmp = TRUE; + if ((Header1->XmpRevision.Data & 0xFE) == 0x12) { + return (TRUE); + } else { + Header1->XmpId = 0; + Header1->XmpOrgConf.Data = 0; + Header1->XmpRevision.Data = 0; + } + } + break; + case SPD_DDR4_SDRAM_TYPE_NUMBER: + Header2 = &Spd->Ddr4.EndUser.Xmp.Header; + if (XmpStart == ((UINT32) (Header2) - (UINT32) Spd)) { + Xmp = TRUE; + if ((Header2->XmpRevision.Data) == 0x20) { + return (TRUE); + } else { + Header2->XmpId = 0; + Header2->XmpOrgConf.Data = 0; + Header2->XmpRevision.Data = 0; + } + } + break; + case SPD_JEDEC_LPDDR3_SDRAM_TYPE_NUMBER: + case SPD_LPDDR3_SDRAM_TYPE_NUMBER: + return (TRUE); + default: + return (FALSE); + } + if (!Xmp) { + return (TRUE); + } + return (FALSE); +} + +/** + Read the SPD data over the SMBus, at the given SmBus SPD address and copy the data to the data structure. + The SPD data locations read is controlled by the current boot mode. + + @param[in] BootMode - The current MRC boot mode. + @param[in] Address - SPD SmBus address offset. + @param[in] Buffer - Buffer that contains the data read from the SPD. + @param[in] SpdDdr3Table - Indicates which SPD bytes to read. + @param[in] SpdDdr3TableSize - Size of SpdDdr3Table in bytes. + @param[in] SpdDdr4Table - Indicates which SPD bytes to read. + @param[in] SpdDdr4TableSize - Size of SpdDdr4Table in bytes. + @param[in] SpdLpddrTable - Indicates which SPD bytes to read. + @param[in] SpdLpddrTableSize - Size of SpdLpddrTable in bytes. + + @retval TRUE if the read is successful, otherwise FALSE on error. +**/ +BOOLEAN +InternalGetSpdData ( + IN SPD_BOOT_MODE BootMode, + IN UINT8 Address, + IN OUT UINT8 *Buffer, + IN UINT8 *SpdDdr3Table, + IN UINT32 SpdDdr3TableSize, + IN UINT8 *SpdDdr4Table, + IN UINT32 SpdDdr4TableSize, + IN UINT8 *SpdLpddrTable, + IN UINT32 SpdLpddrTableSize + ) +{ + const SPD_OFFSET_TABLE *Tbl; + const SPD_OFFSET_TABLE *TableSelect; + EFI_STATUS Status; + UINT32 Byte; + UINT32 Stop; + UINT8 Page; + + Page = (UINT8) (~0); + Status = InternalDoSpdRead (Address, &Buffer[SPD_DDR3_SDRAM_TYPE_OFFSET], 2, 1, &Page); + if (EFI_SUCCESS == Status) { + switch (Buffer[SPD_DDR3_SDRAM_TYPE_OFFSET]) { + case SPD_DDR3_SDRAM_TYPE_NUMBER: + case SPD_LPDDR3_SDRAM_TYPE_NUMBER: + default: + TableSelect = (SPD_OFFSET_TABLE *) SpdDdr3Table; + Stop = (SpdDdr3TableSize / sizeof (SPD_OFFSET_TABLE)); + break; + case SPD_DDR4_SDRAM_TYPE_NUMBER: + TableSelect = (SPD_OFFSET_TABLE *) SpdDdr4Table; + Stop = (SpdDdr4TableSize / sizeof (SPD_OFFSET_TABLE)); + break; + case SPD_JEDEC_LPDDR3_SDRAM_TYPE_NUMBER: + TableSelect = (SPD_OFFSET_TABLE *) SpdLpddrTable; + Stop = (SpdLpddrTableSize / sizeof (SPD_OFFSET_TABLE)); + break; + } + for (Byte = 0; (EFI_SUCCESS == Status) && (Byte < Stop); Byte++) { + Tbl = &TableSelect[Byte]; + if ((1 << BootMode) & Tbl->BootMode) { + Status = InternalDoSpdRead (Address, &Buffer[Tbl->Start], Tbl->Start, Tbl->End - Tbl->Start + 1, &Page); + if (Status == EFI_SUCCESS) { + if (SpdCold == BootMode) { + if (FALSE == InternalVerifyXmp ((MrcSpd *) Buffer, Tbl->Start)) { + break; + } + } + } else { + break; + } + } + } + } + + return ((EFI_SUCCESS == Status) ? TRUE : FALSE); +} + +/** + Initialize the Smbus PPI and program the Smbus BAR + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database +**/ +EFI_STATUS +InternalInitializePchSmbus ( + VOID + ) +{ + UINTN SmbusRegBase; + SmbusRegBase = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SMBUS, + PCI_FUNCTION_NUMBER_PCH_SMBUS + ); + + /// + /// Since PEI has no PCI enumerator, set the BAR & I/O space enable ourselves + /// + MmioAndThenOr32 (SmbusRegBase + R_PCH_SMBUS_BASE, B_PCH_SMBUS_BASE_BAR, PcdGet16 (PcdSmbusBaseAddress)); + + MmioOr8 (SmbusRegBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_IO_SPACE); + + /// + /// Reset the SMBus host controller + /// + MmioOr8 (SmbusRegBase + R_PCH_SMBUS_HOSTC, B_PCH_SMBUS_HOSTC_SSRESET); + + /// + /// Enable the SMBus host controller + /// + MmioAndThenOr8 ( + SmbusRegBase + R_PCH_SMBUS_HOSTC, + (UINT8)(~(B_PCH_SMBUS_HOSTC_SMI_EN | B_PCH_SMBUS_HOSTC_I2C_EN)), + B_PCH_SMBUS_HOSTC_HST_EN + ); + + /// + /// Clear Status Register before anyone uses the interfaces + /// + IoWrite8 (PcdGet16(PcdSmbusBaseAddress) + R_PCH_SMBUS_HSTS, B_PCH_SMBUS_HSTS_ALL); + + return EFI_SUCCESS; +} + +/** + Update Spd Data + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + @param[in] MemConfigNoCrc Pointer to Mem Config No Crc. + @param[in] MiscPeiPreMemConfig Pointer to Misc Config. + + @retval EFI_SUCCESS The function completes successfully + @retval Other The function fail +**/ +VOID +EFIAPI +InternalUpdateSpdData ( + IN OUT FSPM_UPD *FspmUpd, + IN MEMORY_CONFIG_NO_CRC *MemConfigNoCrc, + IN SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig + ) +{ + UINT8 Socket; + UINT8 *SpdData; + + InternalInitializePchSmbus (); + + DEBUG ((DEBUG_INFO, "Updating UPD:Memory Spd Pointers...\n")); + if (FspmUpd == NULL || MemConfigNoCrc == NULL) { + DEBUG ((DEBUG_ERROR, "EFI_INVALID_PARAMETER.\n")); + DEBUG ((DEBUG_ERROR, "Fail to access SPD from SiPolicyPpi\n")); + return; + } + + if (*((UINT32 *)MiscPeiPreMemConfig->SpdAddressTable) != 0x0) { + // + // Update MemConfigNoCrc->SpdData->SpdData + // + for (Socket = 0; Socket < SA_MC_MAX_SOCKETS; Socket++) { + SpdData = (UINT8 *)((UINT32)MemConfigNoCrc->SpdData->SpdData + (Socket * SA_MC_MAX_SPD_SIZE)); + InternalGetSpdData ( + 0, + MiscPeiPreMemConfig->SpdAddressTable[Socket], + (UINT8 *)SpdData, + (UINT8 *)&mSpdDdr3Table, + sizeof(mSpdDdr3Table), + (UINT8 *)&mSpdDdr4Table, + sizeof(mSpdDdr4Table), + (UINT8 *)&mSpdLpddrTable, + sizeof(mSpdLpddrTable) + ); + } + } + + FspmUpd->FspmConfig.MemorySpdPtr00 = (UINT32)MemConfigNoCrc->SpdData->SpdData; + FspmUpd->FspmConfig.MemorySpdPtr01 = (UINT32)MemConfigNoCrc->SpdData->SpdData + (1 * SA_MC_MAX_SPD_SIZE); + FspmUpd->FspmConfig.MemorySpdPtr10 = (UINT32)MemConfigNoCrc->SpdData->SpdData + (2 * SA_MC_MAX_SPD_SIZE); + FspmUpd->FspmConfig.MemorySpdPtr11 = (UINT32)MemConfigNoCrc->SpdData->SpdData + (3 * SA_MC_MAX_SPD_SIZE); + + DEBUG ((DEBUG_INFO, "UPD:MemorySpdPtr Updated\n")); +} + +/** + Performs FSP SA PEI Policy initialization in pre-memory. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSaPolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + EFI_STATUS Status; + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; + MEMORY_CONFIGURATION *MemConfig; + MEMORY_CONFIG_NO_CRC *MemConfigNoCrc; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + + // + // Locate SiPreMemPolicyPpi + // + SiPreMemPolicyPpi = NULL; + MiscPeiPreMemConfig = NULL; + MemConfig = NULL; + MemConfigNoCrc = NULL; + + + Status = PeiServicesLocatePpi( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPreMemPolicyPpi + ); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status) == FALSE) { + Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gMemoryConfigNoCrcGuid, (VOID *) &MemConfigNoCrc); + ASSERT_EFI_ERROR (Status); + Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gMemoryConfigGuid, (VOID *) &MemConfig); + ASSERT_EFI_ERROR (Status); + } + + // + // Update UPD:DqPinsInterleaved + // + FspmUpd->FspmConfig.DqPinsInterleaved = (UINT8)MemConfig->DqPinsInterleaved; + + // + // Update UPD:DqPinsInterleaved + // + FspmUpd->FspmConfig.CaVrefConfig = MemConfig->CaVrefConfig; + + // + // Update UPD:MemorySpdPtrXX + // + InternalUpdateSpdData (FspmUpd, MemConfigNoCrc, MiscPeiPreMemConfig); + + // + // Update UPD:MemorySpdDataLen + // + FspmUpd->FspmConfig.MemorySpdDataLen = SA_MC_MAX_SPD_SIZE; + + // + // Update UPD:PlatformMemorySize + // + // + // @todo: This value is used since #183932. Revisit. + // + FspmUpd->FspmConfig.PlatformMemorySize = MemConfigNoCrc->PlatformMemorySize; + FspmUpd->FspmConfig.SaGv = MemConfig->SaGv; + FspmUpd->FspmConfig.RMT = (UINT8) MemConfig->RMT; + FspmUpd->FspmConfig.DdrFreqLimit = MemConfig->DdrFreqLimit; + + FspmUpd->FspmConfig.SpdProfileSelected = MemConfig->SpdProfileSelected; + FspmUpd->FspmConfig.VddVoltage = MemConfig->VddVoltage; + FspmUpd->FspmConfig.RefClk = MemConfig->RefClk; + FspmUpd->FspmConfig.Ratio = MemConfig->Ratio; + FspmUpd->FspmConfig.OddRatioMode = (UINT8) MemConfig->OddRatioMode; + FspmUpd->FspmConfig.tCL = (UINT8) MemConfig->tCL; + FspmUpd->FspmConfig.tCWL = (UINT8) MemConfig->tCWL; + FspmUpd->FspmConfig.tFAW = MemConfig->tFAW; + FspmUpd->FspmConfig.tRAS = MemConfig->tRAS; + FspmUpd->FspmConfig.tRCDtRP = (UINT8) MemConfig->tRCDtRP; + FspmUpd->FspmConfig.tREFI = MemConfig->tREFI; + FspmUpd->FspmConfig.tRFC = MemConfig->tRFC; + FspmUpd->FspmConfig.tRRD = (UINT8) MemConfig->tRRD; + FspmUpd->FspmConfig.tRTP = (UINT8) MemConfig->tRTP; + FspmUpd->FspmConfig.tWR = (UINT8) MemConfig->tWR; + FspmUpd->FspmConfig.tWTR = (UINT8) MemConfig->tWTR; + FspmUpd->FspmConfig.NModeSupport = MemConfig->NModeSupport; + FspmUpd->FspmConfig.DllBwEn0 = MemConfig->DllBwEn0; + FspmUpd->FspmConfig.DllBwEn1 = MemConfig->DllBwEn1; + FspmUpd->FspmConfig.DllBwEn2 = MemConfig->DllBwEn2; + FspmUpd->FspmConfig.DllBwEn3 = MemConfig->DllBwEn3; + FspmUpd->FspmConfig.EvLoader = (UINT8) MemConfig->EvLoader; + + // + // Update UPD:SmramMask + // + if (MemConfig != NULL) { + FspmUpd->FspmConfig.SmramMask = MemConfig->SmramMask; + } + + return EFI_SUCCESS; +} + +/** + Performs FSP SA PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSaPolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ) +{ + EFI_STATUS Status; + SI_POLICY_PPI *SiPolicyPpi; + GRAPHICS_PEI_CONFIG *GtConfig; + VTD_CONFIG *Vtd; + // + // Locate SiPolicyPpi + // + SiPolicyPpi = NULL; + Status = PeiServicesLocatePpi( + &gSiPolicyPpiGuid, + 0, + NULL, + (VOID **)&SiPolicyPpi + ); + if ((Status == EFI_SUCCESS) && (SiPolicyPpi != NULL)) { + GtConfig = NULL; + Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid, (VOID *) &GtConfig); + ASSERT_EFI_ERROR (Status); + + Vtd = NULL; + Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gVtdConfigGuid, (VOID *) &Vtd); + ASSERT_EFI_ERROR (Status); + + } + + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP UpdatePeiSaPolicy\n")); + if (GtConfig != NULL) { + // + // For FSP, FspsUpd->FspsConfig.PeiGraphicsPeimInit is always enabled as default. + // + FspsUpd->FspsConfig.PeiGraphicsPeimInit = (UINT8) GtConfig->PeiGraphicsPeimInit; // SA: InternalOnly: For Internal validation we still need to enable both Enable/Disable Cases + + // + // Update UPD: VBT & LogoPtr + // + FspsUpd->FspsConfig.GraphicsConfigPtr = (UINT32) GtConfig->GraphicsConfigPtr; + DEBUG(( DEBUG_INFO, "VbtPtr from GraphicsPeiConfig is 0x%x\n", FspsUpd->FspsConfig.GraphicsConfigPtr)); + + FspsUpd->FspsConfig.LogoPtr = (UINT32) GtConfig->LogoPtr; + FspsUpd->FspsConfig.LogoSize = GtConfig->LogoSize; + DEBUG(( DEBUG_INFO, "LogoPtr from PeiFspSaPolicyInit GraphicsPeiConfig is 0x%x\n", FspsUpd->FspsConfig.LogoPtr)); + DEBUG(( DEBUG_INFO, "LogoSize from PeiFspSaPolicyInit GraphicsPeiConfig is 0x%x\n", FspsUpd->FspsConfig.LogoSize)); + + + + } + if (Vtd != NULL) { + FspsUpd->FspsConfig.X2ApicOptOut = (UINT8) Vtd->X2ApicOptOut; + FspsUpd->FspsConfig.VtdBaseAddress[0] = Vtd->BaseAddress[0]; + FspsUpd->FspsConfig.VtdBaseAddress[1] = Vtd->BaseAddress[1]; + FspsUpd->FspsTestConfig.VtdDisable = (UINT8) Vtd->VtdDisable; + } + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspSiPolicyInitLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspSiPolicyInitLib.c new file mode 100644 index 0000000000..49601b1496 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspSiPolicyInitLib.c @@ -0,0 +1,51 @@ +/** @file + Implementation of Fsp SI Policy Initialization. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include + +/** + Performs FSP SI PEI Policy initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSiPolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + EFI_STATUS Status; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + + // + // Locate SiPolicyPpi + // + SiPreMemPolicyPpi = NULL; + Status = PeiServicesLocatePpi ( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPreMemPolicyPpi + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiPolicyInit.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiPolicyInit.c new file mode 100644 index 0000000000..abed092c46 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiPolicyInit.c @@ -0,0 +1,47 @@ +/** @file + This file is SampleCode for Intel PEI Platform Policy initialization. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "PeiPolicyInit.h" + +/** + Initialize Intel PEI Platform Policy + +**/ +VOID +EFIAPI +PeiPolicyInit ( + VOID + ) +{ + EFI_STATUS Status; + SI_POLICY_PPI *SiPolicyPpi; + + // + // Call SiCreateConfigBlocks to initialize Silicon Policy structure + // and get all Intel default policy settings. + // + Status = SiCreateConfigBlocks (&SiPolicyPpi); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) { + return; + } + + // + // Install SiPolicyPpi. + // While installed, RC assumes the Policy is ready and finalized. So please + // update and override any setting before calling this function. + // + Status = SiInstallPolicyPpi (SiPolicyPpi); + ASSERT_EFI_ERROR (Status); +} diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiPolicyInit.h b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiPolicyInit.h new file mode 100644 index 0000000000..e85724411a --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiPolicyInit.h @@ -0,0 +1,24 @@ +/** @file + Header file for the PolicyInitPei PEIM. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PEI_POLICY_INIT_H_ +#define _PEI_POLICY_INIT_H_ + +#include +#include +#include + +#include "PeiSiPolicyInit.h" + +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiPolicyInitLib.h b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiPolicyInitLib.h new file mode 100644 index 0000000000..b5a7f4eef3 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiPolicyInitLib.h @@ -0,0 +1,37 @@ +/** @file + Header file for the PolicyInitPei Library. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _POLICY_INIT_PEI_LIB_H_ +#define _POLICY_INIT_PEI_LIB_H_ + +/** + Initialize Intel PEI Platform Policy + +**/ +VOID +EFIAPI +PeiPolicyInitPreMem ( + VOID + ); + +/** + Initialize Intel PEI Platform Policy + +**/ +VOID +EFIAPI +PeiPolicyInit ( + VOID + ); +#endif diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiPolicyInitPreMem.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiPolicyInitPreMem.c new file mode 100644 index 0000000000..35baba3183 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiPolicyInitPreMem.c @@ -0,0 +1,48 @@ +/** @file + This file is SampleCode for Intel PEI Platform Policy initialization. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "PeiPolicyInit.h" + +/** + Initialize Intel PEI Platform Policy + +**/ +VOID +EFIAPI +PeiPolicyInitPreMem ( + VOID + ) +{ + EFI_STATUS Status; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + + DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Start in Pre-Memory...\n")); + // + // Call SiCreatePreMemConfigBlocks to initialize platform policy structure + // and get all intel default policy settings. + // + Status = SiCreatePreMemConfigBlocks (&SiPreMemPolicyPpi); + ASSERT_EFI_ERROR (Status); + + // + // Install SiPreMemPolicyPpi. + // While installed, RC assumes the Policy is ready and finalized. So please + // update and override any setting before calling this function. + // + Status = SiPreMemInstallPolicyPpi (SiPreMemPolicyPpi); + ASSERT_EFI_ERROR (Status); + + + DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in Pre-Memory\n")); +} diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiPolicyInit.h b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiPolicyInit.h new file mode 100644 index 0000000000..4f4a80b9ae --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiPolicyInit.h @@ -0,0 +1,24 @@ +/** @file + Header file for the PeiSiPolicyInit + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SI_POLICY_INIT_PEI_H_ +#define _SI_POLICY_INIT_PEI_H_ + +#include +#include +#include +#include +#include + +#endif // _SI_POLICY_INIT_PEI_H_ diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf new file mode 100644 index 0000000000..7b91ac3fab --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf @@ -0,0 +1,146 @@ +### @file +# Library functions for Fsp Policy Initialization Library. +# +# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiSiliconPolicyInitLibFsp + FILE_GUID = 2CB87D67-D1A4-4CD3-8CD7-91A1FA1DF6E0 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = SiliconPolicyInitLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 +# + +################################################################################ +# +# Sources Section - list of files that are required for the build to succeed. +# +################################################################################ + +[Sources] + PeiFspPolicyInitLib.c + PeiFspSiPolicyInitLib.c + PeiFspPchPolicyInitLib.c + PeiFspCpuPolicyInitLib.c + PeiFspMePolicyInitLib.c + PeiFspSaPolicyInitLib.c + PeiFspMiscUpdInitLib.c + + PeiPolicyInitPreMem.c + PeiPolicyInit.c + PeiPolicyInit.h + +################################################################################ +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +################################################################################ + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + KabylakeSiliconPkg/SiPkg.dec + KabylakeFspBinPkg/KabylakeFspBinPkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + IoLib + PeiServicesLib + PcdLib + SmbusLib + MmPciLib + ConfigBlockLib + MemoryAllocationLib + DebugPrintErrorLevelLib + +[Pcd] + gSiPkgTokenSpaceGuid.PcdTsegSize ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CONSUMES + +[Ppis] + gSiPolicyPpiGuid ## CONSUMES + gSiPreMemPolicyPpiGuid ## CONSUMES + +[Guids] + gTraceHubPreMemConfigGuid ## CONSUMES + gSmbusPreMemConfigGuid ## CONSUMES + gDciPreMemConfigGuid ## CONSUMES + gHpetPreMemConfigGuid ## CONSUMES + gHsioPciePreMemConfigGuid ## CONSUMES + gHsioSataPreMemConfigGuid ## CONSUMES + gHsioPreMemConfigGuid ## CONSUMES + gPcieRpPreMemConfigGuid ## CONSUMES + gLpcPreMemConfigGuid ## CONSUMES + gPchGeneralPreMemConfigGuid ## CONSUMES + gWatchDogPreMemConfigGuid ## CONSUMES + gLanConfigGuid ## CONSUMES + gPcieRpConfigGuid ## CONSUMES + gSataConfigGuid ## CONSUMES + gHdAudioConfigGuid ## CONSUMES + gCio2ConfigGuid ## CONSUMES + gScsConfigGuid ## CONSUMES + gIshConfigGuid ## CONSUMES + gSpiConfigGuid ## CONSUMES + gSataConfigGuid ## CONSUMES + gUsbConfigGuid ## CONSUMES + gSerialIoConfigGuid ## CONSUMES + gInterruptConfigGuid ## CONSUMES + gLockDownConfigGuid ## CONSUMES + gSaMiscPeiPreMemConfigGuid ## PRODUCES + gMemoryConfigGuid ## CONSUMES + gMemoryConfigNoCrcGuid ## CONSUMES + gGraphicsPeiConfigGuid ## CONSUMES + gMePeiPreMemConfigGuid ## CONSUMES + gMePeiConfigGuid ## CONSUMES + gAmtPeiConfigGuid ## CONSUMES + gDmiConfigGuid ## CONSUMES + gFlashProtectionConfigGuid ## CONSUMES + gIoApicConfigGuid ## CONSUMES + gPmConfigGuid ## CONSUMES + gP2sbConfigGuid ## CONSUMES + gPchGeneralConfigGuid ## CONSUMES + gPort61ConfigGuid ## CONSUMES + gSerialIrqConfigGuid ## CONSUMES + gThermalConfigGuid ## CONSUMES + gCpuSecurityPreMemConfigGuid ## CONSUMES + gCpuTxtPreMemConfigGuid ## CONSUMES + gCpuConfigGuid ## CONSUMES + gBiosGuardConfigGuid ## CONSUMES + gCpuOverclockingPreMemConfigGuid ## CONSUMES + gCpuConfigLibPreMemConfigGuid ## CONSUMES + gCpuSgxConfigGuid ## CONSUMES + gCpuPowerMgmtBasicConfigGuid ## CONSUMES + gCpuPowerMgmtCustomConfigGuid ## CONSUMES + gCpuTestConfigGuid ## CONSUMES + gCpuPidTestConfigGuid ## CONSUMES + gCpuPowerMgmtTestConfigGuid ## CONSUMES + gSmramCpuDataHeaderGuid ## CONSUMES + gFspReservedMemoryResourceHobTsegGuid ## CONSUMES -- cgit v1.2.3