From 274873eca9d33d90335ad011f43a6afffb100110 Mon Sep 17 00:00:00 2001 From: Jiewen Yao Date: Thu, 21 Sep 2017 21:29:43 +0800 Subject: MinKabylake: Reorg FV Cc: Michael A Kubacki Cc: Amy Chan Cc: Chasel Chiu Cc: Brett Wang Cc: Daocheng Bu Cc: Isaac W Oram Cc: Rangasai V Chaganty Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao Reviewed-by: Michael A Kubacki Reviewed-by: Amy Chan Reviewed-by: Isaac W Oram --- .../Include/Fdf/FlashMapInclude.fdf | 34 +- .../KabylakeRvp3/OpenBoardPkg.dsc | 62 +++- .../KabylakeRvp3/OpenBoardPkg.fdf | 410 ++++++++++++--------- .../KabylakeRvp3/OpenBoardPkgPcd.dsc | 8 +- .../KabylakeOpenBoardPkg/KabylakeRvp3/bld.bat | 2 +- 5 files changed, 298 insertions(+), 218 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf b/Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf index 91ca770932..3238a63a0a 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf +++ b/Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf @@ -30,19 +30,21 @@ SET gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = 0x0001E000 SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize = 0x00002000 # SET gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = 0x00020000 # Flash addr (0xFF820000) SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = 0x00020000 # -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvMain2Offset = 0x00080000 # Flash addr (0xFF880000) -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvMain2Size = 0x00090000 # -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvMainOffset = 0x00110000 # Flash addr (0xFF910000) -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvMainSize = 0x00270000 # -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery3Offset = 0x00380000 # Flash addr (0xFFB80000) -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery3Size = 0x00170000 # -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvFspsOffset = 0x004F0000 # Flash addr (0xFFCF0000) -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvFspsSize = 0x00050000 # -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset = 0x00550000 # Flash addr (0xFFD50000) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = 0x000B0000 # -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Offset = 0x00600000 # Flash addr (0xFFE00000) -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Size = 0x00120000 # -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvFspmtOffset = 0x00720000 # Flash addr (0xFFF20000) -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvFspmtSize = 0x000C0000 # -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryOffset = 0x007E0000 # Flash addr (0xFFFE0000) -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoverySize = 0x00020000 # +SET gPlatformModuleTokenSpaceGuid.PcdFlashFvAdvancedOffset = 0x00040000 # Flash addr (0xFF840000) +SET gPlatformModuleTokenSpaceGuid.PcdFlashFvAdvancedSize = 0x00060000 # +SET gPlatformModuleTokenSpaceGuid.PcdFlashFvSecurityOffset = 0x000A0000 # Flash addr (0xFF8A0000) +SET gPlatformModuleTokenSpaceGuid.PcdFlashFvSecuritySize = 0x00070000 # +SET gPlatformModuleTokenSpaceGuid.PcdFlashFvOsBootOffset = 0x00110000 # Flash addr (0xFF910000) +SET gPlatformModuleTokenSpaceGuid.PcdFlashFvOsBootSize = 0x00090000 # +SET gPlatformModuleTokenSpaceGuid.PcdFlashFvUefiBootOffset = 0x001A0000 # Flash addr (0xFF9A0000) +SET gPlatformModuleTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x001E0000 # +SET gPlatformModuleTokenSpaceGuid.PcdFlashFvPostMemoryOffset = 0x00380000 # Flash addr (0xFFB80000) +SET gPlatformModuleTokenSpaceGuid.PcdFlashFvPostMemorySize = 0x00180000 # +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset = 0x00500000 # Flash addr (0xFFD00000) +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = 0x000A0000 # +SET gPlatformModuleTokenSpaceGuid.PcdFlashFvFspSOffset = 0x005A0000 # Flash addr (0xFFDA0000) +SET gPlatformModuleTokenSpaceGuid.PcdFlashFvFspSSize = 0x00060000 # +SET gPlatformModuleTokenSpaceGuid.PcdFlashFvFspMTOffset = 0x00600000 # Flash addr (0xFFE00000) +SET gPlatformModuleTokenSpaceGuid.PcdFlashFvFspMTSize = 0x000C0000 # +SET gPlatformModuleTokenSpaceGuid.PcdFlashFvPreMemoryOffset = 0x006C0000 # Flash addr (0xFFEC0000) +SET gPlatformModuleTokenSpaceGuid.PcdFlashFvPreMemorySize = 0x00140000 # diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc index 925126dc38..e8541ebc0a 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc @@ -58,12 +58,6 @@ # DEFINE BIOS_SIZE_OPTION = SIZE_70 - DEFINE TRACEHUB = - EDK_GLOBAL TRACEHUB = - - DEFINE COV_TOOLS = VS2008 - - ################################################################################ # # SKU Identification section - list of all SKU IDs supported by this @@ -176,8 +170,19 @@ [Components.IA32] +# +# Common +# !include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc +# +# Silicon +# +!include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc + +# +# Platform +# $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf { !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE @@ -186,6 +191,7 @@ NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf !endif } + IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf { @@ -195,28 +201,37 @@ NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf !endif } - - IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf + IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf +# +# Security +# + !if gPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf !endif -# -# Silicon Init Package -# -!include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc + IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf + IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf [Components.X64] +# +# Common +# !include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc + + ShellBinPkg/UefiShell/UefiShell.inf # -# Silicon Init Package +# Silicon # !include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc +# +# Platform +# $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf { @@ -225,7 +240,15 @@ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf !endif } + IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf + $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf + + $(PLATFORM_PACKAGE)/Test/TestPointDumpApp/TestPointDumpApp.inf + +# +# OS Boot +# !if gPlatformModuleTokenSpaceGuid.PcdBootToShellOnly == FALSE $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf { @@ -256,12 +279,10 @@ $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf !endif - IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf - $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf - +# +# Security +# $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf - - $(PLATFORM_PACKAGE)/Test/TestPointDumpApp/TestPointDumpApp.inf !if gPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf @@ -269,9 +290,10 @@ IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf +# +# Other +# $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf - - ShellBinPkg/UefiShell/UefiShell.inf !include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc !include OpenBoardPkgBuildOption.dsc diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf index 2b5bc3bd51..e4e4be45e4 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf @@ -46,7 +46,7 @@ DEFINE SIPKG_PEI_BIN = INF # Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because macro expression is not supported. # So, PlatformSecLib uses PcdFlashAreaBaseAddress + PcdNemCodeCacheBase to get the real CodeCache base address. -SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase = $(gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Offset) +SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase = $(gPlatformModuleTokenSpaceGuid.PcdFlashFvPreMemoryOffset) SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset) SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 @@ -54,15 +54,13 @@ SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpac SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset) SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset = 0x60 -SET gPlatformModuleTokenSpaceGuid.PcdFlashMicrocodeFvBase = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase -SET gPlatformModuleTokenSpaceGuid.PcdFlashMicrocodeFvSize = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize -SET gPlatformModuleTokenSpaceGuid.PcdFlashMicrocodeFvOffset = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset +SET gPlatformModuleTokenSpaceGuid.PcdFlashFvMicrocodeBase = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase +SET gPlatformModuleTokenSpaceGuid.PcdFlashFvMicrocodeSize = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize +SET gPlatformModuleTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize -SET gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress -SET gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvFspWrapperBase = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery3Offset) -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvFspWrapperSize = $(gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery3Size) +SET gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress +SET gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize ################################################################################ # # Following are lists of FD Region layout which correspond to the locations of different @@ -76,7 +74,7 @@ SET gPlatformModuleTokenSpaceGuid.PcdFlashFvFspWrapperSize = $(gPlatformModuleTo # Offset|Size # PcdOffsetCName|PcdSizeCName # RegionType -# Fv Size can be adjusted; FVMAIN_COMPACT can be reduced to 0x120000, and FV_RECOVERY can be enlarged to 0x80000 +# Fv Size can be adjusted # ################################################################################ gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize @@ -138,45 +136,44 @@ gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTo gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize #NV_FTW_SPARE +gPlatformModuleTokenSpaceGuid.PcdFlashFvAdvancedOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvAdvancedSize +gPlatformModuleTokenSpaceGuid.PcdFlashFvAdvancedBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvAdvancedSize +FV = FvAdvanced -gPlatformModuleTokenSpaceGuid.PcdFlashFvMain2Offset|gPlatformModuleTokenSpaceGuid.PcdFlashFvMain2Size -gPlatformModuleTokenSpaceGuid.PcdFlashFvMain2Base|gPlatformModuleTokenSpaceGuid.PcdFlashFvMain2Size -FV = FVMAIN2_COMPACT +gPlatformModuleTokenSpaceGuid.PcdFlashFvSecurityOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvSecuritySize +gPlatformModuleTokenSpaceGuid.PcdFlashFvSecurityBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvSecuritySize +FV = FvSecurity -gPlatformModuleTokenSpaceGuid.PcdFlashFvMainOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvMainSize -gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvMainSize -FV = FVMAIN_COMPACT +gPlatformModuleTokenSpaceGuid.PcdFlashFvOsBootOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvOsBootSize +gPlatformModuleTokenSpaceGuid.PcdFlashFvOsBootBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvOsBootSize +FV = FvOsBoot -gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery3Offset|gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery3Size -gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery3Base|gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery3Size -#FvRecovery3 -FV = FVRECOVERY3_COMPACT - -gPlatformModuleTokenSpaceGuid.PcdFlashFvFspsOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvFspsSize -gPlatformModuleTokenSpaceGuid.PcdFlashFvFspsBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvFspsSize -# FSP_S Section -FV=FSP_S +gPlatformModuleTokenSpaceGuid.PcdFlashFvUefiBootOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvUefiBootSize +gPlatformModuleTokenSpaceGuid.PcdFlashFvUefiBootBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvUefiBootSize +FV = FvUefiBoot +gPlatformModuleTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvPostMemorySize +gPlatformModuleTokenSpaceGuid.PcdFlashFvPostMemoryBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvPostMemorySize +FV = FvPostMemory gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize #Microcode -FV = MICROCODE_FV +FV = FvMicrocode -gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Offset|gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Size -gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Base|gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Size -#FvRecovery -FV = FVRECOVERY2 +gPlatformModuleTokenSpaceGuid.PcdFlashFvFspSOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvFspSSize +gPlatformModuleTokenSpaceGuid.PcdFlashFvFspSBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvFspSSize +# FSP_S Section +FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_S.fd -gPlatformModuleTokenSpaceGuid.PcdFlashFvFspmtOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvFspmtSize -gPlatformModuleTokenSpaceGuid.PcdFlashFvFspmtBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvFspmtSize +gPlatformModuleTokenSpaceGuid.PcdFlashFvFspMTOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvFspMTSize +gPlatformModuleTokenSpaceGuid.PcdFlashFvFspMTBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvFspMTSize # FSP_M & T Section FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_M_T.fd -gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoverySize -gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoverySize -#FvRecovery -FV = FVRECOVERY +gPlatformModuleTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvPreMemorySize +gPlatformModuleTokenSpaceGuid.PcdFlashFvPreMemoryBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvPreMemorySize +FV = FvPreMemory ################################################################################ # @@ -188,8 +185,8 @@ FV = FVRECOVERY # module statements. # ################################################################################ -[FV.MICROCODE_FV] -BlockSize = $(FLASH_BLOCK_SIZE) +[FV.FvMicrocode] +BlockSize = $(FLASH_BLOCK_SIZE) FvAlignment = 16 ERASE_POLARITY = 1 MEMORY_MAPPED = TRUE @@ -211,11 +208,34 @@ FILE RAW = 197DB236-F856-4924-90F8-CDF12FB875F3 { $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/X64/MicrocodeUpdates.bin } +[FV.FvPreMemory] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = FC8FE6B5-CD9B-411E-BD8F-31824D0CDE3D +!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf -[FV.FSP_S] +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf +INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf + +[FV.FvPostMemoryUncompact] BlockSize = $(FLASH_BLOCK_SIZE) -FvAlignment = 16 #FV alignment and FV attributes setting. +FvAlignment = 16 ERASE_POLARITY = 1 MEMORY_MAPPED = TRUE STICKY_WRITE = TRUE @@ -231,14 +251,26 @@ READ_ENABLED_CAP = TRUE READ_STATUS = TRUE READ_LOCK_CAP = TRUE READ_LOCK_STATUS = TRUE +FvNameGuid = 7C4DCFC6-AECA-4707-85B9-FD4B2EEA49E7 + +!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePostMemoryInclude.fdf -FILE FV_IMAGE = 3417F275-4CF1-42D8-A0C3-B3F60779dF4D { -# Use Padded file which adds 0xC bytes of data (Note: Section will add 4 bytes of SECTION Header). This is done to align the FSP Header to 16 bytes - SECTION RAW = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_S_padded.fd +# Init Board Config PCD +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf +INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf + +!if gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable == TRUE +FILE FREEFORM = 4ad46122-ffeb-4a52-bfb0-518cfca02db0 { + SECTION RAW = $(PLATFORM_FSP_BIN_PACKAGE)/SampleCode/Vbt/Vbt.bin + SECTION UI = "Vbt" } +FILE FREEFORM = 7BB28B99-61BB-11D5-9A5D-0090273FC14D { + SECTION RAW = MdeModulePkg/Logo/Logo.bmp +} +!endif # PcdPeiDisplayEnable -[FV.FVRECOVERY3_COMPACT] -BlockSize = $(FLASH_BLOCK_SIZE) +[FV.FvPostMemory] +BlockSize = $(FLASH_BLOCK_SIZE) FvAlignment = 16 ERASE_POLARITY = 1 MEMORY_MAPPED = TRUE @@ -255,20 +287,17 @@ READ_ENABLED_CAP = TRUE READ_STATUS = TRUE READ_LOCK_CAP = TRUE READ_LOCK_STATUS = TRUE +FvNameGuid = 9DFE49DB-8EF0-4D9C-B273-0036144DE917 FILE FV_IMAGE = 244FAAF4-FAE1-4892-8B7D-7EF84CBFA709 { -!if $(TARGET) == DEBUG SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { - SECTION FV_IMAGE = FVRECOVERY3 + SECTION FV_IMAGE = FvPostMemoryUncompact } -!else - SECTION FV_IMAGE = FVRECOVERY3 -!endif } -[FV.FVRECOVERY3] -BlockSize = $(FLASH_BLOCK_SIZE) -FvAlignment = 16 #FV alignment and FV attributes setting. +[FV.FvUefiBootUncompact] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 ERASE_POLARITY = 1 MEMORY_MAPPED = TRUE STICKY_WRITE = TRUE @@ -284,42 +313,44 @@ READ_ENABLED_CAP = TRUE READ_STATUS = TRUE READ_LOCK_CAP = TRUE READ_LOCK_STATUS = TRUE -FvNameGuid = 8579D1CA-45E8-4f1c-A789-FFA770672099 - -################################################################################ -# -# The INF statements point to EDK component and EDK II module INF files, which will be placed into this FV image. -# Parsing tools will scan the INF file to determine the type of component or module. -# The component or module type is used to reference the standard rules -# defined elsewhere in the FDF file. -# -# The format for INF statements is: -# INF $(PathAndInfFileName) -# -################################################################################ - +FvNameGuid = A881D567-6CB0-4eee-8435-2E72D33E45B5 -# Init Board Config PCD -INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf -INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf +INF ShellBinPkg/UefiShell/UefiShell.inf -!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePeiPostMemInclude.fdf +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf +INF IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf -!if gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable == TRUE -FILE FREEFORM = 4ad46122-ffeb-4a52-bfb0-518cfca02db0 { - SECTION RAW = $(PLATFORM_FSP_BIN_PACKAGE)/SampleCode/Vbt/Vbt.bin - SECTION UI = "Vbt" -} -FILE FREEFORM = 7BB28B99-61BB-11D5-9A5D-0090273FC14D { - SECTION RAW = MdeModulePkg/Logo/Logo.bmp -} -!endif # PcdPeiDisplayEnable +[FV.FvUefiBoot] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 0496D33D-EA79-495C-B65D-ABF607184E3B +FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvUefiBootUncompact + } + } -[FV.FVRECOVERY2] -BlockSize = $(FLASH_BLOCK_SIZE) -FvAlignment = 16 #FV alignment and FV attributes setting. +[FV.FvOsBootUncompact] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 ERASE_POLARITY = 1 MEMORY_MAPPED = TRUE STICKY_WRITE = TRUE @@ -335,42 +366,27 @@ READ_ENABLED_CAP = TRUE READ_STATUS = TRUE READ_LOCK_CAP = TRUE READ_LOCK_STATUS = TRUE -FvNameGuid = B73FE497-B92E-416e-8326-45AD0D270091 +FvNameGuid = A0F04529-B715-44C6-BCA4-2DEBDD01EEEC -################################################################################ -# -# The INF statements point to EDK component and EDK II module INF files, which will be placed into this FV image. -# Parsing tools will scan the INF file to determine the type of component or module. -# The component or module type is used to reference the standard rules -# defined elsewhere in the FDF file. -# -# The format for INF statements is: -# INF $(PathAndInfFileName) -# -################################################################################ - ## - # PEI Apriori file example, more PEIM module added later. - ## -APRIORI PEI { -} +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf - ## - # PEI Phase modules - ## - -INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf +!if gPlatformModuleTokenSpaceGuid.PcdBootToShellOnly == FALSE +INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf +INF $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf -!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePeiPreMemInclude.fdf +INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf +INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf -!if gPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE -INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf -!endif +INF RuleOverride = DRIVER_ACPITABLE $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf -INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf +INF $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf -[FV.FVRECOVERY] -BlockSize = $(FLASH_BLOCK_SIZE) -FvAlignment = 16 #FV alignment and FV attributes setting. +!endif + +[FV.FvLateSilicon] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 ERASE_POLARITY = 1 MEMORY_MAPPED = TRUE STICKY_WRITE = TRUE @@ -386,14 +402,26 @@ READ_ENABLED_CAP = TRUE READ_STATUS = TRUE READ_LOCK_CAP = TRUE READ_LOCK_STATUS = TRUE -FvNameGuid = BA34AA5B-110E-4B10-B729-E559EFD075D3 +FvNameGuid = 97F09B89-9E83-4DDC-A3D1-10C4AF539D1E + +!if gPlatformModuleTokenSpaceGuid.PcdBootToShellOnly == FALSE +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxe.inf +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf -!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePeiBfvInclude.fdf +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SmmAccess/Dxe/SmmAccess.inf +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSmiDispatcher.inf +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmControl.inf +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/Spi/Smm/PchSpiSmm.inf +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.inf + +INF RuleOverride = ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaAcpiTables.inf +INF RuleOverride = ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf -[FV.FVMAIN2] +!endif + +[FV.FvOsBoot] BlockSize = $(FLASH_BLOCK_SIZE) -FvForceRebase = FALSE FvAlignment = 16 ERASE_POLARITY = 1 MEMORY_MAPPED = TRUE @@ -410,15 +438,23 @@ READ_ENABLED_CAP = TRUE READ_STATUS = TRUE READ_LOCK_CAP = TRUE READ_LOCK_STATUS = TRUE -FvNameGuid = B92CF322-8AFA-4aa4-B946-005DF1D69778 - - -#INF ShellBinPkg/UefiShell/UefiShell.inf +FvNameGuid = 13BF8810-75FD-4B1A-91E6-E16C4201F80A +FILE FV_IMAGE = B9020753-84A8-4BB6-947C-CE7D41F5CE39 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvOsBootUncompact + } + } + +FILE FV_IMAGE = D4632741-510C-44E3-BE21-C3D6D7881485 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvLateSilicon + } + } -[FV.FVMAIN2_COMPACT] -BlockSize = $(FLASH_BLOCK_SIZE) -FvAlignment = 16 +[FV.FvSecurityPreMemory] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 #FV alignment and FV attributes setting. ERASE_POLARITY = 1 MEMORY_MAPPED = TRUE STICKY_WRITE = TRUE @@ -434,16 +470,13 @@ READ_ENABLED_CAP = TRUE READ_STATUS = TRUE READ_LOCK_CAP = TRUE READ_LOCK_STATUS = TRUE +FvNameGuid = 9B7FA59D-71C6-4A36-906E-9725EA6ADD5B -FILE FV_IMAGE = 4E35FD93-9C72-4c15-8C4B-E77F1DB2D792 { - SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { - SECTION FV_IMAGE = FVMAIN2 - } -} +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPreMemoryInclude.fdf -[FV.FVMAIN] -BlockSize = $(FLASH_BLOCK_SIZE) -FvAlignment = 16 +[FV.FvSecurityPostMemory] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 #FV alignment and FV attributes setting. ERASE_POLARITY = 1 MEMORY_MAPPED = TRUE STICKY_WRITE = TRUE @@ -459,68 +492,60 @@ READ_ENABLED_CAP = TRUE READ_STATUS = TRUE READ_LOCK_CAP = TRUE READ_LOCK_STATUS = TRUE -FvNameGuid = A881D567-6CB0-4eee-8435-2E72D33E45B5 - - ## - # DXE Apriori file example, more DXE module added later. - ## - -APRIORI DXE { -} +FvNameGuid = 4199E560-54AE-45E5-91A4-F7BC3804E14A - ## - # DXE Phase modules - ## - -!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreDxeInclude.fdf - -INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPostMemoryInclude.fdf -!if gPlatformModuleTokenSpaceGuid.PcdBootToShellOnly == FALSE -INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf +INF IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf -$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxe.inf -$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf +!if gPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE +INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf +!endif -INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf -$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SmmAccess/Dxe/SmmAccess.inf +INF IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf + +[FV.FvSecurityLate] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = F753FE9A-EEFD-485B-840B-E032D538102C -$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSmiDispatcher.inf -$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmControl.inf -$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/Spi/Smm/PchSpiSmm.inf -$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.inf +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityLateInclude.fdf -INF $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf -!endif +INF IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf !if gPlatformModuleTokenSpaceGuid.PcdBootToShellOnly == FALSE -INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf -INF RuleOverride = DRIVER_ACPITABLE $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf -INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf - -INF RuleOverride = ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaAcpiTables.inf -INF RuleOverride = ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf - -INF $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf INF $(PLATFORM_SI_PACKAGE)/Hsti/Dxe/HstiSiliconDxe.inf -INF $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf - !endif -INF IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf +!if gPlatformModuleTokenSpaceGuid.PcdBootToShellOnly == FALSE + +INF $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf !if gPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE -INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf +INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf !endif -INF IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf - -INF ShellBinPkg/UefiShell/UefiShell.inf +!endif -[FV.FVMAIN_COMPACT] -BlockSize = $(FLASH_BLOCK_SIZE) +[FV.FvSecurity] +BlockSize = $(FLASH_BLOCK_SIZE) FvAlignment = 16 ERASE_POLARITY = 1 MEMORY_MAPPED = TRUE @@ -537,13 +562,44 @@ READ_ENABLED_CAP = TRUE READ_STATUS = TRUE READ_LOCK_CAP = TRUE READ_LOCK_STATUS = TRUE +FvNameGuid = 5A9A8B4E-149A-4CB2-BDC7-C8D62DE2C8CF -FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { +FILE FV_IMAGE = 757CC075-1428-423D-A73C-22639706C119 { + SECTION FV_IMAGE = FvSecurityPreMemory + } + +FILE FV_IMAGE = 80BB8482-44D5-4BEC-82B5-8D87A933830B { SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { - SECTION FV_IMAGE = FVMAIN + SECTION FV_IMAGE = FvSecurityPostMemory } } +FILE FV_IMAGE = C83522D9-80A1-4D95-8C25-3F1370497406 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvSecurityLate + } + } + +[FV.FvAdvanced] +BlockSize = $(FLASH_BLOCK_SIZE) +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = B23E7388-9953-45C7-9201-0473DDE5487A + ################################################################################ # # Rules are use with the [FV] section's module INF type to define diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc index c39c1335d9..3921ff76c3 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc @@ -52,7 +52,7 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000 gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800 gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400 - gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxFvSupported|10 + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxFvSupported|30 gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeimPerFv|60 @@ -117,8 +117,8 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 gPlatformModuleTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x80 !endif - gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0xFFF7F000 - gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0xFFF20000 + gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0xFFE5F000 + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0xFFE00000 ## Specifies max supported number of Logical Processors. # @Prompt Configure max supported number of Logical Processorss @@ -190,7 +190,7 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 !endif [PcdsDynamicDefault] - gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0xFFCF0070 + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0xFFDA0000 [PcdsDynamicDefault.common.DEFAULT] gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0 diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/bld.bat b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/bld.bat index 1b777dc7aa..b02789f002 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/bld.bat +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/bld.bat @@ -50,7 +50,7 @@ del /f %WORKSPACE_FSP_BIN%\KabylakeFspBinPkg\Fsp_Rebased*.fd cd %WORKSPACE% if exist %WORKSPACE_PLATFORM%\%PROJECT%\OpenBoardPkgPcd.dsc attrib -r %WORKSPACE_PLATFORM%\%PROJECT%\OpenBoardPkgPcd.dsc -@call python %WORKSPACE_PLATFORM%\%PLATFORM_PACKAGE%\Tools\Fsp\RebaseAndPatchFspBinBaseAddress.py %WORKSPACE_PLATFORM%\%PLATFORM_BOARD_PACKAGE%\Include\Fdf\FlashMapInclude.fdf %WORKSPACE_FSP_BIN%\KabylakeFspBinPkg Fsp.fd %WORKSPACE_PLATFORM%\%PROJECT%\OpenBoardPkgPcd.dsc 0x70 +@call python %WORKSPACE_PLATFORM%\%PLATFORM_PACKAGE%\Tools\Fsp\RebaseAndPatchFspBinBaseAddress.py %WORKSPACE_PLATFORM%\%PLATFORM_BOARD_PACKAGE%\Include\Fdf\FlashMapInclude.fdf %WORKSPACE_FSP_BIN%\KabylakeFspBinPkg Fsp.fd %WORKSPACE_PLATFORM%\%PROJECT%\OpenBoardPkgPcd.dsc 0x0 @if %ERRORLEVEL% NEQ 0 ( @echo !!! ERROR:RebaseAndPatchFspBinBaseAddress failed!!! -- cgit v1.2.3