From 5e96ef6cdec8835eacdbe902309139ed07f33174 Mon Sep 17 00:00:00 2001 From: Jiewen Yao Date: Tue, 17 Oct 2017 13:22:45 +0800 Subject: Performance improvement. MemoryInit code will consume the DISB bit in PCH (DRAM Initialization Scratchpad Bit - GEN_PMCON_A[23]) to decide if it goes optimization path. With this change, the time of MemoryInit API is reduced from 10 seconad to 69 millisecond. Cc: Michael A Kubacki Cc: Amy Chan Cc: Chasel Chiu Cc: Brett Wang Cc: Daocheng Bu Cc: Isaac W Oram Cc: Rangasai V Chaganty Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao Reviewed-by: Amy Chan --- .../PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c index 0f7c6acb59..57a1846ad2 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c @@ -25,7 +25,9 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #include #include #include +#include #include +#include /** Performs FSP Misc UPD initialization. @@ -61,6 +63,14 @@ PeiFspMiscUpdUpdatePreMem ( DEBUG ((DEBUG_INFO, "MemoryConfig Size - 0x%x\n", VariableSize)); FspmUpd->FspmArchUpd.NvsBufferPtr = MemorySavedData; + if (FspmUpd->FspmArchUpd.NvsBufferPtr != NULL) { + // + // Set the DISB bit in PCH (DRAM Initialization Scratchpad Bit - GEN_PMCON_A[23]), + // after memory Data is saved to NVRAM. + // + PciOr32 ((UINTN)PCI_LIB_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_PMC, PCI_FUNCTION_NUMBER_PCH_PMC, R_PCH_PMC_GEN_PMCON_A), B_PCH_PMC_GEN_PMCON_A_DISB); + } + // // MOR // -- cgit v1.2.3