From 60d20bd0764bb0c78f56b43979f7ed409bed3fa2 Mon Sep 17 00:00:00 2001 From: Jiewen Yao Date: Mon, 28 Aug 2017 09:37:45 +0800 Subject: new policy design for open board. Cc: Michael A Kubacki Cc: Amy Chan Cc: Chasel Chiu Cc: Brett Wang Cc: Daocheng Bu Cc: Isaac W Oram Cc: Rangasai V Chaganty Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao Reviewed-by: Michael A Kubacki Reviewed-by: Amy Chan --- .../PeiFspPolicyUpdateLib/PcieDeviceTable.c | 121 ---------- .../PeiFspPolicyUpdateLib/PeiFspMiscUpdUpdateLib.c | 83 ------- .../PeiFspPolicyUpdateLib/PeiFspPolicyUpdateLib.c | 166 -------------- .../PeiFspPolicyUpdateLib.inf | 145 ------------ .../PeiFspPolicyUpdateLib/PeiPchPolicyUpdate.c | 159 ------------- .../PeiFspPolicyUpdateLib/PeiPchPolicyUpdate.h | 34 --- .../PeiPchPolicyUpdatePreMem.c | 254 --------------------- .../PeiFspPolicyUpdateLib/PeiSaPolicyUpdate.c | 90 -------- .../PeiFspPolicyUpdateLib/PeiSaPolicyUpdate.h | 36 --- .../PeiSaPolicyUpdatePreMem.c | 74 ------ .../PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c | 121 ++++++++++ .../PeiFspMiscUpdUpdateLib.c | 83 +++++++ .../PeiFspPolicyUpdateLib.c | 192 ++++++++++++++++ .../PeiPchPolicyUpdate.c | 159 +++++++++++++ .../PeiPchPolicyUpdate.h | 34 +++ .../PeiPchPolicyUpdatePreMem.c | 254 +++++++++++++++++++++ .../PeiSaPolicyUpdate.c | 90 ++++++++ .../PeiSaPolicyUpdate.h | 36 +++ .../PeiSaPolicyUpdatePreMem.c | 74 ++++++ .../PeiSiliconPolicyUpdateLibFsp.inf | 145 ++++++++++++ .../KabylakeRvp3/OpenBoardPkg.dsc | 9 +- .../KabylakeRvp3/OpenBoardPkg.fdf | 2 +- .../DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c | 181 +++++++++++++++ .../DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.h | 45 ++++ .../DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.h | 70 ++++++ .../DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c | 71 ++++++ .../DxeSiliconPolicyUpdateLib.c | 59 +++++ .../DxeSiliconPolicyUpdateLib.inf | 55 +++++ .../Policy/PolicyInitDxe/DxeSaPolicyUpdate.c | 71 ------ .../Policy/PolicyInitDxe/GopPolicyInitDxe.c | 181 --------------- .../Policy/PolicyInitDxe/GopPolicyInitDxe.h | 45 ---- .../Policy/PolicyInitDxe/PolicyInitDxe.c | 56 ----- .../Policy/PolicyInitDxe/PolicyInitDxe.h | 46 ---- .../Policy/PolicyInitDxe/PolicyInitDxe.inf | 74 ------ .../Policy/PolicyInitDxe/SaPolicyInitDxe.c | 73 ------ .../Policy/PolicyInitDxe/SaPolicyInitDxe.h | 56 ----- 36 files changed, 1676 insertions(+), 1768 deletions(-) delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PcieDeviceTable.c delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiFspMiscUpdUpdateLib.c delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiFspPolicyUpdateLib.c delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiFspPolicyUpdateLib.inf delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiPchPolicyUpdate.c delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiPchPolicyUpdate.h delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiSaPolicyUpdate.c delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiSaPolicyUpdate.h delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.h create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.h create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/DxeSaPolicyUpdate.c delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/GopPolicyInitDxe.c delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/GopPolicyInitDxe.h delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.c delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.h delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.inf delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/SaPolicyInitDxe.c delete mode 100644 Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/SaPolicyInitDxe.h diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PcieDeviceTable.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PcieDeviceTable.c deleted file mode 100644 index c03c51e8ca..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PcieDeviceTable.c +++ /dev/null @@ -1,121 +0,0 @@ -/** @file - This file is SampleCode of the library for Intel PCH PEI Policy initialization. - -Copyright (c) 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include "PeiPchPolicyUpdate.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define PCI_CLASS_NETWORK 0x02 -#define PCI_CLASS_NETWORK_ETHERNET 0x00 -#define PCI_CLASS_NETWORK_OTHER 0x80 - -GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] = { - // - // Intel PRO/Wireless - // - { 0x8086, 0x422b, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x422c, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x4238, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x4239, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - // - // Intel WiMAX/WiFi Link - // - { 0x8086, 0x0082, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x0085, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x0083, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x0084, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x0086, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x0087, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x0088, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x0089, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x008F, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x0090, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - // - // Intel Crane Peak WLAN NIC - // - { 0x8086, 0x08AE, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x08AF, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - // - // Intel Crane Peak w/BT WLAN NIC - // - { 0x8086, 0x0896, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x0897, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - // - // Intel Kelsey Peak WiFi, WiMax - // - { 0x8086, 0x0885, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x0886, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - // - // Intel Centrino Wireless-N 105 - // - { 0x8086, 0x0894, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x0895, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - // - // Intel Centrino Wireless-N 135 - // - { 0x8086, 0x0892, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x0893, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - // - // Intel Centrino Wireless-N 2200 - // - { 0x8086, 0x0890, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x0891, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - // - // Intel Centrino Wireless-N 2230 - // - { 0x8086, 0x0887, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x0888, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - // - // Intel Centrino Wireless-N 6235 - // - { 0x8086, 0x088E, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x088F, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - // - // Intel CampPeak 2 Wifi - // - { 0x8086, 0x08B5, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x08B6, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - // - // Intel WilkinsPeak 1 Wifi - // - { 0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 }, - { 0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 }, - // - // Intel Wilkins Peak 2 Wifi - // - { 0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 }, - { 0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 }, - // - // Intel Wilkins Peak PF Wifi - // - { 0x8086, 0x08B0, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - - // - // End of Table - // - { 0 } -}; - diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiFspMiscUpdUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiFspMiscUpdUpdateLib.c deleted file mode 100644 index 0f7c6acb59..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiFspMiscUpdUpdateLib.c +++ /dev/null @@ -1,83 +0,0 @@ -/** @file - Implementation of Fsp Misc UPD Initialization. - -Copyright (c) 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include - -/** - Performs FSP Misc UPD initialization. - - @param[in][out] FspmUpd Pointer to FSPM_UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. -**/ -EFI_STATUS -EFIAPI -PeiFspMiscUpdUpdatePreMem ( - IN OUT FSPM_UPD *FspmUpd - ) -{ - EFI_STATUS Status; - UINTN VariableSize; - VOID *MemorySavedData; - UINT8 MorControl; - VOID *MorControlPtr; - - // - // Initialize S3 Data variable (S3DataPtr). It may be used for warm and fast boot paths. - // - VariableSize = 0; - MemorySavedData = NULL; - Status = PeiGetVariable ( - L"MemoryConfig", - &gFspNonVolatileStorageHobGuid, - &MemorySavedData, - &VariableSize - ); - DEBUG ((DEBUG_INFO, "Get L\"MemoryConfig\" gFspNonVolatileStorageHobGuid - %r\n", Status)); - DEBUG ((DEBUG_INFO, "MemoryConfig Size - 0x%x\n", VariableSize)); - FspmUpd->FspmArchUpd.NvsBufferPtr = MemorySavedData; - - // - // MOR - // - MorControl = 0; - MorControlPtr = &MorControl; - VariableSize = sizeof (MorControl); - Status = PeiGetVariable ( - MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME, - &gEfiMemoryOverwriteControlDataGuid, - &MorControlPtr, - &VariableSize - ); - DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status)); - if (MOR_CLEAR_MEMORY_VALUE (MorControl)) { - FspmUpd->FspmConfig.CleanMemory = (BOOLEAN)(MorControl & MOR_CLEAR_MEMORY_BIT_MASK); - } - - return EFI_SUCCESS; -} - diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiFspPolicyUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiFspPolicyUpdateLib.c deleted file mode 100644 index 3f29f736fb..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiFspPolicyUpdateLib.c +++ /dev/null @@ -1,166 +0,0 @@ -/** @file - Provide FSP wrapper platform related function. - -Copyright (c) 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -/** - Performs FSP Misc UPD initialization. - - @param[in][out] FspmUpd Pointer to FSPM_UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. -**/ -EFI_STATUS -EFIAPI -PeiFspMiscUpdUpdatePreMem ( - IN OUT FSPM_UPD *FspmUpd - ); - -/** - Performs FSP PCH PEI Policy pre mem initialization. - - @param[in][out] FspmUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspPchPolicyUpdatePreMem ( - IN OUT FSPM_UPD *FspmUpd - ); - -/** - Performs FSP PCH PEI Policy initialization. - - @param[in][out] FspsUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspPchPolicyUpdate ( - IN OUT FSPS_UPD *FspsUpd - ); - -/** - Performs FSP SA PEI Policy initialization in pre-memory. - - @param[in][out] FspmUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspSaPolicyUpdatePreMem ( - IN OUT FSPM_UPD *FspmUpd - ); - -/** - Performs FSP SA PEI Policy initialization. - - @param[in][out] FspsUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspSaPolicyUpdate ( - IN OUT FSPS_UPD *FspsUpd - ); - -VOID -InternalPrintVariableData ( - IN UINT8 *Data8, - IN UINTN DataSize - ) -{ - UINTN Index; - - for (Index = 0; Index < DataSize; Index++) { - if (Index % 0x10 == 0) { - DEBUG ((DEBUG_INFO, "\n%08X:", Index)); - } - DEBUG ((DEBUG_INFO, " %02X", *Data8++)); - } - DEBUG ((DEBUG_INFO, "\n")); -} - -/** - Performs FSPM UPD Policy update. - - A platform may use this API to update the FSPM UPD policy initialized - by the silicon module or the default UPD data. - The output of FSPM UPD data from this API is the final UPD data. - - @param[in, out] FspmUpd Pointer to FSPM UPD data. -**/ -VOID -EFIAPI -FspmPolicyUpdate ( - IN OUT VOID *FspmUpd - ) -{ - FSPM_UPD *FspmUpdDataPtr; - - FspmUpdDataPtr = FspmUpd; - PeiFspSaPolicyUpdatePreMem (FspmUpdDataPtr); - PeiFspPchPolicyUpdatePreMem (FspmUpdDataPtr); - PeiFspMiscUpdUpdatePreMem (FspmUpdDataPtr); - - InternalPrintVariableData ((VOID *)FspmUpdDataPtr, sizeof(FSPM_UPD)); -} - -/** - Performs FSPS UPD Policy update. - - A platform may use this API to update the FSPS UPD policy initialized - by the silicon module or the default UPD data. - The output of FSPS UPD data from this API is the final UPD data. - - @param[in, out] FspsUpd Pointer to FSPS UPD data. -**/ -VOID -EFIAPI -FspsPolicyUpdate ( - IN OUT VOID *FspsUpd - ) -{ - FSPS_UPD *FspsUpdDataPtr; - - FspsUpdDataPtr = FspsUpd; - PeiFspSaPolicyUpdate (FspsUpdDataPtr); - PeiFspPchPolicyUpdate (FspsUpdDataPtr); - - InternalPrintVariableData ((VOID *)FspsUpdDataPtr, sizeof(FSPS_UPD)); -} - - diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiFspPolicyUpdateLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiFspPolicyUpdateLib.inf deleted file mode 100644 index a1e461525e..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiFspPolicyUpdateLib.inf +++ /dev/null @@ -1,145 +0,0 @@ -## @file -# Provide FSP wrapper platform related function. -# -# Copyright (c) 2017, Intel Corporation. All rights reserved.
-# -# This program and the accompanying materials are licensed and made available under -# the terms and conditions of the BSD License which accompanies this distribution. -# The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -## - -################################################################################ -# -# Defines Section - statements that will be processed to create a Makefile. -# -################################################################################ -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = PeiFspPolicyUpdateLib - FILE_GUID = 4E83003B-49A9-459E-AAA6-1CA3C6D04FB2 - MODULE_TYPE = PEIM - VERSION_STRING = 1.0 - LIBRARY_CLASS = FspPolicyUpdateLib - - -# -# The following information is for reference only and not required by the build tools. -# -# VALID_ARCHITECTURES = IA32 X64 -# - -################################################################################ -# -# Sources Section - list of files that are required for the build to succeed. -# -################################################################################ - -[Sources] - PeiFspPolicyUpdateLib.c - PeiPchPolicyUpdatePreMem.c - PeiPchPolicyUpdate.c - PeiSaPolicyUpdatePreMem.c - PeiSaPolicyUpdate.c - PeiFspMiscUpdUpdateLib.c - PcieDeviceTable.c - -################################################################################ -# -# Package Dependency Section - list of Package files that are required for -# this module. -# -################################################################################ - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - IntelFsp2Pkg/IntelFsp2Pkg.dec - IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec - KabylakeSiliconPkg/SiPkg.dec - KabylakeFspBinPkg/KabylakeFspBinPkg.dec - KabylakeOpenBoardPkg/OpenBoardPkg.dec - MinPlatformPkg/MinPlatformPkg.dec - -[LibraryClasses.IA32] - FspWrapperApiLib - OcWdtLib - PchResetLib - FspWrapperPlatformLib - BaseMemoryLib - CpuPlatformLib - DebugLib - HobLib - IoLib - PcdLib - PostCodeLib - SmbusLib - MmPciLib - ConfigBlockLib - PeiSaPolicyLib - PchGbeLib - PchInfoLib - PchHsioLib - PchPcieRpLib - MemoryAllocationLib - CpuMailboxLib - DebugPrintErrorLevelLib - SiPolicyLib - PchGbeLib - TimerLib - GpioLib - PeiLib - -[Pcd] - gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcSpdData - gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize - - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES - gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable ## CONSUMES - gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber ## CONSUMES - gSiPkgTokenSpaceGuid.PcdSmmbaseSwSmi ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit ## CONSUMES - - gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size - - gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size - gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size - - gBoardModuleTokenSpaceGuid.PcdHdaVerbTable - gBoardModuleTokenSpaceGuid.PcdHdaVerbTable2 - gBoardModuleTokenSpaceGuid.PcdExtHdaVerbTable - gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable1 - gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable2 - gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable3 - gBoardModuleTokenSpaceGuid.PcdDisplayAudioHdaVerbTable - - gBoardModuleTokenSpaceGuid.PcdAudioConnector - - gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid - -[Guids] - gFspNonVolatileStorageHobGuid ## CONSUMES - gTianoLogoGuid ## CONSUMES - gEfiMemoryOverwriteControlDataGuid - diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiPchPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiPchPolicyUpdate.c deleted file mode 100644 index c1c8bf131d..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiPchPolicyUpdate.c +++ /dev/null @@ -1,159 +0,0 @@ -/** @file - This file is SampleCode of the library for Intel PCH PEI Policy initialization. - -Copyright (c) 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include "PeiPchPolicyUpdate.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[]; - -/** - Add verb table helper function. - This function calculates verbtable number and shows verb table information. - - @param[in,out] VerbTableEntryNum Input current VerbTable number and output the number after adding new table - @param[in,out] VerbTableArray Pointer to array of VerbTable - @param[in] VerbTable VerbTable which is going to add into array -**/ -STATIC -VOID -InternalAddVerbTable ( - IN OUT UINT8 *VerbTableEntryNum, - IN OUT UINT32 *VerbTableArray, - IN HDAUDIO_VERB_TABLE *VerbTable - ) -{ - if (VerbTable == NULL) { - DEBUG ((DEBUG_ERROR, "InternalAddVerbTable wrong input: VerbTable == NULL\n")); - return; - } - - VerbTableArray[*VerbTableEntryNum] = (UINT32) VerbTable; - *VerbTableEntryNum += 1; - - DEBUG ((DEBUG_INFO, - "Add verb table for vendor = 0x%04X devId = 0x%04X (size = %d DWords)\n", - VerbTable->Header.VendorId, - VerbTable->Header.DeviceId, - VerbTable->Header.DataDwords) - ); -} - -enum HDAUDIO_CODEC_SELECT { - PchHdaCodecPlatformOnboard = 0, - PchHdaCodecExternalKit = 1 -}; - -/** - Add verb table function. - This function update the verb table number and verb table ptr of policy. - - @param[in] HdAudioConfig HDAudie config block - @param[in] CodecType Platform codec type indicator - @param[in] AudioConnectorType Platform audio connector type -**/ -STATIC -VOID -InternalAddPlatformVerbTables ( - IN OUT FSPS_UPD *FspsUpd, - IN UINT8 CodecType, - IN UINT8 AudioConnectorType - ) -{ - UINT8 VerbTableEntryNum; - UINT32 VerbTableArray[32]; - UINT32 *VerbTablePtr; - - VerbTableEntryNum = 0; - - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdDisplayAudioHdaVerbTable)); - - if (CodecType == PchHdaCodecPlatformOnboard) { - DEBUG ((DEBUG_INFO, "HDA Policy: Onboard codec selected\n")); - if ((VOID *) (UINTN) PcdGet32 (PcdExtHdaVerbTable) != NULL) { - if (AudioConnectorType == 0) { //Type-C Audio connector selected in Bios Setup menu - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdExtHdaVerbTable)); - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL); - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL); - DEBUG ((DEBUG_INFO, "HDA: Type-C Audio connector selected!\n")); - } else { //Stacked Jack Audio connector selected in Bios Setup menu - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable)); - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable2)); - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL); - DEBUG ((DEBUG_INFO, "HDA: Stacked-Jack Audio connector selected!\n")); - } - } else { - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable)); - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable2)); - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL); - } - } else { - DEBUG ((DEBUG_INFO, "HDA Policy: External codec kit selected\n")); - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdCommonHdaVerbTable1)); - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdCommonHdaVerbTable2)); - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdCommonHdaVerbTable3)); - } - - FspsUpd->FspsConfig.PchHdaVerbTableEntryNum = VerbTableEntryNum; - - VerbTablePtr = (UINT32 *) AllocateZeroPool (sizeof (UINT32) * VerbTableEntryNum); - CopyMem (VerbTablePtr, VerbTableArray, sizeof (UINT32) * VerbTableEntryNum); - FspsUpd->FspsConfig.PchHdaVerbTablePtr = (UINT32) VerbTablePtr; -} - -/** - Performs FSP PCH PEI Policy initialization. - - @param[in][out] FspsUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspPchPolicyUpdate ( - IN OUT FSPS_UPD *FspsUpd - ) -{ - - FspsUpd->FspsConfig.PchSubSystemVendorId = V_PCH_INTEL_VENDOR_ID; - FspsUpd->FspsConfig.PchSubSystemId = V_PCH_DEFAULT_SID; - - FspsUpd->FspsConfig.PchPcieDeviceOverrideTablePtr = (UINT32) mPcieDeviceTable; - - InternalAddPlatformVerbTables (FspsUpd, PchHdaCodecPlatformOnboard, PcdGet8 (PcdAudioConnector)); - -DEBUG_CODE_BEGIN(); -if ((PcdGet8 (PcdSerialIoUartDebugEnable) == 1) && - FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 + PcdGet8 (PcdSerialIoUartNumber)] == PchSerialIoDisabled ) { - FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 + PcdGet8 (PcdSerialIoUartNumber)] = PchSerialIoLegacyUart; - } -DEBUG_CODE_END(); - - return EFI_SUCCESS; -} - diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiPchPolicyUpdate.h b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiPchPolicyUpdate.h deleted file mode 100644 index a4e69f4e73..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiPchPolicyUpdate.h +++ /dev/null @@ -1,34 +0,0 @@ -/** @file - -Copyright (c) 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#ifndef _PEI_PCH_POLICY_UPDATE_H_ -#define _PEI_PCH_POLICY_UPDATE_H_ - -// -// External include files do NOT need to be explicitly specified in real EDKII -// environment -// -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#endif diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c deleted file mode 100644 index fc27d67e69..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c +++ /dev/null @@ -1,254 +0,0 @@ -/** @file - This file is SampleCode of the library for Intel PCH PEI Policy initialization. - -Copyright (c) 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include "PeiPchPolicyUpdate.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -VOID -InstallPlatformHsioPtssTable ( - IN OUT FSPM_UPD *FspmUpd - ) -{ - HSIO_PTSS_TABLES *UnknowPtssTables; - HSIO_PTSS_TABLES *SpecificPtssTables; - HSIO_PTSS_TABLES *PtssTables; - UINT8 PtssTableIndex; - UINT32 UnknowTableSize; - UINT32 SpecificTableSize; - UINT32 TableSize; - UINT32 Entry; - UINT8 LaneNum; - UINT8 Index; - UINT8 MaxSataPorts; - UINT8 MaxPciePorts; - UINT8 PcieTopologyReal[PCH_MAX_PCIE_ROOT_PORTS]; - UINT8 PciePort; - UINTN RpBase; - UINTN RpDevice; - UINTN RpFunction; - UINT32 StrapFuseCfg; - UINT8 PcieControllerCfg; - EFI_STATUS Status; - - UnknowPtssTables = NULL; - UnknowTableSize = 0; - SpecificPtssTables = NULL; - SpecificTableSize = 0; - - if (GetPchGeneration () == SklPch) { - switch (PchStepping ()) { - case PchLpB0: - case PchLpB1: - UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable1); - UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable1Size); - SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable1); - SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable1Size); - break; - case PchLpC0: - case PchLpC1: - UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable2); - UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable2Size); - SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable2); - SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable2Size); - break; - case PchHB0: - case PchHC0: - UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable1); - UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable1Size); - SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable1); - SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable1Size); - break; - case PchHD0: - case PchHD1: - UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2); - UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size); - SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2); - SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size); - break; - default: - UnknowPtssTables = NULL; - UnknowTableSize = 0; - SpecificPtssTables = NULL; - SpecificTableSize = 0; - DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n")); - } - } else { - switch (PchStepping ()) { - case KblPchHA0: - UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2); - UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size); - SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2); - SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size); - break; - default: - UnknowPtssTables = NULL; - UnknowTableSize = 0; - SpecificPtssTables = NULL; - SpecificTableSize = 0; - DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n")); - } - } - - PtssTableIndex = 0; - MaxSataPorts = GetPchMaxSataPortNum (); - MaxPciePorts = GetPchMaxPciePortNum (); - ZeroMem (PcieTopologyReal, sizeof (PcieTopologyReal)); - - //Populate PCIe topology based on lane configuration - for (PciePort = 0; PciePort < MaxPciePorts; PciePort += 4) { - Status = GetPchPcieRpDevFun (PciePort, &RpDevice, &RpFunction); - ASSERT_EFI_ERROR (Status); - - RpBase = MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH, (UINT32) RpDevice, (UINT32) RpFunction); - StrapFuseCfg = MmioRead32 (RpBase + R_PCH_PCIE_STRPFUSECFG); - PcieControllerCfg = (UINT8) ((StrapFuseCfg & B_PCH_PCIE_STRPFUSECFG_RPC) >> N_PCH_PCIE_STRPFUSECFG_RPC); - DEBUG ((DEBUG_INFO, "PCIE Port %d StrapFuseCfg Value = %d\n", PciePort, PcieControllerCfg)); - } - for (Index = 0; Index < MaxPciePorts; Index++) { - DEBUG ((DEBUG_INFO, "PCIE PTSS Assigned RP %d Topology = %d\n", Index, PcieTopologyReal[Index])); - } - - //Case 1: BoardId is known, Topology is known/unknown - //Case 1a: SATA - PtssTables = SpecificPtssTables; - TableSize = SpecificTableSize; - for (Index = 0; Index < MaxSataPorts; Index++) { - if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) { - for (Entry = 0; Entry < TableSize; Entry++) { - if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && - (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA) - ) - { - PtssTableIndex++; - if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) && - (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) { - FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] = TRUE; - FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0; - } else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8)) { - if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) { - FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index] = TRUE; - FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0); - } - if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) { - FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index] = TRUE; - FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0); - } - } else { - ASSERT (FALSE); - } - } - } - } - } - //Case 1b: PCIe - for (Index = 0; Index < MaxPciePorts; Index++) { - if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) { - for (Entry = 0; Entry < TableSize; Entry++) { - if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && - (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) && - (PcieTopologyReal[Index] == PtssTables[Entry].Topology)) { - PtssTableIndex++; - if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) && - (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) { - FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] = TRUE; - FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0); - } else { - ASSERT (FALSE); - } - } - } - } - } - //Case 2: BoardId is unknown, Topology is known/unknown - if (PtssTableIndex == 0) { - DEBUG ((DEBUG_INFO, "PTSS Settings for unknown board will be applied\n")); - - PtssTables = UnknowPtssTables; - TableSize = UnknowTableSize; - - for (Index = 0; Index < MaxSataPorts; Index++) { - if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) { - for (Entry = 0; Entry < TableSize; Entry++) { - if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && - (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA) - ) - { - if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) && - (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) { - FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] = TRUE; - FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0; - } else if (PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8) { - if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) { - FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index] = TRUE; - FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0); - } - if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) { - FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index] = TRUE; - FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0); - } - } else { - ASSERT (FALSE); - } - } - } - } - } - for (Index = 0; Index < MaxPciePorts; Index++) { - if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) { - for (Entry = 0; Entry < TableSize; Entry++) { - if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && - (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) && - (PcieTopologyReal[Index] == PtssTables[Entry].Topology)) { - if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) && - (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) { - FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] = TRUE; - FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0); - } else { - ASSERT (FALSE); - } - } - } - } - } - } -} - -/** - Performs FSP PCH PEI Policy pre mem initialization. - - @param[in][out] FspmUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspPchPolicyUpdatePreMem ( - IN OUT FSPM_UPD *FspmUpd - ) -{ - InstallPlatformHsioPtssTable (FspmUpd); - return EFI_SUCCESS; -} - diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiSaPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiSaPolicyUpdate.c deleted file mode 100644 index fd54c63a92..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiSaPolicyUpdate.c +++ /dev/null @@ -1,90 +0,0 @@ -/** @file -Do Platform Stage System Agent initialization. - -Copyright (c) 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include "PeiSaPolicyUpdate.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/** - Performs FSP SA PEI Policy initialization. - - @param[in][out] FspsUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspSaPolicyUpdate ( - IN OUT FSPS_UPD *FspsUpd - ) -{ - VOID *Buffer; - VOID *MemBuffer; - UINT32 Size; - - DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n")); - - FspsUpd->FspsConfig.PeiGraphicsPeimInit = 1; - - Size = 0; - Buffer = NULL; - PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size); - if (Buffer == NULL) { - DEBUG((DEBUG_WARN, "Could not locate VBT\n")); - } else { - MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)); - if ((MemBuffer != NULL) && (Buffer != NULL)) { - CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); - FspsUpd->FspsConfig.GraphicsConfigPtr = (UINT32)(UINTN)MemBuffer; - } else { - DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n")); - FspsUpd->FspsConfig.GraphicsConfigPtr = 0; - } - } - DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", FspsUpd->FspsConfig.GraphicsConfigPtr)); - DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size)); - - Size = 0; - Buffer = NULL; - PeiGetSectionFromAnyFv (&gTianoLogoGuid, EFI_SECTION_RAW, 0, &Buffer, &Size); - if (Buffer == NULL) { - DEBUG((DEBUG_WARN, "Could not locate Logo\n")); - } else { - MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)); - if ((MemBuffer != NULL) && (Buffer != NULL)) { - CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); - FspsUpd->FspsConfig.LogoPtr = (UINT32)(UINTN)MemBuffer; - FspsUpd->FspsConfig.LogoSize = Size; - } else { - DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n")); - FspsUpd->FspsConfig.LogoPtr = 0; - FspsUpd->FspsConfig.LogoSize = 0; - } - } - DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", FspsUpd->FspsConfig.LogoPtr)); - DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n", FspsUpd->FspsConfig.LogoSize)); - - return EFI_SUCCESS; -} - diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiSaPolicyUpdate.h b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiSaPolicyUpdate.h deleted file mode 100644 index da6f746772..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiSaPolicyUpdate.h +++ /dev/null @@ -1,36 +0,0 @@ -/** @file - -Copyright (c) 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#ifndef _PEI_SA_POLICY_UPDATE_H_ -#define _PEI_SA_POLICY_UPDATE_H_ - -// -// External include files do NOT need to be explicitly specified in real EDKII -// environment -// -#include -#include -#include -#include -#include "PeiPchPolicyUpdate.h" -#include -#include - -#include -#include -#include - -extern EFI_GUID gTianoLogoGuid; - -#endif - diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c deleted file mode 100644 index 94d5094855..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c +++ /dev/null @@ -1,74 +0,0 @@ -/** @file -Do Platform Stage System Agent initialization. - -Copyright (c) 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include "PeiSaPolicyUpdate.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - - -/** - Performs FSP SA PEI Policy initialization in pre-memory. - - @param[in][out] FspmUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspSaPolicyUpdatePreMem ( - IN OUT FSPM_UPD *FspmUpd - ) -{ - VOID *Buffer; - - CopyMem((VOID *)(UINTN)FspmUpd->FspmConfig.MemorySpdPtr00, (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize)); - CopyMem((VOID *)(UINTN)FspmUpd->FspmConfig.MemorySpdPtr10, (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize)); - - DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Settings...\n")); - Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap); - if (Buffer) { - CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh0, Buffer, 12); - CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh1, (UINT8*) Buffer + 12, 12); - } - Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram); - if (Buffer) { - CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh0, Buffer, 8); - CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh1, (UINT8*) Buffer + 8, 8); - } - - DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & Rcomp Target Settings...\n")); - Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor); - if (Buffer) { - CopyMem ((VOID *)FspmUpd->FspmConfig.RcompResistor, Buffer, 6); - } - Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget); - if (Buffer) { - CopyMem ((VOID *)FspmUpd->FspmConfig.RcompTarget, Buffer, 10); - } - return EFI_SUCCESS; -} - diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c new file mode 100644 index 0000000000..c03c51e8ca --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c @@ -0,0 +1,121 @@ +/** @file + This file is SampleCode of the library for Intel PCH PEI Policy initialization. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "PeiPchPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCI_CLASS_NETWORK 0x02 +#define PCI_CLASS_NETWORK_ETHERNET 0x00 +#define PCI_CLASS_NETWORK_OTHER 0x80 + +GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] = { + // + // Intel PRO/Wireless + // + { 0x8086, 0x422b, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x422c, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x4238, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x4239, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel WiMAX/WiFi Link + // + { 0x8086, 0x0082, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0085, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0083, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0084, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0086, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0087, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0088, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0089, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x008F, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0090, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Crane Peak WLAN NIC + // + { 0x8086, 0x08AE, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x08AF, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Crane Peak w/BT WLAN NIC + // + { 0x8086, 0x0896, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0897, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Kelsey Peak WiFi, WiMax + // + { 0x8086, 0x0885, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0886, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Centrino Wireless-N 105 + // + { 0x8086, 0x0894, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0895, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Centrino Wireless-N 135 + // + { 0x8086, 0x0892, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0893, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Centrino Wireless-N 2200 + // + { 0x8086, 0x0890, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0891, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Centrino Wireless-N 2230 + // + { 0x8086, 0x0887, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0888, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Centrino Wireless-N 6235 + // + { 0x8086, 0x088E, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x088F, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel CampPeak 2 Wifi + // + { 0x8086, 0x08B5, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x08B6, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel WilkinsPeak 1 Wifi + // + { 0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 }, + { 0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 }, + // + // Intel Wilkins Peak 2 Wifi + // + { 0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 }, + { 0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, 0, 0 }, + // + // Intel Wilkins Peak PF Wifi + // + { 0x8086, 0x08B0, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + + // + // End of Table + // + { 0 } +}; + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c new file mode 100644 index 0000000000..0f7c6acb59 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c @@ -0,0 +1,83 @@ +/** @file + Implementation of Fsp Misc UPD Initialization. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +/** + Performs FSP Misc UPD initialization. + + @param[in][out] FspmUpd Pointer to FSPM_UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. +**/ +EFI_STATUS +EFIAPI +PeiFspMiscUpdUpdatePreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + EFI_STATUS Status; + UINTN VariableSize; + VOID *MemorySavedData; + UINT8 MorControl; + VOID *MorControlPtr; + + // + // Initialize S3 Data variable (S3DataPtr). It may be used for warm and fast boot paths. + // + VariableSize = 0; + MemorySavedData = NULL; + Status = PeiGetVariable ( + L"MemoryConfig", + &gFspNonVolatileStorageHobGuid, + &MemorySavedData, + &VariableSize + ); + DEBUG ((DEBUG_INFO, "Get L\"MemoryConfig\" gFspNonVolatileStorageHobGuid - %r\n", Status)); + DEBUG ((DEBUG_INFO, "MemoryConfig Size - 0x%x\n", VariableSize)); + FspmUpd->FspmArchUpd.NvsBufferPtr = MemorySavedData; + + // + // MOR + // + MorControl = 0; + MorControlPtr = &MorControl; + VariableSize = sizeof (MorControl); + Status = PeiGetVariable ( + MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME, + &gEfiMemoryOverwriteControlDataGuid, + &MorControlPtr, + &VariableSize + ); + DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status)); + if (MOR_CLEAR_MEMORY_VALUE (MorControl)) { + FspmUpd->FspmConfig.CleanMemory = (BOOLEAN)(MorControl & MOR_CLEAR_MEMORY_BIT_MASK); + } + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c new file mode 100644 index 0000000000..f3c56419b5 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c @@ -0,0 +1,192 @@ +/** @file + Provide FSP wrapper platform related function. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/** + Performs FSP Misc UPD initialization. + + @param[in][out] FspmUpd Pointer to FSPM_UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. +**/ +EFI_STATUS +EFIAPI +PeiFspMiscUpdUpdatePreMem ( + IN OUT FSPM_UPD *FspmUpd + ); + +/** + Performs FSP PCH PEI Policy pre mem initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspPchPolicyUpdatePreMem ( + IN OUT FSPM_UPD *FspmUpd + ); + +/** + Performs FSP PCH PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspPchPolicyUpdate ( + IN OUT FSPS_UPD *FspsUpd + ); + +/** + Performs FSP SA PEI Policy initialization in pre-memory. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSaPolicyUpdatePreMem ( + IN OUT FSPM_UPD *FspmUpd + ); + +/** + Performs FSP SA PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSaPolicyUpdate ( + IN OUT FSPS_UPD *FspsUpd + ); + +VOID +InternalPrintVariableData ( + IN UINT8 *Data8, + IN UINTN DataSize + ) +{ + UINTN Index; + + for (Index = 0; Index < DataSize; Index++) { + if (Index % 0x10 == 0) { + DEBUG ((DEBUG_INFO, "\n%08X:", Index)); + } + DEBUG ((DEBUG_INFO, " %02X", *Data8++)); + } + DEBUG ((DEBUG_INFO, "\n")); +} + +/** + Performs silicon pre-mem policy update. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a PPI, etc. + + The input Policy must be returned by SiliconPolicyDonePreMem(). + + 1) In FSP path, the input Policy should be FspmUpd. + A platform may use this API to update the FSPM UPD policy initialized + by the silicon module or the default UPD data. + The output of FSPM UPD data from this API is the final UPD data. + + 2) In non-FSP path, the board may use additional way to get + the silicon policy data field based upon the input Policy. + + @param[in, out] Policy Pointer to policy. + + @return the updated policy. +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePreMem ( + IN OUT VOID *FspmUpd + ) +{ + FSPM_UPD *FspmUpdDataPtr; + + FspmUpdDataPtr = FspmUpd; + PeiFspSaPolicyUpdatePreMem (FspmUpdDataPtr); + PeiFspPchPolicyUpdatePreMem (FspmUpdDataPtr); + PeiFspMiscUpdUpdatePreMem (FspmUpdDataPtr); + + InternalPrintVariableData ((VOID *)FspmUpdDataPtr, sizeof(FSPM_UPD)); + + return FspmUpd; +} + +/** + Performs silicon post-mem policy update. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a PPI, etc. + + The input Policy must be returned by SiliconPolicyDonePostMem(). + + 1) In FSP path, the input Policy should be FspsUpd. + A platform may use this API to update the FSPS UPD policy initialized + by the silicon module or the default UPD data. + The output of FSPS UPD data from this API is the final UPD data. + + 2) In non-FSP path, the board may use additional way to get + the silicon policy data field based upon the input Policy. + + @param[in, out] Policy Pointer to policy. + + @return the updated policy. +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePostMem ( + IN OUT VOID *FspsUpd + ) +{ + FSPS_UPD *FspsUpdDataPtr; + + FspsUpdDataPtr = FspsUpd; + PeiFspSaPolicyUpdate (FspsUpdDataPtr); + PeiFspPchPolicyUpdate (FspsUpdDataPtr); + + InternalPrintVariableData ((VOID *)FspsUpdDataPtr, sizeof(FSPS_UPD)); + + return FspsUpd; +} + + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c new file mode 100644 index 0000000000..c1c8bf131d --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c @@ -0,0 +1,159 @@ +/** @file + This file is SampleCode of the library for Intel PCH PEI Policy initialization. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "PeiPchPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[]; + +/** + Add verb table helper function. + This function calculates verbtable number and shows verb table information. + + @param[in,out] VerbTableEntryNum Input current VerbTable number and output the number after adding new table + @param[in,out] VerbTableArray Pointer to array of VerbTable + @param[in] VerbTable VerbTable which is going to add into array +**/ +STATIC +VOID +InternalAddVerbTable ( + IN OUT UINT8 *VerbTableEntryNum, + IN OUT UINT32 *VerbTableArray, + IN HDAUDIO_VERB_TABLE *VerbTable + ) +{ + if (VerbTable == NULL) { + DEBUG ((DEBUG_ERROR, "InternalAddVerbTable wrong input: VerbTable == NULL\n")); + return; + } + + VerbTableArray[*VerbTableEntryNum] = (UINT32) VerbTable; + *VerbTableEntryNum += 1; + + DEBUG ((DEBUG_INFO, + "Add verb table for vendor = 0x%04X devId = 0x%04X (size = %d DWords)\n", + VerbTable->Header.VendorId, + VerbTable->Header.DeviceId, + VerbTable->Header.DataDwords) + ); +} + +enum HDAUDIO_CODEC_SELECT { + PchHdaCodecPlatformOnboard = 0, + PchHdaCodecExternalKit = 1 +}; + +/** + Add verb table function. + This function update the verb table number and verb table ptr of policy. + + @param[in] HdAudioConfig HDAudie config block + @param[in] CodecType Platform codec type indicator + @param[in] AudioConnectorType Platform audio connector type +**/ +STATIC +VOID +InternalAddPlatformVerbTables ( + IN OUT FSPS_UPD *FspsUpd, + IN UINT8 CodecType, + IN UINT8 AudioConnectorType + ) +{ + UINT8 VerbTableEntryNum; + UINT32 VerbTableArray[32]; + UINT32 *VerbTablePtr; + + VerbTableEntryNum = 0; + + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdDisplayAudioHdaVerbTable)); + + if (CodecType == PchHdaCodecPlatformOnboard) { + DEBUG ((DEBUG_INFO, "HDA Policy: Onboard codec selected\n")); + if ((VOID *) (UINTN) PcdGet32 (PcdExtHdaVerbTable) != NULL) { + if (AudioConnectorType == 0) { //Type-C Audio connector selected in Bios Setup menu + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdExtHdaVerbTable)); + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL); + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL); + DEBUG ((DEBUG_INFO, "HDA: Type-C Audio connector selected!\n")); + } else { //Stacked Jack Audio connector selected in Bios Setup menu + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable)); + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable2)); + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL); + DEBUG ((DEBUG_INFO, "HDA: Stacked-Jack Audio connector selected!\n")); + } + } else { + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable)); + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdHdaVerbTable2)); + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL); + } + } else { + DEBUG ((DEBUG_INFO, "HDA Policy: External codec kit selected\n")); + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdCommonHdaVerbTable1)); + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdCommonHdaVerbTable2)); + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINTN) PcdGet32 (PcdCommonHdaVerbTable3)); + } + + FspsUpd->FspsConfig.PchHdaVerbTableEntryNum = VerbTableEntryNum; + + VerbTablePtr = (UINT32 *) AllocateZeroPool (sizeof (UINT32) * VerbTableEntryNum); + CopyMem (VerbTablePtr, VerbTableArray, sizeof (UINT32) * VerbTableEntryNum); + FspsUpd->FspsConfig.PchHdaVerbTablePtr = (UINT32) VerbTablePtr; +} + +/** + Performs FSP PCH PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspPchPolicyUpdate ( + IN OUT FSPS_UPD *FspsUpd + ) +{ + + FspsUpd->FspsConfig.PchSubSystemVendorId = V_PCH_INTEL_VENDOR_ID; + FspsUpd->FspsConfig.PchSubSystemId = V_PCH_DEFAULT_SID; + + FspsUpd->FspsConfig.PchPcieDeviceOverrideTablePtr = (UINT32) mPcieDeviceTable; + + InternalAddPlatformVerbTables (FspsUpd, PchHdaCodecPlatformOnboard, PcdGet8 (PcdAudioConnector)); + +DEBUG_CODE_BEGIN(); +if ((PcdGet8 (PcdSerialIoUartDebugEnable) == 1) && + FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 + PcdGet8 (PcdSerialIoUartNumber)] == PchSerialIoDisabled ) { + FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 + PcdGet8 (PcdSerialIoUartNumber)] = PchSerialIoLegacyUart; + } +DEBUG_CODE_END(); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h new file mode 100644 index 0000000000..a4e69f4e73 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h @@ -0,0 +1,34 @@ +/** @file + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PEI_PCH_POLICY_UPDATE_H_ +#define _PEI_PCH_POLICY_UPDATE_H_ + +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#endif diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c new file mode 100644 index 0000000000..fc27d67e69 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c @@ -0,0 +1,254 @@ +/** @file + This file is SampleCode of the library for Intel PCH PEI Policy initialization. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "PeiPchPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +VOID +InstallPlatformHsioPtssTable ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + HSIO_PTSS_TABLES *UnknowPtssTables; + HSIO_PTSS_TABLES *SpecificPtssTables; + HSIO_PTSS_TABLES *PtssTables; + UINT8 PtssTableIndex; + UINT32 UnknowTableSize; + UINT32 SpecificTableSize; + UINT32 TableSize; + UINT32 Entry; + UINT8 LaneNum; + UINT8 Index; + UINT8 MaxSataPorts; + UINT8 MaxPciePorts; + UINT8 PcieTopologyReal[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PciePort; + UINTN RpBase; + UINTN RpDevice; + UINTN RpFunction; + UINT32 StrapFuseCfg; + UINT8 PcieControllerCfg; + EFI_STATUS Status; + + UnknowPtssTables = NULL; + UnknowTableSize = 0; + SpecificPtssTables = NULL; + SpecificTableSize = 0; + + if (GetPchGeneration () == SklPch) { + switch (PchStepping ()) { + case PchLpB0: + case PchLpB1: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable1); + UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable1Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable1); + SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable1Size); + break; + case PchLpC0: + case PchLpC1: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPtssTable2); + UnknowTableSize = PcdGet16 (PcdUnknowLpHsioPtssTable2Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsioPtssTable2); + SpecificTableSize = PcdGet16 (PcdSpecificLpHsioPtssTable2Size); + break; + case PchHB0: + case PchHC0: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable1); + UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable1Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable1); + SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable1Size); + break; + case PchHD0: + case PchHD1: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2); + UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2); + SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size); + break; + default: + UnknowPtssTables = NULL; + UnknowTableSize = 0; + SpecificPtssTables = NULL; + SpecificTableSize = 0; + DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n")); + } + } else { + switch (PchStepping ()) { + case KblPchHA0: + UnknowPtssTables = (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtssTable2); + UnknowTableSize = PcdGet16 (PcdUnknowHHsioPtssTable2Size); + SpecificPtssTables = (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsioPtssTable2); + SpecificTableSize = PcdGet16 (PcdSpecificHHsioPtssTable2Size); + break; + default: + UnknowPtssTables = NULL; + UnknowTableSize = 0; + SpecificPtssTables = NULL; + SpecificTableSize = 0; + DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n")); + } + } + + PtssTableIndex = 0; + MaxSataPorts = GetPchMaxSataPortNum (); + MaxPciePorts = GetPchMaxPciePortNum (); + ZeroMem (PcieTopologyReal, sizeof (PcieTopologyReal)); + + //Populate PCIe topology based on lane configuration + for (PciePort = 0; PciePort < MaxPciePorts; PciePort += 4) { + Status = GetPchPcieRpDevFun (PciePort, &RpDevice, &RpFunction); + ASSERT_EFI_ERROR (Status); + + RpBase = MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH, (UINT32) RpDevice, (UINT32) RpFunction); + StrapFuseCfg = MmioRead32 (RpBase + R_PCH_PCIE_STRPFUSECFG); + PcieControllerCfg = (UINT8) ((StrapFuseCfg & B_PCH_PCIE_STRPFUSECFG_RPC) >> N_PCH_PCIE_STRPFUSECFG_RPC); + DEBUG ((DEBUG_INFO, "PCIE Port %d StrapFuseCfg Value = %d\n", PciePort, PcieControllerCfg)); + } + for (Index = 0; Index < MaxPciePorts; Index++) { + DEBUG ((DEBUG_INFO, "PCIE PTSS Assigned RP %d Topology = %d\n", Index, PcieTopologyReal[Index])); + } + + //Case 1: BoardId is known, Topology is known/unknown + //Case 1a: SATA + PtssTables = SpecificPtssTables; + TableSize = SpecificTableSize; + for (Index = 0; Index < MaxSataPorts; Index++) { + if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) { + for (Entry = 0; Entry < TableSize; Entry++) { + if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA) + ) + { + PtssTableIndex++; + if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) { + FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] = TRUE; + FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0; + } else if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8)) { + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) { + FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index] = TRUE; + FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0); + } + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) { + FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index] = TRUE; + FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0); + } + } else { + ASSERT (FALSE); + } + } + } + } + } + //Case 1b: PCIe + for (Index = 0; Index < MaxPciePorts; Index++) { + if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) { + for (Entry = 0; Entry < TableSize; Entry++) { + if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) && + (PcieTopologyReal[Index] == PtssTables[Entry].Topology)) { + PtssTableIndex++; + if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) { + FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] = TRUE; + FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0); + } else { + ASSERT (FALSE); + } + } + } + } + } + //Case 2: BoardId is unknown, Topology is known/unknown + if (PtssTableIndex == 0) { + DEBUG ((DEBUG_INFO, "PTSS Settings for unknown board will be applied\n")); + + PtssTables = UnknowPtssTables; + TableSize = UnknowTableSize; + + for (Index = 0; Index < MaxSataPorts; Index++) { + if (PchGetSataLaneNum (Index, &LaneNum) == EFI_SUCCESS) { + for (Entry = 0; Entry < TableSize; Entry++) { + if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_SATA) + ) + { + if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD20) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) == (UINT32) B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0)) { + FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] = TRUE; + FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] = (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0; + } else if (PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_TX_DWORD8) { + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) { + FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index] = TRUE; + FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0); + } + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) == (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) { + FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index] = TRUE; + FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0); + } + } else { + ASSERT (FALSE); + } + } + } + } + } + for (Index = 0; Index < MaxPciePorts; Index++) { + if (PchGetPcieLaneNum (Index, &LaneNum) == EFI_SUCCESS) { + for (Entry = 0; Entry < TableSize; Entry++) { + if ((LaneNum == PtssTables[Entry].PtssTable.LaneNum) && + (PtssTables[Entry].PtssTable.PhyMode == V_PCH_PCR_FIA_LANE_OWN_PCIEDMI) && + (PcieTopologyReal[Index] == PtssTables[Entry].Topology)) { + if ((PtssTables[Entry].PtssTable.Offset == (UINT32) R_PCH_HSIO_RX_DWORD25) && + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) == (UINT32) B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0)) { + FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] = TRUE; + FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] = (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0); + } else { + ASSERT (FALSE); + } + } + } + } + } + } +} + +/** + Performs FSP PCH PEI Policy pre mem initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspPchPolicyUpdatePreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + InstallPlatformHsioPtssTable (FspmUpd); + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c new file mode 100644 index 0000000000..fd54c63a92 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c @@ -0,0 +1,90 @@ +/** @file +Do Platform Stage System Agent initialization. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "PeiSaPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Performs FSP SA PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSaPolicyUpdate ( + IN OUT FSPS_UPD *FspsUpd + ) +{ + VOID *Buffer; + VOID *MemBuffer; + UINT32 Size; + + DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n")); + + FspsUpd->FspsConfig.PeiGraphicsPeimInit = 1; + + Size = 0; + Buffer = NULL; + PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size); + if (Buffer == NULL) { + DEBUG((DEBUG_WARN, "Could not locate VBT\n")); + } else { + MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)); + if ((MemBuffer != NULL) && (Buffer != NULL)) { + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); + FspsUpd->FspsConfig.GraphicsConfigPtr = (UINT32)(UINTN)MemBuffer; + } else { + DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n")); + FspsUpd->FspsConfig.GraphicsConfigPtr = 0; + } + } + DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", FspsUpd->FspsConfig.GraphicsConfigPtr)); + DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size)); + + Size = 0; + Buffer = NULL; + PeiGetSectionFromAnyFv (&gTianoLogoGuid, EFI_SECTION_RAW, 0, &Buffer, &Size); + if (Buffer == NULL) { + DEBUG((DEBUG_WARN, "Could not locate Logo\n")); + } else { + MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)); + if ((MemBuffer != NULL) && (Buffer != NULL)) { + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); + FspsUpd->FspsConfig.LogoPtr = (UINT32)(UINTN)MemBuffer; + FspsUpd->FspsConfig.LogoSize = Size; + } else { + DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n")); + FspsUpd->FspsConfig.LogoPtr = 0; + FspsUpd->FspsConfig.LogoSize = 0; + } + } + DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", FspsUpd->FspsConfig.LogoPtr)); + DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n", FspsUpd->FspsConfig.LogoSize)); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h new file mode 100644 index 0000000000..da6f746772 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h @@ -0,0 +1,36 @@ +/** @file + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PEI_SA_POLICY_UPDATE_H_ +#define _PEI_SA_POLICY_UPDATE_H_ + +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#include +#include +#include +#include +#include "PeiPchPolicyUpdate.h" +#include +#include + +#include +#include +#include + +extern EFI_GUID gTianoLogoGuid; + +#endif + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c new file mode 100644 index 0000000000..94d5094855 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c @@ -0,0 +1,74 @@ +/** @file +Do Platform Stage System Agent initialization. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "PeiSaPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +/** + Performs FSP SA PEI Policy initialization in pre-memory. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSaPolicyUpdatePreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + VOID *Buffer; + + CopyMem((VOID *)(UINTN)FspmUpd->FspmConfig.MemorySpdPtr00, (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize)); + CopyMem((VOID *)(UINTN)FspmUpd->FspmConfig.MemorySpdPtr10, (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize)); + + DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Settings...\n")); + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap); + if (Buffer) { + CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh0, Buffer, 12); + CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh1, (UINT8*) Buffer + 12, 12); + } + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram); + if (Buffer) { + CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh0, Buffer, 8); + CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh1, (UINT8*) Buffer + 8, 8); + } + + DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & Rcomp Target Settings...\n")); + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor); + if (Buffer) { + CopyMem ((VOID *)FspmUpd->FspmConfig.RcompResistor, Buffer, 6); + } + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget); + if (Buffer) { + CopyMem ((VOID *)FspmUpd->FspmConfig.RcompTarget, Buffer, 10); + } + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf new file mode 100644 index 0000000000..c91c17a499 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf @@ -0,0 +1,145 @@ +## @file +# Provide FSP wrapper platform related function. +# +# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SiliconPolicyUpdateLibFsp + FILE_GUID = 4E83003B-49A9-459E-AAA6-1CA3C6D04FB2 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + LIBRARY_CLASS = SiliconPolicyUpdateLib + + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 +# + +################################################################################ +# +# Sources Section - list of files that are required for the build to succeed. +# +################################################################################ + +[Sources] + PeiFspPolicyUpdateLib.c + PeiPchPolicyUpdatePreMem.c + PeiPchPolicyUpdate.c + PeiSaPolicyUpdatePreMem.c + PeiSaPolicyUpdate.c + PeiFspMiscUpdUpdateLib.c + PcieDeviceTable.c + +################################################################################ +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +################################################################################ + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + KabylakeSiliconPkg/SiPkg.dec + KabylakeFspBinPkg/KabylakeFspBinPkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + +[LibraryClasses.IA32] + FspWrapperApiLib + OcWdtLib + PchResetLib + FspWrapperPlatformLib + BaseMemoryLib + CpuPlatformLib + DebugLib + HobLib + IoLib + PcdLib + PostCodeLib + SmbusLib + MmPciLib + ConfigBlockLib + PeiSaPolicyLib + PchGbeLib + PchInfoLib + PchHsioLib + PchPcieRpLib + MemoryAllocationLib + CpuMailboxLib + DebugPrintErrorLevelLib + SiPolicyLib + PchGbeLib + TimerLib + GpioLib + PeiLib + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdData + gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSmmbaseSwSmi ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit ## CONSUMES + + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size + + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size + + gBoardModuleTokenSpaceGuid.PcdHdaVerbTable + gBoardModuleTokenSpaceGuid.PcdHdaVerbTable2 + gBoardModuleTokenSpaceGuid.PcdExtHdaVerbTable + gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable1 + gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable2 + gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable3 + gBoardModuleTokenSpaceGuid.PcdDisplayAudioHdaVerbTable + + gBoardModuleTokenSpaceGuid.PcdAudioConnector + + gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid + +[Guids] + gFspNonVolatileStorageHobGuid ## CONSUMES + gTianoLogoGuid ## CONSUMES + gEfiMemoryOverwriteControlDataGuid + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc index f82ceeaaac..99b0eb5d51 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc @@ -103,8 +103,8 @@ FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib/PeiFspWrapperApiTestLib.inf FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapperPlatformLib/PeiFspWrapperPlatformLib.inf - FspPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf - FspPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiFspPolicyUpdateLib/PeiFspPolicyUpdateLib.inf + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf + SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf ConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseConfigBlockLib/BaseConfigBlockLib.inf SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/SiliconInitLib/SiliconInitLib.inf @@ -152,6 +152,9 @@ MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/DxeMultiBoardAcpiSupportLib.inf BoardAcpiTableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/DxeMultiBoardAcpiSupportLib.inf + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/DxeSiliconPolicyInitLib/DxeSiliconPolicyInitLib.inf + SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf + # # Silicon Init Package # @@ -214,7 +217,7 @@ # !include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc - $(PLATFORM_BOARD_PACKAGE)/Policy/PolicyInitDxe/PolicyInitDxe.inf + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf { !if $(TARGET) == DEBUG diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf index 2ca305e005..230943d074 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf @@ -477,7 +477,7 @@ APRIORI DXE { INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf !if gPlatformModuleTokenSpaceGuid.PcdBootToShellOnly == FALSE -INF $(PLATFORM_BOARD_PACKAGE)/Policy/PolicyInitDxe/PolicyInitDxe.inf +INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxe.inf $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c b/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c new file mode 100644 index 0000000000..e455208f80 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c @@ -0,0 +1,181 @@ +/** @file + This file initialises and Installs GopPolicy Protocol. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "DxeGopPolicyInit.h" +#include + +GLOBAL_REMOVE_IF_UNREFERENCED GOP_POLICY_PROTOCOL mGOPPolicy; +GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mVbtSize = 0; +GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS mVbtAddress = 0; + +// +// Function implementations +// + +/** + + @param[out] CurrentLidStatus + + @retval EFI_SUCCESS + @retval EFI_UNSUPPORTED +**/ +EFI_STATUS +EFIAPI +GetPlatformLidStatus ( + OUT LID_STATUS *CurrentLidStatus + ) +{ + return EFI_UNSUPPORTED; +} +/** + + @param[out] CurrentDockStatus + + @retval EFI_SUCCESS + @retval EFI_UNSUPPORTED +**/ +EFI_STATUS +EFIAPI +GetPlatformDockStatus ( + OUT DOCK_STATUS CurrentDockStatus + ) +{ + return EFI_UNSUPPORTED; +} + + +/** + + @param[out] VbtAddress + @param[out] VbtSize + + @retval EFI_SUCCESS + @retval EFI_NOT_FOUND +**/ +EFI_STATUS +EFIAPI +GetVbtData ( + OUT EFI_PHYSICAL_ADDRESS *VbtAddress, + OUT UINT32 *VbtSize + ) +{ + EFI_STATUS Status; + UINTN FvProtocolCount; + EFI_HANDLE *FvHandles; + EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv; + UINTN Index; + UINT32 AuthenticationStatus; + UINT8 *Buffer; + UINTN VbtBufferSize; + + + Status = EFI_NOT_FOUND; + if ( mVbtAddress == 0) { + Fv = NULL; + + Buffer = 0; + FvHandles = NULL; + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiFirmwareVolume2ProtocolGuid, + NULL, + &FvProtocolCount, + &FvHandles + ); + if (!EFI_ERROR (Status)) { + for (Index = 0; Index < FvProtocolCount; Index++) { + Status = gBS->HandleProtocol ( + FvHandles[Index], + &gEfiFirmwareVolume2ProtocolGuid, + (VOID **) &Fv + ); + VbtBufferSize = 0; + Status = Fv->ReadSection ( + Fv, + PcdGetPtr (PcdGraphicsVbtGuid), + EFI_SECTION_RAW, + 0, + (VOID **) &Buffer, + &VbtBufferSize, + &AuthenticationStatus + ); + if (!EFI_ERROR (Status)) { + *VbtAddress = (EFI_PHYSICAL_ADDRESS)Buffer; + *VbtSize = (UINT32)VbtBufferSize; + mVbtAddress = *VbtAddress; + mVbtSize = *VbtSize; + Status = EFI_SUCCESS; + break; + } + } + } else { + Status = EFI_NOT_FOUND; + } + + if (FvHandles != NULL) { + FreePool (FvHandles); + FvHandles = NULL; + } + } else { + *VbtAddress = mVbtAddress; + *VbtSize = mVbtSize; + Status = EFI_SUCCESS; + } + + return Status; +} + + + +/** +Initialize GOP DXE Policy + +@param[in] ImageHandle Image handle of this driver. + +@retval EFI_SUCCESS Initialization complete. +@retval EFI_UNSUPPORTED The chipset is unsupported by this driver. +@retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver. +@retval EFI_DEVICE_ERROR Device error, driver exits abnormally. +**/ + +EFI_STATUS +EFIAPI +GopPolicyInitDxe ( + IN EFI_HANDLE ImageHandle + ) +{ + EFI_STATUS Status; + + // + // Initialize the EFI Driver Library + // + SetMem (&mGOPPolicy, sizeof (GOP_POLICY_PROTOCOL), 0); + + mGOPPolicy.Revision = GOP_POLICY_PROTOCOL_REVISION_03; + mGOPPolicy.GetPlatformLidStatus = GetPlatformLidStatus; + mGOPPolicy.GetVbtData = GetVbtData; + mGOPPolicy.GetPlatformDockStatus = GetPlatformDockStatus; + + // + // Install protocol to allow access to this Policy. + // + Status = gBS->InstallMultipleProtocolInterfaces ( + &ImageHandle, + &gGopPolicyProtocolGuid, + &mGOPPolicy, + NULL + ); + + return Status; +} diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.h b/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.h new file mode 100644 index 0000000000..3de117337f --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.h @@ -0,0 +1,45 @@ +/** @file +Header file for the GopPolicyInitDxe Driver. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _GOP_POLICY_INIT_DXE_H_ +#define _GOP_POLICY_INIT_DXE_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +/** +Initialize GOP DXE Policy + +@param[in] ImageHandle Image handle of this driver. + +@retval EFI_SUCCESS Initialization complete. +@retval EFI_UNSUPPORTED The chipset is unsupported by this driver. +@retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver. +@retval EFI_DEVICE_ERROR Device error, driver exits abnormally. +**/ +EFI_STATUS +EFIAPI +GopPolicyInitDxe( + IN EFI_HANDLE ImageHandle + ); + +#endif diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.h b/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.h new file mode 100644 index 0000000000..1a1536c299 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.h @@ -0,0 +1,70 @@ +/** @file + Header file for the SaPolicyInitDxe Driver. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef _SA_POLICY_INIT_DXE_H_ +#define _SA_POLICY_INIT_DXE_H_ + +#include +#include +#include +#include +#include +#include + +#include + + +/** + SA DXE Policy Driver Entry Point \n + - Introduction \n + System Agent DXE drivers behavior can be controlled by platform policy without modifying reference code directly. + Platform policy Protocol is initialized with default settings in this funciton. + This policy Protocol has to be initialized prior to System Agent initialization DXE drivers execution. + + - @pre + - Runtime variable service should be ready if policy initialization required. + + - @result + SA_POLICY_PROTOCOL will be installed successfully and ready for System Agent reference code use. + + - Porting Recommendations \n + Policy should be initialized basing on platform design or user selection (like BIOS Setup Menu) + + @param[in] ImageHandle - Image handle of this driver. + + @retval EFI_SUCCESS Initialization complete. + @exception EFI_UNSUPPORTED The chipset is unsupported by this driver. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver. + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. +**/ +EFI_STATUS +EFIAPI +SaPolicyInitDxe ( + IN EFI_HANDLE ImageHandle + ); + +/** + Get data for platform policy from setup options. + + @param[in] SaPolicy The pointer to get SA Policy protocol instance + + @retval EFI_SUCCESS Operation success. + +**/ +EFI_STATUS +EFIAPI +UpdateDxeSaPolicy ( + IN OUT SA_POLICY_PROTOCOL *SaPolicy + ); + +#endif diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c new file mode 100644 index 0000000000..be3fe02aea --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c @@ -0,0 +1,71 @@ +/** @file + This file is the library for SA DXE Policy initialization. + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "DxeSaPolicyInit.h" + +#define SA_VTD_RMRR_USB_LENGTH 0x20000 + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS mAddress; +GLOBAL_REMOVE_IF_UNREFERENCED UINTN mSize; + +/** + Update RMRR Base and Limit Address for USB. + +**/ +VOID +UpdateRmrrUsbAddress ( + IN OUT SA_POLICY_PROTOCOL *SaPolicy + ) +{ + EFI_STATUS Status; + MISC_DXE_CONFIG *MiscDxeConfig; + + Status = GetConfigBlock ((VOID *)SaPolicy, &gMiscDxeConfigGuid, (VOID *)&MiscDxeConfig); + ASSERT_EFI_ERROR (Status); + + if (1) { + mSize = EFI_SIZE_TO_PAGES(SA_VTD_RMRR_USB_LENGTH); + mAddress = SIZE_4GB; + + Status = (gBS->AllocatePages) ( + AllocateMaxAddress, + EfiReservedMemoryType, + mSize, + &mAddress + ); + ASSERT_EFI_ERROR (Status); + + MiscDxeConfig->RmrrUsbBaseAddress[0] = mAddress; + MiscDxeConfig->RmrrUsbBaseAddress[1] = mAddress + SA_VTD_RMRR_USB_LENGTH - 1; + } +} + +/** + Get data for platform policy from setup options. + + @param[in] SaPolicy The pointer to get SA Policy protocol instance + + @retval EFI_SUCCESS Operation success. + +**/ +EFI_STATUS +EFIAPI +UpdateDxeSaPolicy ( + IN OUT SA_POLICY_PROTOCOL *SaPolicy + ) +{ + UpdateRmrrUsbAddress (SaPolicy); + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c new file mode 100644 index 0000000000..6a258e69d6 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c @@ -0,0 +1,59 @@ +/** @file + +Copyright (c) 2017, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include + +#include "DxeSaPolicyInit.h" +#include "DxeGopPolicyInit.h" + +/** + Performs silicon late policy update. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a Protocol, etc. + + The input Policy must be returned by SiliconPolicyDoneLate(). + + In FSP or non-FSP path, the board may use additional way to get + the silicon policy data field based upon the input Policy. + + @param[in, out] Policy Pointer to policy. + + @return the updated policy. +**/ +VOID * +EFIAPI +SiliconPolicyUpdateLate ( + IN VOID *Policy + ) +{ + SA_POLICY_PROTOCOL *SaPolicy; + EFI_STATUS Status; + + SaPolicy = Policy; + UpdateDxeSaPolicy (SaPolicy); + + if (PcdGetBool(PcdIntelGopEnable)) { + // + // GOP Dxe Policy Initialization + // + Status = GopPolicyInitDxe(gImageHandle); + DEBUG((DEBUG_INFO, "GOP Dxe Policy Initialization done\n")); + ASSERT_EFI_ERROR(Status); + } + + return Policy; +} + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf new file mode 100644 index 0000000000..7a50563c84 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf @@ -0,0 +1,55 @@ +## @file +# Component information file for Silicon Update Library +# +# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = DxeSiliconUpdateLib + FILE_GUID = C523609D-E354-416B-B24F-33468D4BD21D + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = SiliconUpdateLib + +[LibraryClasses] + BaseLib + PcdLib + DebugLib + +[Packages] + MdePkg/MdePkg.dec + KabylakeSiliconPkg/SiPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + +[Sources] + DxeSiliconPolicyUpdateLib.c + DxeGopPolicyInit.c + DxeSaPolicyUpdate.c + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdIntelGopEnable + gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid + +[Protocols] + gEfiFirmwareVolume2ProtocolGuid ## CONSUMES + gSaPolicyProtocolGuid ## CONSUMES + gDxeSiPolicyProtocolGuid ## PRODUCES + gGopPolicyProtocolGuid ## PRODUCES + +[Guids] + gMiscDxeConfigGuid + +[Depex] + gEfiVariableArchProtocolGuid + diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/DxeSaPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/DxeSaPolicyUpdate.c deleted file mode 100644 index 384b94ba54..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/DxeSaPolicyUpdate.c +++ /dev/null @@ -1,71 +0,0 @@ -/** @file - This file is the library for SA DXE Policy initialization. - -Copyright (c) 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include "SaPolicyInitDxe.h" - -#define SA_VTD_RMRR_USB_LENGTH 0x20000 - -GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS mAddress; -GLOBAL_REMOVE_IF_UNREFERENCED UINTN mSize; - -/** - Update RMRR Base and Limit Address for USB. - -**/ -VOID -UpdateRmrrUsbAddress ( - IN OUT SA_POLICY_PROTOCOL *SaPolicy - ) -{ - EFI_STATUS Status; - MISC_DXE_CONFIG *MiscDxeConfig; - - Status = GetConfigBlock ((VOID *)SaPolicy, &gMiscDxeConfigGuid, (VOID *)&MiscDxeConfig); - ASSERT_EFI_ERROR (Status); - - if (1) { - mSize = EFI_SIZE_TO_PAGES(SA_VTD_RMRR_USB_LENGTH); - mAddress = SIZE_4GB; - - Status = (gBS->AllocatePages) ( - AllocateMaxAddress, - EfiReservedMemoryType, - mSize, - &mAddress - ); - ASSERT_EFI_ERROR (Status); - - MiscDxeConfig->RmrrUsbBaseAddress[0] = mAddress; - MiscDxeConfig->RmrrUsbBaseAddress[1] = mAddress + SA_VTD_RMRR_USB_LENGTH - 1; - } -} - -/** - Get data for platform policy from setup options. - - @param[in] SaPolicy The pointer to get SA Policy protocol instance - - @retval EFI_SUCCESS Operation success. - -**/ -EFI_STATUS -EFIAPI -UpdateDxeSaPolicy ( - IN OUT SA_POLICY_PROTOCOL *SaPolicy - ) -{ - UpdateRmrrUsbAddress (SaPolicy); - return EFI_SUCCESS; -} - diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/GopPolicyInitDxe.c b/Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/GopPolicyInitDxe.c deleted file mode 100644 index ff7cb3660b..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/GopPolicyInitDxe.c +++ /dev/null @@ -1,181 +0,0 @@ -/** @file - This file initialises and Installs GopPolicy Protocol. - -Copyright (c) 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include "GopPolicyInitDxe.h" -#include - -GLOBAL_REMOVE_IF_UNREFERENCED GOP_POLICY_PROTOCOL mGOPPolicy; -GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mVbtSize = 0; -GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS mVbtAddress = 0; - -// -// Function implementations -// - -/** - - @param[out] CurrentLidStatus - - @retval EFI_SUCCESS - @retval EFI_UNSUPPORTED -**/ -EFI_STATUS -EFIAPI -GetPlatformLidStatus ( - OUT LID_STATUS *CurrentLidStatus - ) -{ - return EFI_UNSUPPORTED; -} -/** - - @param[out] CurrentDockStatus - - @retval EFI_SUCCESS - @retval EFI_UNSUPPORTED -**/ -EFI_STATUS -EFIAPI -GetPlatformDockStatus ( - OUT DOCK_STATUS CurrentDockStatus - ) -{ - return EFI_UNSUPPORTED; -} - - -/** - - @param[out] VbtAddress - @param[out] VbtSize - - @retval EFI_SUCCESS - @retval EFI_NOT_FOUND -**/ -EFI_STATUS -EFIAPI -GetVbtData ( - OUT EFI_PHYSICAL_ADDRESS *VbtAddress, - OUT UINT32 *VbtSize - ) -{ - EFI_STATUS Status; - UINTN FvProtocolCount; - EFI_HANDLE *FvHandles; - EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv; - UINTN Index; - UINT32 AuthenticationStatus; - UINT8 *Buffer; - UINTN VbtBufferSize; - - - Status = EFI_NOT_FOUND; - if ( mVbtAddress == 0) { - Fv = NULL; - - Buffer = 0; - FvHandles = NULL; - Status = gBS->LocateHandleBuffer ( - ByProtocol, - &gEfiFirmwareVolume2ProtocolGuid, - NULL, - &FvProtocolCount, - &FvHandles - ); - if (!EFI_ERROR (Status)) { - for (Index = 0; Index < FvProtocolCount; Index++) { - Status = gBS->HandleProtocol ( - FvHandles[Index], - &gEfiFirmwareVolume2ProtocolGuid, - (VOID **) &Fv - ); - VbtBufferSize = 0; - Status = Fv->ReadSection ( - Fv, - PcdGetPtr (PcdGraphicsVbtGuid), - EFI_SECTION_RAW, - 0, - (VOID **) &Buffer, - &VbtBufferSize, - &AuthenticationStatus - ); - if (!EFI_ERROR (Status)) { - *VbtAddress = (EFI_PHYSICAL_ADDRESS)Buffer; - *VbtSize = (UINT32)VbtBufferSize; - mVbtAddress = *VbtAddress; - mVbtSize = *VbtSize; - Status = EFI_SUCCESS; - break; - } - } - } else { - Status = EFI_NOT_FOUND; - } - - if (FvHandles != NULL) { - FreePool (FvHandles); - FvHandles = NULL; - } - } else { - *VbtAddress = mVbtAddress; - *VbtSize = mVbtSize; - Status = EFI_SUCCESS; - } - - return Status; -} - - - -/** -Initialize GOP DXE Policy - -@param[in] ImageHandle Image handle of this driver. - -@retval EFI_SUCCESS Initialization complete. -@retval EFI_UNSUPPORTED The chipset is unsupported by this driver. -@retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver. -@retval EFI_DEVICE_ERROR Device error, driver exits abnormally. -**/ - -EFI_STATUS -EFIAPI -GopPolicyInitDxe ( - IN EFI_HANDLE ImageHandle - ) -{ - EFI_STATUS Status; - - // - // Initialize the EFI Driver Library - // - SetMem (&mGOPPolicy, sizeof (GOP_POLICY_PROTOCOL), 0); - - mGOPPolicy.Revision = GOP_POLICY_PROTOCOL_REVISION_03; - mGOPPolicy.GetPlatformLidStatus = GetPlatformLidStatus; - mGOPPolicy.GetVbtData = GetVbtData; - mGOPPolicy.GetPlatformDockStatus = GetPlatformDockStatus; - - // - // Install protocol to allow access to this Policy. - // - Status = gBS->InstallMultipleProtocolInterfaces ( - &ImageHandle, - &gGopPolicyProtocolGuid, - &mGOPPolicy, - NULL - ); - - return Status; -} diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/GopPolicyInitDxe.h b/Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/GopPolicyInitDxe.h deleted file mode 100644 index 3de117337f..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/GopPolicyInitDxe.h +++ /dev/null @@ -1,45 +0,0 @@ -/** @file -Header file for the GopPolicyInitDxe Driver. - -Copyright (c) 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ -#ifndef _GOP_POLICY_INIT_DXE_H_ -#define _GOP_POLICY_INIT_DXE_H_ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - - -/** -Initialize GOP DXE Policy - -@param[in] ImageHandle Image handle of this driver. - -@retval EFI_SUCCESS Initialization complete. -@retval EFI_UNSUPPORTED The chipset is unsupported by this driver. -@retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver. -@retval EFI_DEVICE_ERROR Device error, driver exits abnormally. -**/ -EFI_STATUS -EFIAPI -GopPolicyInitDxe( - IN EFI_HANDLE ImageHandle - ); - -#endif diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.c b/Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.c deleted file mode 100644 index 6faa9e0bd6..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.c +++ /dev/null @@ -1,56 +0,0 @@ -/** @file - This file is a wrapper for Platform Policy driver. Get Setup - Value to initialize Intel DXE Platform Policy. - -Copyright (c) 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include "PolicyInitDxe.h" - -/** - Initialize DXE Platform Policy - - @param[in] ImageHandle Image handle of this driver. - @param[in] SystemTable Global system service table. - - @retval EFI_SUCCESS Initialization complete. - @exception EFI_UNSUPPORTED The chipset is unsupported by this driver. - @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver. - @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. -**/ -EFI_STATUS -EFIAPI -PolicyInitDxeEntryPoint ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - - // - // SystemAgent Dxe Platform Policy Initialization - // - Status = SaPolicyInitDxe (ImageHandle); - DEBUG ((DEBUG_INFO, "SystemAgent Dxe Platform Policy Initialization done\n")); - ASSERT_EFI_ERROR (Status); - - if (PcdGetBool(PcdIntelGopEnable)) { - // - // GOP Dxe Policy Initialization - // - Status = GopPolicyInitDxe(ImageHandle); - DEBUG((DEBUG_INFO, "GOP Dxe Policy Initialization done\n")); - ASSERT_EFI_ERROR(Status); - } - - return Status; - -} diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.h b/Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.h deleted file mode 100644 index 3b57753112..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.h +++ /dev/null @@ -1,46 +0,0 @@ -/** @file - Header file for the PolicyInitDxe Driver. - -Copyright (c) 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ -#ifndef _POLICY_INIT_DXE_H_ -#define _POLICY_INIT_DXE_H_ - - -#include -#include -#include -#include - -#include "SaPolicyInitDxe.h" -#include "GopPolicyInitDxe.h" - -/** - Initialize DXE Platform Policy - - @param[in] ImageHandle - Image handle of this driver. - @param[in] SystemTable - Global system service table. - - @retval EFI_SUCCESS Initialization complete. - @exception EFI_UNSUPPORTED The chipset is unsupported by this driver. - @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver. - @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. -**/ - -EFI_STATUS -EFIAPI -PolicyInitDxeEntryPoint ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -; - -#endif diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.inf b/Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.inf deleted file mode 100644 index 5f9ed1ee82..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.inf +++ /dev/null @@ -1,74 +0,0 @@ -### @file -# Module Information file for the PolicyInit DXE driver. -# -# Copyright (c) 2017, Intel Corporation. All rights reserved.
-# -# This program and the accompanying materials are licensed and made available under -# the terms and conditions of the BSD License which accompanies this distribution. -# The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -### - -[Defines] - INF_VERSION = 0x00010017 - BASE_NAME = KabylakeRvp3PolicyInitDxe - FILE_GUID = 490D0119-4448-440D-8F5C-F58FB53EE057 - VERSION_STRING = 1.0 - MODULE_TYPE = DXE_DRIVER - ENTRY_POINT = PolicyInitDxeEntryPoint - -[LibraryClasses] - BaseLib - BaseMemoryLib - CpuPlatformLib - DebugLib - DxeServicesTableLib - IoLib - MemoryAllocationLib - DxeSaPolicyLib - MmPciLib - PcdLib - PostCodeLib - UefiBootServicesTableLib - UefiDriverEntryPoint - UefiLib - UefiRuntimeServicesTableLib - ConfigBlockLib - -[Packages] - MdePkg/MdePkg.dec - KabylakeSiliconPkg/SiPkg.dec - MinPlatformPkg/MinPlatformPkg.dec - KabylakeOpenBoardPkg/OpenBoardPkg.dec - -[Pcd] - gBoardModuleTokenSpaceGuid.PcdIntelGopEnable - -[Sources] - PolicyInitDxe.c - PolicyInitDxe.h - SaPolicyInitDxe.c - SaPolicyInitDxe.h - GopPolicyInitDxe.c - GopPolicyInitDxe.h - DxeSaPolicyUpdate.c - -[Protocols] - gEfiFirmwareVolume2ProtocolGuid ## CONSUMES - gSaPolicyProtocolGuid ## CONSUMES - gDxeSiPolicyProtocolGuid ## PRODUCES - gGopPolicyProtocolGuid ## PRODUCES - -[Guids] - gMiscDxeConfigGuid - -[Pcd] - gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid - -[Depex] - gEfiVariableArchProtocolGuid - diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/SaPolicyInitDxe.c b/Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/SaPolicyInitDxe.c deleted file mode 100644 index 09e084f9f6..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/SaPolicyInitDxe.c +++ /dev/null @@ -1,73 +0,0 @@ -/** @file - This file is SampleCode for SA DXE Policy initialization. - -Copyright (c) 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ -#include "SaPolicyInitDxe.h" - -// -// Function implementations -// - -/** - Get data for platform policy from setup options. - - @param[in] SaPolicy The pointer to get SA Policy protocol instance - - @retval EFI_SUCCESS Operation success. - -**/ -EFI_STATUS -EFIAPI -UpdateDxeSaPolicy ( - IN OUT SA_POLICY_PROTOCOL *SaPolicy - ); - - -/** - Initialize SA DXE Policy - - @param[in] ImageHandle Image handle of this driver. - - @retval EFI_SUCCESS Initialization complete. - @exception EFI_UNSUPPORTED The chipset is unsupported by this driver. - @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver. - @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. -**/ -EFI_STATUS -EFIAPI -SaPolicyInitDxe ( - IN EFI_HANDLE ImageHandle - ) -{ - EFI_STATUS Status; - SA_POLICY_PROTOCOL *SaPolicy; - - // - // Call CreateSaDxeConfigBlocks to create & initialize platform policy structure - // and get all Intel default policy settings. - // - Status = CreateSaDxeConfigBlocks(&SaPolicy); - DEBUG((DEBUG_INFO, "SaPolicy->TableHeader.NumberOfBlocks = 0x%x\n ", SaPolicy->TableHeader.NumberOfBlocks)); - ASSERT_EFI_ERROR(Status); - - UpdateDxeSaPolicy (SaPolicy); - - // - // Install SaInstallPolicyProtocol. - // While installed, RC assumes the Policy is ready and finalized. So please - // update and override any setting before calling this function. - // - Status = SaInstallPolicyProtocol (ImageHandle, SaPolicy); - ASSERT_EFI_ERROR (Status); - - return Status; -} diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/SaPolicyInitDxe.h b/Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/SaPolicyInitDxe.h deleted file mode 100644 index ebc5023f7b..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/Policy/PolicyInitDxe/SaPolicyInitDxe.h +++ /dev/null @@ -1,56 +0,0 @@ -/** @file - Header file for the SaPolicyInitDxe Driver. - -Copyright (c) 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ -#ifndef _SA_POLICY_INIT_DXE_H_ -#define _SA_POLICY_INIT_DXE_H_ - -#include -#include -#include -#include -#include -#include - -#include - - -/** - SA DXE Policy Driver Entry Point \n - - Introduction \n - System Agent DXE drivers behavior can be controlled by platform policy without modifying reference code directly. - Platform policy Protocol is initialized with default settings in this funciton. - This policy Protocol has to be initialized prior to System Agent initialization DXE drivers execution. - - - @pre - - Runtime variable service should be ready if policy initialization required. - - - @result - SA_POLICY_PROTOCOL will be installed successfully and ready for System Agent reference code use. - - - Porting Recommendations \n - Policy should be initialized basing on platform design or user selection (like BIOS Setup Menu) - - @param[in] ImageHandle - Image handle of this driver. - - @retval EFI_SUCCESS Initialization complete. - @exception EFI_UNSUPPORTED The chipset is unsupported by this driver. - @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver. - @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. -**/ -EFI_STATUS -EFIAPI -SaPolicyInitDxe ( - IN EFI_HANDLE ImageHandle - ); - -#endif -- cgit v1.2.3