From 6bd758d49363906e0145576cea0bbbcaae0742e6 Mon Sep 17 00:00:00 2001 From: Jiewen Yao Date: Thu, 28 Sep 2017 11:26:47 +0800 Subject: Rename gPlatformModuleTokenSpaceGuid to gMinPlatformModuleTokenSpaceGuid. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao --- .../Acpi/BoardAcpiDxe/BoardAcpiDxe.inf | 2 +- .../Include/Fdf/FlashMapInclude.fdf | 52 +++++++++--------- .../Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf | 6 +- .../BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf | 6 +- .../KabylakeRvp3/OpenBoardPkg.dsc | 6 +- .../KabylakeRvp3/OpenBoardPkg.fdf | 64 +++++++++++----------- .../KabylakeRvp3/OpenBoardPkgConfig.dsc | 42 +++++++------- .../KabylakeRvp3/OpenBoardPkgPcd.dsc | 18 +++--- .../KabylakeOpenBoardPkg/KabylakeRvp3/bld.bat | 2 +- 9 files changed, 99 insertions(+), 99 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf index e37afb0b90..4fdd6233fb 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf @@ -60,7 +60,7 @@ gBoardModuleTokenSpaceGuid.PcdAcpiSleepState gBoardModuleTokenSpaceGuid.PcdAcpiHibernate - gPlatformModuleTokenSpaceGuid.PcdLowPowerS0Idle + gMinPlatformModuleTokenSpaceGuid.PcdLowPowerS0Idle gBoardModuleTokenSpaceGuid.PcdDisableActiveTripPoints gBoardModuleTokenSpaceGuid.PcdDisablePassiveTripPoints gBoardModuleTokenSpaceGuid.PcdDisableCriticalTripPoints diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf b/Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf index 3238a63a0a..283c4e9b40 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf +++ b/Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf @@ -22,29 +22,29 @@ DEFINE FLASH_BLOCK_SIZE = 0x00010000 DEFINE FLASH_NUM_BLOCKS = 0x00000080 # #=================================================================================# -SET gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageOffset = 0x00000000 # Flash addr (0xFF800000) -SET gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageSize = 0x00040000 # -SET gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageVariableOffset = 0x00000000 # Flash addr (0xFF800000) -SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = 0x0001E000 # -SET gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = 0x0001E000 # Flash addr (0xFF81E000) -SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize = 0x00002000 # -SET gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = 0x00020000 # Flash addr (0xFF820000) -SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = 0x00020000 # -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvAdvancedOffset = 0x00040000 # Flash addr (0xFF840000) -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvAdvancedSize = 0x00060000 # -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvSecurityOffset = 0x000A0000 # Flash addr (0xFF8A0000) -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvSecuritySize = 0x00070000 # -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvOsBootOffset = 0x00110000 # Flash addr (0xFF910000) -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvOsBootSize = 0x00090000 # -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvUefiBootOffset = 0x001A0000 # Flash addr (0xFF9A0000) -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x001E0000 # -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvPostMemoryOffset = 0x00380000 # Flash addr (0xFFB80000) -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvPostMemorySize = 0x00180000 # -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset = 0x00500000 # Flash addr (0xFFD00000) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = 0x000A0000 # -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvFspSOffset = 0x005A0000 # Flash addr (0xFFDA0000) -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvFspSSize = 0x00060000 # -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvFspMTOffset = 0x00600000 # Flash addr (0xFFE00000) -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvFspMTSize = 0x000C0000 # -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvPreMemoryOffset = 0x006C0000 # Flash addr (0xFFEC0000) -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvPreMemorySize = 0x00140000 # +SET gMinPlatformModuleTokenSpaceGuid.PcdFlashNvStorageOffset = 0x00000000 # Flash addr (0xFF800000) +SET gMinPlatformModuleTokenSpaceGuid.PcdFlashNvStorageSize = 0x00040000 # +SET gMinPlatformModuleTokenSpaceGuid.PcdFlashNvStorageVariableOffset = 0x00000000 # Flash addr (0xFF800000) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = 0x0001E000 # +SET gMinPlatformModuleTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = 0x0001E000 # Flash addr (0xFF81E000) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize = 0x00002000 # +SET gMinPlatformModuleTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = 0x00020000 # Flash addr (0xFF820000) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = 0x00020000 # +SET gMinPlatformModuleTokenSpaceGuid.PcdFlashFvAdvancedOffset = 0x00040000 # Flash addr (0xFF840000) +SET gMinPlatformModuleTokenSpaceGuid.PcdFlashFvAdvancedSize = 0x00060000 # +SET gMinPlatformModuleTokenSpaceGuid.PcdFlashFvSecurityOffset = 0x000A0000 # Flash addr (0xFF8A0000) +SET gMinPlatformModuleTokenSpaceGuid.PcdFlashFvSecuritySize = 0x00070000 # +SET gMinPlatformModuleTokenSpaceGuid.PcdFlashFvOsBootOffset = 0x00110000 # Flash addr (0xFF910000) +SET gMinPlatformModuleTokenSpaceGuid.PcdFlashFvOsBootSize = 0x00090000 # +SET gMinPlatformModuleTokenSpaceGuid.PcdFlashFvUefiBootOffset = 0x001A0000 # Flash addr (0xFF9A0000) +SET gMinPlatformModuleTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x001E0000 # +SET gMinPlatformModuleTokenSpaceGuid.PcdFlashFvPostMemoryOffset = 0x00380000 # Flash addr (0xFFB80000) +SET gMinPlatformModuleTokenSpaceGuid.PcdFlashFvPostMemorySize = 0x00180000 # +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset = 0x00500000 # Flash addr (0xFFD00000) +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = 0x000A0000 # +SET gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspSOffset = 0x005A0000 # Flash addr (0xFFDA0000) +SET gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspSSize = 0x00060000 # +SET gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspMTOffset = 0x00600000 # Flash addr (0xFFE00000) +SET gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspMTSize = 0x000C0000 # +SET gMinPlatformModuleTokenSpaceGuid.PcdFlashFvPreMemoryOffset = 0x006C0000 # Flash addr (0xFFEC0000) +SET gMinPlatformModuleTokenSpaceGuid.PcdFlashFvPreMemorySize = 0x00140000 # diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf index 053012bf37..0cd63164b3 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf @@ -42,9 +42,9 @@ [Pcd] gBoardModuleTokenSpaceGuid.PcdPs2KbMsEnable - gPlatformModuleTokenSpaceGuid.PcdPciExpNative - gPlatformModuleTokenSpaceGuid.PcdNativeAspmEnable - gPlatformModuleTokenSpaceGuid.PcdLowPowerS0Idle + gMinPlatformModuleTokenSpaceGuid.PcdPciExpNative + gMinPlatformModuleTokenSpaceGuid.PcdNativeAspmEnable + gMinPlatformModuleTokenSpaceGuid.PcdLowPowerS0Idle gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress [Sources] diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf index 6e60df9232..8aabdcd385 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf @@ -43,9 +43,9 @@ [Pcd] gBoardModuleTokenSpaceGuid.PcdPs2KbMsEnable - gPlatformModuleTokenSpaceGuid.PcdPciExpNative - gPlatformModuleTokenSpaceGuid.PcdNativeAspmEnable - gPlatformModuleTokenSpaceGuid.PcdLowPowerS0Idle + gMinPlatformModuleTokenSpaceGuid.PcdPciExpNative + gMinPlatformModuleTokenSpaceGuid.PcdNativeAspmEnable + gMinPlatformModuleTokenSpaceGuid.PcdLowPowerS0Idle gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress [Sources] diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc index e8541ebc0a..12b4199cd8 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc @@ -208,7 +208,7 @@ # Security # -!if gPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE +!if gMinPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf !endif @@ -249,7 +249,7 @@ # # OS Boot # -!if gPlatformModuleTokenSpaceGuid.PcdBootToShellOnly == FALSE +!if gMinPlatformModuleTokenSpaceGuid.PcdBootToShellOnly == FALSE $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf { !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE @@ -284,7 +284,7 @@ # $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf -!if gPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE +!if gMinPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf !endif diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf index e4e4be45e4..4721d5cbac 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf @@ -46,7 +46,7 @@ DEFINE SIPKG_PEI_BIN = INF # Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because macro expression is not supported. # So, PlatformSecLib uses PcdFlashAreaBaseAddress + PcdNemCodeCacheBase to get the real CodeCache base address. -SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase = $(gPlatformModuleTokenSpaceGuid.PcdFlashFvPreMemoryOffset) +SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase = $(gMinPlatformModuleTokenSpaceGuid.PcdFlashFvPreMemoryOffset) SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset) SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 @@ -54,13 +54,13 @@ SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpac SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset) SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset = 0x60 -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvMicrocodeBase = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvMicrocodeSize = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize -SET gPlatformModuleTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset +SET gMinPlatformModuleTokenSpaceGuid.PcdFlashFvMicrocodeBase = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase +SET gMinPlatformModuleTokenSpaceGuid.PcdFlashFvMicrocodeSize = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize +SET gMinPlatformModuleTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize -SET gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress -SET gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize +SET gMinPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress +SET gMinPlatformModuleTokenSpaceGuid.PcdFlashAreaSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize ################################################################################ # # Following are lists of FD Region layout which correspond to the locations of different @@ -77,7 +77,7 @@ SET gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize = gSiPkgTokenSpaceG # Fv Size can be adjusted # ################################################################################ -gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +gMinPlatformModuleTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize #NV_VARIABLE_STORE DATA = { @@ -102,7 +102,7 @@ DATA = { #Blockmap[1]: End 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ## This is the VARIABLE_STORE_HEADER -!if gPlatformModuleTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE +!if gMinPlatformModuleTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE # Signature: gEfiAuthenticatedVariableGuid = { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, @@ -118,7 +118,7 @@ DATA = { 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } -gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +gMinPlatformModuleTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize #NV_FTW_WORKING DATA = { @@ -132,28 +132,28 @@ DATA = { 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } -gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize +gMinPlatformModuleTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize #NV_FTW_SPARE -gPlatformModuleTokenSpaceGuid.PcdFlashFvAdvancedOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvAdvancedSize -gPlatformModuleTokenSpaceGuid.PcdFlashFvAdvancedBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvAdvancedSize +gMinPlatformModuleTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformModuleTokenSpaceGuid.PcdFlashFvAdvancedSize +gMinPlatformModuleTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformModuleTokenSpaceGuid.PcdFlashFvAdvancedSize FV = FvAdvanced -gPlatformModuleTokenSpaceGuid.PcdFlashFvSecurityOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvSecuritySize -gPlatformModuleTokenSpaceGuid.PcdFlashFvSecurityBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvSecuritySize +gMinPlatformModuleTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformModuleTokenSpaceGuid.PcdFlashFvSecuritySize +gMinPlatformModuleTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformModuleTokenSpaceGuid.PcdFlashFvSecuritySize FV = FvSecurity -gPlatformModuleTokenSpaceGuid.PcdFlashFvOsBootOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvOsBootSize -gPlatformModuleTokenSpaceGuid.PcdFlashFvOsBootBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvOsBootSize +gMinPlatformModuleTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformModuleTokenSpaceGuid.PcdFlashFvOsBootSize +gMinPlatformModuleTokenSpaceGuid.PcdFlashFvOsBootBase|gMinPlatformModuleTokenSpaceGuid.PcdFlashFvOsBootSize FV = FvOsBoot -gPlatformModuleTokenSpaceGuid.PcdFlashFvUefiBootOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvUefiBootSize -gPlatformModuleTokenSpaceGuid.PcdFlashFvUefiBootBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvUefiBootSize +gMinPlatformModuleTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformModuleTokenSpaceGuid.PcdFlashFvUefiBootSize +gMinPlatformModuleTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformModuleTokenSpaceGuid.PcdFlashFvUefiBootSize FV = FvUefiBoot -gPlatformModuleTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvPostMemorySize -gPlatformModuleTokenSpaceGuid.PcdFlashFvPostMemoryBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvPostMemorySize +gMinPlatformModuleTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformModuleTokenSpaceGuid.PcdFlashFvPostMemorySize +gMinPlatformModuleTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformModuleTokenSpaceGuid.PcdFlashFvPostMemorySize FV = FvPostMemory gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize @@ -161,18 +161,18 @@ gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFlashMicroc #Microcode FV = FvMicrocode -gPlatformModuleTokenSpaceGuid.PcdFlashFvFspSOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvFspSSize -gPlatformModuleTokenSpaceGuid.PcdFlashFvFspSBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvFspSSize +gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspSSize +gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspSSize # FSP_S Section FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_S.fd -gPlatformModuleTokenSpaceGuid.PcdFlashFvFspMTOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvFspMTSize -gPlatformModuleTokenSpaceGuid.PcdFlashFvFspMTBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvFspMTSize +gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspMTOffset|gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspMTSize +gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspMTBase|gMinPlatformModuleTokenSpaceGuid.PcdFlashFvFspMTSize # FSP_M & T Section FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_M_T.fd -gPlatformModuleTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvPreMemorySize -gPlatformModuleTokenSpaceGuid.PcdFlashFvPreMemoryBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvPreMemorySize +gMinPlatformModuleTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformModuleTokenSpaceGuid.PcdFlashFvPreMemorySize +gMinPlatformModuleTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformModuleTokenSpaceGuid.PcdFlashFvPreMemorySize FV = FvPreMemory ################################################################################ @@ -370,7 +370,7 @@ FvNameGuid = A0F04529-B715-44C6-BCA4-2DEBDD01EEEC !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf -!if gPlatformModuleTokenSpaceGuid.PcdBootToShellOnly == FALSE +!if gMinPlatformModuleTokenSpaceGuid.PcdBootToShellOnly == FALSE INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf INF $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf @@ -404,7 +404,7 @@ READ_LOCK_CAP = TRUE READ_LOCK_STATUS = TRUE FvNameGuid = 97F09B89-9E83-4DDC-A3D1-10C4AF539D1E -!if gPlatformModuleTokenSpaceGuid.PcdBootToShellOnly == FALSE +!if gMinPlatformModuleTokenSpaceGuid.PcdBootToShellOnly == FALSE $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxe.inf $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf @@ -498,7 +498,7 @@ FvNameGuid = 4199E560-54AE-45E5-91A4-F7BC3804E14A INF IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf -!if gPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE +!if gMinPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf !endif @@ -528,17 +528,17 @@ FvNameGuid = F753FE9A-EEFD-485B-840B-E032D538102C INF IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf -!if gPlatformModuleTokenSpaceGuid.PcdBootToShellOnly == FALSE +!if gMinPlatformModuleTokenSpaceGuid.PcdBootToShellOnly == FALSE INF $(PLATFORM_SI_PACKAGE)/Hsti/Dxe/HstiSiliconDxe.inf !endif -!if gPlatformModuleTokenSpaceGuid.PcdBootToShellOnly == FALSE +!if gMinPlatformModuleTokenSpaceGuid.PcdBootToShellOnly == FALSE INF $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf -!if gPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE +!if gMinPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf !endif diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgConfig.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgConfig.dsc index 3fd015bd6d..92842ca237 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgConfig.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgConfig.dsc @@ -21,35 +21,35 @@ # Stage 4 - boot to OS # Stage 5 - boot to OS with security boot enabled # - gPlatformModuleTokenSpaceGuid.PcdBootStage|4 + gMinPlatformModuleTokenSpaceGuid.PcdBootStage|4 - gPlatformModuleTokenSpaceGuid.PcdStopAfterDebugInit|FALSE - gPlatformModuleTokenSpaceGuid.PcdStopAfterMemInit|FALSE - gPlatformModuleTokenSpaceGuid.PcdBootToShellOnly|FALSE - gPlatformModuleTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE - gPlatformModuleTokenSpaceGuid.PcdTpm2Enable|FALSE - -!if gPlatformModuleTokenSpaceGuid.PcdBootStage >= 1 - gPlatformModuleTokenSpaceGuid.PcdStopAfterDebugInit|TRUE + gMinPlatformModuleTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformModuleTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformModuleTokenSpaceGuid.PcdBootToShellOnly|FALSE + gMinPlatformModuleTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE + gMinPlatformModuleTokenSpaceGuid.PcdTpm2Enable|FALSE + +!if gMinPlatformModuleTokenSpaceGuid.PcdBootStage >= 1 + gMinPlatformModuleTokenSpaceGuid.PcdStopAfterDebugInit|TRUE !endif -!if gPlatformModuleTokenSpaceGuid.PcdBootStage >= 2 - gPlatformModuleTokenSpaceGuid.PcdStopAfterDebugInit|FALSE - gPlatformModuleTokenSpaceGuid.PcdStopAfterMemInit|TRUE +!if gMinPlatformModuleTokenSpaceGuid.PcdBootStage >= 2 + gMinPlatformModuleTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformModuleTokenSpaceGuid.PcdStopAfterMemInit|TRUE !endif -!if gPlatformModuleTokenSpaceGuid.PcdBootStage >= 3 - gPlatformModuleTokenSpaceGuid.PcdStopAfterMemInit|FALSE - gPlatformModuleTokenSpaceGuid.PcdBootToShellOnly|TRUE +!if gMinPlatformModuleTokenSpaceGuid.PcdBootStage >= 3 + gMinPlatformModuleTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformModuleTokenSpaceGuid.PcdBootToShellOnly|TRUE !endif -!if gPlatformModuleTokenSpaceGuid.PcdBootStage >= 4 - gPlatformModuleTokenSpaceGuid.PcdBootToShellOnly|FALSE +!if gMinPlatformModuleTokenSpaceGuid.PcdBootStage >= 4 + gMinPlatformModuleTokenSpaceGuid.PcdBootToShellOnly|FALSE !endif -!if gPlatformModuleTokenSpaceGuid.PcdBootStage >= 5 - gPlatformModuleTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE - gPlatformModuleTokenSpaceGuid.PcdTpm2Enable|TRUE +!if gMinPlatformModuleTokenSpaceGuid.PcdBootStage >= 5 + gMinPlatformModuleTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE + gMinPlatformModuleTokenSpaceGuid.PcdTpm2Enable|TRUE !endif # @@ -132,5 +132,5 @@ gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE !endif - gPlatformModuleTokenSpaceGuid.PcdPerformanceEnable|FALSE + gMinPlatformModuleTokenSpaceGuid.PcdPerformanceEnable|FALSE diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc index 3921ff76c3..a96500ed0a 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc @@ -34,7 +34,7 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE [PcdsFixedAtBuild.common] -!if gPlatformModuleTokenSpaceGuid.PcdPerformanceEnable == TRUE +!if gMinPlatformModuleTokenSpaceGuid.PcdPerformanceEnable == TRUE gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140 !endif @@ -104,17 +104,17 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC !if $(TARGET) == RELEASE - gPlatformModuleTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402 + gMinPlatformModuleTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402 !else - gPlatformModuleTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B + gMinPlatformModuleTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B !endif - gPlatformModuleTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b + gMinPlatformModuleTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b !if $(TARGET) == RELEASE - gPlatformModuleTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x25 + gMinPlatformModuleTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x25 !else - gPlatformModuleTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x80 + gMinPlatformModuleTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x80 !endif gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0xFFE5F000 @@ -150,7 +150,7 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 # BIT2: Firmware setting this bit is an indication that it will not allow reconfiguration of system resources via non-architectural mechanisms. # BIT3-31: Reserved # - gPlatformModuleTokenSpaceGuid.PcdWsmtProtectionFlags|0x07 + gMinPlatformModuleTokenSpaceGuid.PcdWsmtProtectionFlags|0x07 # # See HstiFeatureBit.h for the definition @@ -161,7 +161,7 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 [PcdsFixedAtBuild.IA32] gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148 - gPlatformModuleTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000 + gMinPlatformModuleTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000 gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 [PcdsFixedAtBuild.X64] @@ -185,7 +185,7 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout" gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport" -!if gPlatformModuleTokenSpaceGuid.PcdPerformanceEnable == TRUE +!if gMinPlatformModuleTokenSpaceGuid.PcdPerformanceEnable == TRUE gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"Timeout" !endif diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/bld.bat b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/bld.bat index b02789f002..56ce0e1f93 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/bld.bat +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/bld.bat @@ -16,7 +16,7 @@ :: 1) /s = Redirects all output to a file called EDK2.log(Prep.log must be existed), which will be located at the root. :: 2) /f = Defines the passing in of a single override to a feature PCD that is used in the platform :: DSC file. If this parameter is used, it is to be followed immediately after by both the feature -:: pcd name and value. FeaturePcd is the full PCD name, like gPlatformModuleTokenSpaceGuid.PcdOptimizeCompilerEnable +:: pcd name and value. FeaturePcd is the full PCD name, like gMinPlatformModuleTokenSpaceGuid.PcdOptimizeCompilerEnable :: 3) /r = Useful for faster rebuilds when no changes have been made to .inf files. Passes -u to :: build.exe to skip the generation of makefiles. :: 4) rom = Build Bios.rom only and building SPIs will be skipped. -- cgit v1.2.3