From 721ef82289296deaa39dcf24a99080967553a200 Mon Sep 17 00:00:00 2001 From: Guo Mang Date: Wed, 3 Aug 2016 13:03:08 +0800 Subject: BraswellPlatformPkg: Restructure code in Silicon/IntelSiliconBasic Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang Reviewed-by: David Wei --- .../Common/Silicon/IntelSiliconBasic/CpuInit/Cpu.c | 7 +- .../IntelSiliconBasic/CpuInit/CpuDataStruct.h | 1 + .../Silicon/IntelSiliconBasic/CpuInit/CpuDxe.h | 3 +- .../Silicon/IntelSiliconBasic/CpuInit/CpuRegs.h | 1 + .../Silicon/IntelSiliconBasic/CpuInit/Exception.h | 1 + .../IntelSiliconBasic/CpuInit/Ia32/CpuAsm.asm | 138 ++--- .../IntelSiliconBasic/CpuInit/Ia32/CpuAsm.s | 142 +++--- .../IntelSiliconBasic/CpuInit/Ia32/Exception.c | 3 +- .../IntelSiliconBasic/CpuInit/Ia32/Htequ.inc | 2 +- .../IntelSiliconBasic/CpuInit/Ia32/InitializeFpu.s | 10 +- .../IntelSiliconBasic/CpuInit/Ia32/MPFuncs32.asm | 60 +-- .../IntelSiliconBasic/CpuInit/Ia32/MPFuncs32.s | 66 +-- .../IntelSiliconBasic/CpuInit/Ia32/MpCommon32.asm | 16 +- .../IntelSiliconBasic/CpuInit/Ia32/MpCommon32.s | 10 +- .../Silicon/IntelSiliconBasic/CpuInit/Ia32/MpCpu.c | 1 + .../IntelSiliconBasic/CpuInit/Ia32/MpProc.asm | 8 +- .../IntelSiliconBasic/CpuInit/Ia32/MpProc.s | 4 +- .../IntelSiliconBasic/CpuInit/Ia32/ProcessorDef.h | 5 +- .../IntelSiliconBasic/CpuInit/MemoryAttribute.c | 5 +- .../IntelSiliconBasic/CpuInit/MemoryAttribute.h | 5 +- .../Silicon/IntelSiliconBasic/CpuInit/Microcode.c | 3 +- .../Silicon/IntelSiliconBasic/CpuInit/MiscFuncs.c | 7 +- .../Silicon/IntelSiliconBasic/CpuInit/MiscFuncs.h | 1 + .../Silicon/IntelSiliconBasic/CpuInit/MpCommon.c | 5 +- .../Silicon/IntelSiliconBasic/CpuInit/MpCommon.h | 7 +- .../Silicon/IntelSiliconBasic/CpuInit/MpCpu.inf | 2 +- .../Silicon/IntelSiliconBasic/CpuInit/MpService.c | 7 +- .../Silicon/IntelSiliconBasic/CpuInit/MtrrSync.c | 3 +- .../IntelSiliconBasic/CpuInit/PlatformMpService.h | 17 +- .../Silicon/IntelSiliconBasic/CpuInit/x64/Cpu.asm | 16 +- .../IntelSiliconBasic/CpuInit/x64/CpuAsm.asm | 12 +- .../IntelSiliconBasic/CpuInit/x64/Exception.c | 2 +- .../CpuInit/x64/MemoryOperation.c | 25 +- .../Silicon/IntelSiliconBasic/CpuInit/x64/MpCpu.c | 1 + .../IntelSiliconBasic/CpuInit/x64/MpFuncs.asm | 64 +-- .../IntelSiliconBasic/CpuInit/x64/PlatformCpuLib.h | 1 + .../IntelSiliconBasic/CpuInit/x64/ProcessorDef.h | 5 +- .../IntelSiliconBasic/CpuInit/x64/VirtualMemory.h | 5 +- .../Include/Library/CpuConfigLib.h | 1 + .../Include/Library/SmmCpuPlatformHookLib.h | 1 + .../Include/Library/SocketLga775Lib.h | 1 + .../Include/Protocol/SmmCpuSync.h | 1 + .../Include/Protocol/SmmCpuSync2.h | 1 + .../IntelSiliconBasic/IntelSiliconBasic.dec | 206 ++++++++ .../Library/CpuConfigLib/CpuConfig.c | 1 + .../Library/CpuConfigLib/CpuConfig.h | 1 + .../Library/CpuConfigLib/CpuConfigLib.inf | 3 +- .../SmmCpuPlatformHookLibNull.c | 1 + .../SmmCpuPlatformHookLibNull.inf | 3 +- .../PciHostBridge/PciHostBridge.c | 3 +- .../PciHostBridge/PciHostBridge.h | 19 +- .../PciHostBridge/PciHostBridge.inf | 2 +- .../PciHostBridge/PciRootBridge.h | 9 +- .../PciHostBridge/PciRootBridgeIo.c | 27 +- .../PiSmmCommunication/PiSmmCommunicationPei.c | 1 + .../PiSmmCommunication/PiSmmCommunicationPrivate.h | 1 + .../PiSmmCommunication/PiSmmCommunicationSmm.c | 1 + .../PiSmmCpuDxeSmm/Ia32/MpFuncs.S | 2 +- .../PiSmmCpuDxeSmm/Ia32/MpFuncs.asm | 20 +- .../PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 6 +- .../PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 6 +- .../PiSmmCpuDxeSmm/Ia32/SmiException.S | 20 +- .../PiSmmCpuDxeSmm/Ia32/SmiException.asm | 2 +- .../PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c | 1 + .../PiSmmCpuDxeSmm/Ia32/SmmProfileArch.h | 1 + .../IntelSiliconBasic/PiSmmCpuDxeSmm/MpService.c | 1 + .../PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 1 + .../PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 1 + .../PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 3 +- .../IntelSiliconBasic/PiSmmCpuDxeSmm/SmmFeatures.h | 1 + .../IntelSiliconBasic/PiSmmCpuDxeSmm/SmmProfile.c | 1 + .../IntelSiliconBasic/PiSmmCpuDxeSmm/SmmProfile.h | 1 + .../PiSmmCpuDxeSmm/SmmProfileInternal.h | 1 + .../IntelSiliconBasic/PiSmmCpuDxeSmm/SyncTimer.c | 1 + .../PiSmmCpuDxeSmm/X64/MpFuncs.asm | 28 +- .../PiSmmCpuDxeSmm/X64/SmiEntry.asm | 6 +- .../PiSmmCpuDxeSmm/X64/SmiException.S | 20 +- .../PiSmmCpuDxeSmm/X64/SmiException.asm | 18 +- .../PiSmmCpuDxeSmm/X64/SmmInit.asm | 4 +- .../PiSmmCpuDxeSmm/X64/SmmProfileArch.c | 1 + .../PiSmmCpuDxeSmm/X64/SmmProfileArch.h | 1 + .../IntelSiliconBasic/SerialDxe/SerialDxe.inf | 53 ++ .../Silicon/IntelSiliconBasic/SerialDxe/SerialIo.c | 555 +++++++++++++++++++++ 83 files changed, 1288 insertions(+), 421 deletions(-) create mode 100644 BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/IntelSiliconBasic.dec create mode 100644 BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/SerialDxe/SerialDxe.inf create mode 100644 BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/SerialDxe/SerialIo.c diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Cpu.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Cpu.c index e8ef367545..71d138f7b2 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Cpu.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Cpu.c @@ -232,7 +232,7 @@ DisableInterrupt ( @param[out] State Pointer to the CPU's current interrupt state @retval EFI_SUCCESS If interrupts were disabled in the CPU. - @retval EFI_INVALID_PARAMETER State is NULL. + @retval EFI_INVALID_PARAMETER State is NULL. **/ EFI_STATUS @@ -629,7 +629,7 @@ Done: } /** - @todo Add structure description + @todo Add structure description **/ typedef struct { @@ -839,7 +839,7 @@ InitializeCpu ( /** Determine the processor core frequency - @retval Processor core frequency multiplied by 3 + @retval Processor core frequency multiplied by 3 **/ UINT16 @@ -997,3 +997,4 @@ ApCpuInitBeforeBoot ( ) { } + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/CpuDataStruct.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/CpuDataStruct.h index 5d61762969..4ad78dd033 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/CpuDataStruct.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/CpuDataStruct.h @@ -119,3 +119,4 @@ typedef struct { } EFI_CPU_VERSION; #endif + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/CpuDxe.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/CpuDxe.h index 9ead237ffe..f3a67032f5 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/CpuDxe.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/CpuDxe.h @@ -49,7 +49,7 @@ #include "CpuDataStruct.h" #define BSEL_CR_OVERCLOCK_CONTROL 0xCD -#define FUSE_BSEL_MASK 0x07 +#define FUSE_BSEL_MASK 0x07 #define INTERRUPT_VECTOR_NUMBER 256 #define INTERRUPT_GATE_ATTRIBUTE 0x8e00 @@ -238,3 +238,4 @@ PCIConfigWA ( ) #endif + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/CpuRegs.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/CpuRegs.h index 5dd1d959e0..e2d2abf4df 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/CpuRegs.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/CpuRegs.h @@ -408,3 +408,4 @@ typedef enum { #pragma pack() #endif + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Exception.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Exception.h index 695670458a..29c04a31bd 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Exception.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Exception.h @@ -69,3 +69,4 @@ InitializeException ( IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol ); #endif + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/CpuAsm.asm b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/CpuAsm.asm index dfc81eeed8..c47d0042f2 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/CpuAsm.asm +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/CpuAsm.asm @@ -14,7 +14,7 @@ page ,132 title CPU ARCHITECTURAL DXE PROTOCOL ASSEMBLY HOOKS .686p -.model flat +.model flat .data ExternalVectorTablePtr DD ? ; Table of call backs @@ -40,47 +40,47 @@ UINTN TYPEDEF UINT32 ;---------------------------------------; ; _InitializeIdt ; ;----------------------------------------------------------------------------; -; +; ; Protocol prototype ; InitializeIdt ( ; IN EFI_CPU_INTERRUPT_HANDLER TableStart, ; IN UINTN *IdtTablePtr, ; IN UINT16 IdtLimit ; ) -; +; ; Routine Description: -; +; ; Creates an IDT table starting at IdtTablPtr. It has IdtLimit/8 entries. ; Table is initialized to intxx where xx is from 00 to number of entries or ; 100h, whichever is smaller. After table has been initialized the LIDT ; instruction is invoked. -; -; TableStart is the pointer to the callback table and is not used by +; +; TableStart is the pointer to the callback table and is not used by ; InitializedIdt but by commonEntry. CommonEntry handles all interrupts, ; does the context save and calls the callback entry, if non-NULL. ; It is the responsibility of the callback routine to do hardware EOIs. -; +; ; Arguments: -; +; ; TableStart - Pointer to interrupt callback table ; ; IdtTablePtr - Pointer to IDT table ; ; IdtLimit - IDT Table limit = number of interrupt entries * 8 -; -; Returns: -; +; +; Returns: +; ; Nothing ; -; +; ; Input: [ebp][0] = Original ebp ; [ebp][4] = Return address ; [ebp][8] = TableStart ; [ebp][0c] = *IdtTablePtr ; [ebp][10] = IdtLimit -; +; ; Output: Nothing -; +; ; Destroys: Nothing ;-----------------------------------------------------------------------------; @@ -98,7 +98,7 @@ _InitializeIdt proc near public mov eax, [ebp+0ch] ; Get Start of IDT mov Idtr1, eax - + mov edi, OFFSET Idtr ; Load IDT register lidt FWORD PTR es:[edi] @@ -108,45 +108,45 @@ _InitializeIdt proc near public _InitializeIdt endp ;----------------------------------------------------------------------------; -; +; ; Protocol prototype ; None -; +; ; Routine Description: -; +; ; These routines handle the individual interrupts. These routines always ; gain control on any interrupt or exception. They save EAX and place -; the interrupt number in EAX. CommonEntry is then jumped to. +; the interrupt number in EAX. CommonEntry is then jumped to. ; instruction is invoked. -; -; CommonEntry handles all interrupts,does the context save and calls the -; callback entry, if non-NULL. It is the responsibility of the callback +; +; CommonEntry handles all interrupts,does the context save and calls the +; callback entry, if non-NULL. It is the responsibility of the callback ; routine to do hardware EOIs. Callbacks are entered into the table ; located at TableStart. Entries are modified by the InstallInterruptHandler ; and UninstallInterruptHandler protocols. -; +; ; Arguments to CommonEntry: -; +; ; EAX - Interrupt or exception number ; ; TableStart - Pointer to interrupt callback table -; -; Returns: -; +; +; Returns: +; ; Nothing ; -; +; ; Output: Nothing -; +; ; Destroys: Nothing ;-----------------------------------------------------------------------------; TemplateStart: push eax - - ;mov eax, 0nnh (nn stands for vector number, which will be fixed at runtime + + ;mov eax, 0nnh (nn stands for vector number, which will be fixed at runtime DB 0b8h -VectorNumber: +VectorNumber: DD 00h jmp dword ptr [CommonInterruptEntry]; @@ -193,7 +193,7 @@ NoErrorCode: ; push [esp] mov dword ptr [esp + 4], 0 -@@: +@@: push ebp mov ebp, esp @@ -385,30 +385,30 @@ nonNullValue: ;---------------------------------------; ; _GetTemplateAddressMap ; ;----------------------------------------------------------------------------; -; +; ; Protocol prototype ; GetTemplateAddressMap ( ; INTERRUPT_HANDLER_TEMPLATE_MAP *AddressMap ; ); -; +; ; Routine Description: -; +; ; Return address map of interrupt handler template so that C code can generate ; interrupt handlers, and dynamically do address fix. -; +; ; Arguments: -; -; -; Returns: -; +; +; +; Returns: +; ; Nothing ; -; +; ; Input: [ebp][0] = Original ebp ; [ebp][4] = Return address -; +; ; Output: Nothing -; +; ; Destroys: Nothing ;-----------------------------------------------------------------------------; _GetTemplateAddressMap proc near public @@ -419,8 +419,8 @@ _GetTemplateAddressMap proc near public mov ebx, dword ptr [ebp+08h] mov dword ptr [ebx], TemplateStart mov dword ptr [ebx+4h], TemplateEnd - TemplateStart - - ; if code in Template is updated, the value fills into the 3rd parameter + + ; if code in Template is updated, the value fills into the 3rd parameter ; also needs update mov dword ptr [ebx+8h], VectorNumber - TemplateStart @@ -434,31 +434,31 @@ _GetTemplateAddressMap endp ;---------------------------------------; ; _InitializeSelectors ; ;----------------------------------------------------------------------------; -; +; ; Protocol prototype ; InitializeSelectors ( ; ) -; +; ; Routine Description: -; +; ; Creates an new GDT in RAM. The problem is that our former selectors -; were ROM based and the EFI OS Loader does not manipulate the machine state +; were ROM based and the EFI OS Loader does not manipulate the machine state ; to change them (as it would for a 16-bit PC/AT startup code that had to ; go from Real Mode to flat mode). -; +; ; Arguments: -; -; -; Returns: -; +; +; +; Returns: +; ; Nothing ; -; +; ; Input: [ebp][0] = Original ebp ; [ebp][4] = Return address -; +; ; Output: Nothing -; +; ; Destroys: Nothing ;-----------------------------------------------------------------------------; @@ -471,7 +471,7 @@ _InitializeSelectors proc near public pushad mov edi, OFFSET Gdtr ; Load GDT register - mov ax,cs ; Get the selector data from our code image + mov ax,cs ; Get the selector data from our code image mov es,ax lgdt FWORD PTR es:[edi] ; and update the GDTR @@ -485,13 +485,13 @@ SelectorRld:: mov es, ax mov fs, ax mov gs, ax - mov ss, ax + mov ss, ax popad pop ebp ret _InitializeSelectors endp - + ;------------------------------------------------------------------------------ ; VOID ; CpuEnableInterrupt ( @@ -513,7 +513,7 @@ CpuEnableInterrupt ENDP CpuDisableInterrupt PROC C PUBLIC cli ret -CpuDisableInterrupt ENDP +CpuDisableInterrupt ENDP ;------------------------------------------------------------------------------ ; VOID @@ -535,7 +535,7 @@ CpuInitFloatPointUnit ENDP GetCodeSegment PROC C PUBLIC mov ax,cs ret -GetCodeSegment ENDP +GetCodeSegment ENDP ;------------------------------------------------------------------------------ @@ -569,7 +569,7 @@ EfiInvd ENDP ;------------------------------------------------------------------------------ _GetIdt proc near public push ebp ; C prolog - + mov ebp, esp mov eax, [ebp+8] sidt FWORD PTR [eax] @@ -581,19 +581,19 @@ _GetIdt ENDP GetCoreNumber PROC C PUBLIC push ebx - + mov eax, 4 mov ecx, 0 cpuid - + shr eax, 26 and eax, 3fh inc al - + pop ebx - + ret - + GetCoreNumber ENDP diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/CpuAsm.s b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/CpuAsm.s index 9b62ca1688..bac06d08f8 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/CpuAsm.s +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/CpuAsm.s @@ -39,7 +39,7 @@ Idtr1: .space 4 .equ IdtrProfile , LockLocation + 0x16 .equ BufferStart , LockLocation + 0x1C .equ Cr3Location , LockLocation + 0x20 -.equ InitFlag , LockLocation + 0x24 +.equ InitFlag , LockLocation + 0x24 .equ WakeUpApManner , LockLocation + 0x28 .equ BistBuffer , LockLocation + 0x2C @@ -53,47 +53,47 @@ Idtr1: .space 4 #---------------------------------------# # _InitializeIdt # #----------------------------------------------------------------------------# -# +# # Protocol prototype # InitializeIdt ( # IN EFI_CPU_INTERRUPT_HANDLER TableStart, # IN UINTN *IdtTablePtr, # IN UINT16 IdtLimit # ) -# +# # Routine Description: -# +# # Creates an IDT table starting at IdtTablPtr. It has IdtLimit/8 entries. # Table is initialized to intxx where xx is from 00 to number of entries or # 100h, whichever is smaller. After table has been initialized the LIDT # instruction is invoked. -# -# TableStart is the pointer to the callback table and is not used by +# +# TableStart is the pointer to the callback table and is not used by # InitializedIdt but by commonEntry. CommonEntry handles all interrupts, # does the context save and calls the callback entry, if non-NULL. # It is the responsibility of the callback routine to do hardware EOIs. -# +# # Arguments: -# +# # TableStart - Pointer to interrupt callback table # # IdtTablePtr - Pointer to IDT table # # IdtLimit - IDT Table limit = number of interrupt entries * 8 -# -# Returns: -# +# +# Returns: +# # Nothing # -# +# # Input: [ebp][0] = Original ebp # [ebp][4] = Return address # [ebp][8] = TableStart # [ebp][0c] = *IdtTablePtr # [ebp][10] = IdtLimit -# +# # Output: Nothing -# +# # Destroys: Nothing #-----------------------------------------------------------------------------# @@ -121,51 +121,51 @@ ASM_PFX(InitializeIdt): ret #----------------------------------------------------------------------------# -# +# # Protocol prototype # None -# +# # Routine Description: -# +# # These routines handle the individual interrupts. These routines always # gain control on any interrupt or exception. They save EAX and place -# the interrupt number in EAX. CommonEntry is then jumped to. +# the interrupt number in EAX. CommonEntry is then jumped to. # instruction is invoked. -# -# CommonEntry handles all interrupts,does the context save and calls the -# callback entry, if non-NULL. It is the responsibility of the callback +# +# CommonEntry handles all interrupts,does the context save and calls the +# callback entry, if non-NULL. It is the responsibility of the callback # routine to do hardware EOIs. Callbacks are entered into the table # located at TableStart. Entries are modified by the InstallInterruptHandler # and UninstallInterruptHandler protocols. -# +# # Arguments to CommonEntry: -# +# # EAX - Interrupt or exception number # # TableStart - Pointer to interrupt callback table -# -# Returns: -# +# +# Returns: +# # Nothing # -# +# # Output: Nothing -# +# # Destroys: Nothing #-----------------------------------------------------------------------------# -TemplateStart: +TemplateStart: pushl %eax - #mov eax, 0nnh (nn stands for vector number, which will be fixed at runtime + #mov eax, 0nnh (nn stands for vector number, which will be fixed at runtime .byte 0xb8 -VectorNumber: +VectorNumber: .long 0x0 jmp *CommonInterruptEntry -TemplateEnd: +TemplateEnd: -CommonEntry: +CommonEntry: #---------------------------------------# # _CommonEntry # @@ -199,7 +199,7 @@ CommonEntry: btl %eax, %cs:ASM_PFX(mErrorCodeFlag) jc L1 -NoErrorCode: +NoErrorCode: # # Push a dummy error code on the stack # to maintain coherent stack map @@ -324,7 +324,7 @@ L1: call *%eax addl $8, %esp -nonNullValue: +nonNullValue: cli ## UINT32 ExceptionData# @@ -402,30 +402,30 @@ nonNullValue: #---------------------------------------# # _GetTemplateAddressMap # #----------------------------------------------------------------------------# -# +# # Protocol prototype # GetTemplateAddressMap ( # INTERRUPT_HANDLER_TEMPLATE_MAP *AddressMap # )# -# +# # Routine Description: -# +# # Return address map of interrupt handler template so that C code can generate # interrupt handlers, and dynamically do address fix. -# +# # Arguments: -# -# -# Returns: -# +# +# +# Returns: +# # Nothing # -# +# # Input: [ebp][0] = Original ebp # [ebp][4] = Return address -# +# # Output: Nothing -# +# # Destroys: Nothing #-----------------------------------------------------------------------------# ASM_GLOBAL ASM_PFX(GetTemplateAddressMap) @@ -438,7 +438,7 @@ ASM_PFX(GetTemplateAddressMap): movl $TemplateStart, (%ebx) movl $(TemplateEnd - TemplateStart), 4(%ebx) - # Note: if code in Template is updated, the value fills into the 3rd parameter + # Note: if code in Template is updated, the value fills into the 3rd parameter # also needs update movl $(VectorNumber - TemplateStart), 8(%ebx) @@ -451,31 +451,31 @@ ASM_PFX(GetTemplateAddressMap): #---------------------------------------# # _InitializeSelectors # #----------------------------------------------------------------------------# -# +# # Protocol prototype # InitializeSelectors ( # ) -# +# # Routine Description: -# +# # Creates an new GDT in RAM. The problem is that our former selectors -# were ROM based and the EFI OS Loader does not manipulate the machine state +# were ROM based and the EFI OS Loader does not manipulate the machine state # to change them (as it would for a 16-bit PC/AT startup code that had to # go from Real Mode to flat mode). -# +# # Arguments: -# -# -# Returns: -# +# +# +# Returns: +# # Nothing # -# +# # Input: [ebp][0] = Original ebp # [ebp][4] = Return address -# +# # Output: Nothing -# +# # Destroys: Nothing #-----------------------------------------------------------------------------# @@ -489,7 +489,7 @@ ASM_PFX(InitializeSelectors): pushal movl $Gdtr, %edi - movw %cs,%ax # Get the selector data from our code image + movw %cs,%ax # Get the selector data from our code image .byte 0x66 movw %ax,%es lgdt %es:(%edi) @@ -538,7 +538,7 @@ ASM_GLOBAL ASM_PFX(CpuDisableInterrupt) ASM_PFX(CpuDisableInterrupt): cli ret -#CpuDisableInterrupt ENDP +#CpuDisableInterrupt ENDP #------------------------------------------------------------------------------ # VOID @@ -562,7 +562,7 @@ ASM_GLOBAL ASM_PFX(GetCodeSegment) ASM_PFX(GetCodeSegment): movw %cs, %ax ret -#GetCodeSegment ENDP +#GetCodeSegment ENDP #------------------------------------------------------------------------------ @@ -598,7 +598,7 @@ ASM_PFX(EfiInvd): ASM_GLOBAL ASM_PFX(GetIdt) ASM_PFX(GetIdt): push %ebp # C prolog - + movl %esp, %ebp movl 8(%ebp), %eax sidt (%eax) @@ -621,7 +621,7 @@ ASM_PFX(C1eExceptionHandler): cli pushal - # Verify if GPE was caused by C1e write. + # Verify if GPE was caused by C1e write. # If not, pass control to real exception handler. cmp $0, ASM_PFX(mWroteMsr) je notourexception @@ -654,19 +654,19 @@ ASM_GLOBAL ASM_PFX(GetCoreNumber) ASM_PFX(GetCoreNumber): pushl %ebx - + movl $4, %eax movl $0, %ecx cpuid - + shrl $26, %eax andl $0x3f, %eax incb %al - + popl %ebx - + ret - + #GetCoreNumber ENDP #-----------------------------------------------------------------------------# @@ -684,7 +684,7 @@ Gdtr: .word GDT_END - GDT_BASE - 1 .p2align 4 -GDT_BASE: +GDT_BASE: # null descriptor # .equ NULL_SEL, $-GDT_BASE # Selector [0] .word 0 # limit 15:0 @@ -757,5 +757,5 @@ GDT_BASE: .byte 0 # page-granular, 32-bit .byte 0 -GDT_END: +GDT_END: diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/Exception.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/Exception.c index 89734ddfe2..cfad3e6044 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/Exception.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/Exception.c @@ -24,7 +24,7 @@ VOID IN VOID *SystemContext ); /** - @todo No description + @todo No description **/ typedef struct { @@ -335,3 +335,4 @@ InitializeException ( return Status; } + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/Htequ.inc b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/Htequ.inc index 5554cefd42..95f00adaa8 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/Htequ.inc +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/Htequ.inc @@ -29,7 +29,7 @@ GdtrProfile equ LockLocation + 10h IdtrProfile equ LockLocation + 16h BufferStart equ LockLocation + 1Ch Cr3Location equ LockLocation + 20h -InitFlag equ LockLocation + 24h +InitFlag equ LockLocation + 24h WakeUpApManner equ LockLocation + 28h BistBuffer equ LockLocation + 2Ch PAUSE32 MACRO diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/InitializeFpu.s b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/InitializeFpu.s index 782eb00bb6..924815114c 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/InitializeFpu.s +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/InitializeFpu.s @@ -12,7 +12,7 @@ ## # -# Float control word initial value: +# Float control word initial value: # all exceptions masked, double-precision, round-to-nearest # ASM_PFX(mFpuControlWord): .word 0x027F @@ -40,7 +40,7 @@ ASM_PFX(InitializeFloatingPointUnits): # finit fldcw ASM_PFX(mFpuControlWord) - + # # Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test # whether the processor supports SSE instruction. @@ -49,14 +49,14 @@ ASM_PFX(InitializeFloatingPointUnits): cpuid btl $25, %edx jnc Done - + # # Set OSFXSR bit 9 in CR4 # - movl %cr4, %eax + movl %cr4, %eax or $0x200, %eax movl %eax, %cr4 - + # # The processor should support SSE instruction and we can use # ldmxcsr instruction diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MPFuncs32.asm b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MPFuncs32.asm index 1350addb7d..3f15ff3749 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MPFuncs32.asm +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MPFuncs32.asm @@ -14,8 +14,8 @@ ;; .686p -.model flat -.code +.model flat +.code include Htequ.inc ;------------------------------------------------------------------------------------- @@ -51,7 +51,7 @@ RendezvousFunnelProcStart:: db 8ch, 0c8h ; mov ax, cs db 8eh, 0d8h ; mov ds, ax db 8eh, 0c0h ; mov es, ax - db 8eh, 0d0h ; mov ss, ax + db 8eh, 0d0h ; mov ss, ax db 33h, 0c0h ; xor ax, ax db 8eh, 0e0h ; mov fs, ax db 8eh, 0e8h ; mov gs, ax @@ -76,18 +76,18 @@ RendezvousFunnelProcStart:: ; db 0B0h, 08h ; mov al, 8 db 0F6h, 0E3h ; mul bl - + db 0BEh, 2Ch, 0Ch ; mov si, BistBuffer db 03h, 0F0h ; add si, ax - + db 66h, 0C7h, 04h dd 00000001h ; mov dword ptr [si], 1 ; Set Valid Flag - db 66h, 89h, 6Ch, 04h ; mov dword ptr [si + 4], ebp ; Store BIST value - + db 66h, 89h, 6Ch, 04h ; mov dword ptr [si + 4], ebp ; Store BIST value + cli hlt jmp $-2 - + ; Switch to flat mode. flat32Start:: @@ -99,12 +99,12 @@ flat32Start:: db 0BEh, 10h, 0Ch ; mov si, GdtrProfile db 66h ; db 66h db 2Eh,0Fh, 01h, 14h ; lgdt fword ptr cs:[si] - + db 0BEh, 16h, 0Ch ; mov si, IdtrProfile db 66h ; db 66h db 2Eh,0Fh, 01h, 1Ch ; lidt fword ptr cs:[si] - - + + db 33h, 0C0h ; xor ax, ax db 8Eh, 0D8h ; mov ds, ax db 0Fh, 20h, 0C0h ; mov eax, cr0 ; Get control register 0 @@ -139,23 +139,23 @@ ProgramStaticStack:: mov edi, esi add edi, BistBuffer mov ecx, dword ptr [edi + 8 * ebx] ; EBX = CpuNumber - + mov edi, esi add edi, StackSize mov eax, dword ptr [edi] - inc ecx + inc ecx mul ecx ; EAX = StackSize * (CpuNumber + 1) - + mov edi, esi add edi, StackStart mov edx, dword ptr [edi] add eax, edx ; EAX = StackStart + StackSize * (CpuNumber + 1) - + mov esp, eax sub esp, MonitorFilterSize ; Reserved Monitor data space or ebx, StartupApSignal ; ebx = #Cpu run signature jmp ProgramLocalApic - + ProgramDynamicStack:: mov edi, esi @@ -215,7 +215,7 @@ EnableXmm:: mov eax, cr4 or eax, 600h mov cr4, eax - + @@: ; ; Call C Function @@ -290,7 +290,7 @@ HltApLoop:: cli hlt jmp HltApLoop - + RendezvousFunnelProc ENDP RendezvousFunnelProcEnd:: ;------------------------------------------------------------------------------------- @@ -300,19 +300,19 @@ AsmGetAddressMap PROC near C PUBLIC pushad mov ebp,esp - + mov ebx, dword ptr [ebp+24h] mov dword ptr [ebx], RendezvousFunnelProcStart mov dword ptr [ebx+4h], PMODE_ENTRY - RendezvousFunnelProcStart mov dword ptr [ebx+8h], FLAT32_JUMP - RendezvousFunnelProcStart mov dword ptr [ebx+0ch], RendezvousFunnelProcEnd - RendezvousFunnelProcStart - + popad ret AsmGetAddressMap ENDP ;------------------------------------------------------------------------------------- -;AsmExchangeRole procedure follows. This procedure executed by current BSP, that is +;AsmExchangeRole procedure follows. This procedure executed by current BSP, that is ;about to become an AP. It switches it'stack with the current AP. ;AsmExchangeRole (IN CPU_EXCHANGE_INFO *MyInfo, IN CPU_EXCHANGE_INFO *OthersInfo); ;------------------------------------------------------------------------------------- @@ -336,7 +336,7 @@ AsmExchangeRole PROC near C PUBLIC pushfd sgdt fword ptr [esi+8] sidt fword ptr [esi+14] - + ; Store the its StackPointer mov dword ptr [esi+4],esp @@ -349,13 +349,13 @@ TryLock1: jz LockObtained1 PAUSE32 jmp TryLock1 - + LockObtained1: mov byte ptr [esi+1], CPU_SWITCH_STATE_STORED db 0f0h ; opcode for lock instruction xchg al, byte ptr [esi] -WaitForOtherStored:: +WaitForOtherStored:: ; wait until the other CPU finish storing its state mov al, NotVacantFlag TryLock2: @@ -365,24 +365,24 @@ TryLock2: jz LockObtained2 PAUSE32 jmp TryLock2 - + LockObtained2: mov bl, byte ptr [edi+1] db 0f0h ; opcode for lock instruction xchg al, byte ptr [edi] cmp bl, CPU_SWITCH_STATE_STORED jb WaitForOtherStored - + ; Since another CPU already stored its state, load them ; load GDTR value lgdt fword ptr [edi+8] - + ; load IDTR value lidt fword ptr [edi+14] ; load its future StackPointer mov esp, dword ptr [edi+4] - + ; update its switch state to LOADED mov al, NotVacantFlag TryLock3: @@ -392,7 +392,7 @@ TryLock3: jz LockObtained3 PAUSE32 jmp TryLock3 - + LockObtained3: mov byte ptr [esi+1], CPU_SWITCH_STATE_LOADED db 0f0h ; opcode for lock instruction @@ -409,7 +409,7 @@ TryLock4: jz LockObtained4 PAUSE32 jmp TryLock4 - + LockObtained4: mov bl, byte ptr [edi+1] db 0f0h ; opcode for lock instruction diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MPFuncs32.s b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MPFuncs32.s index fd44beae0b..01c5e22164 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MPFuncs32.s +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MPFuncs32.s @@ -32,7 +32,7 @@ .equ IdtrProfile , LockLocation + 0x16 .equ BufferStart , LockLocation + 0x1C .equ Cr3Location , LockLocation + 0x20 -.equ InitFlag , LockLocation + 0x24 +.equ InitFlag , LockLocation + 0x24 .equ WakeUpApManner , LockLocation + 0x28 .equ BistBuffer , LockLocation + 0x2C @@ -50,7 +50,7 @@ .long \Offset # 32-bit offset .word \Selector # 16-bit selector .endm - + .macro FCALL32 Selector, Offset .byte 0x09A .long \Offset # 32-bit offset @@ -102,18 +102,18 @@ RendezvousFunnelProcStart: # .byte 0xB0, 0x08 # mov al, 8 .byte 0xF6, 0xE3 # mul bl - + .byte 0xBE, 0x2C, 0x0C # mov si, BistBuffer .byte 0x03, 0xF0 # add si, ax .byte 0x66, 0xC7, 0x04 .byte 0x00000001 # mov dword ptr [si], 1 # Set Valid Flag - .byte 0x66, 0x89, 0x6C, 0x04 # mov dword ptr [si + 4], ebp # Store BIST value - + .byte 0x66, 0x89, 0x6C, 0x04 # mov dword ptr [si + 4], ebp # Store BIST value + cli hlt jmp .-2 - + # Switch to flat mode. flat32Start: @@ -125,12 +125,12 @@ flat32Start: .byte 0xBE, 0x10, 0x0C # mov si, GdtrProfile .byte 0x66 # db 66h .byte 0x2E, 0x0F, 0x01, 0x14 # lgdt fword ptr cs:[si] - + .byte 0xBE, 0x16, 0x0C # mov si, IdtrProfile .byte 0x66 # db 66h .byte 0x2E, 0x0F, 0x01, 0x1C # lidt fword ptr cs:[si] - - + + .byte 0x33, 0xC0 # xor ax, ax .byte 0x8E, 0xD8 # mov ds, ax .byte 0x0F, 0x20, 0xC0 # mov eax, cr0 # Get control register 0 @@ -156,7 +156,7 @@ PMODE_ENTRY: # protected mode entry point movl %esi,%edi addl $InitFlag, %edi - cmpl $2, (%edi) # Check whether in S3 boot path + cmpl $2, (%edi) # Check whether in S3 boot path jz ProgramDynamicStack ProgramStaticStack: @@ -165,23 +165,23 @@ ProgramStaticStack: movl %esi, %edi addl $BistBuffer, %edi movl (%edi, %ebx, 8), %ecx # EBX = CpuNumber - + movl %esi, %edi addl $StackSize, %edi movl (%edi), %eax - incl %ecx + incl %ecx mull %ecx # EAX = StackSize * (CpuNumber + 1) - + movl %esi, %edi addl $StackStart, %edi movl (%edi), %edx addl %edx, %eax # EAX = StackStart + StackSize * (CpuNumber + 1) - + movl %eax, %esp subl $MonitorFilterSize, %esp # Reserved Monitor data space orl $StartupApSignal, %ebx # EBX = #Cpu run signature jmp ProgramLocalApic - + ProgramDynamicStack: movl %esi, %edi @@ -219,7 +219,7 @@ ProgramLocalApic: movl (%edi), %eax andl $0x0FFFE00FF, %eax orl $0x700, %eax - movl %eax, (%edi) + movl %eax, (%edi) movl $0x0FEE00360, %edi movl (%edi), %eax @@ -236,17 +236,17 @@ EnableXmm: # movl %cr0, %eax orl $2, %eax - movl %eax, %cr0 + movl %eax, %cr0 movl %cr4, %eax orl $0x600, %eax movl %eax, %cr4 - + L1: # # Call C Function # movl %esi, %edi - addl $RendezvousProc, %edi + addl $RendezvousProc, %edi addl $WakeUpApManner, %esi # esi = WakeUpApManner Address Location WakeUpThisAp: @@ -315,7 +315,7 @@ HltApLoop: cli hlt jmp HltApLoop - + #RendezvousFunnelProc ENDP RendezvousFunnelProcEnd: @@ -326,19 +326,19 @@ ASM_GLOBAL ASM_PFX(AsmGetAddressMap) ASM_PFX(AsmGetAddressMap): pushal movl %esp, %ebp - + movl 0x24(%ebp), %ebx movl $RendezvousFunnelProcStart, (%ebx) - movl $(PMODE_ENTRY - RendezvousFunnelProcStart), 0x4(%ebx) + movl $(PMODE_ENTRY - RendezvousFunnelProcStart), 0x4(%ebx) movl $(FLAT32_JUMP - RendezvousFunnelProcStart), 0x8(%ebx) movl $(RendezvousFunnelProcEnd - RendezvousFunnelProcStart), 0xc(%ebx) - + popal ret #AsmGetAddressMap ENDP #------------------------------------------------------------------------------------- -#AsmExchangeRole procedure follows. This procedure executed by current BSP, that is +#AsmExchangeRole procedure follows. This procedure executed by current BSP, that is #about to become an AP. It switches it'stack with the current AP. #AsmExchangeRole (IN CPU_EXCHANGE_INFO *MyInfo, IN CPU_EXCHANGE_INFO *OthersInfo)# #------------------------------------------------------------------------------------- @@ -363,7 +363,7 @@ ASM_PFX(AsmExchangeRole): pushfl sgdt 8(%esi) sidt 14(%esi) - + # Store the its StackPointer movl %esp, 4(%esi) @@ -375,11 +375,11 @@ TryLock1: jz LockObtained1 PAUSE32 jmp TryLock1 - + LockObtained1: movb $CPU_SWITCH_STATE_STORED, 1(%esi) lock xchgb (%esi), %al -WaitForOtherStored: +WaitForOtherStored: # wait until the other CPU finish storing its state movb $NotVacantFlag, %al TryLock2: @@ -388,23 +388,23 @@ TryLock2: jz LockObtained2 PAUSE32 jmp TryLock2 - + LockObtained2: movb 1(%edi), %bl lock xchgb (%edi), %al cmpb $CPU_SWITCH_STATE_STORED, %bl jb WaitForOtherStored - + # Since another CPU already stored its state, load them # load GDTR value lgdt 8(%edi) - + # load IDTR value lidt 14(%edi) # load its future StackPointer movl 4(%edi), %esp - + # update its switch state to LOADED movb $NotVacantFlag, %al TryLock3: @@ -413,7 +413,7 @@ TryLock3: jz LockObtained3 PAUSE32 jmp TryLock3 - + LockObtained3: movb $CPU_SWITCH_STATE_LOADED, 1(%esi) lock xchgb (%esi), %al @@ -428,7 +428,7 @@ TryLock4: jz LockObtained4 PAUSE32 jmp TryLock4 - + LockObtained4: movb 1(%edi), %bl lock xchgb (%edi), %al diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpCommon32.asm b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpCommon32.asm index 25434ad41f..1e422f34d0 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpCommon32.asm +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpCommon32.asm @@ -14,14 +14,14 @@ ;; .686p -.model flat +.model flat .data .stack .code .MMX .XMM - include Htequ.inc + include Htequ.inc PAUSE32 MACRO DB 0F3h DB 090h @@ -44,7 +44,7 @@ TryGetLock: jz LockObtained PAUSE32 - jmp TryGetLock + jmp TryGetLock LockObtained: popad @@ -52,7 +52,7 @@ LockObtained: AsmAcquireMPLock ENDP ;------------------------------------------------------------------------------- -; AsmReleaseMPLock (&Lock); +; AsmReleaseMPLock (&Lock); ;------------------------------------------------------------------------------------- AsmReleaseMPLock PROC near C PUBLIC @@ -63,13 +63,13 @@ AsmReleaseMPLock PROC near C PUBLIC mov ebx, dword ptr [ebp+24h] db 0f0h ; opcode for lock instruction xchg al, byte ptr [ebx] - + popad ret AsmReleaseMPLock ENDP ;------------------------------------------------------------------------------- -; AsmGetGdtrIdtr (&Gdt, &Idt); +; AsmGetGdtrIdtr (&Gdt, &Idt); ;------------------------------------------------------------------------------------- AsmGetGdtrIdtr PROC near C PUBLIC @@ -85,7 +85,7 @@ AsmGetGdtrIdtr PROC near C PUBLIC lea esi, IdtDesc mov edi, dword ptr [ebp+28h] mov dword ptr [edi], esi - + popad ret AsmGetGdtrIdtr ENDP @@ -100,4 +100,4 @@ IdtDesc:: ; IDT descriptor DW 0h ; IDT base and limit will be DW 0h ; filled using sidt -END +END \ No newline at end of file diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpCommon32.s b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpCommon32.s index dc110da96a..49877954d3 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpCommon32.s +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpCommon32.s @@ -32,7 +32,7 @@ .equ IdtrProfile , LockLocation + 0x16 .equ BufferStart , LockLocation + 0x1C .equ Cr3Location , LockLocation + 0x20 -.equ InitFlag , LockLocation + 0x24 +.equ InitFlag , LockLocation + 0x24 .equ WakeUpApManner , LockLocation + 0x28 .equ BistBuffer , LockLocation + 0x2C @@ -59,7 +59,7 @@ TryGetLock: PAUSE32 - jmp TryGetLock + jmp TryGetLock LockObtained: popal @@ -83,7 +83,7 @@ ASM_PFX(AsmReleaseMPLock): #AsmReleaseMPLock ENDP #------------------------------------------------------------------------------- -# AsmGetGdtrIdtr (&Gdt, &Idt)# +# AsmGetGdtrIdtr (&Gdt, &Idt)# #------------------------------------------------------------------------------------- ASM_GLOBAL ASM_PFX(AsmGetGdtrIdtr) ASM_PFX(AsmGetGdtrIdtr): @@ -98,7 +98,7 @@ ASM_PFX(AsmGetGdtrIdtr): leal IdtDesc, %esi movl 0x28(%ebp), %edi movl %esi, (%edi) - + popal ret #AsmGetGdtrIdtr ENDP @@ -109,6 +109,6 @@ GdtDesc: # GDT descriptor .word 0x0 # filled using sgdt IdtDesc: # IDT descriptor - .word 0x0 # IDT limit + .word 0x0 # IDT limit .word 0x0 # IDT base and limit will be .word 0x0 # filled using sidt diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpCpu.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpCpu.c index 133e10c57b..b6e3ed8f8e 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpCpu.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpCpu.c @@ -88,3 +88,4 @@ InitializeMpSupport ( return EFI_SUCCESS; } + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpProc.asm b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpProc.asm index e07056d304..e9d6128461 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpProc.asm +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpProc.asm @@ -15,7 +15,7 @@ page ,132 title MP ASSEMBLY HOOKS .686p -.model flat +.model flat .data .stack .code @@ -45,13 +45,13 @@ _MpMtrrSynchUpEntry PROC NEAR PUBLIC ; mov eax, cr3 mov cr3, eax - + mov eax, edx ret - + _MpMtrrSynchUpEntry ENDP - + _MpMtrrSynchUpExit PROC NEAR PUBLIC push ebp ; C prolog diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpProc.s b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpProc.s index 73ebd1cf2e..797ea9be6d 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpProc.s +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpProc.s @@ -38,7 +38,7 @@ ASM_PFX(MpMtrrSynchUpEntry): # movl %cr3, %eax movl %eax, %cr3 - + movl %edx, %eax ret #MpMtrrSynchUpEntry ENDP @@ -63,7 +63,7 @@ ASM_PFX(MpMtrrSynchUpExit): # movl 8(%ebp), %eax movl %eax, %cr4 - + pop %ebp ret #MpMtrrSynchUpExit ENDP diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/ProcessorDef.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/ProcessorDef.h index c150ba60b7..174f9e2312 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/ProcessorDef.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/ProcessorDef.h @@ -19,7 +19,7 @@ #pragma pack(1) /** - @todo No structure description + @todo No structure description **/ typedef struct { @@ -32,7 +32,7 @@ typedef struct { #pragma pack() /** - @todo No structure description + @todo No structure description **/ @@ -54,3 +54,4 @@ AsmGetAddressMap ( ); #endif + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MemoryAttribute.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MemoryAttribute.c index ddf4f56536..2dd763c065 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MemoryAttribute.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MemoryAttribute.c @@ -39,7 +39,7 @@ extern UINT64 mValidMtrrBitsMask; /** @todo Add function description - @retval @todo add return values + @retval @todo add return values **/ VOID @@ -61,7 +61,7 @@ PreMtrrChange ( /** @todo Add function description - @retval @todo add return values + @retval @todo add return values **/ VOID @@ -973,3 +973,4 @@ SetGcdMemorySpaceAttributes ( return EFI_SUCCESS; } + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MemoryAttribute.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MemoryAttribute.h index eb70d66252..b20546b890 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MemoryAttribute.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MemoryAttribute.h @@ -18,7 +18,7 @@ extern UINT32 mUsedMtrr; /** - @todo add description + @todo add description **/ typedef struct { @@ -27,7 +27,7 @@ typedef struct { UINT32 Length; } EFI_FIXED_MTRR; /** - @todo add description + @todo add description **/ typedef struct { @@ -134,3 +134,4 @@ SetGcdMemorySpaceAttributes ( IN UINT64 Attributes ); #endif + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Microcode.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Microcode.c index 61b7227a4e..1e09c6eee1 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Microcode.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Microcode.c @@ -23,7 +23,7 @@ EFI_CPU_MICROCODE_HEADER **mMicrocodePointerBuffer; BOOLEAN mVerifyMicrocodeChecksum = TRUE; // -// Function declaration +// Function declaration // EFI_STATUS FindLoadMicrocode ( @@ -481,3 +481,4 @@ CheckMicrocodeUpdate ( DataSize ); } + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MiscFuncs.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MiscFuncs.c index 975907fa39..5490f55454 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MiscFuncs.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MiscFuncs.c @@ -20,7 +20,7 @@ extern MP_SYSTEM_DATA *mMPSystemData; /** - @todo add description + @todo add description **/ VOID @@ -50,7 +50,7 @@ EfiWriteToScript ( } /** - @todo add description + @todo add description **/ VOID @@ -87,7 +87,7 @@ CpuMiscEnable ( } /** - @todo add description + @todo add description **/ VOID @@ -101,3 +101,4 @@ ProgramProcessorFuncs ( CpuMiscEnable (MPSystemData->MonitorMwaitEnable, B_EFI_MSR_IA32_MISC_ENABLE_MONITOR); } + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MiscFuncs.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MiscFuncs.h index c64c2d1dcc..c2ab1b5e96 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MiscFuncs.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MiscFuncs.h @@ -43,3 +43,4 @@ CpuMiscEnable ( ); #endif + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpCommon.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpCommon.c index ad98d91a56..7a9c12f631 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpCommon.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpCommon.c @@ -30,7 +30,7 @@ EFI_GUID mSmramCpuNvsHeaderGuid = EFI_SMRAM_CPU_NVS_HEADER_GUID; CHAR16 EfiPlatformCpuInfoVariable[] = L"PlatformCpuInfo"; /** - @todo add description + @todo add description **/ BOOLEAN @@ -454,7 +454,7 @@ int _outp( #endif /** - @todo add description + @todo add description **/ VOID @@ -877,3 +877,4 @@ ResetAPs ( ) { } + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpCommon.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpCommon.h index 33840aa76e..7327a3653d 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpCommon.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpCommon.h @@ -53,7 +53,7 @@ #define SIZE_OF_MCE_HANDLER 16 /** - @todo add description + @todo add description **/ typedef struct { @@ -67,7 +67,7 @@ typedef struct { #pragma pack() /** - @todo add description + @todo add description **/ typedef struct { @@ -83,7 +83,7 @@ typedef enum { } WAKEUP_AP_MANNER; /** - @todo add description + @todo add description **/ typedef struct { @@ -423,3 +423,4 @@ LegacyRegionAPCount ( ); #endif + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpCpu.inf b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpCpu.inf index dfade3f5c5..3025a459af 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpCpu.inf +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpCpu.inf @@ -96,7 +96,7 @@ [Packages] MdePkg/MdePkg.dec IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec - BraswellPlatformPkg/BraswellPlatformPkg.dec + BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/IntelSiliconBasic.dec [LibraryClasses] BaseMemoryLib diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpService.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpService.c index 5157e766ae..6d12d8ea65 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpService.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpService.c @@ -975,11 +975,11 @@ PollForInitialization ( } /** - @todo Add function description + @todo Add function description - @param[in] Location @todo Add argument description + @param[in] Location @todo Add argument description - @retval EFI_SUCCESS @todo Add argument description + @retval EFI_SUCCESS @todo Add argument description **/ EFI_STATUS @@ -1779,3 +1779,4 @@ LegacyRegionAPCount ( AsmReleaseMPLock (&mMPSystemData->APSerializeLock); } + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MtrrSync.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MtrrSync.c index daf3f5dc60..7c0a357d72 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MtrrSync.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MtrrSync.c @@ -184,7 +184,7 @@ MpMtrrSynchUp ( } /** - @todo add description + @todo add description **/ VOID @@ -231,3 +231,4 @@ SaveBspMtrrForS3 ( ASSERT (TableIndex < MAX_CPU_S3_MTRR_ENTRY); } + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/PlatformMpService.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/PlatformMpService.h index aaac6ceb8a..29ba5686dc 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/PlatformMpService.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/PlatformMpService.h @@ -20,7 +20,7 @@ #include "MpCommon.h" /** - @todo add description + @todo add description **/ typedef struct { @@ -54,7 +54,7 @@ typedef struct { #define MSR_L3_CACHE_DISABLE 0x40 /** - @todo add description + @todo add description **/ typedef struct { @@ -88,7 +88,7 @@ typedef enum { #define MAX_FEATURE_NUM 6 /** - @todo add description + @todo add description **/ typedef struct { @@ -127,7 +127,7 @@ typedef struct { } CPU_DATA_BLOCK; /** - @todo add description + @todo add description **/ typedef struct { @@ -137,7 +137,7 @@ typedef struct { } MP_CPU_S3_SCRIPT_DATA; /** - @todo add description + @todo add description **/ typedef struct { @@ -147,7 +147,7 @@ typedef struct { } MP_CPU_S3_DATA_POINTER; /** - @todo add description + @todo add description **/ #pragma pack (1) @@ -238,7 +238,7 @@ typedef struct { #pragma pack (1) /** - @todo add description + @todo add description **/ typedef struct { @@ -252,7 +252,7 @@ typedef struct { #define CPU_MP_SERVICE_PRIVATE_SIGNATURE EFI_SIGNATURE_32 ('m', 'p', '3', '2') /** - @todo add description + @todo add description **/ typedef struct { @@ -634,3 +634,4 @@ GetCoreNumber ( ); #endif + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/Cpu.asm b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/Cpu.asm index c621e28bfb..b19f5f7f0f 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/Cpu.asm +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/Cpu.asm @@ -114,7 +114,7 @@ CpuSwitchStacks PROC PUBLIC call rcx ; rcx = EntryPoint ; ; no ret as we have a new stack and we jumped to the new location - ; + ; CpuSwitchStacks ENDP ;------------------------------------------------------------------------------ @@ -122,7 +122,7 @@ CpuSwitchStacks ENDP ; CpuSwitchStacks2Args ( ; IN UINTN EntryPoint, // rcx ; IN UINTN Parameter1, // rdx -; IN UINTN Parameter2, // r8 +; IN UINTN Parameter2, // r8 ; IN UINTN NewStack, // r9 ; IN UINTN Bsp // Only used on IPF ; ); @@ -130,14 +130,14 @@ CpuSwitchStacks ENDP ; BSP not used on IA-32 ; ;------------------------------------------------------------------------------ -CpuSwitchStacks2Args PROC PUBLIC +CpuSwitchStacks2Args PROC PUBLIC mov rsp, r8 ; rsp = NewStack push r8 ; Parameter2 push rdx ; Parameter1 call rcx ; rcx = EntryPoint ; ; no ret as we have a new stack and we jumped to the new location - ; + ; CpuSwitchStacks2Args ENDP @@ -147,7 +147,7 @@ CpuSwitchStacks2Args PROC PUBLIC ; VOID ; ); ;------------------------------------------------------------------------------ -CpuCodeSegment PROC PUBLIC +CpuCodeSegment PROC PUBLIC xor eax, eax mov eax, cs ret @@ -178,9 +178,9 @@ CpuLoadGlobalDescriptorTable PROC PUBLIC CpuLoadGlobalDescriptorTable ENDP CpuInitSelectors PROC PUBLIC - int 68h - ret -CpuInitSelectors ENDP + int 68h + ret +CpuInitSelectors ENDP ;------------------------------------------------------------------------------ ; VOID ; CpuLoadInterruptDescriptorTable ( diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/CpuAsm.asm b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/CpuAsm.asm index 1082001fc4..7318565e5e 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/CpuAsm.asm +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/CpuAsm.asm @@ -1,4 +1,4 @@ -;; @file +;; @file ; Assembly code of the implementation of X64 CPU architectural protocol ; ; Copyright (c) 2005 - 2015, Intel Corporation. All rights reserved.
@@ -74,7 +74,7 @@ ENDM ; +---------------------+ <-- RBP, 16-byte aligned ; -CommonInterruptEntry PROC PUBLIC +CommonInterruptEntry PROC PUBLIC cli ; ; All interrupt handlers are invoked through interrupt gates, so @@ -97,7 +97,7 @@ NoErrorCode: ; push [rsp] mov qword ptr [rsp + 8], 0 -@@: +@@: push rbp mov rbp, rsp @@ -337,18 +337,18 @@ in_long_mode:: mov rsp, rbx ; On a new stack now mov rcx, [rbp+10h] ; Pass Hob Start in RCX - mov rax, [rbp+20h] ; Get the function pointer for + mov rax, [rbp+20h] ; Get the function pointer for ; PpisNeededByDxeIplEntryPoint into EAX call fword ptr [rax] ; Make the call into PpisNeededByDxeIplEntryPoint mov ecx, [rbp+10h] ; Pass Hob Start in RCX - mov eax, [rbp+28h] ; Get the function pointer for + mov eax, [rbp+28h] ; Get the function pointer for ; DxeCoreEntryPoint into EAX call fword ptr [rax] ; Make the call into Dxe Core call CommonInterruptEntry - mov rdi, CommonInterruptEntry + mov rdi, CommonInterruptEntry lgdt fword ptr [rdi] diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/Exception.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/Exception.c index 4e4d4ed1c0..6f1b3bcf08 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/Exception.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/Exception.c @@ -24,7 +24,7 @@ VOID IN VOID *SystemContext ); /** - @todo No structure description + @todo No structure description **/ typedef struct { diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/MemoryOperation.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/MemoryOperation.c index 83bfa8bf05..8dc8f6f061 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/MemoryOperation.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/MemoryOperation.c @@ -49,7 +49,7 @@ UINT64 mValidMtrrBitsMask; #pragma pack (1) /** - @todo add description + @todo add description **/ typedef struct { @@ -62,7 +62,7 @@ typedef struct { } SEGMENT_DESCRIPTOR_x64; /** - @todo Add description + @todo Add description **/ @@ -161,7 +161,7 @@ ALINE_16BYTE_BOUNDRY PSEUDO_DESCRIPTOR_x64 gLidtPseudoDescriptor = { }; /** - @todo add function description + @todo add function description **/ VOID @@ -210,7 +210,7 @@ InitializeInterruptTables ( } /** - @todo add function description + @todo add function description **/ VOID @@ -288,7 +288,7 @@ InitailizeMemoryAttributes ( } /** - @todo add function description + @todo add function description **/ VOID * @@ -312,7 +312,7 @@ AllocateZeroedPage ( @param[in] PageAddress @param[in] **PageDirectoryToConvert - @todo review parameters and description + @todo review parameters and description **/ VOID @@ -367,13 +367,13 @@ Convert2MBPageTo4KPages ( } /** - @todo Add description to function + @todo Add description to function - @param[in] BaseAddress @todo Add parameter description - @param[out] PageTable @todo Add parameter description - @param[out] Page2MBytes @todo Add parameter description + @param[in] BaseAddress @todo Add parameter description + @param[out] PageTable @todo Add parameter description + @param[out] Page2MBytes @todo Add parameter description - @retval @todo Add return value description + @retval @todo Add return value description **/ EFI_STATUS @@ -525,7 +525,7 @@ PrepareMemoryForAPs ( @param[in] ApFunction Address of function assigned to AP. @param[in] WakeUpBuffer Pointer to the address of wakeup buffer. - @retval EFI_SUCCESS Exchange Info successfully prepared for APs. + @retval EFI_SUCCESS Exchange Info successfully prepared for APs. **/ EFI_STATUS @@ -716,3 +716,4 @@ PrepareGdtIdtForAP ( return EFI_SUCCESS; } + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/MpCpu.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/MpCpu.c index 7ef2f43ba1..d2eb96df49 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/MpCpu.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/MpCpu.c @@ -74,3 +74,4 @@ InitializeMpSupport ( return EFI_SUCCESS; } + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/MpFuncs.asm b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/MpFuncs.asm index 9970dfba48..6a843e2a4e 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/MpFuncs.asm +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/MpFuncs.asm @@ -13,7 +13,7 @@ ; ;; -include Htequ.inc +include Htequ.inc ;------------------------------------------------------------------------------------- ;------------------------------------------------------------------------------------- @@ -36,7 +36,7 @@ RendezvousFunnelProcStart:: db 8ch, 0c8h ; mov ax, cs db 8eh, 0d8h ; mov ds, ax db 8eh, 0c0h ; mov es, ax - db 8eh, 0d0h ; mov ss, ax + db 8eh, 0d0h ; mov ss, ax db 33h, 0c0h ; xor ax, ax db 8eh, 0e0h ; mov fs, ax db 8eh, 0e8h ; mov gs, ax @@ -60,7 +60,7 @@ RendezvousFunnelProcStart:: db flat32Start - ($ + 1) ; jz flat32Start ; Record BIST information -; +; db 0B0h, 08h ; mov al, 8 db 0F6h, 0E3h ; mul bl @@ -70,7 +70,7 @@ RendezvousFunnelProcStart:: db 66h, 0C7h, 04h dd 00000001h ; mov dword ptr [si], 1 ; Set Valid Flag - db 66h, 89h, 6Ch, 04h ; mov dword ptr [si + 4], ebp ; Store BIST value + db 66h, 89h, 6Ch, 04h ; mov dword ptr [si + 4], ebp ; Store BIST value cli hlt @@ -101,7 +101,7 @@ flat32Start:: db 0BFh ; opcode of mov di, imm16 dw LongModeStartJump - RendezvousFunnelProcStart ; Get offset of LongModeStartJump - db 66h, 8Bh, 3Dh ; mov edi,dword ptr [di] ; EDI is keeping the LongModeStart Jump Address + db 66h, 8Bh, 3Dh ; mov edi,dword ptr [di] ; EDI is keeping the LongModeStart Jump Address db 31h, 0C0h ; xor ax, ax db 8Eh, 0D8h ; mov ds, ax @@ -179,7 +179,7 @@ LongModeStart:: add edx, RunLoopAndMwaitLoop64Jump - LongModeStart mov dword ptr [rdx], eax -; +; ; ProgramStack ; xor rcx, rcx @@ -306,7 +306,7 @@ RunLoopAndMwaitLoop32:: db 66h, 0B8h, 18h, 00h ; mov ax, 18h db 66h, 8Eh, 0D8h ; mov ds, ax - db 8eh, 0d0h ; mov ss, ax + db 8eh, 0d0h ; mov ss, ax db 0Fh, 20h, 0C0h ; mov eax, cr0 ; Read CR0. db 0Fh, 0BAh, 0F0h, 1Fh ; btr eax, 31 ; Reset PG=0. @@ -387,9 +387,9 @@ AsmGetAddressMap PROC PUBLIC mov qword ptr [rcx+18h], LongModeStart - RendezvousFunnelProcStart mov qword ptr [rcx+20h], LONG_JUMP - RendezvousFunnelProcStart mov qword ptr [rcx+28h], RendezvousFunnelProcEnd - RendezvousFunnelProcStart - + ret - + AsmGetAddressMap ENDP AsmGetGdtrIdtr PROC PUBLIC @@ -401,16 +401,16 @@ AsmGetGdtrIdtr PROC PUBLIC sidt IdtDesc lea rax, IdtDesc mov [rdx], rax - + ret - + AsmGetGdtrIdtr ENDP AsmGetCr3 PROC PUBLIC - + mov rax, cr3 ret - + AsmGetCr3 ENDP @@ -423,24 +423,24 @@ TryGetLock: jz LockObtained pause - jmp TryGetLock + jmp TryGetLock LockObtained: ret - + AsmAcquireMPLock ENDP AsmReleaseMPLock PROC PUBLIC mov al, VacantFlag xchg al, byte ptr [rcx] - + ret - + AsmReleaseMPLock ENDP ;------------------------------------------------------------------------------------- -;AsmExchangeRole procedure follows. This procedure executed by current BSP, that is +;AsmExchangeRole procedure follows. This procedure executed by current BSP, that is ;about to become an AP. It switches it'stack with the current AP. ;AsmExchangeRole (IN CPU_EXCHANGE_INFO *MyInfo, IN CPU_EXCHANGE_INFO *OthersInfo); ;------------------------------------------------------------------------------------- @@ -470,10 +470,10 @@ AsmExchangeRole PROC PUBLIC mov rax, cr0 push rax - + mov rax, cr4 push rax - + ; rsi contains MyInfo pointer mov rsi, rcx @@ -484,7 +484,7 @@ AsmExchangeRole PROC PUBLIC pushfq sgdt fword ptr [rsi + 16] sidt fword ptr [rsi + 26] - + ; Store the its StackPointer mov qword ptr [rsi + 8], rsp @@ -497,13 +497,13 @@ TryLock1: jz LockObtained1 pause jmp TryLock1 - + LockObtained1: mov byte ptr [rsi + 1], CPU_SWITCH_STATE_STORED db 0f0h ; opcode for lock instruction xchg al, byte ptr [rsi] -WaitForOtherStored:: +WaitForOtherStored:: ; wait until the other CPU finish storing its state mov al, NotVacantFlag TryLock2: @@ -513,24 +513,24 @@ TryLock2: jz LockObtained2 PAUSE32 jmp TryLock2 - + LockObtained2: mov bl, byte ptr [rdi + 1] db 0f0h ; opcode for lock instruction xchg al, byte ptr [rdi] cmp bl, CPU_SWITCH_STATE_STORED jb WaitForOtherStored - + ; Since another CPU already stored its state, load them ; load GDTR value lgdt fword ptr [rdi + 16] - + ; load IDTR value lidt fword ptr [rdi + 26] ; load its future StackPointer mov rsp, qword ptr [rdi + 8] - + ; update its switch state to LOADED mov al, NotVacantFlag TryLock3: @@ -540,7 +540,7 @@ TryLock3: jz LockObtained3 PAUSE32 jmp TryLock3 - + LockObtained3: mov byte ptr [rsi+1], CPU_SWITCH_STATE_LOADED db 0f0h ; opcode for lock instruction @@ -557,7 +557,7 @@ TryLock4: jz LockObtained4 PAUSE32 jmp TryLock4 - + LockObtained4: mov bl, byte ptr [rdi+1] db 0f0h ; opcode for lock instruction @@ -570,10 +570,10 @@ LockObtained4: pop rax mov cr4, rax - + pop rax mov cr0, rax - + pop r15 pop r14 pop r13 @@ -595,7 +595,7 @@ AsmExchangeRole ENDP GdtDesc QWORD 0 WORD 0 - + IdtDesc QWORD 0 WORD 0 diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/PlatformCpuLib.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/PlatformCpuLib.h index 33fc064199..1c9e17ffab 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/PlatformCpuLib.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/PlatformCpuLib.h @@ -133,3 +133,4 @@ CpuLoadInterruptDescriptorTable ( ); #endif + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/ProcessorDef.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/ProcessorDef.h index 328a12fdd0..d6612296c3 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/ProcessorDef.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/ProcessorDef.h @@ -18,7 +18,7 @@ #pragma pack(1) /** - @todo @todo add structure description + @todo @todo add structure description **/ typedef struct { @@ -32,7 +32,7 @@ typedef struct { #pragma pack() /** - @todo @todo add structure description + @todo @todo add structure description **/ typedef struct { @@ -55,3 +55,4 @@ AsmGetAddressMap ( ); #endif + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/VirtualMemory.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/VirtualMemory.h index e8ef0afc82..1ff5861300 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/VirtualMemory.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/VirtualMemory.h @@ -118,7 +118,7 @@ typedef union { UINT64 Uint64; } x64_PAGE_TABLE_ENTRY_2M; /** - @todo Add union description + @todo Add union description **/ typedef union { @@ -132,7 +132,7 @@ typedef union { UINT64 Reserved:57; } x64_PAGE_TABLE_ENTRY_COMMON; /** - @todo Add union description + @todo Add union description **/ typedef union { @@ -145,3 +145,4 @@ typedef union { #pragma pack() #endif + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Include/Library/CpuConfigLib.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Include/Library/CpuConfigLib.h index bbe631ed07..56a24dffa2 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Include/Library/CpuConfigLib.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Include/Library/CpuConfigLib.h @@ -684,3 +684,4 @@ SetAndReadCpuCallbackSignal ( ); #endif + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Include/Library/SmmCpuPlatformHookLib.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Include/Library/SmmCpuPlatformHookLib.h index 25d3299226..ea09e539bd 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Include/Library/SmmCpuPlatformHookLib.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Include/Library/SmmCpuPlatformHookLib.h @@ -105,3 +105,4 @@ GetPlatformPageTableAttribute ( ); #endif + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Include/Library/SocketLga775Lib.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Include/Library/SocketLga775Lib.h index 98922d3a73..7173dd79c0 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Include/Library/SocketLga775Lib.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Include/Library/SocketLga775Lib.h @@ -312,3 +312,4 @@ typedef struct { #pragma pack () #endif + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Include/Protocol/SmmCpuSync.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Include/Protocol/SmmCpuSync.h index a0de096e61..0eb96a3133 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Include/Protocol/SmmCpuSync.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Include/Protocol/SmmCpuSync.h @@ -105,3 +105,4 @@ struct _SMM_CPU_SYNC_PROTOCOL { extern EFI_GUID gSmmCpuSyncProtocolGuid; #endif + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Include/Protocol/SmmCpuSync2.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Include/Protocol/SmmCpuSync2.h index b742e536e7..b075e1fe30 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Include/Protocol/SmmCpuSync2.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Include/Protocol/SmmCpuSync2.h @@ -184,3 +184,4 @@ struct _SMM_CPU_SYNC2_PROTOCOL { extern EFI_GUID gSmmCpuSync2ProtocolGuid; #endif + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/IntelSiliconBasic.dec b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/IntelSiliconBasic.dec new file mode 100644 index 0000000000..74c06a0283 --- /dev/null +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/IntelSiliconBasic.dec @@ -0,0 +1,206 @@ +## @file +# IntelSiBasic Package. +# +# Copyright (c) 2015, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + DEC_SPECIFICATION = 0x00010005 + PACKAGE_NAME = IntelSiBasicPkg + PACKAGE_GUID = AF1E4740-7083-4D4E-A83E-2A662CCF3A31 + PACKAGE_VERSION = 0.1 + +[Includes] + Include + +[Guids] +gIntelSiBasicPkgTokenSpaceGuid = { 0x6de9e48c, 0x622, 0x4a33, { 0xab, 0x29, 0xdd, 0xc8, 0xd4, 0xf9, 0xc7, 0x6d}} + +## Include/MultiPlatSupport.h +gDefaultDataFileGuid = { 0x1ae42876, 0x008f, 0x4161, { 0xb2, 0xb7, 0x1c, 0x0d, 0x15, 0xc5, 0xef, 0x43 }} +gDefaultDataOptSizeFileGuid = { 0x003e7b41, 0x98a2, 0x4be2, { 0xb2, 0x7a, 0x6c, 0x30, 0xc7, 0x65, 0x52, 0x25 }} + +gEfiHtBistHobGuid = {0xbe644001, 0xe7d4, 0x48b1, {0xb0, 0x96, 0x8b, 0xa0, 0x47, 0xbc, 0x7a, 0xe7}} + +## Include/Guid/IA32FamilyCpuPkgTokenSpace.h + gEfiCpuTokenSpaceGuid = { 0x2ADA836D, 0x0A3D, 0x43D6, { 0xA2, 0x5A, 0x38, 0x45, 0xCA, 0xD2, 0xD4, 0x00 }} + +[Protocols] +## Include/Protocol/FlashDeviceInfo.h +gFlashDeviceInfoProtocolGuid = { 0xcdd3ef06, 0xe873, 0x46ee, { 0xa0, 0x64, 0x7e, 0xc0, 0xb2, 0xc5, 0x6c, 0x11 }} + +gSmmCpuSyncProtocolGuid = { 0xd5950985, 0x8be3, 0x4b1c, { 0xb6, 0x3f, 0x95, 0xd1, 0x5a, 0xb3, 0xb6, 0x5f }} +gSmmCpuSync2ProtocolGuid = { 0x9db72e22, 0x9262, 0x4a18, { 0x8f, 0xe0, 0x85, 0xe0, 0x3d, 0xfa, 0x96, 0x73 }} +gEfiSmmCpuServiceProtocolGuid = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }} + +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic] +# +# ACPI timer +# +gIntelSiBasicPkgTokenSpaceGuid.PcdAcpiIoBaseAddress|0x1800|UINT16|0x10000021 +gIntelSiBasicPkgTokenSpaceGuid.AcpiTimerLength|24|UINT8|0x10000022 + +# +# SATA controller +# +gIntelSiBasicPkgTokenSpaceGuid.SataMaxSataPort|8|UINT8|0x10000023 +gIntelSiBasicPkgTokenSpaceGuid.SataMaxDevicesPerPort|1|UINT8|0x10000024 + +# +# CPU +# +gIntelSiBasicPkgTokenSpaceGuid.CpuNumberOfThreadsPerCore|2|UINT32|0x10000025 +gIntelSiBasicPkgTokenSpaceGuid.CpuNumberOfCoresPerDie|2|UINT32|0x10000026 +gIntelSiBasicPkgTokenSpaceGuid.CpuNumberOfDiesPerPackage|1|UINT32|0x10000027 +gIntelSiBasicPkgTokenSpaceGuid.CpuNumberOfPackages|1|UINT32|0x10000028 + +gIntelSiBasicPkgTokenSpaceGuid.PcdFlashMicroCodeRegionBase|0xFFD60000|UINT32|0x20000015 +gIntelSiBasicPkgTokenSpaceGuid.PcdFlashMicroCodeRegionSize|0x00023000|UINT32|0x20000016 +gIntelSiBasicPkgTokenSpaceGuid.PcdFlashMicroCodeOffset|0x00|UINT32|0x20000017 + +# +# PCI Host bridge +# +## +## PcdEfiGcdAllocateType is using for EFI_GCD_ALLOCATE_TYPE selection +## value of the struct +## 0x00 EfiGcdAllocateAnySearchBottomUp +## 0x01 EfiGcdAllocateMaxAddressSearchBottomUp +## 0x03 EfiGcdAllocateAnySearchTopDown +## 0x04 EfiGcdAllocateMaxAddressSearchTopDown +## +## below value should not using in this situation +## 0x05 EfiGcdMaxAllocateType : design for max value of struct +## 0x02 EfiGcdAllocateAddress : design for speccification address allocate +## +gIntelSiBasicPkgTokenSpaceGuid.PcdEfiGcdAllocateType|0x01|UINT8|0x40000000 + +## +## Allocate 56 KB [0x2000..0xFFFF] of I/O space for Pci Devices +## If PcdPciReservedMemLimit =0 Pci Reserved default MMIO Limit is PciExpressBase else use PcdPciReservedMemLimit . +## +gIntelSiBasicPkgTokenSpaceGuid.PcdPciReservedIobase |0x1000 |UINT16|0x00010041 +gIntelSiBasicPkgTokenSpaceGuid.PcdPciReservedIoLimit |0xFFFF |UINT16|0x00010042 +gIntelSiBasicPkgTokenSpaceGuid.PcdMmioBase |0x80000000 |UINT32|0x00010043 +gIntelSiBasicPkgTokenSpaceGuid.PcdPciReservedMemLimit |0x00000000 |UINT32|0x00010044 +gIntelSiBasicPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase |0x0000000000000000 |UINT64|0x00010045 +gIntelSiBasicPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit |0x0000000000000000 |UINT64|0x00010046 + +## +## Indicates the receive FIFO depth of UART controller.

+## @Prompt Default UART Receive FIFO Depth. +gIntelSiBasicPkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|1|UINT16|0x00000031 + +## Indidates if SMM Delay feature is supported.

+# TRUE - SMM Delay feature is supported.
+# FALSE - SMM Delay feature is not supported.
+# @Prompt SMM Delay feature. +gEfiCpuTokenSpaceGuid.PcdCpuSmmUseDelayIndication|TRUE|BOOLEAN|0x60000018 +## Indidates if SMM Block feature is supported.

+# TRUE - SMM Block feature is supported.
+# FALSE - SMM Block feature is not supported.
+# @Prompt SMM Block feature. +gEfiCpuTokenSpaceGuid.PcdCpuSmmUseBlockIndication|TRUE|BOOLEAN|0x60000019 + +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic] + + ## Specifies maximum number of processors supported by the platform. + # @Prompt Maximum number of processors supported by the platform. + gEfiCpuTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|64|UINT32|0x30000002 + ## Specifies timeout value in microseconds for the BSP in SMM to wait for all APs to come into SMM. + # @Prompt AP synchronization timeout value in SMM. + gEfiCpuTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000000|UINT64|0x32132104 + ## Specifies stack size in bytes for each processor in SMM. + # @Prompt Processor stack size in SMM. + gEfiCpuTokenSpaceGuid.PcdCpuSmmStackSize|0x2000|UINT32|0x32132105 + ## Specifies buffer size in bytes to save SMM profile data. The value should be a multiple of 4KB. + # @Prompt SMM profile data buffer size. + gEfiCpuTokenSpaceGuid.PcdCpuSmmProfileSize|0x200000|UINT32|0x32132107 + ## Indidates if SMM Code Access Check is enabled. + # If enabled, the SMM handler cannot execut the code outside ranges defined by SMRR. + # This PCD is suggested to TRUE in production image.

+ # TRUE - SMM Code Access Check will be enabled.
+ # FALSE - SMM Code Access Check will be disabled.
+ # @Prompt SMM Code Access Check. + gEfiCpuTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable|TRUE|BOOLEAN|0x60000013 + + + +[PcdsFeatureFlag] + ## Indicates if BSP election in SMM will be enabled. + # If enabled, a BSP will be dynamically elected among all processors in each SMI. + # Otherwise, processor 0 is always as BSP in each SMI.

+ # TRUE - BSP election in SMM will be enabled.
+ # FALSE - BSP election in SMM will be disabled.
+ # @Prompt Enable BSP election in SMM. + gEfiCpuTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE|BOOLEAN|0x32132106 + ## Indicates if SMM Debug will be enabled. + # If enabled, hardware breakpoints in SMRAM can be set outside of SMM mode and take effect in SMM.

+ # TRUE - SMM Debug will be enabled.
+ # FALSE - SMM Debug will be disabled.
+ # @Prompt Enable SMM Debug. + gEfiCpuTokenSpaceGuid.PcdCpuSmmDebug|FALSE|BOOLEAN|0x1000001B + ## Indicates if SMM Stack Guard will be enabled. + # If enabled, stack overflow in SMM can be caught which eases debugging.

+ # TRUE - SMM Stack Guard will be enabled.
+ # FALSE - SMM Stack Guard will be disabled.
+ # @Prompt Enable SMM Stack Guard. + gEfiCpuTokenSpaceGuid.PcdCpuSmmStackGuard|FALSE|BOOLEAN|0x1000001C + ## Indicates if SMM Startup AP in a blocking fashion. + # TRUE - SMM Startup AP in a blocking fashion.
+ # FALSE - SMM Startup AP in a non-blocking fashion.
+ # @Prompt SMM Startup AP in a blocking fashion. + gEfiCpuTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|FALSE|BOOLEAN|0x32132108 + ## Indicates if SMM Profile will be enabled. + # If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged. + # This PCD is only for validation purpose. It should be set to false in production.

+ # TRUE - SMM Profile will be enabled.
+ # FALSE - SMM Profile will be disabled.
+ # @Prompt Enable SMM Profile. + gEfiCpuTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE|BOOLEAN|0x32132109 + ## Indicates if the SMM profile log buffer is a ring buffer. + # If disabled, no additional log can be done when the buffer is full.

+ # TRUE - the SMM profile log buffer is a ring buffer.
+ # FALSE - the SMM profile log buffer is a normal buffer.
+ # @Prompt The SMM profile log buffer is a ring buffer. + gEfiCpuTokenSpaceGuid.PcdCpuSmmProfileRingBuffer|FALSE|BOOLEAN|0x3213210a + ## Indicates if SMM MP sync data resides in un-cached RAM.

+ # TRUE - SMM MP sync data will be resided in un-cached RAM.
+ # FALSE - SMM MP sync data will be resided in cached RAM.
+ # @Prompt SMM MP sync data resides in un-cached RAM. + gEfiCpuTokenSpaceGuid.PcdCpuSmmUncacheCpuSyncData|FALSE|BOOLEAN|0x3213210D + ## Indidates if CPU SMM hot-plug will be enabled.

+ # TRUE - SMM CPU hot-plug will be enabled.
+ # FALSE - SMM CPU hot-plug will be disabled.
+ # @Prompt SMM CPU hot-plug. + gEfiCpuTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE|BOOLEAN|0x3213210C + ## Indidates if lock SMM Feature Control MSR.

+ # TRUE - SMM Feature Control MSR will be locked.
+ # FALSE - SMM Feature Control MSR will not be locked.
+ # @Prompt Lock SMM Feature Control MSR. + gEfiCpuTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|TRUE|BOOLEAN|0x3213210B + +[PcdsDynamic,PcdsDynamicEx] + ## Contains the pointer to CPU Configuration Context Buffer defined in the CpuConfigLib. + # @Prompt The pointer to CPU Configuration Context Buffer. + gEfiCpuTokenSpaceGuid.PcdCpuConfigContextBuffer|0x0|UINT64|0x50000001 + ## Used for a callback mechanism for the CPU MP driver. + # The CPU MP driver will set this PCD at pre-defined points. If there is callback function registered on it, + # the callback function will be triggered, and it may change the value of PcdCpuCallbackSignal. + # @Prompt PCD for CPU callback signal. + gEfiCpuTokenSpaceGuid.PcdCpuCallbackSignal|0x0|UINT8|0x50000002 + ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA. + # @Prompt The pointer to a CPU S3 data buffer. + gEfiCpuTokenSpaceGuid.PcdCpuS3DataAddress|0x0|UINT64|0x60000010 + ## Contains the pointer to a CPU Hot Plug Data structure if CPU hot-plug is supported. + # @Prompt The pointer to CPU Hot Plug Data. + gEfiCpuTokenSpaceGuid.PcdCpuHotPlugDataAddress|0x0|UINT64|0x60000011 diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Library/CpuConfigLib/CpuConfig.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Library/CpuConfigLib/CpuConfig.c index b9b81f92ce..74c86de982 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Library/CpuConfigLib/CpuConfig.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Library/CpuConfigLib/CpuConfig.c @@ -959,3 +959,4 @@ SearchFeatureEntry ( FeatureEntry = CPU_FEATURE_ENTRY_FROM_LINK (Link); return FeatureEntry; } + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Library/CpuConfigLib/CpuConfig.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Library/CpuConfigLib/CpuConfig.h index d3dd0a6fdd..1d4b8b18b8 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Library/CpuConfigLib/CpuConfig.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Library/CpuConfigLib/CpuConfig.h @@ -63,3 +63,4 @@ SearchFeatureEntry ( ); #endif + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Library/CpuConfigLib/CpuConfigLib.inf b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Library/CpuConfigLib/CpuConfigLib.inf index cd2e231796..8284cb6501 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Library/CpuConfigLib/CpuConfigLib.inf +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Library/CpuConfigLib/CpuConfigLib.inf @@ -38,7 +38,7 @@ [Packages] MdePkg/MdePkg.dec - BraswellPlatformPkg/BraswellPlatformPkg.dec + BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/IntelSiliconBasic.dec [LibraryClasses] PcdLib @@ -55,3 +55,4 @@ ## CONSUMES gEfiCpuTokenSpaceGuid.PcdCpuConfigContextBuffer + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.c index bd4417da80..f446847584 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.c @@ -107,3 +107,4 @@ GetPlatformPageTableAttribute ( { return EFI_UNSUPPORTED; } + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.inf b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.inf index 127feca553..0419d5b4f4 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.inf +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.inf @@ -42,4 +42,5 @@ [Packages] MdePkg/MdePkg.dec - BraswellPlatformPkg/BraswellPlatformPkg.dec + BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/IntelSiliconBasic.dec + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PciHostBridge/PciHostBridge.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PciHostBridge/PciHostBridge.c index 66fbf7c3d2..1c296d4671 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PciHostBridge/PciHostBridge.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PciHostBridge/PciHostBridge.c @@ -469,7 +469,7 @@ NotifyPhase ( } /** - @todo add description + @todo add description **/ EFI_STATUS @@ -1103,3 +1103,4 @@ Power2MaxMemory ( return Result; } + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PciHostBridge/PciHostBridge.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PciHostBridge/PciHostBridge.h index a6d1f09d1f..c78ba22a2c 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PciHostBridge/PciHostBridge.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PciHostBridge/PciHostBridge.h @@ -48,7 +48,7 @@ typedef struct { // HostBridge Resource Allocation interface // /** - @todo add description + @todo add description **/ EFI_STATUS @@ -59,7 +59,7 @@ NotifyPhase ( ); /** - @todo add description + @todo add description **/ EFI_STATUS @@ -70,7 +70,7 @@ GetNextRootBridge ( ); /** - @todo add description + @todo add description **/ EFI_STATUS @@ -82,7 +82,7 @@ GetAttributes ( ); /** - @todo add description + @todo add description **/ EFI_STATUS @@ -94,7 +94,7 @@ StartBusEnumeration ( ); /** - @todo add description + @todo add description **/ EFI_STATUS @@ -106,7 +106,7 @@ SetBusNumbers ( ); /** - @todo add description + @todo add description **/ EFI_STATUS @@ -118,7 +118,7 @@ SubmitResources ( ); /** - @todo add description + @todo add description **/ EFI_STATUS @@ -130,7 +130,7 @@ GetProposedResources ( ); /** - @todo add description + @todo add description **/ EFI_STATUS @@ -146,7 +146,7 @@ PreprocessController ( // Help function // /** - @todo add description + @todo add description **/ UINT64 @@ -155,3 +155,4 @@ Power2MaxMemory ( ); #endif + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PciHostBridge/PciHostBridge.inf b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PciHostBridge/PciHostBridge.inf index be1bccc8e9..e12d266b31 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PciHostBridge/PciHostBridge.inf +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PciHostBridge/PciHostBridge.inf @@ -38,7 +38,7 @@ [Packages] MdePkg/MdePkg.dec - BraswellPlatformPkg/BraswellPlatformPkg.dec + BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/IntelSiliconBasic.dec [LibraryClasses] UefiDriverEntryPoint diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PciHostBridge/PciRootBridge.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PciHostBridge/PciRootBridge.h index 31ded9386f..0f0b2da7a7 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PciHostBridge/PciRootBridge.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PciHostBridge/PciRootBridge.h @@ -137,10 +137,10 @@ typedef struct { /** @todo Add function description - @param[in] Protocol - @todo add argument description - @param[in] HostBridgeHandle - @todo add argument description - @param[in] Attri - @todo add argument description - @param[in] ResAppeture - @todo add argument description + @param[in] Protocol - @todo add argument description + @param[in] HostBridgeHandle - @todo add argument description + @param[in] Attri - @todo add argument description + @param[in] ResAppeture - @todo add argument description @retval - @todo add return values @@ -153,3 +153,4 @@ RootBridgeConstructor ( IN PCI_ROOT_BRIDGE_RESOURCE_APPETURE *ResAppeture ); #endif + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PciHostBridge/PciRootBridgeIo.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PciHostBridge/PciRootBridgeIo.c index 5ce22cd215..bec964136e 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PciHostBridge/PciRootBridgeIo.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PciHostBridge/PciRootBridgeIo.c @@ -404,7 +404,7 @@ RootBridgeConstructor ( } /** - @todo add description + @todo add description **/ /** @@ -499,7 +499,7 @@ RootBridgeIoPollMem ( } /** - @todo add description + @todo add description **/ /** @@ -593,7 +593,7 @@ RootBridgeIoPollIo ( } /** - @todo add description + @todo add description **/ /** @@ -662,7 +662,7 @@ RootBridgeIoMemRead ( } /** - @todo add description + @todo add description **/ /** @@ -732,7 +732,7 @@ RootBridgeIoMemWrite ( } /** - @todo add description + @todo add description **/ /** @@ -814,7 +814,7 @@ RootBridgeIoIoRead ( } /** - @todo add description + @todo add description **/ /** @@ -895,7 +895,7 @@ RootBridgeIoIoWrite ( } /** - @todo add description + @todo add description **/ /** @@ -979,7 +979,7 @@ RootBridgeIoCopyMem ( } /** - @todo add description + @todo add description **/ /** @@ -1017,7 +1017,7 @@ RootBridgeIoPciRead ( } /** - @todo add description + @todo add description **/ /** @@ -1247,7 +1247,7 @@ RootBridgeIoFreeBuffer ( } /** - @todo add description + @todo add description **/ /** @@ -1268,7 +1268,7 @@ RootBridgeIoFlush ( } /** - @todo add description + @todo add description **/ /** @@ -1349,7 +1349,7 @@ RootBridgeIoSetAttributes ( } /** - @todo add description + @todo add description **/ /** @@ -1385,7 +1385,7 @@ RootBridgeIoConfiguration ( } /** - @todo add description + @todo add description **/ /** @@ -1457,3 +1457,4 @@ RootBridgeIoPciRW ( return EFI_SUCCESS; } + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCommunication/PiSmmCommunicationPei.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCommunication/PiSmmCommunicationPei.c index d546181ca5..eb3f16d0d7 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCommunication/PiSmmCommunicationPei.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCommunication/PiSmmCommunicationPei.c @@ -422,3 +422,4 @@ PiSmmCommunicationPeiEntryPoint ( return RETURN_SUCCESS; } + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCommunication/PiSmmCommunicationPrivate.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCommunication/PiSmmCommunicationPrivate.h index 1001aa2416..e4da77ae6e 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCommunication/PiSmmCommunicationPrivate.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCommunication/PiSmmCommunicationPrivate.h @@ -29,3 +29,4 @@ typedef struct { #pragma pack(pop) #endif + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCommunication/PiSmmCommunicationSmm.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCommunication/PiSmmCommunicationSmm.c index 7d2091bb02..ec675a5009 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCommunication/PiSmmCommunicationSmm.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCommunication/PiSmmCommunicationSmm.c @@ -286,3 +286,4 @@ PiSmmCommunicationSmmEntryPoint ( return Status; } + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/MpFuncs.S b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/MpFuncs.S index 7d29b44385..ebc100a74e 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/MpFuncs.S +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/MpFuncs.S @@ -42,7 +42,7 @@ RendezvousFunnelProcStart: .byte 0x8c,0xc8 # mov ax, cs .byte 0x8e,0xd8 # mov ds, ax .byte 0x8e,0xc0 # mov es, ax - .byte 0x8e,0xd0 # mov ss, ax + .byte 0x8e,0xd0 # mov ss, ax .byte 0x33,0xc0 # xor ax, ax .byte 0x8e,0xe0 # mov fs, ax .byte 0x8e,0xe8 # mov gs, ax diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/MpFuncs.asm b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/MpFuncs.asm index 9cfb54e4fa..106aa199fd 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/MpFuncs.asm +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/MpFuncs.asm @@ -14,8 +14,8 @@ ;; .686p -.model flat,C -.code +.model flat,C +.code EXTERN InitializeFloatingPointUnits:PROC @@ -47,7 +47,7 @@ RendezvousFunnelProcStart:: db 8ch, 0c8h ; mov ax, cs db 8eh, 0d8h ; mov ds, ax db 8eh, 0c0h ; mov es, ax - db 8eh, 0d0h ; mov ss, ax + db 8eh, 0d0h ; mov ss, ax db 33h, 0c0h ; xor ax, ax db 8eh, 0e0h ; mov fs, ax db 8eh, 0e8h ; mov gs, ax @@ -67,10 +67,10 @@ flat32Start:: dw IdtrProfile ; mov si, IdtrProfile db 66h ; db 66h db 2Eh, 0Fh, 01h, 1Ch ; lidt fword ptr cs:[si] - + db 33h, 0C0h ; xor ax, ax db 8Eh, 0D8h ; mov ds, ax - + db 0Fh, 20h, 0C0h ; mov eax, cr0 ; Get control register 0 db 66h, 83h, 0C8h, 01h ; or eax, 000000001h ; Set PE bit (bit #0) db 0Fh, 22h, 0C0h ; mov cr0, eax @@ -133,12 +133,12 @@ Releaselock:: test eax, eax jz GoToSleep call eax ; Call C function - + GoToSleep:: cli hlt jmp $-2 - + RendezvousFunnelProc ENDP RendezvousFunnelProcEnd:: ;------------------------------------------------------------------------------------- @@ -148,16 +148,16 @@ AsmGetAddressMap PROC near C PUBLIC pushad mov ebp,esp - + mov ebx, dword ptr [ebp+24h] mov dword ptr [ebx], RendezvousFunnelProcStart mov dword ptr [ebx+4h], PMODE_ENTRY - RendezvousFunnelProcStart mov dword ptr [ebx+8h], FLAT32_JUMP - RendezvousFunnelProcStart mov dword ptr [ebx+0ch], RendezvousFunnelProcEnd - RendezvousFunnelProcStart - + popad ret - + AsmGetAddressMap ENDP END diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/SmiEntry.S b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/SmiEntry.S index f2f81a1991..8038cd2203 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/SmiEntry.S +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/SmiEntry.S @@ -82,7 +82,7 @@ ASM_PFX(gSmbase): .space 4 .space 2 _GdtDesc: .space 4 .space 2 -Start32bit: +Start32bit: leal DSC_OFFSET(%edi),%ebx movw DSC_DS(%ebx),%ax movl %eax,%ds @@ -118,7 +118,7 @@ L1: popl %ebp movl $0x80000001, %eax cpuid - btl $29, %edx # check cpuid to identify X64 or IA32 + btl $29, %edx # check cpuid to identify X64 or IA32 leal (0x7fc8 - (L1 - _SmiEntryPoint))(%ebp), %edi leal 4(%edi), %esi jnc L2 @@ -132,7 +132,7 @@ L7: L3: pushl (%esp) - + movl $ASM_PFX(SmiRendezvous), %eax call *%eax popl %ecx diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm index 3bd34376f8..f132627d6b 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm @@ -121,7 +121,7 @@ gSmiStack DD ? pop ebp mov eax, 80000001h cpuid - bt edx, 29 ; check cpuid to identify X64 or IA32 + bt edx, 29 ; check cpuid to identify X64 or IA32 lea edi, [ebp - (@1 - _SmiEntryPoint) + 7fc8h] lea esi, [edi + 4] jnc @2 @@ -134,14 +134,14 @@ gSmiStack DD ? mov dr7, edx ; restore DR6 & DR7 before running C code @3: mov ecx, [esp] ; CPU Index - + push ecx mov eax, SmiRendezvous call eax pop ecx cmp FeaturePcdGet (PcdCpuSmmDebug), 0 - jz @4 + jz @4 mov ecx, dr6 mov edx, dr7 diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/SmiException.S b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/SmiException.S index 4650437d71..76e2cf9ff7 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/SmiException.S +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/SmiException.S @@ -24,7 +24,7 @@ ASM_GLOBAL ASM_PFX(gSavedDebugExceptionIdtEntry) ASM_GLOBAL ASM_PFX(FeaturePcdGet (PcdCpuSmmProfileEnable)) ASM_GLOBAL ASM_PFX(InitializeSmmExternalVectorTablePtr) - .data + .data NullSeg: .quad 0 .quad 0 # reserved for future use @@ -436,16 +436,16 @@ ExternalVectorTablePtr: .long 0 # Saved IDT Entry for Page Fault # ASM_PFX(gSavedPageFaultIdtEntry): - .long 0 - .long 0 + .long 0 + .long 0 # # Saved IDT Entry for INT 1 # ASM_PFX(gSavedDebugExceptionIdtEntry): - .long 0 - .long 0 - + .long 0 + .long 0 + .text ASM_PFX(InitializeSmmExternalVectorTablePtr): @@ -917,7 +917,7 @@ PFHandlerEntry: # Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTEXT_IA32 # is 16-byte aligned # - andl $0xfffffff0, %esp + andl $0xfffffff0, %esp subl $12, %esp ## UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax; @@ -1120,7 +1120,7 @@ ASM_PFX(InitializeIDT): .long IDT_SIZE / 8 lea _SmiExceptionHandlers - 8, %ebx popl %ecx -L1: +L1: leal (%ebx,%ecx,8),%eax movw %ax,(%edx,%ecx,8) shrl $16,%eax @@ -1155,10 +1155,10 @@ L2: cmpb $0, ASM_PFX(FeaturePcdGet (PcdCpuSmmProfileEnable)) jz L3 - + # # Save INT 1 IDT entry in gSavedDebugExceptionIdtEntry -# +# leal _SmiIDT + 1 * 8, %ebx leal ASM_PFX(gSavedDebugExceptionIdtEntry), %edx movl (%ebx), %eax diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/SmiException.asm b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/SmiException.asm index 33b4d8387f..b548b60bf1 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/SmiException.asm +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/SmiException.asm @@ -276,7 +276,7 @@ gSavedPageFaultIdtEntry LABEL DWORD gSavedDebugExceptionIdtEntry LABEL DWORD DD 0 DD 0 - + .code diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c index fbca8c4afe..a473dd9127 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c @@ -64,3 +64,4 @@ RestorePageTableAbove4G ( ) { } + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.h index e41949563c..601373785b 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.h @@ -96,3 +96,4 @@ InitPagesForPFHandler ( ); #endif // _SMM_PROFILE_ARCH_H_ + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/MpService.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/MpService.c index 76fd20dc1b..3ee896ccee 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/MpService.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/MpService.c @@ -1757,3 +1757,4 @@ SmmCpuSync2SendSmiAllExcludingSelf ( SendSmiIpiAllExcludingSelf(); return EFI_SUCCESS; } + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c index d4ab88dff8..1d61307d91 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -1594,3 +1594,4 @@ PerformRemainingTasks ( mSmmReadyToLock = FALSE; } } + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h index 39c7ba5049..ab2489aa8e 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -778,3 +778,4 @@ PerformRemainingTasks ( ); #endif + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf index fd497ac2b8..ccef8cacd4 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf @@ -83,7 +83,7 @@ MdeModulePkg/MdeModulePkg.dec UefiCpuPkg/UefiCpuPkg.dec IntelFrameworkPkg/IntelFrameworkPkg.dec - BraswellPlatformPkg/BraswellPlatformPkg.dec + BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/IntelSiliconBasic.dec [LibraryClasses] UefiDriverEntryPoint @@ -193,3 +193,4 @@ [Depex] gEfiMpServiceProtocolGuid + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/SmmFeatures.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/SmmFeatures.h index 2eabc82e50..5b124030cc 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/SmmFeatures.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/SmmFeatures.h @@ -218,3 +218,4 @@ SmmWriteReg64 ( ); #endif + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/SmmProfile.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/SmmProfile.c index b781d2032b..0af6660fb2 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/SmmProfile.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/SmmProfile.c @@ -1367,3 +1367,4 @@ InitIdtr ( { SmmRegisterExceptionHandler (&mSmmCpuService, EXCEPT_IA32_DEBUG, DebugExceptionHandler); } + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/SmmProfile.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/SmmProfile.h index 0c5411b7ba..4d348eacd9 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/SmmProfile.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/SmmProfile.h @@ -74,3 +74,4 @@ SmmProfileStart ( ); #endif // _SMM_PROFILE_H_ + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/SmmProfileInternal.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/SmmProfileInternal.h index 7403c4fc46..fbb53afa0f 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/SmmProfileInternal.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/SmmProfileInternal.h @@ -188,3 +188,4 @@ SmiDefaultPFHandler ( ); #endif // _SMM_PROFILE_H_ + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/SyncTimer.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/SyncTimer.c index a2c2f1e75b..1a426f5ff3 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/SyncTimer.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/SyncTimer.c @@ -109,3 +109,4 @@ IsSyncTimerTimeout ( return (BOOLEAN) (Delta >= mTimeoutTicker); } + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/X64/MpFuncs.asm b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/X64/MpFuncs.asm index f0a0bc3f89..db45a06c60 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/X64/MpFuncs.asm +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/X64/MpFuncs.asm @@ -39,7 +39,7 @@ Cr3OffsetLocation equ LockLocation + 38h ;text SEGMENT .code -RendezvousFunnelProc PROC +RendezvousFunnelProc PROC RendezvousFunnelProcStart:: ; At this point CS = 0x(vv00) and ip= 0x0. @@ -47,7 +47,7 @@ RendezvousFunnelProcStart:: db 8ch, 0c8h ; mov ax, cs db 8eh, 0d8h ; mov ds, ax db 8eh, 0c0h ; mov es, ax - db 8eh, 0d0h ; mov ss, ax + db 8eh, 0d0h ; mov ss, ax db 33h, 0c0h ; xor ax, ax db 8eh, 0e0h ; mov fs, ax db 8eh, 0e8h ; mov gs, ax @@ -61,7 +61,7 @@ flat32Start:: db 0BEh dw Cr3OffsetLocation ; mov si, Cr3Location db 66h, 8Bh, 0Ch ; mov ecx,dword ptr [si] ; ECX is keeping the value of CR3 - + db 0BEh dw GdtrLocation ; mov si, GdtrProfile db 66h ; db 66h @@ -71,10 +71,10 @@ flat32Start:: dw IdtrLocation ; mov si, IdtrProfile db 66h ; db 66h db 2Eh, 0Fh, 01h, 1Ch ; lidt fword ptr cs:[si] - + db 33h, 0C0h ; xor ax, ax db 8Eh, 0D8h ; mov ds, ax - + db 0Fh, 20h, 0C0h ; mov eax, cr0 ; Get control register 0 db 66h, 83h, 0C8h, 01h ; or eax, 000000001h ; Set PE bit (bit #0) db 0Fh, 22h, 0C0h ; mov cr0, eax @@ -99,25 +99,25 @@ NemInit:: ; protected mode entry point db 0Fh, 22h, 0E0h ; mov cr4, eax db 0Fh, 22h, 0D9h ; mov cr3, ecx - + db 8Bh, 0F2h ; mov esi, edx ; Save wakeup buffer address - + db 0B9h dd 0C0000080h ; mov ecx, 0c0000080h ; EFER MSR number. db 0Fh, 32h ; rdmsr ; Read EFER. db 0Fh, 0BAh, 0E8h, 08h ; bts eax, 8 ; Set LME=1. db 0Fh, 30h ; wrmsr ; Write EFER. - + db 0Fh, 20h, 0C0h ; mov eax, cr0 ; Read CR0. db 0Fh, 0BAh, 0E8h, 1Fh ; bts eax, 31 ; Set PG=1. db 0Fh, 22h, 0C0h ; mov cr0, eax ; Write CR0. LONG_JUMP:: - + db 67h, 0EAh ; far jump dd 0h ; 32-bit offset dw 38h ; 16-bit selector - + LongModeStart:: mov ax, 30h @@ -172,12 +172,12 @@ Releaselock:: sub rsp, 20h call rax add rsp, 20h - + GoToSleep:: cli hlt jmp $-2 - + RendezvousFunnelProcEnd:: RendezvousFunnelProc ENDP @@ -186,7 +186,7 @@ RendezvousFunnelProc ENDP ; AsmGetAddressMap (&AddressMap); ;------------------------------------------------------------------------------------- ; comments here for definition of address map -AsmGetAddressMap PROC +AsmGetAddressMap PROC mov rax, offset RendezvousFunnelProcStart mov qword ptr [rcx], rax mov qword ptr [rcx+8h], NemInit - RendezvousFunnelProcStart @@ -195,7 +195,7 @@ AsmGetAddressMap PROC mov qword ptr [rcx+20h], LongModeStart - RendezvousFunnelProcStart mov qword ptr [rcx+28h], LONG_JUMP - RendezvousFunnelProcStart ret - + AsmGetAddressMap ENDP END diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/X64/SmiEntry.asm b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/X64/SmiEntry.asm index 7e174b2373..766891eff6 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/X64/SmiEntry.asm +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/X64/SmiEntry.asm @@ -202,7 +202,7 @@ gSmiStack DQ ? sub rsp, 208h DB 48h ; FXSAVE64 fxsave [rsp] - + add rsp, -20h call rax add rsp, 20h @@ -211,8 +211,8 @@ gSmiStack DQ ? ; Restore FP registers ; DB 48h ; FXRSTOR64 - fxrstor [rsp] - + fxrstor [rsp] + mov rax, offset FeaturePcdGet (PcdCpuSmmDebug) ;Get absolute address. Avoid RIP relative addressing cmp byte ptr [rax], 0 jz @2 diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/X64/SmiException.S b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/X64/SmiException.S index e786a4395d..dd91e1a9d4 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/X64/SmiException.S +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/X64/SmiException.S @@ -357,16 +357,16 @@ _SmiIDTEnd: # Saved IDT Entry for Page Fault # ASM_PFX(gSavedPageFaultIdtEntry): - .quad 0 - .quad 0 + .quad 0 + .quad 0 # # Saved IDT Entry for INT 1 # ASM_PFX(gSavedDebugExceptionIdtEntry): - .quad 0 - .quad 0 - + .quad 0 + .quad 0 + ExternalVectorTablePtr: .quad 0 # point to the external interrupt vector table # @@ -550,7 +550,7 @@ L1: # Since here the stack pointer is 16-byte aligned, so # EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64 # is 16-byte aligned - # + # ## UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax; ## UINT64 R8, R9, R10, R11, R12, R13, R14, R15; @@ -683,7 +683,7 @@ L5: ## UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; ## Skip restoration of DRx registers to support in-circuit emualators ## or debuggers set breakpoint in interrupt/exception context - addq $8 * 6, %rsp + addq $8 * 6, %rsp ## UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8; popq %rax @@ -758,7 +758,7 @@ L6: cmpq $1, 8(%rsp) jnz Done # Clear TF bit after INT1 handler runs - btcl $8, 40(%rsp) #RFLAGS + btcl $8, 40(%rsp) #RFLAGS Done: @@ -816,7 +816,7 @@ L3: movq (%rcx), %rax movq %rax, (%rdx) movq 8(%rcx), %rax - movq %rax, 8(%rdx) - + movq %rax, 8(%rdx) + L4: ret diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/X64/SmiException.asm b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/X64/SmiException.asm index 551f179848..31126d5c71 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/X64/SmiException.asm +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/X64/SmiException.asm @@ -158,15 +158,15 @@ IDT_SIZE = (offset _SmiIDTEnd - offset _SmiIDT) ; Saved IDT Entry for Page Fault ; gSavedPageFaultIdtEntry LABEL QWORD - DQ 0 - DQ 0 + DQ 0 + DQ 0 ; ; Saved IDT Entry for INT 1 ; gSavedDebugExceptionIdtEntry LABEL QWORD - DQ 0 - DQ 0 + DQ 0 + DQ 0 ExternalVectorTablePtr QWORD 0 ; point to the external interrupt vector table @@ -179,7 +179,7 @@ _PFLOCK DB 0 .code -InitializeSmmExternalVectorTablePtr PROC +InitializeSmmExternalVectorTablePtr PROC mov ExternalVectorTablePtr, rcx ret InitializeSmmExternalVectorTablePtr ENDP @@ -231,7 +231,7 @@ IHDLRIDX = IHDLRIDX + 1 ; Since here the stack pointer is 16-byte aligned, so ; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64 ; is 16-byte aligned - ; + ; ;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax; ;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15; @@ -330,7 +330,7 @@ IHDLRIDX = IHDLRIDX + 1 ;; call into exception handler mov rcx, [rbp + 8] mov rax, ExternalVectorTablePtr ; get the interrupt vectors base - mov rax, [rax + rcx * 8] + mov rax, [rax + rcx * 8] or rax, rax ; NULL? je nonNullValue; @@ -439,7 +439,7 @@ nonNullValue: cmp qword ptr [rsp + 8], 1 jnz @Done ; Clear TF bit after INT1 handler runs - btc dword ptr [rsp + 40], 8 ;RFLAGS + btc dword ptr [rsp + 40], 8 ;RFLAGS @Done: @@ -497,7 +497,7 @@ InitializeIDT PROC mov [rdx], rax mov rax, [rcx + 8] mov [rdx + 8], rax -@@: +@@: ret InitializeIDT ENDP diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/X64/SmmInit.asm b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/X64/SmmInit.asm index b5724d53c6..889d873143 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/X64/SmmInit.asm +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/X64/SmmInit.asm @@ -82,7 +82,7 @@ gSmmInitStack DQ ? movdqa [rsp + 40h], xmm4 movdqa [rsp + 50h], xmm5 - add rsp, -20h + add rsp, -20h call SmmInitHandler add rsp, 20h @@ -94,7 +94,7 @@ gSmmInitStack DQ ? movdqa xmm2, [rsp + 20h] movdqa xmm3, [rsp + 30h] movdqa xmm4, [rsp + 40h] - movdqa xmm5, [rsp + 50h] + movdqa xmm5, [rsp + 50h] rsm SmmStartup ENDP diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/X64/SmmProfileArch.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/X64/SmmProfileArch.c index 535ee7f231..72d1cc4529 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/X64/SmmProfileArch.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/X64/SmmProfileArch.c @@ -300,3 +300,4 @@ RestorePageTableAbove4G ( return; } + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/X64/SmmProfileArch.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/X64/SmmProfileArch.h index ea43d143a6..428612c900 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/X64/SmmProfileArch.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/PiSmmCpuDxeSmm/X64/SmmProfileArch.h @@ -104,3 +104,4 @@ InitPagesForPFHandler ( ); #endif // _SMM_PROFILE_ARCH_H_ + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/SerialDxe/SerialDxe.inf b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/SerialDxe/SerialDxe.inf new file mode 100644 index 0000000000..e8da682183 --- /dev/null +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/SerialDxe/SerialDxe.inf @@ -0,0 +1,53 @@ +## @file +# Serial driver that layers on top of a Serial Port Library instance. +# +# Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.
+# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SerialDxe + FILE_GUID = D3987D4B-971A-435F-8CAF-4967EB627241 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = SerialDxeInitialize + +[Sources.common] + SerialIo.c + +[Packages] + MdePkg/MdePkg.dec + BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/IntelSiliconBasic.dec + BraswellPlatformPkg/BraswellPlatformPkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + UefiBootServicesTableLib + DebugLib + PcdLib + SerialPortLib + +[Protocols] + gEfiSerialIoProtocolGuid ## PRODUCES + gEfiDevicePathProtocolGuid ## PRODUCES + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits ## CONSUMES + gIntelSiBasicPkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth ## CONSUMES + +[Depex] + TRUE + diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/SerialDxe/SerialIo.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/SerialDxe/SerialIo.c new file mode 100644 index 0000000000..2db5e4687b --- /dev/null +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/SerialDxe/SerialIo.c @@ -0,0 +1,555 @@ +/** @file + Serial driver that layers on top of a Serial Port Library instance. + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Copyright (c) 2013-2014, ARM Ltd. All rights reserved.
+ Copyright (c) 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include + +typedef struct { + UART_DEVICE_PATH Uart; + EFI_DEVICE_PATH_PROTOCOL End; +} SERIAL_DEVICE_PATH; + +/** + Reset the serial device. + + @param This Protocol instance pointer. + + @retval EFI_SUCCESS The device was reset. + @retval EFI_DEVICE_ERROR The serial device could not be reset. + +**/ +EFI_STATUS +EFIAPI +SerialReset ( + IN EFI_SERIAL_IO_PROTOCOL *This + ); + +/** + Sets the baud rate, receive FIFO depth, transmit/receive time out, parity, + data bits, and stop bits on a serial device. + + @param This Protocol instance pointer. + @param BaudRate The requested baud rate. A BaudRate value of 0 will use the the + device's default interface speed. + @param ReceiveFifoDepth The requested depth of the FIFO on the receive side of the + serial interface. A ReceiveFifoDepth value of 0 will use + the device's default FIFO depth. + @param Timeout The requested time out for a single character in microseconds. + This timeout applies to both the transmit and receive side of the + interface. A Timeout value of 0 will use the device's default time + out value. + @param Parity The type of parity to use on this serial device. A Parity value of + DefaultParity will use the device's default parity value. + @param DataBits The number of data bits to use on the serial device. A DataBits + value of 0 will use the device's default data bit setting. + @param StopBits The number of stop bits to use on this serial device. A StopBits + value of DefaultStopBits will use the device's default number of + stop bits. + + @retval EFI_SUCCESS The device was reset. + @retval EFI_DEVICE_ERROR The serial device could not be reset. + +**/ +EFI_STATUS +EFIAPI +SerialSetAttributes ( + IN EFI_SERIAL_IO_PROTOCOL *This, + IN UINT64 BaudRate, + IN UINT32 ReceiveFifoDepth, + IN UINT32 Timeout, + IN EFI_PARITY_TYPE Parity, + IN UINT8 DataBits, + IN EFI_STOP_BITS_TYPE StopBits + ); + +/** + Set the control bits on a serial device + + @param This Protocol instance pointer. + @param Control Set the bits of Control that are settable. + + @retval EFI_SUCCESS The new control bits were set on the serial device. + @retval EFI_UNSUPPORTED The serial device does not support this operation. + @retval EFI_DEVICE_ERROR The serial device is not functioning correctly. + +**/ +EFI_STATUS +EFIAPI +SerialSetControl ( + IN EFI_SERIAL_IO_PROTOCOL *This, + IN UINT32 Control + ); + +/** + Retrieves the status of the control bits on a serial device + + @param This Protocol instance pointer. + @param Control A pointer to return the current Control signals from the serial device. + + @retval EFI_SUCCESS The control bits were read from the serial device. + @retval EFI_DEVICE_ERROR The serial device is not functioning correctly. + +**/ +EFI_STATUS +EFIAPI +SerialGetControl ( + IN EFI_SERIAL_IO_PROTOCOL *This, + OUT UINT32 *Control + ); + +/** + Writes data to a serial device. + + @param This Protocol instance pointer. + @param BufferSize On input, the size of the Buffer. On output, the amount of + data actually written. + @param Buffer The buffer of data to write + + @retval EFI_SUCCESS The data was written. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_TIMEOUT The data write was stopped due to a timeout. + +**/ +EFI_STATUS +EFIAPI +SerialWrite ( + IN EFI_SERIAL_IO_PROTOCOL *This, + IN OUT UINTN *BufferSize, + IN VOID *Buffer + ); + +#define EFI_DEBUG_AGENT_GUID \ + { \ + 0x865a5a9b, 0xb85d, 0x474c, { 0x84, 0x55, 0x65, 0xd1, 0xbe, 0x84, 0x4b, 0xe2 } \ + } + +/** + Reads data from a serial device. + + @param This Protocol instance pointer. + @param BufferSize On input, the size of the Buffer. On output, the amount of + data returned in Buffer. + @param Buffer The buffer to return the data into. + + @retval EFI_SUCCESS The data was read. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_TIMEOUT The data write was stopped due to a timeout. + +**/ +EFI_STATUS +EFIAPI +SerialRead ( + IN EFI_SERIAL_IO_PROTOCOL *This, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer + ); + +EFI_HANDLE mSerialHandle = NULL; + +/*{ + MESSAGING_DEVICE_PATH, + MSG_UART_DP, + (UINT8) (sizeof (UART_DEVICE_PATH)), + (UINT8) ((sizeof (UART_DEVICE_PATH)) >> 8), + 0, + 115200, // default BaudRate + 8, // default DataBits + 1, // default Parity + 1, // default StopBits + +},*/ + + +SERIAL_DEVICE_PATH mSerialDevicePath = { + { + { + MESSAGING_DEVICE_PATH, + MSG_UART_DP, + (UINT8) sizeof (UART_DEVICE_PATH), + (UINT8) (sizeof (UART_DEVICE_PATH) >> 8) + + }, + 0, + 115200, // default BaudRate + 8, // default DataBits + 1, // default Parity + 1, // default StopBits + +} , + + { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 } } + + + }; + + +// +// Template used to initialize the Serial IO protocols. +// +EFI_SERIAL_IO_MODE mSerialIoMode = { + // + // value field set in SerialDxeInitialize()? + //--------- ------------------- ----------------------------- + 0, // ControlMask + 1000 * 1000, // Timeout + 0, // BaudRate yes + 1, // ReceiveFifoDepth + 0, // DataBits yes + 0, // Parity yes + 0 // StopBits yes +}; + +EFI_SERIAL_IO_PROTOCOL mSerialIoTemplate = { + SERIAL_IO_INTERFACE_REVISION, + SerialReset, + SerialSetAttributes, + SerialSetControl, + SerialGetControl, + SerialWrite, + SerialRead, + &mSerialIoMode +}; + +/** + Reset the serial device. + + @param This Protocol instance pointer. + + @retval EFI_SUCCESS The device was reset. + @retval EFI_DEVICE_ERROR The serial device could not be reset. + +**/ +EFI_STATUS +EFIAPI +SerialReset ( + IN EFI_SERIAL_IO_PROTOCOL *This + ) +{ + EFI_STATUS Status; + EFI_TPL Tpl; + + Status = SerialPortInitialize (); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Set the Serial I/O mode and update the device path + // + + Tpl = gBS->RaiseTPL (TPL_NOTIFY); + + // + // Set the Serial I/O mode + // + This->Mode->ReceiveFifoDepth = PcdGet16 (PcdUartDefaultReceiveFifoDepth); + This->Mode->Timeout = 1000 * 1000; + This->Mode->BaudRate = PcdGet64 (PcdUartDefaultBaudRate); + This->Mode->DataBits = (UINT32) PcdGet8 (PcdUartDefaultDataBits); + This->Mode->Parity = (UINT32) PcdGet8 (PcdUartDefaultParity); + This->Mode->StopBits = (UINT32) PcdGet8 (PcdUartDefaultStopBits); + + // + // Check if the device path has actually changed + // + if (mSerialDevicePath.Uart.BaudRate == This->Mode->BaudRate && + mSerialDevicePath.Uart.DataBits == (UINT8) This->Mode->DataBits && + mSerialDevicePath.Uart.Parity == (UINT8) This->Mode->Parity && + mSerialDevicePath.Uart.StopBits == (UINT8) This->Mode->StopBits + ) { + gBS->RestoreTPL (Tpl); + return EFI_SUCCESS; + } + + // + // Update the device path + // + mSerialDevicePath.Uart.BaudRate = This->Mode->BaudRate; + mSerialDevicePath.Uart.DataBits = (UINT8) This->Mode->DataBits; + mSerialDevicePath.Uart.Parity = (UINT8) This->Mode->Parity; + mSerialDevicePath.Uart.StopBits = (UINT8) This->Mode->StopBits; + + Status = gBS->ReinstallProtocolInterface ( + mSerialHandle, + &gEfiDevicePathProtocolGuid, + &mSerialDevicePath, + &mSerialDevicePath + ); + + gBS->RestoreTPL (Tpl); + + return Status; +} + +/** + Sets the baud rate, receive FIFO depth, transmit/receive time out, parity, + data bits, and stop bits on a serial device. + + @param This Protocol instance pointer. + @param BaudRate The requested baud rate. A BaudRate value of 0 will use the the + device's default interface speed. + @param ReceiveFifoDepth The requested depth of the FIFO on the receive side of the + serial interface. A ReceiveFifoDepth value of 0 will use + the device's default FIFO depth. + @param Timeout The requested time out for a single character in microseconds. + This timeout applies to both the transmit and receive side of the + interface. A Timeout value of 0 will use the device's default time + out value. + @param Parity The type of parity to use on this serial device. A Parity value of + DefaultParity will use the device's default parity value. + @param DataBits The number of data bits to use on the serial device. A DataBits + value of 0 will use the device's default data bit setting. + @param StopBits The number of stop bits to use on this serial device. A StopBits + value of DefaultStopBits will use the device's default number of + stop bits. + + @retval EFI_SUCCESS The device was reset. + @retval EFI_DEVICE_ERROR The serial device could not be reset. + +**/ +EFI_STATUS +EFIAPI +SerialSetAttributes ( + IN EFI_SERIAL_IO_PROTOCOL *This, + IN UINT64 BaudRate, + IN UINT32 ReceiveFifoDepth, + IN UINT32 Timeout, + IN EFI_PARITY_TYPE Parity, + IN UINT8 DataBits, + IN EFI_STOP_BITS_TYPE StopBits + ) +{ + EFI_STATUS Status; + EFI_TPL Tpl; + + Status = SerialPortSetAttributes (&BaudRate, &ReceiveFifoDepth, &Timeout, &Parity, &DataBits, &StopBits); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Set the Serial I/O mode and update the device path + // + + Tpl = gBS->RaiseTPL (TPL_NOTIFY); + + // + // Set the Serial I/O mode + // + This->Mode->ReceiveFifoDepth = ReceiveFifoDepth; + This->Mode->Timeout = Timeout; + This->Mode->BaudRate = BaudRate; + This->Mode->DataBits = (UINT32) DataBits; + This->Mode->Parity = (UINT32) Parity; + This->Mode->StopBits = (UINT32) StopBits; + + // + // Check if the device path has actually changed + // + if (mSerialDevicePath.Uart.BaudRate == BaudRate && + mSerialDevicePath.Uart.DataBits == DataBits && + mSerialDevicePath.Uart.Parity == (UINT8) Parity && + mSerialDevicePath.Uart.StopBits == (UINT8) StopBits + ) { + gBS->RestoreTPL (Tpl); + return EFI_SUCCESS; + } + + // + // Update the device path + // + mSerialDevicePath.Uart.BaudRate = BaudRate; + mSerialDevicePath.Uart.DataBits = DataBits; + mSerialDevicePath.Uart.Parity = (UINT8) Parity; + mSerialDevicePath.Uart.StopBits = (UINT8) StopBits; + + Status = gBS->ReinstallProtocolInterface ( + mSerialHandle, + &gEfiDevicePathProtocolGuid, + &mSerialDevicePath, + &mSerialDevicePath + ); + + gBS->RestoreTPL (Tpl); + + return Status; +} + +/** + Set the control bits on a serial device + + @param This Protocol instance pointer. + @param Control Set the bits of Control that are settable. + + @retval EFI_SUCCESS The new control bits were set on the serial device. + @retval EFI_UNSUPPORTED The serial device does not support this operation. + @retval EFI_DEVICE_ERROR The serial device is not functioning correctly. + +**/ +EFI_STATUS +EFIAPI +SerialSetControl ( + IN EFI_SERIAL_IO_PROTOCOL *This, + IN UINT32 Control + ) +{ + return SerialPortSetControl (Control); +} + +/** + Retrieves the status of the control bits on a serial device + + @param This Protocol instance pointer. + @param Control A pointer to return the current Control signals from the serial device. + + @retval EFI_SUCCESS The control bits were read from the serial device. + @retval EFI_DEVICE_ERROR The serial device is not functioning correctly. + +**/ +EFI_STATUS +EFIAPI +SerialGetControl ( + IN EFI_SERIAL_IO_PROTOCOL *This, + OUT UINT32 *Control + ) +{ + + return SerialPortGetControl (Control); +} + +/** + Writes data to a serial device. + + @param This Protocol instance pointer. + @param BufferSize On input, the size of the Buffer. On output, the amount of + data actually written. + @param Buffer The buffer of data to write + + @retval EFI_SUCCESS The data was written. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_TIMEOUT The data write was stopped due to a timeout. + +**/ +EFI_STATUS +EFIAPI +SerialWrite ( + IN EFI_SERIAL_IO_PROTOCOL *This, + IN OUT UINTN *BufferSize, + IN VOID *Buffer + ) +{ + UINTN Count; + + Count = SerialPortWrite (Buffer, *BufferSize); + + if (Count != *BufferSize) { + *BufferSize = Count; + return EFI_TIMEOUT; + } + + return EFI_SUCCESS; +} + +/** + Reads data from a serial device. + + @param This Protocol instance pointer. + @param BufferSize On input, the size of the Buffer. On output, the amount of + data returned in Buffer. + @param Buffer The buffer to return the data into. + + @retval EFI_SUCCESS The data was read. + @retval EFI_DEVICE_ERROR The device reported an error. + @retval EFI_TIMEOUT The data write was stopped due to a timeout. + +**/ +EFI_STATUS +EFIAPI +SerialRead ( + IN EFI_SERIAL_IO_PROTOCOL *This, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer + ) +{ + UINTN Count; + + Count = 0; + + if (SerialPortPoll ()) { + Count = SerialPortRead (Buffer, *BufferSize); + } + + if (Count != *BufferSize) { + *BufferSize = Count; + return EFI_TIMEOUT; + } + + return EFI_SUCCESS; +} + +/** + Initialization for the Serial Io Protocol. + + @param[in] ImageHandle The firmware allocated handle for the EFI image. + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + @retval other Some error occurs when executing this entry point. + +**/ +EFI_STATUS +EFIAPI +SerialDxeInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + Status = SerialPortInitialize (); + if (EFI_ERROR (Status)) { + return Status; + } + + mSerialIoMode.BaudRate = PcdGet64 (PcdUartDefaultBaudRate); + mSerialIoMode.DataBits = (UINT32) PcdGet8 (PcdUartDefaultDataBits); + mSerialIoMode.Parity = (UINT32) PcdGet8 (PcdUartDefaultParity); + mSerialIoMode.StopBits = (UINT32) PcdGet8 (PcdUartDefaultStopBits); + mSerialIoMode.ReceiveFifoDepth = PcdGet16 (PcdUartDefaultReceiveFifoDepth); + mSerialDevicePath.Uart.BaudRate = PcdGet64 (PcdUartDefaultBaudRate); + mSerialDevicePath.Uart.DataBits = PcdGet8 (PcdUartDefaultDataBits); + mSerialDevicePath.Uart.Parity = PcdGet8 (PcdUartDefaultParity); + mSerialDevicePath.Uart.StopBits = PcdGet8 (PcdUartDefaultStopBits); + + // + // Make a new handle with Serial IO protocol and its device path on it. + // + Status = gBS->InstallMultipleProtocolInterfaces ( + &mSerialHandle, + &gEfiSerialIoProtocolGuid, &mSerialIoTemplate, + &gEfiDevicePathProtocolGuid, &mSerialDevicePath, + NULL + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} + -- cgit v1.2.3