From 84a773d18bb2d021d760374dafce347a6908b4a4 Mon Sep 17 00:00:00 2001 From: rsun3 Date: Tue, 7 Sep 2010 10:23:05 +0000 Subject: Rename two files to follow the file naming convention. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10853 6f19259b-4bc3-4df7-8a09-765794883524 --- .../ResetVector/Vtf0/Ia16/Real16ToFlat32.asm | 133 +++++++++++++++++++++ .../ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm | 46 +++++++ UefiCpuPkg/ResetVector/Vtf0/Makefile | 6 +- UefiCpuPkg/ResetVector/Vtf0/ResetVectorCode.asm | 6 +- 4 files changed, 185 insertions(+), 6 deletions(-) create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm new file mode 100644 index 0000000000..146df600a6 --- /dev/null +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm @@ -0,0 +1,133 @@ +;------------------------------------------------------------------------------ +; @file +; Transition from 16 bit real mode into 32 bit flat protected mode +; +; Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.
+; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;------------------------------------------------------------------------------ + +%define SEC_DEFAULT_CR0 0x40000023 +%define SEC_DEFAULT_CR4 0x640 + +BITS 16 + +; +; Modified: EAX, EBX +; +TransitionFromReal16To32BitFlat: + + debugShowPostCode POSTCODE_16BIT_MODE + + cli + + mov bx, 0xf000 + mov ds, bx + + mov bx, ADDR16_OF(gdtr) + +o32 lgdt [cs:bx] + + mov eax, SEC_DEFAULT_CR0 + mov cr0, eax + + jmp LINEAR_CODE_SEL:dword ADDR_OF(jumpTo32BitAndLandHere) +BITS 32 +jumpTo32BitAndLandHere: + + mov eax, SEC_DEFAULT_CR4 + mov cr4, eax + + debugShowPostCode POSTCODE_32BIT_MODE + + mov ax, LINEAR_SEL + mov ds, ax + mov es, ax + mov fs, ax + mov gs, ax + mov ss, ax + + OneTimeCallRet TransitionFromReal16To32BitFlat + +ALIGN 2 + +gdtr: + dw GDT_END - GDT_BASE - 1 ; GDT limit + dd ADDR_OF(GDT_BASE) + +ALIGN 16 + +; +; Macros for GDT entries +; + +%define PRESENT_FLAG(p) (p << 7) +%define DPL(dpl) (dpl << 5) +%define SYSTEM_FLAG(s) (s << 4) +%define DESC_TYPE(t) (t) + +; Type: data, expand-up, writable, accessed +%define DATA32_TYPE 3 + +; Type: execute, readable, expand-up, accessed +%define CODE32_TYPE 0xb + +; Type: execute, readable, expand-up, accessed +%define CODE64_TYPE 0xb + +%define GRANULARITY_FLAG(g) (g << 7) +%define DEFAULT_SIZE32(d) (d << 6) +%define CODE64_FLAG(l) (l << 5) +%define UPPER_LIMIT(l) (l) + +; +; The Global Descriptor Table (GDT) +; + +GDT_BASE: +; null descriptor +NULL_SEL equ $-GDT_BASE + DW 0 ; limit 15:0 + DW 0 ; base 15:0 + DB 0 ; base 23:16 + DB 0 ; sys flag, dpl, type + DB 0 ; limit 19:16, flags + DB 0 ; base 31:24 + +; linear data segment descriptor +LINEAR_SEL equ $-GDT_BASE + DW 0xffff ; limit 15:0 + DW 0 ; base 15:0 + DB 0 ; base 23:16 + DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(DATA32_TYPE) + DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(1)|CODE64_FLAG(0)|UPPER_LIMIT(0xf) + DB 0 ; base 31:24 + +; linear code segment descriptor +LINEAR_CODE_SEL equ $-GDT_BASE + DW 0xffff ; limit 15:0 + DW 0 ; base 15:0 + DB 0 ; base 23:16 + DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(CODE32_TYPE) + DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(1)|CODE64_FLAG(0)|UPPER_LIMIT(0xf) + DB 0 ; base 31:24 + +%ifdef ARCH_X64 +; linear code (64-bit) segment descriptor +LINEAR_CODE64_SEL equ $-GDT_BASE + DW 0xffff ; limit 15:0 + DW 0 ; base 15:0 + DB 0 ; base 23:16 + DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(CODE64_TYPE) + DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(0)|CODE64_FLAG(1)|UPPER_LIMIT(0xf) + DB 0 ; base 31:24 +%endif + +GDT_END: + diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm new file mode 100644 index 0000000000..9eba864c28 --- /dev/null +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm @@ -0,0 +1,46 @@ +;------------------------------------------------------------------------------ +; @file +; Transition from 32 bit flat protected mode into 64 bit flat protected mode +; +; Copyright (c) 2008 - 2009, Intel Corporation. All rights reserved.
+; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;------------------------------------------------------------------------------ + +BITS 32 + +; +; Modified: EAX +; +Transition32FlatTo64Flat: + + mov eax, ((ADDR_OF_START_OF_RESET_CODE & ~0xfff) - 0x1000) + mov cr3, eax + + mov eax, cr4 + bts eax, 5 ; enable PAE + mov cr4, eax + + mov ecx, 0xc0000080 + rdmsr + bts eax, 8 ; set LME + wrmsr + + mov eax, cr0 + bts eax, 31 ; set PG + mov cr0, eax ; enable paging + + jmp LINEAR_CODE64_SEL:ADDR_OF(jumpTo64BitAndLandHere) +BITS 64 +jumpTo64BitAndLandHere: + + debugShowPostCode POSTCODE_64BIT_MODE + + OneTimeCallRet Transition32FlatTo64Flat + diff --git a/UefiCpuPkg/ResetVector/Vtf0/Makefile b/UefiCpuPkg/ResetVector/Vtf0/Makefile index bc21d71753..3882da40cd 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Makefile +++ b/UefiCpuPkg/ResetVector/Vtf0/Makefile @@ -1,7 +1,7 @@ ## @file # Makefile to create FFS Raw sections for VTF images. # -# Copyright (c) 2008, Intel Corporation. All rights reserved.
+# Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.
# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -16,8 +16,8 @@ TARGETS = Bin/ResetVector.ia32.raw Bin/ResetVector.x64.raw ASM = nasm COMMON_DEPS = \ - Ia16/16RealTo32Flat.asm \ - Ia32/32FlatTo64Flat.asm \ + Ia16/Real16ToFlat32.asm \ + Ia32/Flat32ToFlat64.asm \ JumpToSec.asm \ Ia16/ResetVectorVtf0.asm \ Ia32/SearchForBfvBase.asm \ diff --git a/UefiCpuPkg/ResetVector/Vtf0/ResetVectorCode.asm b/UefiCpuPkg/ResetVector/Vtf0/ResetVectorCode.asm index a0afbf02d2..96f686b0e6 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/ResetVectorCode.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/ResetVectorCode.asm @@ -2,7 +2,7 @@ ; @file ; This file includes all other code files to assemble the reset vector code ; -; Copyright (c) 2008 - 2009, Intel Corporation. All rights reserved.
+; Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.
; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BSD License ; which accompanies this distribution. The full text of the license may be found at @@ -40,10 +40,10 @@ %include "Ia32/SearchForSecEntry.asm" %ifdef ARCH_X64 -%include "Ia32/32FlatTo64Flat.asm" +%include "Ia32/Flat32ToFlat64.asm" %endif -%include "Ia16/16RealTo32Flat.asm" +%include "Ia16/Real16ToFlat32.asm" %include "Ia16/Init16.asm" %include "Main.asm" -- cgit v1.2.3