From 8b18cc02068d854c7ffeecfe5e0574de429e9395 Mon Sep 17 00:00:00 2001 From: Guo Mang Date: Wed, 3 Aug 2016 13:57:27 +0800 Subject: BraswellPlatformPkg: Restructure code in Board directory Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang Reviewed-by: David Wei --- BraswellPlatformPkg/Board/BraswellCR/Acpi/Acpi.c | 1 + .../Board/BraswellCR/Acpi/Device/Camera/Camera.asl | 28 +- .../BraswellCR/Acpi/Device/Camera/Camera2.asl | 26 +- BraswellPlatformPkg/Board/BraswellCR/Acpi/Ssdt.asl | 6 +- .../Board/BraswellCR/BoardInit/BoardGpios.c | 344 ++++++ .../Board/BraswellCR/BoardInit/BoardGpios.h | 133 +-- .../Board/BraswellCR/BoardInit/BoardInit.c | 308 +---- .../Board/BraswellCR/BoardInit/BoardInit.h | 37 + .../Board/BraswellCR/BoardInit/BoardInit.inf | 9 +- .../Board/BraswellCR/BoardInit/BoardInitLate.c | 73 -- .../Board/BraswellCR/BoardInit/BoardInitLate.inf | 51 - .../BraswellCR/BoardInit/BraswellCRInitExtra.uni | 18 - .../BoardInit/BraswellCRInitLateExtra.uni | 18 - .../Board/BraswellCR/BoardInit/Dram.h | 82 ++ .../Board/BraswellCherryHill/Acpi/Acpi.c | 1 + .../Acpi/Device/Camera/Camera.asl | 28 +- .../Acpi/Device/Camera/Camera2.asl | 26 +- .../Board/BraswellCherryHill/Acpi/Ssdt.asl | 8 +- .../BraswellCherryHill/BoardInit/BoardGpios.c | 433 +++++++ .../BraswellCherryHill/BoardInit/BoardGpios.h | 152 +-- .../Board/BraswellCherryHill/BoardInit/BoardInit.c | 1191 +------------------- .../Board/BraswellCherryHill/BoardInit/BoardInit.h | 37 + .../BraswellCherryHill/BoardInit/BoardInit.inf | 19 +- .../BraswellCherryHill/BoardInit/BoardInitLate.c | 69 -- .../BraswellCherryHill/BoardInit/BoardInitLate.inf | 52 - .../BoardInit/BraswellCherryHillInitExtra.uni | 18 - .../BoardInit/BraswellCherryHillInitLateExtra.uni | 18 - .../Board/BraswellCherryHill/BoardInit/Dram.h | 0 .../Board/WesternDigital/BoardInit/BoardGpios.c | 440 ++++++++ .../Board/WesternDigital/BoardInit/BoardGpios.h | 145 +-- .../Board/WesternDigital/BoardInit/BoardInit.c | 356 +----- .../Board/WesternDigital/BoardInit/BoardInit.h | 37 + .../Board/WesternDigital/BoardInit/BoardInit.inf | 17 + .../Board/WesternDigital/BoardInit/BoardInitLate.c | 71 -- .../WesternDigital/BoardInit/BoardInitLate.inf | 53 - .../Board/WesternDigital/BoardInit/Dram.h | 94 ++ 36 files changed, 1794 insertions(+), 2605 deletions(-) create mode 100644 BraswellPlatformPkg/Board/BraswellCR/BoardInit/BoardGpios.c create mode 100644 BraswellPlatformPkg/Board/BraswellCR/BoardInit/BoardInit.h delete mode 100644 BraswellPlatformPkg/Board/BraswellCR/BoardInit/BoardInitLate.c delete mode 100644 BraswellPlatformPkg/Board/BraswellCR/BoardInit/BoardInitLate.inf delete mode 100644 BraswellPlatformPkg/Board/BraswellCR/BoardInit/BraswellCRInitExtra.uni delete mode 100644 BraswellPlatformPkg/Board/BraswellCR/BoardInit/BraswellCRInitLateExtra.uni create mode 100644 BraswellPlatformPkg/Board/BraswellCR/BoardInit/Dram.h create mode 100644 BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardGpios.c create mode 100644 BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInit.h delete mode 100644 BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInitLate.c delete mode 100644 BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInitLate.inf delete mode 100644 BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BraswellCherryHillInitExtra.uni delete mode 100644 BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BraswellCherryHillInitLateExtra.uni create mode 100644 BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/Dram.h create mode 100644 BraswellPlatformPkg/Board/WesternDigital/BoardInit/BoardGpios.c create mode 100644 BraswellPlatformPkg/Board/WesternDigital/BoardInit/BoardInit.h delete mode 100644 BraswellPlatformPkg/Board/WesternDigital/BoardInit/BoardInitLate.c delete mode 100644 BraswellPlatformPkg/Board/WesternDigital/BoardInit/BoardInitLate.inf create mode 100644 BraswellPlatformPkg/Board/WesternDigital/BoardInit/Dram.h diff --git a/BraswellPlatformPkg/Board/BraswellCR/Acpi/Acpi.c b/BraswellPlatformPkg/Board/BraswellCR/Acpi/Acpi.c index 12375b4121..92c11bd21f 100644 --- a/BraswellPlatformPkg/Board/BraswellCR/Acpi/Acpi.c +++ b/BraswellPlatformPkg/Board/BraswellCR/Acpi/Acpi.c @@ -258,3 +258,4 @@ InstallAcpiBraswellRC ( return EFI_SUCCESS; } + diff --git a/BraswellPlatformPkg/Board/BraswellCR/Acpi/Device/Camera/Camera.asl b/BraswellPlatformPkg/Board/BraswellCR/Acpi/Device/Camera/Camera.asl index 962e864d4a..0543dd001d 100644 --- a/BraswellPlatformPkg/Board/BraswellCR/Acpi/Device/Camera/Camera.asl +++ b/BraswellPlatformPkg/Board/BraswellCR/Acpi/Device/Camera/Camera.asl @@ -52,13 +52,13 @@ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings { - Name (SBUF, ResourceTemplate () // I2C Resource define + Name (SBUF, ResourceTemplate () // I2C Resource define { GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.GPO1", 0x00, ResourceConsumer, , ) { // Pin list - 0x0035 // N"53" DOVDD18 + 0x0035 // N"53" DOVDD18 } GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.GPO1", 0x00, ResourceConsumer, , @@ -72,8 +72,8 @@ { // Pin list 0x0034 // N"52" RESET } - - GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, + + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.GPO1", 0x00, ResourceConsumer, , ) { // Pin list @@ -175,33 +175,33 @@ { Return ("BSW") } - + // Dsm2PlatformSubStr If(LEqual(Arg0, ToUUID("647A6CA2-8B29-49AC-8806-D58B3D2D3EF5"))) { Return ("FFD") } - + // Dsm2SiliconStr If(LEqual(Arg0, ToUUID("A6E922A1-F7B3-4399-B56A-406AE416843B"))) { Return ("BSW") } - + // Dsm2PlatformStr If(LEqual(Arg0, ToUUID("5960313B-0AB0-4940-8840-2CAFA420C015"))) { Return ("INTEL") } - + // Dsm2Info If(LEqual(Arg0, ToUUID("F486D39F-D657-484B-84A6-42A565712B92"))) { Return (Buffer (32) // BSW CR supports only single lane OV2724 sensor module { 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x07, 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x07, 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }) } @@ -234,21 +234,21 @@ Return (0x04) } - If (LEqual (Arg2, 0x02)) + If (LEqual (Arg2, 0x02)) { Return (0x01003507) // 1.8V } - If (LEqual (Arg2, 0x03)) + If (LEqual (Arg2, 0x03)) { Return (0x01002E08) // 2.8V } - If (LEqual (Arg2, 0x04)) + If (LEqual (Arg2, 0x04)) { Return (0x01003400) // RESET } - If (LEqual (Arg2, 0x05)) + If (LEqual (Arg2, 0x05)) { Return (0x01003001) // 1.2V } diff --git a/BraswellPlatformPkg/Board/BraswellCR/Acpi/Device/Camera/Camera2.asl b/BraswellPlatformPkg/Board/BraswellCR/Acpi/Device/Camera/Camera2.asl index 4d14a7c334..31a2ab7e11 100644 --- a/BraswellPlatformPkg/Board/BraswellCR/Acpi/Device/Camera/Camera2.asl +++ b/BraswellPlatformPkg/Board/BraswellCR/Acpi/Device/Camera/Camera2.asl @@ -311,7 +311,7 @@ Return(0x00) } } // End CAM2 - + // // Device STRA // @@ -455,25 +455,25 @@ "\\_SB.GPO1", 0x00, ResourceConsumer, , ) { // Pin list - 0x0032 // GPIO N"50" + 0x0032 // GPIO N"50" } GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.GPO1", 0x00, ResourceConsumer, , ) { // Pin list - 0x0033 // GPIO dvdd12 camerasb03 N"51" + 0x0033 // GPIO dvdd12 camerasb03 N"51" } GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.GPO1", 0x00, ResourceConsumer, , ) { // Pin list - 0x0038 // GPIO dvdd18 camerasb04 N"56" + 0x0038 // GPIO dvdd18 camerasb04 N"56" } GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.GPO1", 0x00, ResourceConsumer, , ) { // Pin list - 0x002D // GPIO avdd28 camerasb08 N"45" + 0x002D // GPIO avdd28 camerasb08 N"45" } GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.GPO1", 0x00, ResourceConsumer, , @@ -585,33 +585,33 @@ { Return ("BSW") } - + //Dsm2PlatformSubStr If(LEqual(Arg0, ToUUID("647A6CA2-8B29-49AC-8806-D58B3D2D3EF5"))) { Return ("FFD") } - + //Dsm2SiliconStr If(LEqual(Arg0, ToUUID("A6E922A1-F7B3-4399-B56A-406AE416843B"))) { Return ("BSW") } - + //Dsm2PlatformStr If(LEqual(Arg0, ToUUID("5960313B-0AB0-4940-8840-2CAFA420C015"))) { Return ("INTEL") } - + //Dsm2Info If(LEqual(Arg0, ToUUID("F486D39F-D657-484B-84A6-42A565712B92"))) { Return (Buffer (32) { 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02, 0x02, - 0x07, 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x07, 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }) } @@ -715,8 +715,8 @@ 0x002F } - GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, - "\\_SB.GPO1", 0x00, ResourceConsumer, , + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, + "\\_SB.GPO1", 0x00, ResourceConsumer, , ) { // Pin list 0x0037 //for camera led camerasb11 diff --git a/BraswellPlatformPkg/Board/BraswellCR/Acpi/Ssdt.asl b/BraswellPlatformPkg/Board/BraswellCR/Acpi/Ssdt.asl index 851f377974..15535b9174 100644 --- a/BraswellPlatformPkg/Board/BraswellCR/Acpi/Ssdt.asl +++ b/BraswellPlatformPkg/Board/BraswellCR/Acpi/Ssdt.asl @@ -17,7 +17,7 @@ DefinitionBlock ( "Ssdt.aml", "SSDT", 0x02, // revision. - // A Revision field value greater than or equal to 2 signifies that integers + // A Revision field value greater than or equal to 2 signifies that integers // declared within the Definition Block are to be evaluated as 64-bit values "INTEL", // OEM ID (6 byte string) "BSW_RC", // OEM table ID (8 byte string) @@ -96,7 +96,7 @@ DefinitionBlock ( { include("Device/Nfc/Nxp1.asl") } - + Scope(\_SB.PCI0) { include("Device/Audio/Audio.asl") @@ -106,4 +106,4 @@ DefinitionBlock ( { include("Device/Wifi/Broadcom.asl") } -} +} \ No newline at end of file diff --git a/BraswellPlatformPkg/Board/BraswellCR/BoardInit/BoardGpios.c b/BraswellPlatformPkg/Board/BraswellCR/BoardInit/BoardGpios.c new file mode 100644 index 0000000000..f987839d82 --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCR/BoardInit/BoardGpios.c @@ -0,0 +1,344 @@ +/** @file + PCH GPIO Porting driver. + + Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "BoardGpios.h" + +CHV_GPIO_PAD_INIT mBSW_CR_GpioInitData[] = +// PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks +{ CHV_GPIO_PAD_CONF (L" N37:CX_PRDY_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x4C38 , NORTH ) , // PRDY_B + CHV_GPIO_PAD_CONF (L" N35:CX_PRDY_B_2 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x4C28 , NORTH ) , // CX_PRDY_B_2 + CHV_GPIO_PAD_CONF (L" N39:CX_PREQ_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x4858 , NORTH ) , // PREQ_B + CHV_GPIO_PAD_CONF (L" N48:GP_CAMERASB00 ", GPIO , M1 , GPIO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x5018 , NORTH ) , // UF_CORE_VR_EN + CHV_GPIO_PAD_CONF (L" N53:GP_CAMERASB01 ", GPIO , M1 , GPIO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x5040 , NORTH ) , // UF_IO_VR_EN + CHV_GPIO_PAD_CONF (L" N46:GP_CAMERASB02 ", GPIO , M1 , GPIO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x5008 , NORTH ) , // UF_ANALOG_VR_EN + CHV_GPIO_PAD_CONF (L" N51:GP_CAMERASB03 ", GPIO , M1 , GPIO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x5030 , NORTH ) , // WF_CORE_VR_EN + CHV_GPIO_PAD_CONF (L" N56:GP_CAMERASB04 ", GPIO , M1 , GPIO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x5058 , NORTH ) , // WF_IO_VR_EN + CHV_GPIO_PAD_CONF (L" N45:GP_CAMERASB05 ", GPIO , M1 , GPIO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x5000 , NORTH ) , // WF_ANALOG_VR_EN + CHV_GPIO_PAD_CONF (L" N49:GP_CAMERASB06 ", GPIO , M1 , GPIO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x5020 , NORTH ) , // WF_VCM_EN + CHV_GPIO_PAD_CONF (L" N54:GP_CAMERASB07 ", GPIO , M1 , GPIO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x5048 , NORTH ) , // FLASH_RESET_N + CHV_GPIO_PAD_CONF (L" N47:GP_CAMERASB08 ", GPIO , M1 , GPIO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x5010 , NORTH ) , // FLASH_TRIGGER + CHV_GPIO_PAD_CONF (L" N52:GP_CAMERASB09 ", GPIO , M1 , GPIO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x5038 , NORTH ) , // UF_CAM_RST_N + CHV_GPIO_PAD_CONF (L" N50:GP_CAMERASB10 ", GPIO , M1 , GPIO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x5028 , NORTH ) , // WF_CAM_RST_N + CHV_GPIO_PAD_CONF (L" N55:GP_CAMERASB11 ", GPIO , M1 , GPIO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x5050 , NORTH ) , // CAM_ACT_LED + CHV_GPIO_PAD_CONF (L" N00:GPIO_DFX0 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x4400 , NORTH ) , // + CHV_GPIO_PAD_CONF (L" N03:GPIO_DFX1 ", GPIO , M1 , GPIO , LOW , LOW , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 3 , NA , 0x4418 , NORTH ) , // GPS_WAKEUP + CHV_GPIO_PAD_CONF (L" N07:GPIO_DFX2 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x4438 , NORTH ) , // COMBO_GPS_RESET_N + CHV_GPIO_PAD_CONF (L" N01:GPIO_DFX3 ", GPIO , M1 , GPI , NA , NA , Trig_Edge_Low , Line2 , P_NONE , NA , NA , NonMaskable , En_Edge_RX_Data , Inv_TX_Enable , NA , NA , NA , 0x4408 , NORTH ) , // SYS_SHDN_N + CHV_GPIO_PAD_CONF (L" N05:GPIO_DFX4 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4428 , NORTH ) , // NGFF_MODEM_RESET_N + CHV_GPIO_PAD_CONF (L" N04:GPIO_DFX5 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4420 , NORTH ) , // WWAN_PWR_EN + CHV_GPIO_PAD_CONF (L" N08:GPIO_DFX6 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4440 , NORTH ) , // + CHV_GPIO_PAD_CONF (L" N07:GPIO_DFX7 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4410 , NORTH ) , // + CHV_GPIO_PAD_CONF (L" N06:GPIO_DFX8 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4430 , NORTH ) , // SOC_NGFF_WIFI_EN + CHV_GPIO_PAD_CONF (L" N19:GPIO_SUS1 ", Native , M6 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4820 , NORTH ) , // NGFF_WWAN_WAKE_GPIO_11_RD + CHV_GPIO_PAD_CONF (L" N24:GPIO_SUS2 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4848 , NORTH ) , // PROCHOT + CHV_GPIO_PAD_CONF (L" N17:GPIO_SUS3 ", GPIO , M1 , GPI , NA , NA , Trig_Edge_Low , Line4 , NA , NA , NA , NonMaskable , En_Edge_RX_Data , NA , NA , NA , NA , 0x4810 , NORTH ) , // I2S_IRQ_N + CHV_GPIO_PAD_CONF (L" N22:GPIO_SUS4 ", Native , M6 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4838 , NORTH ) , // PMU_WAKE_LAN_B + CHV_GPIO_PAD_CONF (L" N20:GPIO_SUS5 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4828 , NORTH ) , // WiFI_32k_CLK + CHV_GPIO_PAD_CONF (L" N71:HV_DDI0_DDC_SCL ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5458 , NORTH ) , // DDI1_HDMI_SOC_SCL + CHV_GPIO_PAD_CONF (L" N66:HV_DDI0_DDC_SDA ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5430 , NORTH ) , // DDI1_HDMI_SOC_SDA + CHV_GPIO_PAD_CONF (L" N61:HV_DDI0_HPD ", Native , M1 , NA , NA , NA , NA , NA , P_NONE , NA , NA , NA , NA , Inv_TX_Enable , NA , NA , NA , 0x5408 , NORTH ) , // DDI0_HPD_N + CHV_GPIO_PAD_CONF (L" N64:HV_DDI1_HPD ", Native , M1 , NA , NA , NA , NA , NA , P_NONE , NA , NA , NA , NA , Inv_TX_Enable , NA , NA , NA , 0x5420 , NORTH ) , // DDI1_HPD_N + CHV_GPIO_PAD_CONF (L" N67:HV_DDI2_DDC_SCL ", Native , M3 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5438 , NORTH ) , // DBG_UART3_TXD + CHV_GPIO_PAD_CONF (L" N62:HV_DDI2_DDC_SDA ", Native , M3 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5410 , NORTH ) , // DBG_UART3_RXD + CHV_GPIO_PAD_CONF (L" N65:PANEL0_BKLTCTL ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5428 , NORTH ) , // DDI0_BKLT_CTRL + CHV_GPIO_PAD_CONF (L" N60:PANEL0_BKLTEN ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5400 , NORTH ) , // DDI0_BKLT_EN + CHV_GPIO_PAD_CONF (L" N72:PANEL0_VDDEN ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5460 , NORTH ) , // DDI0_VDD_EN + CHV_GPIO_PAD_CONF (L" N63:PANEL1_BKLTCTL ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5418 , NORTH ) , // MATA_Adap_ctrl + CHV_GPIO_PAD_CONF (L" N32:PROCHOT_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C10 , NORTH ) , // VR_HOT_N + CHV_GPIO_PAD_CONF (L" N16:SEC_GPIO_SUS10 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4808 , NORTH ) , // I2C_RESERT_N_CONN + CHV_GPIO_PAD_CONF (L" N21:SEC_GPIO_SUS11 ", GPIO , M1 , GPI , NA , NA , Trig_Edge_Low , Line5 , NA , NA , NA , NonMaskable , En_Edge_RX_Data , NA , UNMASK_WAKE , 15 , NA , 0x4830 , NORTH ) , // KBC_INT + CHV_GPIO_PAD_CONF (L" N27:SEC_GPIO_SUS9 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , P_20K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x4860 , NORTH ) , // LAN_LED1 + CHV_GPIO_PAD_CONF (L" N31:TCK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C08 , NORTH ) , // JTAG + CHV_GPIO_PAD_CONF (L" N41:TDI ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C58 , NORTH ) , // + CHV_GPIO_PAD_CONF (L" N39:TDO ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C48 , NORTH ) , // + CHV_GPIO_PAD_CONF (L" N36:TDO_2 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C30 , NORTH ) , // + CHV_GPIO_PAD_CONF (L" N34:TMS ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C20 , NORTH ) , // + CHV_GPIO_PAD_CONF (L" N30:TRST_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C00 , NORTH ) , // +// East Community +// PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks + CHV_GPIO_PAD_CONF (L" E21: MF_ISH_GPIO_0 ", Native , M1 , NA , NA , NA , NA , NA , P_5K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x4830 , EAST ) , // acce_1 + CHV_GPIO_PAD_CONF (L" E18: MF_ISH_GPIO_1 ", Native , M1 , NA , NA , NA , NA , NA , P_5K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x4818 , EAST ) , // acce_2 + CHV_GPIO_PAD_CONF (L" E24: MF_ISH_GPIO_2 ", Native , M1 , NA , NA , NA , NA , NA , P_5K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x4848 , EAST ) , // compass + CHV_GPIO_PAD_CONF (L" E15: MF_ISH_GPIO_3 ", Native , M1 , NA , NA , NA , NA , NA , P_5K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x4800 , EAST ) , // Gyro_1 + CHV_GPIO_PAD_CONF (L" E22: MF_ISH_GPIO_4 ", GPIO , M1 , GPI , NA , NA , Trig_Level , Line0 , P_20K_H , NA , NA , NonMaskable , En_RX_Data ,Inv_RX_Data, NA , 19 , NA , 0x4838 , EAST ) , // SENSOR_HUB_R_INT || Alt_1 + CHV_GPIO_PAD_CONF (L" E19: MF_ISH_GPIO_5 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA ,No_Inversion , NA , NA , NA , 0x4820 , EAST ) , // SENS_HUB_RST_N || Alt_2 + CHV_GPIO_PAD_CONF (L" E25: MF_ISH_GPIO_6 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4850 , EAST ) , // ALS + CHV_GPIO_PAD_CONF (L" E16: MF_ISH_GPIO_7 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA ,No_Inversion , NA , NA , NA , 0x4808 , EAST ) , // SENS_HUB_WAKE || Prox + CHV_GPIO_PAD_CONF (L" E23: MF_ISH_GPIO_8 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4840 , EAST ) , // SAR + CHV_GPIO_PAD_CONF (L" E20: MF_ISH_GPIO_9 ", Native , M1 , NA , NA , NA , NA , NA , P_5K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x4828 , EAST ) , // Gyro_2 + CHV_GPIO_PAD_CONF (L" E04: PMU_AC_PRESENT ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4420 , EAST ) , // AC_PRESENT + CHV_GPIO_PAD_CONF (L" E01:PMU_BATLOW_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4408 , EAST ) , // PMU_BATLOW_N + CHV_GPIO_PAD_CONF (L" E05:PMU_PLTRST_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4428 , EAST ) , // PLT_RST_N + CHV_GPIO_PAD_CONF (L" E08:PMU_PWRBTN_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4440 , EAST ) , // SOC_PWRBTN_N + CHV_GPIO_PAD_CONF (L" E03:PMU_SLP_S0IX_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4418 , EAST ) , // SLP_S0IX_N + CHV_GPIO_PAD_CONF (L" E00:PMU_SLP_S3_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4400 , EAST ) , // SLP_S3_N + CHV_GPIO_PAD_CONF (L" E09:PMU_SLP_S4_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4448 , EAST ) , // SLP_S4_N + CHV_GPIO_PAD_CONF (L" E06:PMU_SUSCLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4430 , EAST ) , // SLEEP_CLK + CHV_GPIO_PAD_CONF (L" E10:PMU_WAKE_B ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x4450 , EAST ) , // PMU_WAKE_N + CHV_GPIO_PAD_CONF (L" E11:PMU_WAKE_LAN_B ", GPIO , M1 , GPI , NA , NA , Trig_Edge_Low , Line2 , NA , NA , NA , NonMaskable , En_Edge_RX_Data , Inv_RX_Data , UNMASK_WAKE , 11 , NA , 0x4458 , EAST ) , // PMU_WAKE_LAN_N + CHV_GPIO_PAD_CONF (L" E02:SUS_STAT_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4410 , EAST ) , // TBD +// South East Community +// PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks + CHV_GPIO_PAD_CONF (L" SE16:SDMMC1_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4808 , SOUTHEAST ) , // SDMMC1_CLK + CHV_GPIO_PAD_CONF (L" SE23:SDMMC1_CMD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4840 , SOUTHEAST ) , // SDMMC1_CMD + CHV_GPIO_PAD_CONF (L" SE17:SDMMC1_D0 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x4810 , SOUTHEAST ) , // SDMMC1_D_0 + CHV_GPIO_PAD_CONF (L" SE24:SDMMC1_D1 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4848 , SOUTHEAST ) , // SDMMC1_D_1 + CHV_GPIO_PAD_CONF (L" SE20:SDMMC1_D2 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4828 , SOUTHEAST ) , // SDMMC1_D_2 + CHV_GPIO_PAD_CONF (L" SE26:SDMMC1_D3_CD_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4858 , SOUTHEAST ) , // SDMMC1_D_3_CD_B + CHV_GPIO_PAD_CONF (L" SE67:MMC1_D4_SD_WE ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5438 , SOUTHEAST ) , // MMC1_D4 + CHV_GPIO_PAD_CONF (L" SE65:MMC1_D5 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5428 , SOUTHEAST ) , // MMC1_D5 + CHV_GPIO_PAD_CONF (L" SE63:MMC1_D6 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5418 , SOUTHEAST ) , // MMC1_D6 + CHV_GPIO_PAD_CONF (L" SE68:MMC1_D7 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5440 , SOUTHEAST ) , // MMC1_D7 + CHV_GPIO_PAD_CONF (L" SE84:MC1_RCLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5448 , SOUTHEAST ) , // SDMMC1_RCLK + CHV_GPIO_PAD_CONF (L" SE77:GPIO_ALERT ", GPIO , M1 , GPI , NA , NA , Trig_Level , Line1 , NA , NA , NA , NonMaskable , En_RX_Data , Inv_RX_Data , NA , 46 , NA , 0x5810 , SOUTHEAST ) , // TCH_PADCONN_INT_N + CHV_GPIO_PAD_CONF (L" SE79:ILB_SERIRQ ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5820 , SOUTHEAST ) , // ILB_SERIRQ + CHV_GPIO_PAD_CONF (L" SE51:MF_LPC_CLKOUT0 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5030 , SOUTHEAST ) , // MF_LPC_CLKOUT0 + CHV_GPIO_PAD_CONF (L" SE47:MF_LPC_AD0 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5010 , SOUTHEAST ) , // MF_LPC_AD0 + CHV_GPIO_PAD_CONF (L" SE52:MF_LPC_AD1 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5038 , SOUTHEAST ) , // MF_LPC_AD1 + CHV_GPIO_PAD_CONF (L" SE45:MF_LPC_AD2 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5000 , SOUTHEAST ) , // MF_LPC_AD2 + CHV_GPIO_PAD_CONF (L" SE50:MF_LPC_AD3 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5028 , SOUTHEAST ) , // MF_LPC_AD3 + CHV_GPIO_PAD_CONF (L" SE46:LPC_CLKRUNB ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5008 , SOUTHEAST ) , // LPC_CLKRUNB + CHV_GPIO_PAD_CONF (L" SE48:LPC_FRAMEB ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5018 , SOUTHEAST ) , // LPC_FRAMEB + CHV_GPIO_PAD_CONF (L" SE00:MF_PLT_CLK0 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4400 , SOUTHEAST ) , // Camera1_clock + CHV_GPIO_PAD_CONF (L" SE02:MF_PLT_CLK1 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4410 , SOUTHEAST ) , // Camera2_clock + CHV_GPIO_PAD_CONF (L" SE07:MF_PLT_CLK2 ", GPIO , M1 , GPI , NA , LOW , Trig_Level , Line2 , NA , NA , NA , NonMaskable , En_RX_Data , NA , NA , NA , NA , 0x4438 , SOUTHEAST ) , // GPS_HOSTREQ + CHV_GPIO_PAD_CONF (L" SE04:MF_PLT_CLK3 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4420 , SOUTHEAST ) , // I2S_MCLK + CHV_GPIO_PAD_CONF (L" SE03:MF_PLT_CLK4 ", Native , M3 , NA , NA , LOW , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4418 , SOUTHEAST ) , // I2C0_ISF_SDA + CHV_GPIO_PAD_CONF (L" SE06:MF_PLT_CLK5 ", Native , M3 , NA , NA , LOW , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4430 , SOUTHEAST ) , // COMBO_GPS_RESET_N + CHV_GPIO_PAD_CONF (L" SE76:PMU_RSTBUTTON_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5808 , SOUTHEAST ) , // SOC_RESETBTN_N + CHV_GPIO_PAD_CONF (L" SE83:SUSPWRDNACK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5840 , SOUTHEAST ) , // SUSPWRDNACK + CHV_GPIO_PAD_CONF (L" SE05:PWM0 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4428 , SOUTHEAST ) , // HAPTIC0, + CHV_GPIO_PAD_CONF (L" SE01:PWM1 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4408 , SOUTHEAST ) , // WIFI_PCIE_RST_N + CHV_GPIO_PAD_CONF (L" SE85:SDMMC3_1P8_EN ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5850 , SOUTHEAST ) , // SD_CARD_PWR_EN + CHV_GPIO_PAD_CONF (L" SE81:SDMMC3_CD_B ", GPIO , M1 , GPI , NA , NA , Trig_Level , NA , NA , NA , NA , NA , En_Edge_RX_Data , NA , NA , NA , NA , 0x5830 , SOUTHEAST ) , // SD_CARD_DET_N + CHV_GPIO_PAD_CONF (L" SE31:SDMMC3_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C08 , SOUTHEAST ) , // SD_CARD_CLK + CHV_GPIO_PAD_CONF (L" SE34:SDMMC3_CMD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C20 , SOUTHEAST ) , // SD_CARD_CMD + CHV_GPIO_PAD_CONF (L" SE35:SDMMC3_D0 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C28 , SOUTHEAST ) , // SD_CARD_D0 + CHV_GPIO_PAD_CONF (L" SE30:SDMMC3_D1 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C00 , SOUTHEAST ) , // SD_CARD_D1 + CHV_GPIO_PAD_CONF (L" SE33:SDMMC3_D2 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C18 , SOUTHEAST ) , // SD_CARD_D2 + CHV_GPIO_PAD_CONF (L" SE32:SDMMC3_D3 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C10 , SOUTHEAST ) , // SD_CARD_D3 + CHV_GPIO_PAD_CONF (L" SE78:SDMMC3_PWR_EN_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5818 , SOUTHEAST ) , // SD_CARD_PWRDN_N + CHV_GPIO_PAD_CONF (L" SE62:SPI1_CLK ", GPIO , M1 , GPI , NA , NA , Trig_Edge_Low , Line4 , NA , NA , NA , NonMaskable , En_Edge_RX_Data , NA , NA , NA , NA , 0x5410 , SOUTHEAST ) , // SOC_THERM_SENSOR_ALERT_N + CHV_GPIO_PAD_CONF (L" SE61:SPI1_CS0_B ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5408 , SOUTHEAST ) , // CS_WAKE_N + CHV_GPIO_PAD_CONF (L" SE66:SPI1_CS1_B ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5430 , SOUTHEAST ) , // SPI_CS for NFC + CHV_GPIO_PAD_CONF (L" SE60:SPI1_MISO ", GPIO , M1 , GPI , NA , NA , Trig_Edge_Low , Line5 , P_20K_H , _ENABLE , NA , NonMaskable , En_RX_Data , Inv_RX_Enable , UNMASK_WAKE , 34 , NA , 0x5400 , SOUTHEAST ) , // PMIC_IRQ_1P8 + CHV_GPIO_PAD_CONF (L" SE64:SPI1_MOSI ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5420 , SOUTHEAST ) , // WIFI_RST_GPIO + CHV_GPIO_PAD_CONF (L" SE80:USB_OC0_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5828 , SOUTHEAST ) , // USB2_OC0_N + CHV_GPIO_PAD_CONF (L" SE75:USB_OC1_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5800 , SOUTHEAST ) , // USB3_OC_N + +// South west Community +// PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks + CHV_GPIO_PAD_CONF (L" SW02:FST_SPI_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4410 , SOUTHWEST ) , // FAST_SPI_CLK + CHV_GPIO_PAD_CONF (L" SW06:FST_SPI_CS0_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4430 , SOUTHWEST ) , // FST_SPI_CS0_N( SPI NOR) + CHV_GPIO_PAD_CONF (L" SW04:FST_SPI_CS1_B ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4420 , SOUTHWEST ) , // RF_KILL_GPS_N_1P8 + CHV_GPIO_PAD_CONF (L" SW07:FST_SPI_CS2_B ", GPIO , M1 , GPO , LOW , NA , NA , NA , P_5K_L , NA , NA , NA , NA , NA , NA , NA , NA , 0x4438 , SOUTHWEST ) , // TCH_PNL_MODE_SEL + CHV_GPIO_PAD_CONF (L" SW01:FST_SPI_D0 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4408 , SOUTHWEST ) , // FST_SPI_D0 + CHV_GPIO_PAD_CONF (L" SW05:FST_SPI_D1 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4428 , SOUTHWEST ) , // FST_SPI_D1 + CHV_GPIO_PAD_CONF (L" SW00:FST_SPI_D2 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4400 , SOUTHWEST ) , // FST_SPI_D2 + CHV_GPIO_PAD_CONF (L" SW03:FST_SPI_D3 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4418 , SOUTHWEST ) , // FST_SPI_D3 + CHV_GPIO_PAD_CONF (L" SW30:MF_HDA_CLK ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x4C00 , SOUTHWEST ) , // MF_HDA_CLK II GP_SSP_0_I2S_TXD + CHV_GPIO_PAD_CONF (L" SW37:MF_HDA_DOCKENB ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C38 , SOUTHWEST ) , // I2S_2_RXD_R_AICO(AIC) + CHV_GPIO_PAD_CONF (L" SW34:MF_HDA_DOCKRSTB ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C20 , SOUTHWEST ) , // I2S_2_TXD_R_AICO (AIC) + CHV_GPIO_PAD_CONF (L" SW31:MF_HDA_RSTB ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C08 , SOUTHWEST ) , // AUD_LINK_RST_N || I2S_0_CLK_R_AICO (AIC) + CHV_GPIO_PAD_CONF (L" SW32:MF_HDA_SDI0 ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C10 , SOUTHWEST ) , // AUD_LINK_SDI0 (ALC282) || I2S_2_CLK_R_AICO (AIC) + CHV_GPIO_PAD_CONF (L" SW36:MF_HDA_SDI1 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C30 , SOUTHWEST ) , // I2S_2_FS_R_AICO + CHV_GPIO_PAD_CONF (L" SW33:MF_HDA_SDO ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C18 , SOUTHWEST ) , // AUD_LINK_SDO_R||I2S_0_RXD_R_AICO (AIC) + CHV_GPIO_PAD_CONF (L" SW35:MF_HDA_SYNC ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C28 , SOUTHWEST ) , // AUD_LINKSYNC_R|| I2S_0_FS_R_AICO (AIC) + CHV_GPIO_PAD_CONF (L" SW22:UART2_CTS_B ", Native , M1 , NA , NA , NA , NA , NA , P_NONE , NA , NA , NA , NA , NA , NA , NA , NA , 0x4838 , SOUTHWEST ) , // UART2_GPS_CTS (GPS)|| UART2_GPS_CTS_CONN (AIC) + CHV_GPIO_PAD_CONF (L" SW19:UART2_RTS_B ", Native , M1 , NA , NA , NA , NA , NA , P_NONE , NA , NA , NA , NA , NA , NA , NA , NA , 0x4820 , SOUTHWEST ) , // UART2_GPS_RTS (GPS)|| UART2_GPS_RTS_CONN (AIC) + CHV_GPIO_PAD_CONF (L" SW17:UART2_RXD ", Native , M1 , NA , NA , NA , NA , NA , P_NONE , NA , NA , NA , NA , NA , NA , NA , NA , 0x4810 , SOUTHWEST ) , // UART2_GPS_RXD (GPS)|| UART2_GPS_RXD_CONN(AIC) + CHV_GPIO_PAD_CONF (L" SW21:UART2_TXD ", Native , M1 , NA , NA , NA , NA , NA , P_NONE , NA , NA , NA , NA , NA , NA , NA , NA , 0x4830 , SOUTHWEST ) , // UART2_GPS_TXD(GPS)|| UART2_GPS_TXD_CONN(AIC) + CHV_GPIO_PAD_CONF (L" SW65:I2C0_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x5428 , SOUTHWEST ) , // 3rd party Sensor Card + CHV_GPIO_PAD_CONF (L" SW61:I2C0_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x5408 , SOUTHWEST ) , // 3rd party Sensor Card + CHV_GPIO_PAD_CONF (L" SW63:I2C1_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x5418 , SOUTHWEST ) , // PMIC + CHV_GPIO_PAD_CONF (L" SW60:I2C1_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x5400 , SOUTHWEST ) , // PMIC + CHV_GPIO_PAD_CONF (L" SW66:I2C2_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x5430 , SOUTHWEST ) , // MIPI_CSI CAMERAS, FLASH + CHV_GPIO_PAD_CONF (L" SW62:I2C2_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x5410 , SOUTHWEST ) , // MIPI_CSI CAMERAS, FLASH + CHV_GPIO_PAD_CONF (L" SW67:I2C3_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x5438 , SOUTHWEST ) , // MIPI_CSI CAMERAS, FLASH + CHV_GPIO_PAD_CONF (L" SW64:I2C3_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x5420 , SOUTHWEST ) , // MIPI_CSI CAMERAS, FLASH + CHV_GPIO_PAD_CONF (L" SW50:I2C4_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x5028 , SOUTHWEST ) , // I2C Audio | Touch PAD + CHV_GPIO_PAD_CONF (L" SW46:I2C4_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x5008 , SOUTHWEST ) , // I2C Audio | Touch PAD + CHV_GPIO_PAD_CONF (L" SW48:I2C5_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x5018 , SOUTHWEST ) , // Touch Panel + CHV_GPIO_PAD_CONF (L" SW45:I2C5_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x5000 , SOUTHWEST ) , // Touch Panel + CHV_GPIO_PAD_CONF (L" SW51:I2C6_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x5030 , SOUTHWEST ) , // INA Decice + CHV_GPIO_PAD_CONF (L" SW47:I2C6_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x5010 , SOUTHWEST ) , // INA Device + CHV_GPIO_PAD_CONF (L" SW90:PCIE_CLKREQ0B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5C00 , SOUTHWEST ) , // RTL8111G (CLKREQ_N) + CHV_GPIO_PAD_CONF (L" SW91:PCIE_CLKREQ1B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5C08 , SOUTHWEST ) , // NGFF(CLKREQ_N) + CHV_GPIO_PAD_CONF (L" SW93:PCIE_CLKREQ2B ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5C18 , SOUTHWEST ) , // NGFF_WWAN_RF_KILL_1P8_N (Active low) + CHV_GPIO_PAD_CONF (L" SW95:PCIE_CLKREQ3B ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5C28 , SOUTHWEST ) , // Tied to Micro SD + CHV_GPIO_PAD_CONF (L" SW75:SATA_GP0 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5800 , SOUTHWEST ) , // TOUCH_PNL_RST_N + CHV_GPIO_PAD_CONF (L" SW76:SATA_GP1 ", GPIO , M1 , GPI , NA , NA , Trig_Level , Line0 , P_1K_H , NA , NA , NonMaskable , NA , Inv_RX_Data , NA , 41 , NA , 0x5808 , SOUTHWEST ) , // TOUCH_INT_N + CHV_GPIO_PAD_CONF (L" SW78:SATA_GP2 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5818 , SOUTHWEST ) , // SATA_DEVSLP_R + CHV_GPIO_PAD_CONF (L" SW80:SATA_GP3 ", Native , M1 , GPIO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5828 , SOUTHWEST ) , // eMMC_RST_N + CHV_GPIO_PAD_CONF (L" SW77:SATA_LEDN ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5810 , SOUTHWEST ) , // SATA_LED_N +}; + +/// Community Configuration +/// Family Configuration +/* +* GPIO Families configuration in CherryView +* +*/ +GPIO_SAI_INIT mBSW_GPIO_SAI_Init_East[] = +{ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_access_reg ", 0x0 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_wake_reg ", 0x4 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_interrupt_reg ", 0x8 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_community_reg ", 0xC , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_broadcast_reg ", 0x10 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_reg ", 0x14 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_pad_broadcast_reg ", 0x18 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_4x2_12_0_regs ", 0x1C , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_4x2_12_1_regs ", 0x20 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_access_reg ", 0x100, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_wake_reg ", 0x104, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_interrupt_reg ", 0x108, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_community_reg ", 0x10C, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_broadcast_reg ", 0x110, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_reg ", 0x114, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_pad_broadcast_reg ", 0x118, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_4x2_12_0_regs ", 0x11c, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_4x2_12_1_regs ", 0x120, 0x18310, ENABLE), +}; + +GPIO_SAI_INIT mBSW_GPIO_SAI_Init_North[] = +{ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_access_reg ", 0x0 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_wake_reg ", 0x4 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_interrupt_reg ", 0x8 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_community_reg ", 0xC , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_broadcast_reg ", 0x10 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_reg ", 0x14 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_pad_broadcast_reg ", 0x18 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_2x4_rcomp_10_0_regs ", 0x1C , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x4_13_0_regs ", 0x20 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_3x4_12_0_regs ", 0x24 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_2x4_12_0_regs ", 0x28 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_3x4_13_0_regs ", 0x2C , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_access_reg ", 0x100, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_wake_reg ", 0x104, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_interrupt_reg ", 0x108, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_community_reg ", 0x10C, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_broadcast_reg ", 0x110, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_reg ", 0x114, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_pad_broadcast_reg ", 0x118, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_2x4_rcomp_10_0_regs ", 0x11C, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x4_13_0_regs ", 0x120, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_3x4_12_0_regs ", 0x124, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_2x4_12_0_regs ", 0x128, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_3x4_13_0_regs ", 0x12C, 0x18310, ENABLE), +}; + +GPIO_SAI_INIT mBSW_GPIO_SAI_Init_SouthEast[] = +{ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_access_reg ", 0x0 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_wake_reg ", 0x4 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_interrupt_reg ", 0x8 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_community_reg ", 0xC , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_broadcast_reg ", 0x10 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_reg ", 0x14 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_pad_broadcast_reg ", 0x18 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_2_regs ", 0x1C , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_3x3_rcomp_13_0_regs ", 0x20 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_hshvfamily_2x3_rcomp_7_0_regs ", 0x24 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_hshvfamily_3x3_rcomp_9_0_regs ", 0x28 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_3x3_10_0_regs ", 0x2C , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_3x3_11_0_regs ", 0x30 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_access_reg ", 0x100, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_wake_reg ", 0x104, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_interrupt_reg ", 0x108, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_community_reg ", 0x10C, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_broadcast_reg ", 0x110, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_reg ", 0x114, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_pad_broadcast_reg ", 0x118, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_2_regs ", 0x11C, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_3x3_rcomp_13_0_regs ", 0x120, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_hshvfamily_2x3_rcomp_7_0_regs ", 0x124, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_hshvfamily_3x3_rcomp_9_0_regs ", 0x128, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_3x3_10_0_regs ", 0x12C, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_3x3_11_0_regs ", 0x130, 0x18310, ENABLE), +}; + +GPIO_SAI_INIT mBSW_GPIO_SAI_Init_SouthWest[] = +{ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_access_reg ",0x0 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_wake_reg ",0x4 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_interrupt_reg ",0x8 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_community_reg ",0xC , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_broadcast_reg ",0x10 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_reg ",0x14 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_pad_broadcast_reg ",0x18 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_2x3_8_1_regs ",0x1C , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_6_regs ",0x20 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_5_regs ",0x24 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_4_regs ",0x28 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_3_regs ",0x2C , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_1_regs ",0x30 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_0_regs ",0x34 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_access_reg ",0x100, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_wake_reg ",0x104, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_interrupt_reg ",0x108, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_community_reg ",0x10C, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_broadcast_reg ",0x110, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_reg ",0x114, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_pad_broadcast_reg ",0x118, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_2x3_8_1_regs ",0x11C, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_6_regs ",0x120, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_5_regs ",0x124, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_4_regs ",0x128, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_3_regs ",0x12C, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_1_regs ",0x130, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_0_regs ",0x134, 0x18310, ENABLE), +}; + +CHV_GPIO_PAD_INIT mBSW_CR_GpioInitData_N[] = +// PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks +{ + CHV_GPIO_PAD_CONF (L" N15:GPIO_SUS0 ", GPIO , M1 , GPI , NA , NA , Trig_Edge_Low , Line3 , P_NONE , NA , NA , NonMaskable , En_Edge_RX_Data , NA , UNMASK_WAKE , 9 , SCI , 0x4800 , NORTH ) , // SOC_WAKE_SCI_N + CHV_GPIO_PAD_CONF (L" N25:GPIO_SUS6 ", GPIO , M1 , GPI , NA , NA , Trig_Edge_Low , Line14 , NA , NA , NA , NonMaskable , En_Edge_RX_Data , NA , NA , 19 , SCI , 0x4850 , NORTH ) , // SOC_RUNTIME_SCI_N + CHV_GPIO_PAD_CONF (L" N18:GPIO_SUS7 ", GPIO , M1 , GPI , NA , NA , Trig_Edge_Low , Line15 , NA , NA , NA , NonMaskable , En_Edge_RX_Data , NA , NA , 12 , SMI , 0x4818 , NORTH ) , // SOC_EXTSMI_N + +}; + +VOID +BraswellCRGpioLateInit ( + VOID + ) +{ + + DEBUG ((EFI_D_ERROR, "Programming BSW CR Board Gpio Tables which are not done properly by FSP...\n")); + + // PAD programming to initialize GPIOs with SCI/SMI support, which depends on FSP PchInit to program basic chipset resources. + InternalGpioPADConfig(0, sizeof(mBSW_CR_GpioInitData_N)/sizeof(mBSW_CR_GpioInitData_N[0]), mBSW_CR_GpioInitData_N); + + // GPIO lock if really want + SAI_SettingOfGpioFamilies(mBSW_GPIO_SAI_Init_East, sizeof(mBSW_GPIO_SAI_Init_East)/sizeof(mBSW_GPIO_SAI_Init_East[0])); + SAI_SettingOfGpioFamilies(mBSW_GPIO_SAI_Init_North, sizeof(mBSW_GPIO_SAI_Init_North)/sizeof(mBSW_GPIO_SAI_Init_North[0])); + SAI_SettingOfGpioFamilies(mBSW_GPIO_SAI_Init_SouthEast, sizeof(mBSW_GPIO_SAI_Init_SouthEast)/sizeof(mBSW_GPIO_SAI_Init_SouthEast[0])); + SAI_SettingOfGpioFamilies(mBSW_GPIO_SAI_Init_SouthWest, sizeof(mBSW_GPIO_SAI_Init_SouthWest)/sizeof(mBSW_GPIO_SAI_Init_SouthWest[0])); +} + +VOID +BraswellCrBoardGpioConfigure ( + VOID + ) +{ + InternalGpioPADConfig(0, sizeof(mBSW_CR_GpioInitData)/sizeof(mBSW_CR_GpioInitData[0]), mBSW_CR_GpioInitData); +} diff --git a/BraswellPlatformPkg/Board/BraswellCR/BoardInit/BoardGpios.h b/BraswellPlatformPkg/Board/BraswellCR/BoardInit/BoardGpios.h index 434cdc0e16..71819caca4 100644 --- a/BraswellPlatformPkg/Board/BraswellCR/BoardInit/BoardGpios.h +++ b/BraswellPlatformPkg/Board/BraswellCR/BoardInit/BoardGpios.h @@ -65,127 +65,16 @@ #define ENABLE 1 #define DISABLE 0 -/// Community Configuration -/// Family Configuration -/* -* GPIO Families configuration in CherryView -* -*/ -GPIO_SAI_INIT mBSW_GPIO_SAI_Init_East[] = -{ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_access_reg ", 0x0 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_wake_reg ", 0x4 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_interrupt_reg ", 0x8 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_community_reg ", 0xC , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_broadcast_reg ", 0x10 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_reg ", 0x14 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_pad_broadcast_reg ", 0x18 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_4x2_12_0_regs ", 0x1C , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_4x2_12_1_regs ", 0x20 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_access_reg ", 0x100, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_wake_reg ", 0x104, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_interrupt_reg ", 0x108, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_community_reg ", 0x10C, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_broadcast_reg ", 0x110, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_reg ", 0x114, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_pad_broadcast_reg ", 0x118, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_4x2_12_0_regs ", 0x11c, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_4x2_12_1_regs ", 0x120, 0x18310, ENABLE), -}; - -GPIO_SAI_INIT mBSW_GPIO_SAI_Init_North[] = -{ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_access_reg ", 0x0 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_wake_reg ", 0x4 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_interrupt_reg ", 0x8 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_community_reg ", 0xC , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_broadcast_reg ", 0x10 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_reg ", 0x14 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_pad_broadcast_reg ", 0x18 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_2x4_rcomp_10_0_regs ", 0x1C , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x4_13_0_regs ", 0x20 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_3x4_12_0_regs ", 0x24 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_2x4_12_0_regs ", 0x28 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_3x4_13_0_regs ", 0x2C , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_access_reg ", 0x100, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_wake_reg ", 0x104, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_interrupt_reg ", 0x108, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_community_reg ", 0x10C, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_broadcast_reg ", 0x110, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_reg ", 0x114, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_pad_broadcast_reg ", 0x118, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_2x4_rcomp_10_0_regs ", 0x11C, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x4_13_0_regs ", 0x120, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_3x4_12_0_regs ", 0x124, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_2x4_12_0_regs ", 0x128, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_3x4_13_0_regs ", 0x12C, 0x18310, ENABLE), -}; - -GPIO_SAI_INIT mBSW_GPIO_SAI_Init_SouthEast[] = -{ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_access_reg ", 0x0 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_wake_reg ", 0x4 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_interrupt_reg ", 0x8 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_community_reg ", 0xC , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_broadcast_reg ", 0x10 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_reg ", 0x14 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_pad_broadcast_reg ", 0x18 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_2_regs ", 0x1C , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_3x3_rcomp_13_0_regs ", 0x20 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_hshvfamily_2x3_rcomp_7_0_regs ", 0x24 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_hshvfamily_3x3_rcomp_9_0_regs ", 0x28 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_3x3_10_0_regs ", 0x2C , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_3x3_11_0_regs ", 0x30 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_access_reg ", 0x100, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_wake_reg ", 0x104, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_interrupt_reg ", 0x108, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_community_reg ", 0x10C, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_broadcast_reg ", 0x110, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_reg ", 0x114, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_pad_broadcast_reg ", 0x118, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_2_regs ", 0x11C, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_3x3_rcomp_13_0_regs ", 0x120, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_hshvfamily_2x3_rcomp_7_0_regs ", 0x124, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_hshvfamily_3x3_rcomp_9_0_regs ", 0x128, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_3x3_10_0_regs ", 0x12C, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_3x3_11_0_regs ", 0x130, 0x18310, ENABLE), -}; - -GPIO_SAI_INIT mBSW_GPIO_SAI_Init_SouthWest[] = -{ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_access_reg ",0x0 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_wake_reg ",0x4 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_interrupt_reg ",0x8 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_community_reg ",0xC , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_broadcast_reg ",0x10 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_reg ",0x14 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_pad_broadcast_reg ",0x18 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_2x3_8_1_regs ",0x1C , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_6_regs ",0x20 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_5_regs ",0x24 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_4_regs ",0x28 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_3_regs ",0x2C , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_1_regs ",0x30 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_0_regs ",0x34 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_access_reg ",0x100, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_wake_reg ",0x104, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_interrupt_reg ",0x108, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_community_reg ",0x10C, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_broadcast_reg ",0x110, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_reg ",0x114, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_pad_broadcast_reg ",0x118, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_2x3_8_1_regs ",0x11C, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_6_regs ",0x120, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_5_regs ",0x124, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_4_regs ",0x128, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_3_regs ",0x12C, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_1_regs ",0x130, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_0_regs ",0x134, 0x18310, ENABLE), -}; - -CHV_GPIO_PAD_INIT mBSW_CR_GpioInitData_N[] = -// PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks -{ - CHV_GPIO_PAD_CONF (L" N15:GPIO_SUS0 ", GPIO , M1 , GPI , NA , NA , Trig_Edge_Low , Line3 , P_NONE , NA , NA , NonMaskable , En_Edge_RX_Data , NA , UNMASK_WAKE , 9 , SCI , 0x4800 , NORTH ) , // SOC_WAKE_SCI_N - CHV_GPIO_PAD_CONF (L" N25:GPIO_SUS6 ", GPIO , M1 , GPI , NA , NA , Trig_Edge_Low , Line14 , NA , NA , NA , NonMaskable , En_Edge_RX_Data , NA , NA , 19 , SCI , 0x4850 , NORTH ) , // SOC_RUNTIME_SCI_N - CHV_GPIO_PAD_CONF (L" N18:GPIO_SUS7 ", GPIO , M1 , GPI , NA , NA , Trig_Edge_Low , Line15 , NA , NA , NA , NonMaskable , En_Edge_RX_Data , NA , NA , 12 , SMI , 0x4818 , NORTH ) , // SOC_EXTSMI_N - -}; +VOID +SAI_SettingOfGpioFamilies ( + GPIO_SAI_INIT* SAI_Conf_Data, + UINT32 familySize + ); + +VOID +BraswellCrBoardGpioConfigure ( + VOID + ); #endif + diff --git a/BraswellPlatformPkg/Board/BraswellCR/BoardInit/BoardInit.c b/BraswellPlatformPkg/Board/BraswellCR/BoardInit/BoardInit.c index c4c900840e..354867091f 100644 --- a/BraswellPlatformPkg/Board/BraswellCR/BoardInit/BoardInit.c +++ b/BraswellPlatformPkg/Board/BraswellCR/BoardInit/BoardInit.c @@ -23,246 +23,12 @@ #include #include #include +#include "BoardInit.h" +#include "BoardGpios.h" +#include "Dram.h" extern EFI_GUID gBswCrImageGuid; -UINT8 mBSW_CR_SpdDataMemorySolderDown[] = { - 0x92, //Byte 0 - 0x12, - 0x0b, - 0x03, - 0x04, //Byte 4 - 0x11, - 0x02, - 0x02, - 0x03, - 0x52, - 0x01, - 0x08, - 0x0a, - 0x00, - 0xfe, - 0x00, - 0x69, - 0x78, - 0x69, - 0x3c, - 0x69, //Byte20 - 0x11, - 0x18, - 0x81, - 0x00, - 0x05, - 0x3c, - 0x3c, - 0x01, - 0x40, - 0x83, - 0x01, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, //Byte40 - 0,0,0,0,0,0,0,0, - 0x00, - 0x00, - 0x00, - 0x00, - 0x0f, - 0x11, - 0x22, - 0x00, - 0,0,0,0,0,0,0,0, //Byte64 - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0x00, //Byte112 - 0x00, - 0x00, - 0x00, - 0x00, - 0x80, - 0xad, - 0x01, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00 //Byte 215 -}; - -CHV_GPIO_PAD_INIT mBSW_CR_GpioInitData[] = -// PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks -{ CHV_GPIO_PAD_CONF (L" N37:CX_PRDY_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x4C38 , NORTH ) , // PRDY_B - CHV_GPIO_PAD_CONF (L" N35:CX_PRDY_B_2 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x4C28 , NORTH ) , // CX_PRDY_B_2 - CHV_GPIO_PAD_CONF (L" N39:CX_PREQ_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x4858 , NORTH ) , // PREQ_B - CHV_GPIO_PAD_CONF (L" N48:GP_CAMERASB00 ", GPIO , M1 , GPIO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x5018 , NORTH ) , // UF_CORE_VR_EN - CHV_GPIO_PAD_CONF (L" N53:GP_CAMERASB01 ", GPIO , M1 , GPIO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x5040 , NORTH ) , // UF_IO_VR_EN - CHV_GPIO_PAD_CONF (L" N46:GP_CAMERASB02 ", GPIO , M1 , GPIO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x5008 , NORTH ) , // UF_ANALOG_VR_EN - CHV_GPIO_PAD_CONF (L" N51:GP_CAMERASB03 ", GPIO , M1 , GPIO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x5030 , NORTH ) , // WF_CORE_VR_EN - CHV_GPIO_PAD_CONF (L" N56:GP_CAMERASB04 ", GPIO , M1 , GPIO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x5058 , NORTH ) , // WF_IO_VR_EN - CHV_GPIO_PAD_CONF (L" N45:GP_CAMERASB05 ", GPIO , M1 , GPIO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x5000 , NORTH ) , // WF_ANALOG_VR_EN - CHV_GPIO_PAD_CONF (L" N49:GP_CAMERASB06 ", GPIO , M1 , GPIO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x5020 , NORTH ) , // WF_VCM_EN - CHV_GPIO_PAD_CONF (L" N54:GP_CAMERASB07 ", GPIO , M1 , GPIO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x5048 , NORTH ) , // FLASH_RESET_N - CHV_GPIO_PAD_CONF (L" N47:GP_CAMERASB08 ", GPIO , M1 , GPIO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x5010 , NORTH ) , // FLASH_TRIGGER - CHV_GPIO_PAD_CONF (L" N52:GP_CAMERASB09 ", GPIO , M1 , GPIO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x5038 , NORTH ) , // UF_CAM_RST_N - CHV_GPIO_PAD_CONF (L" N50:GP_CAMERASB10 ", GPIO , M1 , GPIO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x5028 , NORTH ) , // WF_CAM_RST_N - CHV_GPIO_PAD_CONF (L" N55:GP_CAMERASB11 ", GPIO , M1 , GPIO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x5050 , NORTH ) , // CAM_ACT_LED - CHV_GPIO_PAD_CONF (L" N00:GPIO_DFX0 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x4400 , NORTH ) , // - CHV_GPIO_PAD_CONF (L" N03:GPIO_DFX1 ", GPIO , M1 , GPIO , LOW , LOW , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 3 , NA , 0x4418 , NORTH ) , // GPS_WAKEUP - CHV_GPIO_PAD_CONF (L" N07:GPIO_DFX2 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x4438 , NORTH ) , // COMBO_GPS_RESET_N - CHV_GPIO_PAD_CONF (L" N01:GPIO_DFX3 ", GPIO , M1 , GPI , NA , NA , Trig_Edge_Low , Line2 , P_NONE , NA , NA , NonMaskable , En_Edge_RX_Data , Inv_TX_Enable , NA , NA , NA , 0x4408 , NORTH ) , // SYS_SHDN_N - CHV_GPIO_PAD_CONF (L" N05:GPIO_DFX4 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4428 , NORTH ) , // NGFF_MODEM_RESET_N - CHV_GPIO_PAD_CONF (L" N04:GPIO_DFX5 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4420 , NORTH ) , // WWAN_PWR_EN - CHV_GPIO_PAD_CONF (L" N08:GPIO_DFX6 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4440 , NORTH ) , // - CHV_GPIO_PAD_CONF (L" N07:GPIO_DFX7 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4410 , NORTH ) , // - CHV_GPIO_PAD_CONF (L" N06:GPIO_DFX8 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4430 , NORTH ) , // SOC_NGFF_WIFI_EN - CHV_GPIO_PAD_CONF (L" N19:GPIO_SUS1 ", Native , M6 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4820 , NORTH ) , // NGFF_WWAN_WAKE_GPIO_11_RD - CHV_GPIO_PAD_CONF (L" N24:GPIO_SUS2 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4848 , NORTH ) , // PROCHOT - CHV_GPIO_PAD_CONF (L" N17:GPIO_SUS3 ", GPIO , M1 , GPI , NA , NA , Trig_Edge_Low , Line4 , NA , NA , NA , NonMaskable , En_Edge_RX_Data , NA , NA , NA , NA , 0x4810 , NORTH ) , // I2S_IRQ_N - CHV_GPIO_PAD_CONF (L" N22:GPIO_SUS4 ", Native , M6 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4838 , NORTH ) , // PMU_WAKE_LAN_B - CHV_GPIO_PAD_CONF (L" N20:GPIO_SUS5 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4828 , NORTH ) , // WiFI_32k_CLK - CHV_GPIO_PAD_CONF (L" N71:HV_DDI0_DDC_SCL ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5458 , NORTH ) , // DDI1_HDMI_SOC_SCL - CHV_GPIO_PAD_CONF (L" N66:HV_DDI0_DDC_SDA ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5430 , NORTH ) , // DDI1_HDMI_SOC_SDA - CHV_GPIO_PAD_CONF (L" N61:HV_DDI0_HPD ", Native , M1 , NA , NA , NA , NA , NA , P_NONE , NA , NA , NA , NA , Inv_TX_Enable , NA , NA , NA , 0x5408 , NORTH ) , // DDI0_HPD_N - CHV_GPIO_PAD_CONF (L" N64:HV_DDI1_HPD ", Native , M1 , NA , NA , NA , NA , NA , P_NONE , NA , NA , NA , NA , Inv_TX_Enable , NA , NA , NA , 0x5420 , NORTH ) , // DDI1_HPD_N - CHV_GPIO_PAD_CONF (L" N67:HV_DDI2_DDC_SCL ", Native , M3 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5438 , NORTH ) , // DBG_UART3_TXD - CHV_GPIO_PAD_CONF (L" N62:HV_DDI2_DDC_SDA ", Native , M3 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5410 , NORTH ) , // DBG_UART3_RXD - CHV_GPIO_PAD_CONF (L" N65:PANEL0_BKLTCTL ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5428 , NORTH ) , // DDI0_BKLT_CTRL - CHV_GPIO_PAD_CONF (L" N60:PANEL0_BKLTEN ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5400 , NORTH ) , // DDI0_BKLT_EN - CHV_GPIO_PAD_CONF (L" N72:PANEL0_VDDEN ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5460 , NORTH ) , // DDI0_VDD_EN - CHV_GPIO_PAD_CONF (L" N63:PANEL1_BKLTCTL ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5418 , NORTH ) , // MATA_Adap_ctrl - CHV_GPIO_PAD_CONF (L" N32:PROCHOT_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C10 , NORTH ) , // VR_HOT_N - CHV_GPIO_PAD_CONF (L" N16:SEC_GPIO_SUS10 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4808 , NORTH ) , // I2C_RESERT_N_CONN - CHV_GPIO_PAD_CONF (L" N21:SEC_GPIO_SUS11 ", GPIO , M1 , GPI , NA , NA , Trig_Edge_Low , Line5 , NA , NA , NA , NonMaskable , En_Edge_RX_Data , NA , UNMASK_WAKE , 15 , NA , 0x4830 , NORTH ) , // KBC_INT - CHV_GPIO_PAD_CONF (L" N27:SEC_GPIO_SUS9 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , P_20K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x4860 , NORTH ) , // LAN_LED1 - CHV_GPIO_PAD_CONF (L" N31:TCK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C08 , NORTH ) , // JTAG - CHV_GPIO_PAD_CONF (L" N41:TDI ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C58 , NORTH ) , // - CHV_GPIO_PAD_CONF (L" N39:TDO ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C48 , NORTH ) , // - CHV_GPIO_PAD_CONF (L" N36:TDO_2 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C30 , NORTH ) , // - CHV_GPIO_PAD_CONF (L" N34:TMS ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C20 , NORTH ) , // - CHV_GPIO_PAD_CONF (L" N30:TRST_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C00 , NORTH ) , // -// East Community -// PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks - CHV_GPIO_PAD_CONF (L" E21: MF_ISH_GPIO_0 ", Native , M1 , NA , NA , NA , NA , NA , P_5K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x4830 , EAST ) , // acce_1 - CHV_GPIO_PAD_CONF (L" E18: MF_ISH_GPIO_1 ", Native , M1 , NA , NA , NA , NA , NA , P_5K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x4818 , EAST ) , // acce_2 - CHV_GPIO_PAD_CONF (L" E24: MF_ISH_GPIO_2 ", Native , M1 , NA , NA , NA , NA , NA , P_5K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x4848 , EAST ) , // compass - CHV_GPIO_PAD_CONF (L" E15: MF_ISH_GPIO_3 ", Native , M1 , NA , NA , NA , NA , NA , P_5K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x4800 , EAST ) , // Gyro_1 - CHV_GPIO_PAD_CONF (L" E22: MF_ISH_GPIO_4 ", GPIO , M1 , GPI , NA , NA , Trig_Level , Line0 , P_20K_H , NA , NA , NonMaskable , En_RX_Data ,Inv_RX_Data, NA , 19 , NA , 0x4838 , EAST ) , // SENSOR_HUB_R_INT || Alt_1 - CHV_GPIO_PAD_CONF (L" E19: MF_ISH_GPIO_5 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA ,No_Inversion , NA , NA , NA , 0x4820 , EAST ) , // SENS_HUB_RST_N || Alt_2 - CHV_GPIO_PAD_CONF (L" E25: MF_ISH_GPIO_6 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4850 , EAST ) , // ALS - CHV_GPIO_PAD_CONF (L" E16: MF_ISH_GPIO_7 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA ,No_Inversion , NA , NA , NA , 0x4808 , EAST ) , // SENS_HUB_WAKE || Prox - CHV_GPIO_PAD_CONF (L" E23: MF_ISH_GPIO_8 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4840 , EAST ) , // SAR - CHV_GPIO_PAD_CONF (L" E20: MF_ISH_GPIO_9 ", Native , M1 , NA , NA , NA , NA , NA , P_5K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x4828 , EAST ) , // Gyro_2 - CHV_GPIO_PAD_CONF (L" E04: PMU_AC_PRESENT ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4420 , EAST ) , // AC_PRESENT - CHV_GPIO_PAD_CONF (L" E01:PMU_BATLOW_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4408 , EAST ) , // PMU_BATLOW_N - CHV_GPIO_PAD_CONF (L" E05:PMU_PLTRST_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4428 , EAST ) , // PLT_RST_N - CHV_GPIO_PAD_CONF (L" E08:PMU_PWRBTN_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4440 , EAST ) , // SOC_PWRBTN_N - CHV_GPIO_PAD_CONF (L" E03:PMU_SLP_S0IX_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4418 , EAST ) , // SLP_S0IX_N - CHV_GPIO_PAD_CONF (L" E00:PMU_SLP_S3_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4400 , EAST ) , // SLP_S3_N - CHV_GPIO_PAD_CONF (L" E09:PMU_SLP_S4_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4448 , EAST ) , // SLP_S4_N - CHV_GPIO_PAD_CONF (L" E06:PMU_SUSCLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4430 , EAST ) , // SLEEP_CLK - CHV_GPIO_PAD_CONF (L" E10:PMU_WAKE_B ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x4450 , EAST ) , // PMU_WAKE_N - CHV_GPIO_PAD_CONF (L" E11:PMU_WAKE_LAN_B ", GPIO , M1 , GPI , NA , NA , Trig_Edge_Low , Line2 , NA , NA , NA , NonMaskable , En_Edge_RX_Data , Inv_RX_Data , UNMASK_WAKE , 11 , NA , 0x4458 , EAST ) , // PMU_WAKE_LAN_N - CHV_GPIO_PAD_CONF (L" E02:SUS_STAT_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4410 , EAST ) , // TBD -// South East Community -// PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks - CHV_GPIO_PAD_CONF (L" SE16:SDMMC1_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4808 , SOUTHEAST ) , // SDMMC1_CLK - CHV_GPIO_PAD_CONF (L" SE23:SDMMC1_CMD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4840 , SOUTHEAST ) , // SDMMC1_CMD - CHV_GPIO_PAD_CONF (L" SE17:SDMMC1_D0 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x4810 , SOUTHEAST ) , // SDMMC1_D_0 - CHV_GPIO_PAD_CONF (L" SE24:SDMMC1_D1 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4848 , SOUTHEAST ) , // SDMMC1_D_1 - CHV_GPIO_PAD_CONF (L" SE20:SDMMC1_D2 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4828 , SOUTHEAST ) , // SDMMC1_D_2 - CHV_GPIO_PAD_CONF (L" SE26:SDMMC1_D3_CD_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4858 , SOUTHEAST ) , // SDMMC1_D_3_CD_B - CHV_GPIO_PAD_CONF (L" SE67:MMC1_D4_SD_WE ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5438 , SOUTHEAST ) , // MMC1_D4 - CHV_GPIO_PAD_CONF (L" SE65:MMC1_D5 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5428 , SOUTHEAST ) , // MMC1_D5 - CHV_GPIO_PAD_CONF (L" SE63:MMC1_D6 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5418 , SOUTHEAST ) , // MMC1_D6 - CHV_GPIO_PAD_CONF (L" SE68:MMC1_D7 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5440 , SOUTHEAST ) , // MMC1_D7 - CHV_GPIO_PAD_CONF (L" SE84:MC1_RCLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5448 , SOUTHEAST ) , // SDMMC1_RCLK - CHV_GPIO_PAD_CONF (L" SE77:GPIO_ALERT ", GPIO , M1 , GPI , NA , NA , Trig_Level , Line1 , NA , NA , NA , NonMaskable , En_RX_Data , Inv_RX_Data , NA , 46 , NA , 0x5810 , SOUTHEAST ) , // TCH_PADCONN_INT_N - CHV_GPIO_PAD_CONF (L" SE79:ILB_SERIRQ ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5820 , SOUTHEAST ) , // ILB_SERIRQ - CHV_GPIO_PAD_CONF (L" SE51:MF_LPC_CLKOUT0 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5030 , SOUTHEAST ) , // MF_LPC_CLKOUT0 - CHV_GPIO_PAD_CONF (L" SE47:MF_LPC_AD0 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5010 , SOUTHEAST ) , // MF_LPC_AD0 - CHV_GPIO_PAD_CONF (L" SE52:MF_LPC_AD1 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5038 , SOUTHEAST ) , // MF_LPC_AD1 - CHV_GPIO_PAD_CONF (L" SE45:MF_LPC_AD2 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5000 , SOUTHEAST ) , // MF_LPC_AD2 - CHV_GPIO_PAD_CONF (L" SE50:MF_LPC_AD3 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5028 , SOUTHEAST ) , // MF_LPC_AD3 - CHV_GPIO_PAD_CONF (L" SE46:LPC_CLKRUNB ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5008 , SOUTHEAST ) , // LPC_CLKRUNB - CHV_GPIO_PAD_CONF (L" SE48:LPC_FRAMEB ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5018 , SOUTHEAST ) , // LPC_FRAMEB - CHV_GPIO_PAD_CONF (L" SE00:MF_PLT_CLK0 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4400 , SOUTHEAST ) , // Camera1_clock - CHV_GPIO_PAD_CONF (L" SE02:MF_PLT_CLK1 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4410 , SOUTHEAST ) , // Camera2_clock - CHV_GPIO_PAD_CONF (L" SE07:MF_PLT_CLK2 ", GPIO , M1 , GPI , NA , LOW , Trig_Level , Line2 , NA , NA , NA , NonMaskable , En_RX_Data , NA , NA , NA , NA , 0x4438 , SOUTHEAST ) , // GPS_HOSTREQ - CHV_GPIO_PAD_CONF (L" SE04:MF_PLT_CLK3 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4420 , SOUTHEAST ) , // I2S_MCLK - CHV_GPIO_PAD_CONF (L" SE03:MF_PLT_CLK4 ", Native , M3 , NA , NA , LOW , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4418 , SOUTHEAST ) , // I2C0_ISF_SDA - CHV_GPIO_PAD_CONF (L" SE06:MF_PLT_CLK5 ", Native , M3 , NA , NA , LOW , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4430 , SOUTHEAST ) , // COMBO_GPS_RESET_N - CHV_GPIO_PAD_CONF (L" SE76:PMU_RSTBUTTON_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5808 , SOUTHEAST ) , // SOC_RESETBTN_N - CHV_GPIO_PAD_CONF (L" SE83:SUSPWRDNACK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5840 , SOUTHEAST ) , // SUSPWRDNACK - CHV_GPIO_PAD_CONF (L" SE05:PWM0 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4428 , SOUTHEAST ) , // HAPTIC0, - CHV_GPIO_PAD_CONF (L" SE01:PWM1 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4408 , SOUTHEAST ) , // WIFI_PCIE_RST_N - CHV_GPIO_PAD_CONF (L" SE85:SDMMC3_1P8_EN ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5850 , SOUTHEAST ) , // SD_CARD_PWR_EN - CHV_GPIO_PAD_CONF (L" SE81:SDMMC3_CD_B ", GPIO , M1 , GPI , NA , NA , Trig_Level , NA , NA , NA , NA , NA , En_Edge_RX_Data , NA , NA , NA , NA , 0x5830 , SOUTHEAST ) , // SD_CARD_DET_N - CHV_GPIO_PAD_CONF (L" SE31:SDMMC3_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C08 , SOUTHEAST ) , // SD_CARD_CLK - CHV_GPIO_PAD_CONF (L" SE34:SDMMC3_CMD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C20 , SOUTHEAST ) , // SD_CARD_CMD - CHV_GPIO_PAD_CONF (L" SE35:SDMMC3_D0 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C28 , SOUTHEAST ) , // SD_CARD_D0 - CHV_GPIO_PAD_CONF (L" SE30:SDMMC3_D1 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C00 , SOUTHEAST ) , // SD_CARD_D1 - CHV_GPIO_PAD_CONF (L" SE33:SDMMC3_D2 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C18 , SOUTHEAST ) , // SD_CARD_D2 - CHV_GPIO_PAD_CONF (L" SE32:SDMMC3_D3 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C10 , SOUTHEAST ) , // SD_CARD_D3 - CHV_GPIO_PAD_CONF (L" SE78:SDMMC3_PWR_EN_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5818 , SOUTHEAST ) , // SD_CARD_PWRDN_N - CHV_GPIO_PAD_CONF (L" SE62:SPI1_CLK ", GPIO , M1 , GPI , NA , NA , Trig_Edge_Low , Line4 , NA , NA , NA , NonMaskable , En_Edge_RX_Data , NA , NA , NA , NA , 0x5410 , SOUTHEAST ) , // SOC_THERM_SENSOR_ALERT_N - CHV_GPIO_PAD_CONF (L" SE61:SPI1_CS0_B ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5408 , SOUTHEAST ) , // CS_WAKE_N - CHV_GPIO_PAD_CONF (L" SE66:SPI1_CS1_B ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5430 , SOUTHEAST ) , // SPI_CS for NFC - CHV_GPIO_PAD_CONF (L" SE60:SPI1_MISO ", GPIO , M1 , GPI , NA , NA , Trig_Edge_Low , Line5 , P_20K_H , _ENABLE , NA , NonMaskable , En_RX_Data , Inv_RX_Enable , UNMASK_WAKE , 34 , NA , 0x5400 , SOUTHEAST ) , // PMIC_IRQ_1P8 - CHV_GPIO_PAD_CONF (L" SE64:SPI1_MOSI ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5420 , SOUTHEAST ) , // WIFI_RST_GPIO - CHV_GPIO_PAD_CONF (L" SE80:USB_OC0_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5828 , SOUTHEAST ) , // USB2_OC0_N - CHV_GPIO_PAD_CONF (L" SE75:USB_OC1_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5800 , SOUTHEAST ) , // USB3_OC_N - -// South west Community -// PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks - CHV_GPIO_PAD_CONF (L" SW02:FST_SPI_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4410 , SOUTHWEST ) , // FAST_SPI_CLK - CHV_GPIO_PAD_CONF (L" SW06:FST_SPI_CS0_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4430 , SOUTHWEST ) , // FST_SPI_CS0_N( SPI NOR) - CHV_GPIO_PAD_CONF (L" SW04:FST_SPI_CS1_B ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4420 , SOUTHWEST ) , // RF_KILL_GPS_N_1P8 - CHV_GPIO_PAD_CONF (L" SW07:FST_SPI_CS2_B ", GPIO , M1 , GPO , LOW , NA , NA , NA , P_5K_L , NA , NA , NA , NA , NA , NA , NA , NA , 0x4438 , SOUTHWEST ) , // TCH_PNL_MODE_SEL - CHV_GPIO_PAD_CONF (L" SW01:FST_SPI_D0 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4408 , SOUTHWEST ) , // FST_SPI_D0 - CHV_GPIO_PAD_CONF (L" SW05:FST_SPI_D1 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4428 , SOUTHWEST ) , // FST_SPI_D1 - CHV_GPIO_PAD_CONF (L" SW00:FST_SPI_D2 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4400 , SOUTHWEST ) , // FST_SPI_D2 - CHV_GPIO_PAD_CONF (L" SW03:FST_SPI_D3 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4418 , SOUTHWEST ) , // FST_SPI_D3 - CHV_GPIO_PAD_CONF (L" SW30:MF_HDA_CLK ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , NA , NA , 0x4C00 , SOUTHWEST ) , // MF_HDA_CLK II GP_SSP_0_I2S_TXD - CHV_GPIO_PAD_CONF (L" SW37:MF_HDA_DOCKENB ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C38 , SOUTHWEST ) , // I2S_2_RXD_R_AICO(AIC) - CHV_GPIO_PAD_CONF (L" SW34:MF_HDA_DOCKRSTB ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C20 , SOUTHWEST ) , // I2S_2_TXD_R_AICO (AIC) - CHV_GPIO_PAD_CONF (L" SW31:MF_HDA_RSTB ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C08 , SOUTHWEST ) , // AUD_LINK_RST_N || I2S_0_CLK_R_AICO (AIC) - CHV_GPIO_PAD_CONF (L" SW32:MF_HDA_SDI0 ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C10 , SOUTHWEST ) , // AUD_LINK_SDI0 (ALC282) || I2S_2_CLK_R_AICO (AIC) - CHV_GPIO_PAD_CONF (L" SW36:MF_HDA_SDI1 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C30 , SOUTHWEST ) , // I2S_2_FS_R_AICO - CHV_GPIO_PAD_CONF (L" SW33:MF_HDA_SDO ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C18 , SOUTHWEST ) , // AUD_LINK_SDO_R||I2S_0_RXD_R_AICO (AIC) - CHV_GPIO_PAD_CONF (L" SW35:MF_HDA_SYNC ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x4C28 , SOUTHWEST ) , // AUD_LINKSYNC_R|| I2S_0_FS_R_AICO (AIC) - CHV_GPIO_PAD_CONF (L" SW22:UART2_CTS_B ", Native , M1 , NA , NA , NA , NA , NA , P_NONE , NA , NA , NA , NA , NA , NA , NA , NA , 0x4838 , SOUTHWEST ) , // UART2_GPS_CTS (GPS)|| UART2_GPS_CTS_CONN (AIC) - CHV_GPIO_PAD_CONF (L" SW19:UART2_RTS_B ", Native , M1 , NA , NA , NA , NA , NA , P_NONE , NA , NA , NA , NA , NA , NA , NA , NA , 0x4820 , SOUTHWEST ) , // UART2_GPS_RTS (GPS)|| UART2_GPS_RTS_CONN (AIC) - CHV_GPIO_PAD_CONF (L" SW17:UART2_RXD ", Native , M1 , NA , NA , NA , NA , NA , P_NONE , NA , NA , NA , NA , NA , NA , NA , NA , 0x4810 , SOUTHWEST ) , // UART2_GPS_RXD (GPS)|| UART2_GPS_RXD_CONN(AIC) - CHV_GPIO_PAD_CONF (L" SW21:UART2_TXD ", Native , M1 , NA , NA , NA , NA , NA , P_NONE , NA , NA , NA , NA , NA , NA , NA , NA , 0x4830 , SOUTHWEST ) , // UART2_GPS_TXD(GPS)|| UART2_GPS_TXD_CONN(AIC) - CHV_GPIO_PAD_CONF (L" SW65:I2C0_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x5428 , SOUTHWEST ) , // 3rd party Sensor Card - CHV_GPIO_PAD_CONF (L" SW61:I2C0_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x5408 , SOUTHWEST ) , // 3rd party Sensor Card - CHV_GPIO_PAD_CONF (L" SW63:I2C1_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x5418 , SOUTHWEST ) , // PMIC - CHV_GPIO_PAD_CONF (L" SW60:I2C1_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x5400 , SOUTHWEST ) , // PMIC - CHV_GPIO_PAD_CONF (L" SW66:I2C2_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x5430 , SOUTHWEST ) , // MIPI_CSI CAMERAS, FLASH - CHV_GPIO_PAD_CONF (L" SW62:I2C2_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x5410 , SOUTHWEST ) , // MIPI_CSI CAMERAS, FLASH - CHV_GPIO_PAD_CONF (L" SW67:I2C3_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x5438 , SOUTHWEST ) , // MIPI_CSI CAMERAS, FLASH - CHV_GPIO_PAD_CONF (L" SW64:I2C3_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x5420 , SOUTHWEST ) , // MIPI_CSI CAMERAS, FLASH - CHV_GPIO_PAD_CONF (L" SW50:I2C4_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x5028 , SOUTHWEST ) , // I2C Audio | Touch PAD - CHV_GPIO_PAD_CONF (L" SW46:I2C4_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x5008 , SOUTHWEST ) , // I2C Audio | Touch PAD - CHV_GPIO_PAD_CONF (L" SW48:I2C5_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x5018 , SOUTHWEST ) , // Touch Panel - CHV_GPIO_PAD_CONF (L" SW45:I2C5_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x5000 , SOUTHWEST ) , // Touch Panel - CHV_GPIO_PAD_CONF (L" SW51:I2C6_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x5030 , SOUTHWEST ) , // INA Decice - CHV_GPIO_PAD_CONF (L" SW47:I2C6_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , NA , NA , NA , NA , 0x5010 , SOUTHWEST ) , // INA Device - CHV_GPIO_PAD_CONF (L" SW90:PCIE_CLKREQ0B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5C00 , SOUTHWEST ) , // RTL8111G (CLKREQ_N) - CHV_GPIO_PAD_CONF (L" SW91:PCIE_CLKREQ1B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5C08 , SOUTHWEST ) , // NGFF(CLKREQ_N) - CHV_GPIO_PAD_CONF (L" SW93:PCIE_CLKREQ2B ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5C18 , SOUTHWEST ) , // NGFF_WWAN_RF_KILL_1P8_N (Active low) - CHV_GPIO_PAD_CONF (L" SW95:PCIE_CLKREQ3B ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5C28 , SOUTHWEST ) , // Tied to Micro SD - CHV_GPIO_PAD_CONF (L" SW75:SATA_GP0 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5800 , SOUTHWEST ) , // TOUCH_PNL_RST_N - CHV_GPIO_PAD_CONF (L" SW76:SATA_GP1 ", GPIO , M1 , GPI , NA , NA , Trig_Level , Line0 , P_1K_H , NA , NA , NonMaskable , NA , Inv_RX_Data , NA , 41 , NA , 0x5808 , SOUTHWEST ) , // TOUCH_INT_N - CHV_GPIO_PAD_CONF (L" SW78:SATA_GP2 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5818 , SOUTHWEST ) , // SATA_DEVSLP_R - CHV_GPIO_PAD_CONF (L" SW80:SATA_GP3 ", Native , M1 , GPIO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5828 , SOUTHWEST ) , // eMMC_RST_N - CHV_GPIO_PAD_CONF (L" SW77:SATA_LEDN ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5810 , SOUTHWEST ) , // SATA_LED_N -}; - - EFI_STATUS GetBoardFabIdsKsc ( @@ -329,39 +95,72 @@ BraswellCRBoardDetectionCallback ( if (Status == EFI_SUCCESS) { FabId = (UINT8) BoardFabIds & 0x07; BoardId = (UINT8) ((BoardFabIds & 0x0F00) >> 8); - DEBUG ((EFI_D_INFO, "BoardID detected = %d\n", BoardId)); + if ((BoardId == 0x07)|| (BoardId == 0x06)) { + + // + // Collect board specific configuration for Braswell CR. + // + + // + // ID + // PlatformInfoHob.BoardId = BOARD_ID_BSW_CR; - PlatformInfoHob.BoardSvidConfig = BSW_I2C_PMIC_CONFIG; - DEBUG ((EFI_D_INFO, "I'm BrasWell CR \n\n")); - PlatformInfoHob.MemCfgID = 0; - DEBUG ((EFI_D_INFO, "PlatformInfoHob->MemCfgID= 0x%x\n", PlatformInfoHob.MemCfgID)); PlatformInfoHob.FABID = FabId; - DEBUG ((EFI_D_INFO, "PlatformInfoHob->FABID = 0x%x\n", FabId )); - PlatformInfoHob.PlatformFlavor = FlavorMobile; - DEBUG ((EFI_D_INFO, "PlatformInfoHob->PlatformFlavor = 0x%x\n", PlatformInfoHob.PlatformFlavor )); - DEBUG ((EFI_D_INFO, "PlatformInfoHob->BoardSvidConfig = 0x%x\n", PlatformInfoHob.BoardSvidConfig )); - DEBUG ((EFI_D_INFO, "PlatformInfoHob->BoardId = 0x%x\n", PlatformInfoHob.BoardId )); + PlatformInfoHob.PlatformFlavor = FlavorMobile; + + // + // Memory + // + PlatformInfoHob.MemCfgID = 0; + PcdSet8 (PcdOemMemeoryDimmType,SolderDownMemory); + PcdSet64 (PcdMemorySpdPtr, (UINT64)(UINTN)&mBSW_CR_SpdDataMemorySolderDown); + // + // EC, Fan, Battery + // PlatformInfoHob.ECSupport = TRUE; PlatformInfoHob.FanSupport = TRUE; PlatformInfoHob.BatterySupport = TRUE; - DataSize = sizeof (EFI_PLATFORM_INFO_HOB); - PcdSetPtr (PcdPlatformInfo, &DataSize, &PlatformInfoHob); - + // + // Graphic, Video, Diaplay + // DataSize = sizeof (EFI_GUID); PcdSetPtr (PcdBmpImageGuid, &DataSize, &gBswCrImageGuid); + // + // Power + // + PlatformInfoHob.BoardSvidConfig = BSW_I2C_PMIC_CONFIG; + + // + // Communication + // PcdSet8 (PcdNfcConnection, 1); - PcdSet8 (PcdOemMemeoryDimmType,SolderDownMemory); - PcdSet64 (PcdMemorySpdPtr, (UINT64)(UINTN)&mBSW_CR_SpdDataMemorySolderDown); + // + // GPIO + // + BraswellCrBoardGpioConfigure(); + PcdSet64 (PcdGpioInitFunc, (UINT64)(UINTN)BraswellCRGpioLateInit); - // Program all the gpios at this moment - InternalGpioPADConfig(0, sizeof(mBSW_CR_GpioInitData)/sizeof(mBSW_CR_GpioInitData[0]), mBSW_CR_GpioInitData); + // + // Expose EFI_PLATFORM_INFO_HOB. + // + DataSize = sizeof (EFI_PLATFORM_INFO_HOB); + PcdSetPtr (PcdPlatformInfo, &DataSize, &PlatformInfoHob); Status = PeiServicesInstallPpi (&mBraswellCRDetectedPpi); + + DEBUG ((EFI_D_INFO, "I'm BrasWell CR \n\n")); + DEBUG ((EFI_D_INFO, "PlatformInfoHob->MemCfgID= 0x%x\n", PlatformInfoHob.MemCfgID)); + DEBUG ((EFI_D_INFO, "BoardID detected = %d\n", BoardId)); + DEBUG ((EFI_D_INFO, "PlatformInfoHob->FABID = 0x%x\n", FabId )); + DEBUG ((EFI_D_INFO, "PlatformInfoHob->PlatformFlavor = 0x%x\n", PlatformInfoHob.PlatformFlavor )); + DEBUG ((EFI_D_INFO, "PlatformInfoHob->BoardSvidConfig = 0x%x\n", PlatformInfoHob.BoardSvidConfig )); + DEBUG ((EFI_D_INFO, "PlatformInfoHob->BoardId = 0x%x\n", PlatformInfoHob.BoardId )); + } } @@ -388,3 +187,4 @@ BraswellCRInitConstructor ( return Status; } + diff --git a/BraswellPlatformPkg/Board/BraswellCR/BoardInit/BoardInit.h b/BraswellPlatformPkg/Board/BraswellCR/BoardInit/BoardInit.h new file mode 100644 index 0000000000..ee64703e09 --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCR/BoardInit/BoardInit.h @@ -0,0 +1,37 @@ +/** @file + GPIO setting for CherryView. + + This file includes package header files, library classes. + + Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _BOARDINIT_H_ +#define _BOARDINIT_H_ + +#include +#include "PchAccess.h" +#include "PlatformBaseAddresses.h" +#include +#include +#include +#include +#include +#include + + +VOID +BraswellCRGpioLateInit ( + VOID + ); +#endif + diff --git a/BraswellPlatformPkg/Board/BraswellCR/BoardInit/BoardInit.inf b/BraswellPlatformPkg/Board/BraswellCR/BoardInit/BoardInit.inf index ab9e4bb341..1f47ed0337 100644 --- a/BraswellPlatformPkg/Board/BraswellCR/BoardInit/BoardInit.inf +++ b/BraswellPlatformPkg/Board/BraswellCR/BoardInit/BoardInit.inf @@ -25,6 +25,7 @@ [Sources] BoardInit.c + BoardGpios.c [LibraryClasses] PeiServicesLib @@ -51,6 +52,12 @@ ## SOMETIMES_PRODUCES gEfiEdkIIPlatformTokenSpaceGuid.PcdOemMemeoryDimmType + ## SOMETIMES_CONSUMES + gEfiEdkIIPlatformTokenSpaceGuid.PcdPlatformInfo + + ## SOMETIMES_PRODUCES + gEfiEdkIIPlatformTokenSpaceGuid.PcdGpioInitFunc + [Guids] ## SOMETIMES_CONSUMES gBswCrImageGuid @@ -63,5 +70,3 @@ ## SOMETIMES_CONSUMES gBoardDetectedPpiGuid - - diff --git a/BraswellPlatformPkg/Board/BraswellCR/BoardInit/BoardInitLate.c b/BraswellPlatformPkg/Board/BraswellCR/BoardInit/BoardInitLate.c deleted file mode 100644 index da64e0f30f..0000000000 --- a/BraswellPlatformPkg/Board/BraswellCR/BoardInit/BoardInitLate.c +++ /dev/null @@ -1,73 +0,0 @@ -/** @file - PCH GPIO Porting driver. - - Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php. - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "BoardGpios.h" - -VOID -SAI_SettingOfGpioFamilies ( - GPIO_SAI_INIT* SAI_Conf_Data, - UINT32 familySize - ); - -VOID -BraswellCRGpioLateInit ( - VOID - ) -{ - - DEBUG ((EFI_D_ERROR, "Programming BSW CR Board Gpio Tables which are not done properly by FSP...\n")); - - // PAD programming to initialize GPIOs with SCI/SMI support, which depends on FSP PchInit to program basic chipset resources. - InternalGpioPADConfig(0, sizeof(mBSW_CR_GpioInitData_N)/sizeof(mBSW_CR_GpioInitData_N[0]), mBSW_CR_GpioInitData_N); - - // GPIO lock if really want - SAI_SettingOfGpioFamilies(mBSW_GPIO_SAI_Init_East, sizeof(mBSW_GPIO_SAI_Init_East)/sizeof(mBSW_GPIO_SAI_Init_East[0])); - SAI_SettingOfGpioFamilies(mBSW_GPIO_SAI_Init_North, sizeof(mBSW_GPIO_SAI_Init_North)/sizeof(mBSW_GPIO_SAI_Init_North[0])); - SAI_SettingOfGpioFamilies(mBSW_GPIO_SAI_Init_SouthEast, sizeof(mBSW_GPIO_SAI_Init_SouthEast)/sizeof(mBSW_GPIO_SAI_Init_SouthEast[0])); - SAI_SettingOfGpioFamilies(mBSW_GPIO_SAI_Init_SouthWest, sizeof(mBSW_GPIO_SAI_Init_SouthWest)/sizeof(mBSW_GPIO_SAI_Init_SouthWest[0])); -} - -/** - This function performs Board initialization in Pre-Memory. - - @retval EFI_SUCCESS The PPI is installed and initialized. - @retval EFI ERRORS The PPI is not successfully installed. - @retval EFI_OUT_OF_RESOURCES No enough resoruces (such as out of memory). -**/ -EFI_STATUS -EFIAPI -BraswellCRInitLateConstructor ( - IN EFI_PEI_FILE_HANDLE FileHandle, - IN CONST EFI_PEI_SERVICES **PeiServices - ) -{ - EFI_PLATFORM_INFO_HOB *PlatformInfoHob; - - PlatformInfoHob = PcdGetPtr (PcdPlatformInfo); - if (PlatformInfoHob->BoardId == BOARD_ID_BSW_CR) { - PcdSet64 (PcdGpioInitFunc, (UINT64)(UINTN)BraswellCRGpioLateInit); - } - - return EFI_SUCCESS; -} diff --git a/BraswellPlatformPkg/Board/BraswellCR/BoardInit/BoardInitLate.inf b/BraswellPlatformPkg/Board/BraswellCR/BoardInit/BoardInitLate.inf deleted file mode 100644 index 7478bdb19d..0000000000 --- a/BraswellPlatformPkg/Board/BraswellCR/BoardInit/BoardInitLate.inf +++ /dev/null @@ -1,51 +0,0 @@ -## @file -# GPIO porting module for Intel(R) Atom(TM) x5 Processor Series. -# -# This module will do the basic PCH GPIO porting. -# -# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.
-# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php. -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -## - -[Defines] - INF_VERSION = 0x00010017 - BASE_NAME = BraswellCRInitLate - FILE_GUID = DF215B49-F8A3-49E4-B5BE-C508384762F3 - VERSION_STRING = 1.0 - MODULE_TYPE = PEIM - CONSTRUCTOR = BraswellCRInitLateConstructor - -[Sources] - BoardInitLate.c - -[LibraryClasses] - PeiServicesLib - PcdLib - -[Packages] - MdePkg/MdePkg.dec - BraswellPlatformPkg/BraswellPlatformPkg.dec - ChvRefCodePkg/ChvRefCodePkg.dec - -[Pcd] - ## SOMETIMES_CONSUMES - gEfiEdkIIPlatformTokenSpaceGuid.PcdPlatformInfo - - ## SOMETIMES_PRODUCES - gEfiEdkIIPlatformTokenSpaceGuid.PcdGpioInitFunc - -[Ppis] - ## NOTIFY - gBoardDetectionStartPpiGuid - - ## SOMETIMES_PRODUCES - ## SOMETIMES_CONSUMES - gBoardDetectedPpiGuid diff --git a/BraswellPlatformPkg/Board/BraswellCR/BoardInit/BraswellCRInitExtra.uni b/BraswellPlatformPkg/Board/BraswellCR/BoardInit/BraswellCRInitExtra.uni deleted file mode 100644 index 2dfb11d02b..0000000000 --- a/BraswellPlatformPkg/Board/BraswellCR/BoardInit/BraswellCRInitExtra.uni +++ /dev/null @@ -1,18 +0,0 @@ -// /** @file -// BraswellCRInit Localized Strings and Content -// -// Copyright (c) 2015, Intel Corporation. All rights reserved.
-// -// This program and the accompanying materials -// are licensed and made available under the terms and conditions of the BSD License -// which accompanies this distribution. The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php. -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -// -// **/ - -#string STR_PROPERTIES_MODULE_NAME #language en-US "Intel® Atom™ x5 Processor Series Init module" - - diff --git a/BraswellPlatformPkg/Board/BraswellCR/BoardInit/BraswellCRInitLateExtra.uni b/BraswellPlatformPkg/Board/BraswellCR/BoardInit/BraswellCRInitLateExtra.uni deleted file mode 100644 index a0be4d32af..0000000000 --- a/BraswellPlatformPkg/Board/BraswellCR/BoardInit/BraswellCRInitLateExtra.uni +++ /dev/null @@ -1,18 +0,0 @@ -// /** @file -// BraswellCRInitLate Localized Strings and Content -// -// Copyright (c) 2015, Intel Corporation. All rights reserved.
-// -// This program and the accompanying materials -// are licensed and made available under the terms and conditions of the BSD License -// which accompanies this distribution. The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php. -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -// -// **/ - -#string STR_PROPERTIES_MODULE_NAME #language en-US "Intel® Atom™ x5 Processor Series Init Late module" - - diff --git a/BraswellPlatformPkg/Board/BraswellCR/BoardInit/Dram.h b/BraswellPlatformPkg/Board/BraswellCR/BoardInit/Dram.h new file mode 100644 index 0000000000..30e88ea068 --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCR/BoardInit/Dram.h @@ -0,0 +1,82 @@ +/** @file + DRAM setting for CherryView. + + This file includes package header files, library classes. + + Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +UINT8 mBSW_CR_SpdDataMemorySolderDown[] = { + 0x92, //Byte 0 + 0x12, + 0x0b, + 0x03, + 0x04, //Byte 4 + 0x11, + 0x02, + 0x02, + 0x03, + 0x52, + 0x01, + 0x08, + 0x0a, + 0x00, + 0xfe, + 0x00, + 0x69, + 0x78, + 0x69, + 0x3c, + 0x69, //Byte20 + 0x11, + 0x18, + 0x81, + 0x00, + 0x05, + 0x3c, + 0x3c, + 0x01, + 0x40, + 0x83, + 0x01, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, //Byte40 + 0,0,0,0,0,0,0,0, + 0x00, + 0x00, + 0x00, + 0x00, + 0x0f, + 0x11, + 0x22, + 0x00, + 0,0,0,0,0,0,0,0, //Byte64 + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0x00, //Byte112 + 0x00, + 0x00, + 0x00, + 0x00, + 0x80, + 0xad, + 0x01, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00 //Byte 215 +}; diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Acpi.c b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Acpi.c index 089a1d7daa..8a1878b625 100644 --- a/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Acpi.c +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Acpi.c @@ -259,3 +259,4 @@ InstallAcpiBraswellCherryHill ( return EFI_SUCCESS; } + diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Camera/Camera.asl b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Camera/Camera.asl index 256c4f3397..34a2a4b999 100644 --- a/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Camera/Camera.asl +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Camera/Camera.asl @@ -52,13 +52,13 @@ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings { - Name (SBUF, ResourceTemplate () // I2C Resource define + Name (SBUF, ResourceTemplate () // I2C Resource define { GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.GPO1", 0x00, ResourceConsumer, , ) { // Pin list - 0x0035 // N"53" DOVDD18 + 0x0035 // N"53" DOVDD18 } GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.GPO1", 0x00, ResourceConsumer, , @@ -72,8 +72,8 @@ { // Pin list 0x0034 // N"52" RESET } - - GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, + + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.GPO1", 0x00, ResourceConsumer, , ) { // Pin list @@ -175,33 +175,33 @@ { Return ("BSW") } - + // Dsm2PlatformSubStr If(LEqual(Arg0, ToUUID("647A6CA2-8B29-49AC-8806-D58B3D2D3EF5"))) { Return ("FFD") } - + // Dsm2SiliconStr If(LEqual(Arg0, ToUUID("A6E922A1-F7B3-4399-B56A-406AE416843B"))) { Return ("BSW") } - + // Dsm2PlatformStr If(LEqual(Arg0, ToUUID("5960313B-0AB0-4940-8840-2CAFA420C015"))) { Return ("INTEL") } - + // Dsm2Info If(LEqual(Arg0, ToUUID("F486D39F-D657-484B-84A6-42A565712B92"))) { Return (Buffer (32) { 0x01, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x07, 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x07, 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }) } @@ -234,21 +234,21 @@ Return (0x04) } - If (LEqual (Arg2, 0x02)) + If (LEqual (Arg2, 0x02)) { Return (0x01003507) // 1.8V } - If (LEqual (Arg2, 0x03)) + If (LEqual (Arg2, 0x03)) { Return (0x01002E08) // 2.8V } - If (LEqual (Arg2, 0x04)) + If (LEqual (Arg2, 0x04)) { Return (0x01003400) // RESET } - If (LEqual (Arg2, 0x05)) + If (LEqual (Arg2, 0x05)) { Return (0x01003001) // 1.2V } diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Camera/Camera2.asl b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Camera/Camera2.asl index 4d14a7c334..31a2ab7e11 100644 --- a/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Camera/Camera2.asl +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Device/Camera/Camera2.asl @@ -311,7 +311,7 @@ Return(0x00) } } // End CAM2 - + // // Device STRA // @@ -455,25 +455,25 @@ "\\_SB.GPO1", 0x00, ResourceConsumer, , ) { // Pin list - 0x0032 // GPIO N"50" + 0x0032 // GPIO N"50" } GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.GPO1", 0x00, ResourceConsumer, , ) { // Pin list - 0x0033 // GPIO dvdd12 camerasb03 N"51" + 0x0033 // GPIO dvdd12 camerasb03 N"51" } GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.GPO1", 0x00, ResourceConsumer, , ) { // Pin list - 0x0038 // GPIO dvdd18 camerasb04 N"56" + 0x0038 // GPIO dvdd18 camerasb04 N"56" } GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.GPO1", 0x00, ResourceConsumer, , ) { // Pin list - 0x002D // GPIO avdd28 camerasb08 N"45" + 0x002D // GPIO avdd28 camerasb08 N"45" } GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.GPO1", 0x00, ResourceConsumer, , @@ -585,33 +585,33 @@ { Return ("BSW") } - + //Dsm2PlatformSubStr If(LEqual(Arg0, ToUUID("647A6CA2-8B29-49AC-8806-D58B3D2D3EF5"))) { Return ("FFD") } - + //Dsm2SiliconStr If(LEqual(Arg0, ToUUID("A6E922A1-F7B3-4399-B56A-406AE416843B"))) { Return ("BSW") } - + //Dsm2PlatformStr If(LEqual(Arg0, ToUUID("5960313B-0AB0-4940-8840-2CAFA420C015"))) { Return ("INTEL") } - + //Dsm2Info If(LEqual(Arg0, ToUUID("F486D39F-D657-484B-84A6-42A565712B92"))) { Return (Buffer (32) { 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02, 0x02, - 0x07, 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x07, 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }) } @@ -715,8 +715,8 @@ 0x002F } - GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, - "\\_SB.GPO1", 0x00, ResourceConsumer, , + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, + "\\_SB.GPO1", 0x00, ResourceConsumer, , ) { // Pin list 0x0037 //for camera led camerasb11 diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Ssdt.asl b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Ssdt.asl index a30fcf5bb4..353a29625d 100644 --- a/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Ssdt.asl +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/Acpi/Ssdt.asl @@ -17,7 +17,7 @@ DefinitionBlock ( "Ssdt.aml", "SSDT", 0x02, // revision. - // A Revision field value greater than or equal to 2 signifies that integers + // A Revision field value greater than or equal to 2 signifies that integers // declared within the Definition Block are to be evaluated as 64-bit values "INTEL", // OEM ID (6 byte string) "BSW_RH", // OEM table ID (8 byte string) @@ -30,7 +30,7 @@ DefinitionBlock ( Scope(\_GPE) { Method(_L17) - { + { // Clear the GPE23 Status Bit. Store(1,GP23) // Handle the external SCI Thermal Event. @@ -109,7 +109,7 @@ DefinitionBlock ( { include("Device/Nfc/Nxp1.asl") } - + Scope(\_SB.PCI0) { include("Device/Audio/Audio.asl") @@ -119,4 +119,4 @@ DefinitionBlock ( { include("Device/Wifi/Broadcom.asl") } -} +} \ No newline at end of file diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardGpios.c b/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardGpios.c new file mode 100644 index 0000000000..bbf0aa217b --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardGpios.c @@ -0,0 +1,433 @@ +/** @file + Board Init driver. + + Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "BoardGpios.h" + +// +// TBD: Need update to CH version +// +CHV_GPIO_PAD_INIT mBswCherryHillGpioInitData[] = +{ + // + // North Community + // Group Pin#: PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks + CHV_GPIO_PAD_CONF (L"N37: CX_PRDY_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 29 , NA , 0x4C38 , NORTH ) , // PRDY_B + CHV_GPIO_PAD_CONF (L"N35: CX_PRDY_B_2 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 27 , NA , 0x4C28 , NORTH ) , // CX_PRDY_B_2 + CHV_GPIO_PAD_CONF (L"N39: CX_PREQ_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 20 , NA , 0x4858 , NORTH ) , // PREQ_B + CHV_GPIO_PAD_CONF (L"N48: GP_CAMERASB00 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 37 , NA , 0x5018 , NORTH ) , // CAM_ACT_LED + CHV_GPIO_PAD_CONF (L"N53: GP_CAMERASB01 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 42 , NA , 0x5040 , NORTH ) , // FLASH_RESET_N + CHV_GPIO_PAD_CONF (L"N46: GP_CAMERASB02 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 35 , NA , 0x5008 , NORTH ) , // GPIO_FLHD_N + CHV_GPIO_PAD_CONF (L"N51: GP_CAMERASB03 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 40 , NA , 0x5030 , NORTH ) , // XDP_GP_CAMERASB03 + CHV_GPIO_PAD_CONF (L"N56: GP_CAMERASB04 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 45 , NA , 0x5058 , NORTH ) , // FLASH_TRIG + CHV_GPIO_PAD_CONF (L"N45: GP_CAMERASB05 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 34 , NA , 0x5000 , NORTH ) , // FLASH_TORCH + CHV_GPIO_PAD_CONF (L"N49: GP_CAMERASB06 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 38 , NA , 0x5020 , NORTH ) , // CAM1_PWRDWN + CHV_GPIO_PAD_CONF (L"N54: GP_CAMERASB07 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 43 , NA , 0x5048 , NORTH ) , // CAM2_PWRDWN + CHV_GPIO_PAD_CONF (L"N47: GP_CAMERASB08 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 36 , NA , 0x5010 , NORTH ) , // XDP_GP_CAMERASB08 + CHV_GPIO_PAD_CONF (L"N52: GP_CAMERASB09 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 41 , NA , 0x5038 , NORTH ) , // CAM_1_RST_N + CHV_GPIO_PAD_CONF (L"N50: GP_CAMERASB10 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 39 , NA , 0x5028 , NORTH ) , // CAM_2_RST_N + CHV_GPIO_PAD_CONF (L"N55: GP_CAMERASB11 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 44 , NA , 0x5050 , NORTH ) , // CAM_3_RST_N + CHV_GPIO_PAD_CONF (L"N00: GPIO_DFX0 ", Native , M5 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 0 , NA , 0x4400 , NORTH ) , // C0_BPM0_TX + CHV_GPIO_PAD_CONF (L"N03: GPIO_DFX1 ", Native , M5 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 3 , NA , 0x4418 , NORTH ) , // C0_BPM1_TX + CHV_GPIO_PAD_CONF (L"N07: GPIO_DFX2 ", Native , M5 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 2 , NA , 0x4438 , NORTH ) , // C0_BPM2_TX + CHV_GPIO_PAD_CONF (L"N01: GPIO_DFX3 ", Native , M5 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , Inv_TX_Enable , NA , 1 , NA , 0x4408 , NORTH ) , // C0_BPM3_TX + CHV_GPIO_PAD_CONF (L"N05: GPIO_DFX4 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 5 , NA , 0x4428 , NORTH ) , // + CHV_GPIO_PAD_CONF (L"N04: GPIO_DFX5 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 4 , NA , 0x4420 , NORTH ) , // + CHV_GPIO_PAD_CONF (L"N08: GPIO_DFX6 ", Native , M8 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 8 , NA , 0x4440 , NORTH ) , // + CHV_GPIO_PAD_CONF (L"N02: GPIO_DFX7 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 2 , NA , 0x4410 , NORTH ) , // +//CHV_GPIO_PAD_CONF (L"N06: GPIO_DFX8 ", GPIO , M1 , GPI , NA , NA , Trig_Level , Line0 , NA , NA , NA , NonMaskable , En_RX_Data , No_Inversion , NA , 6 , NA , 0x4430 , NORTH ) , // JACK DETECT? + CHV_GPIO_PAD_CONF (L"N15: GPIO_SUS0 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 9 , NA , 0x4800 , NORTH ) , // GPIO0_SUS0 + CHV_GPIO_PAD_CONF (L"N19: GPIO_SUS1 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 13 , NA , 0x4820 , NORTH ) , // GPIO_SUS1 + CHV_GPIO_PAD_CONF (L"N24: GPIO_SUS2 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 18 , NA , 0x4848 , NORTH ) , // NGFF_PWR_EN + CHV_GPIO_PAD_CONF (L"N17: GPIO_SUS3 ", GPIO , M1 , GPI , NA , NA , Trig_Level , Line1 , NA , NA , NA , NonMaskable , En_Edge_RX_Data , No_Inversion , NA , 11 , NA , 0x4810 , NORTH ) , // NGFF_SDIO_WAKE_N + CHV_GPIO_PAD_CONF (L"N22: GPIO_SUS4 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 16 , NA , 0x4838 , NORTH ) , // NGFF_KILL_BT_N + CHV_GPIO_PAD_CONF (L"N20: GPIO_SUS5 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 14 , NA , 0x4828 , NORTH ) , // NGFF_KILL_WIFI_N + CHV_GPIO_PAD_CONF (L"N71: HV_DDI0_DDC_SCL ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 57 , NA , 0x5458 , NORTH ) , // HDMI_SMB_SOC_SCL + CHV_GPIO_PAD_CONF (L"N66: HV_DDI0_DDC_SDA ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 52 , NA , 0x5430 , NORTH ) , // HDMI_SMB_SOC_SDA + CHV_GPIO_PAD_CONF (L"N61: HV_DDI0_HPD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , Inv_TX_Enable , NA , 47 , NA , 0x5408 , NORTH ) , // SOC_HDMI_HPD + CHV_GPIO_PAD_CONF (L"N64: HV_DDI1_HPD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , Inv_TX_Enable , NA , 50 , NA , 0x5420 , NORTH ) , // SOC_DP1_HPD + CHV_GPIO_PAD_CONF (L"N67: HV_DDI2_DDC_SCL ", Native , M3 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 53 , NA , 0x5438 , NORTH ) , // UART0_TXD (Default) || DDI1_DDC_SCL + CHV_GPIO_PAD_CONF (L"N62: HV_DDI2_DDC_SDA ", Native , M3 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 48 , NA , 0x5410 , NORTH ) , // UART0_RXD (Default) || DDI1_DDC_SCA + CHV_GPIO_PAD_CONF (L"N68: HV_DDI2_HPD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , Inv_TX_Enable , NA , 54 , NA , 0x5440 , NORTH ) , // SOC_DP2_HPD + CHV_GPIO_PAD_CONF (L"N65: PANEL0_BKLTCTL ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 51 , NA , 0x5428 , NORTH ) , // BRD_ID_BIT_0 + CHV_GPIO_PAD_CONF (L"N60: PANEL0_BKLTEN ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 46 , NA , 0x5400 , NORTH ) , // BRD_ID_BIT_1 + CHV_GPIO_PAD_CONF (L"N72: PANEL0_VDDEN ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 58 , NA , 0x5460 , NORTH ) , // BRD_ID_BIT_2 + CHV_GPIO_PAD_CONF (L"N63: PANEL1_BKLTCTL ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 49 , NA , 0x5418 , NORTH ) , // + CHV_GPIO_PAD_CONF (L"N70: PANEL1_BKLTEN ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 56 , NA , 0x5450 , NORTH ) , // + CHV_GPIO_PAD_CONF (L"N69: PANEL1_VDDEN ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 55 , NA , 0x5448 , NORTH ) , // + CHV_GPIO_PAD_CONF (L"N32: PROCHOT_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 24 , NA , 0x4C10 , NORTH ) , // VR_HOT_N + CHV_GPIO_PAD_CONF (L"N16: SEC_GPIO_SUS10 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 10 , NA , 0x4808 , NORTH ) , // GPIO_SUS10 + CHV_GPIO_PAD_CONF (L"N21: SEC_GPIO_SUS11 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 15 , NA , 0x4830 , NORTH ) , // GPIO_SUS11 + CHV_GPIO_PAD_CONF (L"N23: SEC_GPIO_SUS8 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 17 , NA , 0x4840 , NORTH ) , // GPIO_SUS8 +// CHV_GPIO_PAD_CONF (L"N38: SVID0_ALERT_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 30 , NA , 0x4C40 , NORTH ) , // SVID_ALERT_N +// CHV_GPIO_PAD_CONF (L"N40: SVID0_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 32 , NA , 0x4C50 , NORTH ) , // SVD_CLK +// CHV_GPIO_PAD_CONF (L"N33: SVID0_DATA ", Native , M0 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 25 , NA , 0x4C18 , NORTH ) , // SVID_DATA + CHV_GPIO_PAD_CONF (L"N31: TCK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 23 , NA , 0x4C08 , NORTH ) , // XDP_TCK + CHV_GPIO_PAD_CONF (L"N41: TDI ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 33 , NA , 0x4C58 , NORTH ) , // XDP_TDI + CHV_GPIO_PAD_CONF (L"N39: TDO ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 31 , NA , 0x4C48 , NORTH ) , // XDP_TDO + CHV_GPIO_PAD_CONF (L"N36: TDO_2 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 28 , NA , 0x4C30 , NORTH ) , // + CHV_GPIO_PAD_CONF (L"N34: TMS ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 26 , NA , 0x4C20 , NORTH ) , // XDP_TMS + CHV_GPIO_PAD_CONF (L"N30: TRST_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 22 , NA , 0x4C00 , NORTH ) , // XDP_TRST_N + + // + // East Community + // Group Pin#: PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks + // + CHV_GPIO_PAD_CONF (L"E21: MF_ISH_GPIO_0 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 18 , NA , 0x4830 , EAST ) , // FAB ID bit 0 + CHV_GPIO_PAD_CONF (L"E18: MF_ISH_GPIO_1 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 15 , NA , 0x4818 , EAST ) , // FAB ID bit 1 + CHV_GPIO_PAD_CONF (L"E24: MF_ISH_GPIO_2 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 21 , NA , 0x4848 , EAST ) , // FAB ID bit 2 + CHV_GPIO_PAD_CONF (L"E15: MF_ISH_GPIO_3 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 12 , NA , 0x4800 , EAST ) , // FAB ID bit 3 + CHV_GPIO_PAD_CONF (L"E22: MF_ISH_GPIO_4 ", GPIO , M1 , GPI , NA , NA , NA , Line0 , NA , NA , NA , NonMaskable , NA , No_Inversion , NA , 19 , NA , 0x4838 , EAST ) , // Not Used, Test points + CHV_GPIO_PAD_CONF (L"E19: MF_ISH_GPIO_5 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 16 , NA , 0x4820 , EAST ) , // Not Used, Test points + CHV_GPIO_PAD_CONF (L"E25: MF_ISH_GPIO_6 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 22 , NA , 0x4850 , EAST ) , // Not Used, Test points + CHV_GPIO_PAD_CONF (L"E16: MF_ISH_GPIO_7 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 13 , NA , 0x4808 , EAST ) , // Not Used, Test points + CHV_GPIO_PAD_CONF (L"E23: MF_ISH_GPIO_8 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 20 , NA , 0x4840 , EAST ) , // Not Used, Test points + CHV_GPIO_PAD_CONF (L"E20: MF_ISH_GPIO_9 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 17 , NA , 0x4828 , EAST ) , // Not Used, Test points + CHV_GPIO_PAD_CONF (L"E26: MF_ISH_I2C1_SDA ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 23 , NA , 0x4858 , EAST ) , // Not Used, Test points + CHV_GPIO_PAD_CONF (L"E17: MF_ISH_I2C1_SCL ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 14 , NA , 0x4810 , EAST ) , // Not Used, Test points + CHV_GPIO_PAD_CONF (L"E04: PMU_AC_PRESENT ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 4 , NA , 0x4420 , EAST ) , // PMU_AC_PRESENT + CHV_GPIO_PAD_CONF (L"E01: PMU_BATLOW_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 1 , NA , 0x4408 , EAST ) , // PMU_BATLOW_N + CHV_GPIO_PAD_CONF (L"E05: PMU_PLTRST_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 5 , NA , 0x4428 , EAST ) , // PLTRST_3P3_N +//CHV_GPIO_PAD_CONF (L"E08: PMU_PWRBTN_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 8 , NA , 0x4440 , EAST ) , // SOC_PWRBTN_N special programming below + CHV_GPIO_PAD_CONF (L"E07: PMU_SLP_LAN_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 7 , NA , 0x4438 , EAST ) , // Not Used, Available + CHV_GPIO_PAD_CONF (L"E03: PMU_SLP_S0IX_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 3 , NA , 0x4418 , EAST ) , // SLP_S01X_3P3_N + CHV_GPIO_PAD_CONF (L"E00: PMU_SLP_S3_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 0 , NA , 0x4400 , EAST ) , // SLP_S3_3P3_N + CHV_GPIO_PAD_CONF (L"E09: PMU_SLP_S4_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 9 , NA , 0x4448 , EAST ) , // SLP_S4_3P3_N + CHV_GPIO_PAD_CONF (L"E06: PMU_SUSCLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 6 , NA , 0x4430 , EAST ) , // SUSCLK_3P3 + CHV_GPIO_PAD_CONF (L"E10: PMU_WAKE_B ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , No_Inversion , NA , 10 , NA , 0x4450 , EAST ) , // PMU_3P3_WAKE_N + CHV_GPIO_PAD_CONF (L"E11: PMU_WAKE_LAN_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 11 , NA , 0x4458 , EAST ) , // Not Used, Available + CHV_GPIO_PAD_CONF (L"E02: SUS_STAT_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 2 , NA , 0x4410 , EAST ) , // SUS_STAT_N + + // + // South East Community + // Group Pin#: PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks + // + CHV_GPIO_PAD_CONF (L"SE16: SDMMC1_CLK ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_L , NA , NA , NA , NA , No_Inversion , NA , 9 , NA , 0x4808 , SOUTHEAST ) , // EMMC1_CLK + CHV_GPIO_PAD_CONF (L"SE23: SDMMC1_CMD ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 16 , NA , 0x4840 , SOUTHEAST ) , // EMMC1_CMD + CHV_GPIO_PAD_CONF (L"SE17: SDMMC1_D0 ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 10 , NA , 0x4810 , SOUTHEAST ) , // EMMC1_D_0 + CHV_GPIO_PAD_CONF (L"SE24: SDMMC1_D1 ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 17 , NA , 0x4848 , SOUTHEAST ) , // EMMC1_D_1 + CHV_GPIO_PAD_CONF (L"SE20: SDMMC1_D2 ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 13 , NA , 0x4828 , SOUTHEAST ) , // EMMC1_D_2 + CHV_GPIO_PAD_CONF (L"SE26: SDMMC1_D3_CD_B ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 19 , NA , 0x4858 , SOUTHEAST ) , // EMMC1_D_3 + CHV_GPIO_PAD_CONF (L"SE67: MMC1_D4_SD_WE ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 41 , NA , 0x5438 , SOUTHEAST ) , // EMMC1_D4 + CHV_GPIO_PAD_CONF (L"SE65: MMC1_D5 ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 39 , NA , 0x5428 , SOUTHEAST ) , // EMMC1_D5 + CHV_GPIO_PAD_CONF (L"SE63: MMC1_D6 ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 37 , NA , 0x5418 , SOUTHEAST ) , // EMMC1_D6 + CHV_GPIO_PAD_CONF (L"SE68: MMC1_D7 ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 42 , NA , 0x5440 , SOUTHEAST ) , // EMMC1_D7 + CHV_GPIO_PAD_CONF (L"SE69: MMC1_RCLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 43 , NA , 0x5448 , SOUTHEAST ) , // EMMC1_RCLK + CHV_GPIO_PAD_CONF (L"SE77: GPIO_ALERT ", GPIO , M1 , GPI , NA , NA , Trig_Level , Line2 , NA , NA , NA , NonMaskable , En_RX_Data , Inv_RX_Data , NA , 46 , NA , 0x5810 , SOUTHEAST ) , // DCN : 2502579 - Programmed for TCH_PAD_INT_N + CHV_GPIO_PAD_CONF (L"SE79: ILB_SERIRQ ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 48 , NA , 0x5820 , SOUTHEAST ) , // ILB_SERIRQ + CHV_GPIO_PAD_CONF (L"SE51: MF_LPC_CLKOUT0 ", Native , M1 , NA , NA , NA , NA , NA , P_NONE , NA , NA , NA , NA , No_Inversion , NA , 32 , NA , 0x5030 , SOUTHEAST ) , // L_CLKOUT0 + CHV_GPIO_PAD_CONF (L"SE49: MF_LPC_CLKOUT1 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 30 , NA , 0x5020 , SOUTHEAST ) , // L_CLKOUT1 + CHV_GPIO_PAD_CONF (L"SE47: MF_LPC_AD0 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 28 , NA , 0x5010 , SOUTHEAST ) , // LPC_AD0 + CHV_GPIO_PAD_CONF (L"SE52: MF_LPC_AD1 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 33 , NA , 0x5038 , SOUTHEAST ) , // LPC_AD1 + CHV_GPIO_PAD_CONF (L"SE45: MF_LPC_AD2 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 26 , NA , 0x5000 , SOUTHEAST ) , // LPC_AD2 + CHV_GPIO_PAD_CONF (L"SE50: MF_LPC_AD3 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 31 , NA , 0x5028 , SOUTHEAST ) , // LPC_AD3 + CHV_GPIO_PAD_CONF (L"SE46: LPC_CLKRUNB ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 27 , NA , 0x5008 , SOUTHEAST ) , // L_CLKRUN_N + CHV_GPIO_PAD_CONF (L"SE48: LPC_FRAMEB ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 29 , NA , 0x5018 , SOUTHEAST ) , // L_FRAME_N + CHV_GPIO_PAD_CONF (L"SE00: MF_PLT_CLK0 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 0 , NA , 0x4400 , SOUTHEAST ) , // CAM_1_MCLK Camera1_clock + CHV_GPIO_PAD_CONF (L"SE02: MF_PLT_CLK1 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 1 , NA , 0x4410 , SOUTHEAST ) , // CAM_2_MCLK Camera2_clock + CHV_GPIO_PAD_CONF (L"SE07: MF_PLT_CLK2 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 7 , NA , 0x4438 , SOUTHEAST ) , // Not Used + CHV_GPIO_PAD_CONF (L"SE04: MF_PLT_CLK3 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 4 , NA , 0x4420 , SOUTHEAST ) , // I2S_MCLK + CHV_GPIO_PAD_CONF (L"SE03: MF_PLT_CLK4 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 3 , NA , 0x4418 , SOUTHEAST ) , // Not Used + CHV_GPIO_PAD_CONF (L"SE06: MF_PLT_CLK5 ", GPIO , M3 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 6 , NA , 0x4430 , SOUTHEAST ) , // Not Used +//CHV_GPIO_PAD_CONF (L"SE76: PMU_RSTBUTTON_B", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 45 , NA , 0x5808 , SOUTHEAST ) , // SOC_RESETBTN_N special programming below + CHV_GPIO_PAD_CONF (L"SE83: SUSPWRDNACK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 52 , NA , 0x5840 , SOUTHEAST ) , // SUSPWRDNACK_3P3 + CHV_GPIO_PAD_CONF (L"SE05: PWM0 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 5 , NA , 0x4428 , SOUTHEAST ) , // + CHV_GPIO_PAD_CONF (L"SE01: PWM1 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 1 , NA , 0x4408 , SOUTHEAST ) , // WIFI_PCIE_RST_N + CHV_GPIO_PAD_CONF (L"SE85: SDMMC3_1P8_EN ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 54 , NA , 0x5850 , SOUTHEAST ) , // SD_CARD_PWR_EN + CHV_GPIO_PAD_CONF (L"SE81: SDMMC3_CD_B ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 50 , NA , 0x5830 , SOUTHEAST ) , // SD_CARD_DET_N + CHV_GPIO_PAD_CONF (L"SE31: SDMMC3_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 21 , NA , 0x4C08 , SOUTHEAST ) , // SD_CARD_CLK + CHV_GPIO_PAD_CONF (L"SE34: SDMMC3_CMD ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 24 , NA , 0x4C20 , SOUTHEAST ) , // SD_CARD_CMD + CHV_GPIO_PAD_CONF (L"SE35: SDMMC3_D0 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 25 , NA , 0x4C28 , SOUTHEAST ) , // SD_CARD_D0 + CHV_GPIO_PAD_CONF (L"SE30: SDMMC3_D1 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 20 , NA , 0x4C00 , SOUTHEAST ) , // SD_CARD_D1 + CHV_GPIO_PAD_CONF (L"SE33: SDMMC3_D2 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 23 , NA , 0x4C18 , SOUTHEAST ) , // SD_CARD_D2 + CHV_GPIO_PAD_CONF (L"SE32: SDMMC3_D3 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 22 , NA , 0x4C10 , SOUTHEAST ) , // SD_CARD_D3 + CHV_GPIO_PAD_CONF (L"SE78: SDMMC3_PWR_EN_B", Native , M1 , NA , NA , NA , NA , NA , P_20K_L , NA , NA , NA , NA , No_Inversion , NA , 47 , NA , 0x5818 , SOUTHEAST ) , // SD_CARD_PWRDN_N + CHV_GPIO_PAD_CONF (L"SE19: SDMMC2_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 12 , NA , 0x4820 , SOUTHEAST ) , // NGFF_SDEMMC2_CLK + CHV_GPIO_PAD_CONF (L"SE22: SDMMC2_CMD ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 15 , NA , 0x4838 , SOUTHEAST ) , // NGFF_SDEMMC2_CM + CHV_GPIO_PAD_CONF (L"SE25: SDMMC2_D0 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 18 , NA , 0x4850 , SOUTHEAST ) , // NGFF_SDEMMC2_D0 + CHV_GPIO_PAD_CONF (L"SE18: SDMMC2_D1 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 11 , NA , 0x4818 , SOUTHEAST ) , // NGFF_SDEMMC2_D1 + CHV_GPIO_PAD_CONF (L"SE21: SDMMC2_D2 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 14 , NA , 0x4830 , SOUTHEAST ) , // NGFF_SDEMMC2_D2 + CHV_GPIO_PAD_CONF (L"SE15: SDMMC2_D3_CD_B ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 8 , NA , 0x4800 , SOUTHEAST ) , // NGFF_SDEMMC2_D3 + CHV_GPIO_PAD_CONF (L"SE62: SPI1_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 36 , NA , 0x5410 , SOUTHEAST ) , // SPI1_CLK + CHV_GPIO_PAD_CONF (L"SE61: SPI1_CS0_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 35 , NA , 0x5408 , SOUTHEAST ) , // SPI1_CS0_N + CHV_GPIO_PAD_CONF (L"SE66: SPI1_CS1_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 40 , NA , 0x5430 , SOUTHEAST ) , // SPI1_CS1_N + CHV_GPIO_PAD_CONF (L"SE60: SPI1_MISO ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 34 , NA , 0x5400 , SOUTHEAST ) , // SPI1_MISO + CHV_GPIO_PAD_CONF (L"SE64: SPI1_MOSI ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 38 , NA , 0x5420 , SOUTHEAST ) , // SPI1_MOSI + CHV_GPIO_PAD_CONF (L"SE80: USB_OC0_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 49 , NA , 0x5828 , SOUTHEAST ) , // USB3_OC0_N + CHV_GPIO_PAD_CONF (L"SE75: USB_OC1_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 44 , NA , 0x5800 , SOUTHEAST ) , // USB3_OC1_N + // + // South west Community + // Group Pin#: PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks + // + CHV_GPIO_PAD_CONF (L"SW02: FST_SPI_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 2 , NA , 0x4410 , SOUTHWEST ) , // FAST_SPI_CLK + CHV_GPIO_PAD_CONF (L"SW06: FST_SPI_CS0_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 6 , NA , 0x4430 , SOUTHWEST ) , // FST_SPI_CS_N + CHV_GPIO_PAD_CONF (L"SW04: FST_SPI_CS1_B ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 4 , NA , 0x4420 , SOUTHWEST ) , // V3P3DX_TCH_EN + CHV_GPIO_PAD_CONF (L"SW07: FST_SPI_CS2_B ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 7 , NA , 0x4438 , SOUTHWEST ) , // FST_SPI_CS2_N (SPI TPM) + CHV_GPIO_PAD_CONF (L"SW01: FST_SPI_D0 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 1 , NA , 0x4408 , SOUTHWEST ) , // FST_SPI_D0 + CHV_GPIO_PAD_CONF (L"SW05: FST_SPI_D1 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 5 , NA , 0x4428 , SOUTHWEST ) , // FST_SPI_D1 + CHV_GPIO_PAD_CONF (L"SW00: FST_SPI_D2 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 0 , NA , 0x4400 , SOUTHWEST ) , // FST_SPI_D2 + CHV_GPIO_PAD_CONF (L"SW03: FST_SPI_D3 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 3 , NA , 0x4418 , SOUTHWEST ) , // FST_SPI_D3 + CHV_GPIO_PAD_CONF (L"SW30: MF_HDA_CLK ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 16 , NA , 0x4C00 , SOUTHWEST ) , // MF_HDA_CLK II GP_SSP_0_I2S_TXD + CHV_GPIO_PAD_CONF (L"SW37: MF_HDA_DOCKENB ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 23 , NA , 0x4C38 , SOUTHWEST ) , // NGFF_I2S_1_RXD_R_BT || I2S_2_RXD_R_AICO + CHV_GPIO_PAD_CONF (L"SW34: MF_HDA_DOCKRSTB", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 20 , NA , 0x4C20 , SOUTHWEST ) , // NGFF_I2S_1_TXD_R_BT || I2S_2_TXD_R_AICO + CHV_GPIO_PAD_CONF (L"SW31: MF_HDA_RSTB ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 17 , NA , 0x4C08 , SOUTHWEST ) , // AUD_LINK_RST_N + CHV_GPIO_PAD_CONF (L"SW32: MF_HDA_SDI0 ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 18 , NA , 0x4C10 , SOUTHWEST ) , // AUD_LINK_SDI0_SOC + CHV_GPIO_PAD_CONF (L"SW36: MF_HDA_SDI1 ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 22 , NA , 0x4C30 , SOUTHWEST ) , // AUD_LINK_SDI1_SOC + CHV_GPIO_PAD_CONF (L"SW33: MF_HDA_SDO ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 19 , NA , 0x4C18 , SOUTHWEST ) , // AUD_LINK_SDO + CHV_GPIO_PAD_CONF (L"SW35: MF_HDA_SYNC ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 21 , NA , 0x4C28 , SOUTHWEST ) , // AUD_LINK_SYNC + CHV_GPIO_PAD_CONF (L"SW18: UART1_CTS_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 11 , NA , 0x4818 , SOUTHWEST ) , // UART_BT_CTS + CHV_GPIO_PAD_CONF (L"SW15: UART1_RTS_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 8 , NA , 0x4800 , SOUTHWEST ) , // UART_BT_RTS + CHV_GPIO_PAD_CONF (L"SW16: UART1_RXD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 9 , NA , 0x4808 , SOUTHWEST ) , // UART_BT_RXD + CHV_GPIO_PAD_CONF (L"SW20: UART1_TXD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 13 , NA , 0x4828 , SOUTHWEST ) , // UART_BT_TXD + CHV_GPIO_PAD_CONF (L"SW22: UART2_CTS_B ", Native , M1 , NA , NA , NA , NA , NA , P_NONE , NA , NA , NA , NA , No_Inversion , NA , 15 , NA , 0x4838 , SOUTHWEST ) , // UART_GPS_CTS + CHV_GPIO_PAD_CONF (L"SW19: UART2_RTS_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 12 , NA , 0x4820 , SOUTHWEST ) , // UART_GPS_RTS + CHV_GPIO_PAD_CONF (L"SW17: UART2_RXD ", Native , M1 , NA , NA , NA , NA , NA , P_NONE , NA , NA , NA , NA , No_Inversion , NA , 10 , NA , 0x4810 , SOUTHWEST ) , // UART_GPS_RXD + CHV_GPIO_PAD_CONF (L"SW21: UART2_TXD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 14 , NA , 0x4830 , SOUTHWEST ) , // UART_GPS_TXD + CHV_GPIO_PAD_CONF (L"SW65: I2C0_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 37 , NA , 0x5428 , SOUTHWEST ) , // I2C_3P3_NGFF_SDA + CHV_GPIO_PAD_CONF (L"SW61: I2C0_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 33 , NA , 0x5408 , SOUTHWEST ) , // I2C_3P3_NGFF_SCL + CHV_GPIO_PAD_CONF (L"SW63: I2C1_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 35 , NA , 0x5418 , SOUTHWEST ) , // I2C1_SDA_AUD_CONN + CHV_GPIO_PAD_CONF (L"SW60: I2C1_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 32 , NA , 0x5400 , SOUTHWEST ) , // I2C1_SCL_AUD_CONN + CHV_GPIO_PAD_CONF (L"SW66: I2C2_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 38 , NA , 0x5430 , SOUTHWEST ) , // I2C2_SDA_CAM + CHV_GPIO_PAD_CONF (L"SW62: I2C2_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 34 , NA , 0x5410 , SOUTHWEST ) , // I2C2_SCL_CAM + CHV_GPIO_PAD_CONF (L"SW67: I2C3_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 39 , NA , 0x5438 , SOUTHWEST ) , // I2C3_CAM_SDA + CHV_GPIO_PAD_CONF (L"SW64: I2C3_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 36 , NA , 0x5420 , SOUTHWEST ) , // I2C3_CAM_SCL + CHV_GPIO_PAD_CONF (L"SW50: I2C4_SCL ", Native , M3 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 29 , NA , 0x5028 , SOUTHWEST ) , // HV_DDI2_DDC_SCL + CHV_GPIO_PAD_CONF (L"SW46: I2C4_SDA ", Native , M3 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 25 , NA , 0x5008 , SOUTHWEST ) , // HV_DDI2_DDC_SDA + CHV_GPIO_PAD_CONF (L"SW48: I2C5_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 27 , NA , 0x5018 , SOUTHWEST ) , // I2C5_SDA_3P3 + CHV_GPIO_PAD_CONF (L"SW45: I2C5_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 24 , NA , 0x5000 , SOUTHWEST ) , // I2C5_SDA_3P3 + CHV_GPIO_PAD_CONF (L"SW51: I2C6_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 30 , NA , 0x5030 , SOUTHWEST ) , // + CHV_GPIO_PAD_CONF (L"SW47: I2C6_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 26 , NA , 0x5010 , SOUTHWEST ) , // + CHV_GPIO_PAD_CONF (L"SW49: I2C_NFC_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 28 , NA , 0x5020 , SOUTHWEST ) , // I2C_NFC_SDA_3P3 + CHV_GPIO_PAD_CONF (L"SW52: I2C_NFC_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 31 , NA , 0x5038 , SOUTHWEST ) , // I2C_NFC_SCL_3P3 + CHV_GPIO_PAD_CONF (L"SW77: GP_SSP_2_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 50 , NA , 0x5C10 , SOUTHWEST ) , // I2S_2_CLK + CHV_GPIO_PAD_CONF (L"SW81: GP_SSP_2_FS ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 54 , NA , 0x5C30 , SOUTHWEST ) , // I2S_2_FS + CHV_GPIO_PAD_CONF (L"SW79: GP_SSP_2_RXD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 52 , NA , 0x5C20 , SOUTHWEST ) , // I2S_2_RXD + CHV_GPIO_PAD_CONF (L"SW82: GP_SSP_2_TXD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , Inv_TX_Enable , NA , 55 , NA , 0x5C38 , SOUTHWEST ) , // I2S_2_TXD + CHV_GPIO_PAD_CONF (L"SW90: PCIE_CLKREQ0B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 48 , NA , 0x5C00 , SOUTHWEST ) , // + CHV_GPIO_PAD_CONF (L"SW91: PCIE_CLKREQ1B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 49 , NA , 0x5C08 , SOUTHWEST ) , // PCIE_CLKREQ1_N + CHV_GPIO_PAD_CONF (L"SW93: PCIE_CLKREQ2B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 51 , NA , 0x5C18 , SOUTHWEST ) , // PCIE_CLKREQ2_N + CHV_GPIO_PAD_CONF (L"SW95: PCIE_CLKREQ3B ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 53 , NA , 0x5C28 , SOUTHWEST ) , // SDMMC3_WP (Def) +//CHV_GPIO_PAD_CONF (L"SW95: PCIE_CLKREQ3B ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 53 , NA , 0x5C28 , SOUTHWEST ) , // GPI_SOC_HOMESCRN + CHV_GPIO_PAD_CONF (L"SW75: SATA_GP0 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 40 , NA , 0x5800 , SOUTHWEST ) , // reserved for SATA (Interlock switch) + CHV_GPIO_PAD_CONF (L"SW76: SATA_GP1 ", GPIO , M1 , GPI , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 41 , NA , 0x5808 , SOUTHWEST ) , // GPI to select UART0 | DDI1 mode + CHV_GPIO_PAD_CONF (L"SW78: SATA_GP2 ", Native , M1 , NA , NA , NA , NA , NA , NA , _ENABLE , NA , NA , NA , No_Inversion , NA , 43 , NA , 0x5818 , SOUTHWEST ) , // SATA_DEVSLP0 -need to check + CHV_GPIO_PAD_CONF (L"SW80: SATA_GP3 ", GPIO , M2 , GPI , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 45 , NA , 0x5828 , SOUTHWEST ) , // TOUCH_RST_N -need to check + CHV_GPIO_PAD_CONF (L"SW77: SATA_LEDN ", Native , M1 , NA , NA , NA , NA , NA , NA , _ENABLE , NA , NA , NA , No_Inversion , NA , 42 , NA , 0x5810 , SOUTHWEST ) , // SATA_LED_N + CHV_GPIO_PAD_CONF (L"SW79: MF_SMB_ALERTB ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 44 , NA , 0x5820 , SOUTHWEST ) , // SMB_ALERTB_3P3 + CHV_GPIO_PAD_CONF (L"SW81: MF_SMB_CLK ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 46 , NA , 0x5830 , SOUTHWEST ) , // SMB_3P3_CLK + CHV_GPIO_PAD_CONF (L"SW82: MF_SMB_DATA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 47 , NA , 0x5838 , SOUTHWEST ) , // SMB_3P3_DAT +}; + +GPIO_SAI_INIT mBSW_CH_GPIO_SAI_Init_East[] = +{ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_access_reg ", 0x0 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_wake_reg ", 0x4 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_interrupt_reg ", 0x8 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_community_reg ", 0xC , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_broadcast_reg ", 0x10 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_reg ", 0x14 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_pad_broadcast_reg ", 0x18 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_4x2_12_0_regs ", 0x1C , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_4x2_12_1_regs ", 0x20 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_access_reg ", 0x100, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_wake_reg ", 0x104, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_interrupt_reg ", 0x108, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_community_reg ", 0x10C, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_broadcast_reg ", 0x110, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_reg ", 0x114, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_pad_broadcast_reg ", 0x118, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_4x2_12_0_regs ", 0x11c, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_4x2_12_1_regs ", 0x120, 0x18310, ENABLE), +}; + +GPIO_SAI_INIT mBSW_CH_GPIO_SAI_Init_North[] = +{ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_access_reg ", 0x0 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_wake_reg ", 0x4 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_interrupt_reg ", 0x8 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_community_reg ", 0xC , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_broadcast_reg ", 0x10 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_reg ", 0x14 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_pad_broadcast_reg ", 0x18 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_2x4_rcomp_10_0_regs ", 0x1C , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x4_13_0_regs ", 0x20 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_3x4_12_0_regs ", 0x24 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_2x4_12_0_regs ", 0x28 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_3x4_13_0_regs ", 0x2C , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_access_reg ", 0x100, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_wake_reg ", 0x104, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_interrupt_reg ", 0x108, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_community_reg ", 0x10C, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_broadcast_reg ", 0x110, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_reg ", 0x114, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_pad_broadcast_reg ", 0x118, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_2x4_rcomp_10_0_regs ", 0x11C, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x4_13_0_regs ", 0x120, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_3x4_12_0_regs ", 0x124, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_2x4_12_0_regs ", 0x128, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_3x4_13_0_regs ", 0x12C, 0x18310, ENABLE), +}; + +GPIO_SAI_INIT mBSW_CH_GPIO_SAI_Init_SouthEast[] = +{ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_access_reg ", 0x0 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_wake_reg ", 0x4 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_interrupt_reg ", 0x8 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_community_reg ", 0xC , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_broadcast_reg ", 0x10 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_reg ", 0x14 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_pad_broadcast_reg ", 0x18 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_2_regs ", 0x1C , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_3x3_rcomp_13_0_regs ", 0x20 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_hshvfamily_2x3_rcomp_7_0_regs ", 0x24 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_hshvfamily_3x3_rcomp_9_0_regs ", 0x28 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_3x3_10_0_regs ", 0x2C , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_3x3_11_0_regs ", 0x30 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_access_reg ", 0x100, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_wake_reg ", 0x104, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_interrupt_reg ", 0x108, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_community_reg ", 0x10C, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_broadcast_reg ", 0x110, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_reg ", 0x114, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_pad_broadcast_reg ", 0x118, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_2_regs ", 0x11C, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_3x3_rcomp_13_0_regs ", 0x120, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_hshvfamily_2x3_rcomp_7_0_regs ", 0x124, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_hshvfamily_3x3_rcomp_9_0_regs ", 0x128, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_3x3_10_0_regs ", 0x12C, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_3x3_11_0_regs ", 0x130, 0x18310, ENABLE), +}; + +GPIO_SAI_INIT mBSW_CH_GPIO_SAI_Init_SouthWest[] = +{ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_access_reg ",0x0 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_wake_reg ",0x4 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_interrupt_reg ",0x8 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_community_reg ",0xC , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_broadcast_reg ",0x10 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_reg ",0x14 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_pad_broadcast_reg ",0x18 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_2x3_8_1_regs ",0x1C , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_6_regs ",0x20 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_5_regs ",0x24 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_4_regs ",0x28 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_3_regs ",0x2C , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_1_regs ",0x30 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_0_regs ",0x34 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_access_reg ",0x100, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_wake_reg ",0x104, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_interrupt_reg ",0x108, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_community_reg ",0x10C, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_broadcast_reg ",0x110, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_reg ",0x114, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_pad_broadcast_reg ",0x118, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_2x3_8_1_regs ",0x11C, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_6_regs ",0x120, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_5_regs ",0x124, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_4_regs ",0x128, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_3_regs ",0x12C, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_1_regs ",0x130, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_0_regs ",0x134, 0x18310, ENABLE), +}; + + +CHV_GPIO_PAD_INIT mBSW_CH_GpioInitData_SetupBasedConfig[] = +// Group Pin#: PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks +{ + CHV_GPIO_PAD_CONF (L"N53: GP_CAMERASB01 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5040 , NORTH ) , // FLASH_RESET_N +//CHV_GPIO_PAD_CONF (L"N53: GP_CAMERASB01 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5040 , NORTH ) , // IMAGING_DFU : USB3 CAM +//CHV_GPIO_PAD_CONF (L"N53: GP_CAMERASB01 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5040 , NORTH ) , // IMAGING_DFU : MIPI CAM +}; + +CHV_GPIO_PAD_INIT mBSW_CH_GpioInitData_N[] = +// PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks +{ + CHV_GPIO_PAD_CONF (L"N25: GPIO_SUS6 ", GPIO , M1 , GPI , NA , NA , Trig_Edge_Low , Line9 , NA , NA , NA , NonMaskable , En_Edge_RX_Data , No_Inversion , NA , 19 , SCI , 0x4850 , NORTH ) , // XDP_HLT_BOOT + CHV_GPIO_PAD_CONF (L"N18: GPIO_SUS7 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 12 , SMI , 0x4818 , NORTH ) , // + CHV_GPIO_PAD_CONF (L"N23: SEC_GPIO_SUS8 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 17 , NA , 0x4840 , NORTH ) , // + CHV_GPIO_PAD_CONF (L"N27: SEC_GPIO_SUS9 ", GPIO , M1 , GPI , LOW , NA , Trig_Level , Line15 , NA , NA , NA , NonMaskable , En_RX_Data , Inv_RX_Data , NA , 21 , SCI , 0x4860 , NORTH ) , // GPIO_THERM_ALERT_N +}; + +VOID +BraswellCherryHillAdditionalGpioInit ( + VOID + ) +{ + CHV_GPIO_PAD_INIT GpioInitTable[3]; + + DEBUG ((EFI_D_ERROR, "Programming BSW CR Board Gpio Tables which are not done properly by FSP...\n")); + + // + // Copy the default settings for first three external gpios + // + CopyMem (GpioInitTable, mBSW_CH_GpioInitData_N, (sizeof(CHV_GPIO_PAD_INIT) * 3 )); + + // + // Update the gpio setting with the values from patchable pcds + // + // Update GPIO_SUS6 + GpioInitTable[0].padConfg0.padCnf0 = (UINT32)(PcdGet64 (PcdGPIOSUS6Configuration) & 0xFCFF8782); + GpioInitTable[0].padConfg1.padCnf1 &= 0xFFFFFF00; + GpioInitTable[0].padConfg1.padCnf1 |= (UINT32) (RShiftU64(PcdGet64 (PcdGPIOSUS6Configuration), 32) & 0xFF); + GpioInitTable[0].PAD_MISC.r.GPE_ENABLE = (UINT32) (RShiftU64(PcdGet64 (PcdGPIOSUS6Configuration),40) & 0x03); + GpioInitTable[0].PAD_MISC.r.wake_able = (PcdGet64 (PcdGPIOSUS6Configuration) & BIT42) ? 1:0; + GpioInitTable[0].PAD_MISC.r.intr_mask = (PcdGet64 (PcdGPIOSUS6Configuration) & BIT43) ? 1:0; + GpioInitTable[0].PAD_MISC.r.Wake_Mask_Position = (UINT32) (RShiftU64(PcdGet64 (PcdGPIOSUS6Configuration), 44) & 0xFF); + + // Update GPIO_SUS7 + GpioInitTable[1].padConfg0.padCnf0 = (UINT32)(PcdGet64 (PcdGPIOSUS7Configuration) & 0xFCFF8782); + GpioInitTable[1].padConfg1.padCnf1 &= 0xFFFFFF00; + GpioInitTable[1].padConfg1.padCnf1 |= (UINT32) (RShiftU64(PcdGet64 (PcdGPIOSUS7Configuration), 32) & 0xFF); + GpioInitTable[1].PAD_MISC.r.GPE_ENABLE = (UINT32) (RShiftU64(PcdGet64 (PcdGPIOSUS7Configuration), 40) & 0x03); + GpioInitTable[1].PAD_MISC.r.wake_able = (PcdGet64 (PcdGPIOSUS7Configuration) & BIT42) ? 1:0; + GpioInitTable[1].PAD_MISC.r.intr_mask = (PcdGet64 (PcdGPIOSUS7Configuration) & BIT43) ? 1:0; + GpioInitTable[1].PAD_MISC.r.Wake_Mask_Position = (UINT32) (RShiftU64(PcdGet64 (PcdGPIOSUS7Configuration), 44) & 0xFF); + + // Update GPIO_SUS8 + GpioInitTable[2].padConfg0.padCnf0 = (UINT32)(PcdGet64 (PcdGPIOSUS8Configuration) & 0xFCFF8782); + GpioInitTable[2].padConfg1.padCnf1 &= 0xFFFFFF00; + GpioInitTable[2].padConfg1.padCnf1 |= (UINT32) (RShiftU64(PcdGet64 (PcdGPIOSUS8Configuration), 32) & 0xFF); + GpioInitTable[2].PAD_MISC.r.GPE_ENABLE = (UINT32) (RShiftU64(PcdGet64 (PcdGPIOSUS8Configuration), 40) & 0x03); + GpioInitTable[2].PAD_MISC.r.wake_able = (PcdGet64 (PcdGPIOSUS8Configuration) & BIT42) ? 1:0; + GpioInitTable[2].PAD_MISC.r.intr_mask = (PcdGet64 (PcdGPIOSUS8Configuration) & BIT43) ? 1:0; + GpioInitTable[2].PAD_MISC.r.Wake_Mask_Position = (UINT32) (RShiftU64(PcdGet64 (PcdGPIOSUS8Configuration), 44) & 0xFF); + + // PAD programming to initialize GPIOs with SCI/SMI support, which depends on FSP PchInit to program basic chipset resources. + InternalGpioPADConfig(3, (sizeof(mBSW_CH_GpioInitData_N)/sizeof(mBSW_CH_GpioInitData_N[0]) - 3), mBSW_CH_GpioInitData_N); + + // Initialize the three gpios at the gpio header + InternalGpioPADConfig(0, sizeof(GpioInitTable)/sizeof(GpioInitTable[0]), GpioInitTable); + + // GPIO lock if really want + SAI_SettingOfGpioFamilies(mBSW_CH_GPIO_SAI_Init_East, sizeof(mBSW_CH_GPIO_SAI_Init_East)/sizeof(mBSW_CH_GPIO_SAI_Init_East[0])); + SAI_SettingOfGpioFamilies(mBSW_CH_GPIO_SAI_Init_North, sizeof(mBSW_CH_GPIO_SAI_Init_North)/sizeof(mBSW_CH_GPIO_SAI_Init_North[0])); + SAI_SettingOfGpioFamilies(mBSW_CH_GPIO_SAI_Init_SouthEast, sizeof(mBSW_CH_GPIO_SAI_Init_SouthEast)/sizeof(mBSW_CH_GPIO_SAI_Init_SouthEast[0])); + SAI_SettingOfGpioFamilies(mBSW_CH_GPIO_SAI_Init_SouthWest, sizeof(mBSW_CH_GPIO_SAI_Init_SouthWest)/sizeof(mBSW_CH_GPIO_SAI_Init_SouthWest[0])); +} + +VOID +CherryHillBoardGpioConfigure ( + VOID + ) +{ + + InternalGpioPADConfig(0, sizeof(mBswCherryHillGpioInitData)/sizeof(mBswCherryHillGpioInitData[0]), mBswCherryHillGpioInitData); + +} + diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardGpios.h b/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardGpios.h index 71d26e1697..6aeee46347 100644 --- a/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardGpios.h +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardGpios.h @@ -54,150 +54,18 @@ #define GPIO_SOC_RUNTIME_SCI_N 0x4850 -/// ***************************************************************************************************************************************** -/// ***************************************************************************************************************************************** -/// ***************************************************************************************************************************************** -/// *************************************************** CHERRYVIEW GPIO CONFIGURATION ************************************************* -/// ***************************************************************************************************************************************** -/// ***************************************************************************************************************************************** -/// ***************************************************************************************************************************************** - #define ENABLE 1 #define DISABLE 0 -// Braswell Cherry Hill platform - -/// Community Configuration -/// Family Configuration -/* -* GPIO Families configuration in CherryView -* -*/ - -GPIO_SAI_INIT mBSW_CH_GPIO_SAI_Init_East[] = -{ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_access_reg ", 0x0 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_wake_reg ", 0x4 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_interrupt_reg ", 0x8 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_community_reg ", 0xC , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_broadcast_reg ", 0x10 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_reg ", 0x14 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_pad_broadcast_reg ", 0x18 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_4x2_12_0_regs ", 0x1C , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_4x2_12_1_regs ", 0x20 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_access_reg ", 0x100, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_wake_reg ", 0x104, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_interrupt_reg ", 0x108, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_community_reg ", 0x10C, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_broadcast_reg ", 0x110, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_reg ", 0x114, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_pad_broadcast_reg ", 0x118, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_4x2_12_0_regs ", 0x11c, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_4x2_12_1_regs ", 0x120, 0x18310, ENABLE), -}; - -GPIO_SAI_INIT mBSW_CH_GPIO_SAI_Init_North[] = -{ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_access_reg ", 0x0 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_wake_reg ", 0x4 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_interrupt_reg ", 0x8 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_community_reg ", 0xC , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_broadcast_reg ", 0x10 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_reg ", 0x14 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_pad_broadcast_reg ", 0x18 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_2x4_rcomp_10_0_regs ", 0x1C , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x4_13_0_regs ", 0x20 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_3x4_12_0_regs ", 0x24 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_2x4_12_0_regs ", 0x28 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_3x4_13_0_regs ", 0x2C , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_access_reg ", 0x100, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_wake_reg ", 0x104, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_interrupt_reg ", 0x108, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_community_reg ", 0x10C, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_broadcast_reg ", 0x110, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_reg ", 0x114, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_pad_broadcast_reg ", 0x118, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_2x4_rcomp_10_0_regs ", 0x11C, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x4_13_0_regs ", 0x120, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_3x4_12_0_regs ", 0x124, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_2x4_12_0_regs ", 0x128, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_3x4_13_0_regs ", 0x12C, 0x18310, ENABLE), -}; - -GPIO_SAI_INIT mBSW_CH_GPIO_SAI_Init_SouthEast[] = -{ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_access_reg ", 0x0 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_wake_reg ", 0x4 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_interrupt_reg ", 0x8 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_community_reg ", 0xC , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_broadcast_reg ", 0x10 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_reg ", 0x14 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_pad_broadcast_reg ", 0x18 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_2_regs ", 0x1C , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_3x3_rcomp_13_0_regs ", 0x20 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_hshvfamily_2x3_rcomp_7_0_regs ", 0x24 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_hshvfamily_3x3_rcomp_9_0_regs ", 0x28 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_3x3_10_0_regs ", 0x2C , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_3x3_11_0_regs ", 0x30 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_access_reg ", 0x100, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_wake_reg ", 0x104, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_interrupt_reg ", 0x108, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_community_reg ", 0x10C, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_broadcast_reg ", 0x110, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_reg ", 0x114, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_pad_broadcast_reg ", 0x118, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_2_regs ", 0x11C, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_3x3_rcomp_13_0_regs ", 0x120, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_hshvfamily_2x3_rcomp_7_0_regs ", 0x124, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_hshvfamily_3x3_rcomp_9_0_regs ", 0x128, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_3x3_10_0_regs ", 0x12C, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_3x3_11_0_regs ", 0x130, 0x18310, ENABLE), -}; - -GPIO_SAI_INIT mBSW_CH_GPIO_SAI_Init_SouthWest[] = -{ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_access_reg ",0x0 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_wake_reg ",0x4 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_interrupt_reg ",0x8 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_community_reg ",0xC , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_broadcast_reg ",0x10 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_reg ",0x14 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_pad_broadcast_reg ",0x18 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_2x3_8_1_regs ",0x1C , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_6_regs ",0x20 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_5_regs ",0x24 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_4_regs ",0x28 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_3_regs ",0x2C , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_1_regs ",0x30 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_0_regs ",0x34 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_access_reg ",0x100, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_wake_reg ",0x104, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_interrupt_reg ",0x108, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_community_reg ",0x10C, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_broadcast_reg ",0x110, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_reg ",0x114, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_pad_broadcast_reg ",0x118, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_2x3_8_1_regs ",0x11C, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_6_regs ",0x120, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_5_regs ",0x124, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_4_regs ",0x128, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_3_regs ",0x12C, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_1_regs ",0x130, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_0_regs ",0x134, 0x18310, ENABLE), -}; - - -CHV_GPIO_PAD_INIT mBSW_CH_GpioInitData_SetupBasedConfig[] = -// Group Pin#: PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks -{ - CHV_GPIO_PAD_CONF (L"N53: GP_CAMERASB01 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5040 , NORTH ) , // FLASH_RESET_N -//CHV_GPIO_PAD_CONF (L"N53: GP_CAMERASB01 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5040 , NORTH ) , // IMAGING_DFU : USB3 CAM -//CHV_GPIO_PAD_CONF (L"N53: GP_CAMERASB01 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5040 , NORTH ) , // IMAGING_DFU : MIPI CAM -}; - -CHV_GPIO_PAD_INIT mBSW_CH_GpioInitData_N[] = -// PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks -{ - CHV_GPIO_PAD_CONF (L"N25: GPIO_SUS6 ", GPIO , M1 , GPI , NA , NA , Trig_Edge_Low , Line9 , NA , NA , NA , NonMaskable , En_Edge_RX_Data , No_Inversion , NA , 19 , SCI , 0x4850 , NORTH ) , // XDP_HLT_BOOT - CHV_GPIO_PAD_CONF (L"N18: GPIO_SUS7 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 12 , SMI , 0x4818 , NORTH ) , // - CHV_GPIO_PAD_CONF (L"N23: SEC_GPIO_SUS8 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 17 , NA , 0x4840 , NORTH ) , // - CHV_GPIO_PAD_CONF (L"N27: SEC_GPIO_SUS9 ", GPIO , M1 , GPI , LOW , NA , Trig_Level , Line15 , NA , NA , NA , NonMaskable , En_RX_Data , Inv_RX_Data , NA , 21 , SCI , 0x4860 , NORTH ) , // GPIO_THERM_ALERT_N -}; +VOID +SAI_SettingOfGpioFamilies ( + GPIO_SAI_INIT* SAI_Conf_Data, + UINT32 familySize + ); +VOID +CherryHillBoardGpioConfigure ( + VOID + ); #endif + diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInit.c b/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInit.c index 9d69107119..922f47238d 100644 --- a/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInit.c +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInit.c @@ -1,7 +1,7 @@ /** @file Board Init driver. - Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License @@ -24,844 +24,8 @@ #include #include #include -#include -// -// TBD: Need update to CH version -// -extern UINT8 mBSW_CR_SpdDataMemorySolderDown[]; - -// -// TBD: Need update to CH version -// -CHV_GPIO_PAD_INIT mBswCherryHillGpioInitData[] = -{ - // - // North Community - // Group Pin#: PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks - CHV_GPIO_PAD_CONF (L"N00: GPIO_DFX0 ", Native , M5 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 0 , NA , 0x4400 , NORTH ) , // C0_BPM0_TX - CHV_GPIO_PAD_CONF (L"N01: GPIO_DFX3 ", Native , M5 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , Inv_TX_Enable , NA , 1 , NA , 0x4408 , NORTH ) , // C0_BPM3_TX - CHV_GPIO_PAD_CONF (L"N02: GPIO_DFX7 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 2 , NA , 0x4410 , NORTH ) , // - CHV_GPIO_PAD_CONF (L"N03: GPIO_DFX1 ", Native , M5 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 3 , NA , 0x4418 , NORTH ) , // C0_BPM1_TX - CHV_GPIO_PAD_CONF (L"N04: GPIO_DFX5 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 4 , NA , 0x4420 , NORTH ) , // - CHV_GPIO_PAD_CONF (L"N05: GPIO_DFX4 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 5 , NA , 0x4428 , NORTH ) , // - CHV_GPIO_PAD_CONF (L"N06: GPIO_DFX8 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 6 , NA , 0x4430 , NORTH ) , // JACK DETECT? - CHV_GPIO_PAD_CONF (L"N07: GPIO_DFX2 ", Native , M5 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 7 , NA , 0x4438 , NORTH ) , // C0_BPM2_TX - CHV_GPIO_PAD_CONF (L"N08: GPIO_DFX6 ", Native , M8 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 8 , NA , 0x4440 , NORTH ) , // - CHV_GPIO_PAD_CONF (L"N15: GPIO_SUS0 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 9 , NA , 0x4800 , NORTH ) , // GPIO0_SUS0 - CHV_GPIO_PAD_CONF (L"N16: SEC_GPIO_SUS10 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 10 , NA , 0x4808 , NORTH ) , // GPIO_SUS10 - CHV_GPIO_PAD_CONF (L"N17: GPIO_SUS3 ", GPIO , M1 , GPI , NA , NA , Trig_Level , Line1 , NA , NA , NA , NonMaskable , En_Edge_RX_Data , No_Inversion , NA , 11 , NA , 0x4810 , NORTH ) , // NGFF_SDIO_WAKE_N - CHV_GPIO_PAD_CONF (L"N18: GPIO_SUS7 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 12 , SMI , 0x4818 , NORTH ) , // GPIO_SUS7 - CHV_GPIO_PAD_CONF (L"N19: GPIO_SUS1 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 13 , NA , 0x4820 , NORTH ) , // GPIO_SUS1 - CHV_GPIO_PAD_CONF (L"N20: GPIO_SUS5 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 14 , NA , 0x4828 , NORTH ) , // NGFF_KILL_WIFI_N - CHV_GPIO_PAD_CONF (L"N21: SEC_GPIO_SUS11 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 15 , NA , 0x4830 , NORTH ) , // GPIO_SUS11 - CHV_GPIO_PAD_CONF (L"N22: GPIO_SUS4 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 16 , NA , 0x4838 , NORTH ) , // NGFF_KILL_BT_N - CHV_GPIO_PAD_CONF (L"N23: SEC_GPIO_SUS8 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 17 , NA , 0x4840 , NORTH ) , // GPIO_SUS8 - CHV_GPIO_PAD_CONF (L"N24: GPIO_SUS2 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 18 , NA , 0x4848 , NORTH ) , // NGFF_PWR_EN - CHV_GPIO_PAD_CONF (L"N25: GPIO_SUS6 ", GPIO , M1 , GPI , NA , NA , Trig_Edge_Low , Line9 , NA , NA , NA , NonMaskable , En_Edge_RX_Data , No_Inversion , NA , 19 , SCI , 0x4850 , NORTH ) , // XDP_HLT_BOOT - CHV_GPIO_PAD_CONF (L"N26: CX_PREQ_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 20 , NA , 0x4858 , NORTH ) , // PREQ_B - CHV_GPIO_PAD_CONF (L"N27: GPIO_SUS9 ", GPIO , M1 , GPI , LOW , NA , Trig_Level , Line15 , NA , NA , NA , NonMaskable , En_RX_Data , Inv_RX_Data , NA , 21 , SCI , 0x4860 , NORTH ) , // GPIO_SUS9 - CHV_GPIO_PAD_CONF (L"N30: TRST_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 22 , NA , 0x4C00 , NORTH ) , // TRST_B - CHV_GPIO_PAD_CONF (L"N31: TCK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 23 , NA , 0x4C08 , NORTH ) , // XDP_TCK - CHV_GPIO_PAD_CONF (L"N32: PROCHOT_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 24 , NA , 0x4C10 , NORTH ) , // VR_HOT_N - CHV_GPIO_PAD_CONF (L"N33: SVID0_DATA ", Native , M0 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 25 , NA , 0x4C18 , NORTH ) , // SVID_DATA - CHV_GPIO_PAD_CONF (L"N34: TMS ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 26 , NA , 0x4C20 , NORTH ) , // XDP_TMS - CHV_GPIO_PAD_CONF (L"N35: CX_PRDY_B2 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 27 , NA , 0x4C28 , NORTH ) , // PRDY_B2 - CHV_GPIO_PAD_CONF (L"N36: TDO_2 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 28 , NA , 0x4C30 , NORTH ) , // - CHV_GPIO_PAD_CONF (L"N37: CX_PRDY_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 29 , NA , 0x4C38 , NORTH ) , // CX_PRDY_B - CHV_GPIO_PAD_CONF (L"N38: SVID0_ALERT_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , Inv_RX_Data , NA , 30 , NA , 0x4C40 , NORTH ) , // SVID0_ALERT_B - CHV_GPIO_PAD_CONF (L"N39: TDO ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 31 , NA , 0x4C48 , NORTH ) , // XDP_TDO - CHV_GPIO_PAD_CONF (L"N40: SVID0_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 32 , NA , 0x4C50 , NORTH ) , // SVD_CLK - CHV_GPIO_PAD_CONF (L"N41: TDI ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 33 , NA , 0x4C58 , NORTH ) , // XDP_TDI - CHV_GPIO_PAD_CONF (L"N45: GP_CAMERASB05 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 34 , NA , 0x5000 , NORTH ) , // FLASH_TORCH - CHV_GPIO_PAD_CONF (L"N46: GP_CAMERASB02 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 35 , NA , 0x5008 , NORTH ) , // GPIO_FLHD_N - CHV_GPIO_PAD_CONF (L"N47: GP_CAMERASB08 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 36 , NA , 0x5010 , NORTH ) , // XDP_GP_CAMERASB08 - CHV_GPIO_PAD_CONF (L"N48: GP_CAMERASB00 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 37 , NA , 0x5018 , NORTH ) , // CAM_ACT_LED - CHV_GPIO_PAD_CONF (L"N49: GP_CAMERASB06 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 38 , NA , 0x5020 , NORTH ) , // CAM1_PWRDWN - CHV_GPIO_PAD_CONF (L"N50: GP_CAMERASB10 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 39 , NA , 0x5028 , NORTH ) , // CAM_2_RST_N - CHV_GPIO_PAD_CONF (L"N51: GP_CAMERASB03 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 40 , NA , 0x5030 , NORTH ) , // XDP_GP_CAMERASB03 - CHV_GPIO_PAD_CONF (L"N52: GP_CAMERASB09 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 41 , NA , 0x5038 , NORTH ) , // CAM_1_RST_N - CHV_GPIO_PAD_CONF (L"N53: GP_CAMERASB01 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 42 , NA , 0x5040 , NORTH ) , // FLASH_RESET_N - CHV_GPIO_PAD_CONF (L"N54: GP_CAMERASB07 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 43 , NA , 0x5048 , NORTH ) , // CAM2_PWRDWN - CHV_GPIO_PAD_CONF (L"N55: GP_CAMERASB11 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 44 , NA , 0x5050 , NORTH ) , // CAM_3_RST_N - CHV_GPIO_PAD_CONF (L"N56: GP_CAMERASB04 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 45 , NA , 0x5058 , NORTH ) , // FLASH_TRIG - CHV_GPIO_PAD_CONF (L"N60: PANEL0_BKLTEN ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 46 , NA , 0x5400 , NORTH ) , // BRD_ID_BIT_1 - CHV_GPIO_PAD_CONF (L"N61: HV_DDI0_HPD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , Inv_TX_Enable , NA , 47 , NA , 0x5408 , NORTH ) , // SOC_HDMI_HPD - CHV_GPIO_PAD_CONF (L"N62: HV_DDI2_DDC_SDA ", Native , M3 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 48 , NA , 0x5410 , NORTH ) , // UART0_RXD (Default) || DDI1_DDC_SCA - CHV_GPIO_PAD_CONF (L"N63: PANEL1_BKLTCTL ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 49 , NA , 0x5418 , NORTH ) , // - CHV_GPIO_PAD_CONF (L"N64: HV_DDI1_HPD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , Inv_TX_Enable , NA , 50 , NA , 0x5420 , NORTH ) , // SOC_DP1_HPD - CHV_GPIO_PAD_CONF (L"N65: PANEL0_BKLTCTL ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 51 , NA , 0x5428 , NORTH ) , // BRD_ID_BIT_0 - CHV_GPIO_PAD_CONF (L"N66: HV_DDI0_DDC_SDA ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 52 , NA , 0x5430 , NORTH ) , // HDMI_SMB_SOC_SDA - CHV_GPIO_PAD_CONF (L"N67: HV_DDI2_DDC_SCL ", Native , M3 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 53 , NA , 0x5438 , NORTH ) , // UART0_TXD (Default) || DDI1_DDC_SCL - CHV_GPIO_PAD_CONF (L"N68: HV_DDI2_HPD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , Inv_TX_Enable , NA , 54 , NA , 0x5440 , NORTH ) , // SOC_DP2_HPD - CHV_GPIO_PAD_CONF (L"N69: PANEL1_VDDEN ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 55 , NA , 0x5448 , NORTH ) , // - CHV_GPIO_PAD_CONF (L"N70: PANEL1_BKLTEN ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 56 , NA , 0x5450 , NORTH ) , // - CHV_GPIO_PAD_CONF (L"N71: HV_DDI0_DDC_SCL ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 57 , NA , 0x5458 , NORTH ) , // HDMI_SMB_SOC_SCL - CHV_GPIO_PAD_CONF (L"N72: PANEL0_VDDEN ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 58 , NA , 0x5460 , NORTH ) , // BRD_ID_BIT_2 - - // - // East Community - // Group Pin#: PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks - // - CHV_GPIO_PAD_CONF (L"E00: PMU_SLP_S3_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 0 , NA , 0x4400 , EAST ) , // SLP_S3_3P3_N - CHV_GPIO_PAD_CONF (L"E01: PMU_BATLOW_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 1 , NA , 0x4408 , EAST ) , // PMU_BATLOW_N - CHV_GPIO_PAD_CONF (L"E02: SUS_STAT_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 2 , NA , 0x4410 , EAST ) , // SUS_STAT_N - CHV_GPIO_PAD_CONF (L"E03: PMU_SLP_S0IX_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 3 , NA , 0x4418 , EAST ) , // SLP_S01X_3P3_N - CHV_GPIO_PAD_CONF (L"E04: PMU_AC_PRESENT ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 4 , NA , 0x4420 , EAST ) , // PMU_AC_PRESENT - CHV_GPIO_PAD_CONF (L"E05: PMU_PLTRST_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 5 , NA , 0x4428 , EAST ) , // PLTRST_3P3_N - CHV_GPIO_PAD_CONF (L"E06: PMU_SUSCLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 6 , NA , 0x4430 , EAST ) , // SUSCLK_3P3 - CHV_GPIO_PAD_CONF (L"E07: PMU_SLP_LAN_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 7 , NA , 0x4438 , EAST ) , // Not Used, Available - CHV_GPIO_PAD_CONF (L"E08: PMU_PWRBTN_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 8 , NA , 0x4440 , EAST ) , // SOC_PWRBTN_N special programming below - CHV_GPIO_PAD_CONF (L"E09: PMU_SLP_S4_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 9 , NA , 0x4448 , EAST ) , // SLP_S4_3P3_N - CHV_GPIO_PAD_CONF (L"E10: PMU_WAKE_B ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , No_Inversion , NA , 10 , NA , 0x4450 , EAST ) , // PMU_3P3_WAKE_N - CHV_GPIO_PAD_CONF (L"E11: PMU_WAKE_LAN_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 11 , NA , 0x4458 , EAST ) , // Not Used, Available - CHV_GPIO_PAD_CONF (L"E15: MF_ISH_GPIO_3 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 12 , NA , 0x4800 , EAST ) , // FAB ID bit 3 - CHV_GPIO_PAD_CONF (L"E16: MF_ISH_GPIO_7 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 13 , NA , 0x4808 , EAST ) , // Not Used, Test points - CHV_GPIO_PAD_CONF (L"E17: MF_ISH_I2C1_SCL ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 14 , NA , 0x4810 , EAST ) , // Not Used, Test points - CHV_GPIO_PAD_CONF (L"E18: MF_ISH_GPIO_1 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 15 , NA , 0x4818 , EAST ) , // FAB ID bit 1 - CHV_GPIO_PAD_CONF (L"E19: MF_ISH_GPIO_5 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 16 , NA , 0x4820 , EAST ) , // Not Used, Test points - CHV_GPIO_PAD_CONF (L"E20: MF_ISH_GPIO_9 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 17 , NA , 0x4828 , EAST ) , // Not Used, Test points - CHV_GPIO_PAD_CONF (L"E21: MF_ISH_GPIO_0 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 18 , NA , 0x4830 , EAST ) , // FAB ID bit 0 - CHV_GPIO_PAD_CONF (L"E22: MF_ISH_GPIO_4 ", GPIO , M1 , GPI , NA , NA , NA , Line0 , NA , NA , NA , NonMaskable , NA , No_Inversion , NA , 19 , NA , 0x4838 , EAST ) , // Not Used, Test points - CHV_GPIO_PAD_CONF (L"E23: MF_ISH_GPIO_8 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 20 , NA , 0x4840 , EAST ) , // Not Used, Test points - CHV_GPIO_PAD_CONF (L"E24: MF_ISH_GPIO_2 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 21 , NA , 0x4848 , EAST ) , // FAB ID bit 2 - CHV_GPIO_PAD_CONF (L"E25: MF_ISH_GPIO_6 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 22 , NA , 0x4850 , EAST ) , // Not Used, Test points - CHV_GPIO_PAD_CONF (L"E26: MF_ISH_I2C1_SDA ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 23 , NA , 0x4858 , EAST ) , // Not Used, Test points - // - // South East Community - // Group Pin#: PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks - // - CHV_GPIO_PAD_CONF (L"SE00: MF_PLT_CLK0 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 0 , NA , 0x4400 , SOUTHEAST ) , // CAM_1_MCLK Camera1_clock - CHV_GPIO_PAD_CONF (L"SE01: PWM1 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 1 , NA , 0x4408 , SOUTHEAST ) , // WIFI_PCIE_RST_N - CHV_GPIO_PAD_CONF (L"SE02: MF_PLT_CLK1 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 1 , NA , 0x4410 , SOUTHEAST ) , // CAM_2_MCLK Camera2_clock - CHV_GPIO_PAD_CONF (L"SE03: MF_PLT_CLK4 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 3 , NA , 0x4418 , SOUTHEAST ) , // Not Used - CHV_GPIO_PAD_CONF (L"SE04: MF_PLT_CLK3 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 4 , NA , 0x4420 , SOUTHEAST ) , // I2S_MCLK - CHV_GPIO_PAD_CONF (L"SE05: PWM0 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 5 , NA , 0x4428 , SOUTHEAST ) , // - CHV_GPIO_PAD_CONF (L"SE06: MF_PLT_CLK5 ", GPIO , M3 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 6 , NA , 0x4430 , SOUTHEAST ) , // Not Used - CHV_GPIO_PAD_CONF (L"SE07: MF_PLT_CLK2 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 7 , NA , 0x4438 , SOUTHEAST ) , // Not Used - CHV_GPIO_PAD_CONF (L"SE15: SDMMC2_D3_CD_B ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 8 , NA , 0x4800 , SOUTHEAST ) , // NGFF_SDEMMC2_D3 - CHV_GPIO_PAD_CONF (L"SE16: SDMMC1_CLK ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_L , NA , NA , NA , NA , No_Inversion , NA , 9 , NA , 0x4808 , SOUTHEAST ) , // EMMC1_CLK - CHV_GPIO_PAD_CONF (L"SE17: SDMMC1_D0 ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 10 , NA , 0x4810 , SOUTHEAST ) , // EMMC1_D_0 - CHV_GPIO_PAD_CONF (L"SE18: SDMMC2_D1 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 11 , NA , 0x4818 , SOUTHEAST ) , // NGFF_SDEMMC2_D1 - CHV_GPIO_PAD_CONF (L"SE19: SDMMC2_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 12 , NA , 0x4820 , SOUTHEAST ) , // NGFF_SDEMMC2_CLK - CHV_GPIO_PAD_CONF (L"SE20: SDMMC1_D2 ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 13 , NA , 0x4828 , SOUTHEAST ) , // EMMC1_D_2 - CHV_GPIO_PAD_CONF (L"SE21: SDMMC2_D2 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 14 , NA , 0x4830 , SOUTHEAST ) , // NGFF_SDEMMC2_D2 - CHV_GPIO_PAD_CONF (L"SE22: SDMMC2_CMD ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 15 , NA , 0x4838 , SOUTHEAST ) , // NGFF_SDEMMC2_CM - CHV_GPIO_PAD_CONF (L"SE23: SDMMC1_CMD ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 16 , NA , 0x4840 , SOUTHEAST ) , // EMMC1_CMD - CHV_GPIO_PAD_CONF (L"SE24: SDMMC1_D1 ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 17 , NA , 0x4848 , SOUTHEAST ) , // EMMC1_D_1 - CHV_GPIO_PAD_CONF (L"SE25: SDMMC2_D0 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 18 , NA , 0x4850 , SOUTHEAST ) , // NGFF_SDEMMC2_D0 - CHV_GPIO_PAD_CONF (L"SE26: SDMMC1_D3_CD_B ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 19 , NA , 0x4858 , SOUTHEAST ) , // EMMC1_D_3 - CHV_GPIO_PAD_CONF (L"SE30: SDMMC3_D1 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 20 , NA , 0x4C00 , SOUTHEAST ) , // SD_CARD_D1 - CHV_GPIO_PAD_CONF (L"SE31: SDMMC3_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 21 , NA , 0x4C08 , SOUTHEAST ) , // SD_CARD_CLK - CHV_GPIO_PAD_CONF (L"SE32: SDMMC3_D3 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 22 , NA , 0x4C10 , SOUTHEAST ) , // SD_CARD_D3 - CHV_GPIO_PAD_CONF (L"SE33: SDMMC3_D2 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 23 , NA , 0x4C18 , SOUTHEAST ) , // SD_CARD_D2 - CHV_GPIO_PAD_CONF (L"SE34: SDMMC3_CMD ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 24 , NA , 0x4C20 , SOUTHEAST ) , // SD_CARD_CMD - CHV_GPIO_PAD_CONF (L"SE35: SDMMC3_D0 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 25 , NA , 0x4C28 , SOUTHEAST ) , // SD_CARD_D0 - CHV_GPIO_PAD_CONF (L"SE45: MF_LPC_AD2 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 26 , NA , 0x5000 , SOUTHEAST ) , // LPC_AD2 - CHV_GPIO_PAD_CONF (L"SE46: LPC_CLKRUNB ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 27 , NA , 0x5008 , SOUTHEAST ) , // L_CLKRUN_N - CHV_GPIO_PAD_CONF (L"SE47: MF_LPC_AD0 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 28 , NA , 0x5010 , SOUTHEAST ) , // LPC_AD0 - CHV_GPIO_PAD_CONF (L"SE48: LPC_FRAMEB ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 29 , NA , 0x5018 , SOUTHEAST ) , // L_FRAME_N - CHV_GPIO_PAD_CONF (L"SE49: MF_LPC_CLKOUT1 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 30 , NA , 0x5020 , SOUTHEAST ) , // L_CLKOUT1 - CHV_GPIO_PAD_CONF (L"SE50: MF_LPC_AD3 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 31 , NA , 0x5028 , SOUTHEAST ) , // LPC_AD3 - CHV_GPIO_PAD_CONF (L"SE51: MF_LPC_CLKOUT0 ", Native , M1 , NA , NA , NA , NA , NA , P_NONE , NA , NA , NA , NA , No_Inversion , NA , 32 , NA , 0x5030 , SOUTHEAST ) , // L_CLKOUT0 - CHV_GPIO_PAD_CONF (L"SE52: MF_LPC_AD1 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 33 , NA , 0x5038 , SOUTHEAST ) , // LPC_AD1 - CHV_GPIO_PAD_CONF (L"SE60: SPI1_MISO ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 34 , NA , 0x5400 , SOUTHEAST ) , // SPI1_MISO - CHV_GPIO_PAD_CONF (L"SE61: SPI1_CS0_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 35 , NA , 0x5408 , SOUTHEAST ) , // SPI1_CS0_N - CHV_GPIO_PAD_CONF (L"SE62: SPI1_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 36 , NA , 0x5410 , SOUTHEAST ) , // SPI1_CLK - CHV_GPIO_PAD_CONF (L"SE63: MMC1_D6 ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 37 , NA , 0x5418 , SOUTHEAST ) , // EMMC1_D6 - CHV_GPIO_PAD_CONF (L"SE64: SPI1_MOSI ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 38 , NA , 0x5420 , SOUTHEAST ) , // SPI1_MOSI - CHV_GPIO_PAD_CONF (L"SE65: MMC1_D5 ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 39 , NA , 0x5428 , SOUTHEAST ) , // EMMC1_D5 - CHV_GPIO_PAD_CONF (L"SE66: SPI1_CS1_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 40 , NA , 0x5430 , SOUTHEAST ) , // SPI1_CS1_N - CHV_GPIO_PAD_CONF (L"SE67: MMC1_D4_SD_WE ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 41 , NA , 0x5438 , SOUTHEAST ) , // EMMC1_D4 - CHV_GPIO_PAD_CONF (L"SE68: MMC1_D7 ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 42 , NA , 0x5440 , SOUTHEAST ) , // EMMC1_D7 - CHV_GPIO_PAD_CONF (L"SE69: MMC1_RCLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 43 , NA , 0x5448 , SOUTHEAST ) , // EMMC1_RCLK - CHV_GPIO_PAD_CONF (L"SE75: USB_OC1_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 44 , NA , 0x5800 , SOUTHEAST ) , // USB3_OC1_N - CHV_GPIO_PAD_CONF (L"SE76: PMU_RSTBUTTON_B", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 45 , NA , 0x5808 , SOUTHEAST ) , // SOC_RESETBTN_N special programming below - CHV_GPIO_PAD_CONF (L"SE77: GPIO_ALERT ", GPIO , M1 , GPI , NA , NA , Trig_Level , Line2 , NA , NA , NA , NonMaskable , En_RX_Data , Inv_RX_Data , NA , 46 , NA , 0x5810 , SOUTHEAST ) , // DCN : 2502579 - Programmed for TCH_PAD_INT_N - CHV_GPIO_PAD_CONF (L"SE78: SDMMC3_PWR_EN_B", Native , M1 , NA , NA , NA , NA , NA , P_20K_L , NA , NA , NA , NA , No_Inversion , NA , 47 , NA , 0x5818 , SOUTHEAST ) , // SD_CARD_PWRDN_N - CHV_GPIO_PAD_CONF (L"SE79: ILB_SERIRQ ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 48 , NA , 0x5820 , SOUTHEAST ) , // ILB_SERIRQ - CHV_GPIO_PAD_CONF (L"SE80: USB_OC0_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 49 , NA , 0x5828 , SOUTHEAST ) , // USB3_OC0_N - CHV_GPIO_PAD_CONF (L"SE81: SDMMC3_CD_B ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 50 , NA , 0x5830 , SOUTHEAST ) , // SD_CARD_DET_N - CHV_GPIO_PAD_CONF (L"SE82: SPKR ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 51 , NA , 0x5838 , SOUTHEAST ) , // SPKR - CHV_GPIO_PAD_CONF (L"SE83: SUSPWRDNACK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 52 , NA , 0x5840 , SOUTHEAST ) , // SUSPWRDNACK_3P3 - CHV_GPIO_PAD_CONF (L"SE84: SPARE_PIN ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 53 , NA , 0x5848 , SOUTHEAST ) , // SPARE_PIN - CHV_GPIO_PAD_CONF (L"SE85: SDMMC3_1P8_EN ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 54 , NA , 0x5850 , SOUTHEAST ) , // SD_CARD_PWR_EN - // - // South west Community - // Group Pin#: PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks - // - CHV_GPIO_PAD_CONF (L"SW00: FST_SPI_D2 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 0 , NA , 0x4400 , SOUTHWEST ) , // FST_SPI_D2 - CHV_GPIO_PAD_CONF (L"SW01: FST_SPI_D0 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 1 , NA , 0x4408 , SOUTHWEST ) , // FST_SPI_D0 - CHV_GPIO_PAD_CONF (L"SW02: FST_SPI_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 2 , NA , 0x4410 , SOUTHWEST ) , // FAST_SPI_CLK - CHV_GPIO_PAD_CONF (L"SW03: FST_SPI_D3 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 3 , NA , 0x4418 , SOUTHWEST ) , // FST_SPI_D3 - CHV_GPIO_PAD_CONF (L"SW04: FST_SPI_CS1_B ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 4 , NA , 0x4420 , SOUTHWEST ) , // V3P3DX_TCH_EN - CHV_GPIO_PAD_CONF (L"SW05: FST_SPI_D1 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 5 , NA , 0x4428 , SOUTHWEST ) , // FST_SPI_D1 - CHV_GPIO_PAD_CONF (L"SW06: FST_SPI_CS0_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 6 , NA , 0x4430 , SOUTHWEST ) , // FST_SPI_CS_N - CHV_GPIO_PAD_CONF (L"SW07: FST_SPI_CS2_B ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 7 , NA , 0x4438 , SOUTHWEST ) , // FST_SPI_CS2_N (SPI TPM) - CHV_GPIO_PAD_CONF (L"SW15: UART1_RTS_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 8 , NA , 0x4800 , SOUTHWEST ) , // UART_BT_RTS - CHV_GPIO_PAD_CONF (L"SW16: UART1_RXD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 9 , NA , 0x4808 , SOUTHWEST ) , // UART_BT_RXD - CHV_GPIO_PAD_CONF (L"SW17: UART2_RXD ", Native , M1 , NA , NA , NA , NA , NA , P_NONE , NA , NA , NA , NA , No_Inversion , NA , 10 , NA , 0x4810 , SOUTHWEST ) , // UART_GPS_RXD - CHV_GPIO_PAD_CONF (L"SW18: UART1_CTS_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 11 , NA , 0x4818 , SOUTHWEST ) , // UART_BT_CTS - CHV_GPIO_PAD_CONF (L"SW19: UART2_RTS_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 12 , NA , 0x4820 , SOUTHWEST ) , // UART_GPS_RTS - CHV_GPIO_PAD_CONF (L"SW20: UART1_TXD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 13 , NA , 0x4828 , SOUTHWEST ) , // UART_BT_TXD - CHV_GPIO_PAD_CONF (L"SW21: UART2_TXD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 14 , NA , 0x4830 , SOUTHWEST ) , // UART_GPS_TXD - CHV_GPIO_PAD_CONF (L"SW22: UART2_CTS_B ", Native , M1 , NA , NA , NA , NA , NA , P_NONE , NA , NA , NA , NA , No_Inversion , NA , 15 , NA , 0x4838 , SOUTHWEST ) , // UART_GPS_CTS - CHV_GPIO_PAD_CONF (L"SW30: MF_HDA_CLK ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 16 , NA , 0x4C00 , SOUTHWEST ) , // MF_HDA_CLK II GP_SSP_0_I2S_TXD - CHV_GPIO_PAD_CONF (L"SW31: MF_HDA_RSTB ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 17 , NA , 0x4C08 , SOUTHWEST ) , // AUD_LINK_RST_N - CHV_GPIO_PAD_CONF (L"SW32: MF_HDA_SDI0 ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 18 , NA , 0x4C10 , SOUTHWEST ) , // AUD_LINK_SDI0_SOC - CHV_GPIO_PAD_CONF (L"SW33: MF_HDA_SDO ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 19 , NA , 0x4C18 , SOUTHWEST ) , // AUD_LINK_SDO - CHV_GPIO_PAD_CONF (L"SW34: MF_HDA_DOCKRSTB", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 20 , NA , 0x4C20 , SOUTHWEST ) , // NGFF_I2S_1_TXD_R_BT || I2S_2_TXD_R_AICO - CHV_GPIO_PAD_CONF (L"SW35: MF_HDA_SYNC ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 21 , NA , 0x4C28 , SOUTHWEST ) , // AUD_LINK_SYNC - CHV_GPIO_PAD_CONF (L"SW36: MF_HDA_SDI1 ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 22 , NA , 0x4C30 , SOUTHWEST ) , // AUD_LINK_SDI1_SOC - CHV_GPIO_PAD_CONF (L"SW37: MF_HDA_DOCKENB ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 23 , NA , 0x4C38 , SOUTHWEST ) , // NGFF_I2S_1_RXD_R_BT || I2S_2_RXD_R_AICO - CHV_GPIO_PAD_CONF (L"SW45: I2C5_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 24 , NA , 0x5000 , SOUTHWEST ) , // I2C5_SDA_3P3 - CHV_GPIO_PAD_CONF (L"SW46: I2C4_SDA ", Native , M3 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 25 , NA , 0x5008 , SOUTHWEST ) , // HV_DDI2_DDC_SDA - CHV_GPIO_PAD_CONF (L"SW47: I2C6_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 26 , NA , 0x5010 , SOUTHWEST ) , // - CHV_GPIO_PAD_CONF (L"SW48: I2C5_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 27 , NA , 0x5018 , SOUTHWEST ) , // I2C5_SDA_3P3 - CHV_GPIO_PAD_CONF (L"SW49: I2C_NFC_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 28 , NA , 0x5020 , SOUTHWEST ) , // I2C_NFC_SDA_3P3 - CHV_GPIO_PAD_CONF (L"SW50: I2C4_SCL ", Native , M3 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 29 , NA , 0x5028 , SOUTHWEST ) , // HV_DDI2_DDC_SCL - CHV_GPIO_PAD_CONF (L"SW51: I2C6_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 30 , NA , 0x5030 , SOUTHWEST ) , // - CHV_GPIO_PAD_CONF (L"SW52: I2C_NFC_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 31 , NA , 0x5038 , SOUTHWEST ) , // I2C_NFC_SCL_3P3 - CHV_GPIO_PAD_CONF (L"SW60: I2C1_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 32 , NA , 0x5400 , SOUTHWEST ) , // I2C1_SCL_AUD_CONN - CHV_GPIO_PAD_CONF (L"SW61: I2C0_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 33 , NA , 0x5408 , SOUTHWEST ) , // I2C_3P3_NGFF_SCL - CHV_GPIO_PAD_CONF (L"SW62: I2C2_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 34 , NA , 0x5410 , SOUTHWEST ) , // I2C2_SCL_CAM - CHV_GPIO_PAD_CONF (L"SW63: I2C1_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 35 , NA , 0x5418 , SOUTHWEST ) , // I2C1_SDA_AUD_CONN - CHV_GPIO_PAD_CONF (L"SW64: I2C3_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 36 , NA , 0x5420 , SOUTHWEST ) , // I2C3_CAM_SCL - CHV_GPIO_PAD_CONF (L"SW65: I2C0_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 37 , NA , 0x5428 , SOUTHWEST ) , // I2C_3P3_NGFF_SDA - CHV_GPIO_PAD_CONF (L"SW66: I2C2_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 38 , NA , 0x5430 , SOUTHWEST ) , // I2C2_SDA_CAM - CHV_GPIO_PAD_CONF (L"SW67: I2C3_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 39 , NA , 0x5438 , SOUTHWEST ) , // I2C3_CAM_SDA - CHV_GPIO_PAD_CONF (L"SW75: SATA_GP0 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 40 , NA , 0x5800 , SOUTHWEST ) , // reserved for SATA (Interlock switch) - CHV_GPIO_PAD_CONF (L"SW76: SATA_GP1 ", GPIO , M1 , GPI , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 41 , NA , 0x5808 , SOUTHWEST ) , // GPI to select UART0 | DDI1 mode - CHV_GPIO_PAD_CONF (L"SW77: SATA_LEDN ", Native , M1 , NA , NA , NA , NA , NA , NA , _ENABLE , NA , NA , NA , No_Inversion , NA , 42 , NA , 0x5810 , SOUTHWEST ) , // SATA_LED_N - CHV_GPIO_PAD_CONF (L"SW78: SATA_GP2 ", Native , M1 , NA , NA , NA , NA , NA , NA , _ENABLE , NA , NA , NA , No_Inversion , NA , 43 , NA , 0x5818 , SOUTHWEST ) , // SATA_DEVSLP0 -need to check - CHV_GPIO_PAD_CONF (L"SW79: MF_SMB_ALERTB ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 44 , NA , 0x5820 , SOUTHWEST ) , // SMB_ALERTB_3P3 - CHV_GPIO_PAD_CONF (L"SW80: SATA_GP3 ", GPIO , M2 , GPI , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 45 , NA , 0x5828 , SOUTHWEST ) , // TOUCH_RST_N -need to check - CHV_GPIO_PAD_CONF (L"SW81: MF_SMB_CLK ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 46 , NA , 0x5830 , SOUTHWEST ) , // SMB_3P3_CLK - CHV_GPIO_PAD_CONF (L"SW82: MF_SMB_DATA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 47 , NA , 0x5838 , SOUTHWEST ) , // SMB_3P3_DAT - CHV_GPIO_PAD_CONF (L"SW90: PCIE_CLKREQ0B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 48 , NA , 0x5C00 , SOUTHWEST ) , // - CHV_GPIO_PAD_CONF (L"SW91: PCIE_CLKREQ1B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 49 , NA , 0x5C08 , SOUTHWEST ) , // PCIE_CLKREQ1_N - CHV_GPIO_PAD_CONF (L"SW92: GP_SSP_2_CLK ", Native , M1 , NA , NA , NA , NA , NA , P_20K_L , NA , NA , NA , NA , No_Inversion , NA , 50 , NA , 0x5C10 , SOUTHWEST ) , // PCIE_CLKREQ1_N - CHV_GPIO_PAD_CONF (L"SW93: PCIE_CLKREQ2B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 51 , NA , 0x5C18 , SOUTHWEST ) , // PCIE_CLKREQ2_N - CHV_GPIO_PAD_CONF (L"SW94: GP_SSP_2_RXD ", Native , M1 , NA , NA , NA , NA , NA , P_20K_L , NA , NA , NA , NA , No_Inversion , NA , 52 , NA , 0x5C20 , SOUTHWEST ) , // - CHV_GPIO_PAD_CONF (L"SW95: PCIE_CLKREQ3B ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 53 , NA , 0x5C28 , SOUTHWEST ) , // SDMMC3_WP (Def) - CHV_GPIO_PAD_CONF (L"SW96: GP_SSP_2_FS ", Native , M1 , NA , NA , NA , NA , NA , P_20K_L , NA , NA , NA , NA , No_Inversion , NA , 54 , NA , 0x5C30 , SOUTHWEST ) , // I2S_2_FS - CHV_GPIO_PAD_CONF (L"SW97: GP_SSP_2_TXD ", Native , M1 , NA , NA , NA , NA , NA , P_20K_L , NA , NA , NA , NA , Inv_TX_Enable , NA , 55 , NA , 0x5C38 , SOUTHWEST ) , // I2S_2_TXD -}; - -CHAR16* GPIOPadNames[GPIO_TABLE_ROW_NUM] = { - // - // North Community - // - L"N00: GPIO_DFX0 ", - L"N01: GPIO_DFX3 ", - L"N02: GPIO_DFX7 ", - L"N03: GPIO_DFX1 ", - L"N04: GPIO_DFX5 ", - L"N05: GPIO_DFX4 ", - L"N06: GPIO_DFX8 ", - L"N07: GPIO_DFX2 ", - L"N08: GPIO_DFX6 ", - L"N15: GPIO_SUS0 ", - L"N16: SEC_GPIO_SUS10 ", - L"N17: GPIO_SUS3 ", - L"N18: GPIO_SUS7 ", - L"N19: GPIO_SUS1 ", - L"N20: GPIO_SUS5 ", - L"N21: SEC_GPIO_SUS11 ", - L"N22: GPIO_SUS4 ", - L"N23: SEC_GPIO_SUS8 ", - L"N24: GPIO_SUS2 ", - L"N25: GPIO_SUS6 ", - L"N26: CX_PREQ_B ", - L"N27: GPIO_SUS9 ", - L"N30: TRST_B ", - L"N31: TCK ", - L"N32: PROCHOT_B ", - L"N33: SVID0_DATA ", - L"N34: TMS ", - L"N35: CX_PRDY_B2 ", - L"N36: TDO_2 ", - L"N37: CX_PRDY_B ", - L"N38: SVID0_ALERT_B ", - L"N39: TDO ", - L"N40: SVID0_CLK ", - L"N41: TDI ", - L"N45: GP_CAMERASB05 ", - L"N46: GP_CAMERASB02 ", - L"N47: GP_CAMERASB08 ", - L"N48: GP_CAMERASB00 ", - L"N49: GP_CAMERASB06 ", - L"N50: GP_CAMERASB10 ", - L"N51: GP_CAMERASB03 ", - L"N52: GP_CAMERASB09 ", - L"N53: GP_CAMERASB01 ", - L"N54: GP_CAMERASB07 ", - L"N55: GP_CAMERASB11 ", - L"N56: GP_CAMERASB04 ", - L"N60: PANEL0_BKLTEN ", - L"N61: HV_DDI0_HPD ", - L"N62: HV_DDI2_DDC_SDA ", - L"N63: PANEL1_BKLTCTL ", - L"N64: HV_DDI1_HPD ", - L"N65: PANEL0_BKLTCTL ", - L"N66: HV_DDI0_DDC_SDA ", - L"N67: HV_DDI2_DDC_SCL ", - L"N68: HV_DDI2_HPD ", - L"N69: PANEL1_VDDEN ", - L"N70: PANEL1_BKLTEN ", - L"N71: HV_DDI0_DDC_SCL ", - L"N72: PANEL0_VDDEN ", - // - // East Community - // - L"E00: PMU_SLP_S3_B ", - L"E01: PMU_BATLOW_B ", - L"E02: SUS_STAT_B ", - L"E03: PMU_SLP_S0IX_B ", - L"E04: PMU_AC_PRESENT ", - L"E05: PMU_PLTRST_B ", - L"E06: PMU_SUSCLK ", - L"E07: PMU_SLP_LAN_B ", - L"E08: PMU_PWRBTN_B ", - L"E09: PMU_SLP_S4_B ", - L"E10: PMU_WAKE_B ", - L"E11: PMU_WAKE_LAN_B ", - L"E15: MF_ISH_GPIO_3 ", - L"E16: MF_ISH_GPIO_7 ", - L"E17: MF_ISH_I2C1_SCL ", - L"E18: MF_ISH_GPIO_1 ", - L"E19: MF_ISH_GPIO_5 ", - L"E20: MF_ISH_GPIO_9 ", - L"E21: MF_ISH_GPIO_0 ", - L"E22: MF_ISH_GPIO_4 ", - L"E23: MF_ISH_GPIO_8 ", - L"E24: MF_ISH_GPIO_2 ", - L"E25: MF_ISH_GPIO_6 ", - L"E26: MF_ISH_I2C1_SDA ", - // - // South East Community - // - L"SE00: MF_PLT_CLK0 ", - L"SE01: PWM1 ", - L"SE02: MF_PLT_CLK1 ", - L"SE03: MF_PLT_CLK4 ", - L"SE04: MF_PLT_CLK3 ", - L"SE05: PWM0 ", - L"SE06: MF_PLT_CLK5 ", - L"SE07: MF_PLT_CLK2 ", - L"SE15: SDMMC2_D3_CD_B ", - L"SE16: SDMMC1_CLK ", - L"SE17: SDMMC1_D0 ", - L"SE18: SDMMC2_D1 ", - L"SE19: SDMMC2_CLK ", - L"SE20: SDMMC1_D2 ", - L"SE21: SDMMC2_D2 ", - L"SE22: SDMMC2_CMD ", - L"SE23: SDMMC1_CMD ", - L"SE24: SDMMC1_D1 ", - L"SE25: SDMMC2_D0 ", - L"SE26: SDMMC1_D3_CD_B ", - L"SE30: SDMMC3_D1 ", - L"SE31: SDMMC3_CLK ", - L"SE32: SDMMC3_D3 ", - L"SE33: SDMMC3_D2 ", - L"SE34: SDMMC3_CMD ", - L"SE35: SDMMC3_D0 ", - L"SE45: MF_LPC_AD2 ", - L"SE46: LPC_CLKRUNB ", - L"SE47: MF_LPC_AD0 ", - L"SE48: LPC_FRAMEB ", - L"SE49: MF_LPC_CLKOUT1 ", - L"SE50: MF_LPC_AD3 ", - L"SE51: MF_LPC_CLKOUT0 ", - L"SE52: MF_LPC_AD1 ", - L"SE60: SPI1_MISO ", - L"SE61: SPI1_CS0_B ", - L"SE62: SPI1_CLK ", - L"SE63: MMC1_D6 ", - L"SE64: SPI1_MOSI ", - L"SE65: MMC1_D5 ", - L"SE66: SPI1_CS1_B ", - L"SE67: MMC1_D4_SD_WE ", - L"SE68: MMC1_D7 ", - L"SE69: MMC1_RCLK ", - L"SE75: USB_OC1_B ", - L"SE76: PMU_RSTBUTTON_B", - L"SE77: GPIO_ALERT ", - L"SE78: SDMMC3_PWR_EN_B", - L"SE79: ILB_SERIRQ ", - L"SE80: USB_OC0_B ", - L"SE81: SDMMC3_CD_B ", - L"SE82: SPKR ", - L"SE83: SUSPWRDNACK ", - L"SE84: SPARE_PIN ", - L"SE85: SDMMC3_1P8_EN ", - // - // South west Community - // - L"SW00: FST_SPI_D2 ", - L"SW01: FST_SPI_D0 ", - L"SW02: FST_SPI_CLK ", - L"SW03: FST_SPI_D3 ", - L"SW04: FST_SPI_CS1_B ", - L"SW05: FST_SPI_D1 ", - L"SW06: FST_SPI_CS0_B ", - L"SW07: FST_SPI_CS2_B ", - L"SW15: UART1_RTS_B ", - L"SW16: UART1_RXD ", - L"SW17: UART2_RXD ", - L"SW18: UART1_CTS_B ", - L"SW19: UART2_RTS_B ", - L"SW20: UART1_TXD ", - L"SW21: UART2_TXD ", - L"SW22: UART2_CTS_B ", - L"SW30: MF_HDA_CLK ", - L"SW31: MF_HDA_RSTB ", - L"SW32: MF_HDA_SDI0 ", - L"SW33: MF_HDA_SDO ", - L"SW34: MF_HDA_DOCKRSTB", - L"SW35: MF_HDA_SYNC ", - L"SW36: MF_HDA_SDI1 ", - L"SW37: MF_HDA_DOCKENB ", - L"SW45: I2C5_SDA ", - L"SW46: I2C4_SDA ", - L"SW47: I2C6_SDA ", - L"SW48: I2C5_SCL ", - L"SW49: I2C_NFC_SDA ", - L"SW50: I2C4_SCL ", - L"SW51: I2C6_SCL ", - L"SW52: I2C_NFC_SCL ", - L"SW60: I2C1_SDA ", - L"SW61: I2C0_SDA ", - L"SW62: I2C2_SDA ", - L"SW63: I2C1_SCL ", - L"SW64: I2C3_SDA ", - L"SW65: I2C0_SCL ", - L"SW66: I2C2_SCL ", - L"SW67: I2C3_SCL ", - L"SW75: SATA_GP0 ", - L"SW76: SATA_GP1 ", - L"SW77: SATA_LEDN ", - L"SW78: SATA_GP2 ", - L"SW79: MF_SMB_ALERTB ", - L"SW80: SATA_GP3 ", - L"SW81: MF_SMB_CLK ", - L"SW82: MF_SMB_DATA ", - L"SW90: PCIE_CLKREQ0B ", - L"SW91: PCIE_CLKREQ1B ", - L"SW92: GP_SSP_2_CLK ", - L"SW93: PCIE_CLKREQ2B ", - L"SW94: GP_SSP_2_RXD ", - L"SW95: PCIE_CLKREQ3B ", - L"SW96: GP_SSP_2_FS ", - L"SW97: GP_SSP_2_TXD " -}; - -UINT16 GPIOMmioOffset[GPIO_TABLE_ROW_NUM] = { - // - // North Community - // - 0x4400 , - 0x4408 , - 0x4410 , - 0x4418 , - 0x4420 , - 0x4428 , - 0x4430 , - 0x4438 , - 0x4440 , - 0x4800 , - 0x4808 , - 0x4810 , - 0x4818 , - 0x4820 , - 0x4828 , - 0x4830 , - 0x4838 , - 0x4840 , - 0x4848 , - 0x4850 , - 0x4858 , - 0x4860 , - 0x4C00 , - 0x4C08 , - 0x4C10 , - 0x4C18 , - 0x4C20 , - 0x4C28 , - 0x4C30 , - 0x4C38 , - 0x4C40 , - 0x4C48 , - 0x4C50 , - 0x4C58 , - 0x5000 , - 0x5008 , - 0x5010 , - 0x5018 , - 0x5020 , - 0x5028 , - 0x5030 , - 0x5038 , - 0x5040 , - 0x5048 , - 0x5050 , - 0x5058 , - 0x5400 , - 0x5408 , - 0x5410 , - 0x5418 , - 0x5420 , - 0x5428 , - 0x5430 , - 0x5438 , - 0x5440 , - 0x5448 , - 0x5450 , - 0x5458 , - 0x5460 , - // - // East Community - // - 0x4400 , - 0x4408 , - 0x4410 , - 0x4418 , - 0x4420 , - 0x4428 , - 0x4430 , - 0x4438 , - 0x4440 , - 0x4448 , - 0x4450 , - 0x4458 , - 0x4800 , - 0x4808 , - 0x4810 , - 0x4818 , - 0x4820 , - 0x4828 , - 0x4830 , - 0x4838 , - 0x4840 , - 0x4848 , - 0x4850 , - 0x4858 , - // - // South East Community - // - 0x4400 , - 0x4408 , - 0x4410 , - 0x4418 , - 0x4420 , - 0x4428 , - 0x4430 , - 0x4438 , - 0x4800 , - 0x4808 , - 0x4810 , - 0x4818 , - 0x4820 , - 0x4828 , - 0x4830 , - 0x4838 , - 0x4840 , - 0x4848 , - 0x4850 , - 0x4858 , - 0x4C00 , - 0x4C08 , - 0x4C10 , - 0x4C18 , - 0x4C20 , - 0x4C28 , - 0x5000 , - 0x5008 , - 0x5010 , - 0x5018 , - 0x5020 , - 0x5028 , - 0x5030 , - 0x5038 , - 0x5400 , - 0x5408 , - 0x5410 , - 0x5418 , - 0x5420 , - 0x5428 , - 0x5430 , - 0x5438 , - 0x5440 , - 0x5448 , - 0x5800 , - 0x5808 , - 0x5810 , - 0x5818 , - 0x5820 , - 0x5828 , - 0x5830 , - 0x5838 , - 0x5840 , - 0x5848 , - 0x5850 , - // - // South west Community - // - 0x4400 , - 0x4408 , - 0x4410 , - 0x4418 , - 0x4420 , - 0x4428 , - 0x4430 , - 0x4438 , - 0x4800 , - 0x4808 , - 0x4810 , - 0x4818 , - 0x4820 , - 0x4828 , - 0x4830 , - 0x4838 , - 0x4C00 , - 0x4C08 , - 0x4C10 , - 0x4C18 , - 0x4C20 , - 0x4C28 , - 0x4C30 , - 0x4C38 , - 0x5000 , - 0x5008 , - 0x5010 , - 0x5018 , - 0x5020 , - 0x5028 , - 0x5030 , - 0x5038 , - 0x5400 , - 0x5408 , - 0x5410 , - 0x5418 , - 0x5420 , - 0x5428 , - 0x5430 , - 0x5438 , - 0x5800 , - 0x5808 , - 0x5810 , - 0x5818 , - 0x5820 , - 0x5828 , - 0x5830 , - 0x5838 , - 0x5C00 , - 0x5C08 , - 0x5C10 , - 0x5C18 , - 0x5C20 , - 0x5C28 , - 0x5C30 , - 0x5C38 -}; - -UINT8 WakeMaskBit[GPIO_TABLE_ROW_NUM] = { - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25, - 26, - 27, - 28, - 29, - 30, - 31, - 32, - 33, - 34, - 35, - 36, - 37, - 38, - 39, - 40, - 41, - 42, - 43, - 44, - 45, - 46, - 47, - 48, - 49, - 50, - 51, - 52, - 53, - 54, - 55, - 56, - 57, - 58, - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 0, - 1, - 1, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25, - 26, - 27, - 28, - 29, - 30, - 31, - 32, - 33, - 34, - 35, - 36, - 37, - 38, - 39, - 40, - 41, - 42, - 43, - 44, - 45, - 46, - 47, - 48, - 49, - 50, - 51, - 52, - 53, - 54, - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25, - 26, - 27, - 28, - 29, - 30, - 31, - 32, - 33, - 34, - 35, - 36, - 37, - 38, - 39, - 40, - 41, - 42, - 43, - 44, - 45, - 46, - 47, - 48, - 49, - 50, - 51, - 52, - 53, - 54, - 55 -}; - +#include "BoardInit.h" +#include "BoardGpios.h" EFI_STATUS GetBoardFabIdsKsc ( @@ -894,280 +58,6 @@ static EFI_PEI_PPI_DESCRIPTOR mBraswellCherryHillDetectedPpi = { NULL }; -VOID -ProgramGpiosWithPcd ( - IN UINT32 Gpio_Mmio_Offset, - IN UINT32 Gpio_Pin_Num, - IN PLATFORM_GPIO_TABLE_ROW* GpioRowPtr - ) -{ - CHV_GPIO_PAD_INIT GpioConfTable[GPIO_TABLE_ROW_NUM]; - UINT8 RowIndex; - UINT8 Mode_Select = 0; - UINT8 Mode = 0; - UINT8 GPIO_Config = NA; - UINT8 GPIO_STATE = NA; - UINT8 Gpio_Light_Mode = NA; - UINT8 INT_Type = NA; - UINT8 INT_S = NA; - UINT8 Term_H_L = NA; - UINT8 Open_Drain = NA; - UINT8 Current_Source = NA; - UINT8 Int_Mask = NA; - UINT8 Glitch_Cfg = NA; - UINT8 InvertRX_TX = NA; - UINT8 WAKE_Mask = NA; - UINT8 Wake_Mask_Bit = NA; - UINT8 GPE = NA; - UINT16 MMIO_Offset = 0; - UINT32 Community = 0; - - RowIndex = 0; - while (GpioRowPtr->Usage != USAGE_None) { -#ifdef EFI_DEBUG - GpioConfTable[RowIndex].pad_name = GPIOPadNames[RowIndex]; -#endif - - // - // Mode select & GPIO_Config - // - switch (GpioRowPtr->Usage) { - case USAGE_GPIO: - Mode_Select = GPIO; - GPIO_Config = GPIO; - break; - case USAGE_GPO: - Mode_Select = GPIO; - GPIO_Config = GPO; - break; - case USAGE_GPI: - Mode_Select = GPIO; - GPIO_Config = GPI; - break; - case USAGE_HIZ: - Mode_Select = GPIO; - GPIO_Config = HI_Z; - break; - case USAGE_Native: - Mode_Select = Native; - GPIO_Config = NA; - break; - default: - ASSERT(FALSE); - break; - } - // - // Function Number - // - Mode = GpioRowPtr->FuncNum; - // - // GPIO state - // - switch (GpioRowPtr->InitLevel) { - case GPIO_ATTRIBUTE_LOW: - GPIO_STATE = LOW; - break; - case GPIO_ATTRIBUTE_HIGH: - GPIO_STATE = HIGH; - break; - case NA: - GPIO_STATE = NA; - break; - default: - ASSERT(FALSE); - break; - } - // - // Gpio_Light_Mode - // - switch (GpioRowPtr->LightModeBar) { - case GPIO_ATTRIBUTE_HIGH: - Gpio_Light_Mode = HIGH; - break; - case GPIO_ATTRIBUTE_LOW: - Gpio_Light_Mode = LOW; - break; - case NA: - Gpio_Light_Mode = NA; - break; - default: - ASSERT(FALSE); - break; - } - // - // INT_Type - // - switch (GpioRowPtr->TrigType) { - case TRIGGER_Edge_High: - INT_Type = Trig_Edge_High; - break; - case TRIGGER_Edge_Low: - INT_Type = Trig_Edge_Low; - break; - case TRIGGER_Edge_Both: - INT_Type = Trig_Edge_Both; - break; - case TRIGGER_Level_High: - INT_Type = Trig_Level; - break; - case TRIGGER_Level_Low: - INT_Type = Trig_Level; - break; - case TRIGGER_None: - INT_Type = NA; - default: - ; - break; - } - - // - // INT_S - // - INT_S = GpioRowPtr->IntLineNum; - - // - // Term_H_L - // - if (GpioRowPtr->PullDirection == DIRECTION_Pull_Up) { - if (GpioRowPtr->PullStrength == STRENGTH_20K) - Term_H_L = P_20K_H; - else if (GpioRowPtr->PullStrength == STRENGTH_5K) - Term_H_L = P_5K_H; - else if (GpioRowPtr->PullStrength == STRENGTH_1K) - Term_H_L = P_1K_H; - else - Term_H_L = P_NONE; - } else if (GpioRowPtr->PullDirection == DIRECTION_Pull_Down) { - if (GpioRowPtr->PullStrength == STRENGTH_20K) - Term_H_L = P_20K_L; - else if (GpioRowPtr->PullStrength == STRENGTH_5K) - Term_H_L = P_5K_L; - else if (GpioRowPtr->PullStrength == STRENGTH_1K) - Term_H_L = P_1K_L; - else - Term_H_L = P_NONE; - } else { - Term_H_L = NA; - } - - // - // Open_Drain - // - if (GpioRowPtr->DriveType == DRIVE_Open_Drain) { - Open_Drain = _ENABLE; - } else { - Open_Drain = NA; - } - - // - // Int_Mask - // - if (GpioRowPtr->IntLineNum != NA) { - Int_Mask = NonMaskable; - } else { - Int_Mask = NA; - } - - // - // Glitch_Cfg - // - switch (GpioRowPtr->GlitchFilterConfig) { - case GLITCH_DISABLE: - Glitch_Cfg = glitch_Disable; - break; - case GLITCH_EN_EdgeDetect: - Glitch_Cfg = En_EdgeDetect; - break; - case GLITCH_EN_RX_Data: - Glitch_Cfg = En_RX_Data; - break; - case GLITCH_EN_Edge_RX_Data: - Glitch_Cfg = En_Edge_RX_Data; - break; - default: - Glitch_Cfg = NA; - break; - } - - // - // InvertRX_TX - // - switch (GpioRowPtr->InvertRxTx) { - case GPIO_No_Inversion: - InvertRX_TX = No_Inversion; - break; - case GPIO_Inv_RX_Enable: - InvertRX_TX = Inv_RX_Enable; - break; - case GPIO_Inv_TX_Enable: - InvertRX_TX = Inv_TX_Enable; - break; - case GPIO_Inv_RX_TX_Enable: - InvertRX_TX = Inv_RX_TX_Enable; - break; - case GPIO_Inv_RX_Data: - InvertRX_TX = Inv_RX_Data; - break; - case GPIO_Inv_TX_Data: - InvertRX_TX = Inv_TX_Data; - break; - default: - Glitch_Cfg = NA; - break; - } - - // - // Community - // - if (RowIndex < GPIO_TABLE_NORTH_ROW_NUM) { - Community = NORTH; - } else if (RowIndex < ( GPIO_TABLE_NORTH_ROW_NUM + GPIO_TABLE_EAST_ROW_NUM )){ - Community = EAST; - } else if (RowIndex < ( GPIO_TABLE_NORTH_ROW_NUM + GPIO_TABLE_EAST_ROW_NUM + GPIO_TABLE_SOUTHEAST_ROW_NUM)){ - Community = SOUTHEAST; - } else if (RowIndex < GPIO_TABLE_ROW_NUM ){ - Community = SOUTHWEST; - } - - // - // Wake_Mask_Bit - // - Wake_Mask_Bit = WakeMaskBit[RowIndex]; - - // - // GPE - // - if ( GpioRowPtr->IntType == INT_SCI ) { - GPE = SCI; - } else if ( GpioRowPtr->IntType == INT_SMI ){ - GPE = SMI; - } else { - GPE = NA; - } - - // - // MMIO_Offset - // - MMIO_Offset = GPIOMmioOffset[RowIndex]; - - GpioConfTable[RowIndex].padConfg0.padCnf0 = CHV_GPIO_PAD_CONFG0(Mode_Select, Mode, GPIO_Config, GPIO_STATE, Gpio_Light_Mode, INT_S, Term_H_L, Glitch_Cfg); - GpioConfTable[RowIndex].padConfg0_changes.padCnf0= CHV_GPIO_PAD_CONFG0_CHANGE(GPIO_Config, GPIO_STATE, Gpio_Light_Mode, INT_S, Term_H_L, Glitch_Cfg); - GpioConfTable[RowIndex].padConfg1.padCnf1 = CHV_GPIO_PAD_CONFG1(INT_Type, Open_Drain, Current_Source, InvertRX_TX); - GpioConfTable[RowIndex].padConfg1_changes.padCnf1 = CHV_GPIO_PAD_CONFG1_CHANGE(INT_Type, Open_Drain, Current_Source, InvertRX_TX); - GpioConfTable[RowIndex].PAD_MISC.micsData = CHV_GPIO_PAD_MISC(Int_Mask, WAKE_Mask,Wake_Mask_Bit, GPE); - GpioConfTable[RowIndex].Community = Community; - GpioConfTable[RowIndex].MMIO_ADDRESS = CHV_GPIO_PAD_MMIO(MMIO_Offset, Community); - - GpioRowPtr++; - RowIndex++; - if (RowIndex >= Gpio_Pin_Num) - break; - } - - ASSERT(RowIndex == Gpio_Pin_Num); - InternalGpioPADConfig (Gpio_Mmio_Offset, Gpio_Pin_Num, GpioConfTable); -} - EFI_STATUS EFIAPI BraswellCherryHillBoardDetectionCallback ( @@ -1183,7 +73,6 @@ BraswellCherryHillBoardDetectionCallback ( UINT8 FabId; EFI_STATUS Status; VOID *Instance; - PLATFORM_GPIO_TABLE_ROW* GpioRowPtr; Status = PeiServicesLocatePpi ( &gBoardDetectedPpiGuid, @@ -1203,52 +92,73 @@ BraswellCherryHillBoardDetectionCallback ( if (Status != EFI_SUCCESS) { GetBoradFabIdsGpio (&BoardId, &FabId); if (BoardId == 1) { + + // + // Collect board specific configuration for CherryHill CRB. + // + + // + // ID + // PlatformInfoHob.BoardId = BOARD_ID_BSW_CH; + PlatformInfoHob.FABID = FabId; + PlatformInfoHob.PlatformFlavor = FlavorMobile; + + // + // Power + // PlatformInfoHob.BoardSvidConfig = BSW_SVID_CONFIG0; if (SocStepping() >= SocC0) { PlatformInfoHob.BoardSvidConfig = BSW_SVID_CONFIG1; } - DEBUG ((EFI_D_INFO, "I'm Braswell Cherry Hill \n\n")); - DEBUG ((EFI_D_INFO, "SoC Stepping = 0x%x \n", ((UINT32)SocStepping()))); - PlatformInfoHob.MemCfgID = 0; - DEBUG ((EFI_D_INFO, "PlatformInfoHob->MemCfgID= 0x%x\n", PlatformInfoHob.MemCfgID)); - PlatformInfoHob.FABID = FabId; - DEBUG ((EFI_D_INFO, "PlatformInfoHob->FABID = 0x%x\n", FabId )); - PlatformInfoHob.PlatformFlavor = FlavorMobile; - DEBUG ((EFI_D_INFO, "PlatformInfoHob->PlatformFlavor = 0x%x\n", PlatformInfoHob.PlatformFlavor )); - DEBUG ((EFI_D_INFO, "PlatformInfoHob->BoardSvidConfig = 0x%x\n", PlatformInfoHob.BoardSvidConfig )); - DEBUG ((EFI_D_INFO, "PlatformInfoHob->BoardId = 0x%x\n", PlatformInfoHob.BoardId )); + // + // EC, Fan, Battery + // PlatformInfoHob.ECSupport = FALSE; PlatformInfoHob.FanSupport = FALSE; PlatformInfoHob.BatterySupport = FALSE; - DataSize = sizeof (EFI_PLATFORM_INFO_HOB); - PcdSetPtr (PcdPlatformInfo, &DataSize, &PlatformInfoHob); + // + // Memory + // + PlatformInfoHob.MemCfgID = 0; + PcdSet8 (PcdOemMemeoryDimmType,DimmInstalled); + + // + // Grpahic, Video, Display + // DataSize = sizeof (EFI_GUID); PcdSetPtr (PcdBmpImageGuid, &DataSize, &gHdmiDpVbtGuid); + // + // Communication + // PcdSet8 (PcdNfcConnection, 0); - PcdSet8 (PcdOemMemeoryDimmType,DimmInstalled); - // - // Config SC/NC/SUS GPIO Pins + // GPIO // - GpioRowPtr = (PLATFORM_GPIO_TABLE_ROW*)PcdGetPtr (PcdPlatformGpioTable); - if (GpioRowPtr->Usage == USAGE_None) { - // Program all the gpios from the default GPIO table - InternalGpioPADConfig(0, sizeof(mBswCherryHillGpioInitData)/sizeof(mBswCherryHillGpioInitData[0]), mBswCherryHillGpioInitData); - } else { - // - // Use the GPIO table from pcd to initialize North/East/SouthWest/SouthEast GPIO Pins - // - DEBUG ((EFI_D_INFO, "Use GPIO table from pcd to config GPIO pins\n")); - ProgramGpiosWithPcd (0, GPIO_TABLE_ROW_NUM, &GpioRowPtr[0]); - } + CherryHillBoardGpioConfigure(); + PcdSet64 (PcdGpioInitFunc, (UINT64)(UINTN)BraswellCherryHillAdditionalGpioInit); + + // + // Expose EFI_PLATFORM_INFO_HOB + // + DataSize = sizeof (EFI_PLATFORM_INFO_HOB); + PcdSetPtr (PcdPlatformInfo, &DataSize, &PlatformInfoHob); Status = PeiServicesInstallPpi (&mBraswellCherryHillDetectedPpi); + + DEBUG ((EFI_D_INFO, "PlatformInfoHob->FABID = 0x%x\n", FabId )); + DEBUG ((EFI_D_INFO, "I'm Braswell Cherry Hill \n\n")); + DEBUG ((EFI_D_INFO, "SoC Stepping = 0x%x \n", ((UINT32)SocStepping()))); + DEBUG ((EFI_D_INFO, "PlatformInfoHob->MemCfgID= 0x%x\n", PlatformInfoHob.MemCfgID)); + DEBUG ((EFI_D_INFO, "PlatformInfoHob->PlatformFlavor = 0x%x\n", PlatformInfoHob.PlatformFlavor )); + DEBUG ((EFI_D_INFO, "PlatformInfoHob->BoardSvidConfig = 0x%x\n", PlatformInfoHob.BoardSvidConfig )); + DEBUG ((EFI_D_INFO, "PlatformInfoHob->BoardId = 0x%x\n", PlatformInfoHob.BoardId )); + } } @@ -1275,3 +185,4 @@ BraswellCherryHillInitConstructor ( return Status; } + diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInit.h b/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInit.h new file mode 100644 index 0000000000..b4cb4fbd97 --- /dev/null +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInit.h @@ -0,0 +1,37 @@ +/** @file + GPIO setting for CherryView. + + This file includes package header files, library classes. + + Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _BOARDINIT_H_ +#define _BOARDINIT_H_ + +#include +#include "PchAccess.h" +#include "PlatformBaseAddresses.h" +#include +#include +#include +#include +#include +#include + + +VOID +BraswellCherryHillAdditionalGpioInit ( + VOID + ); +#endif + diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInit.inf b/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInit.inf index 0d59894539..077d543d8f 100644 --- a/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInit.inf +++ b/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInit.inf @@ -25,6 +25,7 @@ [Sources] BoardInit.c + BoardGpios.c [LibraryClasses] PeiServicesLib @@ -49,8 +50,21 @@ ## SOMETIMES_PRODUCES gEfiEdkIIPlatformTokenSpaceGuid.PcdOemMemeoryDimmType - ## CONSUMES - gPlatformModuleTokenSpaceGuid.PcdPlatformGpioTable + ## SOMETIMES_CONSUMES + gEfiEdkIIPlatformTokenSpaceGuid.PcdPlatformInfo + + ## SOMETIMES_PRODUCES + gEfiEdkIIPlatformTokenSpaceGuid.PcdGpioInitFunc + + ## SOMETIMES_CONSUMES + gPlatformModuleTokenSpaceGuid.PcdGPIOSUS6Configuration + + ## SOMETIMES_CONSUMES + gPlatformModuleTokenSpaceGuid.PcdGPIOSUS7Configuration + + ## SOMETIMES_CONSUMES + gPlatformModuleTokenSpaceGuid.PcdGPIOSUS8Configuration + [Guids] ## SOMETIMES_CONSUMES @@ -63,3 +77,4 @@ ## SOMETIMES_PRODUCES ## SOMETIMES_CONSUMES gBoardDetectedPpiGuid + diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInitLate.c b/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInitLate.c deleted file mode 100644 index 7321160b78..0000000000 --- a/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInitLate.c +++ /dev/null @@ -1,69 +0,0 @@ -/** @file - Board Init driver. - - Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php. - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "BoardGpios.h" - -VOID -SAI_SettingOfGpioFamilies ( - GPIO_SAI_INIT* SAI_Conf_Data, - UINT32 familySize - ); - -VOID -BraswellCherryHillGpioInit ( - VOID - ) -{ - DEBUG ((EFI_D_ERROR, "Programming BSW CR Board Gpio Tables which are not done properly by FSP...\n")); - - // GPIO lock if really want - SAI_SettingOfGpioFamilies(mBSW_CH_GPIO_SAI_Init_East, sizeof(mBSW_CH_GPIO_SAI_Init_East)/sizeof(mBSW_CH_GPIO_SAI_Init_East[0])); - SAI_SettingOfGpioFamilies(mBSW_CH_GPIO_SAI_Init_North, sizeof(mBSW_CH_GPIO_SAI_Init_North)/sizeof(mBSW_CH_GPIO_SAI_Init_North[0])); - SAI_SettingOfGpioFamilies(mBSW_CH_GPIO_SAI_Init_SouthEast, sizeof(mBSW_CH_GPIO_SAI_Init_SouthEast)/sizeof(mBSW_CH_GPIO_SAI_Init_SouthEast[0])); - SAI_SettingOfGpioFamilies(mBSW_CH_GPIO_SAI_Init_SouthWest, sizeof(mBSW_CH_GPIO_SAI_Init_SouthWest)/sizeof(mBSW_CH_GPIO_SAI_Init_SouthWest[0])); -} - -/** - This function performs Board initialization in Pre-Memory. - - @retval EFI_SUCCESS The PPI is installed and initialized. - @retval EFI ERRORS The PPI is not successfully installed. - @retval EFI_OUT_OF_RESOURCES No enough resoruces (such as out of memory). -**/ -EFI_STATUS -EFIAPI -BraswellCherryHillInitLateConstructor ( - IN EFI_PEI_FILE_HANDLE FileHandle, - IN CONST EFI_PEI_SERVICES **PeiServices - ) -{ - EFI_PLATFORM_INFO_HOB *PlatformInfoHob; - - PlatformInfoHob = PcdGetPtr (PcdPlatformInfo); - if (PlatformInfoHob->BoardId == BOARD_ID_BSW_CH) { - PcdSet64 (PcdGpioInitFunc, (UINT64)(UINTN)BraswellCherryHillGpioInit); - } - - return EFI_SUCCESS; -} diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInitLate.inf b/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInitLate.inf deleted file mode 100644 index a95cc4c34c..0000000000 --- a/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BoardInitLate.inf +++ /dev/null @@ -1,52 +0,0 @@ -## @file -# GPIO porting module for Intel(R) Atom(TM) x5 Processor Series. -# -# This module will do the basic PCH GPIO porting. -# -# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
-# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php. -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -## - -[Defines] - INF_VERSION = 0x00010017 - BASE_NAME = BraswellCherryHillInitLate - FILE_GUID = CC235019-C750-41E4-AF71-A172C07ACE47 - VERSION_STRING = 1.0 - MODULE_TYPE = PEIM - CONSTRUCTOR = BraswellCherryHillInitLateConstructor - -[Sources] - BoardInitLate.c - -[LibraryClasses] - PeiServicesLib - PcdLib - -[Packages] - MdePkg/MdePkg.dec - ChvRefCodePkg/ChvRefCodePkg.dec - BraswellPlatformPkg/BraswellPlatformPkg.dec - -[Pcd] - ## SOMETIMES_CONSUMES - gEfiEdkIIPlatformTokenSpaceGuid.PcdPlatformInfo - - ## SOMETIMES_PRODUCES - gEfiEdkIIPlatformTokenSpaceGuid.PcdGpioInitFunc - -[Ppis] - ## NOTIFY - gBoardDetectionStartPpiGuid - - ## SOMETIMES_PRODUCES - ## SOMETIMES_CONSUMES - gBoardDetectedPpiGuid - diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BraswellCherryHillInitExtra.uni b/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BraswellCherryHillInitExtra.uni deleted file mode 100644 index 245b34a604..0000000000 --- a/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BraswellCherryHillInitExtra.uni +++ /dev/null @@ -1,18 +0,0 @@ -// /** @file -// BraswellCherryHillInit Localized Strings and Content -// -// Copyright (c) 2015, Intel Corporation. All rights reserved.
-// -// This program and the accompanying materials -// are licensed and made available under the terms and conditions of the BSD License -// which accompanies this distribution. The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php. -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -// -// **/ - -#string STR_PROPERTIES_MODULE_NAME #language en-US "Intel® Atom™ x5 Processor Series Init module" - - diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BraswellCherryHillInitLateExtra.uni b/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BraswellCherryHillInitLateExtra.uni deleted file mode 100644 index 0adafe50d0..0000000000 --- a/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/BraswellCherryHillInitLateExtra.uni +++ /dev/null @@ -1,18 +0,0 @@ -// /** @file -// /BraswellCherryHillInitLate Localized Strings and Content -// -// Copyright (c) 2015, Intel Corporation. All rights reserved.
-// -// This program and the accompanying materials -// are licensed and made available under the terms and conditions of the BSD License -// which accompanies this distribution. The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php. -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -// -// **/ - -#string STR_PROPERTIES_MODULE_NAME #language en-US "Intel® Atom™ x5 Processor Series Init Late module" - - diff --git a/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/Dram.h b/BraswellPlatformPkg/Board/BraswellCherryHill/BoardInit/Dram.h new file mode 100644 index 0000000000..e69de29bb2 diff --git a/BraswellPlatformPkg/Board/WesternDigital/BoardInit/BoardGpios.c b/BraswellPlatformPkg/Board/WesternDigital/BoardInit/BoardGpios.c new file mode 100644 index 0000000000..a54afac831 --- /dev/null +++ b/BraswellPlatformPkg/Board/WesternDigital/BoardInit/BoardGpios.c @@ -0,0 +1,440 @@ +/** @file + Board Init driver. + + Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "BoardGpios.h" + +// +// TBD: Need update to CH version +// +CHV_GPIO_PAD_INIT mBswWesternDigitalGpioInitData[] = +{ + // + // North Community + // Group Pin#: PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks + CHV_GPIO_PAD_CONF (L"N37: CX_PRDY_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 29 , NA , 0x4C38 , NORTH ) , // PRDY_B + CHV_GPIO_PAD_CONF (L"N35: CX_PRDY_B_2 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 27 , NA , 0x4C28 , NORTH ) , // CX_PRDY_B_2 + CHV_GPIO_PAD_CONF (L"N39: CX_PREQ_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 20 , NA , 0x4858 , NORTH ) , // PREQ_B + CHV_GPIO_PAD_CONF (L"N48: GP_CAMERASB00 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 37 , NA , 0x5018 , NORTH ) , // CAM_ACT_LED + CHV_GPIO_PAD_CONF (L"N53: GP_CAMERASB01 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 42 , NA , 0x5040 , NORTH ) , // FLASH_RESET_N + CHV_GPIO_PAD_CONF (L"N46: GP_CAMERASB02 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 35 , NA , 0x5008 , NORTH ) , // GPIO_FLHD_N + CHV_GPIO_PAD_CONF (L"N51: GP_CAMERASB03 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 40 , NA , 0x5030 , NORTH ) , // XDP_GP_CAMERASB03 + CHV_GPIO_PAD_CONF (L"N56: GP_CAMERASB04 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 45 , NA , 0x5058 , NORTH ) , // FLASH_TRIG + CHV_GPIO_PAD_CONF (L"N45: GP_CAMERASB05 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 34 , NA , 0x5000 , NORTH ) , // FLASH_TORCH + CHV_GPIO_PAD_CONF (L"N49: GP_CAMERASB06 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 38 , NA , 0x5020 , NORTH ) , // CAM1_PWRDWN + CHV_GPIO_PAD_CONF (L"N54: GP_CAMERASB07 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 43 , NA , 0x5048 , NORTH ) , // CAM2_PWRDWN + CHV_GPIO_PAD_CONF (L"N47: GP_CAMERASB08 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 36 , NA , 0x5010 , NORTH ) , // XDP_GP_CAMERASB08 + CHV_GPIO_PAD_CONF (L"N52: GP_CAMERASB09 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 41 , NA , 0x5038 , NORTH ) , // CAM_1_RST_N + CHV_GPIO_PAD_CONF (L"N50: GP_CAMERASB10 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 39 , NA , 0x5028 , NORTH ) , // CAM_2_RST_N + CHV_GPIO_PAD_CONF (L"N55: GP_CAMERASB11 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 44 , NA , 0x5050 , NORTH ) , // CAM_3_RST_N + CHV_GPIO_PAD_CONF (L"N00: GPIO_DFX0 ", Native , M5 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 0 , NA , 0x4400 , NORTH ) , // C0_BPM0_TX + CHV_GPIO_PAD_CONF (L"N03: GPIO_DFX1 ", Native , M5 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 3 , NA , 0x4418 , NORTH ) , // C0_BPM1_TX + CHV_GPIO_PAD_CONF (L"N07: GPIO_DFX2 ", Native , M5 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 2 , NA , 0x4438 , NORTH ) , // C0_BPM2_TX + CHV_GPIO_PAD_CONF (L"N01: GPIO_DFX3 ", Native , M5 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , Inv_TX_Enable , NA , 1 , NA , 0x4408 , NORTH ) , // C0_BPM3_TX + CHV_GPIO_PAD_CONF (L"N05: GPIO_DFX4 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 5 , NA , 0x4428 , NORTH ) , // + CHV_GPIO_PAD_CONF (L"N04: GPIO_DFX5 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 4 , NA , 0x4420 , NORTH ) , // + CHV_GPIO_PAD_CONF (L"N08: GPIO_DFX6 ", Native , M8 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 8 , NA , 0x4440 , NORTH ) , // + CHV_GPIO_PAD_CONF (L"N02: GPIO_DFX7 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 2 , NA , 0x4410 , NORTH ) , // +//CHV_GPIO_PAD_CONF (L"N06: GPIO_DFX8 ", GPIO , M1 , GPI , NA , NA , Trig_Level , Line0 , NA , NA , NA , NonMaskable , En_RX_Data , No_Inversion , NA , 6 , NA , 0x4430 , NORTH ) , // JACK DETECT? + CHV_GPIO_PAD_CONF (L"N15: GPIO_SUS0 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 9 , NA , 0x4800 , NORTH ) , // GPIO0_SUS0 + CHV_GPIO_PAD_CONF (L"N19: GPIO_SUS1 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 13 , NA , 0x4820 , NORTH ) , // GPIO_SUS1 + CHV_GPIO_PAD_CONF (L"N24: GPIO_SUS2 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 18 , NA , 0x4848 , NORTH ) , // NGFF_PWR_EN + CHV_GPIO_PAD_CONF (L"N17: GPIO_SUS3 ", GPIO , M1 , GPI , NA , NA , Trig_Level , Line1 , NA , NA , NA , NonMaskable , En_Edge_RX_Data , No_Inversion , NA , 11 , NA , 0x4810 , NORTH ) , // NGFF_SDIO_WAKE_N + CHV_GPIO_PAD_CONF (L"N22: GPIO_SUS4 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 16 , NA , 0x4838 , NORTH ) , // NGFF_KILL_BT_N + CHV_GPIO_PAD_CONF (L"N20: GPIO_SUS5 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 14 , NA , 0x4828 , NORTH ) , // NGFF_KILL_WIFI_N + CHV_GPIO_PAD_CONF (L"N71: HV_DDI0_DDC_SCL ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 57 , NA , 0x5458 , NORTH ) , // HDMI_SMB_SOC_SCL + CHV_GPIO_PAD_CONF (L"N66: HV_DDI0_DDC_SDA ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 52 , NA , 0x5430 , NORTH ) , // HDMI_SMB_SOC_SDA + CHV_GPIO_PAD_CONF (L"N61: HV_DDI0_HPD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , Inv_TX_Enable , NA , 47 , NA , 0x5408 , NORTH ) , // SOC_HDMI_HPD + CHV_GPIO_PAD_CONF (L"N64: HV_DDI1_HPD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , Inv_TX_Enable , NA , 50 , NA , 0x5420 , NORTH ) , // SOC_DP1_HPD + CHV_GPIO_PAD_CONF (L"N67: HV_DDI2_DDC_SCL ", Native , M3 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 53 , NA , 0x5438 , NORTH ) , // UART0_TXD (Default) || DDI1_DDC_SCL + CHV_GPIO_PAD_CONF (L"N62: HV_DDI2_DDC_SDA ", Native , M3 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 48 , NA , 0x5410 , NORTH ) , // UART0_RXD (Default) || DDI1_DDC_SCA + CHV_GPIO_PAD_CONF (L"N68: HV_DDI2_HPD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , Inv_TX_Enable , NA , 54 , NA , 0x5440 , NORTH ) , // SOC_DP2_HPD + CHV_GPIO_PAD_CONF (L"N65: PANEL0_BKLTCTL ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 51 , NA , 0x5428 , NORTH ) , // BRD_ID_BIT_0 + CHV_GPIO_PAD_CONF (L"N60: PANEL0_BKLTEN ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 46 , NA , 0x5400 , NORTH ) , // BRD_ID_BIT_1 + CHV_GPIO_PAD_CONF (L"N72: PANEL0_VDDEN ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 58 , NA , 0x5460 , NORTH ) , // BRD_ID_BIT_2 + CHV_GPIO_PAD_CONF (L"N63: PANEL1_BKLTCTL ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 49 , NA , 0x5418 , NORTH ) , // + CHV_GPIO_PAD_CONF (L"N70: PANEL1_BKLTEN ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 56 , NA , 0x5450 , NORTH ) , // + CHV_GPIO_PAD_CONF (L"N69: PANEL1_VDDEN ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 55 , NA , 0x5448 , NORTH ) , // + CHV_GPIO_PAD_CONF (L"N32: PROCHOT_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 24 , NA , 0x4C10 , NORTH ) , // VR_HOT_N + CHV_GPIO_PAD_CONF (L"N16: SEC_GPIO_SUS10 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 10 , NA , 0x4808 , NORTH ) , // GPIO_SUS10 + CHV_GPIO_PAD_CONF (L"N21: SEC_GPIO_SUS11 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 15 , NA , 0x4830 , NORTH ) , // GPIO_SUS11 + CHV_GPIO_PAD_CONF (L"N23: SEC_GPIO_SUS8 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 17 , NA , 0x4840 , NORTH ) , // GPIO_SUS8 +// CHV_GPIO_PAD_CONF (L"N38: SVID0_ALERT_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 30 , NA , 0x4C40 , NORTH ) , // SVID_ALERT_N +// CHV_GPIO_PAD_CONF (L"N40: SVID0_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 32 , NA , 0x4C50 , NORTH ) , // SVD_CLK +// CHV_GPIO_PAD_CONF (L"N33: SVID0_DATA ", Native , M0 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 25 , NA , 0x4C18 , NORTH ) , // SVID_DATA + CHV_GPIO_PAD_CONF (L"N31: TCK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 23 , NA , 0x4C08 , NORTH ) , // XDP_TCK + CHV_GPIO_PAD_CONF (L"N41: TDI ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 33 , NA , 0x4C58 , NORTH ) , // XDP_TDI + CHV_GPIO_PAD_CONF (L"N39: TDO ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 31 , NA , 0x4C48 , NORTH ) , // XDP_TDO + CHV_GPIO_PAD_CONF (L"N36: TDO_2 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 28 , NA , 0x4C30 , NORTH ) , // + CHV_GPIO_PAD_CONF (L"N34: TMS ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 26 , NA , 0x4C20 , NORTH ) , // XDP_TMS + CHV_GPIO_PAD_CONF (L"N30: TRST_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 22 , NA , 0x4C00 , NORTH ) , // XDP_TRST_N + + // + // East Community + // Group Pin#: PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks + // + CHV_GPIO_PAD_CONF (L"E21: MF_ISH_GPIO_0 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 18 , NA , 0x4830 , EAST ) , // FAB ID bit 0 + CHV_GPIO_PAD_CONF (L"E18: MF_ISH_GPIO_1 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 15 , NA , 0x4818 , EAST ) , // FAB ID bit 1 + CHV_GPIO_PAD_CONF (L"E24: MF_ISH_GPIO_2 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 21 , NA , 0x4848 , EAST ) , // FAB ID bit 2 + CHV_GPIO_PAD_CONF (L"E15: MF_ISH_GPIO_3 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 12 , NA , 0x4800 , EAST ) , // FAB ID bit 3 + CHV_GPIO_PAD_CONF (L"E22: MF_ISH_GPIO_4 ", GPIO , M1 , GPI , NA , NA , NA , Line0 , NA , NA , NA , NonMaskable , NA , No_Inversion , NA , 19 , NA , 0x4838 , EAST ) , // Not Used, Test points + CHV_GPIO_PAD_CONF (L"E19: MF_ISH_GPIO_5 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 16 , NA , 0x4820 , EAST ) , // Not Used, Test points + CHV_GPIO_PAD_CONF (L"E25: MF_ISH_GPIO_6 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 22 , NA , 0x4850 , EAST ) , // Not Used, Test points + CHV_GPIO_PAD_CONF (L"E16: MF_ISH_GPIO_7 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 13 , NA , 0x4808 , EAST ) , // Not Used, Test points + CHV_GPIO_PAD_CONF (L"E23: MF_ISH_GPIO_8 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 20 , NA , 0x4840 , EAST ) , // Not Used, Test points + CHV_GPIO_PAD_CONF (L"E20: MF_ISH_GPIO_9 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 17 , NA , 0x4828 , EAST ) , // Not Used, Test points + CHV_GPIO_PAD_CONF (L"E26: MF_ISH_I2C1_SDA ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 23 , NA , 0x4858 , EAST ) , // Not Used, Test points + CHV_GPIO_PAD_CONF (L"E17: MF_ISH_I2C1_SCL ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 14 , NA , 0x4810 , EAST ) , // Not Used, Test points + CHV_GPIO_PAD_CONF (L"E04: PMU_AC_PRESENT ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 4 , NA , 0x4420 , EAST ) , // PMU_AC_PRESENT + CHV_GPIO_PAD_CONF (L"E01: PMU_BATLOW_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 1 , NA , 0x4408 , EAST ) , // PMU_BATLOW_N + CHV_GPIO_PAD_CONF (L"E05: PMU_PLTRST_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 5 , NA , 0x4428 , EAST ) , // PLTRST_3P3_N +//CHV_GPIO_PAD_CONF (L"E08: PMU_PWRBTN_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 8 , NA , 0x4440 , EAST ) , // SOC_PWRBTN_N special programming below + CHV_GPIO_PAD_CONF (L"E07: PMU_SLP_LAN_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 7 , NA , 0x4438 , EAST ) , // Not Used, Available + CHV_GPIO_PAD_CONF (L"E03: PMU_SLP_S0IX_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 3 , NA , 0x4418 , EAST ) , // SLP_S01X_3P3_N + CHV_GPIO_PAD_CONF (L"E00: PMU_SLP_S3_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 0 , NA , 0x4400 , EAST ) , // SLP_S3_3P3_N + CHV_GPIO_PAD_CONF (L"E09: PMU_SLP_S4_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 9 , NA , 0x4448 , EAST ) , // SLP_S4_3P3_N + CHV_GPIO_PAD_CONF (L"E06: PMU_SUSCLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 6 , NA , 0x4430 , EAST ) , // SUSCLK_3P3 + CHV_GPIO_PAD_CONF (L"E10: PMU_WAKE_B ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , No_Inversion , NA , 10 , NA , 0x4450 , EAST ) , // PMU_3P3_WAKE_N + CHV_GPIO_PAD_CONF (L"E11: PMU_WAKE_LAN_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 11 , NA , 0x4458 , EAST ) , // Not Used, Available + CHV_GPIO_PAD_CONF (L"E02: SUS_STAT_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 2 , NA , 0x4410 , EAST ) , // SUS_STAT_N + + // + // South East Community + // Group Pin#: PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks + // + CHV_GPIO_PAD_CONF (L"SE16: SDMMC1_CLK ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_L , NA , NA , NA , NA , No_Inversion , NA , 9 , NA , 0x4808 , SOUTHEAST ) , // EMMC1_CLK + CHV_GPIO_PAD_CONF (L"SE23: SDMMC1_CMD ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 16 , NA , 0x4840 , SOUTHEAST ) , // EMMC1_CMD + CHV_GPIO_PAD_CONF (L"SE17: SDMMC1_D0 ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 10 , NA , 0x4810 , SOUTHEAST ) , // EMMC1_D_0 + CHV_GPIO_PAD_CONF (L"SE24: SDMMC1_D1 ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 17 , NA , 0x4848 , SOUTHEAST ) , // EMMC1_D_1 + CHV_GPIO_PAD_CONF (L"SE20: SDMMC1_D2 ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 13 , NA , 0x4828 , SOUTHEAST ) , // EMMC1_D_2 + CHV_GPIO_PAD_CONF (L"SE26: SDMMC1_D3_CD_B ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 19 , NA , 0x4858 , SOUTHEAST ) , // EMMC1_D_3 + CHV_GPIO_PAD_CONF (L"SE67: MMC1_D4_SD_WE ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 41 , NA , 0x5438 , SOUTHEAST ) , // EMMC1_D4 + CHV_GPIO_PAD_CONF (L"SE65: MMC1_D5 ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 39 , NA , 0x5428 , SOUTHEAST ) , // EMMC1_D5 + CHV_GPIO_PAD_CONF (L"SE63: MMC1_D6 ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 37 , NA , 0x5418 , SOUTHEAST ) , // EMMC1_D6 + CHV_GPIO_PAD_CONF (L"SE68: MMC1_D7 ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 42 , NA , 0x5440 , SOUTHEAST ) , // EMMC1_D7 + CHV_GPIO_PAD_CONF (L"SE69: MMC1_RCLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 43 , NA , 0x5448 , SOUTHEAST ) , // EMMC1_RCLK + CHV_GPIO_PAD_CONF (L"SE77: GPIO_ALERT ", GPIO , M1 , GPI , NA , NA , Trig_Level , Line2 , NA , NA , NA , NonMaskable , En_RX_Data , Inv_RX_Data , NA , 46 , NA , 0x5810 , SOUTHEAST ) , // DCN : 2502579 - Programmed for TCH_PAD_INT_N + CHV_GPIO_PAD_CONF (L"SE79: ILB_SERIRQ ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 48 , NA , 0x5820 , SOUTHEAST ) , // ILB_SERIRQ + CHV_GPIO_PAD_CONF (L"SE51: MF_LPC_CLKOUT0 ", Native , M1 , NA , NA , NA , NA , NA , P_NONE , NA , NA , NA , NA , No_Inversion , NA , 32 , NA , 0x5030 , SOUTHEAST ) , // L_CLKOUT0 + CHV_GPIO_PAD_CONF (L"SE49: MF_LPC_CLKOUT1 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 30 , NA , 0x5020 , SOUTHEAST ) , // L_CLKOUT1 + CHV_GPIO_PAD_CONF (L"SE47: MF_LPC_AD0 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 28 , NA , 0x5010 , SOUTHEAST ) , // LPC_AD0 + CHV_GPIO_PAD_CONF (L"SE52: MF_LPC_AD1 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 33 , NA , 0x5038 , SOUTHEAST ) , // LPC_AD1 + CHV_GPIO_PAD_CONF (L"SE45: MF_LPC_AD2 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 26 , NA , 0x5000 , SOUTHEAST ) , // LPC_AD2 + CHV_GPIO_PAD_CONF (L"SE50: MF_LPC_AD3 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 31 , NA , 0x5028 , SOUTHEAST ) , // LPC_AD3 + CHV_GPIO_PAD_CONF (L"SE46: LPC_CLKRUNB ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 27 , NA , 0x5008 , SOUTHEAST ) , // L_CLKRUN_N + CHV_GPIO_PAD_CONF (L"SE48: LPC_FRAMEB ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 29 , NA , 0x5018 , SOUTHEAST ) , // L_FRAME_N + CHV_GPIO_PAD_CONF (L"SE00: MF_PLT_CLK0 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 0 , NA , 0x4400 , SOUTHEAST ) , // CAM_1_MCLK Camera1_clock + CHV_GPIO_PAD_CONF (L"SE02: MF_PLT_CLK1 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 1 , NA , 0x4410 , SOUTHEAST ) , // CAM_2_MCLK Camera2_clock + CHV_GPIO_PAD_CONF (L"SE07: MF_PLT_CLK2 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 7 , NA , 0x4438 , SOUTHEAST ) , // Not Used + CHV_GPIO_PAD_CONF (L"SE04: MF_PLT_CLK3 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 4 , NA , 0x4420 , SOUTHEAST ) , // I2S_MCLK + CHV_GPIO_PAD_CONF (L"SE03: MF_PLT_CLK4 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 3 , NA , 0x4418 , SOUTHEAST ) , // Not Used + CHV_GPIO_PAD_CONF (L"SE06: MF_PLT_CLK5 ", GPIO , M3 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 6 , NA , 0x4430 , SOUTHEAST ) , // Not Used +//CHV_GPIO_PAD_CONF (L"SE76: PMU_RSTBUTTON_B", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 45 , NA , 0x5808 , SOUTHEAST ) , // SOC_RESETBTN_N special programming below + CHV_GPIO_PAD_CONF (L"SE83: SUSPWRDNACK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 52 , NA , 0x5840 , SOUTHEAST ) , // SUSPWRDNACK_3P3 + CHV_GPIO_PAD_CONF (L"SE05: PWM0 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 5 , NA , 0x4428 , SOUTHEAST ) , // + CHV_GPIO_PAD_CONF (L"SE01: PWM1 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 1 , NA , 0x4408 , SOUTHEAST ) , // WIFI_PCIE_RST_N + CHV_GPIO_PAD_CONF (L"SE85: SDMMC3_1P8_EN ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 54 , NA , 0x5850 , SOUTHEAST ) , // SD_CARD_PWR_EN + CHV_GPIO_PAD_CONF (L"SE81: SDMMC3_CD_B ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 50 , NA , 0x5830 , SOUTHEAST ) , // SD_CARD_DET_N + CHV_GPIO_PAD_CONF (L"SE31: SDMMC3_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 21 , NA , 0x4C08 , SOUTHEAST ) , // SD_CARD_CLK + CHV_GPIO_PAD_CONF (L"SE34: SDMMC3_CMD ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 24 , NA , 0x4C20 , SOUTHEAST ) , // SD_CARD_CMD + CHV_GPIO_PAD_CONF (L"SE35: SDMMC3_D0 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 25 , NA , 0x4C28 , SOUTHEAST ) , // SD_CARD_D0 + CHV_GPIO_PAD_CONF (L"SE30: SDMMC3_D1 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 20 , NA , 0x4C00 , SOUTHEAST ) , // SD_CARD_D1 + CHV_GPIO_PAD_CONF (L"SE33: SDMMC3_D2 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 23 , NA , 0x4C18 , SOUTHEAST ) , // SD_CARD_D2 + CHV_GPIO_PAD_CONF (L"SE32: SDMMC3_D3 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 22 , NA , 0x4C10 , SOUTHEAST ) , // SD_CARD_D3 + CHV_GPIO_PAD_CONF (L"SE78: SDMMC3_PWR_EN_B", Native , M1 , NA , NA , NA , NA , NA , P_20K_L , NA , NA , NA , NA , No_Inversion , NA , 47 , NA , 0x5818 , SOUTHEAST ) , // SD_CARD_PWRDN_N + CHV_GPIO_PAD_CONF (L"SE19: SDMMC2_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 12 , NA , 0x4820 , SOUTHEAST ) , // NGFF_SDEMMC2_CLK + CHV_GPIO_PAD_CONF (L"SE22: SDMMC2_CMD ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 15 , NA , 0x4838 , SOUTHEAST ) , // NGFF_SDEMMC2_CM + CHV_GPIO_PAD_CONF (L"SE25: SDMMC2_D0 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 18 , NA , 0x4850 , SOUTHEAST ) , // NGFF_SDEMMC2_D0 + CHV_GPIO_PAD_CONF (L"SE18: SDMMC2_D1 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 11 , NA , 0x4818 , SOUTHEAST ) , // NGFF_SDEMMC2_D1 + CHV_GPIO_PAD_CONF (L"SE21: SDMMC2_D2 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 14 , NA , 0x4830 , SOUTHEAST ) , // NGFF_SDEMMC2_D2 + CHV_GPIO_PAD_CONF (L"SE15: SDMMC2_D3_CD_B ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 8 , NA , 0x4800 , SOUTHEAST ) , // NGFF_SDEMMC2_D3 + CHV_GPIO_PAD_CONF (L"SE62: SPI1_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 36 , NA , 0x5410 , SOUTHEAST ) , // SPI1_CLK + CHV_GPIO_PAD_CONF (L"SE61: SPI1_CS0_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 35 , NA , 0x5408 , SOUTHEAST ) , // SPI1_CS0_N + CHV_GPIO_PAD_CONF (L"SE66: SPI1_CS1_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 40 , NA , 0x5430 , SOUTHEAST ) , // SPI1_CS1_N + CHV_GPIO_PAD_CONF (L"SE60: SPI1_MISO ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 34 , NA , 0x5400 , SOUTHEAST ) , // SPI1_MISO + CHV_GPIO_PAD_CONF (L"SE64: SPI1_MOSI ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 38 , NA , 0x5420 , SOUTHEAST ) , // SPI1_MOSI + CHV_GPIO_PAD_CONF (L"SE80: USB_OC0_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 49 , NA , 0x5828 , SOUTHEAST ) , // USB3_OC0_N + CHV_GPIO_PAD_CONF (L"SE75: USB_OC1_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 44 , NA , 0x5800 , SOUTHEAST ) , // USB3_OC1_N + // + // South west Community + // Group Pin#: PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks + // + CHV_GPIO_PAD_CONF (L"SW02: FST_SPI_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 2 , NA , 0x4410 , SOUTHWEST ) , // FAST_SPI_CLK + CHV_GPIO_PAD_CONF (L"SW06: FST_SPI_CS0_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 6 , NA , 0x4430 , SOUTHWEST ) , // FST_SPI_CS_N + CHV_GPIO_PAD_CONF (L"SW04: FST_SPI_CS1_B ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 4 , NA , 0x4420 , SOUTHWEST ) , // V3P3DX_TCH_EN + CHV_GPIO_PAD_CONF (L"SW07: FST_SPI_CS2_B ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 7 , NA , 0x4438 , SOUTHWEST ) , // FST_SPI_CS2_N (SPI TPM) + CHV_GPIO_PAD_CONF (L"SW01: FST_SPI_D0 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 1 , NA , 0x4408 , SOUTHWEST ) , // FST_SPI_D0 + CHV_GPIO_PAD_CONF (L"SW05: FST_SPI_D1 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 5 , NA , 0x4428 , SOUTHWEST ) , // FST_SPI_D1 + CHV_GPIO_PAD_CONF (L"SW00: FST_SPI_D2 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 0 , NA , 0x4400 , SOUTHWEST ) , // FST_SPI_D2 + CHV_GPIO_PAD_CONF (L"SW03: FST_SPI_D3 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 3 , NA , 0x4418 , SOUTHWEST ) , // FST_SPI_D3 + CHV_GPIO_PAD_CONF (L"SW30: MF_HDA_CLK ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 16 , NA , 0x4C00 , SOUTHWEST ) , // MF_HDA_CLK II GP_SSP_0_I2S_TXD + CHV_GPIO_PAD_CONF (L"SW37: MF_HDA_DOCKENB ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 23 , NA , 0x4C38 , SOUTHWEST ) , // NGFF_I2S_1_RXD_R_BT || I2S_2_RXD_R_AICO + CHV_GPIO_PAD_CONF (L"SW34: MF_HDA_DOCKRSTB", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 20 , NA , 0x4C20 , SOUTHWEST ) , // NGFF_I2S_1_TXD_R_BT || I2S_2_TXD_R_AICO + CHV_GPIO_PAD_CONF (L"SW31: MF_HDA_RSTB ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 17 , NA , 0x4C08 , SOUTHWEST ) , // AUD_LINK_RST_N + CHV_GPIO_PAD_CONF (L"SW32: MF_HDA_SDI0 ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 18 , NA , 0x4C10 , SOUTHWEST ) , // AUD_LINK_SDI0_SOC + CHV_GPIO_PAD_CONF (L"SW36: MF_HDA_SDI1 ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 22 , NA , 0x4C30 , SOUTHWEST ) , // AUD_LINK_SDI1_SOC + CHV_GPIO_PAD_CONF (L"SW33: MF_HDA_SDO ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 19 , NA , 0x4C18 , SOUTHWEST ) , // AUD_LINK_SDO + CHV_GPIO_PAD_CONF (L"SW35: MF_HDA_SYNC ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 21 , NA , 0x4C28 , SOUTHWEST ) , // AUD_LINK_SYNC + CHV_GPIO_PAD_CONF (L"SW18: UART1_CTS_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 11 , NA , 0x4818 , SOUTHWEST ) , // UART_BT_CTS + CHV_GPIO_PAD_CONF (L"SW15: UART1_RTS_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 8 , NA , 0x4800 , SOUTHWEST ) , // UART_BT_RTS + CHV_GPIO_PAD_CONF (L"SW16: UART1_RXD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 9 , NA , 0x4808 , SOUTHWEST ) , // UART_BT_RXD + CHV_GPIO_PAD_CONF (L"SW20: UART1_TXD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 13 , NA , 0x4828 , SOUTHWEST ) , // UART_BT_TXD + CHV_GPIO_PAD_CONF (L"SW22: UART2_CTS_B ", Native , M1 , NA , NA , NA , NA , NA , P_NONE , NA , NA , NA , NA , No_Inversion , NA , 15 , NA , 0x4838 , SOUTHWEST ) , // UART_GPS_CTS + CHV_GPIO_PAD_CONF (L"SW19: UART2_RTS_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 12 , NA , 0x4820 , SOUTHWEST ) , // UART_GPS_RTS + CHV_GPIO_PAD_CONF (L"SW17: UART2_RXD ", Native , M1 , NA , NA , NA , NA , NA , P_NONE , NA , NA , NA , NA , No_Inversion , NA , 10 , NA , 0x4810 , SOUTHWEST ) , // UART_GPS_RXD + CHV_GPIO_PAD_CONF (L"SW21: UART2_TXD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 14 , NA , 0x4830 , SOUTHWEST ) , // UART_GPS_TXD + CHV_GPIO_PAD_CONF (L"SW65: I2C0_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 37 , NA , 0x5428 , SOUTHWEST ) , // I2C_3P3_NGFF_SDA + CHV_GPIO_PAD_CONF (L"SW61: I2C0_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 33 , NA , 0x5408 , SOUTHWEST ) , // I2C_3P3_NGFF_SCL + CHV_GPIO_PAD_CONF (L"SW63: I2C1_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 35 , NA , 0x5418 , SOUTHWEST ) , // I2C1_SDA_AUD_CONN + CHV_GPIO_PAD_CONF (L"SW60: I2C1_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 32 , NA , 0x5400 , SOUTHWEST ) , // I2C1_SCL_AUD_CONN + CHV_GPIO_PAD_CONF (L"SW66: I2C2_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 38 , NA , 0x5430 , SOUTHWEST ) , // I2C2_SDA_CAM + CHV_GPIO_PAD_CONF (L"SW62: I2C2_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 34 , NA , 0x5410 , SOUTHWEST ) , // I2C2_SCL_CAM + CHV_GPIO_PAD_CONF (L"SW67: I2C3_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 39 , NA , 0x5438 , SOUTHWEST ) , // I2C3_CAM_SDA + CHV_GPIO_PAD_CONF (L"SW64: I2C3_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 36 , NA , 0x5420 , SOUTHWEST ) , // I2C3_CAM_SCL + CHV_GPIO_PAD_CONF (L"SW50: I2C4_SCL ", Native , M3 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 29 , NA , 0x5028 , SOUTHWEST ) , // HV_DDI2_DDC_SCL + CHV_GPIO_PAD_CONF (L"SW46: I2C4_SDA ", Native , M3 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 25 , NA , 0x5008 , SOUTHWEST ) , // HV_DDI2_DDC_SDA + CHV_GPIO_PAD_CONF (L"SW48: I2C5_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 27 , NA , 0x5018 , SOUTHWEST ) , // I2C5_SDA_3P3 + CHV_GPIO_PAD_CONF (L"SW45: I2C5_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 24 , NA , 0x5000 , SOUTHWEST ) , // I2C5_SDA_3P3 + CHV_GPIO_PAD_CONF (L"SW51: I2C6_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 30 , NA , 0x5030 , SOUTHWEST ) , // + CHV_GPIO_PAD_CONF (L"SW47: I2C6_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 26 , NA , 0x5010 , SOUTHWEST ) , // + CHV_GPIO_PAD_CONF (L"SW49: I2C_NFC_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 28 , NA , 0x5020 , SOUTHWEST ) , // I2C_NFC_SDA_3P3 + CHV_GPIO_PAD_CONF (L"SW52: I2C_NFC_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 31 , NA , 0x5038 , SOUTHWEST ) , // I2C_NFC_SCL_3P3 + CHV_GPIO_PAD_CONF (L"SW77: GP_SSP_2_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 50 , NA , 0x5C10 , SOUTHWEST ) , // I2S_2_CLK + CHV_GPIO_PAD_CONF (L"SW81: GP_SSP_2_FS ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 54 , NA , 0x5C30 , SOUTHWEST ) , // I2S_2_FS + CHV_GPIO_PAD_CONF (L"SW79: GP_SSP_2_RXD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 52 , NA , 0x5C20 , SOUTHWEST ) , // I2S_2_RXD + CHV_GPIO_PAD_CONF (L"SW82: GP_SSP_2_TXD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , Inv_TX_Enable , NA , 55 , NA , 0x5C38 , SOUTHWEST ) , // I2S_2_TXD + CHV_GPIO_PAD_CONF (L"SW90: PCIE_CLKREQ0B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 48 , NA , 0x5C00 , SOUTHWEST ) , // + CHV_GPIO_PAD_CONF (L"SW91: PCIE_CLKREQ1B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 49 , NA , 0x5C08 , SOUTHWEST ) , // PCIE_CLKREQ1_N + CHV_GPIO_PAD_CONF (L"SW93: PCIE_CLKREQ2B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 51 , NA , 0x5C18 , SOUTHWEST ) , // PCIE_CLKREQ2_N + CHV_GPIO_PAD_CONF (L"SW95: PCIE_CLKREQ3B ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 53 , NA , 0x5C28 , SOUTHWEST ) , // SDMMC3_WP (Def) +//CHV_GPIO_PAD_CONF (L"SW95: PCIE_CLKREQ3B ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 53 , NA , 0x5C28 , SOUTHWEST ) , // GPI_SOC_HOMESCRN + CHV_GPIO_PAD_CONF (L"SW75: SATA_GP0 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 40 , NA , 0x5800 , SOUTHWEST ) , // reserved for SATA (Interlock switch) + CHV_GPIO_PAD_CONF (L"SW76: SATA_GP1 ", GPIO , M1 , GPI , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 41 , NA , 0x5808 , SOUTHWEST ) , // GPI to select UART0 | DDI1 mode + CHV_GPIO_PAD_CONF (L"SW78: SATA_GP2 ", Native , M1 , NA , NA , NA , NA , NA , NA , _ENABLE , NA , NA , NA , No_Inversion , NA , 43 , NA , 0x5818 , SOUTHWEST ) , // SATA_DEVSLP0 -need to check + CHV_GPIO_PAD_CONF (L"SW80: SATA_GP3 ", GPIO , M2 , GPI , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 45 , NA , 0x5828 , SOUTHWEST ) , // TOUCH_RST_N -need to check + CHV_GPIO_PAD_CONF (L"SW77: SATA_LEDN ", Native , M1 , NA , NA , NA , NA , NA , NA , _ENABLE , NA , NA , NA , No_Inversion , NA , 42 , NA , 0x5810 , SOUTHWEST ) , // SATA_LED_N + CHV_GPIO_PAD_CONF (L"SW79: MF_SMB_ALERTB ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 44 , NA , 0x5820 , SOUTHWEST ) , // SMB_ALERTB_3P3 + CHV_GPIO_PAD_CONF (L"SW81: MF_SMB_CLK ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 46 , NA , 0x5830 , SOUTHWEST ) , // SMB_3P3_CLK + CHV_GPIO_PAD_CONF (L"SW82: MF_SMB_DATA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 47 , NA , 0x5838 , SOUTHWEST ) , // SMB_3P3_DAT +}; + +// Braswell Cherry Hill platform + +/// Community Configuration +/// Family Configuration +/* +* GPIO Families configuration in CherryView +* +*/ + +GPIO_SAI_INIT mBSW_WD_GPIO_SAI_Init_East[] = +{ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_access_reg ", 0x0 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_wake_reg ", 0x4 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_interrupt_reg ", 0x8 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_community_reg ", 0xC , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_broadcast_reg ", 0x10 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_reg ", 0x14 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_pad_broadcast_reg ", 0x18 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_4x2_12_0_regs ", 0x1C , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_4x2_12_1_regs ", 0x20 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_access_reg ", 0x100, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_wake_reg ", 0x104, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_interrupt_reg ", 0x108, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_community_reg ", 0x10C, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_broadcast_reg ", 0x110, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_reg ", 0x114, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_pad_broadcast_reg ", 0x118, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_4x2_12_0_regs ", 0x11c, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_4x2_12_1_regs ", 0x120, 0x18310, ENABLE), +}; + +GPIO_SAI_INIT mBSW_WD_GPIO_SAI_Init_North[] = +{ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_access_reg ", 0x0 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_wake_reg ", 0x4 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_interrupt_reg ", 0x8 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_community_reg ", 0xC , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_broadcast_reg ", 0x10 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_reg ", 0x14 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_pad_broadcast_reg ", 0x18 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_2x4_rcomp_10_0_regs ", 0x1C , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x4_13_0_regs ", 0x20 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_3x4_12_0_regs ", 0x24 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_2x4_12_0_regs ", 0x28 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_3x4_13_0_regs ", 0x2C , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_access_reg ", 0x100, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_wake_reg ", 0x104, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_interrupt_reg ", 0x108, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_community_reg ", 0x10C, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_broadcast_reg ", 0x110, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_reg ", 0x114, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_pad_broadcast_reg ", 0x118, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_2x4_rcomp_10_0_regs ", 0x11C, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x4_13_0_regs ", 0x120, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_3x4_12_0_regs ", 0x124, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_2x4_12_0_regs ", 0x128, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_3x4_13_0_regs ", 0x12C, 0x18310, ENABLE), +}; + +GPIO_SAI_INIT mBSW_WD_GPIO_SAI_Init_SouthEast[] = +{ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_access_reg ", 0x0 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_wake_reg ", 0x4 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_interrupt_reg ", 0x8 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_community_reg ", 0xC , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_broadcast_reg ", 0x10 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_reg ", 0x14 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_pad_broadcast_reg ", 0x18 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_2_regs ", 0x1C , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_3x3_rcomp_13_0_regs ", 0x20 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_hshvfamily_2x3_rcomp_7_0_regs ", 0x24 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_hshvfamily_3x3_rcomp_9_0_regs ", 0x28 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_3x3_10_0_regs ", 0x2C , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_3x3_11_0_regs ", 0x30 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_access_reg ", 0x100, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_wake_reg ", 0x104, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_interrupt_reg ", 0x108, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_community_reg ", 0x10C, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_broadcast_reg ", 0x110, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_reg ", 0x114, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_pad_broadcast_reg ", 0x118, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_2_regs ", 0x11C, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_3x3_rcomp_13_0_regs ", 0x120, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_hshvfamily_2x3_rcomp_7_0_regs ", 0x124, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_hshvfamily_3x3_rcomp_9_0_regs ", 0x128, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_3x3_10_0_regs ", 0x12C, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_3x3_11_0_regs ", 0x130, 0x18310, ENABLE), +}; + +GPIO_SAI_INIT mBSW_WD_GPIO_SAI_Init_SouthWest[] = +{ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_access_reg ",0x0 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_wake_reg ",0x4 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_interrupt_reg ",0x8 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_community_reg ",0xC , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_broadcast_reg ",0x10 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_reg ",0x14 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_pad_broadcast_reg ",0x18 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_2x3_8_1_regs ",0x1C , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_6_regs ",0x20 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_5_regs ",0x24 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_4_regs ",0x28 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_3_regs ",0x2C , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_1_regs ",0x30 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_0_regs ",0x34 , 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_access_reg ",0x100, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_wake_reg ",0x104, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_interrupt_reg ",0x108, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_community_reg ",0x10C, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_broadcast_reg ",0x110, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_reg ",0x114, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_pad_broadcast_reg ",0x118, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_2x3_8_1_regs ",0x11C, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_6_regs ",0x120, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_5_regs ",0x124, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_4_regs ",0x128, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_3_regs ",0x12C, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_1_regs ",0x130, 0x18310, ENABLE), + CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_0_regs ",0x134, 0x18310, ENABLE), +}; + + +CHV_GPIO_PAD_INIT mBSW_WD_GpioInitData_SetupBasedConfig[] = +// Group Pin#: PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks +{ + CHV_GPIO_PAD_CONF (L"N53: GP_CAMERASB01 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5040 , NORTH ) , // FLASH_RESET_N +//CHV_GPIO_PAD_CONF (L"N53: GP_CAMERASB01 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5040 , NORTH ) , // IMAGING_DFU : USB3 CAM +//CHV_GPIO_PAD_CONF (L"N53: GP_CAMERASB01 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5040 , NORTH ) , // IMAGING_DFU : MIPI CAM +}; + +CHV_GPIO_PAD_INIT mBSW_WD_GpioInitData_N[] = +// PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks +{ + CHV_GPIO_PAD_CONF (L"N25: GPIO_SUS6 ", GPIO , M1 , GPI , NA , NA , Trig_Edge_Low , Line9 , NA , NA , NA , NonMaskable , En_Edge_RX_Data , No_Inversion , NA , 19 , SCI , 0x4850 , NORTH ) , // XDP_HLT_BOOT + CHV_GPIO_PAD_CONF (L"N18: GPIO_SUS7 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 12 , SMI , 0x4818 , NORTH ) , // + CHV_GPIO_PAD_CONF (L"N23: SEC_GPIO_SUS8 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 17 , NA , 0x4840 , NORTH ) , // + CHV_GPIO_PAD_CONF (L"N27: SEC_GPIO_SUS9 ", GPIO , M1 , GPI , LOW , NA , Trig_Level , Line15 , NA , NA , NA , NonMaskable , En_RX_Data , Inv_RX_Data , NA , 21 , SCI , 0x4860 , NORTH ) , // GPIO_THERM_ALERT_N +}; + +VOID +BraswellWesternDigitalGpioInit ( + VOID + ) +{ + CHV_GPIO_PAD_INIT GpioInitTable[3]; + + DEBUG ((EFI_D_ERROR, "Programming BSW CR Board Gpio Tables which are not done properly by FSP...\n")); + + // + // Copy the default settings for first three external gpios + // + CopyMem (GpioInitTable, mBSW_WD_GpioInitData_N, (sizeof(CHV_GPIO_PAD_INIT) * 3 )); + + // + // Update the gpio setting with the values from patchable pcds + // + // Update GPIO_SUS6 + GpioInitTable[0].padConfg0.padCnf0 = (UINT32)(PcdGet64 (PcdGPIOSUS6Configuration) & 0xFCFF8782); + GpioInitTable[0].padConfg1.padCnf1 &= 0xFFFFFF00; + GpioInitTable[0].padConfg1.padCnf1 |= (UINT32) (RShiftU64(PcdGet64 (PcdGPIOSUS6Configuration), 32) & 0xFF); + GpioInitTable[0].PAD_MISC.r.GPE_ENABLE = (UINT32) (RShiftU64(PcdGet64 (PcdGPIOSUS6Configuration),40) & 0x03); + GpioInitTable[0].PAD_MISC.r.wake_able = (PcdGet64 (PcdGPIOSUS6Configuration) & BIT42) ? 1:0; + GpioInitTable[0].PAD_MISC.r.intr_mask = (PcdGet64 (PcdGPIOSUS6Configuration) & BIT43) ? 1:0; + GpioInitTable[0].PAD_MISC.r.Wake_Mask_Position = (UINT32) (RShiftU64(PcdGet64 (PcdGPIOSUS6Configuration), 44) & 0xFF); + + // Update GPIO_SUS7 + GpioInitTable[1].padConfg0.padCnf0 = (UINT32)(PcdGet64 (PcdGPIOSUS7Configuration) & 0xFCFF8782); + GpioInitTable[1].padConfg1.padCnf1 &= 0xFFFFFF00; + GpioInitTable[1].padConfg1.padCnf1 |= (UINT32) (RShiftU64(PcdGet64 (PcdGPIOSUS7Configuration), 32) & 0xFF); + GpioInitTable[1].PAD_MISC.r.GPE_ENABLE = (UINT32) (RShiftU64(PcdGet64 (PcdGPIOSUS7Configuration), 40) & 0x03); + GpioInitTable[1].PAD_MISC.r.wake_able = (PcdGet64 (PcdGPIOSUS7Configuration) & BIT42) ? 1:0; + GpioInitTable[1].PAD_MISC.r.intr_mask = (PcdGet64 (PcdGPIOSUS7Configuration) & BIT43) ? 1:0; + GpioInitTable[1].PAD_MISC.r.Wake_Mask_Position = (UINT32) (RShiftU64(PcdGet64 (PcdGPIOSUS7Configuration), 44) & 0xFF); + + // Update GPIO_SUS8 + GpioInitTable[2].padConfg0.padCnf0 = (UINT32)(PcdGet64 (PcdGPIOSUS8Configuration) & 0xFCFF8782); + GpioInitTable[2].padConfg1.padCnf1 &= 0xFFFFFF00; + GpioInitTable[2].padConfg1.padCnf1 |= (UINT32) (RShiftU64(PcdGet64 (PcdGPIOSUS8Configuration), 32) & 0xFF); + GpioInitTable[2].PAD_MISC.r.GPE_ENABLE = (UINT32) (RShiftU64(PcdGet64 (PcdGPIOSUS8Configuration), 40) & 0x03); + GpioInitTable[2].PAD_MISC.r.wake_able = (PcdGet64 (PcdGPIOSUS8Configuration) & BIT42) ? 1:0; + GpioInitTable[2].PAD_MISC.r.intr_mask = (PcdGet64 (PcdGPIOSUS8Configuration) & BIT43) ? 1:0; + GpioInitTable[2].PAD_MISC.r.Wake_Mask_Position = (UINT32) (RShiftU64(PcdGet64 (PcdGPIOSUS8Configuration), 44) & 0xFF); + + // PAD programming to initialize GPIOs with SCI/SMI support, which depends on FSP PchInit to program basic chipset resources. + InternalGpioPADConfig(3, (sizeof(mBSW_WD_GpioInitData_N)/sizeof(mBSW_WD_GpioInitData_N[0]) - 3), mBSW_WD_GpioInitData_N); + + // Initialize the three gpios at the gpio header + InternalGpioPADConfig(0, sizeof(GpioInitTable)/sizeof(GpioInitTable[0]), GpioInitTable); + + // GPIO lock if really want + SAI_SettingOfGpioFamilies(mBSW_WD_GPIO_SAI_Init_East, sizeof(mBSW_WD_GPIO_SAI_Init_East)/sizeof(mBSW_WD_GPIO_SAI_Init_East[0])); + SAI_SettingOfGpioFamilies(mBSW_WD_GPIO_SAI_Init_North, sizeof(mBSW_WD_GPIO_SAI_Init_North)/sizeof(mBSW_WD_GPIO_SAI_Init_North[0])); + SAI_SettingOfGpioFamilies(mBSW_WD_GPIO_SAI_Init_SouthEast, sizeof(mBSW_WD_GPIO_SAI_Init_SouthEast)/sizeof(mBSW_WD_GPIO_SAI_Init_SouthEast[0])); + SAI_SettingOfGpioFamilies(mBSW_WD_GPIO_SAI_Init_SouthWest, sizeof(mBSW_WD_GPIO_SAI_Init_SouthWest)/sizeof(mBSW_WD_GPIO_SAI_Init_SouthWest[0])); +} + +VOID +WesternDigitalBoardGpioConfigure ( + VOID + ) +{ + InternalGpioPADConfig(0, sizeof(mBswWesternDigitalGpioInitData)/sizeof(mBswWesternDigitalGpioInitData[0]), mBswWesternDigitalGpioInitData); +} + diff --git a/BraswellPlatformPkg/Board/WesternDigital/BoardInit/BoardGpios.h b/BraswellPlatformPkg/Board/WesternDigital/BoardInit/BoardGpios.h index 4f7a46869b..0a059888c6 100644 --- a/BraswellPlatformPkg/Board/WesternDigital/BoardInit/BoardGpios.h +++ b/BraswellPlatformPkg/Board/WesternDigital/BoardInit/BoardGpios.h @@ -65,139 +65,16 @@ #define ENABLE 1 #define DISABLE 0 -// Braswell Cherry Hill platform - -/// Community Configuration -/// Family Configuration -/* -* GPIO Families configuration in CherryView -* -*/ - -GPIO_SAI_INIT mBSW_WD_GPIO_SAI_Init_East[] = -{ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_access_reg ", 0x0 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_wake_reg ", 0x4 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_interrupt_reg ", 0x8 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_community_reg ", 0xC , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_broadcast_reg ", 0x10 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_reg ", 0x14 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_pad_broadcast_reg ", 0x18 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_4x2_12_0_regs ", 0x1C , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_4x2_12_1_regs ", 0x20 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_access_reg ", 0x100, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_wake_reg ", 0x104, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_interrupt_reg ", 0x108, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_community_reg ", 0x10C, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_broadcast_reg ", 0x110, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_reg ", 0x114, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_pad_broadcast_reg ", 0x118, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_4x2_12_0_regs ", 0x11c, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_4x2_12_1_regs ", 0x120, 0x18310, ENABLE), -}; - -GPIO_SAI_INIT mBSW_WD_GPIO_SAI_Init_North[] = -{ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_access_reg ", 0x0 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_wake_reg ", 0x4 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_interrupt_reg ", 0x8 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_community_reg ", 0xC , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_broadcast_reg ", 0x10 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_reg ", 0x14 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_pad_broadcast_reg ", 0x18 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_2x4_rcomp_10_0_regs ", 0x1C , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x4_13_0_regs ", 0x20 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_3x4_12_0_regs ", 0x24 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_2x4_12_0_regs ", 0x28 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_3x4_13_0_regs ", 0x2C , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_access_reg ", 0x100, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_wake_reg ", 0x104, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_interrupt_reg ", 0x108, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_community_reg ", 0x10C, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_broadcast_reg ", 0x110, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_reg ", 0x114, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_pad_broadcast_reg ", 0x118, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_2x4_rcomp_10_0_regs ", 0x11C, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x4_13_0_regs ", 0x120, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_3x4_12_0_regs ", 0x124, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_2x4_12_0_regs ", 0x128, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_3x4_13_0_regs ", 0x12C, 0x18310, ENABLE), -}; - -GPIO_SAI_INIT mBSW_WD_GPIO_SAI_Init_SouthEast[] = -{ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_access_reg ", 0x0 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_wake_reg ", 0x4 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_interrupt_reg ", 0x8 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_community_reg ", 0xC , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_broadcast_reg ", 0x10 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_reg ", 0x14 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_pad_broadcast_reg ", 0x18 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_2_regs ", 0x1C , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_3x3_rcomp_13_0_regs ", 0x20 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_hshvfamily_2x3_rcomp_7_0_regs ", 0x24 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_hshvfamily_3x3_rcomp_9_0_regs ", 0x28 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_3x3_10_0_regs ", 0x2C , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_3x3_11_0_regs ", 0x30 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_access_reg ", 0x100, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_wake_reg ", 0x104, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_interrupt_reg ", 0x108, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_community_reg ", 0x10C, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_broadcast_reg ", 0x110, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_reg ", 0x114, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_pad_broadcast_reg ", 0x118, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_2_regs ", 0x11C, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_3x3_rcomp_13_0_regs ", 0x120, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_hshvfamily_2x3_rcomp_7_0_regs ", 0x124, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_hshvfamily_3x3_rcomp_9_0_regs ", 0x128, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_3x3_10_0_regs ", 0x12C, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_3x3_11_0_regs ", 0x130, 0x18310, ENABLE), -}; - -GPIO_SAI_INIT mBSW_WD_GPIO_SAI_Init_SouthWest[] = -{ CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_access_reg ",0x0 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_wake_reg ",0x4 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_interrupt_reg ",0x8 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_community_reg ",0xC , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_broadcast_reg ",0x10 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_family_reg ",0x14 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_pad_broadcast_reg ",0x18 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulphsmvfamily_2x3_8_1_regs ",0x1C , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_6_regs ",0x20 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_5_regs ",0x24 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_4_regs ",0x28 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_3_regs ",0x2C , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_1_regs ",0x30 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_read_access_policy_ulpmsmvfamily_2x3_8_0_regs ",0x34 , 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_access_reg ",0x100, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_wake_reg ",0x104, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_interrupt_reg ",0x108, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_community_reg ",0x10C, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_broadcast_reg ",0x110, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_family_reg ",0x114, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_pad_broadcast_reg ",0x118, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulphsmvfamily_2x3_8_1_regs ",0x11C, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_6_regs ",0x120, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_5_regs ",0x124, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_4_regs ",0x128, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_3_regs ",0x12C, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_1_regs ",0x130, 0x18310, ENABLE), - CHV_GPIO_SAI_INIT(L"gpio_write_access_policy_ulpmsmvfamily_2x3_8_0_regs ",0x134, 0x18310, ENABLE), -}; - - -CHV_GPIO_PAD_INIT mBSW_WD_GpioInitData_SetupBasedConfig[] = -// Group Pin#: PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks -{ - CHV_GPIO_PAD_CONF (L"N53: GP_CAMERASB01 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5040 , NORTH ) , // FLASH_RESET_N -//CHV_GPIO_PAD_CONF (L"N53: GP_CAMERASB01 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5040 , NORTH ) , // IMAGING_DFU : USB3 CAM -//CHV_GPIO_PAD_CONF (L"N53: GP_CAMERASB01 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , 0x5040 , NORTH ) , // IMAGING_DFU : MIPI CAM -}; - -CHV_GPIO_PAD_INIT mBSW_WD_GpioInitData_N[] = -// PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks -{ - CHV_GPIO_PAD_CONF (L"N25: GPIO_SUS6 ", GPIO , M1 , GPI , NA , NA , Trig_Edge_Low , Line9 , NA , NA , NA , NonMaskable , En_Edge_RX_Data , No_Inversion , NA , 19 , SCI , 0x4850 , NORTH ) , // XDP_HLT_BOOT - CHV_GPIO_PAD_CONF (L"N18: GPIO_SUS7 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 12 , SMI , 0x4818 , NORTH ) , // - CHV_GPIO_PAD_CONF (L"N23: SEC_GPIO_SUS8 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 17 , NA , 0x4840 , NORTH ) , // - CHV_GPIO_PAD_CONF (L"N27: SEC_GPIO_SUS9 ", GPIO , M1 , GPI , LOW , NA , Trig_Level , Line15 , NA , NA , NA , NonMaskable , En_RX_Data , Inv_RX_Data , NA , 21 , SCI , 0x4860 , NORTH ) , // GPIO_THERM_ALERT_N -}; +VOID +SAI_SettingOfGpioFamilies ( + GPIO_SAI_INIT* SAI_Conf_Data, + UINT32 familySize + ); + +VOID +WesternDigitalBoardGpioConfigure ( + VOID + ); #endif + diff --git a/BraswellPlatformPkg/Board/WesternDigital/BoardInit/BoardInit.c b/BraswellPlatformPkg/Board/WesternDigital/BoardInit/BoardInit.c index 54f5bab96f..212416505f 100644 --- a/BraswellPlatformPkg/Board/WesternDigital/BoardInit/BoardInit.c +++ b/BraswellPlatformPkg/Board/WesternDigital/BoardInit/BoardInit.c @@ -24,297 +24,9 @@ #include #include #include - -// Input_Struct.tCL = 11; //< actual CL / -// Input_Struct.tRP_tRCD = 11; //< TRP and tRCD in dram clk/ -// Input_Struct.tWR = 12;// MIN =15ns //< in dram clk / -// Input_Struct.tWTR = 6;// MIN = greater of 4CK or 7.5ns //< in dram clk / -// Input_Struct.tRRD = 6;// MIN = greater of 4CK or 7.5ns //< in dram clk / -// Input_Struct.tRTP = 6;// MIN = greater of 4CK or 7.5ns; //< in dram clk / -// Input_Struct.tFAW = 32; -// -// TBD: Need update to CH version -// -UINT8 mWD_CR_SpdDataMemorySolderDown[] = { - 0x92, // Byte 0 - 0x12, // Byte 1 - 0x0b, // Byte 2 (Key Byte / DRAM Device Type) DDR3 SDRAM - 0x03, // Byte 3 (Key Byte / Module Type) SO-DIMM - 0x05, // Byte 4 (8Banks, 8Gb) - 0x23, // Byte 5 (SDRAM Addressing) 00 100 011 = 0x23 - 0x02, // Byte 6 - 0x02, // Byte 7: Module Organization Bit [5, 4, 3] : 000 = 1 Rank Bit [2, 1, 0] :010 = SDRAM Device Width 16 bits - 0x03, // Byte 8: Module Memory Bus Width Bit [2, 1, 0] : 011 = 64 bits - 0x52, // Byte 9: Fine Timebase (FTB) Dividend / Divisor - 0x01, // Byte 10: Medium Timebase (MTB) Dividend - 0x08, // Byte 11: Medium Timebase (MTB) Divisor - 0x0a, // Byte 12: SDRAM Minimum Cycle Time (tCKmin) - 0x00, // Byte 13: Reserved - 0xfe, // Byte 14: CAS Latencies Supported, Least Significant Byte (tCL) - 0x00, // Byte 15: CAS Latencies Supported, Most Significant Byte - 0x69, // Byte 16: Minimum CAS Latency Time (tAAmin) - 0x78, // Byte 17: Minimum Write Recovery Time (tWRmin) - 0x69, // Byte 18: Minimum RAS# to CAS# Delay Time (tRCDmin) - 0x3c, // Byte 19: Minimum Row Active to Row Active Delay Time (tRRDmin) - 0x69, // Byte 20: Minimum Row Precharge Delay Time (tRPmin) - 0x11, // Byte 21: Upper Nibbles for tRAS and tRC - 0x18, // Byte 22: Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte = 34 - 0x81, // Byte 23: Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte - 0x00, // Byte 24: Minimum Refresh Recovery Delay Time (tRFCmin), Least Significant Byte - 0x05, // Byte 25: Minimum Refresh Recovery Delay Time (tRFCmin), Most Significant Byte - 0x3c, // Byte 26: Minimum Internal Write to Read Command Delay Time (tWTRmin) - 0x3c, // Byte 27: Minimum Internal Read to Precharge Command Delay Time (tRTPmin) - 0x01, // Byte 28: Upper Nibble for tFAW - 0x40, // Byte 29: Minimum Four Activate Window Delay Time (tFAWmin), Least Significant Byte - 0x83, // Byte 30: SDRAM Optional Features - 0x01, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, //Byte40 - 0,0,0,0,0,0,0,0, - 0x00, - 0x00, - 0x00, - 0x00, - 0x0f, // Byte 60: - 0x11, - 0x22, - 0x00, - 0,0,0,0,0,0,0,0, //Byte64 - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0x00, //Byte112 - 0x00, - 0x00, - 0x00, - 0x00, - 0x80, - 0xad, - 0x01, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00 //Byte 215 -}; - - -// -// TBD: Need update to CH version -// -CHV_GPIO_PAD_INIT mBswWesternDigitalGpioInitData[] = -{ - // - // North Community - // Group Pin#: PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks - CHV_GPIO_PAD_CONF (L"N37: CX_PRDY_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 29 , NA , 0x4C38 , NORTH ) , // PRDY_B - CHV_GPIO_PAD_CONF (L"N35: CX_PRDY_B_2 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 27 , NA , 0x4C28 , NORTH ) , // CX_PRDY_B_2 - CHV_GPIO_PAD_CONF (L"N39: CX_PREQ_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 20 , NA , 0x4858 , NORTH ) , // PREQ_B - CHV_GPIO_PAD_CONF (L"N48: GP_CAMERASB00 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 37 , NA , 0x5018 , NORTH ) , // CAM_ACT_LED - CHV_GPIO_PAD_CONF (L"N53: GP_CAMERASB01 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 42 , NA , 0x5040 , NORTH ) , // FLASH_RESET_N - CHV_GPIO_PAD_CONF (L"N46: GP_CAMERASB02 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 35 , NA , 0x5008 , NORTH ) , // GPIO_FLHD_N - CHV_GPIO_PAD_CONF (L"N51: GP_CAMERASB03 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 40 , NA , 0x5030 , NORTH ) , // XDP_GP_CAMERASB03 - CHV_GPIO_PAD_CONF (L"N56: GP_CAMERASB04 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 45 , NA , 0x5058 , NORTH ) , // FLASH_TRIG - CHV_GPIO_PAD_CONF (L"N45: GP_CAMERASB05 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 34 , NA , 0x5000 , NORTH ) , // FLASH_TORCH - CHV_GPIO_PAD_CONF (L"N49: GP_CAMERASB06 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 38 , NA , 0x5020 , NORTH ) , // CAM1_PWRDWN - CHV_GPIO_PAD_CONF (L"N54: GP_CAMERASB07 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 43 , NA , 0x5048 , NORTH ) , // CAM2_PWRDWN - CHV_GPIO_PAD_CONF (L"N47: GP_CAMERASB08 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 36 , NA , 0x5010 , NORTH ) , // XDP_GP_CAMERASB08 - CHV_GPIO_PAD_CONF (L"N52: GP_CAMERASB09 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 41 , NA , 0x5038 , NORTH ) , // CAM_1_RST_N - CHV_GPIO_PAD_CONF (L"N50: GP_CAMERASB10 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 39 , NA , 0x5028 , NORTH ) , // CAM_2_RST_N - CHV_GPIO_PAD_CONF (L"N55: GP_CAMERASB11 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 44 , NA , 0x5050 , NORTH ) , // CAM_3_RST_N - CHV_GPIO_PAD_CONF (L"N00: GPIO_DFX0 ", Native , M5 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 0 , NA , 0x4400 , NORTH ) , // C0_BPM0_TX - CHV_GPIO_PAD_CONF (L"N03: GPIO_DFX1 ", Native , M5 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 3 , NA , 0x4418 , NORTH ) , // C0_BPM1_TX - CHV_GPIO_PAD_CONF (L"N07: GPIO_DFX2 ", Native , M5 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 2 , NA , 0x4438 , NORTH ) , // C0_BPM2_TX - CHV_GPIO_PAD_CONF (L"N01: GPIO_DFX3 ", Native , M5 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , Inv_TX_Enable , NA , 1 , NA , 0x4408 , NORTH ) , // C0_BPM3_TX - CHV_GPIO_PAD_CONF (L"N05: GPIO_DFX4 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 5 , NA , 0x4428 , NORTH ) , // - CHV_GPIO_PAD_CONF (L"N04: GPIO_DFX5 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 4 , NA , 0x4420 , NORTH ) , // - CHV_GPIO_PAD_CONF (L"N08: GPIO_DFX6 ", Native , M8 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 8 , NA , 0x4440 , NORTH ) , // - CHV_GPIO_PAD_CONF (L"N02: GPIO_DFX7 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 2 , NA , 0x4410 , NORTH ) , // -//CHV_GPIO_PAD_CONF (L"N06: GPIO_DFX8 ", GPIO , M1 , GPI , NA , NA , Trig_Level , Line0 , NA , NA , NA , NonMaskable , En_RX_Data , No_Inversion , NA , 6 , NA , 0x4430 , NORTH ) , // JACK DETECT? - CHV_GPIO_PAD_CONF (L"N15: GPIO_SUS0 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 9 , NA , 0x4800 , NORTH ) , // GPIO0_SUS0 - CHV_GPIO_PAD_CONF (L"N19: GPIO_SUS1 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 13 , NA , 0x4820 , NORTH ) , // GPIO_SUS1 - CHV_GPIO_PAD_CONF (L"N24: GPIO_SUS2 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 18 , NA , 0x4848 , NORTH ) , // NGFF_PWR_EN - CHV_GPIO_PAD_CONF (L"N17: GPIO_SUS3 ", GPIO , M1 , GPI , NA , NA , Trig_Level , Line1 , NA , NA , NA , NonMaskable , En_Edge_RX_Data , No_Inversion , NA , 11 , NA , 0x4810 , NORTH ) , // NGFF_SDIO_WAKE_N - CHV_GPIO_PAD_CONF (L"N22: GPIO_SUS4 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 16 , NA , 0x4838 , NORTH ) , // NGFF_KILL_BT_N - CHV_GPIO_PAD_CONF (L"N20: GPIO_SUS5 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 14 , NA , 0x4828 , NORTH ) , // NGFF_KILL_WIFI_N - CHV_GPIO_PAD_CONF (L"N71: HV_DDI0_DDC_SCL ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 57 , NA , 0x5458 , NORTH ) , // HDMI_SMB_SOC_SCL - CHV_GPIO_PAD_CONF (L"N66: HV_DDI0_DDC_SDA ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 52 , NA , 0x5430 , NORTH ) , // HDMI_SMB_SOC_SDA - CHV_GPIO_PAD_CONF (L"N61: HV_DDI0_HPD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , Inv_TX_Enable , NA , 47 , NA , 0x5408 , NORTH ) , // SOC_HDMI_HPD - CHV_GPIO_PAD_CONF (L"N64: HV_DDI1_HPD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , Inv_TX_Enable , NA , 50 , NA , 0x5420 , NORTH ) , // SOC_DP1_HPD - CHV_GPIO_PAD_CONF (L"N67: HV_DDI2_DDC_SCL ", Native , M3 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 53 , NA , 0x5438 , NORTH ) , // UART0_TXD (Default) || DDI1_DDC_SCL - CHV_GPIO_PAD_CONF (L"N62: HV_DDI2_DDC_SDA ", Native , M3 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 48 , NA , 0x5410 , NORTH ) , // UART0_RXD (Default) || DDI1_DDC_SCA - CHV_GPIO_PAD_CONF (L"N68: HV_DDI2_HPD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , Inv_TX_Enable , NA , 54 , NA , 0x5440 , NORTH ) , // SOC_DP2_HPD - CHV_GPIO_PAD_CONF (L"N65: PANEL0_BKLTCTL ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 51 , NA , 0x5428 , NORTH ) , // BRD_ID_BIT_0 - CHV_GPIO_PAD_CONF (L"N60: PANEL0_BKLTEN ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 46 , NA , 0x5400 , NORTH ) , // BRD_ID_BIT_1 - CHV_GPIO_PAD_CONF (L"N72: PANEL0_VDDEN ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 58 , NA , 0x5460 , NORTH ) , // BRD_ID_BIT_2 - CHV_GPIO_PAD_CONF (L"N63: PANEL1_BKLTCTL ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 49 , NA , 0x5418 , NORTH ) , // - CHV_GPIO_PAD_CONF (L"N70: PANEL1_BKLTEN ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 56 , NA , 0x5450 , NORTH ) , // - CHV_GPIO_PAD_CONF (L"N69: PANEL1_VDDEN ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 55 , NA , 0x5448 , NORTH ) , // - CHV_GPIO_PAD_CONF (L"N32: PROCHOT_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 24 , NA , 0x4C10 , NORTH ) , // VR_HOT_N - CHV_GPIO_PAD_CONF (L"N16: SEC_GPIO_SUS10 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 10 , NA , 0x4808 , NORTH ) , // GPIO_SUS10 - CHV_GPIO_PAD_CONF (L"N21: SEC_GPIO_SUS11 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 15 , NA , 0x4830 , NORTH ) , // GPIO_SUS11 - CHV_GPIO_PAD_CONF (L"N23: SEC_GPIO_SUS8 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 17 , NA , 0x4840 , NORTH ) , // GPIO_SUS8 -// CHV_GPIO_PAD_CONF (L"N38: SVID0_ALERT_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 30 , NA , 0x4C40 , NORTH ) , // SVID_ALERT_N -// CHV_GPIO_PAD_CONF (L"N40: SVID0_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 32 , NA , 0x4C50 , NORTH ) , // SVD_CLK -// CHV_GPIO_PAD_CONF (L"N33: SVID0_DATA ", Native , M0 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 25 , NA , 0x4C18 , NORTH ) , // SVID_DATA - CHV_GPIO_PAD_CONF (L"N31: TCK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 23 , NA , 0x4C08 , NORTH ) , // XDP_TCK - CHV_GPIO_PAD_CONF (L"N41: TDI ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 33 , NA , 0x4C58 , NORTH ) , // XDP_TDI - CHV_GPIO_PAD_CONF (L"N39: TDO ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 31 , NA , 0x4C48 , NORTH ) , // XDP_TDO - CHV_GPIO_PAD_CONF (L"N36: TDO_2 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 28 , NA , 0x4C30 , NORTH ) , // - CHV_GPIO_PAD_CONF (L"N34: TMS ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 26 , NA , 0x4C20 , NORTH ) , // XDP_TMS - CHV_GPIO_PAD_CONF (L"N30: TRST_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 22 , NA , 0x4C00 , NORTH ) , // XDP_TRST_N - - // - // East Community - // Group Pin#: PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks - // - CHV_GPIO_PAD_CONF (L"E21: MF_ISH_GPIO_0 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 18 , NA , 0x4830 , EAST ) , // FAB ID bit 0 - CHV_GPIO_PAD_CONF (L"E18: MF_ISH_GPIO_1 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 15 , NA , 0x4818 , EAST ) , // FAB ID bit 1 - CHV_GPIO_PAD_CONF (L"E24: MF_ISH_GPIO_2 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 21 , NA , 0x4848 , EAST ) , // FAB ID bit 2 - CHV_GPIO_PAD_CONF (L"E15: MF_ISH_GPIO_3 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 12 , NA , 0x4800 , EAST ) , // FAB ID bit 3 - CHV_GPIO_PAD_CONF (L"E22: MF_ISH_GPIO_4 ", GPIO , M1 , GPI , NA , NA , NA , Line0 , NA , NA , NA , NonMaskable , NA , No_Inversion , NA , 19 , NA , 0x4838 , EAST ) , // Not Used, Test points - CHV_GPIO_PAD_CONF (L"E19: MF_ISH_GPIO_5 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 16 , NA , 0x4820 , EAST ) , // Not Used, Test points - CHV_GPIO_PAD_CONF (L"E25: MF_ISH_GPIO_6 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 22 , NA , 0x4850 , EAST ) , // Not Used, Test points - CHV_GPIO_PAD_CONF (L"E16: MF_ISH_GPIO_7 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 13 , NA , 0x4808 , EAST ) , // Not Used, Test points - CHV_GPIO_PAD_CONF (L"E23: MF_ISH_GPIO_8 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 20 , NA , 0x4840 , EAST ) , // Not Used, Test points - CHV_GPIO_PAD_CONF (L"E20: MF_ISH_GPIO_9 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 17 , NA , 0x4828 , EAST ) , // Not Used, Test points - CHV_GPIO_PAD_CONF (L"E26: MF_ISH_I2C1_SDA ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 23 , NA , 0x4858 , EAST ) , // Not Used, Test points - CHV_GPIO_PAD_CONF (L"E17: MF_ISH_I2C1_SCL ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 14 , NA , 0x4810 , EAST ) , // Not Used, Test points - CHV_GPIO_PAD_CONF (L"E04: PMU_AC_PRESENT ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 4 , NA , 0x4420 , EAST ) , // PMU_AC_PRESENT - CHV_GPIO_PAD_CONF (L"E01: PMU_BATLOW_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 1 , NA , 0x4408 , EAST ) , // PMU_BATLOW_N - CHV_GPIO_PAD_CONF (L"E05: PMU_PLTRST_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 5 , NA , 0x4428 , EAST ) , // PLTRST_3P3_N -//CHV_GPIO_PAD_CONF (L"E08: PMU_PWRBTN_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 8 , NA , 0x4440 , EAST ) , // SOC_PWRBTN_N special programming below - CHV_GPIO_PAD_CONF (L"E07: PMU_SLP_LAN_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 7 , NA , 0x4438 , EAST ) , // Not Used, Available - CHV_GPIO_PAD_CONF (L"E03: PMU_SLP_S0IX_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 3 , NA , 0x4418 , EAST ) , // SLP_S01X_3P3_N - CHV_GPIO_PAD_CONF (L"E00: PMU_SLP_S3_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 0 , NA , 0x4400 , EAST ) , // SLP_S3_3P3_N - CHV_GPIO_PAD_CONF (L"E09: PMU_SLP_S4_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 9 , NA , 0x4448 , EAST ) , // SLP_S4_3P3_N - CHV_GPIO_PAD_CONF (L"E06: PMU_SUSCLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 6 , NA , 0x4430 , EAST ) , // SUSCLK_3P3 - CHV_GPIO_PAD_CONF (L"E10: PMU_WAKE_B ", Native , M1 , NA , NA , NA , NA , NA , P_1K_H , NA , NA , NA , NA , No_Inversion , NA , 10 , NA , 0x4450 , EAST ) , // PMU_3P3_WAKE_N - CHV_GPIO_PAD_CONF (L"E11: PMU_WAKE_LAN_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 11 , NA , 0x4458 , EAST ) , // Not Used, Available - CHV_GPIO_PAD_CONF (L"E02: SUS_STAT_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 2 , NA , 0x4410 , EAST ) , // SUS_STAT_N - - // - // South East Community - // Group Pin#: PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks - // - CHV_GPIO_PAD_CONF (L"SE16: SDMMC1_CLK ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_L , NA , NA , NA , NA , No_Inversion , NA , 9 , NA , 0x4808 , SOUTHEAST ) , // EMMC1_CLK - CHV_GPIO_PAD_CONF (L"SE23: SDMMC1_CMD ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 16 , NA , 0x4840 , SOUTHEAST ) , // EMMC1_CMD - CHV_GPIO_PAD_CONF (L"SE17: SDMMC1_D0 ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 10 , NA , 0x4810 , SOUTHEAST ) , // EMMC1_D_0 - CHV_GPIO_PAD_CONF (L"SE24: SDMMC1_D1 ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 17 , NA , 0x4848 , SOUTHEAST ) , // EMMC1_D_1 - CHV_GPIO_PAD_CONF (L"SE20: SDMMC1_D2 ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 13 , NA , 0x4828 , SOUTHEAST ) , // EMMC1_D_2 - CHV_GPIO_PAD_CONF (L"SE26: SDMMC1_D3_CD_B ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 19 , NA , 0x4858 , SOUTHEAST ) , // EMMC1_D_3 - CHV_GPIO_PAD_CONF (L"SE67: MMC1_D4_SD_WE ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 41 , NA , 0x5438 , SOUTHEAST ) , // EMMC1_D4 - CHV_GPIO_PAD_CONF (L"SE65: MMC1_D5 ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 39 , NA , 0x5428 , SOUTHEAST ) , // EMMC1_D5 - CHV_GPIO_PAD_CONF (L"SE63: MMC1_D6 ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 37 , NA , 0x5418 , SOUTHEAST ) , // EMMC1_D6 - CHV_GPIO_PAD_CONF (L"SE68: MMC1_D7 ", Native , M1 , NA , NA , HIGH , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 42 , NA , 0x5440 , SOUTHEAST ) , // EMMC1_D7 - CHV_GPIO_PAD_CONF (L"SE69: MMC1_RCLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 43 , NA , 0x5448 , SOUTHEAST ) , // EMMC1_RCLK - CHV_GPIO_PAD_CONF (L"SE77: GPIO_ALERT ", GPIO , M1 , GPI , NA , NA , Trig_Level , Line2 , NA , NA , NA , NonMaskable , En_RX_Data , Inv_RX_Data , NA , 46 , NA , 0x5810 , SOUTHEAST ) , // DCN : 2502579 - Programmed for TCH_PAD_INT_N - CHV_GPIO_PAD_CONF (L"SE79: ILB_SERIRQ ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 48 , NA , 0x5820 , SOUTHEAST ) , // ILB_SERIRQ - CHV_GPIO_PAD_CONF (L"SE51: MF_LPC_CLKOUT0 ", Native , M1 , NA , NA , NA , NA , NA , P_NONE , NA , NA , NA , NA , No_Inversion , NA , 32 , NA , 0x5030 , SOUTHEAST ) , // L_CLKOUT0 - CHV_GPIO_PAD_CONF (L"SE49: MF_LPC_CLKOUT1 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 30 , NA , 0x5020 , SOUTHEAST ) , // L_CLKOUT1 - CHV_GPIO_PAD_CONF (L"SE47: MF_LPC_AD0 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 28 , NA , 0x5010 , SOUTHEAST ) , // LPC_AD0 - CHV_GPIO_PAD_CONF (L"SE52: MF_LPC_AD1 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 33 , NA , 0x5038 , SOUTHEAST ) , // LPC_AD1 - CHV_GPIO_PAD_CONF (L"SE45: MF_LPC_AD2 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 26 , NA , 0x5000 , SOUTHEAST ) , // LPC_AD2 - CHV_GPIO_PAD_CONF (L"SE50: MF_LPC_AD3 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 31 , NA , 0x5028 , SOUTHEAST ) , // LPC_AD3 - CHV_GPIO_PAD_CONF (L"SE46: LPC_CLKRUNB ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 27 , NA , 0x5008 , SOUTHEAST ) , // L_CLKRUN_N - CHV_GPIO_PAD_CONF (L"SE48: LPC_FRAMEB ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 29 , NA , 0x5018 , SOUTHEAST ) , // L_FRAME_N - CHV_GPIO_PAD_CONF (L"SE00: MF_PLT_CLK0 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 0 , NA , 0x4400 , SOUTHEAST ) , // CAM_1_MCLK Camera1_clock - CHV_GPIO_PAD_CONF (L"SE02: MF_PLT_CLK1 ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 1 , NA , 0x4410 , SOUTHEAST ) , // CAM_2_MCLK Camera2_clock - CHV_GPIO_PAD_CONF (L"SE07: MF_PLT_CLK2 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 7 , NA , 0x4438 , SOUTHEAST ) , // Not Used - CHV_GPIO_PAD_CONF (L"SE04: MF_PLT_CLK3 ", GPIO , M1 , GPI , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 4 , NA , 0x4420 , SOUTHEAST ) , // I2S_MCLK - CHV_GPIO_PAD_CONF (L"SE03: MF_PLT_CLK4 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 3 , NA , 0x4418 , SOUTHEAST ) , // Not Used - CHV_GPIO_PAD_CONF (L"SE06: MF_PLT_CLK5 ", GPIO , M3 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 6 , NA , 0x4430 , SOUTHEAST ) , // Not Used -//CHV_GPIO_PAD_CONF (L"SE76: PMU_RSTBUTTON_B", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 45 , NA , 0x5808 , SOUTHEAST ) , // SOC_RESETBTN_N special programming below - CHV_GPIO_PAD_CONF (L"SE83: SUSPWRDNACK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 52 , NA , 0x5840 , SOUTHEAST ) , // SUSPWRDNACK_3P3 - CHV_GPIO_PAD_CONF (L"SE05: PWM0 ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 5 , NA , 0x4428 , SOUTHEAST ) , // - CHV_GPIO_PAD_CONF (L"SE01: PWM1 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 1 , NA , 0x4408 , SOUTHEAST ) , // WIFI_PCIE_RST_N - CHV_GPIO_PAD_CONF (L"SE85: SDMMC3_1P8_EN ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 54 , NA , 0x5850 , SOUTHEAST ) , // SD_CARD_PWR_EN - CHV_GPIO_PAD_CONF (L"SE81: SDMMC3_CD_B ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 50 , NA , 0x5830 , SOUTHEAST ) , // SD_CARD_DET_N - CHV_GPIO_PAD_CONF (L"SE31: SDMMC3_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 21 , NA , 0x4C08 , SOUTHEAST ) , // SD_CARD_CLK - CHV_GPIO_PAD_CONF (L"SE34: SDMMC3_CMD ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 24 , NA , 0x4C20 , SOUTHEAST ) , // SD_CARD_CMD - CHV_GPIO_PAD_CONF (L"SE35: SDMMC3_D0 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 25 , NA , 0x4C28 , SOUTHEAST ) , // SD_CARD_D0 - CHV_GPIO_PAD_CONF (L"SE30: SDMMC3_D1 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 20 , NA , 0x4C00 , SOUTHEAST ) , // SD_CARD_D1 - CHV_GPIO_PAD_CONF (L"SE33: SDMMC3_D2 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 23 , NA , 0x4C18 , SOUTHEAST ) , // SD_CARD_D2 - CHV_GPIO_PAD_CONF (L"SE32: SDMMC3_D3 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 22 , NA , 0x4C10 , SOUTHEAST ) , // SD_CARD_D3 - CHV_GPIO_PAD_CONF (L"SE78: SDMMC3_PWR_EN_B", Native , M1 , NA , NA , NA , NA , NA , P_20K_L , NA , NA , NA , NA , No_Inversion , NA , 47 , NA , 0x5818 , SOUTHEAST ) , // SD_CARD_PWRDN_N - CHV_GPIO_PAD_CONF (L"SE19: SDMMC2_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 12 , NA , 0x4820 , SOUTHEAST ) , // NGFF_SDEMMC2_CLK - CHV_GPIO_PAD_CONF (L"SE22: SDMMC2_CMD ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 15 , NA , 0x4838 , SOUTHEAST ) , // NGFF_SDEMMC2_CM - CHV_GPIO_PAD_CONF (L"SE25: SDMMC2_D0 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 18 , NA , 0x4850 , SOUTHEAST ) , // NGFF_SDEMMC2_D0 - CHV_GPIO_PAD_CONF (L"SE18: SDMMC2_D1 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 11 , NA , 0x4818 , SOUTHEAST ) , // NGFF_SDEMMC2_D1 - CHV_GPIO_PAD_CONF (L"SE21: SDMMC2_D2 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 14 , NA , 0x4830 , SOUTHEAST ) , // NGFF_SDEMMC2_D2 - CHV_GPIO_PAD_CONF (L"SE15: SDMMC2_D3_CD_B ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 8 , NA , 0x4800 , SOUTHEAST ) , // NGFF_SDEMMC2_D3 - CHV_GPIO_PAD_CONF (L"SE62: SPI1_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 36 , NA , 0x5410 , SOUTHEAST ) , // SPI1_CLK - CHV_GPIO_PAD_CONF (L"SE61: SPI1_CS0_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 35 , NA , 0x5408 , SOUTHEAST ) , // SPI1_CS0_N - CHV_GPIO_PAD_CONF (L"SE66: SPI1_CS1_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 40 , NA , 0x5430 , SOUTHEAST ) , // SPI1_CS1_N - CHV_GPIO_PAD_CONF (L"SE60: SPI1_MISO ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 34 , NA , 0x5400 , SOUTHEAST ) , // SPI1_MISO - CHV_GPIO_PAD_CONF (L"SE64: SPI1_MOSI ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 38 , NA , 0x5420 , SOUTHEAST ) , // SPI1_MOSI - CHV_GPIO_PAD_CONF (L"SE80: USB_OC0_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 49 , NA , 0x5828 , SOUTHEAST ) , // USB3_OC0_N - CHV_GPIO_PAD_CONF (L"SE75: USB_OC1_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 44 , NA , 0x5800 , SOUTHEAST ) , // USB3_OC1_N - // - // South west Community - // Group Pin#: PAD Name Mode Select Mode# GPIO Config GPIO TX State GPIO Light INT Type INT Select Term H/L Open Drain Current Source Mask/Un-Mask Glitch Cfg InvertRX_TX WAKE Cap Wake_Mask_Bit GPE MMIO Addr Community Remarks - // - CHV_GPIO_PAD_CONF (L"SW02: FST_SPI_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 2 , NA , 0x4410 , SOUTHWEST ) , // FAST_SPI_CLK - CHV_GPIO_PAD_CONF (L"SW06: FST_SPI_CS0_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 6 , NA , 0x4430 , SOUTHWEST ) , // FST_SPI_CS_N - CHV_GPIO_PAD_CONF (L"SW04: FST_SPI_CS1_B ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 4 , NA , 0x4420 , SOUTHWEST ) , // V3P3DX_TCH_EN - CHV_GPIO_PAD_CONF (L"SW07: FST_SPI_CS2_B ", GPIO , M1 , GPO , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 7 , NA , 0x4438 , SOUTHWEST ) , // FST_SPI_CS2_N (SPI TPM) - CHV_GPIO_PAD_CONF (L"SW01: FST_SPI_D0 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 1 , NA , 0x4408 , SOUTHWEST ) , // FST_SPI_D0 - CHV_GPIO_PAD_CONF (L"SW05: FST_SPI_D1 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 5 , NA , 0x4428 , SOUTHWEST ) , // FST_SPI_D1 - CHV_GPIO_PAD_CONF (L"SW00: FST_SPI_D2 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 0 , NA , 0x4400 , SOUTHWEST ) , // FST_SPI_D2 - CHV_GPIO_PAD_CONF (L"SW03: FST_SPI_D3 ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 3 , NA , 0x4418 , SOUTHWEST ) , // FST_SPI_D3 - CHV_GPIO_PAD_CONF (L"SW30: MF_HDA_CLK ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 16 , NA , 0x4C00 , SOUTHWEST ) , // MF_HDA_CLK II GP_SSP_0_I2S_TXD - CHV_GPIO_PAD_CONF (L"SW37: MF_HDA_DOCKENB ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 23 , NA , 0x4C38 , SOUTHWEST ) , // NGFF_I2S_1_RXD_R_BT || I2S_2_RXD_R_AICO - CHV_GPIO_PAD_CONF (L"SW34: MF_HDA_DOCKRSTB", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 20 , NA , 0x4C20 , SOUTHWEST ) , // NGFF_I2S_1_TXD_R_BT || I2S_2_TXD_R_AICO - CHV_GPIO_PAD_CONF (L"SW31: MF_HDA_RSTB ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 17 , NA , 0x4C08 , SOUTHWEST ) , // AUD_LINK_RST_N - CHV_GPIO_PAD_CONF (L"SW32: MF_HDA_SDI0 ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 18 , NA , 0x4C10 , SOUTHWEST ) , // AUD_LINK_SDI0_SOC - CHV_GPIO_PAD_CONF (L"SW36: MF_HDA_SDI1 ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 22 , NA , 0x4C30 , SOUTHWEST ) , // AUD_LINK_SDI1_SOC - CHV_GPIO_PAD_CONF (L"SW33: MF_HDA_SDO ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 19 , NA , 0x4C18 , SOUTHWEST ) , // AUD_LINK_SDO - CHV_GPIO_PAD_CONF (L"SW35: MF_HDA_SYNC ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 21 , NA , 0x4C28 , SOUTHWEST ) , // AUD_LINK_SYNC - CHV_GPIO_PAD_CONF (L"SW18: UART1_CTS_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 11 , NA , 0x4818 , SOUTHWEST ) , // UART_BT_CTS - CHV_GPIO_PAD_CONF (L"SW15: UART1_RTS_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 8 , NA , 0x4800 , SOUTHWEST ) , // UART_BT_RTS - CHV_GPIO_PAD_CONF (L"SW16: UART1_RXD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 9 , NA , 0x4808 , SOUTHWEST ) , // UART_BT_RXD - CHV_GPIO_PAD_CONF (L"SW20: UART1_TXD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 13 , NA , 0x4828 , SOUTHWEST ) , // UART_BT_TXD - CHV_GPIO_PAD_CONF (L"SW22: UART2_CTS_B ", Native , M1 , NA , NA , NA , NA , NA , P_NONE , NA , NA , NA , NA , No_Inversion , NA , 15 , NA , 0x4838 , SOUTHWEST ) , // UART_GPS_CTS - CHV_GPIO_PAD_CONF (L"SW19: UART2_RTS_B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 12 , NA , 0x4820 , SOUTHWEST ) , // UART_GPS_RTS - CHV_GPIO_PAD_CONF (L"SW17: UART2_RXD ", Native , M1 , NA , NA , NA , NA , NA , P_NONE , NA , NA , NA , NA , No_Inversion , NA , 10 , NA , 0x4810 , SOUTHWEST ) , // UART_GPS_RXD - CHV_GPIO_PAD_CONF (L"SW21: UART2_TXD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 14 , NA , 0x4830 , SOUTHWEST ) , // UART_GPS_TXD - CHV_GPIO_PAD_CONF (L"SW65: I2C0_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 37 , NA , 0x5428 , SOUTHWEST ) , // I2C_3P3_NGFF_SDA - CHV_GPIO_PAD_CONF (L"SW61: I2C0_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 33 , NA , 0x5408 , SOUTHWEST ) , // I2C_3P3_NGFF_SCL - CHV_GPIO_PAD_CONF (L"SW63: I2C1_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 35 , NA , 0x5418 , SOUTHWEST ) , // I2C1_SDA_AUD_CONN - CHV_GPIO_PAD_CONF (L"SW60: I2C1_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 32 , NA , 0x5400 , SOUTHWEST ) , // I2C1_SCL_AUD_CONN - CHV_GPIO_PAD_CONF (L"SW66: I2C2_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 38 , NA , 0x5430 , SOUTHWEST ) , // I2C2_SDA_CAM - CHV_GPIO_PAD_CONF (L"SW62: I2C2_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 34 , NA , 0x5410 , SOUTHWEST ) , // I2C2_SCL_CAM - CHV_GPIO_PAD_CONF (L"SW67: I2C3_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 39 , NA , 0x5438 , SOUTHWEST ) , // I2C3_CAM_SDA - CHV_GPIO_PAD_CONF (L"SW64: I2C3_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 36 , NA , 0x5420 , SOUTHWEST ) , // I2C3_CAM_SCL - CHV_GPIO_PAD_CONF (L"SW50: I2C4_SCL ", Native , M3 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 29 , NA , 0x5028 , SOUTHWEST ) , // HV_DDI2_DDC_SCL - CHV_GPIO_PAD_CONF (L"SW46: I2C4_SDA ", Native , M3 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 25 , NA , 0x5008 , SOUTHWEST ) , // HV_DDI2_DDC_SDA - CHV_GPIO_PAD_CONF (L"SW48: I2C5_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 27 , NA , 0x5018 , SOUTHWEST ) , // I2C5_SDA_3P3 - CHV_GPIO_PAD_CONF (L"SW45: I2C5_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 24 , NA , 0x5000 , SOUTHWEST ) , // I2C5_SDA_3P3 - CHV_GPIO_PAD_CONF (L"SW51: I2C6_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 30 , NA , 0x5030 , SOUTHWEST ) , // - CHV_GPIO_PAD_CONF (L"SW47: I2C6_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 26 , NA , 0x5010 , SOUTHWEST ) , // - CHV_GPIO_PAD_CONF (L"SW49: I2C_NFC_SDA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 28 , NA , 0x5020 , SOUTHWEST ) , // I2C_NFC_SDA_3P3 - CHV_GPIO_PAD_CONF (L"SW52: I2C_NFC_SCL ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , Inv_TX_Enable , NA , 31 , NA , 0x5038 , SOUTHWEST ) , // I2C_NFC_SCL_3P3 - CHV_GPIO_PAD_CONF (L"SW77: GP_SSP_2_CLK ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 50 , NA , 0x5C10 , SOUTHWEST ) , // I2S_2_CLK - CHV_GPIO_PAD_CONF (L"SW81: GP_SSP_2_FS ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 54 , NA , 0x5C30 , SOUTHWEST ) , // I2S_2_FS - CHV_GPIO_PAD_CONF (L"SW79: GP_SSP_2_RXD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 52 , NA , 0x5C20 , SOUTHWEST ) , // I2S_2_RXD - CHV_GPIO_PAD_CONF (L"SW82: GP_SSP_2_TXD ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , Inv_TX_Enable , NA , 55 , NA , 0x5C38 , SOUTHWEST ) , // I2S_2_TXD - CHV_GPIO_PAD_CONF (L"SW90: PCIE_CLKREQ0B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 48 , NA , 0x5C00 , SOUTHWEST ) , // - CHV_GPIO_PAD_CONF (L"SW91: PCIE_CLKREQ1B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 49 , NA , 0x5C08 , SOUTHWEST ) , // PCIE_CLKREQ1_N - CHV_GPIO_PAD_CONF (L"SW93: PCIE_CLKREQ2B ", Native , M1 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 51 , NA , 0x5C18 , SOUTHWEST ) , // PCIE_CLKREQ2_N - CHV_GPIO_PAD_CONF (L"SW95: PCIE_CLKREQ3B ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 53 , NA , 0x5C28 , SOUTHWEST ) , // SDMMC3_WP (Def) -//CHV_GPIO_PAD_CONF (L"SW95: PCIE_CLKREQ3B ", Native , M2 , NA , NA , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 53 , NA , 0x5C28 , SOUTHWEST ) , // GPI_SOC_HOMESCRN - CHV_GPIO_PAD_CONF (L"SW75: SATA_GP0 ", GPIO , M1 , GPO , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 40 , NA , 0x5800 , SOUTHWEST ) , // reserved for SATA (Interlock switch) - CHV_GPIO_PAD_CONF (L"SW76: SATA_GP1 ", GPIO , M1 , GPI , HIGH , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 41 , NA , 0x5808 , SOUTHWEST ) , // GPI to select UART0 | DDI1 mode - CHV_GPIO_PAD_CONF (L"SW78: SATA_GP2 ", Native , M1 , NA , NA , NA , NA , NA , NA , _ENABLE , NA , NA , NA , No_Inversion , NA , 43 , NA , 0x5818 , SOUTHWEST ) , // SATA_DEVSLP0 -need to check - CHV_GPIO_PAD_CONF (L"SW80: SATA_GP3 ", GPIO , M2 , GPI , LOW , NA , NA , NA , NA , NA , NA , NA , NA , No_Inversion , NA , 45 , NA , 0x5828 , SOUTHWEST ) , // TOUCH_RST_N -need to check - CHV_GPIO_PAD_CONF (L"SW77: SATA_LEDN ", Native , M1 , NA , NA , NA , NA , NA , NA , _ENABLE , NA , NA , NA , No_Inversion , NA , 42 , NA , 0x5810 , SOUTHWEST ) , // SATA_LED_N - CHV_GPIO_PAD_CONF (L"SW79: MF_SMB_ALERTB ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 44 , NA , 0x5820 , SOUTHWEST ) , // SMB_ALERTB_3P3 - CHV_GPIO_PAD_CONF (L"SW81: MF_SMB_CLK ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 46 , NA , 0x5830 , SOUTHWEST ) , // SMB_3P3_CLK - CHV_GPIO_PAD_CONF (L"SW82: MF_SMB_DATA ", Native , M1 , NA , NA , NA , NA , NA , P_20K_H , NA , NA , NA , NA , No_Inversion , NA , 47 , NA , 0x5838 , SOUTHWEST ) , // SMB_3P3_DAT -}; +#include "BoardInit.h" +#include "BoardGpios.h" +#include "Dram.h" @@ -387,44 +99,73 @@ BraswellWesternDigitalBoardDetectionCallback ( // Workaround: If BoardId = 1, it is Cherry Hill CRB; otherwise, we treat it as Western Digital board (temp solution). // if (BoardId != 1) { + + // + // Collect board specific configuration for Western Digital EPIC. + // + + // + // ID + // PlatformInfoHob.BoardId = BOARD_ID_BSW_WD; - PlatformInfoHob.BoardSvidConfig = BSW_SVID_CONFIG0; - if (SocStepping() >= SocC0) { - PlatformInfoHob.BoardSvidConfig = BSW_SVID_CONFIG1; - } - DEBUG ((EFI_D_INFO, "I'm Braswell Western Digtial EPIC \n\n")); - DEBUG ((EFI_D_INFO, "SoC Stepping = 0x%x \n", ((UINT32)SocStepping()))); PlatformInfoHob.MemCfgID = 0; - DEBUG ((EFI_D_INFO, "PlatformInfoHob->MemCfgID= 0x%x\n", PlatformInfoHob.MemCfgID)); PlatformInfoHob.FABID = FabId; - DEBUG ((EFI_D_INFO, "PlatformInfoHob->FABID = 0x%x\n", FabId )); PlatformInfoHob.PlatformFlavor = FlavorMobile; - DEBUG ((EFI_D_INFO, "PlatformInfoHob->PlatformFlavor = 0x%x\n", PlatformInfoHob.PlatformFlavor )); - DEBUG ((EFI_D_INFO, "PlatformInfoHob->BoardSvidConfig = 0x%x\n", PlatformInfoHob.BoardSvidConfig )); - DEBUG ((EFI_D_INFO, "PlatformInfoHob->BoardId = 0x%x\n", PlatformInfoHob.BoardId )); + // + // EC + // PlatformInfoHob.ECSupport = FALSE; PlatformInfoHob.FanSupport = FALSE; PlatformInfoHob.BatterySupport = FALSE; - DataSize = sizeof (EFI_PLATFORM_INFO_HOB); - PcdSetPtr (PcdPlatformInfo, &DataSize, &PlatformInfoHob); + + // + // Grpahic + // DataSize = sizeof (EFI_GUID); PcdSetPtr (PcdBmpImageGuid, &DataSize, &gHdmiDpVbtGuid); + // + // Communication + // PcdSet8 (PcdNfcConnection, 0); // - // WD uses solder down memory + // Memory // PcdSet8 (PcdOemMemeoryDimmType,SolderDownMemory); PcdSet64 (PcdMemorySpdPtr, (UINT64)(UINTN)&mWD_CR_SpdDataMemorySolderDown); + //PcdSet8 (PcdMrcInitSpdAddr1, 0xA0); + //PcdSet8 (PcdMrcInitSpdAddr2, 0xA2); + + // + // Power + // + PlatformInfoHob.BoardSvidConfig = BSW_SVID_CONFIG0; + if (SocStepping() >= SocC0) { + PlatformInfoHob.BoardSvidConfig = BSW_SVID_CONFIG1; + } - // Program all the gpios at this moment - InternalGpioPADConfig(0, sizeof(mBswWesternDigitalGpioInitData)/sizeof(mBswWesternDigitalGpioInitData[0]), mBswWesternDigitalGpioInitData); + // + // GPIO + // + WesternDigitalBoardGpioConfigure(); + PcdSet64 (PcdGpioInitFunc, (UINT64)(UINTN)BraswellWesternDigitalGpioInit); + DataSize = sizeof (EFI_PLATFORM_INFO_HOB); + PcdSetPtr (PcdPlatformInfo, &DataSize, &PlatformInfoHob); Status = PeiServicesInstallPpi (&mBraswellWesternDigitalDetectedPpi); + + DEBUG ((EFI_D_INFO, "I'm Braswell Western Digtial EPIC \n\n")); + DEBUG ((EFI_D_INFO, "SoC Stepping = 0x%x \n", ((UINT32)SocStepping()))); + DEBUG ((EFI_D_INFO, "PlatformInfoHob->MemCfgID= 0x%x\n", PlatformInfoHob.MemCfgID)); + DEBUG ((EFI_D_INFO, "PlatformInfoHob->FABID = 0x%x\n", FabId )); + DEBUG ((EFI_D_INFO, "PlatformInfoHob->PlatformFlavor = 0x%x\n", PlatformInfoHob.PlatformFlavor )); + DEBUG ((EFI_D_INFO, "PlatformInfoHob->BoardSvidConfig = 0x%x\n", PlatformInfoHob.BoardSvidConfig )); + DEBUG ((EFI_D_INFO, "PlatformInfoHob->BoardId = 0x%x\n", PlatformInfoHob.BoardId )); + } } @@ -451,3 +192,4 @@ BraswellWesternDigitalInitConstructor ( return Status; } + diff --git a/BraswellPlatformPkg/Board/WesternDigital/BoardInit/BoardInit.h b/BraswellPlatformPkg/Board/WesternDigital/BoardInit/BoardInit.h new file mode 100644 index 0000000000..9ef2de06de --- /dev/null +++ b/BraswellPlatformPkg/Board/WesternDigital/BoardInit/BoardInit.h @@ -0,0 +1,37 @@ +/** @file + GPIO setting for CherryView. + + This file includes package header files, library classes. + + Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _BOARDINIT_H_ +#define _BOARDINIT_H_ + +#include +#include "PchAccess.h" +#include "PlatformBaseAddresses.h" +#include +#include +#include +#include +#include +#include + + +VOID +BraswellWesternDigitalGpioInit ( + VOID + ); +#endif + diff --git a/BraswellPlatformPkg/Board/WesternDigital/BoardInit/BoardInit.inf b/BraswellPlatformPkg/Board/WesternDigital/BoardInit/BoardInit.inf index e80db437dd..fab48e0e4b 100644 --- a/BraswellPlatformPkg/Board/WesternDigital/BoardInit/BoardInit.inf +++ b/BraswellPlatformPkg/Board/WesternDigital/BoardInit/BoardInit.inf @@ -25,6 +25,7 @@ [Sources] BoardInit.c + BoardGpios.c [LibraryClasses] PeiServicesLib @@ -52,6 +53,21 @@ ## SOMETIMES_PRODUCES gEfiEdkIIPlatformTokenSpaceGuid.PcdOemMemeoryDimmType + ## SOMETIMES_CONSUMES + gEfiEdkIIPlatformTokenSpaceGuid.PcdPlatformInfo + + ## SOMETIMES_PRODUCES + gEfiEdkIIPlatformTokenSpaceGuid.PcdGpioInitFunc + + ## SOMETIMES_CONSUMES + gPlatformModuleTokenSpaceGuid.PcdGPIOSUS6Configuration + + ## SOMETIMES_CONSUMES + gPlatformModuleTokenSpaceGuid.PcdGPIOSUS7Configuration + + ## SOMETIMES_CONSUMES + gPlatformModuleTokenSpaceGuid.PcdGPIOSUS8Configuration + [Guids] ## SOMETIMES_CONSUMES @@ -64,3 +80,4 @@ ## SOMETIMES_PRODUCES ## SOMETIMES_CONSUMES gBoardDetectedPpiGuid + diff --git a/BraswellPlatformPkg/Board/WesternDigital/BoardInit/BoardInitLate.c b/BraswellPlatformPkg/Board/WesternDigital/BoardInit/BoardInitLate.c deleted file mode 100644 index 86447e915e..0000000000 --- a/BraswellPlatformPkg/Board/WesternDigital/BoardInit/BoardInitLate.c +++ /dev/null @@ -1,71 +0,0 @@ -/** @file - Board Init driver. - - Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php. - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "BoardGpios.h" - -VOID -SAI_SettingOfGpioFamilies ( - GPIO_SAI_INIT* SAI_Conf_Data, - UINT32 familySize - ); - -VOID -BraswellWesternDigitalGpioInit ( - VOID - ) -{ - - DEBUG ((EFI_D_ERROR, "Programming BSW CR Board Gpio Tables which are not done properly by FSP...\n")); - - - // GPIO lock if really want - SAI_SettingOfGpioFamilies(mBSW_WD_GPIO_SAI_Init_East, sizeof(mBSW_WD_GPIO_SAI_Init_East)/sizeof(mBSW_WD_GPIO_SAI_Init_East[0])); - SAI_SettingOfGpioFamilies(mBSW_WD_GPIO_SAI_Init_North, sizeof(mBSW_WD_GPIO_SAI_Init_North)/sizeof(mBSW_WD_GPIO_SAI_Init_North[0])); - SAI_SettingOfGpioFamilies(mBSW_WD_GPIO_SAI_Init_SouthEast, sizeof(mBSW_WD_GPIO_SAI_Init_SouthEast)/sizeof(mBSW_WD_GPIO_SAI_Init_SouthEast[0])); - SAI_SettingOfGpioFamilies(mBSW_WD_GPIO_SAI_Init_SouthWest, sizeof(mBSW_WD_GPIO_SAI_Init_SouthWest)/sizeof(mBSW_WD_GPIO_SAI_Init_SouthWest[0])); -} - -/** - This function performs Board initialization in Pre-Memory. - - @retval EFI_SUCCESS The PPI is installed and initialized. - @retval EFI ERRORS The PPI is not successfully installed. - @retval EFI_OUT_OF_RESOURCES No enough resoruces (such as out of memory). -**/ -EFI_STATUS -EFIAPI -BraswellWesternDigitalInitLateConstructor ( - IN EFI_PEI_FILE_HANDLE FileHandle, - IN CONST EFI_PEI_SERVICES **PeiServices - ) -{ - EFI_PLATFORM_INFO_HOB *PlatformInfoHob; - - PlatformInfoHob = PcdGetPtr (PcdPlatformInfo); - if (PlatformInfoHob->BoardId == BOARD_ID_BSW_WD) { - PcdSet64 (PcdGpioInitFunc, (UINT64)(UINTN)BraswellWesternDigitalGpioInit); - } - - return EFI_SUCCESS; -} diff --git a/BraswellPlatformPkg/Board/WesternDigital/BoardInit/BoardInitLate.inf b/BraswellPlatformPkg/Board/WesternDigital/BoardInit/BoardInitLate.inf deleted file mode 100644 index 71bffffcb2..0000000000 --- a/BraswellPlatformPkg/Board/WesternDigital/BoardInit/BoardInitLate.inf +++ /dev/null @@ -1,53 +0,0 @@ -## @file -# GPIO porting module for Intel(R) Atom(TM) x5 Processor Series. -# -# This module will do the basic PCH GPIO porting. -# -# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.
-# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php. -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -## - -[Defines] - INF_VERSION = 0x00010017 - BASE_NAME = BraswellWesternDigitalInitLate - FILE_GUID = CC235019-C750-41E4-AF71-A172C07ACE47 - VERSION_STRING = 1.0 - MODULE_TYPE = PEIM - CONSTRUCTOR = BraswellWesternDigitalInitLateConstructor - -[Sources] - BoardInitLate.c - -[LibraryClasses] - PeiServicesLib - PcdLib - -[Packages] - MdePkg/MdePkg.dec - ChvRefCodePkg/ChvRefCodePkg.dec - BraswellPlatformPkg/BraswellPlatformPkg.dec - -[Pcd] - ## SOMETIMES_CONSUMES - gEfiEdkIIPlatformTokenSpaceGuid.PcdPlatformInfo - - ## SOMETIMES_PRODUCES - gEfiEdkIIPlatformTokenSpaceGuid.PcdGpioInitFunc - - -[Ppis] - ## NOTIFY - gBoardDetectionStartPpiGuid - - ## SOMETIMES_PRODUCES - ## SOMETIMES_CONSUMES - gBoardDetectedPpiGuid - diff --git a/BraswellPlatformPkg/Board/WesternDigital/BoardInit/Dram.h b/BraswellPlatformPkg/Board/WesternDigital/BoardInit/Dram.h new file mode 100644 index 0000000000..e7849b29d3 --- /dev/null +++ b/BraswellPlatformPkg/Board/WesternDigital/BoardInit/Dram.h @@ -0,0 +1,94 @@ +/** @file + Board Init driver. + + Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + +// Input_Struct.tCL = 11; //< actual CL / +// Input_Struct.tRP_tRCD = 11; //< TRP and tRCD in dram clk/ +// Input_Struct.tWR = 12;// MIN =15ns //< in dram clk / +// Input_Struct.tWTR = 6;// MIN = greater of 4CK or 7.5ns //< in dram clk / +// Input_Struct.tRRD = 6;// MIN = greater of 4CK or 7.5ns //< in dram clk / +// Input_Struct.tRTP = 6;// MIN = greater of 4CK or 7.5ns; //< in dram clk / +// Input_Struct.tFAW = 32; +// +// TBD: Need update to CH version +// +UINT8 mWD_CR_SpdDataMemorySolderDown[] = { + 0x92, // Byte 0 + 0x12, // Byte 1 + 0x0b, // Byte 2 (Key Byte / DRAM Device Type) DDR3 SDRAM + 0x03, // Byte 3 (Key Byte / Module Type) SO-DIMM + 0x05, // Byte 4 (8Banks, 8Gb) + 0x23, // Byte 5 (SDRAM Addressing) 00 100 011 = 0x23 + 0x02, // Byte 6 + 0x02, // Byte 7: Module Organization Bit [5, 4, 3] : 000 = 1 Rank Bit [2, 1, 0] :010 = SDRAM Device Width 16 bits + 0x03, // Byte 8: Module Memory Bus Width Bit [2, 1, 0] : 011 = 64 bits + 0x52, // Byte 9: Fine Timebase (FTB) Dividend / Divisor + 0x01, // Byte 10: Medium Timebase (MTB) Dividend + 0x08, // Byte 11: Medium Timebase (MTB) Divisor + 0x0a, // Byte 12: SDRAM Minimum Cycle Time (tCKmin) + 0x00, // Byte 13: Reserved + 0xfe, // Byte 14: CAS Latencies Supported, Least Significant Byte (tCL) + 0x00, // Byte 15: CAS Latencies Supported, Most Significant Byte + 0x69, // Byte 16: Minimum CAS Latency Time (tAAmin) + 0x78, // Byte 17: Minimum Write Recovery Time (tWRmin) + 0x69, // Byte 18: Minimum RAS# to CAS# Delay Time (tRCDmin) + 0x3c, // Byte 19: Minimum Row Active to Row Active Delay Time (tRRDmin) + 0x69, // Byte 20: Minimum Row Precharge Delay Time (tRPmin) + 0x11, // Byte 21: Upper Nibbles for tRAS and tRC + 0x18, // Byte 22: Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte = 34 + 0x81, // Byte 23: Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte + 0x00, // Byte 24: Minimum Refresh Recovery Delay Time (tRFCmin), Least Significant Byte + 0x05, // Byte 25: Minimum Refresh Recovery Delay Time (tRFCmin), Most Significant Byte + 0x3c, // Byte 26: Minimum Internal Write to Read Command Delay Time (tWTRmin) + 0x3c, // Byte 27: Minimum Internal Read to Precharge Command Delay Time (tRTPmin) + 0x01, // Byte 28: Upper Nibble for tFAW + 0x40, // Byte 29: Minimum Four Activate Window Delay Time (tFAWmin), Least Significant Byte + 0x83, // Byte 30: SDRAM Optional Features + 0x01, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, //Byte40 + 0,0,0,0,0,0,0,0, + 0x00, + 0x00, + 0x00, + 0x00, + 0x0f, // Byte 60: + 0x11, + 0x22, + 0x00, + 0,0,0,0,0,0,0,0, //Byte64 + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0x00, //Byte112 + 0x00, + 0x00, + 0x00, + 0x00, + 0x80, + 0xad, + 0x01, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00 //Byte 215 +}; + + + -- cgit v1.2.3