From 8b2982cd59533486c31f6effae45cdf7899209b8 Mon Sep 17 00:00:00 2001 From: Jiewen Yao Date: Sat, 17 Mar 2018 07:41:44 +0800 Subject: PurleyOpenBoardPkg: Initial version. Cc: Isaac W Oram Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao Reviewed-by: Isaac W Oram --- .../Acpi/BoardAcpiDxe/AmlOffsetTable.c | 284 + .../Acpi/BoardAcpiDxe/BoardAcpiDxe.c | 552 ++ .../Acpi/BoardAcpiDxe/BoardAcpiDxe.h | 88 + .../Acpi/BoardAcpiDxe/BoardAcpiDxe.inf | 79 + .../Acpi/BoardAcpiDxe/BoardAcpiDxeDsdt.c | 522 ++ .../PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt.inf | 37 + .../Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl | 25 + .../Acpi/BoardAcpiDxe/Dsdt/CommonPlatform.asi | 233 + .../Acpi/BoardAcpiDxe/Dsdt/DSDT.asl | 83 + .../Acpi/BoardAcpiDxe/Dsdt/Gpe.asl | 140 + .../Acpi/BoardAcpiDxe/Dsdt/HostBus.asl | 262 + .../BoardAcpiDxe/Dsdt/IioPcieHotPlugGpeHandler.asl | 848 ++ .../BoardAcpiDxe/Dsdt/IioPcieRootPortHotPlug.asl | 692 ++ .../Acpi/BoardAcpiDxe/Dsdt/Itss.asl | 38 + .../Acpi/BoardAcpiDxe/Dsdt/Mother.asi | 208 + .../Acpi/BoardAcpiDxe/Dsdt/Os.asi | 151 + .../Acpi/BoardAcpiDxe/Dsdt/PC00.asi | 391 + .../Acpi/BoardAcpiDxe/Dsdt/PC01.asi | 261 + .../Acpi/BoardAcpiDxe/Dsdt/PC02.asi | 261 + .../Acpi/BoardAcpiDxe/Dsdt/PC03.asi | 266 + .../Acpi/BoardAcpiDxe/Dsdt/PC04.asi | 238 + .../Acpi/BoardAcpiDxe/Dsdt/PC05.asi | 239 + .../Acpi/BoardAcpiDxe/Dsdt/PC06.asi | 334 + .../Acpi/BoardAcpiDxe/Dsdt/PC06Ejd.asi | 15 + .../Acpi/BoardAcpiDxe/Dsdt/PC07.asi | 265 + .../Acpi/BoardAcpiDxe/Dsdt/PC08.asi | 268 + .../Acpi/BoardAcpiDxe/Dsdt/PC09.asi | 266 + .../Acpi/BoardAcpiDxe/Dsdt/PC10.asi | 238 + .../Acpi/BoardAcpiDxe/Dsdt/PC11.asi | 237 + .../Acpi/BoardAcpiDxe/Dsdt/PC12.asi | 330 + .../Acpi/BoardAcpiDxe/Dsdt/PC12Ejd.asi | 15 + .../Acpi/BoardAcpiDxe/Dsdt/PC13.asi | 262 + .../Acpi/BoardAcpiDxe/Dsdt/PC14.asi | 265 + .../Acpi/BoardAcpiDxe/Dsdt/PC15.asi | 265 + .../Acpi/BoardAcpiDxe/Dsdt/PC16.asi | 237 + .../Acpi/BoardAcpiDxe/Dsdt/PC17.asi | 237 + .../Acpi/BoardAcpiDxe/Dsdt/PC18.asi | 348 + .../Acpi/BoardAcpiDxe/Dsdt/PC18Ejd.asi | 15 + .../Acpi/BoardAcpiDxe/Dsdt/PC19.asi | 265 + .../Acpi/BoardAcpiDxe/Dsdt/PC20.asi | 266 + .../Acpi/BoardAcpiDxe/Dsdt/PC21.asi | 266 + .../Acpi/BoardAcpiDxe/Dsdt/PC22.asi | 238 + .../Acpi/BoardAcpiDxe/Dsdt/PC23.asi | 238 + .../Acpi/BoardAcpiDxe/Dsdt/PC24.asi | 237 + .../Acpi/BoardAcpiDxe/Dsdt/PC25.asi | 265 + .../Acpi/BoardAcpiDxe/Dsdt/PC26.asi | 265 + .../Acpi/BoardAcpiDxe/Dsdt/PC27.asi | 265 + .../Acpi/BoardAcpiDxe/Dsdt/PC28.asi | 238 + .../Acpi/BoardAcpiDxe/Dsdt/PC29.asi | 238 + .../Acpi/BoardAcpiDxe/Dsdt/PC30.asi | 262 + .../Acpi/BoardAcpiDxe/Dsdt/PC31.asi | 265 + .../Acpi/BoardAcpiDxe/Dsdt/PC32.asi | 266 + .../Acpi/BoardAcpiDxe/Dsdt/PC33.asi | 266 + .../Acpi/BoardAcpiDxe/Dsdt/PC34.asi | 238 + .../Acpi/BoardAcpiDxe/Dsdt/PC35.asi | 238 + .../Acpi/BoardAcpiDxe/Dsdt/PC36.asi | 263 + .../Acpi/BoardAcpiDxe/Dsdt/PC37.asi | 265 + .../Acpi/BoardAcpiDxe/Dsdt/PC38.asi | 266 + .../Acpi/BoardAcpiDxe/Dsdt/PC39.asi | 266 + .../Acpi/BoardAcpiDxe/Dsdt/PC40.asi | 238 + .../Acpi/BoardAcpiDxe/Dsdt/PC41.asi | 238 + .../Acpi/BoardAcpiDxe/Dsdt/PC42.asi | 296 + .../Acpi/BoardAcpiDxe/Dsdt/PC43.asi | 265 + .../Acpi/BoardAcpiDxe/Dsdt/PC44.asi | 238 + .../Acpi/BoardAcpiDxe/Dsdt/PC45.asi | 238 + .../Acpi/BoardAcpiDxe/Dsdt/PC46.asi | 238 + .../Acpi/BoardAcpiDxe/Dsdt/PC47.asi | 238 + .../Acpi/BoardAcpiDxe/Dsdt/Pch.asi | 16 + .../Acpi/BoardAcpiDxe/Dsdt/PchApic.asi | 23 + .../Acpi/BoardAcpiDxe/Dsdt/PchEhci1.asi | 97 + .../Acpi/BoardAcpiDxe/Dsdt/PchEhci2.asi | 98 + .../Acpi/BoardAcpiDxe/Dsdt/PchGbe.asl | 23 + .../Acpi/BoardAcpiDxe/Dsdt/PchLpc.asi | 28 + .../Acpi/BoardAcpiDxe/Dsdt/PchSata.asi | 813 ++ .../Acpi/BoardAcpiDxe/Dsdt/PchXhci.asi | 335 + .../Acpi/BoardAcpiDxe/Dsdt/PciCrs.asi | 318 + .../Acpi/BoardAcpiDxe/Dsdt/PciIrq.asi | 461 ++ .../Acpi/BoardAcpiDxe/Dsdt/PcieHp.asi | 650 ++ .../Acpi/BoardAcpiDxe/Dsdt/PcieHpDev.asi | 20 + .../Acpi/BoardAcpiDxe/Dsdt/PcieNonHpDev.asi | 22 + .../Acpi/BoardAcpiDxe/Dsdt/PcieSeg.asi | 361 + .../Acpi/BoardAcpiDxe/Dsdt/Platform.asl | 85 + .../Acpi/BoardAcpiDxe/Dsdt/PlatformGpe.asi | 84 + .../Acpi/BoardAcpiDxe/Dsdt/PlatformPciTree_WFP.asi | 8076 ++++++++++++++++++++ .../Acpi/BoardAcpiDxe/Dsdt/Sck1Ejd.asi | 15 + .../Acpi/BoardAcpiDxe/Dsdt/Sck2Ejd.asi | 15 + .../Acpi/BoardAcpiDxe/Dsdt/Sck3Ejd.asi | 15 + .../Acpi/BoardAcpiDxe/Dsdt/Uncore0.asi | 39 + .../Acpi/BoardAcpiDxe/Dsdt/Uncore1.asi | 181 + .../Acpi/BoardAcpiDxe/Dsdt/Uncore2.asi | 131 + .../Acpi/BoardAcpiDxe/Dsdt/Uncore3.asi | 104 + .../Acpi/BoardAcpiDxe/Dsdt/WFPPlatform.asl | 195 + .../BoardMtOlympus/GitEdk2MinMtOlympus.bat | 86 + .../BasePlatformHookLib/BasePlatformHookLib.c | 300 + .../BasePlatformHookLib/BasePlatformHookLib.inf | 44 + .../Library/BoardAcpiLib/DxeBoardAcpiTableLib.c | 41 + .../Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf | 47 + .../BoardAcpiLib/DxeMtOlympusAcpiTableLib.c | 58 + .../Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c | 67 + .../Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf | 47 + .../BoardAcpiLib/SmmMtOlympusAcpiEnableLib.c | 42 + .../Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c | 125 + .../Library/BoardInitLib/AllLanesEparam.c | 49 + .../Library/BoardInitLib/GpioTable.c | 302 + .../BoardMtOlympus/Library/BoardInitLib/IioBifur.c | 94 + .../Library/BoardInitLib/PeiBoardInitPostMemLib.c | 51 + .../BoardInitLib/PeiBoardInitPostMemLib.inf | 44 + .../Library/BoardInitLib/PeiBoardInitPreMemLib.c | 117 + .../Library/BoardInitLib/PeiBoardInitPreMemLib.inf | 77 + .../Library/BoardInitLib/PeiMtOlympusDetect.c | 33 + .../Library/BoardInitLib/PeiMtOlympusInitLib.h | 23 + .../BoardInitLib/PeiMtOlympusInitPostMemLib.c | 91 + .../BoardInitLib/PeiMtOlympusInitPreMemLib.c | 576 ++ .../BoardMtOlympus/Library/BoardInitLib/UsbOC.c | 51 + .../BoardMtOlympus/PlatformPkg.dsc | 225 + .../BoardMtOlympus/PlatformPkg.fdf | 638 ++ .../BoardMtOlympus/PlatformPkgBuildOption.dsc | 95 + .../BoardMtOlympus/PlatformPkgConfig.dsc | 61 + .../BoardMtOlympus/PlatformPkgPcd.dsc | 341 + .../BoardMtOlympus/StructureConfig.dsc | 6222 +++++++++++++++ .../PurleyOpenBoardPkg/BoardMtOlympus/bld.bat | 145 + .../PurleyOpenBoardPkg/BoardMtOlympus/logo.txt | 11 + .../BoardMtOlympus/postbuild.bat | 101 + .../PurleyOpenBoardPkg/BoardMtOlympus/prebuild.bat | 213 + .../Features/Ipmi/Library/IpmiLibKcs/IpmiLibKcs.c | 369 + .../Ipmi/Library/IpmiLibKcs/IpmiLibKcs.inf | 46 + .../Features/Ipmi/Library/IpmiLibKcs/KcsBmc.c | 491 ++ .../Features/Ipmi/Library/IpmiLibKcs/KcsBmc.h | 214 + .../IpmiPlatformHookLib/IpmiPlatformHookLib.c | 45 + .../IpmiPlatformHookLib/IpmiPlatformHookLib.inf | 35 + .../PurleyOpenBoardPkg/Include/Acpi/GlobalNvs.asi | 288 + .../Include/Acpi/GlobalNvsAreaDef.h | 134 + .../Include/Guid/PchRcVariable.h | 420 + .../Include/Guid/SetupVariable.h | 545 ++ .../Include/IioBifurcationSlotTable.h | 106 + .../Intel/PurleyOpenBoardPkg/Include/Platform.h | 98 + .../PurleyOpenBoardPkg/Include/Ppi/SystemBoard.h | 69 + .../Include/Protocol/PciIovPlatform.h | 76 + .../Intel/PurleyOpenBoardPkg/Include/SetupTable.h | 27 + .../Intel/PurleyOpenBoardPkg/Include/SioRegs.h | 41 + .../PurleyOpenBoardPkg/Pci/PciPlatform/IoApic.h | 28 + .../Pci/PciPlatform/PciIovPlatformPolicy.c | 102 + .../Pci/PciPlatform/PciIovPlatformPolicy.h | 57 + .../Pci/PciPlatform/PciPlatform.c | 189 + .../Pci/PciPlatform/PciPlatform.h | 207 + .../Pci/PciPlatform/PciPlatform.inf | 78 + .../Pci/PciPlatform/PciPlatformHooks.c | 533 ++ .../Pci/PciPlatform/PciPlatformHooks.h | 30 + .../Pci/PciPlatform/PciSupportLib.c | 109 + .../Pci/PciPlatform/PciSupportLib.h | 50 + Platform/Intel/PurleyOpenBoardPkg/PlatPkg.dec | 146 + .../Policy/IioUdsDataDxe/IioUdsDataDxe.c | 92 + .../Policy/IioUdsDataDxe/IioUdsDataDxe.h | 87 + .../Policy/IioUdsDataDxe/IioUdsDataDxe.inf | 44 + .../SiliconPolicyInitLib/SiliconPolicyInitLib.c | 136 + .../SiliconPolicyInitLib/SiliconPolicyInitLib.inf | 47 + .../SiliconPolicyUpdateLib/PchPolicyUpdateUsb.c | 105 + .../SiliconPolicyUpdateLib.c | 665 ++ .../SiliconPolicyUpdateLib.inf | 62 + .../Policy/PlatformCpuPolicy/PlatformCpuPolicy.c | 661 ++ .../Policy/PlatformCpuPolicy/PlatformCpuPolicy.inf | 88 + .../Policy/S3NvramSave/S3NvramSave.c | 262 + .../Policy/S3NvramSave/S3NvramSave.h | 37 + .../Policy/S3NvramSave/S3NvramSave.inf | 66 + .../Policy/SystemBoard/SystemBoardCommon.c | 631 ++ .../Policy/SystemBoard/SystemBoardPei.c | 261 + .../Policy/SystemBoard/SystemBoardPei.h | 188 + .../Policy/SystemBoard/SystemBoardPei.inf | 84 + 168 files changed, 47531 insertions(+) create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/AmlOffsetTable.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxeDsdt.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt.inf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CommonPlatform.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.asl create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/HostBus.asl create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieHotPlugGpeHandler.asl create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieRootPortHotPlug.asl create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Mother.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Os.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC00.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC01.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC02.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC03.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC04.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC05.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC06.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC06Ejd.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC07.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC08.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC09.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC10.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC11.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC12.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC12Ejd.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC13.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC14.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC15.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC16.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC17.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC18.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC18Ejd.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC19.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC20.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC21.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC22.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC23.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC24.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC25.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC26.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC27.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC28.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC29.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC30.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC31.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC32.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC33.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC34.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC35.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC36.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC37.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC38.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC39.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC40.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC41.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC42.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC43.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC44.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC45.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC46.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC47.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Pch.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchApic.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci1.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci2.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchGbe.asl create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchLpc.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchSata.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchXhci.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciCrs.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciIrq.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHp.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHpDev.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieNonHpDev.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieSeg.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGpe.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformPciTree_WFP.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck1Ejd.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck2Ejd.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck3Ejd.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore0.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore1.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore2.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore3.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/WFPPlatform.asl create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/GitEdk2MinMtOlympus.bat create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BasePlatformHookLib/BasePlatformHookLib.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BasePlatformHookLib/BasePlatformHookLib.inf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/DxeMtOlympusAcpiTableLib.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmMtOlympusAcpiEnableLib.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/AllLanesEparam.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/GpioTable.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/IioBifur.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPostMemLib.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPostMemLib.inf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPreMemLib.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPreMemLib.inf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusDetect.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitLib.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitPostMemLib.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitPreMemLib.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/UsbOC.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.dsc create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.fdf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgBuildOption.dsc create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgConfig.dsc create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgPcd.dsc create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/StructureConfig.dsc create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/bld.bat create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/logo.txt create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/postbuild.bat create mode 100644 Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/prebuild.bat create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/IpmiLibKcs.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/IpmiLibKcs.inf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/KcsBmc.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/KcsBmc.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Include/Acpi/GlobalNvs.asi create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Include/Guid/PchRcVariable.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Include/Guid/SetupVariable.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Include/IioBifurcationSlotTable.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Include/Platform.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Include/Ppi/SystemBoard.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Include/Protocol/PciIovPlatform.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Include/SetupTable.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Include/SioRegs.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/IoApic.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciIovPlatformPolicy.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciIovPlatformPolicy.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatform.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatform.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatform.inf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatformHooks.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatformHooks.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciSupportLib.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciSupportLib.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/PlatPkg.dec create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/IioUdsDataDxe/IioUdsDataDxe.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/IioUdsDataDxe/IioUdsDataDxe.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/IioUdsDataDxe/IioUdsDataDxe.inf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicyInitLib/SiliconPolicyInitLib.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicyInitLib/SiliconPolicyInitLib.inf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicyUpdateLib/PchPolicyUpdateUsb.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLib.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLib.inf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/PlatformCpuPolicy/PlatformCpuPolicy.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/PlatformCpuPolicy/PlatformCpuPolicy.inf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/S3NvramSave/S3NvramSave.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/S3NvramSave/S3NvramSave.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/S3NvramSave/S3NvramSave.inf create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/SystemBoardCommon.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/SystemBoardPei.c create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/SystemBoardPei.h create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/SystemBoardPei.inf diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/AmlOffsetTable.c b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/AmlOffsetTable.c new file mode 100644 index 0000000000..5d8714f589 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/AmlOffsetTable.c @@ -0,0 +1,284 @@ +/* + * + * Intel ACPI Component Architecture + * + * + */ +#ifndef __AML_OFFSET_TABLE_H +#define __AML_OFFSET_TABLE_H + +typedef struct { + char *Pathname; /* Full pathname (from root) to the object */ + unsigned short ParentOpcode; /* AML opcode for the parent object */ + unsigned long NamesegOffset; /* Offset of last nameseg in the parent namepath */ + unsigned char Opcode; /* AML opcode for the data */ + unsigned long Offset; /* Offset for the data */ + unsigned long long Value; /* Original value of the data (as applicable) */ +} AML_OFFSET_TABLE_ENTRY; + +#endif /* __AML_OFFSET_TABLE_H */ + +/* + * Information specific to the supported object types: + * + * Integers: + * Opcode is the integer prefix, indicates length of the data + * (One of: BYTE, WORD, DWORD, QWORD, ZERO, ONE, ONES) + * Offset points to the actual integer data + * Value is the existing value in the AML + * + * Packages: + * Opcode is the package or var_package opcode + * Offset points to the package opcode + * Value is the package element count + * + * Operation Regions: + * Opcode is the address integer prefix, indicates length of the data + * Offset points to the region address + * Value is the existing address value in the AML + * + * Control Methods: + * Offset points to the method flags byte + * Value is the existing flags value in the AML + * + * Processors: + * Offset points to the first byte of the PBlock Address + * + * Resource Descriptors: + * Opcode is the descriptor type + * Offset points to the start of the descriptor + * + * Scopes/Devices/ThermalZones: + * Nameseg offset only + */ +AML_OFFSET_TABLE_ENTRY DSDT_PLATWFP__OffsetTable[] = +{ + {"PSYS", 0x5B80, 0x0000038B, 0x0C, 0x00000391, 0x0000000030584946}, /* OPERATIONREGION */ + {"_SB_.PC00.FIX1", 0x0011, 0x00000000, 0x88, 0x0000D187, 0x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC00.FIX2", 0x0011, 0x00000000, 0x88, 0x0000D1AF, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC00.FIX5", 0x0011, 0x00000000, 0x87, 0x0000D1BF, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC00.FIX3", 0x0011, 0x00000000, 0x87, 0x0000D20D, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC00.FIX4", 0x0011, 0x00000000, 0x8A, 0x0000D227, 0x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC01.FIX1", 0x0011, 0x00000000, 0x88, 0x0000EA9B, 0x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC01.FIX5", 0x0011, 0x00000000, 0x87, 0x0000EAAB, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC01.FIX2", 0x0011, 0x00000000, 0x88, 0x0000EAC5, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC01.FIX6", 0x0011, 0x00000000, 0x88, 0x0000EAD5, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC01.FIX7", 0x0011, 0x00000000, 0x88, 0x0000EAE5, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC01.FIX3", 0x0011, 0x00000000, 0x87, 0x0000EAF5, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC01.FIX4", 0x0011, 0x00000000, 0x8A, 0x0000EB0F, 0x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC01.BR1A.MCTL", 0x5B80, 0x0000EB91, 0x0C, 0x0000EB97, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC01.BR1B.MCTL", 0x5B80, 0x0000F3B2, 0x0C, 0x0000F3B8, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC01.BR1C.MCTL", 0x5B80, 0x0000FBD3, 0x0C, 0x0000FBD9, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC01.BR1D.MCTL", 0x5B80, 0x000103F4, 0x0C, 0x000103FA, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC02.FIX1", 0x0011, 0x00000000, 0x88, 0x00010E93, 0x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC02.FIX5", 0x0011, 0x00000000, 0x87, 0x00010EA3, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC02.FIX2", 0x0011, 0x00000000, 0x88, 0x00010EBD, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC02.FIX6", 0x0011, 0x00000000, 0x88, 0x00010ECD, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC02.FIX7", 0x0011, 0x00000000, 0x88, 0x00010EDD, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC02.FIX3", 0x0011, 0x00000000, 0x87, 0x00010EED, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC02.FIX4", 0x0011, 0x00000000, 0x8A, 0x00010F07, 0x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC02.BR2A.MCTL", 0x5B80, 0x00010F89, 0x0C, 0x00010F8F, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC02.BR2B.MCTL", 0x5B80, 0x00011969, 0x0C, 0x0001196F, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC02.BR2C.MCTL", 0x5B80, 0x0001218A, 0x0C, 0x00012190, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC02.BR2D.MCTL", 0x5B80, 0x000129AB, 0x0C, 0x000129B1, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC03.FIX1", 0x0011, 0x00000000, 0x88, 0x000133E4, 0x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC03.FIX5", 0x0011, 0x00000000, 0x87, 0x000133F4, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC03.FIX2", 0x0011, 0x00000000, 0x88, 0x0001340E, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC03.FIX6", 0x0011, 0x00000000, 0x88, 0x0001341E, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC03.FIX7", 0x0011, 0x00000000, 0x88, 0x0001342E, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC03.FIX3", 0x0011, 0x00000000, 0x87, 0x0001343E, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC03.FIX4", 0x0011, 0x00000000, 0x8A, 0x00013458, 0x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC03.BR3A.MCTL", 0x5B80, 0x000134DA, 0x0C, 0x000134E0, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC03.BR3B.MCTL", 0x5B80, 0x00013CFB, 0x0C, 0x00013D01, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC03.BR3C.MCTL", 0x5B80, 0x0001451C, 0x0C, 0x00014522, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC03.BR3D.MCTL", 0x5B80, 0x00014D3D, 0x0C, 0x00014D43, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC04.FIX1", 0x0011, 0x00000000, 0x88, 0x000156F0, 0x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC04.FIX5", 0x0011, 0x00000000, 0x87, 0x00015700, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC04.FIX2", 0x0011, 0x00000000, 0x88, 0x0001571A, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC04.FIX6", 0x0011, 0x00000000, 0x88, 0x0001572A, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC04.FIX7", 0x0011, 0x00000000, 0x88, 0x0001573A, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC04.FIX3", 0x0011, 0x00000000, 0x87, 0x0001574A, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC04.FIX4", 0x0011, 0x00000000, 0x8A, 0x00015764, 0x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC04.MCP0.MCTL", 0x5B80, 0x000157E6, 0x0C, 0x000157EC, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC05.FIX1", 0x0011, 0x00000000, 0x88, 0x0001612D, 0x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC05.FIX5", 0x0011, 0x00000000, 0x87, 0x0001613D, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC05.FIX2", 0x0011, 0x00000000, 0x88, 0x00016157, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC05.FIX6", 0x0011, 0x00000000, 0x88, 0x00016167, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC05.FIX7", 0x0011, 0x00000000, 0x88, 0x00016177, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC05.FIX3", 0x0011, 0x00000000, 0x87, 0x00016187, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC05.FIX4", 0x0011, 0x00000000, 0x8A, 0x000161A1, 0x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC05.MCP1.MCTL", 0x5B80, 0x00016223, 0x0C, 0x00016229, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC06.FIX1", 0x0011, 0x00000000, 0x88, 0x00016FD9, 0x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC06.FIX5", 0x0011, 0x00000000, 0x87, 0x00016FE9, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC06.FIX2", 0x0011, 0x00000000, 0x88, 0x00017003, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC06.FIX6", 0x0011, 0x00000000, 0x88, 0x00017013, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC06.FIX7", 0x0011, 0x00000000, 0x88, 0x00017023, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC06.FIX3", 0x0011, 0x00000000, 0x87, 0x00017033, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC06.FIX4", 0x0011, 0x00000000, 0x8A, 0x0001704D, 0x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC06.QRP0.MCTL", 0x5B80, 0x00017149, 0x0C, 0x0001714F, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC07.FIX1", 0x0011, 0x00000000, 0x88, 0x00017BC4, 0x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC07.FIX5", 0x0011, 0x00000000, 0x87, 0x00017BD4, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC07.FIX2", 0x0011, 0x00000000, 0x88, 0x00017BEE, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC07.FIX6", 0x0011, 0x00000000, 0x88, 0x00017BFE, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC07.FIX7", 0x0011, 0x00000000, 0x88, 0x00017C0E, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC07.FIX3", 0x0011, 0x00000000, 0x87, 0x00017C1E, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC07.FIX4", 0x0011, 0x00000000, 0x8A, 0x00017C38, 0x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC07.QR1A.MCTL", 0x5B80, 0x00017CCA, 0x0C, 0x00017CD0, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC07.QR1B.MCTL", 0x5B80, 0x00018506, 0x0C, 0x0001850C, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC07.QR1C.MCTL", 0x5B80, 0x00018D42, 0x0C, 0x00018D48, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC07.QR1D.MCTL", 0x5B80, 0x0001957E, 0x0C, 0x00019584, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC08.FIX1", 0x0011, 0x00000000, 0x88, 0x0001A04E, 0x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC08.FIX5", 0x0011, 0x00000000, 0x87, 0x0001A05E, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC08.FIX2", 0x0011, 0x00000000, 0x88, 0x0001A078, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC08.FIX6", 0x0011, 0x00000000, 0x88, 0x0001A088, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC08.FIX7", 0x0011, 0x00000000, 0x88, 0x0001A098, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC08.FIX3", 0x0011, 0x00000000, 0x87, 0x0001A0A8, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC08.FIX4", 0x0011, 0x00000000, 0x8A, 0x0001A0C2, 0x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC08.QR2A.MCTL", 0x5B80, 0x0001A154, 0x0C, 0x0001A15A, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC08.QR2B.MCTL", 0x5B80, 0x0001A990, 0x0C, 0x0001A996, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC08.QR2C.MCTL", 0x5B80, 0x0001B1CC, 0x0C, 0x0001B1D2, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC08.QR2D.MCTL", 0x5B80, 0x0001BA08, 0x0C, 0x0001BA0E, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC09.FIX1", 0x0011, 0x00000000, 0x88, 0x0001C461, 0x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC09.FIX5", 0x0011, 0x00000000, 0x87, 0x0001C471, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC09.FIX2", 0x0011, 0x00000000, 0x88, 0x0001C48B, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC09.FIX6", 0x0011, 0x00000000, 0x88, 0x0001C49B, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC09.FIX7", 0x0011, 0x00000000, 0x88, 0x0001C4AB, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC09.FIX3", 0x0011, 0x00000000, 0x87, 0x0001C4BB, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC09.FIX4", 0x0011, 0x00000000, 0x8A, 0x0001C4D5, 0x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC09.QR3A.MCTL", 0x5B80, 0x0001C567, 0x0C, 0x0001C56D, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC09.QR3B.MCTL", 0x5B80, 0x0001CDA3, 0x0C, 0x0001CDA9, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC09.QR3C.MCTL", 0x5B80, 0x0001D5DF, 0x0C, 0x0001D5E5, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC09.QR3D.MCTL", 0x5B80, 0x0001DE1B, 0x0C, 0x0001DE21, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC10.FIX1", 0x0011, 0x00000000, 0x88, 0x0001E7EE, 0x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC10.FIX5", 0x0011, 0x00000000, 0x87, 0x0001E7FE, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC10.FIX2", 0x0011, 0x00000000, 0x88, 0x0001E818, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC10.FIX6", 0x0011, 0x00000000, 0x88, 0x0001E828, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC10.FIX7", 0x0011, 0x00000000, 0x88, 0x0001E838, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC10.FIX3", 0x0011, 0x00000000, 0x87, 0x0001E848, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC10.FIX4", 0x0011, 0x00000000, 0x8A, 0x0001E862, 0x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC10.MCP2.MCTL", 0x5B80, 0x0001E8F4, 0x0C, 0x0001E8FA, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC11.FIX1", 0x0011, 0x00000000, 0x88, 0x0001F250, 0x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC11.FIX5", 0x0011, 0x00000000, 0x87, 0x0001F260, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC11.FIX2", 0x0011, 0x00000000, 0x88, 0x0001F27A, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC11.FIX6", 0x0011, 0x00000000, 0x88, 0x0001F28A, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC11.FIX7", 0x0011, 0x00000000, 0x88, 0x0001F29A, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC11.FIX3", 0x0011, 0x00000000, 0x87, 0x0001F2AA, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC11.FIX4", 0x0011, 0x00000000, 0x8A, 0x0001F2C4, 0x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC11.MCP3.MCTL", 0x5B80, 0x0001F356, 0x0C, 0x0001F35C, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC12.FIX1", 0x0011, 0x00000000, 0x88, 0x0002011C, 0x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC12.FIX5", 0x0011, 0x00000000, 0x87, 0x0002012C, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC12.FIX2", 0x0011, 0x00000000, 0x88, 0x00020146, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC12.FIX6", 0x0011, 0x00000000, 0x88, 0x00020156, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC12.FIX7", 0x0011, 0x00000000, 0x88, 0x00020166, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC12.FIX3", 0x0011, 0x00000000, 0x87, 0x00020176, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC12.FIX4", 0x0011, 0x00000000, 0x8A, 0x00020190, 0x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC12.RRP0.MCTL", 0x5B80, 0x0002028C, 0x0C, 0x00020292, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC13.FIX1", 0x0011, 0x00000000, 0x88, 0x00020D07, 0x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC13.FIX5", 0x0011, 0x00000000, 0x87, 0x00020D17, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC13.FIX2", 0x0011, 0x00000000, 0x88, 0x00020D31, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC13.FIX6", 0x0011, 0x00000000, 0x88, 0x00020D41, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC13.FIX7", 0x0011, 0x00000000, 0x88, 0x00020D51, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC13.FIX3", 0x0011, 0x00000000, 0x87, 0x00020D61, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC13.FIX4", 0x0011, 0x00000000, 0x8A, 0x00020D7B, 0x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC13.RR1A.MCTL", 0x5B80, 0x00020E0D, 0x0C, 0x00020E13, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC13.RR1B.MCTL", 0x5B80, 0x00021649, 0x0C, 0x0002164F, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC13.RR1C.MCTL", 0x5B80, 0x00021E85, 0x0C, 0x00021E8B, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC13.RR1D.MCTL", 0x5B80, 0x000226C1, 0x0C, 0x000226C7, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC14.FIX1", 0x0011, 0x00000000, 0x88, 0x0002316F, 0x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC14.FIX5", 0x0011, 0x00000000, 0x87, 0x0002317F, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC14.FIX2", 0x0011, 0x00000000, 0x88, 0x00023199, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC14.FIX6", 0x0011, 0x00000000, 0x88, 0x000231A9, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC14.FIX7", 0x0011, 0x00000000, 0x88, 0x000231B9, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC14.FIX3", 0x0011, 0x00000000, 0x87, 0x000231C9, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC14.FIX4", 0x0011, 0x00000000, 0x8A, 0x000231E3, 0x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC14.RR2A.MCTL", 0x5B80, 0x00023275, 0x0C, 0x0002327B, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC14.RR2B.MCTL", 0x5B80, 0x00023AB1, 0x0C, 0x00023AB7, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC14.RR2C.MCTL", 0x5B80, 0x000242ED, 0x0C, 0x000242F3, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC14.RR2D.MCTL", 0x5B80, 0x00024B29, 0x0C, 0x00024B2F, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC15.FIX1", 0x0011, 0x00000000, 0x88, 0x00025582, 0x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC15.FIX5", 0x0011, 0x00000000, 0x87, 0x00025592, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC15.FIX2", 0x0011, 0x00000000, 0x88, 0x000255AC, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC15.FIX6", 0x0011, 0x00000000, 0x88, 0x000255BC, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC15.FIX7", 0x0011, 0x00000000, 0x88, 0x000255CC, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC15.FIX3", 0x0011, 0x00000000, 0x87, 0x000255DC, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC15.FIX4", 0x0011, 0x00000000, 0x8A, 0x000255F6, 0x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC15.RR3A.MCTL", 0x5B80, 0x00025688, 0x0C, 0x0002568E, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC15.RR3B.MCTL", 0x5B80, 0x00025EC4, 0x0C, 0x00025ECA, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC15.RR3C.MCTL", 0x5B80, 0x00026700, 0x0C, 0x00026706, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC15.RR3D.MCTL", 0x5B80, 0x00026F3C, 0x0C, 0x00026F42, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC16.FIX1", 0x0011, 0x00000000, 0x88, 0x0002790F, 0x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC16.FIX5", 0x0011, 0x00000000, 0x87, 0x0002791F, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC16.FIX2", 0x0011, 0x00000000, 0x88, 0x00027939, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC16.FIX6", 0x0011, 0x00000000, 0x88, 0x00027949, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC16.FIX7", 0x0011, 0x00000000, 0x88, 0x00027959, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC16.FIX3", 0x0011, 0x00000000, 0x87, 0x00027969, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC16.FIX4", 0x0011, 0x00000000, 0x8A, 0x00027983, 0x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC16.MCP4.MCTL", 0x5B80, 0x00027A15, 0x0C, 0x00027A1B, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC17.FIX1", 0x0011, 0x00000000, 0x88, 0x00028371, 0x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC17.FIX5", 0x0011, 0x00000000, 0x87, 0x00028381, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC17.FIX2", 0x0011, 0x00000000, 0x88, 0x0002839B, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC17.FIX6", 0x0011, 0x00000000, 0x88, 0x000283AB, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC17.FIX7", 0x0011, 0x00000000, 0x88, 0x000283BB, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC17.FIX3", 0x0011, 0x00000000, 0x87, 0x000283CB, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC17.FIX4", 0x0011, 0x00000000, 0x8A, 0x000283E5, 0x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC17.MCP5.MCTL", 0x5B80, 0x00028477, 0x0C, 0x0002847D, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC18.FIX1", 0x0011, 0x00000000, 0x88, 0x0002923D, 0x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC18.FIX5", 0x0011, 0x00000000, 0x87, 0x0002924D, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC18.FIX2", 0x0011, 0x00000000, 0x88, 0x00029267, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC18.FIX6", 0x0011, 0x00000000, 0x88, 0x00029277, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC18.FIX7", 0x0011, 0x00000000, 0x88, 0x00029287, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC18.FIX3", 0x0011, 0x00000000, 0x87, 0x00029297, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC18.FIX4", 0x0011, 0x00000000, 0x8A, 0x000292B1, 0x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC18.SRP0.MCTL", 0x5B80, 0x000293AD, 0x0C, 0x000293B3, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC19.FIX1", 0x0011, 0x00000000, 0x88, 0x00029E28, 0x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC19.FIX5", 0x0011, 0x00000000, 0x87, 0x00029E38, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC19.FIX2", 0x0011, 0x00000000, 0x88, 0x00029E52, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC19.FIX6", 0x0011, 0x00000000, 0x88, 0x00029E62, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC19.FIX7", 0x0011, 0x00000000, 0x88, 0x00029E72, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC19.FIX3", 0x0011, 0x00000000, 0x87, 0x00029E82, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC19.FIX4", 0x0011, 0x00000000, 0x8A, 0x00029E9C, 0x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC19.SR1A.MCTL", 0x5B80, 0x00029F2E, 0x0C, 0x00029F34, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC19.SR1B.MCTL", 0x5B80, 0x0002A76A, 0x0C, 0x0002A770, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC19.SR1C.MCTL", 0x5B80, 0x0002AFA6, 0x0C, 0x0002AFAC, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC19.SR1D.MCTL", 0x5B80, 0x0002B7E2, 0x0C, 0x0002B7E8, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC20.FIX1", 0x0011, 0x00000000, 0x88, 0x0002C2B2, 0x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC20.FIX5", 0x0011, 0x00000000, 0x87, 0x0002C2C2, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC20.FIX2", 0x0011, 0x00000000, 0x88, 0x0002C2DC, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC20.FIX6", 0x0011, 0x00000000, 0x88, 0x0002C2EC, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC20.FIX7", 0x0011, 0x00000000, 0x88, 0x0002C2FC, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC20.FIX3", 0x0011, 0x00000000, 0x87, 0x0002C30C, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC20.FIX4", 0x0011, 0x00000000, 0x8A, 0x0002C326, 0x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC20.SR2A.MCTL", 0x5B80, 0x0002C3B8, 0x0C, 0x0002C3BE, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC20.SR2B.MCTL", 0x5B80, 0x0002CBF4, 0x0C, 0x0002CBFA, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC20.SR2C.MCTL", 0x5B80, 0x0002D430, 0x0C, 0x0002D436, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC20.SR2D.MCTL", 0x5B80, 0x0002DC6C, 0x0C, 0x0002DC72, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC21.FIX1", 0x0011, 0x00000000, 0x88, 0x0002E6C5, 0x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC21.FIX5", 0x0011, 0x00000000, 0x87, 0x0002E6D5, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC21.FIX2", 0x0011, 0x00000000, 0x88, 0x0002E6EF, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC21.FIX6", 0x0011, 0x00000000, 0x88, 0x0002E6FF, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC21.FIX7", 0x0011, 0x00000000, 0x88, 0x0002E70F, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC21.FIX3", 0x0011, 0x00000000, 0x87, 0x0002E71F, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC21.FIX4", 0x0011, 0x00000000, 0x8A, 0x0002E739, 0x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC21.SR3A.MCTL", 0x5B80, 0x0002E7CB, 0x0C, 0x0002E7D1, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC21.SR3B.MCTL", 0x5B80, 0x0002F007, 0x0C, 0x0002F00D, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC21.SR3C.MCTL", 0x5B80, 0x0002F843, 0x0C, 0x0002F849, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC21.SR3D.MCTL", 0x5B80, 0x0003007F, 0x0C, 0x00030085, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC22.FIX1", 0x0011, 0x00000000, 0x88, 0x00030A52, 0x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC22.FIX5", 0x0011, 0x00000000, 0x87, 0x00030A62, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC22.FIX2", 0x0011, 0x00000000, 0x88, 0x00030A7C, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC22.FIX6", 0x0011, 0x00000000, 0x88, 0x00030A8C, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC22.FIX7", 0x0011, 0x00000000, 0x88, 0x00030A9C, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC22.FIX3", 0x0011, 0x00000000, 0x87, 0x00030AAC, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC22.FIX4", 0x0011, 0x00000000, 0x8A, 0x00030AC6, 0x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC22.MCP6.MCTL", 0x5B80, 0x00030B58, 0x0C, 0x00030B5E, 0x0000000038584946}, /* OPERATIONREGION */ + {"_SB_.PC23.FIX1", 0x0011, 0x00000000, 0x88, 0x000314B4, 0x0000000000000000}, /* WORDBUSNUMBER */ + {"_SB_.PC23.FIX5", 0x0011, 0x00000000, 0x87, 0x000314C4, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC23.FIX2", 0x0011, 0x00000000, 0x88, 0x000314DE, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC23.FIX6", 0x0011, 0x00000000, 0x88, 0x000314EE, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC23.FIX7", 0x0011, 0x00000000, 0x88, 0x000314FE, 0x0000000000000000}, /* WORDIO */ + {"_SB_.PC23.FIX3", 0x0011, 0x00000000, 0x87, 0x0003150E, 0x0000000000000000}, /* DWORDMEMORY */ + {"_SB_.PC23.FIX4", 0x0011, 0x00000000, 0x8A, 0x00031528, 0x0000000000000000}, /* QWORDMEMORY */ + {"_SB_.PC23.MCP7.MCTL", 0x5B80, 0x000315BA, 0x0C, 0x000315C0, 0x0000000038584946}, /* OPERATIONREGION */ + {NULL,0,0,0,0,0} /* Table terminator */ +}; + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c new file mode 100644 index 0000000000..b69bd8ace8 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c @@ -0,0 +1,552 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "BoardAcpiDxe.h" + +EFI_STATUS +PatchDsdtTable ( + IN OUT EFI_ACPI_COMMON_HEADER *Table + ); + +#pragma optimize("",off) + +BIOS_ACPI_PARAM *mAcpiParameter; + +EFI_IIO_UDS_PROTOCOL *mIioUds; + +UINT32 mNumOfBitShift; +BOOLEAN mForceX2ApicId; +BOOLEAN mX2ApicEnabled; + +struct SystemMemoryMapHob *mSystemMemoryMap; + +SOCKET_MP_LINK_CONFIGURATION mSocketMpLinkConfiguration; +SOCKET_IIO_CONFIGURATION mSocketIioConfiguration; +SOCKET_POWERMANAGEMENT_CONFIGURATION mSocketPowermanagementConfiguration; + +BOOLEAN mFirstNotify; +PCH_RC_CONFIGURATION mPchRcConfiguration; + +UINT8 mKBPresent = 0; +UINT8 mMousePresent = 0; + +/** + + Locate the first instance of a protocol. If the protocol requested is an + FV protocol, then it will return the first FV that contains the ACPI table + storage file. + + @param Protocol - The protocol to find. + Instance - Return pointer to the first instance of the protocol. + Type - The type of protocol to locate. + + @retval EFI_SUCCESS - The function completed successfully. + @retval EFI_NOT_FOUND - The protocol could not be located. + @retval EFI_OUT_OF_RESOURCES - There are not enough resources to find the protocol. + +**/ +EFI_STATUS +LocateSupportProtocol ( + IN EFI_GUID *Protocol, + IN EFI_GUID *gEfiAcpiMultiTableStorageGuid, + OUT VOID **Instance, + IN UINT32 Type + ) +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + UINTN NumberOfHandles; + EFI_FV_FILETYPE FileType; + UINT32 FvStatus; + EFI_FV_FILE_ATTRIBUTES Attributes; + UINTN Size; + UINTN Index; + + FvStatus = 0; + // + // Locate protocol. + // + Status = gBS->LocateHandleBuffer ( + ByProtocol, + Protocol, + NULL, + &NumberOfHandles, + &HandleBuffer + ); + if (EFI_ERROR (Status)) { + // + // Defined errors at this time are not found and out of resources. + // + return Status; + } + // + // Looking for FV with ACPI storage file + // + for (Index = 0; Index < NumberOfHandles; Index++) { + // + // Get the protocol on this handle + // This should not fail because of LocateHandleBuffer + // + Status = gBS->HandleProtocol ( + HandleBuffer[Index], + Protocol, + Instance + ); + ASSERT (!EFI_ERROR (Status)); + + if (!Type) { + // + // Not looking for the FV protocol, so find the first instance of the + // protocol. There should not be any errors because our handle buffer + // should always contain at least one or LocateHandleBuffer would have + // returned not found. + // + break; + } + // + // See if it has the ACPI storage file + // + Status = ((EFI_FIRMWARE_VOLUME2_PROTOCOL *) (*Instance))->ReadFile ( + *Instance, + gEfiAcpiMultiTableStorageGuid, + NULL, + &Size, + &FileType, + &Attributes, + &FvStatus + ); + + // + // If we found it, then we are done + // + if (!EFI_ERROR (Status)) { + break; + } + } + // + // Our exit status is determined by the success of the previous operations + // If the protocol was found, Instance already points to it. + // + // + // Free any allocated buffers + // + gBS->FreePool (HandleBuffer); + + return Status; +} + +/** + + GC_TODO: add routine description + + @param None + + @retval EFI_SUCCESS - GC_TODO: add retval description + +**/ +EFI_STATUS +PlatformHookInit ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS AcpiParameterAddr; + UINT32 RegEax; + UINT32 RegEbx; + UINT32 RegEcx; + UINT32 RegEdx; + + CopyMem (&mSocketMpLinkConfiguration, PcdGetPtr(PcdSocketMpLinkConfigData), sizeof(SOCKET_MP_LINK_CONFIGURATION)); + CopyMem (&mSocketPowermanagementConfiguration, PcdGetPtr(PcdSocketPowerManagementConfigData), sizeof(SOCKET_POWERMANAGEMENT_CONFIGURATION)); + CopyMem (&mSocketIioConfiguration, PcdGetPtr(PcdSocketIioConfigData), sizeof(SOCKET_IIO_CONFIGURATION)); + CopyMem (&mPchRcConfiguration, PcdGetPtr(PcdPchRcConfigurationData), sizeof(PCH_RC_CONFIGURATION)); + + DEBUG ((DEBUG_INFO, "mX2ApicEnabled - 0x%x\n", mX2ApicEnabled)); + DEBUG ((DEBUG_INFO, "mForceX2ApicId - 0x%x\n", mForceX2ApicId)); + + { + UINT32 Index; + + for (Index = 0; Index < 4; Index++) { + AsmCpuidEx(CPUID_EXTENDED_TOPOLOGY, Index, &RegEax, &RegEbx, &RegEcx, &RegEdx); + DEBUG ((DEBUG_INFO, "CPUID(0xB - %d) - 0x%08x.0x%08x.0x%08x.0x%08x\n", Index, RegEax, RegEbx, RegEcx, RegEdx)); + } + } + + // + // Allocate 256 runtime memory to pass ACPI parameter + // This Address must be < 4G because we only have 32bit in the dsdt + // + AcpiParameterAddr = 0xffffffff; + Status = gBS->AllocatePages ( + AllocateMaxAddress, + EfiACPIMemoryNVS, + EFI_SIZE_TO_PAGES (sizeof(BIOS_ACPI_PARAM)), + &AcpiParameterAddr + ); + ASSERT_EFI_ERROR (Status); + mAcpiParameter = (BIOS_ACPI_PARAM *)AcpiParameterAddr; + + DEBUG ((EFI_D_ERROR, "ACPI Parameter Block Address: 0x%X\n", mAcpiParameter)); + PcdSet64 (PcdAcpiGnvsAddress, (UINT64)(UINTN)mAcpiParameter); + + ZeroMem (mAcpiParameter, sizeof (BIOS_ACPI_PARAM)); + mAcpiParameter->PlatformId = 0; +#if MAX_SOCKET > 4 + mAcpiParameter->IoApicEnable = PcdGet32 (PcdPcIoApicEnable); +#else + mAcpiParameter->IoApicEnable = (PcdGet32 (PcdPcIoApicEnable) << 1) | 1; +#endif + DEBUG((EFI_D_ERROR, "io apic settings:%d\n", mAcpiParameter->IoApicEnable)); + + AsmCpuid (CPUID_VERSION_INFO, &RegEax, &RegEbx, &RegEcx, &RegEdx); + mAcpiParameter->ProcessorId = (RegEax & 0xFFFF0); + + // support up to 64 threads/socket + AsmCpuidEx(CPUID_EXTENDED_TOPOLOGY, 1, &mNumOfBitShift, NULL, NULL, NULL); + mNumOfBitShift &= 0x1F; + + // Set the bit shift value for CPU SKU + mAcpiParameter->CpuSkuNumOfBitShift = (UINT8) mNumOfBitShift; + + mAcpiParameter->ProcessorApicIdBase[0] = (UINT32) (0 << mNumOfBitShift); + mAcpiParameter->ProcessorApicIdBase[1] = (UINT32) (1 << mNumOfBitShift); + mAcpiParameter->ProcessorApicIdBase[2] = (UINT32) (2 << mNumOfBitShift); + mAcpiParameter->ProcessorApicIdBase[3] = (UINT32) (3 << mNumOfBitShift); + mAcpiParameter->ProcessorApicIdBase[4] = (UINT32) (4 << mNumOfBitShift); + mAcpiParameter->ProcessorApicIdBase[5] = (UINT32) (5 << mNumOfBitShift); + mAcpiParameter->ProcessorApicIdBase[6] = (UINT32) (6 << mNumOfBitShift); + mAcpiParameter->ProcessorApicIdBase[7] = (UINT32) (7 << mNumOfBitShift); + + if(mForceX2ApicId) { + mAcpiParameter->ProcessorApicIdBase[0] = 0x7F00; + mAcpiParameter->ProcessorApicIdBase[1] = 0x7F20; + mAcpiParameter->ProcessorApicIdBase[2] = 0x7F40; + mAcpiParameter->ProcessorApicIdBase[3] = 0x7F60; + mAcpiParameter->ProcessorApicIdBase[4] = 0x7F80; + mAcpiParameter->ProcessorApicIdBase[5] = 0x7Fa0; + mAcpiParameter->ProcessorApicIdBase[6] = 0x7Fc0; + mAcpiParameter->ProcessorApicIdBase[7] = 0x7Fe0; + + if (mNumOfBitShift == 4) { + mAcpiParameter->ProcessorApicIdBase[0] = 0x7F00; + mAcpiParameter->ProcessorApicIdBase[1] = 0x7F10; + mAcpiParameter->ProcessorApicIdBase[2] = 0x7F20; + mAcpiParameter->ProcessorApicIdBase[3] = 0x7F30; + mAcpiParameter->ProcessorApicIdBase[4] = 0x7F40; + mAcpiParameter->ProcessorApicIdBase[5] = 0x7F50; + mAcpiParameter->ProcessorApicIdBase[6] = 0x7F60; + mAcpiParameter->ProcessorApicIdBase[7] = 0x7F70; + } else if(mNumOfBitShift == 6) { + mAcpiParameter->ProcessorApicIdBase[0] = 0x7E00; + mAcpiParameter->ProcessorApicIdBase[1] = 0x7E20; + mAcpiParameter->ProcessorApicIdBase[2] = 0x7E40; + mAcpiParameter->ProcessorApicIdBase[3] = 0x7E60; + mAcpiParameter->ProcessorApicIdBase[4] = 0x7E80; + mAcpiParameter->ProcessorApicIdBase[5] = 0x7Ea0; + mAcpiParameter->ProcessorApicIdBase[6] = 0x7Ec0; + mAcpiParameter->ProcessorApicIdBase[7] = 0x7Ee0; + } + } + + // + // If SNC is enabled, and NumOfCluster is 2, set the ACPI variable for PXM value + // + if(mIioUds->IioUdsPtr->SystemStatus.OutSncEn && (mIioUds->IioUdsPtr->SystemStatus.OutNumOfCluster == 2)){ + mAcpiParameter->SncAnd2Cluster = 1; + } else { + mAcpiParameter->SncAnd2Cluster = 0; + } + + mAcpiParameter->MmCfg = (UINT32)mIioUds->IioUdsPtr->PlatformData.PciExpressBase; + mAcpiParameter->TsegSize = (UINT32)(mIioUds->IioUdsPtr->PlatformData.MemTsegSize >> 20); + + return EFI_SUCCESS; +} + +/** + + This function will update any runtime platform specific information. + This currently includes: + Setting OEM table values, ID, table ID, creator ID and creator revision. + Enabling the proper processor entries in the APIC tables. + + @param Table - The table to update + + @retval EFI_SUCCESS - The function completed successfully. + +**/ +EFI_STATUS +PlatformUpdateTables ( + IN OUT EFI_ACPI_COMMON_HEADER *Table, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ) +{ + EFI_STATUS Status; + + Status = EFI_SUCCESS; + + // + // By default, a table belongs in all ACPI table versions published. + // Some tables will override this because they have different versions of the table. + // + *Version = EFI_ACPI_TABLE_VERSION_2_0; + // + // Update the processors in the APIC table + // + switch (Table->Signature) { + + case EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE: + // + // Patch the memory resource + // + Status = PatchDsdtTable(Table); + break; + + default: + ASSERT(FALSE); + break; + } + // + // + // Update the hardware signature in the FACS structure + // + // + // + return Status; +} + + + +/** + + GC_TODO: Add function description + + @param Event - GC_TODO: add argument description + @param Context - GC_TODO: add argument description + + @retval GC_TODO: add return values + +**/ +STATIC +VOID +EFIAPI +OnReadyToBoot ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + UINT32 RegEax; + UINT32 RegEbx; + UINT32 RegEcx; + UINT32 RegEdx; + + if (mFirstNotify) { + return ; + } + + mFirstNotify = TRUE; + + CopyMem (&mSocketIioConfiguration, PcdGetPtr(PcdSocketIioConfigData), sizeof(SOCKET_IIO_CONFIGURATION)); + CopyMem (&mSocketPowermanagementConfiguration,PcdGetPtr(PcdSocketPowerManagementConfigData), sizeof(SOCKET_POWERMANAGEMENT_CONFIGURATION)); + CopyMem (&mPchRcConfiguration, PcdGetPtr(PcdPchRcConfigurationData), sizeof(PCH_RC_CONFIGURATION)); + + // CpuPm.Asl: External (CSEN, FieldUnitObj) + mAcpiParameter->CStateEnable = !mSocketPowermanagementConfiguration.ProcessorAutonomousCstateEnable; + // CpuPm.Asl: External (C3EN, FieldUnitObj) + mAcpiParameter->C3Enable = mSocketPowermanagementConfiguration.C3Enable; + // CpuPm.Asl: External (C6EN, FieldUnitObj) + if (mSocketPowermanagementConfiguration.C6Enable == PPM_AUTO) { + mAcpiParameter->C6Enable = 1; //POR Default = Enabled + } else { + mAcpiParameter->C6Enable = mSocketPowermanagementConfiguration.C6Enable; + } + if(mAcpiParameter->C6Enable && mAcpiParameter->C3Enable) { //C3 and C6 enable are exclusive + mAcpiParameter->C6Enable = 1; + mAcpiParameter->C3Enable = 0; + } + // CpuPm.Asl: External (C7EN, FieldUnitObj) + mAcpiParameter->C7Enable = 0; + // CpuPm.Asl: External (OSCX, FieldUnitObj) + mAcpiParameter->OSCX = mSocketPowermanagementConfiguration.OSCx; + // CpuPm.Asl: External (MWOS, FieldUnitObj) + mAcpiParameter->MonitorMwaitEnable = 1; + // CpuPm.Asl: External (PSEN, FieldUnitObj) + mAcpiParameter->PStateEnable = mSocketPowermanagementConfiguration.ProcessorEistEnable; + // CpuPm.Asl: External (HWAL, FieldUnitObj) + mAcpiParameter->HWAllEnable = 0; //Update in PatchGv3SsdtTable + + mAcpiParameter->KBPresent = mKBPresent; + mAcpiParameter->MousePresent = mMousePresent; + mAcpiParameter->TStateEnable = mSocketPowermanagementConfiguration.TStateEnable; + //Fine grained T state + AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &RegEax, &RegEbx, &RegEcx, &RegEdx); + if ((RegEax & EFI_FINE_GRAINED_CLOCK_MODULATION) && (mSocketPowermanagementConfiguration.OnDieThermalThrottling > 0)){ + mAcpiParameter->TStateFineGrained = 1; + } + if(RegEax & B_CPUID_POWER_MANAGEMENT_EAX_HWP_LVT_INTERRUPT_SUPPORT) { + mAcpiParameter->HwpInterrupt = 1; + } + // CpuPm.Asl: External (HWEN, FieldUnitObj) + mAcpiParameter->HWPMEnable = mSocketPowermanagementConfiguration.ProcessorHWPMEnable; + // CpuPm.Asl: External (ACEN, FieldUnitObj) + mAcpiParameter->AutoCstate = mSocketPowermanagementConfiguration.ProcessorAutonomousCstateEnable; + + mAcpiParameter->EmcaEn = 0; + + mAcpiParameter->PcieAcpiHotPlugEnable = (UINT8) (BOOLEAN) (mSocketIioConfiguration.PcieAcpiHotPlugEnable != 0); + // + // Initialize USB3 mode from setup data + // + // If mode != manual control + // just copy mode from setup + if (mPchRcConfiguration.PchUsbManualMode != 1) { + mAcpiParameter->XhciMode = mPchRcConfiguration.PchUsbManualMode; + } + +} + +/** + + Entry point for Acpi platform driver. + + @param ImageHandle - A handle for the image that is initializing this driver. + @param SystemTable - A pointer to the EFI system table. + + @retval EFI_SUCCESS - Driver initialized successfully. + @retval EFI_LOAD_ERROR - Failed to Initialize or has been loaded. + @retval EFI_OUT_OF_RESOURCES - Could not allocate needed resources. + +**/ +EFI_STATUS +EFIAPI +InstallAcpiBoard ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_STATUS AcpiStatus; + EFI_ACPI_TABLE_PROTOCOL *AcpiTable; + EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol; + INTN Instance; + EFI_ACPI_COMMON_HEADER *CurrentTable; + UINTN TableHandle; + UINT32 FvStatus; + UINT32 Size; + EFI_EVENT Event; + EFI_ACPI_TABLE_VERSION TableVersion; + EFI_HOB_GUID_TYPE *GuidHob; + + mFirstNotify = FALSE; + + TableVersion = EFI_ACPI_TABLE_VERSION_NONE; + Instance = 0; + CurrentTable = NULL; + TableHandle = 0; + + // + // Locate the IIO Protocol Interface + // + Status = gBS->LocateProtocol (&gEfiIioUdsProtocolGuid,NULL,&mIioUds); + ASSERT_EFI_ERROR (Status); + + GuidHob = GetFirstGuidHob (&gEfiMemoryMapGuid); + ASSERT (GuidHob != NULL); + if (GuidHob == NULL) { + return EFI_NOT_FOUND; + } + mSystemMemoryMap = GET_GUID_HOB_DATA(GuidHob); + + PlatformHookInit (); + + // + // Find the AcpiTable protocol + // + Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, &AcpiTable); + ASSERT_EFI_ERROR (Status); + + // + // Locate the firmware volume protocol + // + Status = LocateSupportProtocol ( + &gEfiFirmwareVolume2ProtocolGuid, + &gEfiCallerIdGuid, + &FwVol, + TRUE + ); + ASSERT_EFI_ERROR (Status); + + Status = EFI_SUCCESS; + Instance = 0; + + // + // Read tables from the storage file. + // + while (!EFI_ERROR (Status)) { + CurrentTable = NULL; + + Status = FwVol->ReadSection ( + FwVol, + &gEfiCallerIdGuid, + EFI_SECTION_RAW, + Instance, + &CurrentTable, + (UINTN *) &Size, + &FvStatus + ); + + if (!EFI_ERROR (Status)) { + // + // Allow platform specific code to reject the table or update it + // + { + // + // Perform any table specific updates. + // + AcpiStatus = PlatformUpdateTables (CurrentTable, &TableVersion); + if (!EFI_ERROR (AcpiStatus)) { + // + // Add the table + // + TableHandle = 0; + if (TableVersion != EFI_ACPI_TABLE_VERSION_NONE) { + AcpiStatus = AcpiTable->InstallAcpiTable ( + AcpiTable, + CurrentTable, + CurrentTable->Length, + &TableHandle + ); + } + ASSERT_EFI_ERROR (AcpiStatus); + } + } + // + // Increment the instance + // + Instance++; + } + } + + Status = EfiCreateEventReadyToBootEx( + TPL_NOTIFY, + OnReadyToBoot, + NULL, + &Event + ); + + // + // Finished + // + return EFI_SUCCESS; +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.h b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.h new file mode 100644 index 0000000000..5e4f293844 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.h @@ -0,0 +1,88 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _ACPI_PLATFORM_H_ +#define _ACPI_PLATFORM_H_ + +// +// Statements that include other header files +// +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "Platform.h" +#include "Register/PchRegsUsb.h" +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "Register/PchRegsUsb.h" + +#include +#define EFI_FINE_GRAINED_CLOCK_MODULATION BIT5 +#define B_CPUID_POWER_MANAGEMENT_EAX_HWP_LVT_INTERRUPT_SUPPORT BIT9 + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf new file mode 100644 index 0000000000..c4ec05b15d --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf @@ -0,0 +1,79 @@ +### @file +# +# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +### + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = BoardAcpiDxe + FILE_GUID = F3253A17-2AFE-419E-A5DA-B95A3F7DAB25 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = InstallAcpiBoard + +[Sources] + Dsdt/WFPPlatform.asl + AmlOffsetTable.c + BoardAcpiDxe.c + BoardAcpiDxeDsdt.c + +[Packages] + PurleyOpenBoardPkg/PlatPkg.dec + PurleySktPkg/SocketPkg.dec + PurleyRcPkg/RcPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + LewisburgPkg/PchRcPkg.dec + UefiCpuPkg/UefiCpuPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + +[LibraryClasses] + UefiBootServicesTableLib + UefiDriverEntryPoint + BaseMemoryLib + DebugLib + UefiLib + UefiRuntimeServicesTableLib + HobLib + PcdLib + BoardAcpiTableLib + +[Protocols] + gEfiMpServiceProtocolGuid + gEfiIioUdsProtocolGuid + gEfiGlobalNvsAreaProtocolGuid + gEfiPciIoProtocolGuid + gEfiFirmwareVolume2ProtocolGuid + gEfiAcpiTableProtocolGuid + gEfiPciRootBridgeIoProtocolGuid + +[Guids] + gEfiMemoryMapGuid + +[Pcd] + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData + gOemSkuTokenSpaceGuid.PcdAcpiGnvsAddress + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable + +[Depex] + gEfiAcpiTableProtocolGuid AND + gEfiMpServiceProtocolGuid + +[BuildOptions] + # add -vr and -so to generate offset.h + *_*_*_ASL_FLAGS = -oi -vr -so + + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxeDsdt.c b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxeDsdt.c new file mode 100644 index 0000000000..df4c62403d --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxeDsdt.c @@ -0,0 +1,522 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// +// Statements that include other files +// + +// +// Statements that include other header files +// +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "Register/PchRegsUsb.h" + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include + +extern BOOLEAN mCpuOrderSorted; + +typedef struct { + char *Pathname; /* Full pathname (from root) to the object */ + unsigned short ParentOpcode; /* AML opcode for the parent object */ + unsigned long NamesegOffset; /* Offset of last nameseg in the parent namepath */ + unsigned char Opcode; /* AML opcode for the data */ + unsigned long Offset; /* Offset for the data */ + unsigned long long Value; /* Original value of the data (as applicable) */ +} AML_OFFSET_TABLE_ENTRY; + +extern AML_OFFSET_TABLE_ENTRY *mAmlOffsetTablePointer; +extern AML_OFFSET_TABLE_ENTRY DSDT_PLATWFP__OffsetTable[]; + +#define AML_NAME_OP 0x08 +#define AML_NAME_PREFIX_SIZE 0x06 +#define AML_NAME_DWORD_SIZE 0x0C + +#define MEM_ADDR_SHFT_VAL 26 // For 64 MB granularity + +#pragma pack(1) + +typedef struct { + UINT8 DescriptorType; + UINT16 ResourceLength; + UINT8 ResourceType; + UINT8 Flags; + UINT8 SpecificFlags; + UINT64 Granularity; + UINT64 Minimum; + UINT64 Maximum; + UINT64 TranslationOffset; + UINT64 AddressLength; +} AML_RESOURCE_ADDRESS64; + + +typedef struct { + UINT8 DescriptorType; + UINT16 ResourceLength; + UINT8 ResourceType; + UINT8 Flags; + UINT8 SpecificFlags; + UINT32 Granularity; + UINT32 Minimum; + UINT32 Maximum; + UINT32 TranslationOffset; + UINT32 AddressLength; +} AML_RESOURCE_ADDRESS32; + + +typedef struct { + UINT8 DescriptorType; + UINT16 ResourceLength; + UINT8 ResourceType; + UINT8 Flags; + UINT8 SpecificFlags; + UINT16 Granularity; + UINT16 Minimum; + UINT16 Maximum; + UINT16 TranslationOffset; + UINT16 AddressLength; +} AML_RESOURCE_ADDRESS16; + +#pragma pack() + +#define PCIE_PORT_4_DEV 0x00 +#define PCIE_PORT_5_DEV 0x00 + +#define PORTS_PER_SOCKET 0x0F +#define PCIE_PORT_ALL_FUNC 0x00 + +typedef struct _PCIE_PORT_INFO { + UINT8 Device; + UINT8 Stack; +} PCIE_PORT_INFO; + +#pragma optimize("",off) + +extern BIOS_ACPI_PARAM *mAcpiParameter; + +extern struct SystemMemoryMapHob *mSystemMemoryMap; +extern EFI_IIO_UDS_PROTOCOL *mIioUds; + + +extern SOCKET_MP_LINK_CONFIGURATION mSocketMpLinkConfiguration; +extern SOCKET_IIO_CONFIGURATION mSocketIioConfiguration; +extern SOCKET_POWERMANAGEMENT_CONFIGURATION mSocketPowermanagementConfiguration; + +extern UINT32 mNumOfBitShift; + +AML_OFFSET_TABLE_ENTRY *mAmlOffsetTablePointer = DSDT_PLATWFP__OffsetTable; + +/** + + Update the DSDT table + + @param *TableHeader - The table to be set + + @retval EFI_SUCCESS - DSDT updated + @retval EFI_INVALID_PARAMETER - DSDT not updated + +**/ +EFI_STATUS +PatchDsdtTable ( + IN OUT EFI_ACPI_COMMON_HEADER *Table + ) +{ + PCIE_PORT_INFO PCIEPortDefaults[] = { + // DMI/PCIE 0 + { PCIE_PORT_0_DEV, IIO_CSTACK }, + //IOU0 + { PCIE_PORT_1A_DEV, IIO_PSTACK0 }, + { PCIE_PORT_1B_DEV, IIO_PSTACK0 }, + { PCIE_PORT_1C_DEV, IIO_PSTACK0 }, + { PCIE_PORT_1D_DEV, IIO_PSTACK0 }, + //IOU1 + { PCIE_PORT_2A_DEV, IIO_PSTACK1 }, + { PCIE_PORT_2B_DEV, IIO_PSTACK1 }, + { PCIE_PORT_2C_DEV, IIO_PSTACK1 }, + { PCIE_PORT_2D_DEV, IIO_PSTACK1 }, + //IOU2 + { PCIE_PORT_3A_DEV, IIO_PSTACK2 }, + { PCIE_PORT_3B_DEV, IIO_PSTACK2 }, + { PCIE_PORT_3C_DEV, IIO_PSTACK2 }, + { PCIE_PORT_3D_DEV, IIO_PSTACK2 }, + //MCP0 and MCP1 + { PCIE_PORT_4_DEV, IIO_PSTACK3 }, + { PCIE_PORT_5_DEV, IIO_PSTACK4 } + }; + EFI_STATUS Status; + UINT8 *DsdtPointer; + UINT32 *Signature; + UINT32 Fixes, NodeIndex; + UINT8 Counter; + UINT16 i; // DSDT_PLATEXRP_OffsetTable LUT entries extends beyond 256! + UINT64 MemoryBaseLimit = 0; + UINT64 PciHGPEAddr = 0; + UINT64 BusDevFunc = 0; + UINT64 PcieHpBus = 0; + UINT64 PcieHpDev = 0; + UINT64 PcieHpFunc= 0; + UINT8 PortCount = 0; + UINT8 StackNumBus = 0; + UINT8 StackNumIo = 0; + UINT8 StackNumMem32 = 0; + UINT8 StackNumMem64 = 0; + UINT8 StackNumVgaIo0 = 1; // Start looking for Stack 1 + UINT8 StackNumVgaIo1 = 1; // Start looking for Stack 1 + UINT8 StackNumVgaMmioL = 0; + UINT8 Stack = 0; + UINT8 CurrSkt = 0, CurrStack = 0; + UINT64 IioBusIndex = 0; + UINT8 BusBase = 0, BusLimit = 0; + UINT16 IoBase = 0, IoLimit = 0; + UINT32 MemBase32 = 0, MemLimit32 = 0; + UINT64 MemBase64 = 0, MemLimit64 = 0; + AML_RESOURCE_ADDRESS16 *AmlResourceAddress16Pointer; + AML_RESOURCE_ADDRESS32 *AmlResourceAddress32Pointer; + AML_RESOURCE_ADDRESS64 *AmlResourceAddress64Pointer; + EFI_ACPI_DESCRIPTION_HEADER *TableHeader; + + Status = EFI_SUCCESS; + TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *)Table; + + if (mAmlOffsetTablePointer == NULL) return EFI_INVALID_PARAMETER; + + mAcpiParameter->MemoryBoardBitMask = 0; + + for(Counter = 0; Counter < mSystemMemoryMap->numberEntries; Counter++) { + NodeIndex = mSystemMemoryMap->Element[Counter].NodeId; + if((mAcpiParameter->MemoryBoardBitMask) & (1 << NodeIndex)){ + MemoryBaseLimit = mAcpiParameter->MemoryBoardRange[NodeIndex] + LShiftU64(mSystemMemoryMap->Element[Counter].ElementSize, MEM_ADDR_SHFT_VAL); + mAcpiParameter->MemoryBoardRange[NodeIndex] = MemoryBaseLimit; + } else { + mAcpiParameter->MemoryBoardBitMask |= 1 << NodeIndex; + MemoryBaseLimit = LShiftU64(mSystemMemoryMap->Element[Counter].BaseAddress, 30); + mAcpiParameter->MemoryBoardBase[NodeIndex] = MemoryBaseLimit; + MemoryBaseLimit = LShiftU64((mSystemMemoryMap->Element[Counter].BaseAddress + mSystemMemoryMap->Element[Counter].ElementSize), MEM_ADDR_SHFT_VAL); + mAcpiParameter->MemoryBoardRange[NodeIndex] = MemoryBaseLimit; + } + } + + // + // Mark all spare memory controllers as 1 in MemSpareMask bitmap. + // + mAcpiParameter->MemSpareMask = ~mAcpiParameter->MemoryBoardBitMask; + + mAcpiParameter->IioPresentBitMask = 0; + mAcpiParameter->SocketBitMask = 0; + + for (Counter = 0; Counter < MAX_SOCKET; Counter++) { + if (!mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Counter].Valid) continue; + mAcpiParameter->SocketBitMask |= 1 << Counter; + mAcpiParameter->IioPresentBitMask |= LShiftU64(mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Counter].stackPresentBitmap, (Counter * 8)); + for (Stack = 0; Stack < MAX_IIO_STACK; Stack++) { + mAcpiParameter->BusBase[Counter * MAX_IIO_STACK + Stack] = mIioUds->IioUdsPtr->PlatformData.IIO_resource[Counter].StackRes[Stack].BusBase; + } + } + + PciHGPEAddr = mIioUds->IioUdsPtr->PlatformData.PciExpressBase + 0x188; + BusDevFunc = 0x00; + PcieHpBus = 0; + PcieHpDev = 0; + PcieHpFunc = 0; + + Fixes = 0; + // + // Loop through the AML looking for values that we must fix up. + // + for (i = 0; mAmlOffsetTablePointer[i].Pathname != 0; i++) { + // + // Point to offset in DSDT for current item in AmlOffsetTable. + // + DsdtPointer = (UINT8 *) (TableHeader) + mAmlOffsetTablePointer[i].Offset; + + if (mAmlOffsetTablePointer[i].Opcode == AML_DWORD_PREFIX) { + // + // If Opcode is 0x0C, then operator is Name() or OperationRegion(). + // (TableHeader + AmlOffsetTable.Offset) is at offset for value to change. + // + // The assert below confirms that AML structure matches the offsets table. + // If not then patching the AML would just corrupt it and result in OS failure. + // If you encounter this assert something went wrong in *.offset.h files + // generation. Remove the files and rebuild. + // + ASSERT(DsdtPointer[-1] == mAmlOffsetTablePointer[i].Opcode); + // + // AmlOffsetTable.Value has FIX tag, so check that to decide what to modify. + // + Signature = (UINT32 *) (&mAmlOffsetTablePointer[i].Value); + switch (*Signature) { + // + // PSYS - "FIX0" OperationRegion() in Acpi\AcpiTables\Dsdt\CommonPlatform.asi + // + case (SIGNATURE_32 ('F', 'I', 'X', '0')): + DEBUG ((DEBUG_INFO, "FIX0 - 0x%x\n", mAcpiParameter)); + * (UINT32 *) DsdtPointer = (UINT32) (UINTN) mAcpiParameter; + // + // "FIX8" OperationRegion() in Acpi\AcpiTables\Dsdt\PcieHp.asi + // + case (SIGNATURE_32 ('F', 'I', 'X', '8')): + Stack = PCIEPortDefaults[PortCount % PORTS_PER_SOCKET].Stack; + PcieHpBus = mIioUds->IioUdsPtr->PlatformData.IIO_resource[IioBusIndex].StackRes[Stack].BusBase; + PcieHpDev = PCIEPortDefaults[PortCount % PORTS_PER_SOCKET].Device; + PcieHpFunc = PCIE_PORT_ALL_FUNC; + + //DEBUG((DEBUG_ERROR,"IioBus = %x, hpDev = %x, HpFunc= %x\n",IioBusIndex, PcieHpDev,PcieHpFunc)); + PciHGPEAddr &= ~(0xFFFF000); // clear bus device func numbers + BusDevFunc = (PcieHpBus << 8) | (PcieHpDev << 3) | PcieHpFunc; + * (UINT32 *) DsdtPointer = (UINT32) (UINTN) (PciHGPEAddr + (BusDevFunc << 12)); + //DEBUG((DEBUG_ERROR,", BusDevFunc= %x, PortCount = %x\n",BusDevFunc, PortCount)); + + PortCount++; + Fixes++; + break; + + default: + break; + } + } else if (mAmlOffsetTablePointer[i].Opcode == AML_INDEX_OP) { + // + // If Opcode is 0x88, then operator is WORDBusNumber() or WORDIO(). + // (TableHeader + AmlOffsetTable.Offset) must be cast to AML_RESOURCE_ADDRESS16 to change values. + // + AmlResourceAddress16Pointer = (AML_RESOURCE_ADDRESS16 *) (DsdtPointer); + // + // The assert below confirms that AML structure matches the offsets table. + // If not then patching the AML would just corrupt it and result in OS failure. + // If you encounter this assert something went wrong in *.offset.h files + // generation. Remove the files and rebuild. + // + ASSERT(AmlResourceAddress16Pointer->DescriptorType == mAmlOffsetTablePointer[i].Opcode); + + // + // Last 4 chars of AmlOffsetTable.Pathname has FIX tag. + // + Signature = (UINT32 *) (mAmlOffsetTablePointer[i].Pathname + AsciiStrLen(mAmlOffsetTablePointer[i].Pathname) - 4); + switch (*Signature) { + // + // "FIX1" BUS resource for PCXX in Acpi\AcpiTables\Dsdt\SysBus.asi and PCXX.asi + // + case (SIGNATURE_32 ('F', 'I', 'X', '1')): + CurrSkt = StackNumBus / MAX_IIO_STACK; + CurrStack = StackNumBus % MAX_IIO_STACK; + BusBase = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].BusBase; + BusLimit = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].BusLimit; + AmlResourceAddress16Pointer->Granularity = 0; + if (BusLimit > BusBase) { + AmlResourceAddress16Pointer->Minimum = (UINT16) BusBase; + AmlResourceAddress16Pointer->Maximum = (UINT16) BusLimit; + AmlResourceAddress16Pointer->AddressLength = (UINT16) (BusLimit - BusBase + 1); + } + //DEBUG((DEBUG_ERROR,", FIX1 BusBase = 0x%x, BusLimit = 0x%x\n",BusBase, BusLimit)); + StackNumBus++; + Fixes++; + break; + + // + // "FIX2" IO resource for for PCXX in Acpi\AcpiTables\Dsdt\SysBus.asi and PCXX.asi + // + case (SIGNATURE_32 ('F', 'I', 'X', '2')): + AmlResourceAddress16Pointer->Granularity = 0; + CurrSkt = StackNumIo / MAX_IIO_STACK; + CurrStack = StackNumIo % MAX_IIO_STACK; + IoBase = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].PciResourceIoBase; + IoLimit = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].PciResourceIoLimit; + if (IoLimit > IoBase) { + AmlResourceAddress16Pointer->Minimum = (UINT16) IoBase; + AmlResourceAddress16Pointer->Maximum = (UINT16) IoLimit; + AmlResourceAddress16Pointer->AddressLength = (UINT16) (IoLimit - IoBase + 1); + } + //DEBUG((DEBUG_ERROR,", FIX2 IoBase = 0x%x, IoLimit = 0x%x\n",IoBase, IoLimit)); + StackNumIo++; + Fixes++; + break; + + // + // "FIX6" IO resource for PCXX in Acpi\AcpiTables\Dsdt\PCXX.asi + // + case (SIGNATURE_32 ('F', 'I', 'X', '6')): + AmlResourceAddress16Pointer->Granularity = 0; + CurrSkt = StackNumVgaIo0 / MAX_IIO_STACK; + CurrStack = StackNumVgaIo0 % MAX_IIO_STACK; + if ((mSocketMpLinkConfiguration.LegacyVgaSoc == CurrSkt) && + (mSocketMpLinkConfiguration.LegacyVgaStack == CurrStack)){ + AmlResourceAddress16Pointer->Minimum = (UINT16) 0x03b0; + AmlResourceAddress16Pointer->Maximum = (UINT16) 0x03bb; + AmlResourceAddress16Pointer->AddressLength = (UINT16) 0x000C; + } + StackNumVgaIo0++; + Fixes++; + break; + + // + // "FIX7" IO resource for PCXX in Acpi\AcpiTables\Dsdt\PCXX.asi + // + case (SIGNATURE_32 ('F', 'I', 'X', '7')): + AmlResourceAddress16Pointer->Granularity = 0; + CurrSkt = StackNumVgaIo1 / MAX_IIO_STACK; + CurrStack = StackNumVgaIo1 % MAX_IIO_STACK; + if ((mSocketMpLinkConfiguration.LegacyVgaSoc == CurrSkt) && + (mSocketMpLinkConfiguration.LegacyVgaStack == CurrStack)) { + AmlResourceAddress16Pointer->Minimum = (UINT16) 0x03c0; + AmlResourceAddress16Pointer->Maximum = (UINT16) 0x03df; + AmlResourceAddress16Pointer->AddressLength = (UINT16) 0x0020; + } + StackNumVgaIo1++; + Fixes++; + break; + + default: + break; + } + } else if (mAmlOffsetTablePointer[i].Opcode == AML_SIZE_OF_OP) { + // + // If Opcode is 0x87, then operator is DWORDMemory(). + // (TableHeader + AmlOffsetTable.Offset) must be cast to AML_RESOURCE_ADDRESS32 to change values. + // + AmlResourceAddress32Pointer = (AML_RESOURCE_ADDRESS32 *) (DsdtPointer); + // + // The assert below confirms that AML structure matches the offsets table. + // If not then patching the AML would just corrupt it and result in OS failure. + // If you encounter this assert something went wrong in *.offset.h files + // generation. Remove the files and rebuild. + // + ASSERT(AmlResourceAddress32Pointer->DescriptorType == mAmlOffsetTablePointer[i].Opcode); + // + // Last 4 chars of AmlOffsetTable.Pathname has FIX tag. + // + Signature = (UINT32 *) (mAmlOffsetTablePointer[i].Pathname + AsciiStrLen(mAmlOffsetTablePointer[i].Pathname) - 4); + switch (*Signature) { + // + // "FIX3" PCI32 resource for PCXX in Acpi\AcpiTables\Dsdt\SysBus.asi and PCXX.asi + // + case (SIGNATURE_32 ('F', 'I', 'X', '3')): + AmlResourceAddress32Pointer->Granularity = 0; + CurrSkt = StackNumMem32 / MAX_IIO_STACK; + CurrStack = StackNumMem32 % MAX_IIO_STACK; + MemBase32 = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].PciResourceMem32Base; + MemLimit32 = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].PciResourceMem32Limit; + if (MemLimit32 > MemBase32) { + AmlResourceAddress32Pointer->Minimum = (UINT32) MemBase32; + AmlResourceAddress32Pointer->Maximum = (UINT32) MemLimit32; + AmlResourceAddress32Pointer->AddressLength = (UINT32) (MemLimit32 - MemBase32 + 1); + } + //DEBUG((DEBUG_ERROR,", FIX3 MemBase32 = 0x%08x, MemLimit32 = 0x%08x\n",MemBase32, MemLimit32)); + StackNumMem32++; + Fixes++; + break; + + // + // "FIX5" IO resource for PCXX in Acpi\AcpiTables\Dsdt\PCXX.asi + // + case (SIGNATURE_32 ('F', 'I', 'X', '5')): + AmlResourceAddress32Pointer->Granularity = 0; + CurrSkt = StackNumVgaMmioL / MAX_IIO_STACK; + CurrStack = StackNumVgaMmioL % MAX_IIO_STACK; + if ((mSocketMpLinkConfiguration.LegacyVgaSoc == CurrSkt) && + (mSocketMpLinkConfiguration.LegacyVgaStack == CurrStack)) { + AmlResourceAddress32Pointer->Minimum = 0x000a0000; + AmlResourceAddress32Pointer->Maximum = 0x000bffff; + AmlResourceAddress32Pointer->AddressLength = 0x00020000; + } + StackNumVgaMmioL++; + Fixes++; + break; + + default: + break; + } + } else if (mAmlOffsetTablePointer[i].Opcode == AML_CREATE_DWORD_FIELD_OP) { + // + // If Opcode is 0x8A, then operator is QWORDMemory(). + // (TableHeader + AmlOffsetTable.Offset) must be cast to AML_RESOURCE_ADDRESS64 to change values. + // + AmlResourceAddress64Pointer = (AML_RESOURCE_ADDRESS64 *) (DsdtPointer); + // + // The assert below confirms that AML structure matches the offsets table. + // If not then patching the AML would just corrupt it and result in OS failure. + // If you encounter this assert something went wrong in *.offset.h files + // generation. Remove the files and rebuild. + // + ASSERT(AmlResourceAddress64Pointer->DescriptorType == mAmlOffsetTablePointer[i].Opcode); + // + // Last 4 chars of AmlOffsetTable.Pathname has FIX tag. + // + Signature = (UINT32 *) (mAmlOffsetTablePointer[i].Pathname + AsciiStrLen(mAmlOffsetTablePointer[i].Pathname) - 4); + switch (*Signature) { + // + // "FIX4" PCI64 resource for PCXX in Acpi\AcpiTables\Dsdt\SysBus.asi and PCXX.asi + // + case (SIGNATURE_32 ('F', 'I', 'X', '4')): + DEBUG((DEBUG_ERROR,"Pci64BitResourceAllocation = 0x%x\n",mSocketIioConfiguration.Pci64BitResourceAllocation)); + if (mSocketIioConfiguration.Pci64BitResourceAllocation) { + AmlResourceAddress64Pointer->Granularity = 0; + CurrSkt = StackNumMem64 / MAX_IIO_STACK; + CurrStack = StackNumMem64 % MAX_IIO_STACK; + MemBase64 = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].PciResourceMem64Base; + MemLimit64 = mIioUds->IioUdsPtr->PlatformData.IIO_resource[CurrSkt].StackRes[CurrStack].PciResourceMem64Limit; + if (MemLimit64 > MemBase64) { + AmlResourceAddress64Pointer->Minimum = (UINT64) MemBase64; + AmlResourceAddress64Pointer->Maximum = (UINT64) MemLimit64; + AmlResourceAddress64Pointer->AddressLength = (UINT64) (MemLimit64 - MemBase64 + 1); + } + DEBUG((DEBUG_ERROR,", FIX4 MemBase64 = 0x%x, MemLimit64 = 0x%x\n",MemBase64, MemLimit64)); + StackNumMem64++; + Fixes++; + } + break; + default: + break; + } + } + } + + //return Status; + return EFI_SUCCESS; + +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt.inf b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt.inf new file mode 100644 index 0000000000..2c53d67d49 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt.inf @@ -0,0 +1,37 @@ +### @file +# +# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +### + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = Dsdt + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + +[Sources] + Dsdt/WFPPlatform.asl + +[Packages] + MdePkg/MdePkg.dec + LewisburgPkg/PchRcPkg.dec + PurleyOpenBoardPkg/PlatPkg.dec + PurleySktPkg/SocketPkg.dec + PurleyRcPkg/RcPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + +[BuildOptions] + # add -vr and -so to generate offset.h + *_*_*_ASL_FLAGS = -oi -vr -so + + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl new file mode 100644 index 0000000000..e7986b8670 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl @@ -0,0 +1,25 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + +/////////////////////////////////////////////////////////////////////////////////// +//Values are set like this to have ASL compiler reserve enough space for objects +/////////////////////////////////////////////////////////////////////////////////// +// +// Available Sleep states +// +Name(SS1,0) +Name(SS2,0) +Name(SS3,1) +Name(SS4,1) + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CommonPlatform.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CommonPlatform.asi new file mode 100644 index 0000000000..8e9f2d5375 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CommonPlatform.asi @@ -0,0 +1,233 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "MaxSocket.h" + + // + // External declarations + // HECI-1/HECI-2 are in PurleyPlatPkg\Me\Sps\Acpi\SpsNm.asl + // + External(\_SB.PC00.HEC2.HPTS, MethodObj) + External(\_SB.PC00.HEC2.HWAK, MethodObj) + + // + // System Sleep States + // + Name (\_S0,Package (){0,0,0,0}) + Name (\_S3,Package (){5,0,0,0}) // Name changed to \DS3 if disabled in Setup + Name (\_S4,Package (){6,0,0,0}) // Name changed to \DS4 if disabled in Setup + Name (\_S5,Package (){7,0,0,0}) + + // + // Native OS hot plug support, 0->ACPI, 1->OS + // + Name (\OSHF, 0) + + // + // OS flag + // + #include "Os.asi" + + // + // for determing PIC mode + // + Name (\PICM,Zero) + Method (\_PIC, 1, NotSerialized) { + Store(Arg0,\PICM) + } + + OperationRegion (DBG0, SystemIO, 0x80, 2) + Field (DBG0, ByteAcc,NoLock,Preserve) { + IO80, 8, + IO81, 8 + } + + // + // Access CMOS range + // + OperationRegion (ACMS, SystemIO, 0x72, 2) + Field ( ACMS, ByteAcc, NoLock, Preserve) { + INDX, 8, + DATA, 8 + } + + // + // SWGPE_CTRL + // + OperationRegion (GPCT, SystemIO, 0x442, 1) + Field ( GPCT, ByteAcc, NoLock, Preserve) { + , 1, + SGPC , 1, + } + + // + // GPI_INV + // + OperationRegion (GPIV, SystemIO, 0x52c, 2) + Field ( GPIV, ByteAcc, NoLock, Preserve) { + GP0I , 1, + } + +#include "Acpi/GlobalNvs.asi" + + // + // Operation region for GPI status bits + // + OperationRegion (GSTS, SystemIO, 0x422, 2) + Field ( GSTS, ByteAcc, NoLock, Preserve) { + GP00 , 1, + , 12, + GP13 , 1, + } + + // + // GPE0 HOT_PLUG_EN + // + OperationRegion (GPE0, SystemIO, 0x428, 8) + Field (GPE0, ByteAcc,NoLock,Preserve) { + ,1, + GPEH,1, + ,1, + USB1,1, + USB2,1, + USB5,1, + ,3, + PCIE,1, + ,1, + PMEE,1, + USB3,1, + PMB0,1, + USB4,1, + ,9, + ,1, + ,7, + USB6,1, + ,15, + } + + // + // GPES Status + // + OperationRegion (GPES, SystemIO, 0x420, 8) + Field (GPES, ByteAcc,NoLock,Preserve) { + ,1, + GPSH,1, + SGPS,1, + US1S,1, + US2S,1, + US5S,1, + ,1, + SMWS,1, + ,1, + PEES,1, + ,1, + PMES,1, + + US3S ,1, + PMBS,1, + US4S ,1, + ,9, + ,1, + ,7, + US6S,1, + ,15, + } + + // + // System sleep down + // + Method (_PTS, 1, NotSerialized) + { + Store (0x72, IO80) // Sync with EfiPostCode.h + + // + // Clear wake event status. + // + Store(1,US1S) + Store(1,US2S) + Store(1,US5S) + Store(1,SMWS) + Store(1,PMES) + Store(1,US3S) + Store(1,PMBS) + Store(1,US4S) + Store(1,US6S) + + // + // Enable SCI and wake event sources. + // + Store(1,GPEH) + Store(1,USB1) + Store(1,USB2) + Store(1,USB5) + Store(1,PCIE) + Store(1,PMEE) + Store(1,USB3) + Store(1,PMB0) + Store(1,USB4) + Store(1,USB6) + + // + // If HECI-2 exist call its prepare-to-sleep handler. + // The handler checks whether HECI-2 is enabled. + // + If (CondRefOf(\_SB.PC00.HEC2.HPTS)) + { + \_SB.PC00.HEC2.HPTS() + } + + /// WA for S3 on XHCI + \_SB.PC00.XHCI.XHCS() + } + + //#include "Uncore.asi" + + // + // System Wake up + // + Method (_WAK, 1, Serialized) + { + Store (0x73, IO80) // Sync with EfiPostCode.h + + // + // If HECI-2 exist call its wake-up handler. + // The handler checks whether HECI-2 is enabled. + // + If (CondRefOf(\_SB.PC00.HEC2.HWAK)) + { + \_SB.PC00.HEC2.HWAK() + } + + // + // If waking from S3 + // + If (LEqual(Arg0, 3)) { + } + + Return(Package(){0, 0}) + } + + Scope(\_SB) { + + // Information on CPU and Memory for hotplug SKUs + // #include "CpuMemHp.asi" + + OperationRegion (IOB2, SystemIO, 0xB2, 2) //MKF_SMIPORT + Field (IOB2, ByteAcc, NoLock, Preserve) { + SMIC, 8, // SW-SMI ctrl port + SMIS, 8, // SW-SMI status port + } + + } // end _SB scope + + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.asl new file mode 100644 index 0000000000..427be161b5 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.asl @@ -0,0 +1,83 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + +// Comment out includes as ifdefs don't work at trim stage + +// +// + +Scope(\_SB) { + // + //--------------------------------------------------------------------------- + // List of IRQ resource buffers compatible with _PRS return format. + //--------------------------------------------------------------------------- + // Naming legend: + // RSxy, PRSy - name of the IRQ resource buffer to be returned by _PRS, "xy" - last two characters of IRQ Link name. + // Note. PRSy name is generated if IRQ Link name starts from "LNK". + // HLxy , LLxy - reference names, can be used to access bit mask of available IRQs. HL and LL stand for active High(Low) Level triggered Irq model. + //--------------------------------------------------------------------------- + Name(PRSA, ResourceTemplate(){ // Link name: LNKA + IRQ(Level, ActiveLow, Shared, LLKA) {3,4,5,6,10,11,12,14,15} + }) + Alias(PRSA,PRSB) // Link name: LNKB + Alias(PRSA,PRSC) // Link name: LNKC + Alias(PRSA,PRSD) // Link name: LNKD + Alias(PRSA,PRSE) // Link name: LNKE + Alias(PRSA,PRSF) // Link name: LNKF + Alias(PRSA,PRSG) // Link name: LNKG + Alias(PRSA,PRSH) // Link name: LNKH +} + +// +// + + Scope(\_SB.PC00) { + // + // PCI-specific method's GUID + // + Name(PCIG, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D")) + // + // PCI's _DSM - an attempt at modular _DSM implementation + // When writing your own _DSM function that needs to include PCI-specific methods, do this: + // + // Method(_YOUR_DSM,4){ + // if(Lequal(Arg0,PCIG)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) } + // ...continue your _DSM by checking different GUIDs... + // else { return(0) } + // } + // + Method(PCID, 4, Serialized) { + If(LEqual(Arg0, PCIG)) { // PCIE capabilities UUID + If(LGreaterEqual(Arg1,3)) { // revision at least 3 + If(LEqual(Arg2,0)) { Return (Buffer(2){0x01,0x03}) } // function 0: list of supported functions + If(LEqual(Arg2,8)) { Return (1) } // function 8: Avoiding Power-On Reset Delay Duplication on Sx Resume + If(LEqual(Arg2,9)) { Return (Package(5){50000,Ones,Ones,50000,Ones}) } // function 9: Specifying Device Readiness Durations + } + } + return (Buffer(1){0}) + } + }//scope +Scope(\_SB.PC00) { + //PciCheck, Arg0=UUID, returns true if support for 'PCI delays optimization ECR' is enabled and the UUID is correct + Method(PCIC,1,Serialized) { + If(LEqual(ECR1,1)) { + If(LEqual(Arg0, PCIG)) { + return (1) + } + } + return (0) + } +} + + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl new file mode 100644 index 0000000000..b2986a16a7 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl @@ -0,0 +1,140 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + // General Purpose Events. This Scope handles the Run-time and + // Wake-time SCIs. The specific method called will be determined by + // the _Lxx value, where xx equals the bit location in the General + // Purpose Event register(s). + + // + // If the Root Port is enabled, run PCI_EXP_STS handler + // + If(LNotEqual(\_SB.PC00.RP01.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP01.HPME() + Notify(\_SB.PC00.RP01, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP02.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP02.HPME() + Notify(\_SB.PC00.RP02, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP03.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP03.HPME() + Notify(\_SB.PC00.RP03, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP04.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP04.HPME() + Notify(\_SB.PC00.RP04, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP05.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP05.HPME() + Notify(\_SB.PC00.RP05, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP06.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP06.HPME() + Notify(\_SB.PC00.RP06, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP07.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP07.HPME() + Notify(\_SB.PC00.RP07, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP08.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP08.HPME() + Notify(\_SB.PC00.RP08, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP09.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP09.HPME() + Notify(\_SB.PC00.RP09, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP10.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP10.HPME() + Notify(\_SB.PC00.RP10, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP11.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP11.HPME() + Notify(\_SB.PC00.RP11, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP12.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP12.HPME() + Notify(\_SB.PC00.RP12, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP13.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP13.HPME() + Notify(\_SB.PC00.RP13, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP14.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP14.HPME() + Notify(\_SB.PC00.RP14, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP15.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP15.HPME() + Notify(\_SB.PC00.RP15, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP16.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP16.HPME() + Notify(\_SB.PC00.RP16, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP17.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP17.HPME() + Notify(\_SB.PC00.RP17, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP18.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP18.HPME() + Notify(\_SB.PC00.RP18, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP19.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP19.HPME() + Notify(\_SB.PC00.RP19, 0x02) + } + + If(LNotEqual(\_SB.PC00.RP20.VDID,0xFFFFFFFF)) + { + \_SB.PC00.RP20.HPME() + Notify(\_SB.PC00.RP20, 0x02) + } diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/HostBus.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/HostBus.asl new file mode 100644 index 0000000000..27a997cbfb --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/HostBus.asl @@ -0,0 +1,262 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// +// Define various System Agent (SA) PCI Configuration Space +// registers which will be used to dynamically produce all +// resources in the Host Bus _CRS. +// +OperationRegion (HBUS, PCI_Config, 0x00, 0x100) +Field (HBUS, DWordAcc, NoLock, Preserve) +{ + Offset(0x40), // EPBAR (0:0:0:40) + EPEN, 1, // Enable + , 11, + EPBR, 20, // EPBAR [31:12] + + Offset(0x48), // MCHBAR (0:0:0:48) + MHEN, 1, // Enable + , 14, + MHBR, 17, // MCHBAR [31:15] + + Offset(0x50), // GGC (0:0:0:50) + GCLK, 1, // GGCLCK + + Offset(0x54), // DEVEN (0:0:0:54) + D0EN, 1, // DEV0 Enable + D1F2, 1, // DEV1 FUN2 Enable + D1F1, 1, // DEV1 FUN1 Enable + D1F0, 1, // DEV1 FUN0 Enable + + Offset(0x60), // PCIEXBAR (0:0:0:60) + PXEN, 1, // Enable + PXSZ, 2, // PCI Express Size + , 23, + PXBR, 6, // PCI Express BAR [31:26] + + Offset(0x68), // DMIBAR (0:0:0:68) + DIEN, 1, // Enable + , 11, + DIBR, 20, // DMIBAR [31:12] + + Offset(0x70), // MESEG_BASE (0:0:0:70) + , 20, + MEBR, 12, // MESEG_BASE [31:20] + + Offset(0x80), // PAM0 Register (0:0:0:80) + , 4, + PM0H, 2, // PAM 0, High Nibble + , 2, + + Offset(0x81), // PAM1 Register (0:0:0:81) + PM1L, 2, // PAM1, Low Nibble + , 2, + PM1H, 2, // PAM1, High Nibble + , 2, + + Offset(0x82), // PAM2 Register (0:0:0:82) + PM2L, 2, // PAM2, Low Nibble + , 2, + PM2H, 2, // PAM2, High Nibble + , 2, + + Offset(0x83), // PAM3 Register (0:0:0:83) + PM3L, 2, // PAM3, Low Nibble + , 2, + PM3H, 2, // PAM3, High Nibble + , 2, + + Offset(0x84), // PAM4 Register (0:0:0:84) + PM4L, 2, // PAM4, Low Nibble + , 2, + PM4H, 2, // PAM4, High Nibble + , 2, + + Offset(0x85), // PAM5 Register (0:0:0:85) + PM5L, 2, // PAM5, Low Nibble + , 2, + PM5H, 2, // PAM5, High Nibble + , 2, + + Offset(0x86), // PAM6 Register (0:0:0:86) + PM6L, 2, // PAM6, Low Nibble + , 2, + PM6H, 2, // PAM6, High Nibble + , 2, + + Offset(0xA8), // Top of Upper Usable DRAM Register (0:0:0:A8) + , 20, + TUUD, 19, // TOUUD [38:20] + + Offset(0xBC), // Top of Lower Usable DRAM Register (0:0:0:BC) + , 20, + TLUD, 12, // TOLUD [31:20] + + Offset(0xC8), // ERRSTS register (0:0:0:C8) + , 7, + HTSE, 1 // Host Thermal Sensor Event for SMI/SCI/SERR +} +// +// Define a buffer that will store all the bus, memory, and IO information +// relating to the Host Bus. This buffer will be dynamically altered in +// the _CRS and passed back to the OS. +// +Name(BUF0,ResourceTemplate() +{ + // + // Bus Number Allocation: Bus 0 to 0xFF + // + WORDBusNumber(ResourceProducer,MinFixed,MaxFixed,PosDecode,0x00, + 0x0000,0x00FF,0x00,0x0100,,,PB00) + + // + // I/O Region Allocation 0 ( 0x0000 - 0x0CF7 ) + // + DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange, + 0x00,0x0000,0x0CF7,0x00,0x0CF8,,,PI00) + + // + // PCI Configuration Registers ( 0x0CF8 - 0x0CFF ) + // + Io(Decode16,0x0CF8,0x0CF8,1,0x08) + + // + // I/O Region Allocation 1 ( 0x0D00 - 0xFFFF ) + // + DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange, + 0x00,0x0D00,0xFFFF,0x00,0xF300,,,PI01) + + // + // Video Buffer Area ( 0xA0000 - 0xBFFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xA0000,0xBFFFF,0x00,0x20000,,,A000) + + // + // ISA Add-on BIOS Area ( 0xC0000 - 0xC3FFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xC0000,0xC3FFF,0x00,0x4000,,,C000) + + // + // ISA Add-on BIOS Area ( 0xC4000 - 0xC7FFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xC4000,0xC7FFF,0x00,0x4000,,,C400) + + // + // ISA Add-on BIOS Area ( 0xC8000 - 0xCBFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xC8000,0xCBFFF,0x00,0x4000,,,C800) + + // + // ISA Add-on BIOS Area ( 0xCC000 - 0xCFFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xCC000,0xCFFFF,0x00,0x4000,,,CC00) + + // + // ISA Add-on BIOS Area ( 0xD0000 - 0xD3FFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xD0000,0xD3FFF,0x00,0x4000,,,D000) + + // + // ISA Add-on BIOS Area ( 0xD4000 - 0xD7FFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xD4000,0xD7FFF,0x00,0x4000,,,D400) + + // + // ISA Add-on BIOS Area ( 0xD8000 - 0xDBFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xD8000,0xDBFFF,0x00,0x4000,,,D800) + + // + // ISA Add-on BIOS Area ( 0xDC000 - 0xDFFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xDC000,0xDFFFF,0x00,0x4000,,,DC00) + + // + // BIOS Extension Area ( 0xE0000 - 0xE3FFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xE0000,0xE3FFF,0x00,0x4000,,,E000) + + // + // BIOS Extension Area ( 0xE4000 - 0xE7FFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xE4000,0xE7FFF,0x00,0x4000,,,E400) + + // + // BIOS Extension Area ( 0xE8000 - 0xEBFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xE8000,0xEBFFF,0x00,0x4000,,,E800) + + // + // BIOS Extension Area ( 0xEC000 - 0xEFFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xEC000,0xEFFFF,0x00,0x4000,,,EC00) + + // + // BIOS Area ( 0xF0000 - 0xFFFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xF0000,0xFFFFF,0x00,0x10000,,,F000) + +// // +// // Memory Hole Region ( 0xF00000 - 0xFFFFFF ) +// // +// DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, +// ReadWrite,0x00,0xF00000,0xFFFFFF,0x00,0x100000,,,HOLE) + + // + // PCI Memory Region ( TOLUD - 0xFEAFFFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0x00000000,0xFEAFFFFF,0x00,0xFEB00000,,,PM01) + + // + // PCI Memory Region ( TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE) ) + // (This is dummy range for OS compatibility, will patch it in _CRS) + // + QWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0x10000,0x1FFFF,0x00,0x10000,,,PM02) +}) + +Name(EP_B, 0) // to store EP BAR +Name(MH_B, 0) // to store MCH BAR +Name(PC_B, 0) // to store PCIe BAR +Name(PC_L, 0) // to store PCIe BAR Length +Name(DM_B, 0) // to store DMI BAR + + +// +// Get PCIe BAR +// +Method(GPCB,0,Serialized) +{ + if(LEqual(PC_B,0)) + { + //ShiftLeft(\_SB.PC00.PXBR,26,PC_B) + Store(MCFG,PC_B) + } + Return(PC_B) +} + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieHotPlugGpeHandler.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieHotPlugGpeHandler.asl new file mode 100644 index 0000000000..03a7d13c2e --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieHotPlugGpeHandler.asl @@ -0,0 +1,848 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + // + // Delay introduced as initial delay after entering ACPI hotplug method + // + Sleep (200) + Store (0x01, IO80) + Sleep (10) + Store (0,Local1) + + // PC01 Port 1A PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC01.BR1A.PMEP,1) ) { + Store(\_SB.PC01.BR1A.PMEH(1), Local0) + } else { + Store (\_SB.PC01.BR1A.HPEH(1), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(1, Local1) + Notify(\_SB.PC01.BR1A, Local0) + } + + // PC01 Port 1B PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC01.BR1B.PMEP,1) ) { + Store(\_SB.PC01.BR1B.PMEH(2), Local0) + } else { + Store (\_SB.PC01.BR1B.HPEH(2), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(2, Local1) + Notify(\_SB.PC01.BR1B, Local0) + } + + // PC01 Port 1C PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC01.BR1C.PMEP,1) ) { + Store(\_SB.PC01.BR1C.PMEH(3), Local0) + } else { + Store (\_SB.PC01.BR1C.HPEH(3), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(3, Local1) + Notify(\_SB.PC01.BR1C, Local0) + } + + // PC01 Port 1D PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC01.BR1D.PMEP,1) ) { + Store(\_SB.PC01.BR1D.PMEH(4), Local0) + } else { + Store (\_SB.PC01.BR1D.HPEH(4), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(4, Local1) + Notify(\_SB.PC01.BR1D, Local0) + } + + // PC02 Port 2A PCI-Ex Hot Plug + If( LEqual(\_SB.PC02.BR2A.PMEP,1) ) { + Store(\_SB.PC02.BR2A.PMEH(5), Local0) + } else { + Store (\_SB.PC02.BR2A.HPEH(5), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(5, Local1) + Notify(\_SB.PC02.BR2A, Local0) + } + + // PC02 Port 2B PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC02.BR2B.PMEP,1) ) { + Store(\_SB.PC02.BR2B.PMEH(6), Local0) + } else { + Store (\_SB.PC02.BR2B.HPEH(6), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(6, Local1) + Notify(\_SB.PC02.BR2B, Local0) + } + + // PC02 Port 2C PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC02.BR2C.PMEP,1) ) { + Store(\_SB.PC02.BR2C.PMEH(7), Local0) + } else { + Store (\_SB.PC02.BR2C.HPEH(7), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(7, Local1) + Notify(\_SB.PC02.BR2C, Local0) + } + + // PC02 Port 2D PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC02.BR2D.PMEP,1) ) { + Store(\_SB.PC02.BR2D.PMEH(8), Local0) + } else { + Store (\_SB.PC02.BR2D.HPEH(8), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(8, Local1) + Notify(\_SB.PC02.BR2D, Local0) + } + + // PC03 Port 3A PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC03.BR3A.PMEP,1) ) { + Store(\_SB.PC03.BR3A.PMEH(9), Local0) + } else { + Store (\_SB.PC03.BR3A.HPEH(9), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(9, Local1) + Notify(\_SB.PC03.BR3A, Local0) + } + + // PC03 Port 3B PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC03.BR3B.PMEP,10) ) { + Store(\_SB.PC03.BR3B.PMEH(10), Local0) + } else { + Store (\_SB.PC03.BR3B.HPEH(10), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(10, Local1) + Notify(\_SB.PC03.BR3B, Local0) + } + + // PC03 Port 3C PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC03.BR3C.PMEP,1) ) { + Store(\_SB.PC03.BR3C.PMEH(11), Local0) + } else { + Store (\_SB.PC03.BR3C.HPEH(11), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(11, Local1) + Notify(\_SB.PC03.BR3C, Local0) + } + + // PC03 Port 3D PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC03.BR3D.PMEP,1) ) { + Store(\_SB.PC03.BR3D.PMEH(12), Local0) + } else { + Store (\_SB.PC03.BR3D.HPEH(12), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(12, Local1) + Notify(\_SB.PC03.BR3D, Local0) + } + + // PC06 Port 0 PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC06.QRP0.PMEP,1) ) { + Store(\_SB.PC06.QRP0.PMEH(1), Local0) + } else { + Store (\_SB.PC06.QRP0.HPEH(1), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(1, Local1) + Notify(\_SB.PC06.QRP0, Local0) + } + + // PC07 Port 1A PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC07.QR1A.PMEP,1) ) { + Store(\_SB.PC07.QR1A.PMEH(1), Local0) + } else { + Store (\_SB.PC07.QR1A.HPEH(1), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(1, Local1) + Notify(\_SB.PC07.QR1A, Local0) + } + + // PC07 Port 1B PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC07.QR1B.PMEP,1) ) { + Store(\_SB.PC07.QR1B.PMEH(2), Local0) + } else { + Store (\_SB.PC07.QR1B.HPEH(2), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(2, Local1) + Notify(\_SB.PC07.QR1B, Local0) + } + + // PC07 Port 1C PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC07.QR1C.PMEP,1) ) { + Store(\_SB.PC07.QR1C.PMEH(3), Local0) + } else { + Store (\_SB.PC07.QR1C.HPEH(3), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(3, Local1) + Notify(\_SB.PC07.QR1C, Local0) + } + + // PC07 Port 1D PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC07.QR1D.PMEP,1) ) { + Store(\_SB.PC07.QR1D.PMEH(4), Local0) + } else { + Store (\_SB.PC07.QR1D.HPEH(4), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(4, Local1) + Notify(\_SB.PC07.QR1D, Local0) + } + + // PC08 Port 2A PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC08.QR2A.PMEP,1) ) { + Store(\_SB.PC08.QR2A.PMEH(5), Local0) + } else { + Store (\_SB.PC08.QR2A.HPEH(5), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(5, Local1) + Notify(\_SB.PC08.QR2A, Local0) + } + + // PC08 Port 2B PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC08.QR2B.PMEP,1) ) { + Store(\_SB.PC08.QR2B.PMEH(6), Local0) + } else { + Store (\_SB.PC08.QR2B.HPEH(6), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(6, Local1) + Notify(\_SB.PC08.QR2B, Local0) + } + + // PC08 Port 2C PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC08.QR2C.PMEP,1) ) { + Store(\_SB.PC08.QR2C.PMEH(7), Local0) + } else { + Store (\_SB.PC08.QR2C.HPEH(7), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(7, Local1) + Notify(\_SB.PC08.QR2C, Local0) + } + + // PC08 Port 2D PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC08.QR2D.PMEP,1) ) { + Store(\_SB.PC08.QR2D.PMEH(8), Local0) + } else { + Store (\_SB.PC08.QR2D.HPEH(8), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(8, Local1) + Notify(\_SB.PC08.QR2D, Local0) + } + + // PC09 Port 3A PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC09.QR3A.PMEP,1) ) { + Store(\_SB.PC09.QR3A.PMEH(9), Local0) + } else { + Store (\_SB.PC09.QR3A.HPEH(9), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(9, Local1) + Notify(\_SB.PC09.QR3A, Local0) + } + + // PC09 Port 3B PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC09.QR3B.PMEP,1) ) { + Store(\_SB.PC09.QR3B.PMEH(10), Local0) + } else { + Store (\_SB.PC09.QR3B.HPEH(10), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(10, Local1) + Notify(\_SB.PC09.QR3B, Local0) + } + + // PC09 Port 3C PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC09.QR3C.PMEP,1) ) { + Store(\_SB.PC09.QR3C.PMEH(11), Local0) + } else { + Store (\_SB.PC09.QR3C.HPEH(11), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(11, Local1) + Notify(\_SB.PC09.QR3C, Local0) + } + + // PC09 Port 3D PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC09.QR3D.PMEP,1) ) { + Store(\_SB.PC09.QR3D.PMEH(12), Local0) + } else { + Store (\_SB.PC09.QR3D.HPEH(12), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(12, Local1) + Notify(\_SB.PC09.QR3D, Local0) + } + + // PC12 Port 0 PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC12.RRP0.PMEP,1) ) { + Store(\_SB.PC12.RRP0.PMEH(1), Local0) + } else { + Store (\_SB.PC12.RRP0.HPEH(1), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(1, Local1) + Notify(\_SB.PC12.RRP0, Local0) + } + + // PC13 Port 1A PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC13.RR1A.PMEP,1) ) { + Store(\_SB.PC13.RR1A.PMEH(1), Local0) + } else { + Store (\_SB.PC13.RR1A.HPEH(1), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(1, Local1) + Notify(\_SB.PC13.RR1A, Local0) + } + + // PC13 Port 1B PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC13.RR1B.PMEP,1) ) { + Store(\_SB.PC13.RR1B.PMEH(2), Local0) + } else { + Store (\_SB.PC13.RR1B.HPEH(2), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(2, Local1) + Notify(\_SB.PC13.RR1B, Local0) + } + + // PC13 Port 1C PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC13.RR1C.PMEP,1) ) { + Store(\_SB.PC13.RR1C.PMEH(3), Local0) + } else { + Store (\_SB.PC13.RR1C.HPEH(3), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(3, Local1) + Notify(\_SB.PC13.RR1C, Local0) + } + + // PC13 Port 1D PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC13.RR1D.PMEP,1) ) { + Store(\_SB.PC13.RR1D.PMEH(4), Local0) + } else { + Store (\_SB.PC13.RR1D.HPEH(4), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(4, Local1) + Notify(\_SB.PC13.RR1D, Local0) + } + + // PC14 Port 2A PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC14.RR2A.PMEP,1) ) { + Store(\_SB.PC14.RR2A.PMEH(5), Local0) + } else { + Store (\_SB.PC14.RR2A.HPEH(5), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(5, Local1) + Notify(\_SB.PC14.RR2A, Local0) + } + + // PC14 Port 2B PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC14.RR2B.PMEP,1) ) { + Store(\_SB.PC14.RR2B.PMEH(6), Local0) + } else { + Store (\_SB.PC14.RR2B.HPEH(6), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(6, Local1) + Notify(\_SB.PC14.RR2B, Local0) + } + + // PC14 Port 2C PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC14.RR2C.PMEP,1) ) { + Store(\_SB.PC14.RR2C.PMEH(7), Local0) + } else { + Store (\_SB.PC14.RR2C.HPEH(7), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(7, Local1) + Notify(\_SB.PC14.RR2C, Local0) + } + + // PC15 Port 2D PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC14.RR2D.PMEP,1) ) { + Store(\_SB.PC14.RR2D.PMEH(8), Local0) + } else { + Store (\_SB.PC14.RR2D.HPEH(8), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(8, Local1) + Notify(\_SB.PC14.RR2D, Local0) + } + + // PC15 Port 3A PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC15.RR3A.PMEP,1) ) { + Store(\_SB.PC15.RR3A.PMEH(9), Local0) + } else { + Store (\_SB.PC15.RR3A.HPEH(9), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(9, Local1) + Notify(\_SB.PC15.RR3A, Local0) + } + + // PC15 Port 3B PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC15.RR3B.PMEP,1) ) { + Store(\_SB.PC15.RR3B.PMEH(10), Local0) + } else { + Store (\_SB.PC15.RR3B.HPEH(10), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(10, Local1) + Notify(\_SB.PC15.RR3B, Local0) + } + + // PC15 Port 3C PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC15.RR3C.PMEP,1) ) { + Store(\_SB.PC15.RR3C.PMEH(11), Local0) + } else { + Store (\_SB.PC15.RR3C.HPEH(11), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(11, Local1) + Notify(\_SB.PC15.RR3C, Local0) + } + + // PC15 Port 3D PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC15.RR3D.PMEP,1) ) { + Store(\_SB.PC15.RR3D.PMEH(12), Local0) + } else { + Store (\_SB.PC15.RR3D.HPEH(12), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(12, Local1) + Notify(\_SB.PC15.RR3D, Local0) + } + + // PC18 Port 0 PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC18.SRP0.PMEP,1) ) { + Store(\_SB.PC18.SRP0.PMEH(1), Local0) + } else { + Store (\_SB.PC18.SRP0.HPEH(1), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(1, Local1) + Notify(\_SB.PC18.SRP0, Local0) + } + + // PC19 Port 1A PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC19.SR1A.PMEP,1) ) { + Store(\_SB.PC19.SR1A.PMEH(1), Local0) + } else { + Store (\_SB.PC19.SR1A.HPEH(1), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(1, Local1) + Notify(\_SB.PC19.SR1A, Local0) + } + + // PC19 Port 1B PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC19.SR1B.PMEP,1) ) { + Store(\_SB.PC19.SR1B.PMEH(2), Local0) + } else { + Store (\_SB.PC19.SR1B.HPEH(2), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(2, Local1) + Notify(\_SB.PC19.SR1B, Local0) + } + + // PC19 Port 1C PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC19.SR1C.PMEP,1) ) { + Store(\_SB.PC19.SR1C.PMEH(3), Local0) + } else { + Store (\_SB.PC19.SR1C.HPEH(3), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(3, Local1) + Notify(\_SB.PC19.SR1C, Local0) + } + + // PC19 Port 1D PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC19.SR1D.PMEP,1) ) { + Store(\_SB.PC19.SR1D.PMEH(4), Local0) + } else { + Store (\_SB.PC19.SR1D.HPEH(4), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(4, Local1) + Notify(\_SB.PC19.SR1D, Local0) + } + + // PC20 Port 2A PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC20.SR2A.PMEP,1) ) { + Store(\_SB.PC20.SR2A.PMEH(5), Local0) + } else { + Store (\_SB.PC20.SR2A.HPEH(5), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(5, Local1) + Notify(\_SB.PC20.SR2A, Local0) + } + + // PC20 Port 2B PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC20.SR2B.PMEP,1) ) { + Store(\_SB.PC20.SR2B.PMEH(6), Local0) + } else { + Store (\_SB.PC20.SR2B.HPEH(6), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(6, Local1) + Notify(\_SB.PC20.SR2B, Local0) + } + + // PC20 Port 2C PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC20.SR2C.PMEP,1) ) { + Store(\_SB.PC20.SR2C.PMEH(7), Local0) + } else { + Store (\_SB.PC20.SR2C.HPEH(7), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(7, Local1) + Notify(\_SB.PC20.SR2C, Local0) + } + + // PC20 Port 2D PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC20.SR2D.PMEP,1) ) { + Store(\_SB.PC20.SR2D.PMEH(8), Local0) + } else { + Store (\_SB.PC20.SR2D.HPEH(8), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(8, Local1) + Notify(\_SB.PC20.SR2D, Local0) + } + + // PC21 Port 3A PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC21.SR3A.PMEP,1) ) { + Store(\_SB.PC21.SR3A.PMEH(9), Local0) + } else { + Store (\_SB.PC21.SR3A.HPEH(9), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(9, Local1) + Notify(\_SB.PC21.SR3A, Local0) + } + + // PC21 Port 3B PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC21.SR3B.PMEP,1) ) { + Store(\_SB.PC21.SR3B.PMEH(10), Local0) + } else { + Store (\_SB.PC21.SR3B.HPEH(10), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(10, Local1) + Notify(\_SB.PC21.SR3B, Local0) + } + + // PC21 Port 3C PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC21.SR3C.PMEP,1) ) { + Store(\_SB.PC21.SR3C.PMEH(11), Local0) + } else { + Store (\_SB.PC21.SR3C.HPEH(11), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(11, Local1) + Notify(\_SB.PC21.SR3C, Local0) + } + + // PC21 Port 3D PCI-Ex Hot Plug + // If PM_PME event clear INTs and AttnBtnPressed + If( LEqual(\_SB.PC21.SR3D.PMEP,1) ) { + Store(\_SB.PC21.SR3D.PMEH(12), Local0) + } else { + Store (\_SB.PC21.SR3D.HPEH(12), Local0) + } + If(Lnot(LEqual(Local0,0xFF))) { + Store(12, Local1) + Notify(\_SB.PC21.SR3D, Local0) + } + + //If a hotplug event was serviced check if this was generated by PM_PME + If (Lnot (LEqual(Local0, 0))) { + //Clear the status bit 16 of PMEStatus + //Clear the PME Pending bit 17 of PMEStatus + If( LEqual(Local1, 1)) { + Store(1, \_SB.PC01.BR1A.PMES) + Store(1, \_SB.PC01.BR1A.PMEP) + } + If( LEqual(Local1, 2)) { + Store(1, \_SB.PC01.BR1B.PMES) + Store(1, \_SB.PC01.BR1B.PMEP) + } + If( LEqual(Local1, 3)) { + Store(1, \_SB.PC01.BR1C.PMES) + Store(1, \_SB.PC01.BR1C.PMEP) + } + If( LEqual(Local1, 4)) { + Store(1, \_SB.PC01.BR1D.PMES) + Store(1, \_SB.PC01.BR1D.PMEP) + } + + If( LEqual(Local1, 5)) { + Store(1, \_SB.PC02.BR2A.PMES) + Store(1, \_SB.PC02.BR2A.PMEP) + } + If( LEqual(Local1, 6)) { + Store(1, \_SB.PC02.BR2B.PMES) + Store(1, \_SB.PC02.BR2B.PMEP) + } + If( LEqual(Local1, 7)) { + Store(1, \_SB.PC02.BR2C.PMES) + Store(1, \_SB.PC02.BR2C.PMEP) + } + If( LEqual(Local1, 8)) { + Store(1, \_SB.PC02.BR2D.PMES) + Store(1, \_SB.PC02.BR2D.PMEP) + } + If( LEqual(Local1, 9)) { + Store(1, \_SB.PC03.BR3A.PMES) + Store(1, \_SB.PC03.BR3A.PMEP) + } + If( LEqual(Local1, 10)) { + Store(1, \_SB.PC03.BR3B.PMES) + Store(1, \_SB.PC03.BR3B.PMEP) + } + If( LEqual(Local1, 11)) { + Store(1, \_SB.PC03.BR3C.PMES) + Store(1, \_SB.PC03.BR3C.PMEP) + } + If( LEqual(Local1, 12)) { + Store(1, \_SB.PC03.BR3D.PMES) + Store(1, \_SB.PC03.BR3D.PMEP) + } + + If( LEqual(Local1, 1)) { + Store(1, \_SB.PC06.QRP0.PMES) + Store(1, \_SB.PC06.QRP0.PMEP) + } + If( LEqual(Local1, 1)) { + Store(1, \_SB.PC07.QR1A.PMES) + Store(1, \_SB.PC07.QR1A.PMEP) + } + If( LEqual(Local1, 2)) { + Store(1, \_SB.PC07.QR1B.PMES) + Store(1, \_SB.PC07.QR1B.PMEP) + } + If( LEqual(Local1, 3)) { + Store(1, \_SB.PC07.QR1C.PMES) + Store(1, \_SB.PC07.QR1C.PMEP) + } + If( LEqual(Local1, 4)) { + Store(1, \_SB.PC07.QR1D.PMES) + Store(1, \_SB.PC07.QR1D.PMEP) + } + If( LEqual(Local1, 5)) { + Store(1, \_SB.PC08.QR2A.PMES) + Store(1, \_SB.PC08.QR2A.PMEP) + } + If( LEqual(Local1, 6)) { + Store(1, \_SB.PC08.QR2B.PMES) + Store(1, \_SB.PC08.QR2B.PMEP) + } + If( LEqual(Local1, 7)) { + Store(1, \_SB.PC08.QR2C.PMES) + Store(1, \_SB.PC08.QR2C.PMEP) + } + If( LEqual(Local1, 8)) { + Store(1, \_SB.PC08.QR2D.PMES) + Store(1, \_SB.PC08.QR2D.PMEP) + } + If( LEqual(Local1, 9)) { + Store(1, \_SB.PC09.QR3A.PMES) + Store(1, \_SB.PC09.QR3A.PMEP) + } + If( LEqual(Local1, 10)) { + Store(1, \_SB.PC09.QR3B.PMES) + Store(1, \_SB.PC09.QR3B.PMEP) + } + If( LEqual(Local1, 11)) { + Store(1, \_SB.PC09.QR3C.PMES) + Store(1, \_SB.PC09.QR3C.PMEP) + } + If( LEqual(Local1, 12)) { + Store(1, \_SB.PC09.QR3D.PMES) + Store(1, \_SB.PC09.QR3D.PMEP) + } + + If( LEqual(Local1, 1)) { + Store(1, \_SB.PC12.RRP0.PMES) + Store(1, \_SB.PC12.RRP0.PMEP) + } + If( LEqual(Local1, 1)) { + Store(1, \_SB.PC13.RR1A.PMES) + Store(1, \_SB.PC13.RR1A.PMEP) + } + If( LEqual(Local1, 2)) { + Store(1, \_SB.PC13.RR1B.PMES) + Store(1, \_SB.PC13.RR1B.PMEP) + } + If( LEqual(Local1, 3)) { + Store(1, \_SB.PC13.RR1C.PMES) + Store(1, \_SB.PC13.RR1C.PMEP) + } + If( LEqual(Local1, 4)) { + Store(1, \_SB.PC13.RR1D.PMES) + Store(1, \_SB.PC13.RR1D.PMEP) + } + If( LEqual(Local1, 5)) { + Store(1, \_SB.PC14.RR2A.PMES) + Store(1, \_SB.PC14.RR2A.PMEP) + } + If( LEqual(Local1, 6)) { + Store(1, \_SB.PC14.RR2B.PMES) + Store(1, \_SB.PC14.RR2B.PMEP) + } + If( LEqual(Local1, 7)) { + Store(1, \_SB.PC14.RR2C.PMES) + Store(1, \_SB.PC14.RR2C.PMEP) + } + If( LEqual(Local1, 8)) { + Store(1, \_SB.PC14.RR2D.PMES) + Store(1, \_SB.PC14.RR2D.PMEP) + } + If( LEqual(Local1, 9)) { + Store(1, \_SB.PC15.RR3A.PMES) + Store(1, \_SB.PC15.RR3A.PMEP) + } + If( LEqual(Local1, 10)) { + Store(1, \_SB.PC15.RR3B.PMES) + Store(1, \_SB.PC15.RR3B.PMEP) + } + If( LEqual(Local1, 11)) { + Store(1, \_SB.PC15.RR3C.PMES) + Store(1, \_SB.PC15.RR3C.PMEP) + } + If( LEqual(Local1, 12)) { + Store(1, \_SB.PC15.RR3D.PMES) + Store(1, \_SB.PC15.RR3D.PMEP) + } + + If( LEqual(Local1, 1)) { + Store(1, \_SB.PC18.SRP0.PMES) + Store(1, \_SB.PC18.SRP0.PMEP) + } + If( LEqual(Local1, 1)) { + Store(1, \_SB.PC19.SR1A.PMES) + Store(1, \_SB.PC19.SR1A.PMEP) + } + If( LEqual(Local1, 2)) { + Store(1, \_SB.PC19.SR1B.PMES) + Store(1, \_SB.PC19.SR1B.PMEP) + } + If( LEqual(Local1, 3)) { + Store(1, \_SB.PC19.SR1C.PMES) + Store(1, \_SB.PC19.SR1C.PMEP) + } + If( LEqual(Local1, 4)) { + Store(1, \_SB.PC19.SR1D.PMES) + Store(1, \_SB.PC19.SR1D.PMEP) + } + If( LEqual(Local1, 5)) { + Store(1, \_SB.PC20.SR2A.PMES) + Store(1, \_SB.PC20.SR2A.PMEP) + } + If( LEqual(Local1, 6)) { + Store(1, \_SB.PC20.SR2B.PMES) + Store(1, \_SB.PC20.SR2B.PMEP) + } + If( LEqual(Local1, 7)) { + Store(1, \_SB.PC20.SR2C.PMES) + Store(1, \_SB.PC20.SR2C.PMEP) + } + If( LEqual(Local1, 8)) { + Store(1, \_SB.PC20.SR2D.PMES) + Store(1, \_SB.PC20.SR2D.PMEP) + } + If( LEqual(Local1, 9)) { + Store(1, \_SB.PC21.SR3A.PMES) + Store(1, \_SB.PC21.SR3A.PMEP) + } + If( LEqual(Local1, 10)) { + Store(1, \_SB.PC21.SR3B.PMES) + Store(1, \_SB.PC21.SR3B.PMEP) + } + If( LEqual(Local1, 11)) { + Store(1, \_SB.PC21.SR3C.PMES) + Store(1, \_SB.PC21.SR3C.PMEP) + } + If( LEqual(Local1, 12)) { + Store(1, \_SB.PC21.SR3D.PMES) + Store(1, \_SB.PC21.SR3D.PMEP) + } + + Store(0x01,PEES) //Clear bit 9 of Status + Store(0x00,PMEE) //Clear bit 9 of GPE0_EN + } diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieRootPortHotPlug.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieRootPortHotPlug.asl new file mode 100644 index 0000000000..e6dc91db33 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/IioPcieRootPortHotPlug.asl @@ -0,0 +1,692 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + +//;************************************************************************; +//; IMPORTANT NOTE: +//; Code in this file should be generic/common for any IIO PCIe root port. +//; DO NOT use hard-coded Bus/Dev/Function # in this file. +//; +//;************************************************************************; + + + + Name(DBFL, 0) // Debug flag 0/1 = disable/enable debug checkpoints in this file + + + + //;************************************************************************; + //; This DVPS() method detects if the root port is present and hot-plug capable. + //; Input : None + //; Output: Non-zero - Root port is present and hot-plug capable + //; Zero - otherwise + //;************************************************************************; + Method(DVPS,0) { + // Check if VID/DID = 3C0x_8086 to see if the root port exists + If (LNotEqual(VID, 0x8086)) { Return(Zero) } + //If( LNotEqual(And(DID, 0xFFF0), 0x3C00)) { Return(Zero) } + If( LNotEqual(And(DID, 0xFFF0), 0x2F00)) { Return(Zero) } //HSX + // Check the root port to see if slot is implemented and Hot-Plug Capable + If(LNot(And(SLIP, HPCP))) { Return(Zero) } + Return (One) + } + + + //;************************************************************************; + //; This HPEN() method programs "Enable ACPI mode for Hot-plug" bit based on input Arg0 + //; See IIO PCIe rootport MISCCTRLSTS register 188h[3] definition + //; Input : 0/1 bit value to set "Enable ACPI mode for Hot-plug" (IIO PCIe rootport register 188h[3]) + //; Output: None + //;************************************************************************; + Method (HPEN, 1, Serialized) { + + DB55(0x71, 0) // debug point + + // get Bus/Dev/Func information of this root port + Store(^^_BBN, Local0) // Local0 = Bus# of parent Host bus + //Store(_BBN, Local0) // implicit reference to PC00._BBN + ShiftRight(_ADR, 16, Local1) // Local1 = self Device # + And(_ADR, 0x0000ffff, Local2) // Local2 = self Function # + + // Calculate MMCFG config address of MISCCTRLSTS register at B:D:F:offset 188h + //Name (MISR, 0xC0000188) + Name (MISR, 0) // create a pointer to MMCFG region space + Add(MMBS, 0x188, MISR) // MISR = MMCFG_BASE_ADDR + Offset of MISCCTRLSTS CSR + Add(ShiftLeft(Local0, 20), MISR, MISR) // Build bus/dev/func number fields of MISR + Add(ShiftLeft(Local1, 15), MISR, MISR) + Add(ShiftLeft(Local2, 12), MISR, MISR) + + DB55(0x77, MISR) // debug point + + + // Create OpRegion for MISCCTRLSTS register at B:D:F:offset 188h + OperationRegion (OP37, SystemMemory, MISR, 0x04) + Field (OP37, DWordAcc, NoLock, Preserve) { + , 3, + HGPE, 1, // "Enable ACPI mode for Hot-plug" (register 188h[3]) + } + + // Program "Enable ACPI mode for Hot-plug" bit to input Arg0 + Store(Arg0, HGPE) + } + + //;************************************************************************; + //; This DB55() method is a debug method + //; Input : Arg0 Postcode to be sent to IO Port 80h + //; Arg1 DWord data to be copied to debug memory location + //; in BIOS Data Area (DBA) 40:42 + //; Output: None + //;************************************************************************; + Method (DB55, 2, NotSerialized) { + + If (DBFL) { // if debug is enabled + Store(Arg0, IO80) // send postcode to port 80h + Store(Arg1, MDWD) // store Arg1 to debug memory location + Sleep(4000) // stall for 4 seconds + } + } + + OperationRegion (OP38, SystemMemory, 0x442, 0x04) + Field (OP38, AnyAcc, NoLock, Preserve) { + MDWD, 32, // dword at BIOS Data Area (BDA) 40:42 (floppy task-file), used as debug memory location + } + + + Method (_INI, 0, NotSerialized) { + + If (LEqual(Zero,DVPS)) { + Return // Do nothing if this root port is not "Present and Hot-plugable" + } + HPEN(1) // No. Enable ACPI Hot-plug events + } + + +/* Greencity code + OperationRegion (MCTL, SystemMemory, 0xA0048188, 0x04) + Field (MCTL, ByteAcc, NoLock, Preserve) { + , 3, + HGPE, 1, + , 7, + , 8, + , 8 + } + + Method (_INI, 0, NotSerialized) { + Store (0x01, HGPE) //enable GPE message generation for ACPI hotplug support + } +*/ + +//MCWU Changed ^HP02 to HP02 to avoid re-definition when this file is included under multiple BRxx devices + //Name(^HP02, Package(4){0x08, 0x40, 1, 0} ) + Name(HP02, Package(4){0x08, 0x40, 1, 0} ) + Method(_HPP, 0) { return(HP02) } + + // + // begin hotplug code + // + Name(SHPC, 0x40) // Slot Hot-plug Capable + + Name(SPDS, 0x040) // Slot Presence Detect State + + Name(MRLS, 0x0) // MRL Closed, Standby Power to slot is on + Name(CCOM, 0x010) // Command Complete + Name(SPDC, 0x08) // Slot Presence Detect Changes + Name(MRLC, 0x04) // Slot MRL Changed + Name(SPFD, 0x02) // Slot Power Fault Detected + Name(SABP, 0x01) // Slot Attention Button Pressed + + Name(SPOF, 0x10) // Slot Power Off + Name(SPON, 0x0F) // Slot Power On Mask + + Name(ALMK, 0x1C) // Slot Atten. LED Mask + Name(ALON, 0x01) // Slot Atten. LED On + Name(ALBL, 0x02) // Slot Atten LED Blink + Name(ALOF, 0x03) // Slot Atten LED Off + + Name(PLMK, 0x13) // Slot Pwr. LED Mask + Name(PLON, 0x04) // Slot Pwr. LED On + Name(PLBL, 0x08) // Slot Pwr. LED Blink + Name(PLOF, 0x0C) // Slot Pwr. LED Off + + //;************************************* + //; Bit 3 = Presence Detect Event + //; Bit 2 = MRL Sensor Event + //; Bit 1 = PWR Fault Event + //; Bit 0 = Attention Button Event + //;************************************* + Name(HPEV, 0xF) // Possible interrupt events (all) + + //;************************************************************************; + //; + //; PCIe Slot Capabilities Register A4-A7h + //; Bit - 31-7 - Not used + //; Bit - 6 - Hot-Plug Capable + //; Bit - 5 - Hot-Plug Surprise + //; Bit - 4 - Power Indicator Present. + //; Bit - 3 - Attention Indicator Present. + //; Bit - 2 - MRL Sensor Present. + //; Bit - 1 - Power Controller Present. + //; Bit - 0 - Attention Button Present. + //; + //; PCIe Slot control Register A8-A9h + //; + //; Bit - 10 - PWR Control Disable + //; Bit - 9:8 - Attn Indicator + //; Bit - 7:6 - PWR Indicator + //; Bit - 5 - Hot-Plug Interrupt Event Enable + //; Bit - 4 - Command Complete Interrupt enable + //; Bit - 3 - Presence Detect Changed Interrupt enable + //; Bit - 2 - MRL Sensor Changed Interrupt enable + //; Bit - 1 - PwrFault Detect Interrupt enable + //; Bit - 0 - Attention Button Pressed Interrupt Enable + //; + //; PCIe Slot Status Registers AA-ADh + //; + //; Bit - 6 - Presence Detect State. + //; Bit - 5 - MRL Sensor State. + //; Bit - 4 - Command Completed. + //; + //; RWC Status Bits + //; + //; Bit - 3 - Presence Detect Changed. + //; Bit - 2 - MRL Sensor Changed. + //; Bit - 1 - Power Fault Detected. + //; Bit - 0 - Attention Button Pressed. + //;************************************************************************; + + OperationRegion(PPA4, PCI_Config, 0x00, 0x0ff) + Field(PPA4,ByteAcc,NoLock,Preserve) { + + Offset(0x00), // VenderID/DeviceID register + VID, 16, // VID = 0x8086 + DID, 16, // Device IDs for IIO PCI Express root ports are as follows: + // 0x3C00: DMI mode 0x3C01: the DMI port running in PCIe mode + // 0x3C02: Port 1a + // 0x3C03: Port 1b + // 0x3C04: Port 2a + // 0x3C05: Port 2b + // 0x3C06: Port 2c + // 0x3C07: Port 2d + // 0x3C08: Port 3a in PCIe mode + // 0x3C09: Port 3b + // 0x3C0A: Port 3c + // 0x3C0B: Port 3d + // (0x3C0F: IIO NTB Secondary Endpoint) + + Offset(0x92), // PXPCAP - PCIe CAP Register + , 8, + SLIP, 1, // bit8 Slot Implemented + + offset(0xA4), // SLTCAP - Slot Capabilities Register + ATBP,1, // bit0 Attention Button Present + PWCP,1, // bit1 Power Controller Present + MRSP,1, // bit2 MRL Sensor Present + ATIP,1, // bit3 Attention Indicator Present + PWIP,1, // bit4 Power Indicator Present + HPSR,1, // bit5 Hot-Plug Surprise + HPCP,1, // bit6 Hot-Plug Capable + + offset(0xA8), // SLTCON - PCIE Slot Control Register + ABIE,1, // bit0 Attention Button Pressed Interrupt Enable + PFIE,1, // bit1 Power Fault Detected Interrupt Enable + MSIE,1, // bit2 MRL Sensor Changed Interrupt Enable + PDIE,1, // bit3 Presence Detect Changed Interrupt Enable. + CCIE,1, // bit4 Command Complete Interrupt Enable. + HPIE,1, // bit5 Hot-plug Interrupt Enable. + SCTL,5, // bit[10:6] Attn/Power indicator and Power controller. + + offset(0xAA), // SLTSTS - PCIE Slot Status Register + SSTS,7, // The status bits in Slot Status Reg + ,1, +} + + OperationRegion(PPA8, PCI_Config, 0x00, 0x0ff) + Field(PPA8,ByteAcc,NoLock,Preserve) { + Offset(0xA8), // SLTCON - PCIE Slot Control Register + ,6, + ATID,2, // bit[7:6] Attention Indicator Control. + PWID,2, // bit[9:8] Power Indicator Control. + PWCC,1, // bit[10] Power Controller Control. + ,5, + Offset(0xAA), // SLTSTS - PCIE Slot status Register (WRC) + ABPS,1, // bit0 Attention Button Pressed Status (RWC) + PFDS,1, // bit1 Power Fault Detect Status (RWC) + MSCS,1, // bit2 MRL Sensor Changed Status + PDCS,1, // bit3 Presence Detect Changed Status + CMCS,1, // bit4 Command Complete Status + MSSC,1, // bit5 MRL Sensor State + PRDS,1, // bit6 Presence Detect State + ,1, + } + + //;************************************************************************; + //; This OSHP (Operating System Hot Plug) method is provided for each HPC + //; which is controlled by ACPI. This method disables ACPI access to the + //; HPC and restores the normal System Interrupt and Wakeup Signal + //; connection. + //;************************************************************************; + Method(OSHP) { // OS call to unhook Legacy ASL PCI-Express HP code. + Store(SSTS, SSTS) // Clear any status +// Store(0x0, HGPE) // Disable GPE generation + HPEN(0) // Disable GPE generation + } + + //;************************************************************************; + //; Hot Plug Controller Command Method + //; + //; Input: Arg0 - Command to issue + //; + //;************************************************************************; + Method(HPCC,1) { + Store(SCTL, Local0) // get current command state + Store(0, Local1) // reset the timeout value + If(LNotEqual(Arg0, Local0)) { // see if state is different + Store(Arg0, SCTL) // Update the Slot Control + While(LAnd (LNot(CMCS), LNotEqual(100, Local1))) { // spin while CMD complete bit is not set, + // check for timeout to avoid dead loop + Store(0x2C, IO80) + Sleep(2) // allow processor time slice + Add(Local1, 2, Local1) + } + Store(0x1, CMCS) // Clear the command complete status + } + } + + //;************************************************************************; + //; Attention Indicator Command + //; + //; Input: Arg0 - Command to issue + //; 1 = ON + //; 2 = Blink + //; 3 = OFF + //;************************************************************************; + Method(ATCM,1) { + Store(SCTL, Local0) // Get Slot Control + And(Local0, ALMK, Local0) // Mask the Attention Indicator Bits + If(LEqual(Arg0, 0x1)){ // Attenion indicator "ON?" + Or(Local0, ALON, Local0) // Set the Attention Indicator to "ON" + } + If(LEqual(Arg0, 0x2)){ // Attenion indicator "BLINK?" + Or(Local0, ALBL, Local0) // Set the Attention Indicator to "BLINK" + } + If(LEqual(Arg0, 0x3)){ // Attenion indicator "OFF?" + Or(Local0, ALOF, Local0) // Set the Attention Indicator to "OFF" + } + HPCC(Local0) + } + + //;************************************************************************; + //; Power Indicator Command + //; + //; Input: Arg0 - Command to issue + //; 1 = ON + //; 2 = Blink + //; 3 = OFF + //;************************************************************************; + Method(PWCM,1){ + Store(SCTL, Local0) // Get Slot Control + And(Local0, PLMK, Local0) // Mask the Power Indicator Bits + If(LEqual(Arg0, 0x1)){ // Power indicator "ON?" + Or(Local0, PLON, Local0) // Set the Power Indicator to "ON" + } + If(LEqual(Arg0, 0x2)){ // Power indicator "BLINK?" + Or(Local0, PLBL, Local0) // Set the Power Indicator to "BLINK" + } + If(LEqual(Arg0, 0x3)){ // Power indicator "OFF?" + Or(Local0, PLOF, Local0) // Set the Power Indicator to "OFF" + } + HPCC(Local0) + } + + //;************************************************************************; + //; Power Slot Command + //; + //; Input: Arg0 - Command to issue + //; 1 = Slot Power ON + //; 2 = Slot Power Off + //;************************************************************************; + Method(PWSL,1){ + Store(SCTL, Local0) // Get Slot Control + If(Arg0){ // Power Slot "ON" Arg0 = 1 + And(Local0, SPON, Local0) // Turns the Power "ON" + } Else { // Power Slot "OFF" + Or(Local0, SPOF, Local0) // Turns the Power "OFF" + } + HPCC(Local0) + } + + //;************************************************************************; + //; _OST Methods to indicate that the device Eject/insert request is + //; pending, OS could not complete it + //; + //; Input: Arg0 - Value used in Notify to OS + //; 0x00 - card insert + //; 0x03 - card eject + //; Arg1 - status of Notify + //; 0 - success + //; 0x80 - Ejection not supported by OSPM + //; 0x81 - Device in use + //; 0x82 - Device Busy + //; 0x84 - Ejection in progress-pending + //;************************************************************************; + Method(_OST,3,Serialized) { + Switch(And(Arg0,0xFF)) { // Mask to retain low byte + Case(0x03) { // Ejection Request + Switch(ToInteger(Arg1)) { + Case(Package() {0x80, 0x81, 0x82, 0x83}) { + // + // Ejection Failure for some reason + // + If (Lnot(PWCC)) { // if slot is powered + PWCM(0x1) // Set PowerIndicator to ON + Store(0x1,ABIE) // Set AttnBtn Interrupt ON + } + } + } + } + } + } // End _OST + + //;************************************************************************; + //; Eject Control Methods to indicate that the device is hot-ejectable and + //; should "eject" the device. + //; + //; Input: Arg0 - Not use. + //; + //;************************************************************************; + Method(EJ02, 1){ + Store(0xFF, IO80) + Store(SCTL, Local0) // Get IOH Port 9/SLot3 Control state + if( LNot( LEqual( ATID, 1))) { // Check if Attention LED is not solid "ON" + And(Local0, ALMK, Local0) // Mask the Attention Indicator Bits + Or(Local0, ALBL, Local0) // Set the Attention Indicator to blink + } + HPCC(Local0) // issue command + + Store(SCTL, Local0) // Get IOH Port 9/SLot3 Control state + Or(Local0, SPOF, Local0) // Set the Power Controller Control to Power Off + HPCC(Local0) + + Store(SCTL, Local0) // Get PEXH Port 9/SLot3 Control state + Or(Local0, PLOF, Local0) // Set the Power Indicator to Off. + HPCC(Local0) + } // End of EJ02 + + //;************************************************************************; + //; PM_PME Wake Handler for Slot 3 only + //; + //; Input: Arg0 - Slot Number + //; + //;************************************************************************; + Method(PMEH,1){ // Handler for PCI-E PM_PME Wake Event/Interrupt (GPI xxh) + If(And(HPEV, SSTS)){ // Check for Hot-Plug Events + If(ABPS) { + Store (Arg0, IO80) // Send slot number to Port 80 + Store(0x1, ABPS) // Clear the interrupt status + Sleep(200) // delay 200ms + } + } + Return (0xff) // Indicate that this controller did not interrupt + } // End of Method PMEH + + //;************************************************************************; + //; Hot-Plug Handler for an IIO PCIe root port slot + //; + //; Input: Arg0 - Slot Numnber (not used) + //; Output: + //; 0xFF - No hotplug event detected + //; 0x03 - Eject Request detected + //; 0x00 - Device Presence Changed + //; + //;************************************************************************; + Method(HPEH,1){ // Handler for PCI-E Hot-Plug Event/Interupt Called from \_SB.GPE._L01() + + If (LEqual(Zero,DVPS)) { + Return (0xff) // Do nothing if root port is not "Present and Hot-plugable" + } + + Store(0x22, IO80) + Sleep(100) + Store(0,CCIE) // Disable command interrupt + If(And(HPEV, SSTS)){ // Check for Hot-Plug Events + Store(0x3A, IO80) + Sleep(10) + Store(PP3H(0x0), Local0) // Call the Slot 3 Hot plug Interrupt Handler + Return(Local0) // Return PP2H information + } + Else{ + Return (0xff) // Indicate that this controller did not interrupt + } + Store(0x2F, IO80) + Sleep(10) + } // End of Method HPEH + + //;************************************************************************; + //; Interrut Event Handler + //; + //; Input: Arg0 - Slot Numnber + //; + //;************************************************************************; + Method(PP3H,1){ // Slot 3 Hot plug Interrupt Handler + // + // Check for the Atention Button Press, Slot Empty/Presence, Power Controller Control. + // + Sleep(200) // HW Workaround for AttentionButton Status to stabilise + If(ABPS) { // Check if Attention Button Pressed for Device 4 + If(LNot(PRDS)) { // See if nothing installed (no card in slot) + PWSL(0x0) // make sure Power is Off + PWCM(0x3) // Set Power Indicator to "OFF" + // + // Check for MRL here and set attn indicator accordingly + // + If(LEqual(MSSC,MRLS)) { // Standby power is on - MRL closed + ATCM(0x2) // Set Attention Indicator to "BLINK" + } else { // Standby power is off - MRL open + ATCM(0x3) // set attention indicator "OFF" + } + Store(0x0, ABIE) // set Attention Button Interrupt to disable + Store(0x1, ABPS) // Clear the interrupt status + Sleep(200) // delay 200ms + Return(0xff) // Attn Button pressed without card in slot. Do nothing + } + // + // Card is present in slot so.... + // + Store(0x0, ABIE) // set Attention Button Interrupt to disable + // Attn Btn Interrupt has to be enabled only after an insert oprn + Store(0x1, ABPS) // Clear the interrupt status + Sleep(200) // delay 200ms + // + // Check for MRL here - only if SPWR is OFF blink AttnInd and retun 0xff + // + If(LNot(LEqual(MSSC,MRLS))) { // Standby power is off + PWSL(0x0) // make sure Power is Off + PWCM(0x3) // Set Power Indicator to "OFF" + ATCM(0x2) // Set Attention Indicator to "BLINK" + Return(0xff) // Attn Button pressed with card in slot, but MRL open. Do nothing + } + //Card Present, if StandbyPwr is ON proceed as below with Eject Sequence + If(PWCC) { // Slot not Powered + PWCM(0x3) // Set Power Indicator to "OFF" + ATCM(0x2) // Set Attention Indicator to "BLINK" + Return(0xff) // Attn Button pressed with card in slot, MRL closed, Slot not powered. Do nothing + } else { // See if Slot is already Powered + PWCM(0x2) // Set power Indicator to BLINK + Sleep(600) // Wait 100ms + Store(600, Local0) // set 5 second accumulator to 0 + Store(0x1, ABPS) // Clear the interrupt status + Sleep(200) // delay 200ms + While(LNot(ABPS)) { // check for someone pressing Attention + Sleep(200) // Wait 200ms + Add(Local0, 200, Local0) + If(LEqual(5000, Local0)) { // heck if 5sec has passed without pressing attnetion btn + Store(0x1, ABPS) // Clear the interrupt status + Sleep(200) // delay 200ms + Return (0x3) // continue with Eject request + } + } + PWCM(0x1) // Set power Indicator baCK "ON" + Store(0x1, ABPS) // Clear the Attention status + Sleep(200) // delay 200ms + Store(0x1, ABIE) // set Attention Button Interrupt to enable + Return (0xff) // do nothing and abort + } + } // End if for the Attention Button Hot Plug Interrupt. + + If(PFDS) { // Check if Power Fault Detected + Store(0x1, PFDS) // Clear the Power Fault Status + PWSL(0x0) // set Power Off + PWCM(0x3) // set power indicator to OFF + ATCM(0x1) // set attention indicator "ON" + Return(0x03) // Eject request. + } // End if for the Power Fault Interrupt. + + If(MSCS) { // Check interrupt caused by the MRL Sensor + Store(0x1, MSCS) // Clear the MRL Status + If(LEqual(MSSC,MRLS)) { // Standby power is on - MRL closed + If(PRDS) { // Card is Present + // Slot Power is Off, so power up the slot + ATCM(0x3) // Set Attention Indicator to off + PWCM(0x2) // Set Power Indicator to Blink + Sleep(600) // Wait 100ms + Store(600, Local0) // set 5 second accumulator to 0 + Store(0x1, ABPS) // Clear the interrupt status + While(LNot(ABPS)) { // check for someone pressing Attention + Sleep(200) // Wait 200ms + Add(Local0, 200, Local0) + If(LEqual(5000, Local0)) { // Check if 5 sec elapsed + Store(0x1, ABIE) // Enable Attention button interrupt + ATCM(0x3) // set attention indicator "OFF" + PWSL(0x1) // Power the Slot + Sleep(500) // Wait for .5 Sec for the Power to Stabilize. + // Check for the Power Fault Detection + If(LNot(PFDS)) { // No Power Fault + PWCM(0x1) // Set Power Indicator to "ON" + // Or(LVLS, 0x000010000, LVLS) // Enable the Device 4 Slot Clock (GPIO16) + // Notify the OS to load the Driver for the card + Store(0x00, Local1) + Store(0x1, ABIE) // Enable Attention button interrupt + } Else { // Power Fault present + PWSL(0x0) // set Slot Power Off + PWCM(0x3) // set power indicator to OFF + ATCM(0x1) // set attention indicator "ON" + // And (LVLS, 0x0FFFEFFFF, LVLS) // Disable the Device 4 Slot Clock (GPIO16) + Store(0x03, Local1) // Eject request. + } // End if for the Slot Power Fault + Store(0x1, ABPS) // Clear the Attention status + Sleep(200) // delay 200ms + Return(Local1) + } + } + // + // someone pressed Attention Button + // + Store(0x1, ABPS) // Clear the Attention status + Sleep(200) // delay 200ms + PWSL(0x0) // Set Slot Power off + PWCM(0x3) // Set Power Indicator back to "OFF" + ATCM(02) // Set Attention Indicator to "BLINK" + Return(0xff) // leave it off + // End of Insert sequence + } + //MRL is closed, Card is not present + PWSL(0x0) // Set Slot Power off + PWCM(0x3) // Set Power Indicator back to "OFF" + ATCM(02) // Set Attention Indicator to "BLINK" + Return(0xff) // leave it off + } else { // MRL is open i.e Stdby power is turned off + If(PRDS) { + //card present MRL switched off + ATCM(0x2) // Set Attention Indicator to "BLINK" + If(Lnot(PWCC)) { // If slot is powered + // This event is not supported and someone has opened the MRL and dumped the power + // on the slot with possible pending transactions. This could hose the OS. + // Try to Notify the OS to unload the drivers. + PWSL(0x0) // Set Slot Power off + PWCM(0x3) // Set Power Indicator back to "OFF" + Return(0x03) // Eject request. + } else { // Slot not powered, MRL is opened, card still in slot - Eject not fully complete + Return(0xFF) + } + } + //no card present and Stdby power switched off, turn AI off + ATCM(0x3) // Set Attention Indicator to "OFF" + Return(0xff) // leave it off + } // End of MRL switch open/close state + } // End of MRL Sensor State Change + + If(PDCS) { // Check if Presence Detect Changed Status + Store(0x1, PDCS) // Clear the Presence Detect Changed Status + If(LNot(PRDS)) { // Slot is Empty + PWSL(0x0) // Set Slot Power "OFF" + PWCM(0x3) // set power indicator to "OFF" + If(LEqual(MSSC,MRLS)) { // If Standby power is on + ATCM(0x2) // Set Attention Indicator to "Blink" + } else { + ATCM(0x3) // Set Attention Indicator to "OFF" + } + Return(0xFF) // Do nothing + } Else { // Slot Card is inserted + // Irrespective of MRL state blink indicator + PWSL(0x0) // Set Slot Power off + PWCM(0x3) // Set Power Indicator back to "OFF" + ATCM(0x2) // Set Attention Indicator to "Blink" + Return(0xFF) // Do nothing + } + } // End if for the Presence Detect Changed Hot Plug Interrupt. + Return(0xff) // should not get here, but do device check if it does. + } // End of method PP5H + // + // End of hotplug code + // + + Device(H000) { + Name(_ADR, 0x00000000) + Name(_SUN, 0x0002) // Slot User Number + Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot + } + Device(H001) { + Name(_ADR, 0x00000001) + Name(_SUN, 0x0002) // Slot User Number + Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot + } + Device(H002) { + Name(_ADR, 0x00000002) + Name(_SUN, 0x0002) // Slot User Number + Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot + } + Device(H003) { + Name(_ADR, 0x00000003) + Name(_SUN, 0x0002) // Slot User Number + Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot + } + Device(H004) { + Name(_ADR, 0x00000004) + Name(_SUN, 0x0002) // Slot User Number + Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot + } + Device(H005) { + Name(_ADR, 0x00000005) + Name(_SUN, 0x0002) // Slot User Number + Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot + } + Device(H006) { + Name(_ADR, 0x00000006) + Name(_SUN, 0x0002) // Slot User Number + Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot + } + Device(H007) { + Name(_ADR, 0x00000007) + Name(_SUN, 0x0002) // Slot User Number + Method(_EJ0, 1) { EJ02(Arg0) } // Remove all power from the slot + } diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl new file mode 100644 index 0000000000..b6a7188cbb --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl @@ -0,0 +1,38 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// ITSS +// Define the needed ITSS registers used by ASL on Interrupt +// mapping. + +scope(\_SB){ + OperationRegion(ITSS, SystemMemory, 0xfdc43100, 0x208) + Field(ITSS, ByteAcc, NoLock, Preserve) + { + PARC, 8, + PBRC, 8, + PCRC, 8, + PDRC, 8, + PERC, 8, + PFRC, 8, + PGRC, 8, + PHRC, 8, + Offset(0x200), // Offset 3300h ITSSPRC - ITSS Power Reduction Control + , 1, + , 1, + SCGE, 1, // ITSSPRC[2]: 8254 Static Clock Gating Enable (8254CGE) + + } +} + + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Mother.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Mother.asi new file mode 100644 index 0000000000..46abd5706c --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Mother.asi @@ -0,0 +1,208 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Device (DMAC) { + Name (_HID, EISAID("PNP0200")) + Name (_CRS,ResourceTemplate() { + IO(Decode16, 0x0, 0x0, 0, 0x10) + IO(Decode16, 0x81, 0x81, 0, 0x3) + IO(Decode16, 0x87, 0x87, 0, 0x1) + IO(Decode16, 0x89, 0x89, 0, 0x3) + IO(Decode16, 0x8f, 0x8f, 0, 0x1) + IO(Decode16, 0xc0, 0xc0, 0, 0x20) + DMA(Compatibility,NotBusMaster,Transfer8) {4} + }) +} + +Device (RTC) { + Name (_HID,EISAID("PNP0B00")) + Name (_CRS,ResourceTemplate() { + IO(Decode16,0x70,0x70,0x01,0x02) + IO(Decode16,0x74,0x74,0x01,0x04) + IRQNoFlags(){8} + }) +} + +Device (PIC) { + Name (_HID,EISAID("PNP0000")) + Name (_CRS,ResourceTemplate() { + IO(Decode16,0x20,0x20,0x01,0x1E) // length of 1Eh includes all aliases + IO(Decode16,0xA0,0xA0,0x01,0x1E) + IO(Decode16,0x4D0,0x4D0,0x01,0x02) + }) +} + +Device (FPU) { + Name (_HID,EISAID("PNP0C04")) + Name (_CRS,ResourceTemplate() { + IO(Decode16,0xF0,0xF0,0x01,0x1) + IRQNoFlags(){13} + }) +} + +Device(TMR) +{ + Name(_HID,EISAID("PNP0100")) + + Name(_CRS,ResourceTemplate() { + IO(Decode16,0x40,0x40,0x01,0x04) + IO(Decode16,0x50,0x50,0x01,0x04) // alias + IRQNoFlags(){0} + }) +} + +Device (SPKR) { + Name (_HID,EISAID("PNP0800")) + Name (_CRS,ResourceTemplate() { + IO(Decode16,0x61,0x61,0x01,0x01) + }) +} + +// +// all "PNP0C02" devices- pieces that don't fit anywhere else +// +Device(XTRA) { + Name(_HID,EISAID("PNP0C02")) // Generic motherboard devices + Name(_CRS, + ResourceTemplate() { + IO(Decode16,0x500,0x500,0x01,0x40) // GPIO space, ICH5 + IO(Decode16,0x400,0x400,0x01,0x80) // PM IO, ICH5 + IO(Decode16,0x92,0x92,0x01,0x01) // INIT & Fast A20 port, ICH5 + // + // Resource conflict with COM Port + // + //IO(Decode16,0x680,0x680,0x01,0x80) // Runtime registers, National SIO + IO(Decode16,0x10,0x10,0x01,0x10) + IO(Decode16,0x72,0x72,0x01,0x02) + IO(Decode16,0x80,0x80,0x01,0x01) + IO(Decode16,0x84,0x84,0x01,0x03) + IO(Decode16,0x88,0x88,0x01,0x01) + IO(Decode16,0x8c,0x8c,0x01,0x03) + IO(Decode16,0x90,0x90,0x01,0x10) + // + // SMBus decode range + // + IO(Decode16,0x540,0x540,0x01,0x40) + // + // Pilot Mail Box decode range + // + IO(Decode16,0x600,0x600,0x01,0x20) + // + // BMC KCS decode range + // + IO(Decode16,0xCA0,0xCA0,0x01,0x6) + // + // Performance Status and control ports decode range + // + IO(Decode16,0x880,0x880,0x01,0x4) + + //IO Descriptor added for range 800-81f for S501302 + IO(Decode16,0x800,0x800,0x01,0x20) + //IO Descriptor added for range 2F8-2FF for S501706 + //IO(Decode16,0x2F8,0x2F8,0x01,0x08) + //IO(Decode16,0x60,0x60,0x01,0x01) + //IO(Decode16,0x64,0x64,0x01,0x01) + + //PCH_ACPI_FLAG: RCBA is not supported in SPT + // + // RCBA memory range + // + //Memory32Fixed (ReadOnly, 0xFED1C000, 0x6FFFF) // ICH9 bios spec section 5.10 - reserved memory address space. + Memory32Fixed (ReadOnly, 0xFED1C000, 0x24000) // ICH9 bios spec section 5.10 - reserved memory address space. + // Leave FED40000-FED45000 for TPM + Memory32Fixed (ReadOnly, 0xFED45000, 0x47000) // ICH9 bios spec section 5.10 - reserved memory address space. + + // + // FLASH range + // + Memory32Fixed (ReadOnly, 0xFF000000, 0x1000000) //16MB as per IIO spec + + // + // Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) + // + Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000) + + // + // HECI range, 32 bytes from HECI1_BASE_ADDRESS (0xFE90_0000 to 0xFE90_001F) + // + //Memory32Fixed (ReadWrite, 0xFE900000, 0x20) + Memory32Fixed (ReadWrite, 0xFED12000, 0x10) + + // + // HECI range, 32 bytes from HECI2_BASE_ADDRESS (0xFEA0_0000 to 0xFEA0_001F) + // + //Memory32Fixed (ReadWrite, 0xFEA00000, 0x20) + Memory32Fixed (ReadWrite, 0xFED12010, 0x10) + + // + // IIO RCBA memory range + // + Memory32Fixed (ReadOnly, 0xFED1B000, 0x1000) + } + ) +} + +// +// High Performance Event Timer (HPET) +// +Device (HPET) { + Name (_HID, EisaId ("PNP0103")) + + Method (_STA, 0, NotSerialized) { + If (\HPTE) { + Return (0x0F) + } Else { + Return (0x00) + } + } + + Name (CRS0, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400) + }) + + Name (CRS1, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xFED01000, 0x00000400) + }) + + Name (CRS2, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xFED02000, 0x00000400) + }) + + Name (CRS3, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xFED03000, 0x00000400) + }) + + // + // Owning control method can't be re-entrant, so _CRS must be Serialized + // + Method (_CRS, 0, Serialized) { + Switch (ToInteger(\HPTB)) { + Case (0xFED00000) { + Return (CRS0) + } + + Case (0xFED01000) { + Return (CRS1) + } + + Case (0xFED02000) { + Return (CRS2) + } + + Case (0xFED03000) { + Return (CRS3) + } + } + Return (CRS0) + } +} \ No newline at end of file diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Os.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Os.asi new file mode 100644 index 0000000000..2492a1726c --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Os.asi @@ -0,0 +1,151 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope (\_SB) { + + Name (XCNT, 0) + Name (OSYS, 0) // Global variable for type of OS. + + // + // Device specific method + // + Method (_DSM, 4, Serialized) { + If (LEqual(Arg0,ToUUID("663E35AF-CC10-41A4-88EA-5470AF055295"))){ + + // L1 DIR POINTER + Switch (ToInteger(Arg2)) { + // + //Function 0: Return supported functions, based on revision + // + Case(0) + { + Switch (ToInteger(Arg1)) { + Case(0) { + If (Lequal(EMCA,1)) + { + Return ( Buffer() {0x3} ) + } + Else + { + Return (Buffer() {0}) + } + } + } + + } + // + // Function 1: + // + Case(1) {Return (LDIR) } + Default { } + } + } + + Return (Buffer() {0}) + } + + Method (_INI) { + + If (CondRefOf (_OSI)) { + + If (\_OSI ("Windows 2001.1 SP1")) { + Store (5, OSYS) // Windows Server 2003 SP1 + } + + If (\_OSI ("Windows 2001.1")) { + Store (6, OSYS) // Windows Server 2003 + } + + If (\_OSI ("Windows 2001 SP2")) { + Store (7, OSYS) // Windows XP SP2 + } + + If (\_OSI ("Windows 2001")) { + Store (8, OSYS) // Windows XP + } + + If (\_OSI ("Windows 2006.1")) { + Store (9, OSYS) // Windows Server 2008 + } + + If (\_OSI ("Windows 2006 SP1")) { + Store (10, OSYS) // Windows Vista SP1 + } + + If (\_OSI ("Windows 2006")) { + Store (11, OSYS) // Windows Vista + } + + If (\_OSI ("Windows 2009")) { + Store (12, OSYS) // Windows Server 2008 R2 & Windows 7 + } + + If (\_OSI ("Windows 2012")) { + Store (13, OSYS) // Windows Server 2012 & Windows 8 + } + + If (\_OSI ("Windows 2013")) { + Store (14, OSYS) // Windows Server 2012 R2 & Windows 8.1 + } + + If (\_OSI ("Windows 2015")) { + Store (15, OSYS) // Windows 10 & Windows Server Technical Preview + } + + If (\_OSI ("Windows 2016")) { + Store (16, OSYS) // Windows 10, version 1607 + } + + If (\_OSI ("Windows 2017")) { + Store (17, OSYS) // Windows 10, version 1703 + } + + // + // Check Linux also + // + If (\_OSI ("Linux")) { + Store (1, OSYS) + } + + If (\_OSI ("FreeBSD")) { + Store (2, OSYS) + } + + If (\_OSI ("HP-UX")) { + Store (3, OSYS) + } + + If (\_OSI ("OpenVMS")) { + Store (4, OSYS) + } + + // + // Running WinSvr2012, Win8, or later? + // + If (LGreaterEqual (\_SB.OSYS, 13)) { + // + // It is Svr2012 or Win8 + // Call xHCI device to switch USB ports over + // unless it has been done already + // + If (LEqual (XCNT, 0)) { + Store (0x84, IO80) + Increment (XCNT) + } + } Else { + Store (\_SB.OSYS, IO80) + } + } + } // End Method (_INI) + +} // End Scope (_SB) diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC00.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC00.asi new file mode 100644 index 0000000000..bebf4e0fcb --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC00.asi @@ -0,0 +1,391 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + // + // Set this root port to use the correct Proximity Domain + // + Name(_PXM, 0) + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + +#include "Pch.asi" +#include "PchApic.asi" + + +#define RESOURCE_CHUNK1_OFF 0 +#define RESOURCE_CHUNK2_OFF 16 //(RESOURCE_CHUNK1_OFF + 16) +#define RESOURCE_CHUNK3_OFF 24 //(RESOURCE_CHUNK2_OFF + 8) +#define RESOURCE_CHUNK4_OFF 40 //(RESOURCE_CHUNK3_OFF + 16) +#define RESOURCE_CHUNK5_OFF 56 //(RESOURCE_CHUNK4_OFF + 16) +#define RESOURCE_CHUNK6_OFF 82 //(RESOURCE_CHUNK5_OFF + 26) +#define RESOURCE_CHUNK7_OFF 108 //(RESOURCE_CHUNK6_OFF + 26) + +#define PciResourceStart Local0 +#define PciResourceLen Local1 + + Name(P0RS, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( // Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + IO( // Consumed resource (CF8-CFF) + Decode16, + 0x0cf8, + 0xcf8, + 1, + 8 + ) + + //RESOURCE_CHUNK3_OFF + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity + 0x0000, // Min + 0x0cf7, // Max + 0x0000, // Translation + 0x0cf8 // Range Length + ) + + //RESOURCE_CHUNK4_OFF + WORDIO( // Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // Descriptor Name + ) + + //RESOURCE_CHUNK6_OFF + DWORDMEMORY( // descriptor for Shadow RAM + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x00000000, // Min (calculated dynamically) + 0x00000000, // Max (calculated dynamically) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) + , + , + SRAM // DescriptorName populated so iASL doesn't flag 0 value fields and no tag as error + ) +/* + //RESOURCE_TPM + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity + 0xFED40000, // Min (calculated dynamically) + 0xFEDFFFFF, // Max = 4GB - 1MB (fwh + fwh alias...) + 0x00000000, // Translation + 0x000C0000 // Range Length (calculated dynamically) + ) +*/ + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable, + ReadWrite,0x00,0xFE010000,0xFE010FFF,0x00,0x1000) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of P0RS Buffer + + OperationRegion(TMEM, PCI_Config, 0x00, 0x100) + Field(TMEM, ByteAcc, NoLock, Preserve) { + Offset(0x40), + , 4, + BSEG, 4, + PAMS, 48, + Offset(0x52), + DIM0, 4, + DIM1, 4, + , 8, + DIM2, 4, + } + + Name(MTBL, Package(0x10) { + 0x0, + 0x20, + 0x20, + 0x30, + 0x40, + 0x40, + 0x60, + 0x80, + 0x80, + 0x80, + 0x80, + 0xc0, + 0x100, + 0x100, + 0x100, + 0x200 + }) + + Name(ERNG, Package(0xd) { + 0xc0000, + 0xc4000, + 0xc8000, + 0xcc000, + 0xd0000, + 0xd4000, + 0xd8000, + 0xdc000, + 0xe0000, + 0xe4000, + 0xe8000, + 0xec000, + 0xf0000 + }) + + Name(PAMB, Buffer(0x7) { + }) + + Method(EROM, 0x0, NotSerialized) { + CreateDWordField(P0RS, ^SRAM._MIN, RMIN) // Do not reference hard-coded address + CreateDWordField(P0RS, ^SRAM._MAX, RMAX) // Do not reference hard-coded address + CreateDWordField(P0RS, ^SRAM._LEN, RLEN) // Do not reference hard-coded address + CreateByteField(PAMB, 0x6, BREG) + Store(PAMS, PAMB) + Store(BSEG, BREG) + Store(0x0, RMIN) + Store(0x0, RMAX) + Store(0x0, RLEN) + Store(0x0, Local0) + While(LLess(Local0, 0xd)) + { + ShiftRight(Local0, 0x1, Local1) + Store(DerefOf(Index(PAMB, Local1, )), Local2) + If(And(Local0, 0x1, )) + { + ShiftRight(Local2, 0x4, Local2) + } + And(Local2, 0x3, Local2) + If(RMIN) + { + If(Local2) + { + Add(DerefOf(Index(ERNG, Local0, )), 0x3fff, RMAX) + If(LEqual(RMAX, 0xf3fff)) + { + Store(0xfffff, RMAX) + } + Subtract(RMAX, RMIN, RLEN) + Increment(RLEN) + } + Else + { + Store(0xc, Local0) + } + } + Else + { + If(Local2) + { + Store(DerefOf(Index(ERNG, Local0, )), RMIN) + Add(DerefOf(Index(ERNG, Local0, )), 0x3fff, RMAX) + If(LEqual(RMAX, 0xf3fff)) + { + Store(0xfffff, RMAX) + } + Subtract(RMAX, RMIN, RLEN) + Increment(RLEN) + } + Else + { + } + } + Increment(Local0) + } + } + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + EROM() + Return(P0RS) + } + + // + // Memory Riser UID will be in Interger form to support CPU Migration. + // First two digits will indicate Memory Device(01) and last two + // digits will represent the Memory Riser number. + // + Device (MHP0) { + // Within the IIO, read D5:F1 for Memory HP status + Name(_ADR, 0x00050001) // D5:F1 + Name(_UID, "00-00") + + // MHP0 - Config register for Slot status + OperationRegion(MHP0, PCI_Config, 0x00, 0x100) + Field(MHP0,ByteAcc,NoLock,Preserve) { + Offset(0x0E), + STM0,7, + } + } + + Device (MHP1) { + // Within the IIO, read D5:F1 for Memory HP status + Name(_ADR, 0x00050001) // D5:F1 + Name(_UID, "00-01") + + // MHP1 - Config register for Slot status + OperationRegion(MHP1, PCI_Config, 0x00, 0x100) + Field(MHP1,ByteAcc,NoLock,Preserve) { + Offset(0x1E), + STM1,7, + } + } diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC01.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC01.asi new file mode 100644 index 0000000000..aeb0d2ef83 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC01.asi @@ -0,0 +1,261 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + // + // Set this root port to use the correct Proximity Domain + // + Name(_PXM, 0) + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met? + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + Store (0xE3, IO80) + \_SB.PC01.BR1A.OSHP () + \_SB.PC01.BR1B.OSHP () + \_SB.PC01.BR1C.OSHP () + \_SB.PC01.BR1D.OSHP () + + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 0, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Shift for IIO Stack 1 + ShiftRight(IIOH, 1, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR01, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR01 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR01) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC02.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC02.asi new file mode 100644 index 0000000000..f92d2eea84 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC02.asi @@ -0,0 +1,261 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + // + // Set this root port to use the correct Proximity Domain + // + Name(_PXM, 0) + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met? + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC02.BR2A.OSHP () + \_SB.PC02.BR2B.OSHP () + \_SB.PC02.BR2C.OSHP () + \_SB.PC02.BR2D.OSHP () + + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 0, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Shift for IIO Stack 2 + ShiftRight(IIOH, 2, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR02, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR02 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR02) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC03.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC03.asi new file mode 100644 index 0000000000..466537d014 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC03.asi @@ -0,0 +1,266 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + // + // Set this root port to use the correct Proximity Domain + // + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(0) + } else { + Return(1) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met? + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC03.BR3A.OSHP () + \_SB.PC03.BR3B.OSHP () + \_SB.PC03.BR3C.OSHP () + \_SB.PC03.BR3D.OSHP () + + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 0, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Shift for IIO Stack 3 + ShiftRight(IIOH, 3, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR03, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR03 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR03) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC04.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC04.asi new file mode 100644 index 0000000000..2ff1c2f64d --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC04.asi @@ -0,0 +1,238 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + // + // Set this root port to use the correct Proximity Domain + // + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(0) + } else { + Return(1) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 0, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Shift for IIO Stack 4 + ShiftRight(IIOH, 4, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR04, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR04 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR04) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC05.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC05.asi new file mode 100644 index 0000000000..f2b9bce5e3 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC05.asi @@ -0,0 +1,239 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + // + // Set this root port to use the correct Proximity Domain + // + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(0) + } else { + Return(1) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 0, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Shift for IIO Stack 5 + ShiftRight(IIOH, 5, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR05, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR05 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR05) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC06.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC06.asi new file mode 100644 index 0000000000..bc856473bb --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC06.asi @@ -0,0 +1,334 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(1) + } else { + Return(2) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met? + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC06.QRP0.OSHP () + + + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + // owning control method can't be reentrant, so _DSM must be Serialized + Method (_DSM, 4, Serialized) { // Device specific method + if(LEqual(Arg0,ToUUID("D8C1A3A6-BE9B-4C9B-91BF-C3CB81FC5DAF"))){ + Switch(ToInteger(Arg2)) { + case(0) {Return ( Buffer() {0x1F} )} // function indexes 1-4 supported + case(1) {Return (Buffer() {0x44, 0x52, 0x48, 0x31, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00 } ) } // DRHD buffer containing relavent ATSR structure for I/O Hub n + + case(2) {Return (Buffer() {0x41, 0x54, 0x53, 0x31, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00 } ) }// ATSR buffer containing relavent ATSR structure for I/O Hub n + case(3) {Return (Buffer() {0x52, 0x48, 0x53, 0x31, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00 } ) }// RHSA buffer containing relavent ATSR structure for I/O Hub n + Default { } + } + } + Return (Buffer() {0}) + } + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 1, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 1 in bitmap (8 x Socket #) + ShiftRight(IIOH, 8, Local1) + // Shift for IIO Stack 0 + ShiftRight(Local1, 0, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA +/* TODO: ifdef does not work here, need to enable this code after PPO + // All PCI-Ex ports are dependent on IIOx stack + Name(_EDL, Package() { + \_SB.PC06.QRP0, \_SB.PC07.QR1A, \_SB.PC07.QR1B, \_SB.PC07.QR1C, \_SB.PC07.QR1D, + \_SB.PC08.QR2A, \_SB.PC08.QR2B, \_SB.PC08.QR2C, \_SB.PC08.QR2D, + \_SB.PC09.QR3A, \_SB.PC09.QR3B, \_SB.PC09.QR3C, \_SB.PC09.QR3D + }) +*/ + Name(PR06, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR06 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR06) + } + + // + // Memory Riser UID will be in Interger form to support CPU Migration. + // First two digits will indicate Memory Device(01) and last two + // digits will represent the Memory Riser number. + // + Device (MHP0) { + // Within the IIO, read D5:F1 for Memory HP status + Name(_ADR, 0x00050001) // D5:F1 + Name(_UID, "01-00") + + // MHP0 - Config register for Slot status + OperationRegion(MHP0, PCI_Config, 0xE, 2) + Field(MHP0,ByteAcc,NoLock,Preserve) { + STM2,7, + } + } + + Device (MHP1) { + // Within the IIO, read D5:F1 for Memory HP status + Name(_ADR, 0x00050001) // D5:F1 + Name(_UID, "01-01") + + // MHP1 - Config register for Slot status + OperationRegion(MHP1, PCI_Config, 0x1E, 2) + Field(MHP1,ByteAcc,NoLock,Preserve) { + STM3,7, + } + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC06Ejd.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC06Ejd.asi new file mode 100644 index 0000000000..1921d0e157 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC06Ejd.asi @@ -0,0 +1,15 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + // Eject device if PC06 is removed. + Name(_EJD,"\\_SB.PC06") // Dependent on PC06 diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC07.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC07.asi new file mode 100644 index 0000000000..50c1269e4e --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC07.asi @@ -0,0 +1,265 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(1) + } else { + Return(2) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met? + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC07.QR1A.OSHP () + \_SB.PC07.QR1B.OSHP () + \_SB.PC07.QR1C.OSHP () + \_SB.PC07.QR1D.OSHP () + + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 1, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 1 in bitmap (8 x Socket #) + ShiftRight(IIOH, 8, Local1) + // Shift for IIO Stack 1 + ShiftRight(Local1, 1, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR07, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR07 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR07) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC08.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC08.asi new file mode 100644 index 0000000000..18c737a55a --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC08.asi @@ -0,0 +1,268 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(1) + } else { + Return(2) + } + } + +// +// Moving _OSC method to respective stack PCXX.asi. +// + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met? + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC08.QR2A.OSHP () + \_SB.PC08.QR2B.OSHP () + \_SB.PC08.QR2C.OSHP () + \_SB.PC08.QR2D.OSHP () + + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 1, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 1 in bitmap (8 x Socket #) + ShiftRight(IIOH, 8, Local1) + // Shift for IIO Stack 2 + ShiftRight(Local1, 2, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR08, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR08 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR08) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC09.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC09.asi new file mode 100644 index 0000000000..66730a27e9 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC09.asi @@ -0,0 +1,266 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(1) + } else { + Return(3) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met? + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC09.QR3A.OSHP () + \_SB.PC09.QR3B.OSHP () + \_SB.PC09.QR3C.OSHP () + \_SB.PC09.QR3D.OSHP () + + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 1, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 1 in bitmap (8 x Socket #) + ShiftRight(IIOH, 8, Local1) + // Shift for IIO Stack 3 + ShiftRight(Local1, 3, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR09, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR09 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR09) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC10.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC10.asi new file mode 100644 index 0000000000..a12136c053 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC10.asi @@ -0,0 +1,238 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(1) + } else { + Return(3) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 1, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 1 in bitmap (8 x Socket #) + ShiftRight(IIOH, 8, Local1) + // Shift for IIO Stack 4 + ShiftRight(Local1, 4, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR10, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR10 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR10) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC11.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC11.asi new file mode 100644 index 0000000000..efafb7ea99 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC11.asi @@ -0,0 +1,237 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(1) + } else { + Return(3) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 1, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 1 in bitmap (8 x Socket #) + ShiftRight(IIOH, 8, Local1) + // Shift for IIO Stack 5 + ShiftRight(Local1, 5, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR11, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR11 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR11) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC12.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC12.asi new file mode 100644 index 0000000000..bd860fe411 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC12.asi @@ -0,0 +1,330 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(2) + } else { + Return(4) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met? + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC12.RRP0.OSHP () + + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + // owning control method can't be reentrant, so _DSM must be Serialized + Method (_DSM, 4, Serialized) { // Device specific method + if(LEqual(Arg0,ToUUID("D8C1A3A6-BE9B-4C9B-91BF-C3CB81FC5DAF"))){ + Switch(ToInteger(Arg2)) { + case(0) {Return ( Buffer() {0x1F} )} // function indexes 1-4 supported + case(1) {Return (Buffer() {0x44, 0x52, 0x48, 0x32, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00 } ) } // DRHD buffer containing relavent ATSR structure for I/O Hub n + + case(2) {Return (Buffer() {0x41, 0x54, 0x53, 0x32, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00 } ) }// ATSR buffer containing relavent ATSR structure for I/O Hub n + case(3) {Return (Buffer() {0x52, 0x48, 0x53, 0x32, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00 } ) }// RHSA buffer containing relavent ATSR structure for I/O Hub n + Default { } + } + } + Return (Buffer() {0}) + } + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 2, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 2 in bitmap (8 x Socket #) + ShiftRight(IIOH, 16, Local1) + // Shift for IIO Stack 0 + ShiftRight(Local1, 0, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA +/* TODO: ifdef does not work here, need to enable this code after PPO + // All PCI-Ex ports are dependent on IIO2 + Name(_EDL, Package() { + \_SB.PC12.RRP0, \_SB.PC13.RR1A, \_SB.PC13.RR1B, \_SB.PC13.RR1C, \_SB.PC13.RR1D, + \_SB.PC14.RR2A, \_SB.PC14.RR2B, \_SB.PC14.RR2C, \_SB.PC14.RR2D, + \_SB.PC15.RR3A, \_SB.PC15.RR3B, \_SB.PC15.RR3C, \_SB.PC15.RR3D + }) +*/ + Name(PR12, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR12 Buffer + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR12) + } + + // + // Memory Riser UID will be in Interger form to support CPU Migration. + // First two digits will indicate Memory Device(01) and last two + // digits will represent the Memory Riser number. + // + Device (MHP0) { + // Within the IIO, read D5:F1 for Memory HP status + Name(_ADR, 0x00050001) // D5:F1 + Name(_UID, "02-00") + + // MHP0 - Config register for Slot status + OperationRegion(MHP0, PCI_Config, 0xE, 2) + Field(MHP0,ByteAcc,NoLock,Preserve) { + STM4,7, + } + } + + Device (MHP1) { + // Within the IIO, read D5:F1 for Memory HP status + Name(_ADR, 0x00050001) // D5:F1 + Name(_UID, "02-01") + + // MHP1 - Config register for Slot status + OperationRegion(MHP1, PCI_Config, 0x1E, 2) + Field(MHP1,ByteAcc,NoLock,Preserve) { + STM5,7, + } + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC12Ejd.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC12Ejd.asi new file mode 100644 index 0000000000..7a9aedf818 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC12Ejd.asi @@ -0,0 +1,15 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + // Eject device if PC12 is removed. + Name(_EJD,"\\_SB.PC12") // Dependent on PC12 diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC13.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC13.asi new file mode 100644 index 0000000000..3183a62ff2 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC13.asi @@ -0,0 +1,262 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(2) + } else { + Return(4) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met? + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC13.RR1A.OSHP () + \_SB.PC13.RR1B.OSHP () + \_SB.PC13.RR1C.OSHP () + \_SB.PC13.RR1D.OSHP () + + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 2, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 2 in bitmap (8 x Socket #) + ShiftRight(IIOH, 16, Local1) + // Shift for IIO Stack 1 + ShiftRight(Local1, 1, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR13, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR13 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR13) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC14.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC14.asi new file mode 100644 index 0000000000..24b1d0e35c --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC14.asi @@ -0,0 +1,265 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(2) + } else { + Return(4) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + //Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met? + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC14.RR2A.OSHP () + \_SB.PC14.RR2B.OSHP () + \_SB.PC14.RR2C.OSHP () + \_SB.PC14.RR2D.OSHP () + + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 2, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 2 in bitmap (8 x Socket #) + ShiftRight(IIOH, 16, Local1) + // Shift for IIO Stack 2 + ShiftRight(Local1, 2, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR14, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR14 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR14) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC15.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC15.asi new file mode 100644 index 0000000000..77f5aa8185 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC15.asi @@ -0,0 +1,265 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(2) + } else { + Return(5) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met? + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC15.RR3A.OSHP () + \_SB.PC15.RR3B.OSHP () + \_SB.PC15.RR3C.OSHP () + \_SB.PC15.RR3D.OSHP () + + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 2, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 2 in bitmap (8 x Socket #) + ShiftRight(IIOH, 16, Local1) + // Shift for IIO Stack 3 + ShiftRight(Local1, 3, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR15, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR15 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR15) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC16.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC16.asi new file mode 100644 index 0000000000..1d4e6d89df --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC16.asi @@ -0,0 +1,237 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(2) + } else { + Return(5) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 2, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 2 in bitmap (8 x Socket #) + ShiftRight(IIOH, 16, Local1) + // Shift for IIO Stack 4 + ShiftRight(Local1, 4, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR16, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR16 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR16) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC17.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC17.asi new file mode 100644 index 0000000000..4e04769467 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC17.asi @@ -0,0 +1,237 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(2) + } else { + Return(5) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 2, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 2 in bitmap (8 x Socket #) + ShiftRight(IIOH, 16, Local1) + // Shift for IIO Stack 5 + ShiftRight(Local1, 5, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR17, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR17 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR17) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC18.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC18.asi new file mode 100644 index 0000000000..ca8f18ecd2 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC18.asi @@ -0,0 +1,348 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(3) + } else { + Return(6) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met? + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC18.SRP0.OSHP () + + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + // owning control method can't be reentrant, so _DSM must be Serialized + Method (_DSM, 4, Serialized) { // Device specific method + if(LEqual(Arg0,ToUUID("D8C1A3A6-BE9B-4C9B-91BF-C3CB81FC5DAF"))){ + Switch(ToInteger(Arg2)) { + case(0) {Return ( Buffer() {0x1F} )} // function indexes 1-4 supported + case(1) {Return (Buffer() {0x44, 0x52, 0x48, 0x33, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00 } ) } // DRHD buffer containing relavent ATSR structure for I/O Hub n + + case(2) {Return (Buffer() {0x41, 0x54, 0x53, 0x33, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00 } ) }// ATSR buffer containing relavent ATSR structure for I/O Hub n + case(3) {Return (Buffer() {0x52, 0x48, 0x53, 0x33, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00 } ) }// RHSA buffer containing relavent ATSR structure for I/O Hub n + Default { } + } + } + Return (Buffer() {0}) + } + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 3, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 3 in bitmap (8 x Socket #) + ShiftRight(IIOH, 24, Local1) + // Shift for IIO Stack 0 + ShiftRight(Local1, 0, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA +/* TODO: ifdef does not work here, need to enable this code after PPO + // All PCI-Ex ports are dependent on IIO3 + Name(_EDL, Package() { + \_SB.PC18.SRP0, \_SB.PC19.SR1A, \_SB.PC19.SR1B, \_SB.PC19.SR1C, \_SB.PC19.SR1D, + \_SB.PC20.SR2A, \_SB.PC20.SR2B, \_SB.PC20.SR2C, \_SB.PC20.SR2D, + \_SB.PC21.SR3A, \_SB.PC21.SR3B, \_SB.PC21.SR3C, \_SB.PC21.SR3D + }) + + Method(_EJ0, 1) { + Notify(\_SB.PC18.SRP0, Arg0) + Notify(\_SB.PC19.SR1A, Arg0) + Notify(\_SB.PC19.SR1B, Arg0) + Notify(\_SB.PC19.SR1C, Arg0) + Notify(\_SB.PC19.SR1D, Arg0) + Notify(\_SB.PC20.SR2A, Arg0) + Notify(\_SB.PC20.SR2B, Arg0) + Notify(\_SB.PC20.SR2C, Arg0) + Notify(\_SB.PC20.SR2D, Arg0) + Notify(\_SB.PC21.SR3A, Arg0) + Notify(\_SB.PC21.SR3B, Arg0) + Notify(\_SB.PC21.SR3C, Arg0) + Notify(\_SB.PC21.SR3D, Arg0) + \_SB.GSMI(3, 3) //EVENT_IIO_HP, IIO ID + } +*/ + Name(PR18, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIXH - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR18 Buffer + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR18) + } + + // + // Memory Riser UID will be in Interger form to support CPU Migration. + // First two digits will indicate Memory Device(01) and last two + // digits will represent the Memory Riser number. + // + Device (MHP0) { + // Within the IIO, read D5:F1 for Memory HP status + Name(_ADR, 0x00050001) // D5:F1 + Name(_UID, "03-00") + + // MHP0 - Config register for Slot status + OperationRegion(MHP0, PCI_Config, 0xE, 2) + Field(MHP0,ByteAcc,NoLock,Preserve) { + STM6,7, + } + } + + Device (MHP1) { + // Within the IIO, read D5:F1 for Memory HP status + Name(_ADR, 0x00050001) // D5:F1 + Name(_UID, "03-01") + + // MHP1 - Config register for Slot status + OperationRegion(MHP1, PCI_Config, 0x1E, 2) + Field(MHP1,ByteAcc,NoLock,Preserve) { + STM7,7, + } + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC18Ejd.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC18Ejd.asi new file mode 100644 index 0000000000..6e0a48b128 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC18Ejd.asi @@ -0,0 +1,15 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + // Eject device if PC18 is removed. + Name(_EJD,"\\_SB.PC18") // Dependent on PC18 diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC19.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC19.asi new file mode 100644 index 0000000000..121645a3cd --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC19.asi @@ -0,0 +1,265 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(3) + } else { + Return(6) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met? + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC19.SR1A.OSHP () + \_SB.PC19.SR1B.OSHP () + \_SB.PC19.SR1C.OSHP () + \_SB.PC19.SR1D.OSHP () + + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 3, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 3 in bitmap (8 x Socket #) + ShiftRight(IIOH, 24, Local1) + // Shift for IIO Stack + ShiftRight(Local1, 1, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR19, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR19 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR19) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC20.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC20.asi new file mode 100644 index 0000000000..fcdb44071b --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC20.asi @@ -0,0 +1,266 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(3) + } else { + Return(6) + } + } + + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met? + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC20.SR2A.OSHP () + \_SB.PC20.SR2B.OSHP () + \_SB.PC20.SR2C.OSHP () + \_SB.PC20.SR2D.OSHP () + + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 3, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 3 in bitmap (8 x Socket #) + ShiftRight(IIOH, 24, Local1) + // Shift for IIO Stack + ShiftRight(Local1, 2, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR20, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR20 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR20) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC21.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC21.asi new file mode 100644 index 0000000000..3ae6e1c8d8 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC21.asi @@ -0,0 +1,266 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(3) + } else { + Return(7) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met? + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC21.SR3A.OSHP () + \_SB.PC21.SR3B.OSHP () + \_SB.PC21.SR3C.OSHP () + \_SB.PC21.SR3D.OSHP () + + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 3, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 3 in bitmap (8 x Socket #) + ShiftRight(IIOH, 24, Local1) + // Shift for IIO Stack 3 + ShiftRight(Local1, 3, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR21, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR21 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR21) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC22.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC22.asi new file mode 100644 index 0000000000..e3d64db58c --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC22.asi @@ -0,0 +1,238 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(3) + } else { + Return(7) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 3, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 3 in bitmap (8 x Socket #) + ShiftRight(IIOH, 24, Local1) + // Shift for IIO Stack 4 + ShiftRight(Local1, 4, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR22, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR22 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR22) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC23.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC23.asi new file mode 100644 index 0000000000..e64380e4e8 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC23.asi @@ -0,0 +1,238 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(3) + } else { + Return(7) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 3, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 3 in bitmap (8 x Socket #) + ShiftRight(IIOH, 24, Local1) + // Shift for IIO Stack 5 + ShiftRight(Local1, 5, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR23, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR23 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR23) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC24.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC24.asi new file mode 100644 index 0000000000..bed4dfbc2b --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC24.asi @@ -0,0 +1,237 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(4) + } else { + Return(8) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 4, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 4 in bitmap (8 x Socket #) + ShiftRight(IIOH, 32, Local1) + // Shift for IIO Stack 0 + ShiftRight(Local1, 0, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR24, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR24 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR24) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC25.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC25.asi new file mode 100644 index 0000000000..8c2b3b288c --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC25.asi @@ -0,0 +1,265 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(4) + } else { + Return(8) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met? + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC25.CR1A.OSHP () + \_SB.PC25.CR1B.OSHP () + \_SB.PC25.CR1C.OSHP () + \_SB.PC25.CR1D.OSHP () + + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 4, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 4 in bitmap (8 x Socket #) + ShiftRight(IIOH, 32, Local1) + // Shift for IIO Stack 1 + ShiftRight(Local1, 1, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR25, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR25 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR25) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC26.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC26.asi new file mode 100644 index 0000000000..95aeb03b0d --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC26.asi @@ -0,0 +1,265 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(4) + } else { + Return(8) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met? + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC26.CR2A.OSHP () + \_SB.PC26.CR2B.OSHP () + \_SB.PC26.CR2C.OSHP () + \_SB.PC26.CR2D.OSHP () + + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 4, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 4 in bitmap (8 x Socket #) + ShiftRight(IIOH, 32, Local1) + // Shift for IIO Stack 2 + ShiftRight(Local1, 2, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR26, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR26 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR26) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC27.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC27.asi new file mode 100644 index 0000000000..750b4eaa24 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC27.asi @@ -0,0 +1,265 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(4) + } else { + Return(9) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met? + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC27.CR3A.OSHP () + \_SB.PC27.CR3B.OSHP () + \_SB.PC27.CR3C.OSHP () + \_SB.PC27.CR3D.OSHP () + + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 4, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 4 in bitmap (8 x Socket #) + ShiftRight(IIOH, 32, Local1) + // Shift for IIO Stack 3 + ShiftRight(Local1, 3, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR27, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR27 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR27) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC28.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC28.asi new file mode 100644 index 0000000000..3e8b3b24bd --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC28.asi @@ -0,0 +1,238 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(4) + } else { + Return(9) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 4, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 4 in bitmap (8 x Socket #) + ShiftRight(IIOH, 32, Local1) + // Shift for IIO Stack 4 + ShiftRight(Local1, 4, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR28, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR28 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR28) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC29.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC29.asi new file mode 100644 index 0000000000..f10ec64b94 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC29.asi @@ -0,0 +1,238 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(4) + } else { + Return(9) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 4, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 4 in bitmap (8 x Socket #) + ShiftRight(IIOH, 32, Local1) + // Shift for IIO Stack 5 + ShiftRight(Local1, 5, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR29, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR29 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR29) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC30.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC30.asi new file mode 100644 index 0000000000..ec46cccc38 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC30.asi @@ -0,0 +1,262 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(5) + } else { + Return(10) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met? + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC30.TRP0.OSHP () + + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 5, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 5 in bitmap (8 x Socket #) + ShiftRight(IIOH, 40, Local1) + // Shift for IIO Stack 0 + ShiftRight(Local1, 0, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR30, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR30 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR30) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC31.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC31.asi new file mode 100644 index 0000000000..382e75f644 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC31.asi @@ -0,0 +1,265 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(5) + } else { + Return(10) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met? + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC31.TR1A.OSHP () + \_SB.PC31.TR1B.OSHP () + \_SB.PC31.TR1C.OSHP () + \_SB.PC31.TR1D.OSHP () + + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 5, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 5 in bitmap (8 x Socket #) + ShiftRight(IIOH, 40, Local1) + // Shift for IIO Stack 1 + ShiftRight(Local1, 1, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR31, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR31 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR31) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC32.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC32.asi new file mode 100644 index 0000000000..6c921b52db --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC32.asi @@ -0,0 +1,266 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(5) + } else { + Return(10) + } + } + + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met? + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC32.TR2A.OSHP () + \_SB.PC32.TR2B.OSHP () + \_SB.PC32.TR2C.OSHP () + \_SB.PC32.TR2D.OSHP () + + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 5, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 5 in bitmap (8 x Socket #) + ShiftRight(IIOH, 40, Local1) + // Shift for IIO Stack 2 + ShiftRight(Local1, 2, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR32, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR32 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR32) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC33.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC33.asi new file mode 100644 index 0000000000..39097f45d2 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC33.asi @@ -0,0 +1,266 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(5) + } else { + Return(11) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met? + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC33.TR3A.OSHP () + \_SB.PC33.TR3B.OSHP () + \_SB.PC33.TR3C.OSHP () + \_SB.PC33.TR3D.OSHP () + + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 5, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 5 in bitmap (8 x Socket #) + ShiftRight(IIOH, 40, Local1) + // Shift for IIO Stack 3 + ShiftRight(Local1, 3, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR33, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR33 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR33) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC34.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC34.asi new file mode 100644 index 0000000000..3335a9f77a --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC34.asi @@ -0,0 +1,238 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(5) + } else { + Return(11) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 5, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 5 in bitmap (8 x Socket #) + ShiftRight(IIOH, 40, Local1) + // Shift for IIO Stack 4 + ShiftRight(Local1, 4, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR34, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR34 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR34) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC35.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC35.asi new file mode 100644 index 0000000000..03503ce5ee --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC35.asi @@ -0,0 +1,238 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(5) + } else { + Return(11) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 5, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 5 in bitmap (8 x Socket #) + ShiftRight(IIOH, 40, Local1) + // Shift for IIO Stack 5 + ShiftRight(Local1, 5, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR35, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR35 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR35) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC36.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC36.asi new file mode 100644 index 0000000000..606c9132a8 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC36.asi @@ -0,0 +1,263 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(6) + } else { + Return(12) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met? + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC36.URP0.OSHP () + + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 6, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 6 in bitmap (8 x Socket #) + ShiftRight(IIOH, 48, Local1) + // Shift for IIO Stack 0 + ShiftRight(Local1, 0, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR36, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR36 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR36) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC37.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC37.asi new file mode 100644 index 0000000000..8544b4bb9f --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC37.asi @@ -0,0 +1,265 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(6) + } else { + Return(12) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met? + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC37.UR1A.OSHP () + \_SB.PC37.UR1B.OSHP () + \_SB.PC37.UR1C.OSHP () + \_SB.PC37.UR1D.OSHP () + + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 6, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 6 in bitmap (8 x Socket #) + ShiftRight(IIOH, 48, Local1) + // Shift for IIO Stack 1 + ShiftRight(Local1, 1, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR37, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR37 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR37) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC38.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC38.asi new file mode 100644 index 0000000000..c64a085a9c --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC38.asi @@ -0,0 +1,266 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(6) + } else { + Return(12) + } + } + + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met? + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC38.UR2A.OSHP () + \_SB.PC38.UR2B.OSHP () + \_SB.PC38.UR2C.OSHP () + \_SB.PC38.UR2D.OSHP () + + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 6, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 6 in bitmap (8 x Socket #) + ShiftRight(IIOH, 48, Local1) + // Shift for IIO Stack 2 + ShiftRight(Local1, 2, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR38, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR38 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR38) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC39.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC39.asi new file mode 100644 index 0000000000..24562e7688 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC39.asi @@ -0,0 +1,266 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(6) + } else { + Return(13) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met? + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC39.UR3A.OSHP () + \_SB.PC39.UR3B.OSHP () + \_SB.PC39.UR3C.OSHP () + \_SB.PC39.UR3D.OSHP () + + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 6, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 6 in bitmap (8 x Socket #) + ShiftRight(IIOH, 48, Local1) + // Shift for IIO Stack 3 + ShiftRight(Local1, 3, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR39, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR39 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR39) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC40.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC40.asi new file mode 100644 index 0000000000..85b0ded149 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC40.asi @@ -0,0 +1,238 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(6) + } else { + Return(13) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 6, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 6 in bitmap (8 x Socket #) + ShiftRight(IIOH, 48, Local1) + // Shift for IIO Stack 4 + ShiftRight(Local1, 4, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR40, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR40 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR40) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC41.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC41.asi new file mode 100644 index 0000000000..a6221b7eba --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC41.asi @@ -0,0 +1,238 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(6) + } else { + Return(13) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 6, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 6 in bitmap (8 x Socket #) + ShiftRight(IIOH, 48, Local1) + // Shift for IIO Stack 5 + ShiftRight(Local1, 5, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR41, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR41 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR41) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC42.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC42.asi new file mode 100644 index 0000000000..6da3a3e15a --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC42.asi @@ -0,0 +1,296 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(7) + } else { + Return(14) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met? + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC42.VRP0.OSHP () + + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + // owning control method can't be reentrant, so _DSM must be Serialized + Method (_DSM, 4, Serialized) { // Device specific method + if(LEqual(Arg0,ToUUID("D8C1A3A6-BE9B-4C9B-91BF-C3CB81FC5DAF"))){ + Switch(ToInteger(Arg2)) { + case(0) {Return ( Buffer() {0x1F} )} // function indexes 1-4 supported + case(1) {Return (Buffer() {0x44, 0x52, 0x48, 0x33, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00 } ) } // DRHD buffer containing relavent ATSR structure for I/O Hub n + + case(2) {Return (Buffer() {0x41, 0x54, 0x53, 0x33, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00 } ) }// ATSR buffer containing relavent ATSR structure for I/O Hub n + case(3) {Return (Buffer() {0x52, 0x48, 0x53, 0x33, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00, + 00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00 } ) }// RHSA buffer containing relavent ATSR structure for I/O Hub n + Default { } + } + } + Return (Buffer() {0}) + } + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 7, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 7 in bitmap (8 x Socket #) + ShiftRight(IIOH, 56, Local1) + // Shift for IIO Stack 0 + ShiftRight(Local1, 0, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR42, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR42 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR42) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC43.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC43.asi new file mode 100644 index 0000000000..d56c84d8ea --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC43.asi @@ -0,0 +1,265 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(7) + } else { + Return(14) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Only allow native hot plug control if OS supports + // * ASPM + // * MSI/MSI-X + // + If (LOr(AHPE, LNotEqual(And(SUPP, 0x16), 0x16))) { // Conditions not met? + And(CTRL, 0x1E, CTRL) // Mask bit 0 to deny. + Sleep(1000) + } + + // + // Never allow SHPC (no SHPC controller in system) + // + And(CTRL, 0x1D, CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + If (Not(And(CDW1,1))) { // Query Flag Clear? + // + // Disable GPEs for Features granted native control + // + If (And(CTRL, 0x01)) { // Native Hot plug control granted? + \_SB.PC43.VR1A.OSHP () + \_SB.PC43.VR1B.OSHP () + \_SB.PC43.VR1C.OSHP () + \_SB.PC43.VR1D.OSHP () + + Store (0x01, GPSH) // Clear Hotplug SCI Enable in GPE0 + } + } + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 7, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 7 in bitmap (8 x Socket #) + ShiftRight(IIOH, 56, Local1) + // Shift for IIO Stack 1 + ShiftRight(Local1, 1, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR43, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR43 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR43) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC44.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC44.asi new file mode 100644 index 0000000000..2b9eaebf90 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC44.asi @@ -0,0 +1,238 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(7) + } else { + Return(14) + } + } + + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 7, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 7 in bitmap (8 x Socket #) + ShiftRight(IIOH, 56, Local1) + // Shift for IIO Stack 2 + ShiftRight(Local1, 2, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR44, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR44 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR44) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC45.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC45.asi new file mode 100644 index 0000000000..efd01f1a28 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC45.asi @@ -0,0 +1,238 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(7) + } else { + Return(15) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 7, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 7 in bitmap (8 x Socket #) + ShiftRight(IIOH, 56, Local1) + // Shift for IIO Stack 3 + ShiftRight(Local1, 3, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR45, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR45 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR45) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC46.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC46.asi new file mode 100644 index 0000000000..bf845cbb9f --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC46.asi @@ -0,0 +1,238 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(7) + } else { + Return(15) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 7, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 7 in bitmap (8 x Socket #) + ShiftRight(IIOH, 56, Local1) + // Shift for IIO Stack 4 + ShiftRight(Local1, 4, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR46, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR46 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR46) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC47.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC47.asi new file mode 100644 index 0000000000..67c41e76e8 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PC47.asi @@ -0,0 +1,238 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (SUPP, 0) + Name (CTRL, 0) + + Method(_PXM) { + if (LEqual (CLOD, 0)) { + Return(7) + } else { + Return(15) + } + } + + Method(_OSC,4) { + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,0,CDW1) + If (LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + + // + // Create DWord-addressable fields from the capabilities Buffer + // + CreateDWordField(Arg3,4,CDW2) + + // + // Fill 3rd capability DWORD only if the count is greater than 2. + // + If(LGreater(Arg2,2)) { + CreateDWordField(Arg3,8,CDW3) + } + + // + // Save Capabilities DWord2 & 3 + // + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // Disable Native PCIe AER handling from OS so that it uses Firmware First model in WHEA + // + And (CTRL, 0x17, CTRL) + + + If (LNotEqual(Arg1,one)) { // unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // + // update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Return(Arg3) + + } Else { + // + // Just indicate unrecognized UUID + // Leave it at that + // + Or (CDW1,4,CDW1) + Store (0xEE, IO80) + Return(Arg3) + } + } // End _OSC + + + Method(_STA){ + // Have to account for logical offline condition which IIOx stack is still in QPI fabric, but not OS visible + ShiftRight(PRBM, 7, Local1) + And(Local1, 0x1, Local1) + // Check if Socket is present + if(LEqual(Local1, 0x1)) { + // Account for Socket 7 in bitmap (8 x Socket #) + ShiftRight(IIOH, 56, Local1) + // Shift for IIO Stack 5 + ShiftRight(Local1, 5, Local1) + And(Local1, 0x1, Local1) + // Check if IIO Stack is present + if(LEqual(Local1, 0x1)) { + // IIOx stack present and logically online + Return(0x0F) + } + } + // IIOx stack logically offline + Return(0x00) + + } // End Method STA + + Name(PR47, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX1 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX1 - Patched by ACPI Platform Driver during POST) + , + , + FIX1 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //: Off board video card not detected in device manager when it is connected to CPU + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is Fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max (FIX5 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (FIX5 - Patched by ACPI Platform Driver during POST) + , + , + FIX5 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //RESOURCE_CHUNK2_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX2 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0001, // Range Length = Max-Min+1 (FIX2 - Patched by ACPI Platform Driver during POST) + , + , + FIX2 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX6 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX6 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + //Off board video card not detected in device manager when it is connected to CPU + //Descriptor for IO space of the video card. + WORDIO( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Min (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Max (FIX7 - Patched by ACPI Platform Driver during POST) + 0x0000, // Translation + 0x0000, // Range Length + , + , + FIX7 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Min (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX3 - Patched by ACPI Platform Driver during POST) + 0x00000000, // Translation + 0x00000000, // Range Length (calculated dynamically) (FIX3 - Patched by ACPI Platform Driver during POST) + , + , + FIX3 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000000, // Granularity (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Min (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias) (FIX4 - Patched by ACPI Platform Driver during POST) + 0x00000000000, // Translation + 0x00000000000, // Range Length (calculated dynamically) (FIX4 - Patched by ACPI Platform Driver during POST) + , + , + FIX4 // DescriptorName populated so iASL outputs offset for it in a .h file + ) + }) // end of PR47 Buffer + + + // Current resource template return + Method(_CRS, 0x0, NotSerialized) { + Return(PR47) + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Pch.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Pch.asi new file mode 100644 index 0000000000..77c4f1797b --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Pch.asi @@ -0,0 +1,16 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// +// I/O controller miscellaneous +// diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchApic.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchApic.asi new file mode 100644 index 0000000000..8c5787c44c --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchApic.asi @@ -0,0 +1,23 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Device(APIC) { + Name (_HID,EISAID("PNP0003")) // APIC resources + Name (_CRS, ResourceTemplate() { + // + // APIC range(0xFEC0_0000 to 0xFECF_FFFF) + // + Memory32Fixed (ReadOnly, 0xFEC00000, 0x100000) // IO APIC + } + ) +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci1.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci1.asi new file mode 100644 index 0000000000..bb6d1fc8c9 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci1.asi @@ -0,0 +1,97 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Name (OPAC, 0) + +OperationRegion(PWKE,PCI_Config,0x54,0x18) +Field(PWKE,DWordAcc,NoLock,Preserve) +{ + , 8, + PMEE, 1, // PWR_CNTL_STS.PME_En + , 6, + PMES, 1, // PWR_CNTL_STS.PME_Sts + Offset (0x0E), + , 1, + PWUC, 10 // Port Wake Up Capability Mask +} + +// +// Indicate access to OperationRegions is enabled/disabled +// +Method (_REG, 2) +{ + // If OperationRegion ID = PCI_Config + // + If (LEqual (Arg0, 2)) + { + // If access is enabled + // + If (LEqual(Arg1, 1)) + { + // Set local flag + // + Store (One, OPAC) + } + Else + { + // Clear local flag + // + Store (One, OPAC) + } + } +} + +// +// Enable/disable ports on this controller to wake the system +// +Method (_PSW,1) +{ + If (Arg0) + { + Store (Ones,PWUC) + } + Else + { + Store (0,PWUC) + } +} + +// +// Initialization for this controller +// +Method (_INI, 0) +{ + // If access to OperationRegion is enabled + // + If (LEqual (OPAC, One)) + { + Store (1, PMES) // clear PME status + Store (0, PMEE) // clear PME enable + } +} + +// The CRB leaves the USB ports on in S3/S4 to allow +// the ability to Wake from USB. Therefore, define +// the below control methods to state D2 entry during +// the given S-State. + +Method(_S3D,0) +{ + Return(2) +} + +Method(_S4D,0) +{ + Return(2) +} + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci2.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci2.asi new file mode 100644 index 0000000000..027a362ee5 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci2.asi @@ -0,0 +1,98 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Name (OPAC, 0) + +OperationRegion(PWKE,PCI_Config,0x54,0x18) +Field(PWKE,DWordAcc,NoLock,Preserve) +{ + , 8, + PMEE, 1, // PWR_CNTL_STS.PME_En + , 6, + PMES, 1, // PWR_CNTL_STS.PME_Sts + Offset (0x0E), + , 1, + PWUC, 10 // Port Wake Up Capability Mask +} + +// +// Indicate access to OperationRegions is enabled/disabled +// +Method (_REG, 2) +{ + // If OperationRegion ID = PCI_Config + // + If (LEqual (Arg0, 2)) + { + // If access is enabled + // + If (LEqual(Arg1, 1)) + { + // Set local flag + // + Store (One, OPAC) + } + Else + { + // Clear local flag + // + Store (One, OPAC) + } + } +} + +// +// Enable/disable ports on this controller to wake the system +// +Method (_PSW,1) +{ + If (Arg0) + { + Store (Ones,PWUC) + } + Else + { + Store (0,PWUC) + } +} + +// +// Initialization for this controller +// +Method (_INI, 0) +{ + // If access to OperationRegion is enabled + // + If (LEqual (OPAC, One)) + { + Store (1, PMES) // clear PME status + Store (0, PMEE) // clear PME enable + } +} + +// The CRB leaves the USB ports on in S3/S4 to allow +// the ability to Wake from USB. Therefore, define +// the below control methods to state D2 entry during +// the given S-State. + +Method(_S3D,0) +{ + Return(2) +} + +Method(_S4D,0) +{ + Return(2) +} + + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchGbe.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchGbe.asl new file mode 100644 index 0000000000..9919367878 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchGbe.asl @@ -0,0 +1,23 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +/// +/// Gbe Ethernet ASL methods and structures +/// + + // + // GPE bit 13 indicates wake from this device, can wakeup from S4 state + // + Method(_PRW, 0) { + Return(Package() {13, 4}) + } \ No newline at end of file diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchLpc.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchLpc.asi new file mode 100644 index 0000000000..51b4f99d3c --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchLpc.asi @@ -0,0 +1,28 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// +// Define bits in LPC bridge config space +// (\_SB.PCI0.LPC0) +// +OperationRegion (LPCB, PCI_Config, 0x00, 0x100) +Field (LPCB, DWordAcc, NoLock, Preserve) +{ + Offset (0xAC), + , 16, + XSMB, 1 // set when OS routes USB ports to xHCI in SmartAuto mode so next POST will know +} + +#include "IrqLink.asl" // PCI routing control methods +#include "Mother.asi" // Static motherboard device resource declaration + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchSata.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchSata.asi new file mode 100644 index 0000000000..2fdfd2cb1d --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchSata.asi @@ -0,0 +1,813 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + OperationRegion (IDER,PCI_Config,0x40,0x20) + Field (IDER, AnyAcc, NoLock, Preserve) + { + PFT0 , 1 , // Drive 0 Fast Timing Bank (TIME0) + PIE0 , 1 , // Drive 0 IORDY Sample Point Enable (IE0) + PPE0 , 1 , // Drive 0 Prefetch/Posting Enable (PPE0) + PDE0 , 1 , // Drive 0 DMA Timing Enable (DTE0) + PFT1 , 1 , // Drive 1 Fast Timing Bank (TIME1) + PIE1 , 1 , // Drive 1 IORDY Sample Point Enable (IE1) + PPE1 , 1 , // Drive 1 Prefetch/Posting Enable (PPE1) + PDE1 , 1 , // Drive 1 DMA Timing Enable (DTE1) + PRT0 , 2 , // Drive 0 Recovery Time (RCT) + , 2 , // Reserved + PIP0 , 2 , // Drive 0 IORDY Sample Point (ISP) + PSIT , 1 , // Drive 1 Timing Register Enable (SITRE) + PIDE , 1 , // IDE Decode Enable (IDE) + offset (0x2) , + SFT0 , 1 , // Drive 0 Fast Timing Bank (TIME0) + SIE0 , 1 , // Drive 0 IORDY Sample Point Enable (IE0) + SPE0 , 1 , // Drive 0 Prefetch/Posting Enable (PPE0) + SDE0 , 1 , // Drive 0 DMA Timing Enable (DTE0) + SFT1 , 1 , // Drive 1 Fast Timing Bank (TIME1) + SIE1 , 1 , // Drive 1 IORDY Sample Point Enable (IE1) + SPE1 , 1 , // Drive 1 Prefetch/Posting Enable (PPE1) + SDE1 , 1 , // Drive 1 DMA Timing Enable (DTE1) + SRT0 , 2 , // Drive 0 Recovery Time (RCT) + , 2 , // Reserved + SIP0 , 2 , // Drive 0 IORDY Sample Point (ISP) + SSIT , 1 , // Drive 1 Timing Register Enable (SITRE) + SIDE , 1 , // IDE Decode Enable (IDE) + + PRT1 , 2 , // Drive 1 Recovery Time (RCT) + PIP1 , 2 , // Drive 1 IORDY Sample Point (ISP) + SRT1 , 2 , // Drive 1 Recovery Time (RCT) + SIP1 , 2 , // Drive 1 IORDY Sample Point (ISP) + + offset (0x08) , + + UDM0 , 1 , // Primary Drive 0 Synchronous DMA Mode Enable + UDM1 , 1 , // Primary Drive 1 Synchronous DMA Mode Enable + UDM2 , 1 , // Secondary Drive 0 Synchronous DMA Mode Enable + UDM3 , 1 , // Secondary Drive 1 Synchronous DMA Mode Enable + + offset (0x0A) , + + PCT0 , 2 , // Primary Drive 0 Cycle Time (PCT0) + , 2 , // Reserved + PCT1 , 2 , // Primary Drive 1 Cycle Time (PCT1) + , 2 , // Reserved + SCT0 , 2 , // Secondary Drive 0 Cycle Time (SCT0) + , 2 , // Reserved + SCT1 , 2 , // Secondary Drive 1 Cycle Time (SCT1) + + offset (0x14) , + PCB0 , 1 , // Primary Drive 0 Base Clock (PCB0) + PCB1 , 1 , // Primary Drive 0 Base Clock (PCB0) + SCB0 , 1 , // Secondary Drive 1 Base Clock (SCB0) + SCB1 , 1 , // Secondary Drive 1 Base Clock (SCB1) + PCCR , 2 , // Primary Channel Cable Reporting + SCCR , 2 , // Secondary Channel Cable Reporting + , 4 , // Reserved + PUM0 , 1 , // Primary Drive 0 UDMA 5 Supported + PUM1 , 1 , // Primary Drive 1 UDMA 5 Supported + SUM0 , 1 , // Secondary Drive 0 UDMA 5 Supported + SUM1 , 1 , // Secondary Drive 1 UDMA 5 Supported + PSIG , 2 , // PRIM_SIG_MODE + SSIG , 2 , // SEC_SIG_MODE + } + + // + // Get PIO Timing + // Arg0 Fast PIO Timing + // Arg1 DMA Fast Timing + // Arg2 RCT Timing + // Arg3 ISP Timing + // + + Method(GPIO,4) + { + + If (LEqual (Or (Arg0, Arg1) , 0) ) { + // + // No PIO Timing and DMA Timing support + // + Return (0xFFFFFFFF) + + } Else { + If (And ( LEqual (Arg0, 0) , LEqual (Arg1, 1) ) ) { + // + // Compatible PIO timing support + // + Return (900) + } + } + + // + // Using ISP and RCT timing , PCI Clock = 33 Mhz , 30ns per clock + // + Return (Multiply(30,Subtract(9,Add(Arg2,Arg3)))) + } + // + // Get DMA Timing + // Arg0 UDMA Supported + // Arg1 Ata100 + // Arg2 Ata66/33 + // Arg3 Cable report / SATA No mater this input + // Arg4 Cycle Timing + // + Method(GDMA,5) + { + // + // Ultra DMA 66 & 100 need 80 pin conductor + // + If (LEqual (Arg0, 1)) { + // + // Ultra DMA Support + // + If (LEqual (Arg1, 1)) { + // + // ATA100 80 pin conducter support , Ultra DMA 5 Support + // + If (LEqual (Arg4, 2)) { + Return (15) + } + Return (20) + + } + If (LEqual (Arg2, 1)) { + // + // ATA66 80 pin conducter support , Base Clock 66Mhz , 15ns per clock + // + Return (Multiply(15,Subtract(4,Arg4))) + } + // + // Else Ultra DMA33Mhz Supported only,Base Clock 33Mhz , 30ns per clock + // + Return (Multiply(30,Subtract(4,Arg4))) + } + // Doesnt support DMA mode + + Return (0xFFFFFFFE) + } + // + // Set Flag + // Arg0 IORDY for drive 0 + // Arg1 Ultra DMA for drive 0 + // Arg2 IORDY for drive 1 + // Arg3 Ultra DMA for drive 1 + // Arg4 indicates chipset can set timing independently for each drive + // + Method(SFLG, 5) + { + // + // The Chipset always support separate timing setting and always support IORDY + // + Store (0, Local0) + Or (Arg1 ,Local0,Local0) + Or (ShiftLeft (Arg0,1) ,Local0, Local0) + Or (ShiftLeft (Arg2,3) ,Local0, Local0) + Or (ShiftLeft (Arg3,2) ,Local0, Local0) + Or (ShiftLeft (Arg4,4) ,Local0, Local0) + Return (Local0) + } + // + // Set PIO Timing + // Arg0 Timing + // Arg1 ATA Device PIO Mode Supported Flag + // Arg2 ATA Device PIO Mode Supported Timing + // + // PIO/Mode Timing + // PIO0/Compatible 900 ns + // PIO2/SW2 240 ns + // PIO3/MW1 180 ns + // PIO4/MW2 120 ns + // + + Method(SPIO , 3) + { + Name(PBUF, Buffer(5) { 0x00,0x00,0x00,0x00,0x00}) + CreateByteField(PBUF, 0, RCT) + CreateByteField(PBUF, 1, ISP) + CreateByteField(PBUF, 2, FAST) + CreateByteField(PBUF, 3, DMAE) + CreateByteField(PBUF, 4, PIOT) + If (LOr (LEqual (Arg0, 0x0), LEqual (Arg0, 0x0FFFFFFFF)) ) { + + Return (PBUF) + } + If (LGreater (Arg0, 240)) { + // + // Compatible timing + // + Store (1, DMAE) // PIO Mode 0 + Store (0, PIOT) // Set to PIO Mode 0 + + } Else { + // + // Fast Timing Enable + // + Store (1, FAST) + + If (And (Arg1, 0x002)) { + // + // ATA Device Supported PIO Mode Report + // + If (And (LEqual (Arg0, 120), And( Arg2 , 0x002) ) ) { + // + // Device support PIO Mode 4 + // + Store (3, RCT) // RCT = 1 CLK + Store (2, ISP) // ISP = 3 CLK + Store (4, PIOT) // Set to PIO Mode 4 + } Else { + If (And (LLessEqual (Arg0, 180), And( Arg2 , 0x001) ) ) { + // + // Device support PIO Mode 3 + // + Store (1, RCT) // RCT = 3 CLK + Store (2, ISP) // ISP = 3 CLK + Store (3, PIOT) // Set to PIO Mode 3 + } Else { + // + // PIO Mode 2 + // + Store (0, RCT) // RCT = 4 CLK + Store (1, ISP) // ISP = 4 CLK + Store (2, PIOT) // Set to PIO Mode 2 + } + } + } + } + Return (PBUF) + } + // + // Set DMA Timing + // Arg0 Timing + // Arg1 ATA Device PIO Mode Supported Flag + // Arg2 ATA Device PIO Mode Supported Timing + // + // UDMA/Mode Timing + // UDMA5 20 ns + // UDMA4 30 ns + // UDMA3 45 ns + // UDMA2 60 ns + // UDMA1 90 ns + // UDMA0 120 ns + // + + Method(SDMA , 3) + { + Name(PBUF, Buffer(5) { 0x00,0x00,0x00,0x00}) + CreateByteField(PBUF, 0, PCT) + CreateByteField(PBUF, 1, PCB) + CreateByteField(PBUF, 2, UDMT) // ATA 100 Support + CreateByteField(PBUF, 3, UDME) // Ultra DMA Enable + CreateByteField(PBUF, 4, DMAT) + If (LOr (LEqual (Arg0, 0x0), LEqual (Arg0, 0x0FFFFFFFF)) ) { + + Return (PBUF) + } + If (LLessEqual (Arg0, 120)) { + // + // Ultra DMA Supported + // + If (And (Arg1, 0x004)) { + // + // ATA Device Supported UDMA Mode Report + // + Store (1, UDME) + If (And (LEqual (Arg0, 15), And( Arg2 , 0x0040) ) ) { + // + // Ultra DMA 6 + // + Store (1, UDMT) + Store (1, PCB) + Store (2, PCT) + Store (6, DMAT) // Set to UDMA Mode 6 + } Else { + If (And (LEqual (Arg0, 20), And( Arg2 , 0x0020) ) ) { + // + // Ultra DMA 5 + // + Store (1, UDMT) + Store (1, PCB) + Store (1, PCT) + Store (5, DMAT) // Set to UDMA Mode 5 + } Else { + + If (And (LLessEqual (Arg0, 30), And( Arg2 , 0x00010) ) ) { + // + // Ultra DMA 4 + // + Store (1, PCB) + Store (2, PCT) + Store (4, DMAT) // Set to UDMA Mode 4 + + } Else { + + If (And (LLessEqual (Arg0, 45), And( Arg2 , 0x0008) ) ) { + // + // Ultra DMA 3 + // + Store (1, PCB) + Store (1, PCT) + Store (3, DMAT) // Set to UDMA Mode 3 + + } Else { + + If (And (LLessEqual (Arg0, 60), And( Arg2 , 0x0004) ) ) { + // + // Ultra DMA 2 + // + Store (2, PCT) + Store (2, DMAT) // Set to UDMA Mode 2 + } Else { + + If (And (LLessEqual (Arg0, 90), And( Arg2 , 0x0002) ) ) { + // + // Ultra DMA 1 + // + Store (1, PCT) + Store (1, DMAT) // Set to UDMA Mode 1 + } Else { + + If (And (LLessEqual (Arg0, 120), And( Arg2 , 0x0001) ) ) { + // + // Ultra DMA 0 + // + Store (0, DMAT) // Set to UDMA Mode 0 + } + }}}}}} + } + } + Return (PBUF) + } + + + // + // Primary ide channel + // + Device(PRID) + { + Name(_ADR,0) + Name(TDM0, 0) // Drive 0 Ultra DMA Type + Name(TPI0, 0) // Drive 0 PIO Type + Name(TDM1, 0) // Drive 1 Ultra DMA Type + Name(TPI1, 0) // Drive 1 PIO Type + + Method(_GTM) + { + Name(PBUF, Buffer(20) { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00 }) + + CreateDwordField(PBUF, 0, PIO0) + CreateDwordField(PBUF, 4, DMA0) + CreateDwordField(PBUF, 8, PIO1) + CreateDwordField(PBUF, 12, DMA1) + CreateDwordField(PBUF, 16, FLAG) + + Store ( GPIO (PFT0, PDE0, PRT0, PIP0 ), PIO0) + // + // Setting the Drive1 PIO Timing, check if we use the same timging for + // both Drive0 and Drive1, and if the Drive0 is attached, else use + // separate timing + // + + If ( And (PSIT, 1) ) { + Store ( GPIO (PFT1, PDE1, PRT1, PIP1 ), PIO1) + } Else { + Store ( GPIO (PFT1, PDE1, PRT0, PIP0 ), PIO1) + } + + If (LEqual (PIO0, 0xFFFFFFFF)) { + Store(PIO0, DMA0) + } Else { + Store ( GDMA(UDM0, PUM0, PCB0,And (PCCR ,0x1), PCT0) , DMA0) + If ( LGreater ( DMA0, PIO0)) { + Store(PIO0, DMA0) + } + } + If (LEqual (PIO1, 0xFFFFFFFF)) { + Store(PIO1, DMA1) + } Else { + Store ( GDMA(UDM1, PUM1, PCB1,And (PCCR ,0x2), PCT1) , DMA1) + If ( LGreater ( DMA1, PIO1)) { + Store(PIO1, DMA1) + } + } + Store (SFLG (PIE0, UDM0, PIE1, UDM1, 1), FLAG) + + Return (PBUF) + } + + Method(_STM,3) + { + CreateDwordField(Arg0, 0, PIO0) + CreateDwordField(Arg0, 4, DMA0) + CreateDwordField(Arg0, 8, PIO1) + CreateDwordField(Arg0, 12, DMA1) + CreateDwordField(Arg0, 16, FLAG) + + // + // Device 0 Raw data + // + CreateWordField(Arg1, 106, RPS0) // word 53 + CreateWordField(Arg1, 128, IOM0) // word 64 + CreateWordField(Arg1, 176, DMM0) // Word 88 + + // + // Device 1 Raw data + // + CreateWordField(Arg2, 106, RPS1) // word 53 + CreateWordField(Arg2, 128, IOM1) // word 64 + CreateWordField(Arg2, 176, DMM1) // Word 88 + + Name(IOTM, Buffer(5) { 0x00,0x00,0x00,0x00}) + + CreateByteField(IOTM, 0, RCT) + CreateByteField(IOTM, 1, ISP) + CreateByteField(IOTM, 2, FAST) + CreateByteField(IOTM, 3, DMAE) + CreateByteField(IOTM, 4, TPIO) // PIO Type + + Name(DMAT, Buffer(5) { 0x00,0x00,0x00,0x00}) + + CreateByteField(DMAT, 0, PCT) + CreateByteField(DMAT, 1, PCB) + CreateByteField(DMAT, 2, UDMT) // ATA 100 Support + CreateByteField(DMAT, 3, UDME) // Ultra DMA Enable + CreateByteField(DMAT, 4, TDMA) // UDMA Type + + If (And (FLAG , 0x10)) { + Store (1, PSIT) + } + + Store (SPIO (PIO0,RPS0,IOM0), IOTM) + + If (Or (DMAE, FAST)) { + Store (RCT, PRT0) + Store (ISP, PIP0) + Store (FAST, PFT0) + Store (DMAE, PDE0) + Store (TPIO, TPI0) + } + Store (SPIO (PIO1,RPS1,IOM1), IOTM) + + If (Or (DMAE, FAST)) { + Store (FAST, PFT1) + Store (DMAE, PDE1) + Store (TPIO, TPI1) + If (And (PSIT,1)) { + // + // Need set Drive 1 PIO Timing seperate + // + Store (RCT, PRT1) + Store (ISP, PIP1) + } Else { + Store (RCT, PRT0) + Store (ISP, PIP0) + } + } + If (And (FLAG , 0x01)) { + Store (SDMA (DMA0,RPS0,DMM0), DMAT) + Store (PCT , PCT0) + Store (PCB , PCB0) + Store (UDME, UDM0) + Store (UDMT, PUM0) + Store (TDMA, TDM0) + } Else { + Store (0, UDM0) + } + + If (And (FLAG , 0x04)) { + Store (SDMA (DMA1,RPS1,DMM1), DMAT) + Store (PCT , PCT1) + Store (PCB , PCB1) + Store (UDME, UDM1) + Store (UDMT, PUM1) + Store (TDMA, TDM1) + } Else { + Store (0, UDM1) + } + // + // Check IORDY Support + // + If (And (FLAG , 0x2)) { + Store (1 , PIE0) + } + If (And (FLAG , 0x8)) { + Store (1 , PIE1) + } + + } + Device(MAST) + { + Name(_ADR,0) + Method(_GTF) + { + // + // Set ATA Device to corresponding Mode + // + Name(ATA0, Buffer(14) + { 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF }) + + CreateByteField(ATA0,1,PIO0) // PIO0 = PIO Mode, Drive 0 + CreateByteField(ATA0,8,DMA0) // DMA0 = DMA Mode, Drive 0 + + + Store (TPI0, PIO0) // Type we Already get + + Or (PIO0, 0x08 ,PIO0) + + If ( And (UDM0, 1)) { + Store (TDM0, DMA0) // Ultra DMA + Or (DMA0, 0x40, DMA0) + } Else { + Store (TPI0, DMA0) // Use PIO Timing + If ( LNotEqual (DMA0, 0)) { + Subtract(DMA0, 2, DMA0) + } + Or (DMA0, 0x20, DMA0) + } + Return (ATA0) + } + } + Device(SLAV) + { + Name(_ADR,1) + Method(_GTF) + { + // + // Set ATA Device to corresponding Mode + // + Name(ATA1, Buffer(14) + { 0x03, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xEF }) + + CreateByteField(ATA1,1,PIO1) // PIO0 = PIO Mode, Drive 0 + CreateByteField(ATA1,8,DMA1) // DMA0 = DMA Mode, Drive 0 + + Store (TPI1, PIO1) // Type we Already get + + Or (PIO1, 0x08 ,PIO1) + + If ( And (UDM1, 1)) { + Store (TDM1, DMA1) // Ultra DMA + Or (DMA1, 0x40, DMA1) + } Else { + Store (TPI1, DMA1) // Use PIO Timing + If ( LNotEqual (DMA1, 0)) { + Subtract(DMA1, 2, DMA1) + } + Or (DMA1, 0x20, DMA1) + } + Return(ATA1) + } + } + } + // + // Secondary SATA channel + // + Device(SECD) + { + Name(_ADR,1) + Name(TDM0, 0) + Name(TPI0, 0) + Name(TDM1, 0) + Name(TPI1, 0) + + Name(DMT1, Buffer(5) { 0x00,0x00,0x00,0x00}) + Name(DMT2, Buffer(5) { 0x00,0x00,0x00,0x00}) + Name(POT1, Buffer(5) { 0x00,0x00,0x00,0x00}) + Name(POT2, Buffer(5) { 0x00,0x00,0x00,0x00}) + + Name(STMI, Buffer(20) { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00 }) + + Method(_GTM) + { + Name(PBUF, Buffer(20) { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00 }) + + CreateDwordField(PBUF, 0, PIO0) + CreateDwordField(PBUF, 4, DMA0) + CreateDwordField(PBUF, 8, PIO1) + CreateDwordField(PBUF, 12, DMA1) + CreateDwordField(PBUF, 16, FLAG) + + Store ( GPIO (SFT0, SDE0, SRT0, SIP0 ), PIO0) + // + // Setting the Drive1 PIO Timing, check if we use the same timging for + // both Drive0 and Drive1, and if the Drive0 is attached, else use + // separate timing + // + If ( And (SSIT, 1) ) { + Store ( GPIO (SFT1, SDE1, SRT1, SIP1 ), PIO1) + } Else { + Store ( GPIO (SFT1, SDE1, SRT0, SIP0 ), PIO1) + } + + If (LEqual (PIO0, 0xFFFFFFFF)) { + Store(PIO0, DMA0) + } Else { + Store ( GDMA(UDM2, SUM0, SCB0,And (SCCR ,0x1), SCT0) , DMA0) + If ( LGreater ( DMA0, PIO0)) { + Store(PIO0, DMA0) + } + } + + If (LEqual (PIO1, 0xFFFFFFFF)) { + Store(PIO1, DMA1) + } Else { + Store ( GDMA(UDM3, SUM1, SCB1,And (SCCR ,0x2), SCT1) , DMA1) + If ( LGreater ( DMA1, PIO1)) { + Store(PIO1, DMA1) + } + } + + Store (SFLG (SIE0, UDM2, SIE1, UDM3, 1), FLAG) + + Return (PBUF) + } + Method(_STM,3) + { + CreateDwordField(Arg0, 0, PIO0) + CreateDwordField(Arg0, 4, DMA0) + CreateDwordField(Arg0, 8, PIO1) + CreateDwordField(Arg0, 12, DMA1) + CreateDwordField(Arg0, 16, FLAG) + + Store (Arg0, STMI) + // + // Device 0 Raw data + // + CreateWordField(Arg1, 106, RPS0) // word 53 + CreateWordField(Arg1, 128, IOM0) // word 64 + CreateWordField(Arg1, 176, DMM0) // Word 88 + + // + // Device 1 Raw data + // + CreateWordField(Arg2, 106, RPS1) // word 53 + CreateWordField(Arg2, 128, IOM1) // word 64 + CreateWordField(Arg2, 176, DMM1) // Word 88 + + Name(IOTM, Buffer(5) { 0x00,0x00,0x00,0x00}) + + CreateByteField(IOTM, 0, RCT) + CreateByteField(IOTM, 1, ISP) + CreateByteField(IOTM, 2, FAST) + CreateByteField(IOTM, 3, DMAE) + CreateByteField(IOTM, 4, TPIO) // PIO Type + + Name(DMAT, Buffer(5) { 0x00,0x00,0x00,0x00}) + + CreateByteField(DMAT, 0, PCT) + CreateByteField(DMAT, 1, PCB) + CreateByteField(DMAT, 2, UDMT) // ATA 100 Support + CreateByteField(DMAT, 3, UDME) // Ultra DMA Enable + CreateByteField(DMAT, 4, TDMA) // UDMA Type + + If (And (FLAG , 0x10)) { + Store (1, SSIT) + } + + // + // Get Timing and Flag Setting + // + Store (SPIO (PIO0,RPS0,IOM0), IOTM) + // + // If no drive0 connect, do nothing to program Drive0 timing + // + If (Or (DMAE, FAST)) { + Store (RCT, SRT0) + Store (ISP, SIP0) + Store (FAST, SFT0) + Store (DMAE, SDE0) + Store (TPIO, TPI0) + } + + Store (SPIO (PIO1,RPS1,IOM1), IOTM) + + Store (IOTM,POT2) + + If (Or (DMAE, FAST)) { + Store (FAST, SFT1) + Store (DMAE, SDE1) + Store (TPIO, TPI1) + If (And (SSIT,1)) { + // + // Need set Drive 1 PIO Timing separately + // + Store (RCT, SRT1) + Store (ISP, SIP1) + } Else { + Store (RCT, SRT0) + Store (ISP, SIP0) + } + } + + If (And (FLAG , 0x01)) { + Store (SDMA (DMA0,RPS0,DMM0), DMAT) + Store (PCT , SCT0) + Store (PCB , SCB0) + Store (UDME , UDM2) + Store (UDMT , SUM0) + Store (TDMA, TDM0) + } Else { + Store (0, UDM2) + } + If (And (FLAG , 0x04)) { + Store (SDMA (DMA1,RPS1,DMM1), DMAT) + Store (PCT , SCT1) + Store (PCB , SCB1) + Store (UDME , UDM3) + Store (UDMT , SUM1) + Store (TDMA , TDM1) + } Else { + Store (0, UDM3) + } + // + // Check IORDY Support + // + If (And (FLAG , 0x2)) { + Store (1 , SIE0) + } + If (And (FLAG , 0x8)) { + Store (1 , SIE1) + } + + } + Device(MAST) + { + Name(_ADR,0) + Method(_GTF) + { + // + // Set ATA Device to corresponding Mode + // + Name(ATA0, Buffer(14) + { 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF }) + + CreateByteField(ATA0,1,PIO0) // PIO0 = PIO Mode, Drive 0 + CreateByteField(ATA0,8,DMA0) // DMA0 = DMA Mode, Drive 0 + + Store (TPI0, PIO0) // Type we Already get + + Or (PIO0, 0x08 ,PIO0) + + If ( And (UDM2, 1)) { + Store (TDM0, DMA0) // Ultra DMA + Or (DMA0, 0x40, DMA0) + } Else { + Store (TPI0, DMA0) // Use PIO Timing + If ( LNotEqual (DMA0, 0)) { + Subtract(DMA0, 2, DMA0) + } + Or (DMA0, 0x20, DMA0) + } + Return (ATA0) + } + } + Device(SLAV) + { + Name(_ADR,1) + Method(_GTF) + { + // + // Set ATA Device to corresponding Mode + // + Name(ATA1, Buffer(14) + { 0x03, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xEF }) + + CreateByteField(ATA1,1,PIO1) // PIO0 = PIO Mode, Drive 0 + CreateByteField(ATA1,8,DMA1) // DMA0 = DMA Mode, Drive 0 + + Store (TPI1, PIO1) // Type we Already get + + Or (PIO1, 0x08 ,PIO1) + + If ( And (UDM3, 1)) { + Store (TDM1, DMA1) // Ultra DMA + Or (DMA1, 0x40, DMA1) + } Else { + Store (TPI1, DMA1) // Use PIO Timing + If ( LNotEqual (DMA1, 0)) { + Subtract(DMA1, 2, DMA1) + } + Or (DMA1, 0x20, DMA1) + } + Return(ATA1) + } + } + } diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchXhci.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchXhci.asi new file mode 100644 index 0000000000..22a4ab5234 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchXhci.asi @@ -0,0 +1,335 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Name (OPAC, Zero) +Name (XRST, Zero) +Name (XUSB, Zero) + +OperationRegion (XPRT, PCI_Config, 0x74, 0x6C) +Field (XPRT, DWordAcc, NoLock, Preserve) +{ + , 8, + PMEE, 1, // PWR_CNTL_STS.PME_En + , 6, + PMES, 1, // PWR_CNTL_STS.PME_Sts + Offset (0x5C), + PR2, 32, // XUSB2PR: xHC USB 2.0 Port Routing Register. + PR2M, 32, // XUSB2PRM: xHC USB 2.0 Port Routing Mask Register. + PR3, 32, // USB3_PSSEN: USB3.0 Port SuperSpeed Enable Register. + PR3M, 32 // USB3PRM: USB3.0 Port Routing Mask Register +} + +Method (_PSW,1) +{ + If (Arg0) + { + Store (Ones,PMEE) + } + Else + { + Store (0,PMEE) + } +} + + +// +// Indicate access to OperationRegions is enabled/disabled +// +Method (_REG, 2) { + // + // If OperationRegion ID = PCI_Config + // + If (LEqual (Arg0, 2)) { + // + // If access is enabled + // + If (LEqual(Arg1, 1)) { + // + // Set local flag + // + Store (One, OPAC) + + } Else { + // + // Clear local flag + // + Store (One, OPAC) + } + } +} + +// +// Initialization for this controller +// +Method (_INI, 0) { + // + // If access to OperationRegion is enabled + // + If (LEqual (OPAC, One)) { + Store (1, PMES) // clear PME status + Store (0, PMEE) // clear PME enable + } +} + +// +// _OSC for xHCI +// This method enables XHCI controller if available. +// +// Arguments: +// Arg0 (Integer): Revision ID - should be set to 1 +// +// Arg1 (Integer): Count of DWords in Arg3 +// +// Arg2 (Buffer) : Capabilities Buffer +// DWORD #0 (Status/Error): +// Bit 0 - Query Support Flag +// Bit 1 - Always clear(0) +// Bit 2 - Always clear(0) +// Bit 3 - Always clear(0) +// +// All others - reserved +// +// DWORD #1 (Supported): +// Bit 0 - 1: Switch to xHCI +// +// All others - reserved +// +// DWORD #2 (Controlled): +// Bit 0 - 1: Clear Smart Auto state (disable xHCI) +// +// All others - reserved +// +// Returns: +// Capabilities Buffer: +// DWORD #0 (Status): +// Bit 0 - Reserved (not used) +// +// Bit 1 - _OSC failure. Platform Firmware was unable to process the request or query. +// Capabilities bits may have been masked. +// +// Bit 2 - Unrecognized UUID. This bit is set to indicate that the platform firmware +// does not recognize the UUID passed in _OSC Arg0. +// Capabilities bits are preserved. +// +// Bit 3 - Unrecognized Revision. This bit is set to indicate that the platform firmware +// does not recognize the Revision ID passed in via Arg1. +// Capabilities bits beyond those comprehended by the firmware will be masked. +// +// Bit 4 - Capabilities Masked. This bit is set to indicate +// that capabilities bits set by driver software +// have been cleared by platform firmware. +// +// Bit 5 - 0: EHCI controller exposed to OS +// 1: xHCI controller exposed to OS +// +// All others - reserved (return 0) +// +// DWORD #1 (Supported): +// Bit 0 - 0: EHCI supported +// 1: xHCI supported +// +// All others - reserved +// +// DWORD #2 (Controlled): +// +// All bits - reserved +// + +Method (POSC, 3) { + + Store (0x81, IO80) + + // + // Create DWord fields from the Capabilities Buffer + // + CreateDWordField (Arg2, 0, CDW1) // CDW1 = DWORD that starts at offset 0 of Arg2 + CreateDWordField (Arg2, 4, CDW2) // CDW2 = DWORD that starts at offset 4 of Arg2 + CreateDWordField (Arg2, 8, CDW3) // CDW3 = DWORD that starts at offset 8 of Arg2 + + // + // Are we running a version of Windows that runs the Intel xHCI driver? + // i.e. Windows Server 2008 through Windows Server 2008 R2 & Windows 7 + // + If (LAnd (LGreaterEqual (\_SB.OSYS, 9), LLessEqual (\_SB.OSYS, 12))) { + // + // Running Windows + // Check revision is >= 2 + // + If (LLess (Arg0, 2)) { + // + // Set unknown revision bit + // + Or (CDW1, 8, CDW1) + Store (0x82, IO80) + } + } Else { + // + // If the Intel xHCI driver not calling, + // then it must be SVOS + If (LNotEqual (Arg0, 1)) { + // + // Set unknown revision bit + // + Or (CDW1, 8, CDW1) + Store (0x82, IO80) + } + } + + // + // Set failure if xHCI is disabled by BIOS + // + If (LEqual (XHMD, 0)) { + Or (CDW1, 2, CDW1) + Store (0x83, IO80) + } + + // + // If no error bits set + // + If (LEqual (And (CDW1, 0xE), 0)) { + // + // If not just querying support + // + If (LNot (And (CDW1, 1))) { + // + // If uninstaller calling + // to switch back to EHCI + // + If (And (CDW3, 1)) { + // + // Switch to EHCI + // + ESEL() + Store (0x85, IO80) + + // + // And clear ACPINVS variable + // that is a copy of USB3.0 setup option + // so that we will not re-enable xHCI until + // the next reboot + // + Store (0, XHMD) + } + + // + // Uninstaller not calling, + // OS wants to enable xHCI? + // + If (And (CDW2, 1)) { + // + // Switch to xHCI + // + XSEL(0) + Store (0x84, IO80) + } Else { + // + // Switch to EHCI + // + ESEL() + Store (0x85, IO80) + } + } + } + + Return(Arg2) +} + +// +// Put all ports in XHCI mode +// +Method (XSEL, 1, Serialized) { + // + // If xHCI in auto or smart auto mode + // or Arg0 == 1 + // + If ( LOr (LOr (LEqual (XHMD, 2), LEqual (XHMD, 3)), Arg0) ) { + // + // If xHCI in smart auto mode + // + If (LEqual (XHMD, 3)) { + // + // Set B0:D31:F0 ACh[16] to indicate OS has routed ports to xHCI controller + // + Store (1, \_SB.PC00.LPC0.XSMB) + } + + // + // Set flags so on Sx resume, we'll know OS has previously + // routed ports to xHCI + // + Store (1, XUSB) + Store (1, XRST) // Backup XUSB, cause it might lost in iRST G3 or DeepSx + + // + // Enable selected SS ports, route corresponding HS ports to xHCI + // + Store (0, Local0) + And (PR3, 0xFFFFFFC0, Local0) + Or (Local0, PR3M, PR3) + Store (0, Local0) + And (PR2, 0xFFFF8000, Local0) + Or (Local0, PR2M, PR2) + } +} + +// +// Put all ports in EHCI mode +// +Method (ESEL, 0, Serialized) { + // + // xHCI in auto or smart auto mode + // + If (LOr (LEqual (XHMD, 2), LEqual (XHMD, 3))) { + // + // Disable all SS ports, route all HS ports to EHCI + // + And (PR3, 0xFFFFFFC0, PR3) + And (PR2, 0xFFFF8000, PR2) + + // + // Mark as not routed. + // + Store (0, XUSB) + Store (0, XRST) + } +} + +Method (XWAK, 0, Serialized) { + // + // If ports were routed to xHCI before sleep + // + If (LOr (LEqual (XUSB, 1), LEqual (XRST, 1))) { + // + // Restore back to xHCI, ignore XHMD + // + XSEL(1) + + // + // And tell OS to re-enumerate xHCI + // + Notify (\_SB.PC00.XHCI, 0x00) + } +} + +// +// Report what D state the controller is in +// when the system changes to S3 and S4 +// +Method(_S3D, 0, NotSerialized) { + Return(2) +} + +Method(_S4D, 0, NotSerialized) { + Return(2) +} + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciCrs.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciCrs.asi new file mode 100644 index 0000000000..6b1613b800 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciCrs.asi @@ -0,0 +1,318 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// Return the proximity domain/node # that this bus is on +// With this info OSPM will know what memory and I/O resources +// are under the same IOH +// +Name(_PXM, 0) + +#define RESOURCE_CHUNK1_OFF 0 +#define RESOURCE_CHUNK2_OFF 16 //(RESOURCE_CHUNK1_OFF + 16) +#define RESOURCE_CHUNK3_OFF 24 //(RESOURCE_CHUNK2_OFF + 8) +#define RESOURCE_CHUNK4_OFF 40 //(RESOURCE_CHUNK3_OFF + 16) +#define RESOURCE_CHUNK5_OFF 56 //(RESOURCE_CHUNK4_OFF + 16) +#define RESOURCE_CHUNK6_OFF 82 //(RESOURCE_CHUNK5_OFF + 26) +#define RESOURCE_CHUNK7_OFF 108 //(RESOURCE_CHUNK6_OFF + 26) + +#define PciResourceStart Local0 +#define PciResourceLen Local1 + +Name(PBRS, ResourceTemplate() { + //RESOURCE_CHUNK1_OFF + WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity + 0x0000, // Min + 0x0000, // Max + 0x0000, // Translation + 0x0000,,, // Range Length = Max-Min+1 + PB00 + ) + + //RESOURCE_CHUNK2_OFF + IO( //Consumed resource (CF8-CFF) + Decode16, + 0x0cf8, + 0xcf8, + 1, + 8 + ) + + //RESOURCE_CHUNK3_OFF + WORDIO( //Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity + 0x0000, // Min + 0x0cf7, // Max + 0x0000, // Translation + 0x0cf8 // Range Length + ) + + //RESOURCE_CHUNK4_OFF + WORDIO( //Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x00, // Granularity + 0x0000, // Min + 0x0000, // Max + 0x00, // Translation + 0x0000,,, // Range Length + PI01 + ) + + //RESOURCE_CHUNK5_OFF + DWORDMEMORY( // descriptor for video RAM on video card + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x000a0000, // Min + 0x000bffff, // Max + 0x00000000, // Translation + 0x00020000 // Range Length + ) + + //RESOURCE_CHUNK6_OFF + DWORDMEMORY( // descriptor for Shadow RAM + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x00000000, // Min (calculated dynamically) + 0x00000000, // Max (calculated dynamically) + 0x00000000, // Translation + 0x00000000,,, // Range Length (calculated dynamically) + SDRM + ) + + //RESOURCE_TPM + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity + 0xFED40000, // Min (calculated dynamically) + 0xFEDFFFFF, // Max = 4GB - 1MB (fwh + fwh alias...) + 0x00000000, // Translation + 0x000C0000 // Range Length (calculated dynamically) + ) + + // + // PCI RESOURCE_32bit + // + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00, // Granularity + 0x00000000, // Min (calculated dynamically) + 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias...) + 0x00, // Translation + 0x00000000,,, // Range Length (calculated dynamically) + PM01 + ) + + // + // PCI RESOURCE_64bit + // + QWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00, // Granularity + 0x00000000000, // Min (calculated dynamically) + 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias...) + 0x00, // Translation + 0x00000000000,,, // Range Length (calculated dynamically) + PM02 + ) +}) // end of PBRS Buffer + + +Method(_CRS, 0x0, NotSerialized) +{ + //calculate Shadow RAM + EROM() + + // Fix up Bus Number Resources + CreateWordField(PBRS, ^PB00._MIN, PBMN) + Store(BBI0, PBMN) + CreateWordField(PBRS, ^PB00._MAX, PBMX) // (MAX bus decoded - 1, assuming Uncore Bus is MAX decoded BUS Number) + Store(BBL0, PBMX) + CreateWordField(PBRS, ^PB00._LEN, PBLN) + Subtract(PBMX, PBMN, PBLN) + Add(1, PBLN, PBLN) + + // Fix up 16-bit IO resources + CreateWordField(PBRS, ^PI01._MIN, PIMN) + Store(IOBA, PIMN) + CreateWordField(PBRS, ^PI01._MAX, PIMX) + Store(IOLA, PIMX) + CreateWordField(PBRS, ^PI01._LEN, PILN) + Subtract(PIMX, PIMN, PILN) + Add(1, PILN, PILN) + + // Fix up 32-bit Memory resources + CreateDWordField(PBRS, ^PM01._MIN, PMMN) + Store(MMB0, PMMN) + CreateDWordField(PBRS, ^PM01._MAX, PMMX) + Store(MML0, PMMX) + CreateDWordField(PBRS, ^PM01._LEN, PMLN) + Subtract(PMMX, PMMN, PMLN) + Add(1, PMLN, PMLN) + + // Fix up 64-bit Memory resources +// If(LAnd(MMH0, LGreater(OSFL, 8))) { + CreateQWordField(PBRS, ^PM02._MIN, P2MN) + Store(HMB0, P2MN) + CreateQWordField(PBRS, ^PM02._MAX, P2MX) + Store(HML0, P2MX) + CreateQWordField(PBRS, ^PM02._LEN, P2LN) + Subtract(P2MX, P2MN, P2LN) + Add(1, P2LN, P2LN) +// } + + Return(PBRS) +} + +Method(_STA,0) { + If (NPB0) { + Return(0x0F) + } + Return(0x00) +} + +OperationRegion(TMEM, PCI_Config, 0x52, 0x3) +Field(TMEM, ByteAcc, NoLock, Preserve) { + DIM0, 4, + DIM1, 4, + , 8, + DIM2, 4 +} + +Name(MTBL, Package(0x10) { + 0x0, + 0x20, + 0x20, + 0x30, + 0x40, + 0x40, + 0x60, + 0x80, + 0x80, + 0x80, + 0x80, + 0xc0, + 0x100, + 0x100, + 0x100, + 0x200 +}) + + +OperationRegion(PAMX, PCI_Config, 0x90, 0x7) +Field(PAMX, ByteAcc, NoLock, Preserve) { + , 4, + BSEG, 4, + PAMS, 48 +} + +Name(ERNG, Package(0xd) { + 0xc0000, + 0xc4000, + 0xc8000, + 0xcc000, + 0xd0000, + 0xd4000, + 0xd8000, + 0xdc000, + 0xe0000, + 0xe4000, + 0xe8000, + 0xec000, + 0xf0000 +}) + +Name(PAMB, Buffer(0x7) { +}) + +Method(EROM, 0x0, NotSerialized) { + CreateDWordField(PBRS, 0x5c, RMIN) + CreateDWordField(PBRS, 0x60, RMAX) + CreateDWordField(PBRS, 0x68, RLEN) + CreateByteField(PAMB, 0x6, BREG) + Store(PAMS, PAMB) + Store(BSEG, BREG) + Store(0x0, RMIN) + Store(0x0, RMAX) + Store(0x0, RLEN) + Store(0x0, Local0) + While(LLess(Local0, 0xd)) { + ShiftRight(Local0, 0x1, Local1) + Store(DerefOf(Index(PAMB, Local1, )), Local2) + If(And(Local0, 0x1, )) { + ShiftRight(Local2, 0x4, Local2) + } + And(Local2, 0x3, Local2) + If(RMIN) { + If(Local2) { + Add(DerefOf(Index(ERNG, Local0, )), 0x3fff, RMAX) + If(LEqual(RMAX, 0xf3fff)) { + Store(0xfffff, RMAX) + } + Subtract(RMAX, RMIN, RLEN) + Increment(RLEN) + } Else { + Store(0xc, Local0) + } + } Else { + If(Local2) { + Store(DerefOf(Index(ERNG, Local0, )), RMIN) + Add(DerefOf(Index(ERNG, Local0, )), 0x3fff, RMAX) + If(LEqual(RMAX, 0xf3fff)) { + Store(0xfffff, RMAX) + } + Subtract(RMAX, RMIN, RLEN) + Increment(RLEN) + } Else { + } + } + Increment(Local0) + } +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciIrq.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciIrq.asi new file mode 100644 index 0000000000..b64b70b76a --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciIrq.asi @@ -0,0 +1,461 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +OperationRegion (PRR0, PCI_Config, 0x00, 0x100) +Field (PRR0, AnyAcc, NoLock, Preserve) { + Offset(0x60), + PIRA, 8, + PIRB, 8, + PIRC, 8, + PIRD, 8, + Offset(0x68), + PIRE, 8, + PIRF, 8, + PIRG, 8, + PIRH, 8 +} + +Device (LNKA) { // PCI IRQ link A + Name (_HID,EISAID("PNP0C0F")) + //Name(_UID, 1) + Method (_STA,0,NotSerialized) { + If(And(PIRA, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } // Don't display + } + + Method (_DIS,0,NotSerialized) { + Or (PIRA, 0x80, PIRA) + } + + Method (_CRS,0,Serialized) { + Name (BUF0, ResourceTemplate() {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And(PIRA, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One,Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0,And (PIRA,0x0F),IRQW) // Save in buffer + Return (BUF0) // Return Buf0 + } // End of _CRS method + + Name (_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + + FindSetRightBit(IRQW,Local0) // Set IRQ + If (LNotEqual (IRQW,Zero)){ + And (Local0, 0x7F,Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80,Local0) + } + Store (Local0, PIRA) + } // End of _SRS Method +} + +Device(LNKB) { // PCI IRQ link B + Name (_HID,EISAID("PNP0C0F")) + //Name(_UID, 2) + Method (_STA,0,NotSerialized) { + If (And (PIRB, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } // Don't display + } + + Method (_DIS,0,NotSerialized) { + Or (PIRB, 0x80,PIRB) + } + + Method (_CRS,0,Serialized) { + Name(BUF0, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (PIRB, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One,Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0,And (PIRB,0x0F),IRQW) // Save in buffer + Return (BUF0) // Return Buf0 + } // End of _CRS method + + Name (_PRS, + ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + + FindSetRightBit(IRQW,Local0) // Set IRQ + If (LNotEqual(IRQW,Zero)) { + And (Local0, 0x7F, Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80, Local0) + } + Store (Local0, PIRB) + } // End of _SRS Method +} + +Device(LNKC) { // PCI IRQ link C + Name(_HID, EISAID("PNP0C0F")) + //Name(_UID, 3) + + Method (_STA,0,NotSerialized) { + If (And (PIRC, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } // Don't display + } + + Method (_DIS, 0, NotSerialized) { + Or (PIRC, 0x80, PIRC) + } + + Method (_CRS, 0, Serialized) { + Name (BUF0, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (PIRC, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One,Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0,And (PIRC,0x0F),IRQW) + Return (BUF0) + } // End of _CRS method + + Name (_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + FindSetRightBit(IRQW,Local0) // Set IRQ + If (LNotEqual (IRQW,Zero)) { + And (Local0, 0x7F, Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80,Local0) + } + Store (Local0, PIRC) + } // End of _SRS Method +} + +Device (LNKD) { // PCI IRQ link D + Name (_HID,EISAID ("PNP0C0F")) + + //Name(_UID, 4) + + Method (_STA, 0, NotSerialized) { + If (And (PIRD, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } // Don't display + } + + Method (_DIS, 0, NotSerialized) { + Or(PIRD, 0x80,PIRD) + } + + Method (_CRS,0,Serialized) { + Name (BUF0, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (PIRD, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One,Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0, And (PIRD,0x0F), IRQW) + Return (BUF0) // Return Buf0 + } // End of _CRS method + + Name (_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + FindSetRightBit (IRQW, Local0)// Set IRQ + If (LNotEqual (IRQW, Zero)) { + And (Local0, 0x7F, Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80, Local0) + } + Store(Local0, PIRD) + } // End of _SRS Method +} + +Device(LNKE) { // PCI IRQ link E + Name(_HID,EISAID("PNP0C0F")) + + //Name(_UID, 5) + + Method (_STA,0,NotSerialized) { + If (And (PIRE, 0x80)) { + Return(0x9) + } Else { + Return(0xB) + } // Don't display + } + + Method (_DIS,0,NotSerialized) { + Or (PIRE, 0x80, PIRE) + } + + Method (_CRS, 0, Serialized) { + Name (BUF0, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (PIRE, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One, Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0, And (PIRE,0x0F), IRQW) + Return (BUF0) // Return Buf0 + } // End of _CRS method + + Name(_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + FindSetRightBit (IRQW, Local0) // Set IRQ + If (LNotEqual (IRQW, Zero)) { + And (Local0, 0x7F, Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80, Local0) + } + Store (Local0, PIRE) + } // End of _SRS Method +} + +Device(LNKF) { // PCI IRQ link F + Name (_HID,EISAID("PNP0C0F")) + + //Name(_UID, 6) + + Method (_STA,0,Serialized) { + If (And (PIRF, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } // Don't display + } + + Method (_DIS,0,NotSerialized) { + Or (PIRB, 0x80, PIRF) + } + + Method (_CRS,0,Serialized) { + Name(BUF0, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (PIRF, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One, Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0, And (PIRF, 0x0F),IRQW) + Return (BUF0) + } // End of _CRS method + + Name(_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + FindSetRightBit (IRQW,Local0) // Set IRQ + If (LNotEqual (IRQW,Zero)) { + And (Local0, 0x7F,Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80, Local0) + } + Store (Local0, PIRF) + } // End of _SRS Method +} + +Device(LNKG) { // PCI IRQ link G + Name(_HID,EISAID("PNP0C0F")) + //Name(_UID, 7) + Method(_STA,0,NotSerialized) { + If (And (PIRG, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } // Don't display + } + + Method (_DIS, 0, NotSerialized) { + Or(PIRG, 0x80,PIRG) + } + + Method (_CRS,0,Serialized){ + Name(BUF0,ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And(PIRG, 0x80)) { + Store(Zero, Local0) + } Else { + Store(One,Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0,And(PIRG,0x0F),IRQW) + Return (BUF0) + } // End of _CRS method + + Name (_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + FindSetRightBit(IRQW,Local0) // Set IRQ + If (LNotEqual (IRQW,Zero)) { + And (Local0, 0x7F,Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80,Local0) + } + Store (Local0, PIRG) + } // End of _SRS Method +} + +Device(LNKH) { // PCI IRQ link H + Name (_HID,EISAID("PNP0C0F")) + + //Name(_UID, 8) + + Method (_STA,0,Serialized) { + If (And(PIRH, 0x80)) { + Return(0x9) + } Else { + Return(0xB) + } // Don't display + } + + Method (_DIS,0,NotSerialized) { + Or(PIRH, 0x80,PIRH) + } + + Method (_CRS,0,Serialized) { + Name(BUF0, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (PIRH, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One,Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0,And(PIRH,0x0F),IRQW) + Return (BUF0) + } // End of _CRS method + + Name(_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + FindSetRightBit (IRQW,Local0)// Set IRQ + If (LNotEqual (IRQW,Zero)) { + And (Local0, 0x7F,Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80,Local0) + } + Store (Local0, PIRH) + } +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHp.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHp.asi new file mode 100644 index 0000000000..3f23c5bd82 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHp.asi @@ -0,0 +1,650 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + // + // BIOS parameter + // The address will be fixed dynamically during boot. + // Will be updated by ACPI platform driver as "FIX8" + // + OperationRegion (MCTL, SystemMemory, 0x38584946, 0x04) + Field (MCTL, ByteAcc, NoLock, Preserve) { + , 3, + HGPE, 1, + , 7, + , 8, + , 8 + } + +// +// No longer needed, See PPA4 +// +// OperationRegion (PSTS, PCI_Config, 0xB0, 0x04) +// Field (PSTS, ByteAcc, NoLock, Preserve) { +// , 16, +// PMES, 1, // PME Status bit 16 +// PMEP, 1, //PME Pending bit 17 +// , 14 +// } + + + Method (_INI, 0, NotSerialized) { + Store (0x01, HGPE) //enable GPE message generation for ACPI hotplug support + } + + Name(_HPP, Package(){0x08, 0x40, 1, 0}) + + // + // begin hotplug code + // + Name(SHPC, 0x40) // Slot Hot-plug Capable + + Name(SPDS, 0x040) // Slot Presence Detect State + + Name(MRLS, 0x0) // MRL Closed, Standby Power to slot is on + Name(CCOM, 0x010) // Command Complete + Name(SPDC, 0x08) // Slot Presence Detect Changes + Name(MRLC, 0x04) // Slot MRL Changed + Name(SPFD, 0x02) // Slot Power Fault Detected + Name(SABP, 0x01) // Slot Attention Button Pressed + + Name(SPOF, 0x10) // Slot Power Off + Name(SPON, 0x0F) // Slot Power On Mask + + Name(ALMK, 0x1C) // Slot Atten. LED Mask + Name(ALON, 0x01) // Slot Atten. LED On + Name(ALBL, 0x02) // Slot Atten LED Blink + Name(ALOF, 0x03) // Slot Atten LED Off + + Name(PLMK, 0x13) // Slot Pwr. LED Mask + Name(PLON, 0x04) // Slot Pwr. LED On + Name(PLBL, 0x08) // Slot Pwr. LED Blink + Name(PLOF, 0x0C) // Slot Pwr. LED Off + + //;************************************* + //; Bit 3 = Presence Detect Event + //; Bit 2 = MRL Sensor Event + //; Bit 1 = PWR Fault Event + //; Bit 0 = Attention Button Event + //;************************************* + Name(HPEV, 0xF) // Possible interrupt events (all) + + //;************************************************************************; + //; + //; PCIe Link Control Register A0-A1h + //; + //; Bit - 4 - Link disable. + //; + //;************************************************************************; +// +// No longer needed, see PPA4 +// +// OperationRegion(PPA0, PCI_Config, 0xA0, 0x02) +// Field(PPA0,ByteAcc,NoLock,Preserve) { +// ,4, +// LDIS,1, // Link Disable bit4. +// ,11, +// } + + //;************************************************************************; + //; + //; PCIe Slot Capabilities Register A4-A7h + //; Bit - 31-5 - Not used + //; Bit - 4 - Power Indicator Present. + //; Bit - 3 - Attention Indicator Present. + //; Bit - 2 - MRL Sensor Present. + //; Bit - 1 - Power Controller Present. + //; Bit - 0 - Attention Button Present. + //; + //; PCIe Slot control Register A8-A9h + //; + //; Bit - 10 - PWR Control Disable + //; Bit - 9:8 - Attn Indicator + //; Bit - 7:6 - PWR Indicator + //; Bit - 5 - Hot-Plug Interrupt Event Enable + //; Bit - 4 - Command Complete Interrupt enable + //; Bit - 3 - Presence Detect Changed Interrupt enable + //; Bit - 2 - MRL Sensor Changed Interrupt enable + //; Bit - 1 - PwrFault Detect Interrupt enable + //; Bit - 0 - Attention Button Pressed Interrupt Enable + //; + //; PCIe Slot Status Registers AA-ADh + //; + //; Bit - 6 - Presence Detect State. + //; Bit - 5 - MRL Sensor State. + //; Bit - 4 - Command Completed. + //; + //; RWC Status Bits + //; + //; Bit - 3 - Presence Detect Changed. + //; Bit - 2 - MRL Sensor Changed. + //; Bit - 1 - Power Fault Detected. + //; Bit - 0 - Attention Button Pressed. + //;************************************************************************; + OperationRegion(PPA4, PCI_Config, 0x00, 0x100) + Field(PPA4,ByteAcc,NoLock,Preserve) { + Offset (0xA0), // from PPA0 OpRegion + ,4, + LDIS,1, // Link Disable bit4. + ,11, + Offset(0xA4), // A4-A7h PCI Slot Capabilities Register + ATBP,1, // Attention Button Present + ,1, // Skip Power Controller Present + MRSP,1, // MRL Sensor Present + ATIP,1, // Attention Indicator Present + PWIP,1, // Power Indicator Present + ,14, + PSNM,13, // Physical Slot Number + Offset(0xA8), // PCIE Slot Control Register + ABIE,1, // Attention Button Pressed Interrupt Enable + PFIE,1, // Power Fault Detected Interrupt Enable + MSIE,1, // MRL Sensor Changed Interrupt Enable + PDIE,1, // Presence Detect Changed Interrupt Enable. + CCIE,1, // Command Complete Interrupt Enable. + HPIE,1, // Hot-plug Interrupt Enable. + SCTL,5, // Attn/Power indicator and Power controller. + ,5, // reserved + Offset(0xAA), // PCIE Slot Status Register + SSTS,7, // The status bits in Slot Status Reg + ,1, + Offset (0xB0), // from PSTS OpRegion + , 16, + PMES, 1, // PME Status bit 16 + PMEP, 1, // PME Pending bit 17 + , 14 + } + + // + // These Methods replace the bit field definitions in PPA8 + // that were bit fields within SCTL + // + Method (ATID, 0) { + Return (And (SCTL, 0x03)) + } + + Method (PWID, 0) { + Return (ShiftRight (And (SCTL, 0x0C), 2)) + } + + Method (PWCC, 0) { + Return (ShiftRight (And (SCTL, 0x10), 4)) + } + + // + // These methods replace the bit fields definitions in PPA8 + // that were bit fields within SSTS + // + Method (ABPS, 1) { + If (LEqual (Arg0, 1)) { + Or (SSTS, 0x01, SSTS) + } + Return (And (SSTS, 0x01)) + } + + Method (PFDS, 1) { + If (LEqual (Arg0, 1)) { + Or (SSTS, 0x02, SSTS) + } + Return (ShiftRight (And (SSTS, 0x02), 1)) + } + + Method (MSCS, 1) { + If (LEqual (Arg0, 1)) { + Or (SSTS, 0x04, SSTS) + } + Return (ShiftRight (And (SSTS, 0x04), 2)) + } + + Method (PDCS, 1) { + If (LEqual (Arg0, 1)) { + Or (SSTS, 0x08, SSTS) + } + Return (ShiftRight (And (SSTS, 0x08), 3)) + } + + Method (CMCS, 1) { + If (LEqual (Arg0, 1)) { + Or (SSTS, 0x10, SSTS) + } + Return (ShiftRight (And (SSTS, 0x10), 4)) + } + + Method (MSSC, 1) { + If (LEqual (Arg0, 1)) { + Or (SSTS, 0x20, SSTS) + } + Return (ShiftRight (And (SSTS, 0x20), 5)) + } + + Method (PRDS, 1) { + If (LEqual (Arg0, 1)) { + Or (SSTS, 0x40, SSTS) + } + Return (ShiftRight (And (SSTS, 0x40), 6)) + } + + +// OperationRegion(PPA8, PCI_Config, 0x00, 0x0ff) +// Field(PPA8,ByteAcc,NoLock,Preserve) { +// Offset(0xA8), // PCIE Slot Control Register +// ,6, +// ATID,2, // Attention Indicator Control. +// PWID,2, // Power Indicator Control. +// PWCC,1, // Power Controller Control. +// ,5, +// Offset(0xAA), // RWC status +// ABPS,1, // Attention Button Pressed Status (RWC) +// PFDS,1, // Power Fault Detect Status (RWC) +// MSCS,1, // MRL Sensor Changed Status +// PDCS,1, // Presence Detect Changed Status +// CMCS,1, // Command Complete Status +// MSSC,1, // MRL Sensor State +// PRDS,1, // Presence Detect State +// ,1, +// } + + //;************************************************************************; + //; This OSHP (Operating System Hot Plug) method is provided for each HPC + //; which is controlled by ACPI. This method disables ACPI access to the + //; HPC and restores the normal System Interrupt and Wakeup Signal + //; connection. + //;************************************************************************; + Method(OSHP) { // OS call to unhook Legacy ASL PCI-Express HP code. + Store(SSTS, SSTS) // Clear any status + Store(0x0, HGPE) // Disable GPE generation + } + + //;************************************************************************; + //; Hot Plug Controller Command Method + //; + //; Input: Arg0 - Command to issue + //; + //;************************************************************************; + Method(HPCC,1) { + Store(SCTL, Local0) // get current command state + Store(0, Local1) // reset the timeout value + If(LNotEqual(Arg0, Local0)) { // see if state is different + Store(Arg0, SCTL) // Update the Slot Control + While(LAnd (LNot(CMCS(0)), LNotEqual(100, Local1))) { // spin while CMD complete bit is not set, + // check for timeout to avoid dead loop + Store(0xFB, IO80) + Sleep(2) // allow processor time slice + Add(Local1, 2, Local1) + } + CMCS(1) // Clear the command complete status + } + } + + //;************************************************************************; + //; Attention Indicator Command + //; + //; Input: Arg0 - Command to issue + //; 1 = ON + //; 2 = Blink + //; 3 = OFF + //;************************************************************************; + Method(ATCM,1) { + Store(SCTL, Local0) // Get Slot Control + And(Local0, ALMK, Local0) // Mask the Attention Indicator Bits + If(LEqual(Arg0, 0x1)){ // Attenion indicator "ON?" + Or(Local0, ALON, Local0) // Set the Attention Indicator to "ON" + } + If(LEqual(Arg0, 0x2)){ // Attenion indicator "BLINK?" + Or(Local0, ALBL, Local0) // Set the Attention Indicator to "BLINK" + } + If(LEqual(Arg0, 0x3)){ // Attenion indicator "OFF?" + Or(Local0, ALOF, Local0) // Set the Attention Indicator to "OFF" + } + HPCC(Local0) + } + + //;************************************************************************; + //; Power Indicator Command + //; + //; Input: Arg0 - Command to issue + //; 1 = ON + //; 2 = Blink + //; 3 = OFF + //;************************************************************************; + Method(PWCM,1){ + Store(SCTL, Local0) // Get Slot Control + And(Local0, PLMK, Local0) // Mask the Power Indicator Bits + If(LEqual(Arg0, 0x1)){ // Power indicator "ON?" + Or(Local0, PLON, Local0) // Set the Power Indicator to "ON" + } + If(LEqual(Arg0, 0x2)){ // Power indicator "BLINK?" + Or(Local0, PLBL, Local0) // Set the Power Indicator to "BLINK" + } + If(LEqual(Arg0, 0x3)){ // Power indicator "OFF?" + Or(Local0, PLOF, Local0) // Set the Power Indicator to "OFF" + } + HPCC(Local0) + } + + //;************************************************************************; + //; Power Slot Command + //; + //; Input: Arg0 - Command to issue + //; 1 = Slot Power ON + //; 2 = Slot Power Off + //;************************************************************************; + Method(PWSL,1){ + Store(SCTL, Local0) // Get Slot Control + If(Arg0){ // Power Slot "ON" Arg0 = 1 + And(Local0, SPON, Local0) // Turns the Power "ON" + } Else { // Power Slot "OFF" + Or(Local0, SPOF, Local0) // Turns the Power "OFF" + } + HPCC(Local0) + } + + //;************************************************************************; + //; _OST Methods to indicate that the device Eject/insert request is + //; pending, OS could not complete it + //; + //; Input: Arg0 - Value used in Notify to OS + //; 0x00 - card insert + //; 0x03 - card eject + //; Arg1 - status of Notify + //; 0 - success + //; 0x80 - Ejection not supported by OSPM + //; 0x81 - Device in use + //; 0x82 - Device Busy + //; 0x84 - Ejection in progress-pending + //;************************************************************************; + Method(_OST,3,Serialized) { + Switch(And(Arg0,0xFF)) { // Mask to retain low byte + Case(0x03) { // Ejection Request + Switch(ToInteger(Arg1)) { + Case(Package() {0x80, 0x81, 0x82, 0x83}) { + // + // Ejection Failure for some reason + // + If (Lnot(PWCC())) { // if slot is powered + PWCM(0x1) // Set PowerIndicator to ON + Store(0x1,ABIE) // Set AttnBtn Interrupt ON + } + } + } + } + } + } // End _OST + + //;************************************************************************; + //; Eject Control Methods to indicate that the device is hot-ejectable and + //; should "eject" the device. + //; + //; + //;************************************************************************; + Method(EJ0L){ + Store(0xFF, IO80) + Store(SCTL, Local0) // Get IIO Port Control state + if( LNot( LEqual( ATID(), 1))) { // Check if Attention LED is not solid "ON" + And(Local0, ALMK, Local0) // Mask the Attention Indicator Bits + Or(Local0, ALBL, Local0) // Set the Attention Indicator to blink + } + HPCC(Local0) // issue command + + Store(SCTL, Local0) // Get IIO Port Control state + Or(Local0, SPOF, Local0) // Set the Power Controller Control to Power Off + HPCC(Local0) + + Store(SCTL, Local0) // Get IIO Port Control state + Or(Local0, PLOF, Local0) // Set the Power Indicator to Off. + HPCC(Local0) + + Store(SCTL, Local0) // Get IIO Port Control state + Or(Local0, ALOF, Local0) // Set the Attntion LED to Off. + HPCC(Local0) + + } // End of EJ0L + + //;************************************************************************; + //; PM_PME Wake Handler for All Slots + //; + //; Input: Arg0 - Slot Numnber + //; + //;************************************************************************; + Method(PMEH,1){ // Handler for PCI-E PM_PME Wake Event/Interupt (GPI xxh) + If(And(HPEV, SSTS)){ // Check for Hot-Plug Events + If(ABPS(0)) { + Store (Arg0, IO80) // Send slot number to Port 80 + ABPS(1) // Clear the interrupt status + Sleep(200) // delay 200ms + } + } + Return (0xff) // Indicate that this controller did not interrupt + } // End of Method PMEH + + //;************************************************************************; + //; Hot-Plug Handler for All Slots. + //; + //; Input: Arg0 - Slot Number + //; + //;************************************************************************; + Method(HPEH,1){ // Handler for PCI-E Hot-Plug Event/Interupt (GPI xxh) + Store(0xFE, IO80) + Sleep(100) + Store(0,CCIE) // Disable command interrupt + If(And(HPEV, SSTS)){ // Check for Hot-Plug Events + Store(0xFD, IO80) + Sleep(10) + Store (Arg0, IO80) // Send slot number to Port 80 + Sleep(10) + Store(PPXH(), Local0) // Call Hot plug Interrupt Handler + Return(Local0) // Return PPXH information + } + Else{ + Return (0xff) // Indicate that this controller did not interrupt + } + Store(0xFC, IO80) + Sleep(10) + } // End of Method HPEH + + //;************************************************************************; + //; Interrut Event Handler + //; + //; + //;************************************************************************; + Method(PPXH){ // Hot plug Interrupt Handler + // + // Check for the Atention Button Press, Slot Empty/Presence, Power Controller Control. + // + Sleep(200) // HW Workaround for AttentionButton Status to stabilise + If(ABPS(0)) { // Check if Attention Button Pressed + If(LNot(PRDS(0))) { // See if nothing installed (no card in slot) + Store(0x1, LDIS) // Disable the Link associated with PCI-E port + PWSL(0x0) // make sure Power is Off + PWCM(0x3) // Set Power Indicator to "OFF" + // + // Check for MRL here and set attn indicator accordingly + // + If(LEqual(MSSC(0),MRLS)) { // Standby power is on - MRL closed + ATCM(0x2) // Set Attention Indicator to "BLINK" + } else { // Standby power is off - MRL open + ATCM(0x3) // set attention indicator "OFF" + } + Store(0x0, ABIE) // set Attention Button Interrupt to disable + ABPS(1) // Clear the interrupt status + Sleep(200) // delay 200ms + Return(0xff) // Attn Button pressed without card in slot. Do nothing + } + // + // Card is present in slot so.... + // + Store(0x0, ABIE) // set Attention Button Interrupt to disable + // Attn Btn Interrupt has to be enabled only after an insert oprn + ABPS(1) // Clear the interrupt status + Sleep(200) // delay 200ms + // + // Check for MRL here - only if SPWR is OFF blink AttnInd and retun 0xff + // + //If(LNot(LEqual(MSSC()),MRLS))) { // Standby power is off + // PWSL(0x0) // make sure Power is Off + // PWCM(0x3) // Set Power Indicator to "OFF" + // ATCM(0x2) // Set Attention Indicator to "BLINK" + // Return(0xff) // Attn Button pressed with card in slot, but MRL open. Do nothing + //} + //Card Present, if StandbyPwr is ON proceed as below with Eject Sequence + If(PWCC()) { // Slot not Powered + PWCM(0x3) // Set Power Indicator to "OFF" + ATCM(0x2) // Set Attention Indicator to "BLINK" + Return(0xff) // Attn Button pressed with card in slot, MRL closed, Slot not powered. Do nothing + } Else { // See if Slot is already Powered + PWCM(0x2) // Set power Indicator to BLINK + Sleep(600) // Wait 100ms + Store(600, Local0) // set 5 second accumulator to 0 + ABPS(1) // Clear the interrupt status + Sleep(200) // delay 200ms + While(LNot(ABPS(0))) { // check for someone pressing Attention + Sleep(200) // Wait 200ms + Add(Local0, 200, Local0) + If(LEqual(5000, Local0)) { // heck if 5sec has passed without pressing attnetion btn + ABPS(1) // Clear the interrupt status + Sleep(200) // delay 200ms + Return (0x3) // continue with Eject request + } + } + PWCM(0x1) // Set power Indicator baCK "ON" + ABPS(1) // Clear the Attention status + Sleep(200) // delay 200ms + Store(0x1, ABIE) // set Attention Button Interrupt to enable + Return (0xff) // do nothing and abort + } + } // End if for the Attention Button Hot Plug Interrupt. + + If(PFDS(0)) { // Check if Power Fault Detected + PFDS(1) // Clear the Power Fault Status + PWSL(0x0) // set Power Off + PWCM(0x3) // set power indicator to OFF + ATCM(0x1) // set attention indicator "ON" + Store(0x1, LDIS) // Disable the Link associated with PCI-E port + Return(0x03) // Eject request. + } // End if for the Power Fault Interrupt. + + If(MSCS(0)) { // Check interrupt caused by the MRL Sensor + MSCS(1) // Clear the MRL Status + If(LEqual(MSSC(0),MRLS)) { // Standby power is on - MRL closed + If(PRDS(0)) { // Card is Present + + ATCM(0x3) // Set Attention Indicator to off + PWCM(0x2) // Set Power Indicator to Blink + Sleep(600) // Wait 100ms + Store(600, Local0) // set 5 second accumulator to 0 + ABPS(1) // Clear the interrupt status + While(LNot(ABPS(0))) { // check for someone pressing Attention + Sleep(200) // Wait 200ms + Add(Local0, 200, Local0) + If(LEqual(5000, Local0)) { // Check if 5 sec elapsed + Store(0x1, ABIE) // Enable Attention button interrupt + ATCM(0x3) // set attention indicator "OFF" + Store(0x0, LDIS) // Enable the Link associated with PCI-E port + PWSL(0x1) // Power the Slot + Sleep(500) // Wait for .5 Sec for the Power to Stabilize. + // Check for the Power Fault Detection + If(LNot(PFDS(0))) { // No Power Fault + PWCM(0x1) // Set Power Indicator to "ON" + // Or(LVLS, 0x000010000, LVLS) // Enable the Device 4 Slot Clock (GPIO16) + // Notify the OS to load the Driver for the card + Store(0x00, Local1) + Store(0x1, ABIE) // Enable Attention button interrupt + } Else { // Power Fault present + PWSL(0x0) // set Slot Power Off + PWCM(0x3) // set power indicator to OFF + ATCM(0x1) // set attention indicator "ON" + Store(0x1, LDIS) // Disable the Link associated with PCI-E port + // And (LVLS, 0x0FFFEFFFF, LVLS) // Disable the Device 4 Slot Clock (GPIO16) + Store(0x03, Local1) // Eject request. + } // End if for the Slot Power Fault + ABPS(1) // Clear the Attention status + Sleep(200) // delay 200ms + Return(Local1) + } + } + // + // someone pressed Attention Button + // + ABPS(1) // Clear the Attention status + Sleep(200) // delay 200ms + PWSL(0x0) // Set Slot Power off + PWCM(0x3) // Set Power Indicator back to "OFF" + ATCM(02) // Set Attention Indicator to "BLINK" + Store(0x1, LDIS) // Disable the Link associated with PCI-E port + Return(0xff) // leave it off + // End of Insert sequence + } + //MRL is closed, Card is not present + PWSL(0x0) // Set Slot Power off + PWCM(0x3) // Set Power Indicator back to "OFF" + ATCM(02) // Set Attention Indicator to "BLINK" + Store(0x1, LDIS) // Disable the Link associated with PCI-E port + Return(0xff) // leave it off + } Else { // MRL is open i.e Stdby power is turned off + If(PRDS(0)) { //card present MRL switched off + ATCM(0x2) // Set Attention Indicator to "BLINK" + If(Lnot(PWCC())) { // If slot is powered + // This event is not supported and someone has opened the MRL and dumped the power + // on the slot with possible pending transactions. This could hose the OS. + // Try to Notify the OS to unload the drivers. + PWSL(0x0) // Set Slot Power off + PWCM(0x3) // Set Power Indicator back to "OFF" + Store(0x1, LDIS) // Disable the Link associated with PCI-E port + Return(0x03) // Eject request. + } Else { // Slot not powered, MRL is opened, card still in slot - Eject not fully complete + Return(0xFF) + } + } + //no card present and Stdby power switched off, turn AI off + ATCM(0x3) // Set Attention Indicator to "OFF" + Return(0xff) // leave it off + } // End of MRL switch open/close state + } // End of MRL Sensor State Change + + If(PDCS(0)) { // Check if Presence Detect Changed Status + PDCS(1) // Clear the Presence Detect Changed Status + If(LNot(PRDS(0))) { // Slot is Empty + PWSL(0x0) // Set Slot Power "OFF" + PWCM(0x3) // set power indicator to "OFF" + If(LEqual(MSSC(0),MRLS)) { // If Standby power is on + ATCM(0x2) // Set Attention Indicator to "Blink" + } else { + ATCM(0x3) // Set Attention Indicator to "OFF" + } + Store(0x1, LDIS) // Disable the Link associated with PCI-E port + Return(0xFF) // Do nothing + } Else { // Slot Card is inserted + // Irrespective of MRL state, do the following + Store(0x0, LDIS) // Enable the Link associated with PCI-E port + PWSL(0x1) // Set Slot Power ON + Sleep(500) // Wait for .5 Sec for the Power to Stabilize. + If(LNot(PFDS(0))) { // No Power Fault + PWCM(0x1) // Set Power Indicator to "ON" + Store(0x00, Local1) + Store(0x1, ABIE) // Enable Attention button interrupt + ATCM(0x3) // Set Attention Indicator to "OFF" + } Else { // Power Fault present + PWSL(0x0) // set Slot Power Off + PWCM(0x3) // set power indicator to OFF + ATCM(0x1) // set attention indicator "ON" + Store(0x1, LDIS) // Disable the Link associated with PCI-E port + Store(0x03, Local1) // Eject request. + } // End if for the Slot Power Fault + ABPS(1) // Clear the Attention status + Sleep(200) // delay 200ms + Return(Local1) + } + } // End if for the Presence Detect Changed Hot Plug Interrupt. + Return(0xff) // should not get here, but do device check if it does. + } // End of method PP5H + // + // End of hotplug code + // diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHpDev.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHpDev.asi new file mode 100644 index 0000000000..d9a4565519 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHpDev.asi @@ -0,0 +1,20 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Method(SNUM, 0, Serialized) { + Store(PSNM, Local0) + Return(Local0) + } + + Method(_SUN, 0) { Return(SNUM) } // Slot User Number + Method(_EJ0, 1) { EJ0L() } // Remove all power from the slot diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieNonHpDev.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieNonHpDev.asi new file mode 100644 index 0000000000..4f90be3373 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieNonHpDev.asi @@ -0,0 +1,22 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Method(SNUM, 0, Serialized) { + Store(PSNM, Local0) + Return(Local0) + } + + Method(_SUN, 0) { + Return(SNUM) + } // Slot User Number + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieSeg.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieSeg.asi new file mode 100644 index 0000000000..781d764bb8 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieSeg.asi @@ -0,0 +1,361 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "MaxSocket.h" + + Scope(\) { + + // + // \SG00, SG01,... SG07 are defined to contain Segment # for Segment/socket 0, 1, .... + // + // Create _SEG for each segment/socket + // + + // + // Debug method for use under BITS + // Example: Set SG01 to 5 SSEG(1,5) + // + Method(SSEG, 2) { + If (LEqual(Arg0, 0) ) { Store (Arg1, SG00) } + If (LEqual(Arg0, 1) ) { Store (Arg1, SG01) } + If (LEqual(Arg0, 2) ) { Store (Arg1, SG02) } + If (LEqual(Arg0, 3) ) { Store (Arg1, SG03) } + } + + +// ------------------------------------------------------ +// Socket 0 PC00 - PC05 share the same segment number SG00 +// ------------------------------------------------------ + + Scope(\_SB.PC00) { + Method (_SEG, 0, NotSerialized) { + return (SG00) + } + } + + Scope(\_SB.PC01) { + Method (_SEG, 0, NotSerialized) { + return (SG00) + } + } + + Scope(\_SB.PC02) { + Method (_SEG, 0, NotSerialized) { + return (SG00) + } + } + + Scope(\_SB.PC03) { + Method (_SEG, 0, NotSerialized) { + return (SG00) + } + } + + Scope(\_SB.PC04) { + Method (_SEG, 0, NotSerialized) { + return (SG00) + } + } + + Scope(\_SB.PC05) { + Method (_SEG, 0, NotSerialized) { + return (SG00) + } + } + +// ------------------------------------------------------ +// Socket 1 PC06 - PC11 share the same segment number SG01 +// ------------------------------------------------------ + + Scope(\_SB.PC06) { + Method (_SEG, 0, NotSerialized) { + return (SG01) + } + } + + Scope(\_SB.PC07) { + Method (_SEG, 0, NotSerialized) { + return (SG01) + } + } + + Scope(\_SB.PC08) { + Method (_SEG, 0, NotSerialized) { + return (SG01) + } + } + + Scope(\_SB.PC09) { + Method (_SEG, 0, NotSerialized) { + return (SG01) + } + } + + Scope(\_SB.PC10) { + Method (_SEG, 0, NotSerialized) { + return (SG01) + } + } + + Scope(\_SB.PC11) { + Method (_SEG, 0, NotSerialized) { + return (SG01) + } + } + +// ------------------------------------------------------ +// Socket 2 PC12 - PC17 share the same segment number SG02 +// ------------------------------------------------------ + + Scope(\_SB.PC12) { + Method (_SEG, 0, NotSerialized) { + return (SG02) + } + } + + Scope(\_SB.PC13) { + Method (_SEG, 0, NotSerialized) { + return (SG02) + } + } + + Scope(\_SB.PC14) { + Method (_SEG, 0, NotSerialized) { + return (SG02) + } + } + + Scope(\_SB.PC15) { + Method (_SEG, 0, NotSerialized) { + return (SG02) + } + } + + Scope(\_SB.PC16) { + Method (_SEG, 0, NotSerialized) { + return (SG02) + } + } + + Scope(\_SB.PC17) { + Method (_SEG, 0, NotSerialized) { + return (SG02) + } + } + + +// ------------------------------------------------------ +// Socket 3 PC18 - PC23 share the same segment number SG03 +// ------------------------------------------------------ + + Scope(\_SB.PC18) { + Method (_SEG, 0, NotSerialized) { + return (SG03) + } + } + + Scope(\_SB.PC19) { + Method (_SEG, 0, NotSerialized) { + return (SG03) + } + } + + Scope(\_SB.PC20) { + Method (_SEG, 0, NotSerialized) { + return (SG03) + } + } + + Scope(\_SB.PC21) { + Method (_SEG, 0, NotSerialized) { + return (SG03) + } + } + + Scope(\_SB.PC22) { + Method (_SEG, 0, NotSerialized) { + return (SG03) + } + } + + Scope(\_SB.PC23) { + Method (_SEG, 0, NotSerialized) { + return (SG03) + } + } + +#if MAX_SOCKET > 4 + +// ------------------------------------------------------ +// Socket 4 PC24 - PC29 share the same segment number SG03 +// ------------------------------------------------------ + + Scope(\_SB.PC24) { + Method (_SEG, 0, NotSerialized) { + return (SG04) + } + } + + Scope(\_SB.PC25) { + Method (_SEG, 0, NotSerialized) { + return (SG04) + } + } + + Scope(\_SB.PC26) { + Method (_SEG, 0, NotSerialized) { + return (SG04) + } + } + + Scope(\_SB.PC27) { + Method (_SEG, 0, NotSerialized) { + return (SG04) + } + } + + Scope(\_SB.PC28) { + Method (_SEG, 0, NotSerialized) { + return (SG04) + } + } + + Scope(\_SB.PC29) { + Method (_SEG, 0, NotSerialized) { + return (SG04) + } + } + +// ------------------------------------------------------ +// Socket 5 PC30 - PC35 share the same segment number SG03 +// ------------------------------------------------------ + + Scope(\_SB.PC30) { + Method (_SEG, 0, NotSerialized) { + return (SG05) + } + } + + Scope(\_SB.PC31) { + Method (_SEG, 0, NotSerialized) { + return (SG05) + } + } + + Scope(\_SB.PC32) { + Method (_SEG, 0, NotSerialized) { + return (SG05) + } + } + + Scope(\_SB.PC33) { + Method (_SEG, 0, NotSerialized) { + return (SG05) + } + } + + Scope(\_SB.PC34) { + Method (_SEG, 0, NotSerialized) { + return (SG05) + } + } + + Scope(\_SB.PC35) { + Method (_SEG, 0, NotSerialized) { + return (SG05) + } + } + +// ------------------------------------------------------ +// Socket 6 PC36 - PC41 share the same segment number SG03 +// ------------------------------------------------------ + + Scope(\_SB.PC36) { + Method (_SEG, 0, NotSerialized) { + return (SG06) + } + } + + Scope(\_SB.PC37) { + Method (_SEG, 0, NotSerialized) { + return (SG06) + } + } + + Scope(\_SB.PC38) { + Method (_SEG, 0, NotSerialized) { + return (SG06) + } + } + + Scope(\_SB.PC39) { + Method (_SEG, 0, NotSerialized) { + return (SG06) + } + } + + Scope(\_SB.PC40) { + Method (_SEG, 0, NotSerialized) { + return (SG06) + } + } + + Scope(\_SB.PC41) { + Method (_SEG, 0, NotSerialized) { + return (SG06) + } + } + +// ------------------------------------------------------ +// Socket 7 PC42 - PC47 share the same segment number SG03 +// ------------------------------------------------------ + + Scope(\_SB.PC42) { + Method (_SEG, 0, NotSerialized) { + return (SG07) + } + } + + Scope(\_SB.PC43) { + Method (_SEG, 0, NotSerialized) { + return (SG07) + } + } + + Scope(\_SB.PC44) { + Method (_SEG, 0, NotSerialized) { + return (SG07) + } + } + + Scope(\_SB.PC45) { + Method (_SEG, 0, NotSerialized) { + return (SG07) + } + } + + Scope(\_SB.PC46) { + Method (_SEG, 0, NotSerialized) { + return (SG07) + } + } + + Scope(\_SB.PC47) { + Method (_SEG, 0, NotSerialized) { + return (SG07) + } + } +#endif + +} // End Scope(\) + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl new file mode 100644 index 0000000000..69ad6e0382 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl @@ -0,0 +1,85 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + +// Interrupt specific registers +include("Itss.asl") +// +// Original file line: 163 +// + +Method(ADBG,1,Serialized) +{ + Return(0) +} + +// +// Original file line: 1460 +// +Scope (\) +{ + // + // Global Name, returns current Interrupt controller mode; + // updated from _PIC control method + // + + // + // Procedure: GPRW + // + // Description: Generic Wake up Control Method ("Big brother") + // to detect the Max Sleep State available in ASL Name scope + // and Return the Package compatible with _PRW format. + // Input: Arg0 = bit offset within GPE register space device event will be triggered to. + // Arg1 = Max Sleep state, device can resume the System from. + // If Arg1 = 0, Update Arg1 with Max _Sx state enabled in the System. + // Output: _PRW package + // + Name(PRWP, Package(){Zero, Zero}) // _PRW Package + + Method(GPRW, 2) + { + Store(Arg0, Index(PRWP, 0)) // copy GPE# + // + // SS1-SS4 - enabled in BIOS Setup Sleep states + // + Store(ShiftLeft(SS1,1),Local0) // S1 ? + Or(Local0,ShiftLeft(SS2,2),Local0) // S2 ? + Or(Local0,ShiftLeft(SS3,3),Local0) // S3 ? + Or(Local0,ShiftLeft(SS4,4),Local0) // S4 ? + // + // Local0 has a bit mask of enabled Sx(1 based) + // bit mask of enabled in BIOS Setup Sleep states(1 based) + // + If(And(ShiftLeft(1, Arg1), Local0)) + { + // + // Requested wake up value (Arg1) is present in Sx list of available Sleep states + // + Store(Arg1, Index(PRWP, 1)) // copy Sx# + } + Else + { + // + // Not available -> match Wake up value to the higher Sx state + // + ShiftRight(Local0, 1, Local0) + // If(LOr(LEqual(OSFL, 1), LEqual(OSFL, 2))) { // ??? Win9x + // FindSetLeftBit(Local0, Index(PRWP,1)) // Arg1 == Max Sx + // } Else { // ??? Win2k / XP + FindSetLeftBit(Local0, Index(PRWP,1)) // Arg1 == Min Sx + // } + } + + Return(PRWP) + } +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGpe.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGpe.asi new file mode 100644 index 0000000000..ec7c3e3315 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGpe.asi @@ -0,0 +1,84 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// General Purpose Event +#include "MaxSocket.h" + +Scope (\_GPE) { + + // + // ME HECI2 SCI handler + // Note: This SCI from HECI2 is routed to ICH9 over the DMI and it + // sets the DMISCI status bit in TCO block. From there it is routed + // to bit6 GPE0 status register. + // + OperationRegion (TCOS, SystemIO, 0x464, 2) // ICH_ACPI_BASE_ADDRESS + TCO_BASE + R_TCO1_STS + Field (TCOS, ByteAcc, NoLock, WriteAsZeros) { + Offset (0x1), + , 1, + DSCI, 1, + } + + Method(NTFI, 2){ + If(And(Arg0, 0x01)){ + Notify(\_SB.PC06, Arg1) + Notify(\_SB.PC07, Arg1) + Notify(\_SB.PC08, Arg1) + Notify(\_SB.PC09, Arg1) + Notify(\_SB.PC10, Arg1) + Notify(\_SB.PC11, Arg1) + } + If(And(Arg0, 0x02)){ + Notify(\_SB.PC12, Arg1) + Notify(\_SB.PC13, Arg1) + Notify(\_SB.PC14, Arg1) + Notify(\_SB.PC15, Arg1) + Notify(\_SB.PC16, Arg1) + Notify(\_SB.PC17, Arg1) + } + If(And(Arg0, 0x04)){ + Notify(\_SB.PC18, Arg1) + Notify(\_SB.PC19, Arg1) + Notify(\_SB.PC20, Arg1) + Notify(\_SB.PC21, Arg1) + Notify(\_SB.PC22, Arg1) + Notify(\_SB.PC23, Arg1) + } + } //End Method NTFI + + // Tell OS to run thru the new status of this device (Software SCI generated from SMM for all Hot plug events) + Method (_L62, 0x0, NotSerialized) { + if(LEqual(SCI0, 3)) { // Device ejection (Invoked with _EJ0 method called) + Store (0, SCI0) + } else { // Device check (OS can still reject online request based on resources and capability) + NTFI (IIOP, 0) + Store (0, MEBC) + Store (0, CPHP) + Store (0, IIOP) + } + Store (0, SGPC) + Store (1, SGPS) + + } + + // PME supported for Slots, use GPE 9 for PME + // Hot plug on all slots for now, change later. + // Slot numbers on silk screen might be different than the port number, currently use port numbers. + // + // IIO PCI_E Slot Hotplug GPE Event + // + Method (_L61, 0, NotSerialized) { + #include "IioPcieHotPlugGpeHandler.asl" + }// end of _L01 GPE Method + +}// end of _GPE scope. diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformPciTree_WFP.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformPciTree_WFP.asi new file mode 100644 index 0000000000..28344b9aa2 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformPciTree_WFP.asi @@ -0,0 +1,8076 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + +Scope (\_SB) { + + Name (PR00, Package() { + // [DMI0]: Legacy PCI Express Port 0 on PC00 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [CB0A]: CB3DMA on PC00 + // [CB0E]: CB3DMA on PC00 + Package() { 0x0004FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [CB0B]: CB3DMA on PC00 + // [CB0F]: CB3DMA on PC00 + Package() { 0x0004FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + // [CB0C]: CB3DMA on PC00 + // [CB0G]: CB3DMA on PC00 + Package() { 0x0004FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + // [CB0D]: CB3DMA on PC00 + // [CB0H]: CB3DMA on PC00 + Package() { 0x0004FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [IIM0]: IIOMISC on PC00 + Package() { 0x0005FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0005FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0005FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0005FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [UBX0]: Uncore 0 UBOX Device + Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [DISP]: Display Controller + Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [IHC1]: HECI #1 + // [IHC3]: HECI #3 + Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [IHC2]: HECI #2 + Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + // [IIDR]: IDE-Redirection (IDE-R) + Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + // [IMKT]: Keyboard and Text (KT) Redirection + Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [SAT2]: sSATA Host controller 2 on PCH + Package() { 0x0011FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [XHCI]: xHCI controller 1 on PCH + Package() { 0x0014FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [OTG0]: USB Device Controller (OTG) on PCH + Package() { 0x0014FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + // [TERM]: Thermal Subsystem on PCH + Package() { 0x0014FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + // [CAMR]: Camera IO Host Controller on PCH + Package() { 0x0014FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [HEC1]: HECI #1 on PCH + // [HEC3]: HECI #3 on PCH + Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [HEC2]: HECI #2 on PCH + Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + // [IDER]: ME IDE redirect on PCH + Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + // [MEKT]: MEKT on PCH + Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [SAT1]: SATA controller 1 on PCH + Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [NAN1]: NAND Cycle Router on PCH + Package() { 0x0018FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [RP17]: PCIE PCH Root Port #17 + Package() { 0x001BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [RP18]: PCIE PCH Root Port #18 + Package() { 0x001BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + // [RP19]: PCIE PCH Root Port #19 + Package() { 0x001BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + // [RP20]: PCIE PCH Root Port #20 + Package() { 0x001BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [RP01]: PCIE PCH Root Port #1 + // [RP05]: PCIE PCH Root Port #5 + Package() { 0x001CFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [RP02]: PCIE PCH Root Port #2 + // [RP06]: PCIE PCH Root Port #6 + Package() { 0x001CFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + // [RP03]: PCIE PCH Root Port #3 + // [RP07]: PCIE PCH Root Port #7 + Package() { 0x001CFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + // [RP04]: PCIE PCH Root Port #4 + // [RP08]: PCIE PCH Root Port #8 + Package() { 0x001CFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [RP09]: PCIE PCH Root Port #9 + // [RP13]: PCIE PCH Root Port #13 + Package() { 0x001DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [RP10]: PCIE PCH Root Port #10 + // [RP14]: PCIE PCH Root Port #14 + Package() { 0x001DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + // [RP11]: PCIE PCH Root Port #11 + // [RP15]: PCIE PCH Root Port #15 + Package() { 0x001DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + // [RP12]: PCIE PCH Root Port #12 + // [RP16]: PCIE PCH Root Port #16 + Package() { 0x001DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [UAR0]: UART #0 on PCH + Package() { 0x001EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [UAR1]: UART #1 on PCH + Package() { 0x001EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + // [SPI0]: SPI #0 on PCH + Package() { 0x001EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + // [SPI1]: SPI #1 on PCH + Package() { 0x001EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CAVS]: HD Audio Subsystem Controller on PCH + // [SMBS]: SMBus controller on PCH + // [GBE1]: GbE Controller on PCH + // [NTPK]: Northpeak Controller on PCH + Package() { 0x001FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR00, Package() { + // [DMI0]: Legacy PCI Express Port 0 on PC00 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [CB0A]: CB3DMA on PC00 + // [CB0E]: CB3DMA on PC00 + Package() { 0x0004FFFF, 0, 0, 16 }, + // [CB0B]: CB3DMA on PC00 + // [CB0F]: CB3DMA on PC00 + Package() { 0x0004FFFF, 1, 0, 17 }, + // [CB0C]: CB3DMA on PC00 + // [CB0G]: CB3DMA on PC00 + Package() { 0x0004FFFF, 2, 0, 18 }, + // [CB0D]: CB3DMA on PC00 + // [CB0H]: CB3DMA on PC00 + Package() { 0x0004FFFF, 3, 0, 19 }, + // [IIM0]: IIOMISC on PC00 + Package() { 0x0005FFFF, 0, 0, 16 }, + Package() { 0x0005FFFF, 1, 0, 17 }, + Package() { 0x0005FFFF, 2, 0, 18 }, + Package() { 0x0005FFFF, 3, 0, 19 }, + // [UBX0]: Uncore 0 UBOX Device + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + // [DISP]: Display Controller + Package() { 0x000FFFFF, 0, 0, 16 }, + // [IHC1]: HECI #1 + // [IHC3]: HECI #3 + Package() { 0x0010FFFF, 0, 0, 16 }, + // [IHC2]: HECI #2 + Package() { 0x0010FFFF, 1, 0, 17 }, + // [IIDR]: IDE-Redirection (IDE-R) + Package() { 0x0010FFFF, 2, 0, 18 }, + // [IMKT]: Keyboard and Text (KT) Redirection + Package() { 0x0010FFFF, 3, 0, 19 }, + // [SAT2]: sSATA Host controller 2 on PCH + Package() { 0x0011FFFF, 0, 0, 16 }, + // [XHCI]: xHCI controller 1 on PCH + Package() { 0x0014FFFF, 0, 0, 16 }, + // [OTG0]: USB Device Controller (OTG) on PCH + Package() { 0x0014FFFF, 1, 0, 17 }, + // [TERM]: Thermal Subsystem on PCH + Package() { 0x0014FFFF, 2, 0, 18 }, + // [CAMR]: Camera IO Host Controller on PCH + Package() { 0x0014FFFF, 3, 0, 19 }, + // [HEC1]: HECI #1 on PCH + // [HEC3]: HECI #3 on PCH + Package() { 0x0016FFFF, 0, 0, 16 }, + // [HEC2]: HECI #2 on PCH + Package() { 0x0016FFFF, 1, 0, 17 }, + // [IDER]: ME IDE redirect on PCH + Package() { 0x0016FFFF, 2, 0, 18 }, + // [MEKT]: MEKT on PCH + Package() { 0x0016FFFF, 3, 0, 19 }, + // [SAT1]: SATA controller 1 on PCH + Package() { 0x0017FFFF, 0, 0, 16 }, + // [NAN1]: NAND Cycle Router on PCH + Package() { 0x0018FFFF, 0, 0, 16 }, + // [RP17]: PCIE PCH Root Port #17 + Package() { 0x001BFFFF, 0, 0, 16 }, + // [RP18]: PCIE PCH Root Port #18 + Package() { 0x001BFFFF, 1, 0, 17 }, + // [RP19]: PCIE PCH Root Port #19 + Package() { 0x001BFFFF, 2, 0, 18 }, + // [RP20]: PCIE PCH Root Port #20 + Package() { 0x001BFFFF, 3, 0, 19 }, + // [RP01]: PCIE PCH Root Port #1 + // [RP05]: PCIE PCH Root Port #5 + Package() { 0x001CFFFF, 0, 0, 16 }, + // [RP02]: PCIE PCH Root Port #2 + // [RP06]: PCIE PCH Root Port #6 + Package() { 0x001CFFFF, 1, 0, 17 }, + // [RP03]: PCIE PCH Root Port #3 + // [RP07]: PCIE PCH Root Port #7 + Package() { 0x001CFFFF, 2, 0, 18 }, + // [RP04]: PCIE PCH Root Port #4 + // [RP08]: PCIE PCH Root Port #8 + Package() { 0x001CFFFF, 3, 0, 19 }, + // [RP09]: PCIE PCH Root Port #9 + // [RP13]: PCIE PCH Root Port #13 + Package() { 0x001DFFFF, 0, 0, 16 }, + // [RP10]: PCIE PCH Root Port #10 + // [RP14]: PCIE PCH Root Port #14 + Package() { 0x001DFFFF, 1, 0, 17 }, + // [RP11]: PCIE PCH Root Port #11 + // [RP15]: PCIE PCH Root Port #15 + Package() { 0x001DFFFF, 2, 0, 18 }, + // [RP12]: PCIE PCH Root Port #12 + // [RP16]: PCIE PCH Root Port #16 + Package() { 0x001DFFFF, 3, 0, 19 }, + // [UAR0]: UART #0 on PCH + Package() { 0x001EFFFF, 0, 0, 20 }, + // [UAR1]: UART #1 on PCH + Package() { 0x001EFFFF, 1, 0, 21 }, + // [SPI0]: SPI #0 on PCH + Package() { 0x001EFFFF, 2, 0, 22 }, + // [SPI1]: SPI #1 on PCH + Package() { 0x001EFFFF, 3, 0, 23 }, + // [CAVS]: HD Audio Subsystem Controller on PCH + // [SMBS]: SMBus controller on PCH + // [GBE1]: GbE Controller on PCH + // [NTPK]: Northpeak Controller on PCH + Package() { 0x001FFFFF, 0, 0, 16 }, + }) + + Name (AH00, Package() { + // [DMI0]: Legacy PCI Express Port 0 on PC00 + Package() { 0x0000FFFF, 0, 0, 31 }, + // [CB0A]: CB3DMA on PC00 + // [CB0E]: CB3DMA on PC00 + Package() { 0x0004FFFF, 0, 0, 26 }, + // [CB0B]: CB3DMA on PC00 + // [CB0F]: CB3DMA on PC00 + Package() { 0x0004FFFF, 1, 0, 27 }, + // [CB0C]: CB3DMA on PC00 + // [CB0G]: CB3DMA on PC00 + Package() { 0x0004FFFF, 2, 0, 26 }, + // [CB0D]: CB3DMA on PC00 + // [CB0H]: CB3DMA on PC00 + Package() { 0x0004FFFF, 3, 0, 27 }, + // [IIM0]: IIOMISC on PC00 + Package() { 0x0005FFFF, 0, 0, 16 }, + Package() { 0x0005FFFF, 1, 0, 17 }, + Package() { 0x0005FFFF, 2, 0, 18 }, + Package() { 0x0005FFFF, 3, 0, 19 }, + // [UBX0]: Uncore 0 UBOX Device + Package() { 0x0008FFFF, 0, 0, 24 }, + Package() { 0x0008FFFF, 1, 0, 28 }, + Package() { 0x0008FFFF, 2, 0, 29 }, + Package() { 0x0008FFFF, 3, 0, 30 }, + // [DISP]: Display Controller + Package() { 0x000FFFFF, 0, 0, 16 }, + // [IHC1]: HECI #1 + // [IHC3]: HECI #3 + Package() { 0x0010FFFF, 0, 0, 16 }, + // [IHC2]: HECI #2 + Package() { 0x0010FFFF, 1, 0, 17 }, + // [IIDR]: IDE-Redirection (IDE-R) + Package() { 0x0010FFFF, 2, 0, 18 }, + // [IMKT]: Keyboard and Text (KT) Redirection + Package() { 0x0010FFFF, 3, 0, 19 }, + // [SAT2]: sSATA Host controller 2 on PCH + Package() { 0x0011FFFF, 0, 0, 16 }, + // [XHCI]: xHCI controller 1 on PCH + Package() { 0x0014FFFF, 0, 0, 16 }, + // [OTG0]: USB Device Controller (OTG) on PCH + Package() { 0x0014FFFF, 1, 0, 17 }, + // [TERM]: Thermal Subsystem on PCH + Package() { 0x0014FFFF, 2, 0, 18 }, + // [CAMR]: Camera IO Host Controller on PCH + Package() { 0x0014FFFF, 3, 0, 19 }, + // [HEC1]: HECI #1 on PCH + // [HEC3]: HECI #3 on PCH + Package() { 0x0016FFFF, 0, 0, 16 }, + // [HEC2]: HECI #2 on PCH + Package() { 0x0016FFFF, 1, 0, 17 }, + // [IDER]: ME IDE redirect on PCH + Package() { 0x0016FFFF, 2, 0, 18 }, + // [MEKT]: MEKT on PCH + Package() { 0x0016FFFF, 3, 0, 19 }, + // [SAT1]: SATA controller 1 on PCH + Package() { 0x0017FFFF, 0, 0, 16 }, + // [NAN1]: NAND Cycle Router on PCH + Package() { 0x0018FFFF, 0, 0, 16 }, + // [RP17]: PCIE PCH Root Port #17 + Package() { 0x001BFFFF, 0, 0, 16 }, + // [RP18]: PCIE PCH Root Port #18 + Package() { 0x001BFFFF, 1, 0, 17 }, + // [RP19]: PCIE PCH Root Port #19 + Package() { 0x001BFFFF, 2, 0, 18 }, + // [RP20]: PCIE PCH Root Port #20 + Package() { 0x001BFFFF, 3, 0, 19 }, + // [RP01]: PCIE PCH Root Port #1 + // [RP05]: PCIE PCH Root Port #5 + Package() { 0x001CFFFF, 0, 0, 16 }, + // [RP02]: PCIE PCH Root Port #2 + // [RP06]: PCIE PCH Root Port #6 + Package() { 0x001CFFFF, 1, 0, 17 }, + // [RP03]: PCIE PCH Root Port #3 + // [RP07]: PCIE PCH Root Port #7 + Package() { 0x001CFFFF, 2, 0, 18 }, + // [RP04]: PCIE PCH Root Port #4 + // [RP08]: PCIE PCH Root Port #8 + Package() { 0x001CFFFF, 3, 0, 19 }, + // [RP09]: PCIE PCH Root Port #9 + // [RP13]: PCIE PCH Root Port #13 + Package() { 0x001DFFFF, 0, 0, 16 }, + // [RP10]: PCIE PCH Root Port #10 + // [RP14]: PCIE PCH Root Port #14 + Package() { 0x001DFFFF, 1, 0, 17 }, + // [RP11]: PCIE PCH Root Port #11 + // [RP15]: PCIE PCH Root Port #15 + Package() { 0x001DFFFF, 2, 0, 18 }, + // [RP12]: PCIE PCH Root Port #12 + // [RP16]: PCIE PCH Root Port #16 + Package() { 0x001DFFFF, 3, 0, 19 }, + // [UAR0]: UART #0 on PCH + Package() { 0x001EFFFF, 0, 0, 20 }, + // [UAR1]: UART #1 on PCH + Package() { 0x001EFFFF, 1, 0, 21 }, + // [SPI0]: SPI #0 on PCH + Package() { 0x001EFFFF, 2, 0, 22 }, + // [SPI1]: SPI #1 on PCH + Package() { 0x001EFFFF, 3, 0, 23 }, + // [CAVS]: HD Audio Subsystem Controller on PCH + // [SMBS]: SMBus controller on PCH + // [GBE1]: GbE Controller on PCH + // [NTPK]: Northpeak Controller on PCH + Package() { 0x001FFFFF, 0, 0, 16 }, + }) + + Name (PR01, Package() { + // [SLTH]: PCIE PCH Slot #17 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR01, Package() { + // [SLTH]: PCIE PCH Slot #17 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (PR02, Package() { + // [SLTI]: PCIE PCH Slot #18 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKD, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR02, Package() { + // [SLTI]: PCIE PCH Slot #18 + Package() { 0x0000FFFF, 0, 0, 17 }, + Package() { 0x0000FFFF, 1, 0, 18 }, + Package() { 0x0000FFFF, 2, 0, 19 }, + Package() { 0x0000FFFF, 3, 0, 16 }, + }) + + Name (PR03, Package() { + // [SLTJ]: PCIE PCH Slot #19 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKD, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKB, 0 }, + }) + + Name (AR03, Package() { + // [SLTJ]: PCIE PCH Slot #19 + Package() { 0x0000FFFF, 0, 0, 18 }, + Package() { 0x0000FFFF, 1, 0, 19 }, + Package() { 0x0000FFFF, 2, 0, 16 }, + Package() { 0x0000FFFF, 3, 0, 17 }, + }) + + Name (PR04, Package() { + // [SLTK]: PCIE PCH Slot #20 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKD, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKC, 0 }, + }) + + Name (AR04, Package() { + // [SLTK]: PCIE PCH Slot #20 + Package() { 0x0000FFFF, 0, 0, 19 }, + Package() { 0x0000FFFF, 1, 0, 16 }, + Package() { 0x0000FFFF, 2, 0, 17 }, + Package() { 0x0000FFFF, 3, 0, 18 }, + }) + + Name (PR05, Package() { + // [SLT1]: PCIE PCH Slot #1 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR05, Package() { + // [SLT1]: PCIE PCH Slot #1 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (PR06, Package() { + // [SLT2]: PCIE PCH Slot #2 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKD, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR06, Package() { + // [SLT2]: PCIE PCH Slot #2 + Package() { 0x0000FFFF, 0, 0, 17 }, + Package() { 0x0000FFFF, 1, 0, 18 }, + Package() { 0x0000FFFF, 2, 0, 19 }, + Package() { 0x0000FFFF, 3, 0, 16 }, + }) + + Name (PR07, Package() { + // [SLT3]: PCIE PCH Slot #3 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKD, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKB, 0 }, + }) + + Name (AR07, Package() { + // [SLT3]: PCIE PCH Slot #3 + Package() { 0x0000FFFF, 0, 0, 18 }, + Package() { 0x0000FFFF, 1, 0, 19 }, + Package() { 0x0000FFFF, 2, 0, 16 }, + Package() { 0x0000FFFF, 3, 0, 17 }, + }) + + Name (PR08, Package() { + // [SLT4]: PCIE PCH Slot #4 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKD, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKC, 0 }, + }) + + Name (AR08, Package() { + // [SLT4]: PCIE PCH Slot #4 + Package() { 0x0000FFFF, 0, 0, 19 }, + Package() { 0x0000FFFF, 1, 0, 16 }, + Package() { 0x0000FFFF, 2, 0, 17 }, + Package() { 0x0000FFFF, 3, 0, 18 }, + }) + + Name (PR09, Package() { + // [SLT5]: PCIE PCH Slot #5 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR09, Package() { + // [SLT5]: PCIE PCH Slot #5 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (PR0A, Package() { + // [SLT6]: PCIE PCH Slot #6 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKD, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR0A, Package() { + // [SLT6]: PCIE PCH Slot #6 + Package() { 0x0000FFFF, 0, 0, 17 }, + Package() { 0x0000FFFF, 1, 0, 18 }, + Package() { 0x0000FFFF, 2, 0, 19 }, + Package() { 0x0000FFFF, 3, 0, 16 }, + }) + + Name (PR0B, Package() { + // [SLT7]: PCIE PCH Slot #7 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKD, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKB, 0 }, + }) + + Name (AR0B, Package() { + // [SLT7]: PCIE PCH Slot #7 + Package() { 0x0000FFFF, 0, 0, 18 }, + Package() { 0x0000FFFF, 1, 0, 19 }, + Package() { 0x0000FFFF, 2, 0, 16 }, + Package() { 0x0000FFFF, 3, 0, 17 }, + }) + + Name (PR0C, Package() { + // [SLT8]: PCIE PCH Slot #8 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKD, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKC, 0 }, + }) + + Name (AR0C, Package() { + // [SLT8]: PCIE PCH Slot #8 + Package() { 0x0000FFFF, 0, 0, 19 }, + Package() { 0x0000FFFF, 1, 0, 16 }, + Package() { 0x0000FFFF, 2, 0, 17 }, + Package() { 0x0000FFFF, 3, 0, 18 }, + }) + + Name (PR0D, Package() { + // [SLT9]: PCIE PCH Slot #9 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR0D, Package() { + // [SLT9]: PCIE PCH Slot #9 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (PR0E, Package() { + // [SLTA]: PCIE PCH Slot #10 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKD, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR0E, Package() { + // [SLTA]: PCIE PCH Slot #10 + Package() { 0x0000FFFF, 0, 0, 17 }, + Package() { 0x0000FFFF, 1, 0, 18 }, + Package() { 0x0000FFFF, 2, 0, 19 }, + Package() { 0x0000FFFF, 3, 0, 16 }, + }) + + Name (PR0F, Package() { + // [SLTB]: PCIE PCH Slot #11 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKD, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKB, 0 }, + }) + + Name (AR0F, Package() { + // [SLTB]: PCIE PCH Slot #11 + Package() { 0x0000FFFF, 0, 0, 18 }, + Package() { 0x0000FFFF, 1, 0, 19 }, + Package() { 0x0000FFFF, 2, 0, 16 }, + Package() { 0x0000FFFF, 3, 0, 17 }, + }) + + Name (PR10, Package() { + // [SLTC]: PCIE PCH Slot #12 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKD, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKC, 0 }, + }) + + Name (AR10, Package() { + // [SLTC]: PCIE PCH Slot #12 + Package() { 0x0000FFFF, 0, 0, 19 }, + Package() { 0x0000FFFF, 1, 0, 16 }, + Package() { 0x0000FFFF, 2, 0, 17 }, + Package() { 0x0000FFFF, 3, 0, 18 }, + }) + + Name (PR11, Package() { + // [SLTD]: PCIE PCH Slot #13 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR11, Package() { + // [SLTD]: PCIE PCH Slot #13 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (PR12, Package() { + // [SLTE]: PCIE PCH Slot #14 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKD, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR12, Package() { + // [SLTE]: PCIE PCH Slot #14 + Package() { 0x0000FFFF, 0, 0, 17 }, + Package() { 0x0000FFFF, 1, 0, 18 }, + Package() { 0x0000FFFF, 2, 0, 19 }, + Package() { 0x0000FFFF, 3, 0, 16 }, + }) + + Name (PR13, Package() { + // [SLTF]: PCIE PCH Slot #15 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKD, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKB, 0 }, + }) + + Name (AR13, Package() { + // [SLTF]: PCIE PCH Slot #15 + Package() { 0x0000FFFF, 0, 0, 18 }, + Package() { 0x0000FFFF, 1, 0, 19 }, + Package() { 0x0000FFFF, 2, 0, 16 }, + Package() { 0x0000FFFF, 3, 0, 17 }, + }) + + Name (PR14, Package() { + // [SLTG]: PCIE PCH Slot #16 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKD, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKC, 0 }, + }) + + Name (AR14, Package() { + // [SLTG]: PCIE PCH Slot #16 + Package() { 0x0000FFFF, 0, 0, 19 }, + Package() { 0x0000FFFF, 1, 0, 16 }, + Package() { 0x0000FFFF, 2, 0, 17 }, + Package() { 0x0000FFFF, 3, 0, 18 }, + }) + + Name (PR15, Package() { + // [BR1A]: PCI Express Port 1A on PC01 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [BR1B]: PCI Express Port 1B on PC01 + Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [BR1C]: PCI Express Port 1C on PC01 + Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [BR1D]: PCI Express Port 1D on PC01 + Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [CHA0]: Uncore 1 CHAUTIL0-7 Device + Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHA1]: Uncore 1 CHAUTIL8-15 Device + Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHA2]: Uncore 1 CHAUTIL16-23 Device + Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHA3]: Uncore 1 CHAUTIL24-27 Device + Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHA4]: Uncore 1 CHASAD0-7 Device + Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHA5]: Uncore 1 CHASAD8-15 Device + Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHA6]: Uncore 1 CHASAD16-23 Device + Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHA7]: Uncore 1 CHASAD24-27 Device + Package() { 0x0011FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0011FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0011FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0011FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CMS0]: Uncore 1 CMSCHA0-7 Device + Package() { 0x0014FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0014FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0014FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0014FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CMS1]: Uncore 1 CMS0CHA8-15 Device + Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CMS2]: Uncore 1 CMS0CHA16-23 Device + Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CMS3]: Uncore 1 CMS0CHA24-27 Device + Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CDL0]: Uncore 1 CHASADALL Device + Package() { 0x001DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x001DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x001DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x001DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [PCU0]: Uncore 1 PCUCR Devices + Package() { 0x001EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x001EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x001EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x001EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [VCU0]: Uncore 1 VCUCR Device + Package() { 0x001FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x001FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x001FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x001FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR15, Package() { + // [BR1A]: PCI Express Port 1A on PC01 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [BR1B]: PCI Express Port 1B on PC01 + Package() { 0x0001FFFF, 0, 0, 16 }, + // [BR1C]: PCI Express Port 1C on PC01 + Package() { 0x0002FFFF, 0, 0, 16 }, + // [BR1D]: PCI Express Port 1D on PC01 + Package() { 0x0003FFFF, 0, 0, 16 }, + // [CHA0]: Uncore 1 CHAUTIL0-7 Device + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + // [CHA1]: Uncore 1 CHAUTIL8-15 Device + Package() { 0x0009FFFF, 0, 0, 16 }, + Package() { 0x0009FFFF, 1, 0, 17 }, + Package() { 0x0009FFFF, 2, 0, 18 }, + Package() { 0x0009FFFF, 3, 0, 19 }, + // [CHA2]: Uncore 1 CHAUTIL16-23 Device + Package() { 0x000AFFFF, 0, 0, 16 }, + Package() { 0x000AFFFF, 1, 0, 17 }, + Package() { 0x000AFFFF, 2, 0, 18 }, + Package() { 0x000AFFFF, 3, 0, 19 }, + // [CHA3]: Uncore 1 CHAUTIL24-27 Device + Package() { 0x000BFFFF, 0, 0, 16 }, + Package() { 0x000BFFFF, 1, 0, 17 }, + Package() { 0x000BFFFF, 2, 0, 18 }, + Package() { 0x000BFFFF, 3, 0, 19 }, + // [CHA4]: Uncore 1 CHASAD0-7 Device + Package() { 0x000EFFFF, 0, 0, 16 }, + Package() { 0x000EFFFF, 1, 0, 17 }, + Package() { 0x000EFFFF, 2, 0, 18 }, + Package() { 0x000EFFFF, 3, 0, 19 }, + // [CHA5]: Uncore 1 CHASAD8-15 Device + Package() { 0x000FFFFF, 0, 0, 16 }, + Package() { 0x000FFFFF, 1, 0, 17 }, + Package() { 0x000FFFFF, 2, 0, 18 }, + Package() { 0x000FFFFF, 3, 0, 19 }, + // [CHA6]: Uncore 1 CHASAD16-23 Device + Package() { 0x0010FFFF, 0, 0, 16 }, + Package() { 0x0010FFFF, 1, 0, 17 }, + Package() { 0x0010FFFF, 2, 0, 18 }, + Package() { 0x0010FFFF, 3, 0, 19 }, + // [CHA7]: Uncore 1 CHASAD24-27 Device + Package() { 0x0011FFFF, 0, 0, 16 }, + Package() { 0x0011FFFF, 1, 0, 17 }, + Package() { 0x0011FFFF, 2, 0, 18 }, + Package() { 0x0011FFFF, 3, 0, 19 }, + // [CMS0]: Uncore 1 CMSCHA0-7 Device + Package() { 0x0014FFFF, 0, 0, 16 }, + Package() { 0x0014FFFF, 1, 0, 17 }, + Package() { 0x0014FFFF, 2, 0, 18 }, + Package() { 0x0014FFFF, 3, 0, 19 }, + // [CMS1]: Uncore 1 CMS0CHA8-15 Device + Package() { 0x0015FFFF, 0, 0, 16 }, + Package() { 0x0015FFFF, 1, 0, 17 }, + Package() { 0x0015FFFF, 2, 0, 18 }, + Package() { 0x0015FFFF, 3, 0, 19 }, + // [CMS2]: Uncore 1 CMS0CHA16-23 Device + Package() { 0x0016FFFF, 0, 0, 16 }, + Package() { 0x0016FFFF, 1, 0, 17 }, + Package() { 0x0016FFFF, 2, 0, 18 }, + Package() { 0x0016FFFF, 3, 0, 19 }, + // [CMS3]: Uncore 1 CMS0CHA24-27 Device + Package() { 0x0017FFFF, 0, 0, 16 }, + Package() { 0x0017FFFF, 1, 0, 17 }, + Package() { 0x0017FFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 3, 0, 19 }, + // [CDL0]: Uncore 1 CHASADALL Device + Package() { 0x001DFFFF, 0, 0, 16 }, + Package() { 0x001DFFFF, 1, 0, 17 }, + Package() { 0x001DFFFF, 2, 0, 18 }, + Package() { 0x001DFFFF, 3, 0, 19 }, + // [PCU0]: Uncore 1 PCUCR Devices + Package() { 0x001EFFFF, 0, 0, 16 }, + Package() { 0x001EFFFF, 1, 0, 17 }, + Package() { 0x001EFFFF, 2, 0, 18 }, + Package() { 0x001EFFFF, 3, 0, 19 }, + // [VCU0]: Uncore 1 VCUCR Device + Package() { 0x001FFFFF, 0, 0, 16 }, + Package() { 0x001FFFFF, 1, 0, 17 }, + Package() { 0x001FFFFF, 2, 0, 18 }, + Package() { 0x001FFFFF, 3, 0, 19 }, + }) + + Name (AH15, Package() { + // [BR1A]: PCI Express Port 1A on PC01 + Package() { 0x0000FFFF, 0, 0, 39 }, + // [BR1B]: PCI Express Port 1B on PC01 + Package() { 0x0001FFFF, 0, 0, 39 }, + // [BR1C]: PCI Express Port 1C on PC01 + Package() { 0x0002FFFF, 0, 0, 39 }, + // [BR1D]: PCI Express Port 1D on PC01 + Package() { 0x0003FFFF, 0, 0, 39 }, + // [CHA0]: Uncore 1 CHAUTIL0-7 Device + Package() { 0x0008FFFF, 0, 0, 32 }, + Package() { 0x0008FFFF, 1, 0, 36 }, + Package() { 0x0008FFFF, 2, 0, 37 }, + Package() { 0x0008FFFF, 3, 0, 38 }, + // [CHA1]: Uncore 1 CHAUTIL8-15 Device + Package() { 0x0009FFFF, 0, 0, 32 }, + Package() { 0x0009FFFF, 1, 0, 36 }, + Package() { 0x0009FFFF, 2, 0, 37 }, + Package() { 0x0009FFFF, 3, 0, 38 }, + // [CHA2]: Uncore 1 CHAUTIL16-23 Device + Package() { 0x000AFFFF, 0, 0, 32 }, + Package() { 0x000AFFFF, 1, 0, 36 }, + Package() { 0x000AFFFF, 2, 0, 37 }, + Package() { 0x000AFFFF, 3, 0, 38 }, + // [CHA3]: Uncore 1 CHAUTIL24-27 Device + Package() { 0x000BFFFF, 0, 0, 32 }, + Package() { 0x000BFFFF, 1, 0, 36 }, + Package() { 0x000BFFFF, 2, 0, 37 }, + Package() { 0x000BFFFF, 3, 0, 38 }, + // [CHA4]: Uncore 1 CHASAD0-7 Device + Package() { 0x000EFFFF, 0, 0, 32 }, + Package() { 0x000EFFFF, 1, 0, 36 }, + Package() { 0x000EFFFF, 2, 0, 37 }, + Package() { 0x000EFFFF, 3, 0, 38 }, + // [CHA5]: Uncore 1 CHASAD8-15 Device + Package() { 0x000FFFFF, 0, 0, 32 }, + Package() { 0x000FFFFF, 1, 0, 36 }, + Package() { 0x000FFFFF, 2, 0, 37 }, + Package() { 0x000FFFFF, 3, 0, 38 }, + // [CHA6]: Uncore 1 CHASAD16-23 Device + Package() { 0x0010FFFF, 0, 0, 32 }, + Package() { 0x0010FFFF, 1, 0, 36 }, + Package() { 0x0010FFFF, 2, 0, 37 }, + Package() { 0x0010FFFF, 3, 0, 38 }, + // [CHA7]: Uncore 1 CHASAD24-27 Device + Package() { 0x0011FFFF, 0, 0, 32 }, + Package() { 0x0011FFFF, 1, 0, 36 }, + Package() { 0x0011FFFF, 2, 0, 37 }, + Package() { 0x0011FFFF, 3, 0, 38 }, + // [CMS0]: Uncore 1 CMSCHA0-7 Device + Package() { 0x0014FFFF, 0, 0, 32 }, + Package() { 0x0014FFFF, 1, 0, 36 }, + Package() { 0x0014FFFF, 2, 0, 37 }, + Package() { 0x0014FFFF, 3, 0, 38 }, + // [CMS1]: Uncore 1 CMS0CHA8-15 Device + Package() { 0x0015FFFF, 0, 0, 32 }, + Package() { 0x0015FFFF, 1, 0, 36 }, + Package() { 0x0015FFFF, 2, 0, 37 }, + Package() { 0x0015FFFF, 3, 0, 38 }, + // [CMS2]: Uncore 1 CMS0CHA16-23 Device + Package() { 0x0016FFFF, 0, 0, 32 }, + Package() { 0x0016FFFF, 1, 0, 36 }, + Package() { 0x0016FFFF, 2, 0, 37 }, + Package() { 0x0016FFFF, 3, 0, 38 }, + // [CMS3]: Uncore 1 CMS0CHA24-27 Device + Package() { 0x0017FFFF, 0, 0, 32 }, + Package() { 0x0017FFFF, 1, 0, 36 }, + Package() { 0x0017FFFF, 2, 0, 37 }, + Package() { 0x0017FFFF, 3, 0, 38 }, + // [CDL0]: Uncore 1 CHASADALL Device + Package() { 0x001DFFFF, 0, 0, 32 }, + Package() { 0x001DFFFF, 1, 0, 36 }, + Package() { 0x001DFFFF, 2, 0, 37 }, + Package() { 0x001DFFFF, 3, 0, 38 }, + // [PCU0]: Uncore 1 PCUCR Devices + Package() { 0x001EFFFF, 0, 0, 32 }, + Package() { 0x001EFFFF, 1, 0, 36 }, + Package() { 0x001EFFFF, 2, 0, 37 }, + Package() { 0x001EFFFF, 3, 0, 38 }, + // [VCU0]: Uncore 1 VCUCR Device + Package() { 0x001FFFFF, 0, 0, 32 }, + Package() { 0x001FFFFF, 1, 0, 36 }, + Package() { 0x001FFFFF, 2, 0, 37 }, + Package() { 0x001FFFFF, 3, 0, 38 }, + }) + + Name (PR16, Package() { + // [SL01]: PCI Express Slot 1 on 1A on PC01 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR16, Package() { + // [SL01]: PCI Express Slot 1 on 1A on PC01 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH16, Package() { + // [SL01]: PCI Express Slot 1 on 1A on PC01 + Package() { 0x0000FFFF, 0, 0, 32 }, + Package() { 0x0000FFFF, 1, 0, 36 }, + Package() { 0x0000FFFF, 2, 0, 37 }, + Package() { 0x0000FFFF, 3, 0, 38 }, + }) + + Name (PR17, Package() { + // [SL02]: PCI Express Slot 2 on 1B on PC01 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR17, Package() { + // [SL02]: PCI Express Slot 2 on 1B on PC01 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH17, Package() { + // [SL02]: PCI Express Slot 2 on 1B on PC01 + Package() { 0x0000FFFF, 0, 0, 33 }, + Package() { 0x0000FFFF, 1, 0, 38 }, + Package() { 0x0000FFFF, 2, 0, 36 }, + Package() { 0x0000FFFF, 3, 0, 37 }, + }) + + Name (PR18, Package() { + // [SL03]: PCI Express Slot 3 on 1C on PC01 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR18, Package() { + // [SL03]: PCI Express Slot 3 on 1C on PC01 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH18, Package() { + // [SL03]: PCI Express Slot 3 on 1C on PC01 + Package() { 0x0000FFFF, 0, 0, 34 }, + Package() { 0x0000FFFF, 1, 0, 37 }, + Package() { 0x0000FFFF, 2, 0, 38 }, + Package() { 0x0000FFFF, 3, 0, 36 }, + }) + + Name (PR19, Package() { + // [SL04]: PCI Express Slot 4 on 1D on PC01 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR19, Package() { + // [SL04]: PCI Express Slot 4 on 1D on PC01 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH19, Package() { + // [SL04]: PCI Express Slot 4 on 1D on PC01 + Package() { 0x0000FFFF, 0, 0, 35 }, + Package() { 0x0000FFFF, 1, 0, 38 }, + Package() { 0x0000FFFF, 2, 0, 36 }, + Package() { 0x0000FFFF, 3, 0, 37 }, + }) + + Name (PR1A, Package() { + // [BR2A]: PCI Express Port 2A on PC02 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [BR2B]: PCI Express Port 2B on PC02 + Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [BR2C]: PCI Express Port 2C on PC02 + Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [BR2D]: PCI Express Port 2D on PC02 + Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [M2M0]: Uncore 2 M2MEM0 Device + Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M2M1]: Uncore 2 M2MEM10 Device + Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCM0]: Uncore 2 MCMAIN Device + Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCD0]: Uncore 2 MCDECS2 Device + Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCM1]: Uncore 2 MCMAIN Device + Package() { 0x000CFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000CFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000CFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000CFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCD1]: Uncore 2 MCDECS12 Device + Package() { 0x000DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [UMC0]: Uncore 2 Unicast MC0 DDRIO0 Device + Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [UMC1]: Uncore 2 Unicast MC1 DDRIO0 Device + Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR1A, Package() { + // [BR2A]: PCI Express Port 2A on PC02 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [BR2B]: PCI Express Port 2B on PC02 + Package() { 0x0001FFFF, 0, 0, 16 }, + // [BR2C]: PCI Express Port 2C on PC02 + Package() { 0x0002FFFF, 0, 0, 16 }, + // [BR2D]: PCI Express Port 2D on PC02 + Package() { 0x0003FFFF, 0, 0, 16 }, + // [M2M0]: Uncore 2 M2MEM0 Device + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + // [M2M1]: Uncore 2 M2MEM10 Device + Package() { 0x0009FFFF, 0, 0, 16 }, + Package() { 0x0009FFFF, 1, 0, 17 }, + Package() { 0x0009FFFF, 2, 0, 18 }, + Package() { 0x0009FFFF, 3, 0, 19 }, + // [MCM0]: Uncore 2 MCMAIN Device + Package() { 0x000AFFFF, 0, 0, 16 }, + Package() { 0x000AFFFF, 1, 0, 17 }, + Package() { 0x000AFFFF, 2, 0, 18 }, + Package() { 0x000AFFFF, 3, 0, 19 }, + // [MCD0]: Uncore 2 MCDECS2 Device + Package() { 0x000BFFFF, 0, 0, 16 }, + Package() { 0x000BFFFF, 1, 0, 17 }, + Package() { 0x000BFFFF, 2, 0, 18 }, + Package() { 0x000BFFFF, 3, 0, 19 }, + // [MCM1]: Uncore 2 MCMAIN Device + Package() { 0x000CFFFF, 0, 0, 16 }, + Package() { 0x000CFFFF, 1, 0, 17 }, + Package() { 0x000CFFFF, 2, 0, 18 }, + Package() { 0x000CFFFF, 3, 0, 19 }, + // [MCD1]: Uncore 2 MCDECS12 Device + Package() { 0x000DFFFF, 0, 0, 16 }, + Package() { 0x000DFFFF, 1, 0, 17 }, + Package() { 0x000DFFFF, 2, 0, 18 }, + Package() { 0x000DFFFF, 3, 0, 19 }, + // [UMC0]: Uncore 2 Unicast MC0 DDRIO0 Device + Package() { 0x0016FFFF, 0, 0, 16 }, + Package() { 0x0016FFFF, 1, 0, 17 }, + Package() { 0x0016FFFF, 2, 0, 18 }, + Package() { 0x0016FFFF, 3, 0, 19 }, + // [UMC1]: Uncore 2 Unicast MC1 DDRIO0 Device + Package() { 0x0017FFFF, 0, 0, 16 }, + Package() { 0x0017FFFF, 1, 0, 17 }, + Package() { 0x0017FFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 3, 0, 19 }, + }) + + Name (AH1A, Package() { + // [BR2A]: PCI Express Port 2A on PC02 + Package() { 0x0000FFFF, 0, 0, 47 }, + // [BR2B]: PCI Express Port 2B on PC02 + Package() { 0x0001FFFF, 0, 0, 47 }, + // [BR2C]: PCI Express Port 2C on PC02 + Package() { 0x0002FFFF, 0, 0, 47 }, + // [BR2D]: PCI Express Port 2D on PC02 + Package() { 0x0003FFFF, 0, 0, 47 }, + // [M2M0]: Uncore 2 M2MEM0 Device + Package() { 0x0008FFFF, 0, 0, 40 }, + Package() { 0x0008FFFF, 1, 0, 44 }, + Package() { 0x0008FFFF, 2, 0, 45 }, + Package() { 0x0008FFFF, 3, 0, 46 }, + // [M2M1]: Uncore 2 M2MEM10 Device + Package() { 0x0009FFFF, 0, 0, 40 }, + Package() { 0x0009FFFF, 1, 0, 44 }, + Package() { 0x0009FFFF, 2, 0, 45 }, + Package() { 0x0009FFFF, 3, 0, 46 }, + // [MCM0]: Uncore 2 MCMAIN Device + Package() { 0x000AFFFF, 0, 0, 40 }, + Package() { 0x000AFFFF, 1, 0, 44 }, + Package() { 0x000AFFFF, 2, 0, 45 }, + Package() { 0x000AFFFF, 3, 0, 46 }, + // [MCD0]: Uncore 2 MCDECS2 Device + Package() { 0x000BFFFF, 0, 0, 40 }, + Package() { 0x000BFFFF, 1, 0, 44 }, + Package() { 0x000BFFFF, 2, 0, 45 }, + Package() { 0x000BFFFF, 3, 0, 46 }, + // [MCM1]: Uncore 2 MCMAIN Device + Package() { 0x000CFFFF, 0, 0, 40 }, + Package() { 0x000CFFFF, 1, 0, 44 }, + Package() { 0x000CFFFF, 2, 0, 45 }, + Package() { 0x000CFFFF, 3, 0, 46 }, + // [MCD1]: Uncore 2 MCDECS12 Device + Package() { 0x000DFFFF, 0, 0, 40 }, + Package() { 0x000DFFFF, 1, 0, 44 }, + Package() { 0x000DFFFF, 2, 0, 45 }, + Package() { 0x000DFFFF, 3, 0, 46 }, + // [UMC0]: Uncore 2 Unicast MC0 DDRIO0 Device + Package() { 0x0016FFFF, 0, 0, 40 }, + Package() { 0x0016FFFF, 1, 0, 44 }, + Package() { 0x0016FFFF, 2, 0, 45 }, + Package() { 0x0016FFFF, 3, 0, 46 }, + // [UMC1]: Uncore 2 Unicast MC1 DDRIO0 Device + Package() { 0x0017FFFF, 0, 0, 40 }, + Package() { 0x0017FFFF, 1, 0, 44 }, + Package() { 0x0017FFFF, 2, 0, 45 }, + Package() { 0x0017FFFF, 3, 0, 46 }, + }) + + Name (PR1B, Package() { + // [SL05]: PCI Express Slot 5 on 2A on PC02 + // [EPCU]: EVA PCIe Uplink + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR1B, Package() { + // [SL05]: PCI Express Slot 5 on 2A on PC02 + // [EPCU]: EVA PCIe Uplink + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH1B, Package() { + // [SL05]: PCI Express Slot 5 on 2A on PC02 + // [EPCU]: EVA PCIe Uplink + Package() { 0x0000FFFF, 0, 0, 40 }, + Package() { 0x0000FFFF, 1, 0, 44 }, + Package() { 0x0000FFFF, 2, 0, 45 }, + Package() { 0x0000FFFF, 3, 0, 46 }, + }) + + Name (PR1C, Package() { + // [VSP0]: EVA Virtual Switch Port 0 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [VSP1]: EVA Virtual Switch Port 1 + Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [VSP2]: EVA Virtual Switch Port 2 + Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [VSP3]: EVA Virtual Switch Port 3 + Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR1C, Package() { + // [VSP0]: EVA Virtual Switch Port 0 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + // [VSP1]: EVA Virtual Switch Port 1 + Package() { 0x0001FFFF, 0, 0, 16 }, + // [VSP2]: EVA Virtual Switch Port 2 + Package() { 0x0002FFFF, 0, 0, 16 }, + // [VSP3]: EVA Virtual Switch Port 3 + Package() { 0x0003FFFF, 0, 0, 16 }, + }) + + Name (AH1C, Package() { + // [VSP0]: EVA Virtual Switch Port 0 + Package() { 0x0000FFFF, 0, 0, 40 }, + Package() { 0x0000FFFF, 1, 0, 44 }, + Package() { 0x0000FFFF, 2, 0, 45 }, + Package() { 0x0000FFFF, 3, 0, 46 }, + // [VSP1]: EVA Virtual Switch Port 1 + Package() { 0x0001FFFF, 0, 0, 40 }, + // [VSP2]: EVA Virtual Switch Port 2 + Package() { 0x0002FFFF, 0, 0, 40 }, + // [VSP3]: EVA Virtual Switch Port 3 + Package() { 0x0003FFFF, 0, 0, 40 }, + }) + + Name (PR1D, Package() { + // [CPM0]: EVA CPM0 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR1D, Package() { + // [CPM0]: EVA CPM0 + Package() { 0x0000FFFF, 0, 0, 16 }, + }) + + Name (AH1D, Package() { + // [CPM0]: EVA CPM0 + Package() { 0x0000FFFF, 0, 0, 40 }, + }) + + Name (PR1E, Package() { + // [CPM1]: EVA CPM1 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR1E, Package() { + // [CPM1]: EVA CPM1 + Package() { 0x0000FFFF, 0, 0, 16 }, + }) + + Name (AH1E, Package() { + // [CPM1]: EVA CPM1 + Package() { 0x0000FFFF, 0, 0, 41 }, + }) + + Name (PR1F, Package() { + // [CPM2]: EVA CPM2 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR1F, Package() { + // [CPM2]: EVA CPM2 + Package() { 0x0000FFFF, 0, 0, 16 }, + }) + + Name (AH1F, Package() { + // [CPM2]: EVA CPM2 + Package() { 0x0000FFFF, 0, 0, 45 }, + }) + + Name (PR20, Package() { + // [FPK0]: EVA Fort Park 0 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [FPK1]: EVA Fort Park 1 + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + // [FPK2]: EVA Fort Park 2 + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + // [FPK3]: EVA Fort Park 3 + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR20, Package() { + // [FPK0]: EVA Fort Park 0 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [FPK1]: EVA Fort Park 1 + Package() { 0x0000FFFF, 1, 0, 17 }, + // [FPK2]: EVA Fort Park 2 + Package() { 0x0000FFFF, 2, 0, 18 }, + // [FPK3]: EVA Fort Park 3 + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH20, Package() { + // [FPK0]: EVA Fort Park 0 + Package() { 0x0000FFFF, 0, 0, 46 }, + // [FPK1]: EVA Fort Park 1 + Package() { 0x0000FFFF, 1, 0, 46 }, + // [FPK2]: EVA Fort Park 2 + Package() { 0x0000FFFF, 2, 0, 46 }, + // [FPK3]: EVA Fort Park 3 + Package() { 0x0000FFFF, 3, 0, 46 }, + }) + + Name (PR21, Package() { + // [SL06]: PCI Express Slot 6 on 2B on PC02 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR21, Package() { + // [SL06]: PCI Express Slot 6 on 2B on PC02 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH21, Package() { + // [SL06]: PCI Express Slot 6 on 2B on PC02 + Package() { 0x0000FFFF, 0, 0, 41 }, + Package() { 0x0000FFFF, 1, 0, 46 }, + Package() { 0x0000FFFF, 2, 0, 44 }, + Package() { 0x0000FFFF, 3, 0, 45 }, + }) + + Name (PR22, Package() { + // [SL07]: PCI Express Slot 7 on 2C on PC02 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR22, Package() { + // [SL07]: PCI Express Slot 7 on 2C on PC02 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH22, Package() { + // [SL07]: PCI Express Slot 7 on 2C on PC02 + Package() { 0x0000FFFF, 0, 0, 42 }, + Package() { 0x0000FFFF, 1, 0, 45 }, + Package() { 0x0000FFFF, 2, 0, 46 }, + Package() { 0x0000FFFF, 3, 0, 44 }, + }) + + Name (PR23, Package() { + // [SL08]: PCI Express Slot 8 on 2D on PC02 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR23, Package() { + // [SL08]: PCI Express Slot 8 on 2D on PC02 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH23, Package() { + // [SL08]: PCI Express Slot 8 on 2D on PC02 + Package() { 0x0000FFFF, 0, 0, 43 }, + Package() { 0x0000FFFF, 1, 0, 46 }, + Package() { 0x0000FFFF, 2, 0, 44 }, + Package() { 0x0000FFFF, 3, 0, 45 }, + }) + + Name (PR24, Package() { + // [BR3A]: PCI Express Port 3A on PC03 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [BR3B]: PCI Express Port 3B on PC03 + Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [BR3C]: PCI Express Port 3C on PC03 + Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [BR3D]: PCI Express Port 3D on PC03 + Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [KTI0]: KTI0 + Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [KTI1]: KTI1 + Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [KTI2]: KTI2 + Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M3K0]: M3K0 + Package() { 0x0012FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0012FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0012FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0012FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M2U0]: M2U0 + Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M2D0]: M2D0 + Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M20]: M20 + Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR24, Package() { + // [BR3A]: PCI Express Port 3A on PC03 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [BR3B]: PCI Express Port 3B on PC03 + Package() { 0x0001FFFF, 0, 0, 16 }, + // [BR3C]: PCI Express Port 3C on PC03 + Package() { 0x0002FFFF, 0, 0, 16 }, + // [BR3D]: PCI Express Port 3D on PC03 + Package() { 0x0003FFFF, 0, 0, 16 }, + // [KTI0]: KTI0 + Package() { 0x000EFFFF, 0, 0, 16 }, + Package() { 0x000EFFFF, 1, 0, 17 }, + Package() { 0x000EFFFF, 2, 0, 18 }, + Package() { 0x000EFFFF, 3, 0, 19 }, + // [KTI1]: KTI1 + Package() { 0x000FFFFF, 0, 0, 16 }, + Package() { 0x000FFFFF, 1, 0, 17 }, + Package() { 0x000FFFFF, 2, 0, 18 }, + Package() { 0x000FFFFF, 3, 0, 19 }, + // [KTI2]: KTI2 + Package() { 0x0010FFFF, 0, 0, 16 }, + Package() { 0x0010FFFF, 1, 0, 17 }, + Package() { 0x0010FFFF, 2, 0, 18 }, + Package() { 0x0010FFFF, 3, 0, 19 }, + // [M3K0]: M3K0 + Package() { 0x0012FFFF, 0, 0, 16 }, + Package() { 0x0012FFFF, 1, 0, 17 }, + Package() { 0x0012FFFF, 2, 0, 18 }, + Package() { 0x0012FFFF, 3, 0, 19 }, + // [M2U0]: M2U0 + Package() { 0x0015FFFF, 0, 0, 16 }, + Package() { 0x0015FFFF, 1, 0, 17 }, + Package() { 0x0015FFFF, 2, 0, 18 }, + Package() { 0x0015FFFF, 3, 0, 19 }, + // [M2D0]: M2D0 + Package() { 0x0016FFFF, 0, 0, 16 }, + Package() { 0x0016FFFF, 1, 0, 17 }, + Package() { 0x0016FFFF, 2, 0, 18 }, + Package() { 0x0016FFFF, 3, 0, 19 }, + // [M20]: M20 + Package() { 0x0017FFFF, 0, 0, 16 }, + Package() { 0x0017FFFF, 1, 0, 17 }, + Package() { 0x0017FFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 3, 0, 19 }, + }) + + Name (AH24, Package() { + // [BR3A]: PCI Express Port 3A on PC03 + Package() { 0x0000FFFF, 0, 0, 55 }, + // [BR3B]: PCI Express Port 3B on PC03 + Package() { 0x0001FFFF, 0, 0, 55 }, + // [BR3C]: PCI Express Port 3C on PC03 + Package() { 0x0002FFFF, 0, 0, 55 }, + // [BR3D]: PCI Express Port 3D on PC03 + Package() { 0x0003FFFF, 0, 0, 55 }, + // [KTI0]: KTI0 + Package() { 0x000EFFFF, 0, 0, 48 }, + Package() { 0x000EFFFF, 1, 0, 52 }, + Package() { 0x000EFFFF, 2, 0, 53 }, + Package() { 0x000EFFFF, 3, 0, 54 }, + // [KTI1]: KTI1 + Package() { 0x000FFFFF, 0, 0, 48 }, + Package() { 0x000FFFFF, 1, 0, 52 }, + Package() { 0x000FFFFF, 2, 0, 53 }, + Package() { 0x000FFFFF, 3, 0, 54 }, + // [KTI2]: KTI2 + Package() { 0x0010FFFF, 0, 0, 48 }, + Package() { 0x0010FFFF, 1, 0, 52 }, + Package() { 0x0010FFFF, 2, 0, 53 }, + Package() { 0x0010FFFF, 3, 0, 54 }, + // [M3K0]: M3K0 + Package() { 0x0012FFFF, 0, 0, 48 }, + Package() { 0x0012FFFF, 1, 0, 52 }, + Package() { 0x0012FFFF, 2, 0, 53 }, + Package() { 0x0012FFFF, 3, 0, 54 }, + // [M2U0]: M2U0 + Package() { 0x0015FFFF, 0, 0, 48 }, + Package() { 0x0015FFFF, 1, 0, 52 }, + Package() { 0x0015FFFF, 2, 0, 53 }, + Package() { 0x0015FFFF, 3, 0, 54 }, + // [M2D0]: M2D0 + Package() { 0x0016FFFF, 0, 0, 48 }, + Package() { 0x0016FFFF, 1, 0, 52 }, + Package() { 0x0016FFFF, 2, 0, 53 }, + Package() { 0x0016FFFF, 3, 0, 54 }, + // [M20]: M20 + Package() { 0x0017FFFF, 0, 0, 48 }, + Package() { 0x0017FFFF, 1, 0, 52 }, + Package() { 0x0017FFFF, 2, 0, 53 }, + Package() { 0x0017FFFF, 3, 0, 54 }, + }) + + Name (PR25, Package() { + // [SL09]: PCI Express Slot 9 on 3A on PC03 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR25, Package() { + // [SL09]: PCI Express Slot 9 on 3A on PC03 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH25, Package() { + // [SL09]: PCI Express Slot 9 on 3A on PC03 + Package() { 0x0000FFFF, 0, 0, 48 }, + Package() { 0x0000FFFF, 1, 0, 52 }, + Package() { 0x0000FFFF, 2, 0, 53 }, + Package() { 0x0000FFFF, 3, 0, 54 }, + }) + + Name (PR26, Package() { + // [SL0A]: PCI Express Slot 10 on 3B on PC03 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR26, Package() { + // [SL0A]: PCI Express Slot 10 on 3B on PC03 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH26, Package() { + // [SL0A]: PCI Express Slot 10 on 3B on PC03 + Package() { 0x0000FFFF, 0, 0, 49 }, + Package() { 0x0000FFFF, 1, 0, 54 }, + Package() { 0x0000FFFF, 2, 0, 52 }, + Package() { 0x0000FFFF, 3, 0, 53 }, + }) + + Name (PR27, Package() { + // [SL0B]: PCI Express Slot 11 on 3C on PC03 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR27, Package() { + // [SL0B]: PCI Express Slot 11 on 3C on PC03 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH27, Package() { + // [SL0B]: PCI Express Slot 11 on 3C on PC03 + Package() { 0x0000FFFF, 0, 0, 50 }, + Package() { 0x0000FFFF, 1, 0, 53 }, + Package() { 0x0000FFFF, 2, 0, 54 }, + Package() { 0x0000FFFF, 3, 0, 52 }, + }) + + Name (PR28, Package() { + // [SL0C]: PCI Express Slot 12 on 3D on PC03 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR28, Package() { + // [SL0C]: PCI Express Slot 12 on 3D on PC03 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH28, Package() { + // [SL0C]: PCI Express Slot 12 on 3D on PC03 + Package() { 0x0000FFFF, 0, 0, 51 }, + Package() { 0x0000FFFF, 1, 0, 54 }, + Package() { 0x0000FFFF, 2, 0, 52 }, + Package() { 0x0000FFFF, 3, 0, 53 }, + }) + + Name (PR29, Package() { + // [MCP0]: PCI Express Port 4 on PC04 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR29, Package() { + // [MCP0]: PCI Express Port 4 on PC04 + Package() { 0x0000FFFF, 0, 0, 16 }, + }) + + Name (AH29, Package() { + // [MCP0]: PCI Express Port 4 on PC04 + Package() { 0x0000FFFF, 0, 0, 63 }, + }) + + Name (PR2A, Package() { + // [SL0D]: PCI Express Slot 13 on 4 on PC04 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR2A, Package() { + // [SL0D]: PCI Express Slot 13 on 4 on PC04 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH2A, Package() { + // [SL0D]: PCI Express Slot 13 on 4 on PC04 + Package() { 0x0000FFFF, 0, 0, 56 }, + Package() { 0x0000FFFF, 1, 0, 60 }, + Package() { 0x0000FFFF, 2, 0, 61 }, + Package() { 0x0000FFFF, 3, 0, 62 }, + }) + + Name (PR2B, Package() { + // [MCP1]: PCI Express Port 5 on PC05 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR2B, Package() { + // [MCP1]: PCI Express Port 5 on PC05 + Package() { 0x0000FFFF, 0, 0, 16 }, + }) + + Name (AH2B, Package() { + // [MCP1]: PCI Express Port 5 on PC05 + Package() { 0x0000FFFF, 0, 0, 71 }, + }) + + Name (PR2C, Package() { + // [SL0E]: PCI Express Slot 14 on 5 on PC05 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR2C, Package() { + // [SL0E]: PCI Express Slot 14 on 5 on PC05 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH2C, Package() { + // [SL0E]: PCI Express Slot 14 on 5 on PC05 + Package() { 0x0000FFFF, 0, 0, 64 }, + Package() { 0x0000FFFF, 1, 0, 68 }, + Package() { 0x0000FFFF, 2, 0, 69 }, + Package() { 0x0000FFFF, 3, 0, 70 }, + }) + + Name (PR2D, Package() { + // [QRP0]: PCI Express Port 0 on PC06 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [CB1B]: CB3DMA on PC06 + // [CB1F]: CB3DMA on PC06 + Package() { 0x0004FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + // [CB1C]: CB3DMA on PC06 + // [CB1G]: CB3DMA on PC06 + Package() { 0x0004FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + // [CB1D]: CB3DMA on PC06 + // [CB1H]: CB3DMA on PC06 + Package() { 0x0004FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CB1E]: CB3DMA on PC06 + // [CB1A]: CB3DMA on PC06 + Package() { 0x0004FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [IIM1]: IIOMISC on PC01 + Package() { 0x0005FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0005FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0005FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0005FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [UBX1]: Uncore 4 UBOX Device + Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR2D, Package() { + // [QRP0]: PCI Express Port 0 on PC06 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [CB1B]: CB3DMA on PC06 + // [CB1F]: CB3DMA on PC06 + Package() { 0x0004FFFF, 1, 0, 17 }, + // [CB1C]: CB3DMA on PC06 + // [CB1G]: CB3DMA on PC06 + Package() { 0x0004FFFF, 2, 0, 18 }, + // [CB1D]: CB3DMA on PC06 + // [CB1H]: CB3DMA on PC06 + Package() { 0x0004FFFF, 3, 0, 19 }, + // [CB1E]: CB3DMA on PC06 + // [CB1A]: CB3DMA on PC06 + Package() { 0x0004FFFF, 0, 0, 16 }, + // [IIM1]: IIOMISC on PC01 + Package() { 0x0005FFFF, 0, 0, 16 }, + Package() { 0x0005FFFF, 1, 0, 17 }, + Package() { 0x0005FFFF, 2, 0, 18 }, + Package() { 0x0005FFFF, 3, 0, 19 }, + // [UBX1]: Uncore 4 UBOX Device + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + }) + + Name (AH2D, Package() { + // [QRP0]: PCI Express Port 0 on PC06 + Package() { 0x0000FFFF, 0, 0, 79 }, + // [CB1B]: CB3DMA on PC06 + // [CB1F]: CB3DMA on PC06 + Package() { 0x0004FFFF, 1, 0, 75 }, + // [CB1C]: CB3DMA on PC06 + // [CB1G]: CB3DMA on PC06 + Package() { 0x0004FFFF, 2, 0, 74 }, + // [CB1D]: CB3DMA on PC06 + // [CB1H]: CB3DMA on PC06 + Package() { 0x0004FFFF, 3, 0, 75 }, + // [CB1E]: CB3DMA on PC06 + // [CB1A]: CB3DMA on PC06 + Package() { 0x0004FFFF, 0, 0, 74 }, + // [IIM1]: IIOMISC on PC01 + Package() { 0x0005FFFF, 0, 0, 16 }, + Package() { 0x0005FFFF, 1, 0, 17 }, + Package() { 0x0005FFFF, 2, 0, 18 }, + Package() { 0x0005FFFF, 3, 0, 19 }, + // [UBX1]: Uncore 4 UBOX Device + Package() { 0x0008FFFF, 0, 0, 72 }, + Package() { 0x0008FFFF, 1, 0, 76 }, + Package() { 0x0008FFFF, 2, 0, 77 }, + Package() { 0x0008FFFF, 3, 0, 78 }, + }) + + Name (PR2E, Package() { + // [SL0F]: PCI Express Slot 15 on P0 on PC06 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR2E, Package() { + // [SL0F]: PCI Express Slot 15 on P0 on PC06 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH2E, Package() { + // [SL0F]: PCI Express Slot 15 on P0 on PC06 + Package() { 0x0000FFFF, 0, 0, 72 }, + Package() { 0x0000FFFF, 1, 0, 76 }, + Package() { 0x0000FFFF, 2, 0, 77 }, + Package() { 0x0000FFFF, 3, 0, 78 }, + }) + + Name (PR2F, Package() { + // [QR1A]: PCI Express Port 1A on PC07 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [QR1B]: PCI Express Port 1B on PC07 + Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [QR1C]: PCI Express Port 1C on PC07 + Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [QR1D]: PCI Express Port 1D on PC07 + Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [CHB0]: Uncore 5 CHAUTIL0-7 Device + Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHB1]: Uncore 5 CHAUTIL8-15 Device + Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHB2]: Uncore 5 CHAUTIL16-23 Device + Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHB3]: Uncore 5 CHAUTIL24-27 Device + Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHB4]: Uncore 5 CHASAD0-7 Device + Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHB5]: Uncore 5 CHASAD8-15 Device + Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHB6]: Uncore 5 CHASAD16-23 Device + Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHB7]: Uncore 5 CHASAD24-27 Device + Package() { 0x0011FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0011FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0011FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0011FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CMS4]: Uncore 5 CMSCHA0-7 Device + Package() { 0x0014FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0014FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0014FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0014FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CMS5]: Uncore 5 CMS0CHA8-15 Device + Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CMS6]: Uncore 5 CMS0CHA16-23 Device + Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CMS7]: Uncore 5 CMS0CHA24-27 Device + Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CDL1]: Uncore 5 CHASADALL Device + Package() { 0x001DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x001DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x001DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x001DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [PCU1]: Uncore 5 PCUCR Devices + Package() { 0x001EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x001EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x001EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x001EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [VCU1]: Uncore 5 VCUCR Device + Package() { 0x001FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x001FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x001FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x001FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR2F, Package() { + // [QR1A]: PCI Express Port 1A on PC07 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [QR1B]: PCI Express Port 1B on PC07 + Package() { 0x0001FFFF, 0, 0, 16 }, + // [QR1C]: PCI Express Port 1C on PC07 + Package() { 0x0002FFFF, 0, 0, 16 }, + // [QR1D]: PCI Express Port 1D on PC07 + Package() { 0x0003FFFF, 0, 0, 16 }, + // [CHB0]: Uncore 5 CHAUTIL0-7 Device + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + // [CHB1]: Uncore 5 CHAUTIL8-15 Device + Package() { 0x0009FFFF, 0, 0, 16 }, + Package() { 0x0009FFFF, 1, 0, 17 }, + Package() { 0x0009FFFF, 2, 0, 18 }, + Package() { 0x0009FFFF, 3, 0, 19 }, + // [CHB2]: Uncore 5 CHAUTIL16-23 Device + Package() { 0x000AFFFF, 0, 0, 16 }, + Package() { 0x000AFFFF, 1, 0, 17 }, + Package() { 0x000AFFFF, 2, 0, 18 }, + Package() { 0x000AFFFF, 3, 0, 19 }, + // [CHB3]: Uncore 5 CHAUTIL24-27 Device + Package() { 0x000BFFFF, 0, 0, 16 }, + Package() { 0x000BFFFF, 1, 0, 17 }, + Package() { 0x000BFFFF, 2, 0, 18 }, + Package() { 0x000BFFFF, 3, 0, 19 }, + // [CHB4]: Uncore 5 CHASAD0-7 Device + Package() { 0x000EFFFF, 0, 0, 16 }, + Package() { 0x000EFFFF, 1, 0, 17 }, + Package() { 0x000EFFFF, 2, 0, 18 }, + Package() { 0x000EFFFF, 3, 0, 19 }, + // [CHB5]: Uncore 5 CHASAD8-15 Device + Package() { 0x000FFFFF, 0, 0, 16 }, + Package() { 0x000FFFFF, 1, 0, 17 }, + Package() { 0x000FFFFF, 2, 0, 18 }, + Package() { 0x000FFFFF, 3, 0, 19 }, + // [CHB6]: Uncore 5 CHASAD16-23 Device + Package() { 0x0010FFFF, 0, 0, 16 }, + Package() { 0x0010FFFF, 1, 0, 17 }, + Package() { 0x0010FFFF, 2, 0, 18 }, + Package() { 0x0010FFFF, 3, 0, 19 }, + // [CHB7]: Uncore 5 CHASAD24-27 Device + Package() { 0x0011FFFF, 0, 0, 16 }, + Package() { 0x0011FFFF, 1, 0, 17 }, + Package() { 0x0011FFFF, 2, 0, 18 }, + Package() { 0x0011FFFF, 3, 0, 19 }, + // [CMS4]: Uncore 5 CMSCHA0-7 Device + Package() { 0x0014FFFF, 0, 0, 16 }, + Package() { 0x0014FFFF, 1, 0, 17 }, + Package() { 0x0014FFFF, 2, 0, 18 }, + Package() { 0x0014FFFF, 3, 0, 19 }, + // [CMS5]: Uncore 5 CMS0CHA8-15 Device + Package() { 0x0015FFFF, 0, 0, 16 }, + Package() { 0x0015FFFF, 1, 0, 17 }, + Package() { 0x0015FFFF, 2, 0, 18 }, + Package() { 0x0015FFFF, 3, 0, 19 }, + // [CMS6]: Uncore 5 CMS0CHA16-23 Device + Package() { 0x0016FFFF, 0, 0, 16 }, + Package() { 0x0016FFFF, 1, 0, 17 }, + Package() { 0x0016FFFF, 2, 0, 18 }, + Package() { 0x0016FFFF, 3, 0, 19 }, + // [CMS7]: Uncore 5 CMS0CHA24-27 Device + Package() { 0x0017FFFF, 0, 0, 16 }, + Package() { 0x0017FFFF, 1, 0, 17 }, + Package() { 0x0017FFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 3, 0, 19 }, + // [CDL1]: Uncore 5 CHASADALL Device + Package() { 0x001DFFFF, 0, 0, 16 }, + Package() { 0x001DFFFF, 1, 0, 17 }, + Package() { 0x001DFFFF, 2, 0, 18 }, + Package() { 0x001DFFFF, 3, 0, 19 }, + // [PCU1]: Uncore 5 PCUCR Devices + Package() { 0x001EFFFF, 0, 0, 16 }, + Package() { 0x001EFFFF, 1, 0, 17 }, + Package() { 0x001EFFFF, 2, 0, 18 }, + Package() { 0x001EFFFF, 3, 0, 19 }, + // [VCU1]: Uncore 5 VCUCR Device + Package() { 0x001FFFFF, 0, 0, 16 }, + Package() { 0x001FFFFF, 1, 0, 17 }, + Package() { 0x001FFFFF, 2, 0, 18 }, + Package() { 0x001FFFFF, 3, 0, 19 }, + }) + + Name (AH2F, Package() { + // [QR1A]: PCI Express Port 1A on PC07 + Package() { 0x0000FFFF, 0, 0, 87 }, + // [QR1B]: PCI Express Port 1B on PC07 + Package() { 0x0001FFFF, 0, 0, 87 }, + // [QR1C]: PCI Express Port 1C on PC07 + Package() { 0x0002FFFF, 0, 0, 87 }, + // [QR1D]: PCI Express Port 1D on PC07 + Package() { 0x0003FFFF, 0, 0, 87 }, + // [CHB0]: Uncore 5 CHAUTIL0-7 Device + Package() { 0x0008FFFF, 0, 0, 80 }, + Package() { 0x0008FFFF, 1, 0, 84 }, + Package() { 0x0008FFFF, 2, 0, 85 }, + Package() { 0x0008FFFF, 3, 0, 86 }, + // [CHB1]: Uncore 5 CHAUTIL8-15 Device + Package() { 0x0009FFFF, 0, 0, 80 }, + Package() { 0x0009FFFF, 1, 0, 84 }, + Package() { 0x0009FFFF, 2, 0, 85 }, + Package() { 0x0009FFFF, 3, 0, 86 }, + // [CHB2]: Uncore 5 CHAUTIL16-23 Device + Package() { 0x000AFFFF, 0, 0, 80 }, + Package() { 0x000AFFFF, 1, 0, 84 }, + Package() { 0x000AFFFF, 2, 0, 85 }, + Package() { 0x000AFFFF, 3, 0, 86 }, + // [CHB3]: Uncore 5 CHAUTIL24-27 Device + Package() { 0x000BFFFF, 0, 0, 80 }, + Package() { 0x000BFFFF, 1, 0, 84 }, + Package() { 0x000BFFFF, 2, 0, 85 }, + Package() { 0x000BFFFF, 3, 0, 86 }, + // [CHB4]: Uncore 5 CHASAD0-7 Device + Package() { 0x000EFFFF, 0, 0, 80 }, + Package() { 0x000EFFFF, 1, 0, 84 }, + Package() { 0x000EFFFF, 2, 0, 85 }, + Package() { 0x000EFFFF, 3, 0, 86 }, + // [CHB5]: Uncore 5 CHASAD8-15 Device + Package() { 0x000FFFFF, 0, 0, 80 }, + Package() { 0x000FFFFF, 1, 0, 84 }, + Package() { 0x000FFFFF, 2, 0, 85 }, + Package() { 0x000FFFFF, 3, 0, 86 }, + // [CHB6]: Uncore 5 CHASAD16-23 Device + Package() { 0x0010FFFF, 0, 0, 80 }, + Package() { 0x0010FFFF, 1, 0, 84 }, + Package() { 0x0010FFFF, 2, 0, 85 }, + Package() { 0x0010FFFF, 3, 0, 86 }, + // [CHB7]: Uncore 5 CHASAD24-27 Device + Package() { 0x0011FFFF, 0, 0, 80 }, + Package() { 0x0011FFFF, 1, 0, 84 }, + Package() { 0x0011FFFF, 2, 0, 85 }, + Package() { 0x0011FFFF, 3, 0, 86 }, + // [CMS4]: Uncore 5 CMSCHA0-7 Device + Package() { 0x0014FFFF, 0, 0, 80 }, + Package() { 0x0014FFFF, 1, 0, 84 }, + Package() { 0x0014FFFF, 2, 0, 85 }, + Package() { 0x0014FFFF, 3, 0, 86 }, + // [CMS5]: Uncore 5 CMS0CHA8-15 Device + Package() { 0x0015FFFF, 0, 0, 80 }, + Package() { 0x0015FFFF, 1, 0, 84 }, + Package() { 0x0015FFFF, 2, 0, 85 }, + Package() { 0x0015FFFF, 3, 0, 86 }, + // [CMS6]: Uncore 5 CMS0CHA16-23 Device + Package() { 0x0016FFFF, 0, 0, 80 }, + Package() { 0x0016FFFF, 1, 0, 84 }, + Package() { 0x0016FFFF, 2, 0, 85 }, + Package() { 0x0016FFFF, 3, 0, 86 }, + // [CMS7]: Uncore 5 CMS0CHA24-27 Device + Package() { 0x0017FFFF, 0, 0, 80 }, + Package() { 0x0017FFFF, 1, 0, 84 }, + Package() { 0x0017FFFF, 2, 0, 85 }, + Package() { 0x0017FFFF, 3, 0, 86 }, + // [CDL1]: Uncore 5 CHASADALL Device + Package() { 0x001DFFFF, 0, 0, 80 }, + Package() { 0x001DFFFF, 1, 0, 84 }, + Package() { 0x001DFFFF, 2, 0, 85 }, + Package() { 0x001DFFFF, 3, 0, 86 }, + // [PCU1]: Uncore 5 PCUCR Devices + Package() { 0x001EFFFF, 0, 0, 80 }, + Package() { 0x001EFFFF, 1, 0, 84 }, + Package() { 0x001EFFFF, 2, 0, 85 }, + Package() { 0x001EFFFF, 3, 0, 86 }, + // [VCU1]: Uncore 5 VCUCR Device + Package() { 0x001FFFFF, 0, 0, 80 }, + Package() { 0x001FFFFF, 1, 0, 84 }, + Package() { 0x001FFFFF, 2, 0, 85 }, + Package() { 0x001FFFFF, 3, 0, 86 }, + }) + + Name (PR30, Package() { + // [SL10]: PCI Express Slot 16 on 1A on PC07 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR30, Package() { + // [SL10]: PCI Express Slot 16 on 1A on PC07 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH30, Package() { + // [SL10]: PCI Express Slot 16 on 1A on PC07 + Package() { 0x0000FFFF, 0, 0, 80 }, + Package() { 0x0000FFFF, 1, 0, 84 }, + Package() { 0x0000FFFF, 2, 0, 85 }, + Package() { 0x0000FFFF, 3, 0, 86 }, + }) + + Name (PR31, Package() { + // [SL11]: PCI Express Slot 17 on 1B on PC07 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR31, Package() { + // [SL11]: PCI Express Slot 17 on 1B on PC07 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH31, Package() { + // [SL11]: PCI Express Slot 17 on 1B on PC07 + Package() { 0x0000FFFF, 0, 0, 81 }, + Package() { 0x0000FFFF, 1, 0, 86 }, + Package() { 0x0000FFFF, 2, 0, 84 }, + Package() { 0x0000FFFF, 3, 0, 85 }, + }) + + Name (PR32, Package() { + // [SL12]: PCI Express Slot 18 on 1C on PC07 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR32, Package() { + // [SL12]: PCI Express Slot 18 on 1C on PC07 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH32, Package() { + // [SL12]: PCI Express Slot 18 on 1C on PC07 + Package() { 0x0000FFFF, 0, 0, 82 }, + Package() { 0x0000FFFF, 1, 0, 85 }, + Package() { 0x0000FFFF, 2, 0, 86 }, + Package() { 0x0000FFFF, 3, 0, 84 }, + }) + + Name (PR33, Package() { + // [SL13]: PCI Express Slot 19 on 1D on PC07 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR33, Package() { + // [SL13]: PCI Express Slot 19 on 1D on PC07 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH33, Package() { + // [SL13]: PCI Express Slot 19 on 1D on PC07 + Package() { 0x0000FFFF, 0, 0, 83 }, + Package() { 0x0000FFFF, 1, 0, 86 }, + Package() { 0x0000FFFF, 2, 0, 84 }, + Package() { 0x0000FFFF, 3, 0, 85 }, + }) + + Name (PR34, Package() { + // [QR2A]: PCI Express Port 2A on PC08 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [QR2B]: PCI Express Port 2B on PC08 + Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [QR2C]: PCI Express Port 2C on PC08 + Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [QR2D]: PCI Express Port 2D on PC08 + Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [M2M2]: Uncore 6 M2MEM0 Device + Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M2M3]: Uncore 6 M2MEM10 Device + Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCM2]: Uncore 6 MCMAIN Device + Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCD2]: Uncore 6 MCDECS2 Device + Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCM3]: Uncore 6 MCMAIN Device + Package() { 0x000CFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000CFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000CFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000CFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCD3]: Uncore 6 MCDECS12 Device + Package() { 0x000DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [UMC2]: Uncore 6 Unicast MC0 DDRIO0 Device + Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [UMC3]: Uncore 6 Unicast MC1 DDRIO0 Device + Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR34, Package() { + // [QR2A]: PCI Express Port 2A on PC08 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [QR2B]: PCI Express Port 2B on PC08 + Package() { 0x0001FFFF, 0, 0, 16 }, + // [QR2C]: PCI Express Port 2C on PC08 + Package() { 0x0002FFFF, 0, 0, 16 }, + // [QR2D]: PCI Express Port 2D on PC08 + Package() { 0x0003FFFF, 0, 0, 16 }, + // [M2M2]: Uncore 6 M2MEM0 Device + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + // [M2M3]: Uncore 6 M2MEM10 Device + Package() { 0x0009FFFF, 0, 0, 16 }, + Package() { 0x0009FFFF, 1, 0, 17 }, + Package() { 0x0009FFFF, 2, 0, 18 }, + Package() { 0x0009FFFF, 3, 0, 19 }, + // [MCM2]: Uncore 6 MCMAIN Device + Package() { 0x000AFFFF, 0, 0, 16 }, + Package() { 0x000AFFFF, 1, 0, 17 }, + Package() { 0x000AFFFF, 2, 0, 18 }, + Package() { 0x000AFFFF, 3, 0, 19 }, + // [MCD2]: Uncore 6 MCDECS2 Device + Package() { 0x000BFFFF, 0, 0, 16 }, + Package() { 0x000BFFFF, 1, 0, 17 }, + Package() { 0x000BFFFF, 2, 0, 18 }, + Package() { 0x000BFFFF, 3, 0, 19 }, + // [MCM3]: Uncore 6 MCMAIN Device + Package() { 0x000CFFFF, 0, 0, 16 }, + Package() { 0x000CFFFF, 1, 0, 17 }, + Package() { 0x000CFFFF, 2, 0, 18 }, + Package() { 0x000CFFFF, 3, 0, 19 }, + // [MCD3]: Uncore 6 MCDECS12 Device + Package() { 0x000DFFFF, 0, 0, 16 }, + Package() { 0x000DFFFF, 1, 0, 17 }, + Package() { 0x000DFFFF, 2, 0, 18 }, + Package() { 0x000DFFFF, 3, 0, 19 }, + // [UMC2]: Uncore 6 Unicast MC0 DDRIO0 Device + Package() { 0x0016FFFF, 0, 0, 16 }, + Package() { 0x0016FFFF, 1, 0, 17 }, + Package() { 0x0016FFFF, 2, 0, 18 }, + Package() { 0x0016FFFF, 3, 0, 19 }, + // [UMC3]: Uncore 6 Unicast MC1 DDRIO0 Device + Package() { 0x0017FFFF, 0, 0, 16 }, + Package() { 0x0017FFFF, 1, 0, 17 }, + Package() { 0x0017FFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 3, 0, 19 }, + }) + + Name (AH34, Package() { + // [QR2A]: PCI Express Port 2A on PC08 + Package() { 0x0000FFFF, 0, 0, 95 }, + // [QR2B]: PCI Express Port 2B on PC08 + Package() { 0x0001FFFF, 0, 0, 95 }, + // [QR2C]: PCI Express Port 2C on PC08 + Package() { 0x0002FFFF, 0, 0, 95 }, + // [QR2D]: PCI Express Port 2D on PC08 + Package() { 0x0003FFFF, 0, 0, 95 }, + // [M2M2]: Uncore 6 M2MEM0 Device + Package() { 0x0008FFFF, 0, 0, 88 }, + Package() { 0x0008FFFF, 1, 0, 92 }, + Package() { 0x0008FFFF, 2, 0, 93 }, + Package() { 0x0008FFFF, 3, 0, 94 }, + // [M2M3]: Uncore 6 M2MEM10 Device + Package() { 0x0009FFFF, 0, 0, 88 }, + Package() { 0x0009FFFF, 1, 0, 92 }, + Package() { 0x0009FFFF, 2, 0, 93 }, + Package() { 0x0009FFFF, 3, 0, 94 }, + // [MCM2]: Uncore 6 MCMAIN Device + Package() { 0x000AFFFF, 0, 0, 88 }, + Package() { 0x000AFFFF, 1, 0, 92 }, + Package() { 0x000AFFFF, 2, 0, 93 }, + Package() { 0x000AFFFF, 3, 0, 94 }, + // [MCD2]: Uncore 6 MCDECS2 Device + Package() { 0x000BFFFF, 0, 0, 88 }, + Package() { 0x000BFFFF, 1, 0, 92 }, + Package() { 0x000BFFFF, 2, 0, 93 }, + Package() { 0x000BFFFF, 3, 0, 94 }, + // [MCM3]: Uncore 6 MCMAIN Device + Package() { 0x000CFFFF, 0, 0, 88 }, + Package() { 0x000CFFFF, 1, 0, 92 }, + Package() { 0x000CFFFF, 2, 0, 93 }, + Package() { 0x000CFFFF, 3, 0, 94 }, + // [MCD3]: Uncore 6 MCDECS12 Device + Package() { 0x000DFFFF, 0, 0, 88 }, + Package() { 0x000DFFFF, 1, 0, 92 }, + Package() { 0x000DFFFF, 2, 0, 93 }, + Package() { 0x000DFFFF, 3, 0, 94 }, + // [UMC2]: Uncore 6 Unicast MC0 DDRIO0 Device + Package() { 0x0016FFFF, 0, 0, 88 }, + Package() { 0x0016FFFF, 1, 0, 92 }, + Package() { 0x0016FFFF, 2, 0, 93 }, + Package() { 0x0016FFFF, 3, 0, 94 }, + // [UMC3]: Uncore 6 Unicast MC1 DDRIO0 Device + Package() { 0x0017FFFF, 0, 0, 88 }, + Package() { 0x0017FFFF, 1, 0, 92 }, + Package() { 0x0017FFFF, 2, 0, 93 }, + Package() { 0x0017FFFF, 3, 0, 94 }, + }) + + Name (PR35, Package() { + // [SL14]: PCI Express Slot 20 on 2A on PC08 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR35, Package() { + // [SL14]: PCI Express Slot 20 on 2A on PC08 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH35, Package() { + // [SL14]: PCI Express Slot 20 on 2A on PC08 + Package() { 0x0000FFFF, 0, 0, 88 }, + Package() { 0x0000FFFF, 1, 0, 92 }, + Package() { 0x0000FFFF, 2, 0, 93 }, + Package() { 0x0000FFFF, 3, 0, 94 }, + }) + + Name (PR36, Package() { + // [SL15]: PCI Express Slot 21 on 2B on PC08 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR36, Package() { + // [SL15]: PCI Express Slot 21 on 2B on PC08 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH36, Package() { + // [SL15]: PCI Express Slot 21 on 2B on PC08 + Package() { 0x0000FFFF, 0, 0, 89 }, + Package() { 0x0000FFFF, 1, 0, 94 }, + Package() { 0x0000FFFF, 2, 0, 92 }, + Package() { 0x0000FFFF, 3, 0, 93 }, + }) + + Name (PR37, Package() { + // [SL16]: PCI Express Slot 22 on 2C on PC08 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR37, Package() { + // [SL16]: PCI Express Slot 22 on 2C on PC08 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH37, Package() { + // [SL16]: PCI Express Slot 22 on 2C on PC08 + Package() { 0x0000FFFF, 0, 0, 90 }, + Package() { 0x0000FFFF, 1, 0, 93 }, + Package() { 0x0000FFFF, 2, 0, 94 }, + Package() { 0x0000FFFF, 3, 0, 92 }, + }) + + Name (PR38, Package() { + // [SL17]: PCI Express Slot 23 on 2D on PC08 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR38, Package() { + // [SL17]: PCI Express Slot 23 on 2D on PC08 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH38, Package() { + // [SL17]: PCI Express Slot 23 on 2D on PC08 + Package() { 0x0000FFFF, 0, 0, 91 }, + Package() { 0x0000FFFF, 1, 0, 94 }, + Package() { 0x0000FFFF, 2, 0, 92 }, + Package() { 0x0000FFFF, 3, 0, 93 }, + }) + + Name (PR39, Package() { + // [QR3A]: PCI Express Port 3A on PC09 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [QR3B]: PCI Express Port 3B on PC09 + Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [QR3C]: PCI Express Port 3C on PC09 + Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [QR3D]: PCI Express Port 3D on PC09 + Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [KTI3]: Uncore 7 KTI3 + Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [KTI4]: Uncore 7 KTI4 + Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [KTI5]: Uncore 7 KTI5 + Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M3K1]: Uncore 7 M3K1 + Package() { 0x0012FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0012FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0012FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0012FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M2U1]: Uncore 7 M2U1 + Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M2D1]: Uncore 7 M2D1 + Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M21]: Uncore 7 M21 + Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR39, Package() { + // [QR3A]: PCI Express Port 3A on PC09 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [QR3B]: PCI Express Port 3B on PC09 + Package() { 0x0001FFFF, 0, 0, 16 }, + // [QR3C]: PCI Express Port 3C on PC09 + Package() { 0x0002FFFF, 0, 0, 16 }, + // [QR3D]: PCI Express Port 3D on PC09 + Package() { 0x0003FFFF, 0, 0, 16 }, + // [KTI3]: Uncore 7 KTI3 + Package() { 0x000EFFFF, 0, 0, 16 }, + Package() { 0x000EFFFF, 1, 0, 17 }, + Package() { 0x000EFFFF, 2, 0, 18 }, + Package() { 0x000EFFFF, 3, 0, 19 }, + // [KTI4]: Uncore 7 KTI4 + Package() { 0x000FFFFF, 0, 0, 16 }, + Package() { 0x000FFFFF, 1, 0, 17 }, + Package() { 0x000FFFFF, 2, 0, 18 }, + Package() { 0x000FFFFF, 3, 0, 19 }, + // [KTI5]: Uncore 7 KTI5 + Package() { 0x0010FFFF, 0, 0, 16 }, + Package() { 0x0010FFFF, 1, 0, 17 }, + Package() { 0x0010FFFF, 2, 0, 18 }, + Package() { 0x0010FFFF, 3, 0, 19 }, + // [M3K1]: Uncore 7 M3K1 + Package() { 0x0012FFFF, 0, 0, 16 }, + Package() { 0x0012FFFF, 1, 0, 17 }, + Package() { 0x0012FFFF, 2, 0, 18 }, + Package() { 0x0012FFFF, 3, 0, 19 }, + // [M2U1]: Uncore 7 M2U1 + Package() { 0x0015FFFF, 0, 0, 16 }, + Package() { 0x0015FFFF, 1, 0, 17 }, + Package() { 0x0015FFFF, 2, 0, 18 }, + Package() { 0x0015FFFF, 3, 0, 19 }, + // [M2D1]: Uncore 7 M2D1 + Package() { 0x0016FFFF, 0, 0, 16 }, + Package() { 0x0016FFFF, 1, 0, 17 }, + Package() { 0x0016FFFF, 2, 0, 18 }, + Package() { 0x0016FFFF, 3, 0, 19 }, + // [M21]: Uncore 7 M21 + Package() { 0x0017FFFF, 0, 0, 16 }, + Package() { 0x0017FFFF, 1, 0, 17 }, + Package() { 0x0017FFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 3, 0, 19 }, + }) + + Name (AH39, Package() { + // [QR3A]: PCI Express Port 3A on PC09 + Package() { 0x0000FFFF, 0, 0, 103 }, + // [QR3B]: PCI Express Port 3B on PC09 + Package() { 0x0001FFFF, 0, 0, 103 }, + // [QR3C]: PCI Express Port 3C on PC09 + Package() { 0x0002FFFF, 0, 0, 103 }, + // [QR3D]: PCI Express Port 3D on PC09 + Package() { 0x0003FFFF, 0, 0, 103 }, + // [KTI3]: Uncore 7 KTI3 + Package() { 0x000EFFFF, 0, 0, 96 }, + Package() { 0x000EFFFF, 1, 0, 100 }, + Package() { 0x000EFFFF, 2, 0, 101 }, + Package() { 0x000EFFFF, 3, 0, 102 }, + // [KTI4]: Uncore 7 KTI4 + Package() { 0x000FFFFF, 0, 0, 96 }, + Package() { 0x000FFFFF, 1, 0, 100 }, + Package() { 0x000FFFFF, 2, 0, 101 }, + Package() { 0x000FFFFF, 3, 0, 102 }, + // [KTI5]: Uncore 7 KTI5 + Package() { 0x0010FFFF, 0, 0, 96 }, + Package() { 0x0010FFFF, 1, 0, 100 }, + Package() { 0x0010FFFF, 2, 0, 101 }, + Package() { 0x0010FFFF, 3, 0, 102 }, + // [M3K1]: Uncore 7 M3K1 + Package() { 0x0012FFFF, 0, 0, 96 }, + Package() { 0x0012FFFF, 1, 0, 100 }, + Package() { 0x0012FFFF, 2, 0, 101 }, + Package() { 0x0012FFFF, 3, 0, 102 }, + // [M2U1]: Uncore 7 M2U1 + Package() { 0x0015FFFF, 0, 0, 96 }, + Package() { 0x0015FFFF, 1, 0, 100 }, + Package() { 0x0015FFFF, 2, 0, 101 }, + Package() { 0x0015FFFF, 3, 0, 102 }, + // [M2D1]: Uncore 7 M2D1 + Package() { 0x0016FFFF, 0, 0, 96 }, + Package() { 0x0016FFFF, 1, 0, 100 }, + Package() { 0x0016FFFF, 2, 0, 101 }, + Package() { 0x0016FFFF, 3, 0, 102 }, + // [M21]: Uncore 7 M21 + Package() { 0x0017FFFF, 0, 0, 96 }, + Package() { 0x0017FFFF, 1, 0, 100 }, + Package() { 0x0017FFFF, 2, 0, 101 }, + Package() { 0x0017FFFF, 3, 0, 102 }, + }) + + Name (PR3A, Package() { + // [SL18]: PCI Express Slot 24 on 3A on PC09 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR3A, Package() { + // [SL18]: PCI Express Slot 24 on 3A on PC09 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH3A, Package() { + // [SL18]: PCI Express Slot 24 on 3A on PC09 + Package() { 0x0000FFFF, 0, 0, 96 }, + Package() { 0x0000FFFF, 1, 0, 100 }, + Package() { 0x0000FFFF, 2, 0, 101 }, + Package() { 0x0000FFFF, 3, 0, 102 }, + }) + + Name (PR3B, Package() { + // [SL19]: PCI Express Slot 25 on 3B on PC09 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR3B, Package() { + // [SL19]: PCI Express Slot 25 on 3B on PC09 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH3B, Package() { + // [SL19]: PCI Express Slot 25 on 3B on PC09 + Package() { 0x0000FFFF, 0, 0, 97 }, + Package() { 0x0000FFFF, 1, 0, 102 }, + Package() { 0x0000FFFF, 2, 0, 100 }, + Package() { 0x0000FFFF, 3, 0, 101 }, + }) + + Name (PR3C, Package() { + // [SL1A]: PCI Express Slot 26 on 3C on PC09 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR3C, Package() { + // [SL1A]: PCI Express Slot 26 on 3C on PC09 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH3C, Package() { + // [SL1A]: PCI Express Slot 26 on 3C on PC09 + Package() { 0x0000FFFF, 0, 0, 98 }, + Package() { 0x0000FFFF, 1, 0, 101 }, + Package() { 0x0000FFFF, 2, 0, 102 }, + Package() { 0x0000FFFF, 3, 0, 100 }, + }) + + Name (PR3D, Package() { + // [SL1B]: PCI Express Slot 27 on 3D on PC09 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR3D, Package() { + // [SL1B]: PCI Express Slot 27 on 3D on PC09 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH3D, Package() { + // [SL1B]: PCI Express Slot 27 on 3D on PC09 + Package() { 0x0000FFFF, 0, 0, 99 }, + Package() { 0x0000FFFF, 1, 0, 102 }, + Package() { 0x0000FFFF, 2, 0, 100 }, + Package() { 0x0000FFFF, 3, 0, 101 }, + }) + + Name (PR3E, Package() { + // [MCP2]: PCI Express Port 13 on PC10 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR3E, Package() { + // [MCP2]: PCI Express Port 13 on PC10 + Package() { 0x0000FFFF, 0, 0, 16 }, + }) + + Name (AH3E, Package() { + // [MCP2]: PCI Express Port 13 on PC10 + Package() { 0x0000FFFF, 0, 0, 111 }, + }) + + Name (PR3F, Package() { + // [SL1C]: PCI Express Slot 28 on 4 on PC10 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR3F, Package() { + // [SL1C]: PCI Express Slot 28 on 4 on PC10 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH3F, Package() { + // [SL1C]: PCI Express Slot 28 on 4 on PC10 + Package() { 0x0000FFFF, 0, 0, 104 }, + Package() { 0x0000FFFF, 1, 0, 108 }, + Package() { 0x0000FFFF, 2, 0, 109 }, + Package() { 0x0000FFFF, 3, 0, 110 }, + }) + + Name (PR40, Package() { + // [MCP3]: PCI Express Port 14 on PC11 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR40, Package() { + // [MCP3]: PCI Express Port 14 on PC11 + Package() { 0x0000FFFF, 0, 0, 16 }, + }) + + Name (AH40, Package() { + // [MCP3]: PCI Express Port 14 on PC11 + Package() { 0x0000FFFF, 0, 0, 119 }, + }) + + Name (PR41, Package() { + // [SL1D]: PCI Express Slot 29 on 5 on PC11 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR41, Package() { + // [SL1D]: PCI Express Slot 29 on 5 on PC11 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH41, Package() { + // [SL1D]: PCI Express Slot 29 on 5 on PC11 + Package() { 0x0000FFFF, 0, 0, 112 }, + Package() { 0x0000FFFF, 1, 0, 116 }, + Package() { 0x0000FFFF, 2, 0, 117 }, + Package() { 0x0000FFFF, 3, 0, 118 }, + }) + + Name (PR42, Package() { + // [RRP0]: PCI Express Port 0 on PC12 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [CB2B]: CB3DMA on PC12 + // [CB2F]: CB3DMA on PC12 + Package() { 0x0004FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + // [CB2C]: CB3DMA on PC12 + // [CB2G]: CB3DMA on PC12 + Package() { 0x0004FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + // [CB2D]: CB3DMA on PC12 + // [CB2H]: CB3DMA on PC12 + Package() { 0x0004FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CB2E]: CB3DMA on PC12 + // [CB2A]: CB3DMA on PC12 + Package() { 0x0004FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [IIM2]: IIOMISC on PC02 + Package() { 0x0005FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0005FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0005FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0005FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [UBX2]: Uncore 8 UBOX Device + Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR42, Package() { + // [RRP0]: PCI Express Port 0 on PC12 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [CB2B]: CB3DMA on PC12 + // [CB2F]: CB3DMA on PC12 + Package() { 0x0004FFFF, 1, 0, 17 }, + // [CB2C]: CB3DMA on PC12 + // [CB2G]: CB3DMA on PC12 + Package() { 0x0004FFFF, 2, 0, 18 }, + // [CB2D]: CB3DMA on PC12 + // [CB2H]: CB3DMA on PC12 + Package() { 0x0004FFFF, 3, 0, 19 }, + // [CB2E]: CB3DMA on PC12 + // [CB2A]: CB3DMA on PC12 + Package() { 0x0004FFFF, 0, 0, 16 }, + // [IIM2]: IIOMISC on PC02 + Package() { 0x0005FFFF, 0, 0, 16 }, + Package() { 0x0005FFFF, 1, 0, 17 }, + Package() { 0x0005FFFF, 2, 0, 18 }, + Package() { 0x0005FFFF, 3, 0, 19 }, + // [UBX2]: Uncore 8 UBOX Device + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + }) + + Name (AH42, Package() { + // [RRP0]: PCI Express Port 0 on PC12 + Package() { 0x0000FFFF, 0, 0, 127 }, + // [CB2B]: CB3DMA on PC12 + // [CB2F]: CB3DMA on PC12 + Package() { 0x0004FFFF, 1, 0, 123 }, + // [CB2C]: CB3DMA on PC12 + // [CB2G]: CB3DMA on PC12 + Package() { 0x0004FFFF, 2, 0, 122 }, + // [CB2D]: CB3DMA on PC12 + // [CB2H]: CB3DMA on PC12 + Package() { 0x0004FFFF, 3, 0, 123 }, + // [CB2E]: CB3DMA on PC12 + // [CB2A]: CB3DMA on PC12 + Package() { 0x0004FFFF, 0, 0, 122 }, + // [IIM2]: IIOMISC on PC02 + Package() { 0x0005FFFF, 0, 0, 16 }, + Package() { 0x0005FFFF, 1, 0, 17 }, + Package() { 0x0005FFFF, 2, 0, 18 }, + Package() { 0x0005FFFF, 3, 0, 19 }, + // [UBX2]: Uncore 8 UBOX Device + Package() { 0x0008FFFF, 0, 0, 120 }, + Package() { 0x0008FFFF, 1, 0, 124 }, + Package() { 0x0008FFFF, 2, 0, 125 }, + Package() { 0x0008FFFF, 3, 0, 126 }, + }) + + Name (PR43, Package() { + // [SL1E]: PCI Express Slot 30 on P0 on PC12 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR43, Package() { + // [SL1E]: PCI Express Slot 30 on P0 on PC12 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH43, Package() { + // [SL1E]: PCI Express Slot 30 on P0 on PC12 + Package() { 0x0000FFFF, 0, 0, 120 }, + Package() { 0x0000FFFF, 1, 0, 124 }, + Package() { 0x0000FFFF, 2, 0, 125 }, + Package() { 0x0000FFFF, 3, 0, 126 }, + }) + + Name (PR44, Package() { + // [RR1A]: PCI Express Port 1A on PC13 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [RR1B]: PCI Express Port 1B on PC13 + Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [RR1C]: PCI Express Port 1C on PC13 + Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [RR1D]: PCI Express Port 1D on PC13 + Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [CHC0]: Uncore 9 CHAUTIL0-7 Device + Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHC1]: Uncore 9 CHAUTIL8-15 Device + Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHC2]: Uncore 9 CHAUTIL16-23 Device + Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHC3]: Uncore 9 CHAUTIL24-27 Device + Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHC4]: Uncore 9 CHASAD0-7 Device + Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHC5]: Uncore 9 CHASAD8-15 Device + Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHC6]: Uncore 9 CHASAD16-23 Device + Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHC7]: Uncore 9 CHASAD24-27 Device + Package() { 0x0011FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0011FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0011FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0011FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CMS8]: Uncore 9 CMSCHA0-7 Device + Package() { 0x0014FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0014FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0014FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0014FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CMS9]: Uncore 9 CMS0CHA8-15 Device + Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CDL2]: Uncore 9 CHASADALL Device + Package() { 0x001DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x001DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x001DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x001DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [PCU2]: Uncore 9 PCUCR Devices + Package() { 0x001EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x001EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x001EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x001EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [VCU2]: Uncore 9 VCUCR Device + Package() { 0x001FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x001FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x001FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x001FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR44, Package() { + // [RR1A]: PCI Express Port 1A on PC13 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [RR1B]: PCI Express Port 1B on PC13 + Package() { 0x0001FFFF, 0, 0, 16 }, + // [RR1C]: PCI Express Port 1C on PC13 + Package() { 0x0002FFFF, 0, 0, 16 }, + // [RR1D]: PCI Express Port 1D on PC13 + Package() { 0x0003FFFF, 0, 0, 16 }, + // [CHC0]: Uncore 9 CHAUTIL0-7 Device + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + // [CHC1]: Uncore 9 CHAUTIL8-15 Device + Package() { 0x0009FFFF, 0, 0, 16 }, + Package() { 0x0009FFFF, 1, 0, 17 }, + Package() { 0x0009FFFF, 2, 0, 18 }, + Package() { 0x0009FFFF, 3, 0, 19 }, + // [CHC2]: Uncore 9 CHAUTIL16-23 Device + Package() { 0x000AFFFF, 0, 0, 16 }, + Package() { 0x000AFFFF, 1, 0, 17 }, + Package() { 0x000AFFFF, 2, 0, 18 }, + Package() { 0x000AFFFF, 3, 0, 19 }, + // [CHC3]: Uncore 9 CHAUTIL24-27 Device + Package() { 0x000BFFFF, 0, 0, 16 }, + Package() { 0x000BFFFF, 1, 0, 17 }, + Package() { 0x000BFFFF, 2, 0, 18 }, + Package() { 0x000BFFFF, 3, 0, 19 }, + // [CHC4]: Uncore 9 CHASAD0-7 Device + Package() { 0x000EFFFF, 0, 0, 16 }, + Package() { 0x000EFFFF, 1, 0, 17 }, + Package() { 0x000EFFFF, 2, 0, 18 }, + Package() { 0x000EFFFF, 3, 0, 19 }, + // [CHC5]: Uncore 9 CHASAD8-15 Device + Package() { 0x000FFFFF, 0, 0, 16 }, + Package() { 0x000FFFFF, 1, 0, 17 }, + Package() { 0x000FFFFF, 2, 0, 18 }, + Package() { 0x000FFFFF, 3, 0, 19 }, + // [CHC6]: Uncore 9 CHASAD16-23 Device + Package() { 0x0010FFFF, 0, 0, 16 }, + Package() { 0x0010FFFF, 1, 0, 17 }, + Package() { 0x0010FFFF, 2, 0, 18 }, + Package() { 0x0010FFFF, 3, 0, 19 }, + // [CHC7]: Uncore 9 CHASAD24-27 Device + Package() { 0x0011FFFF, 0, 0, 16 }, + Package() { 0x0011FFFF, 1, 0, 17 }, + Package() { 0x0011FFFF, 2, 0, 18 }, + Package() { 0x0011FFFF, 3, 0, 19 }, + // [CMS8]: Uncore 9 CMSCHA0-7 Device + Package() { 0x0014FFFF, 0, 0, 16 }, + Package() { 0x0014FFFF, 1, 0, 17 }, + Package() { 0x0014FFFF, 2, 0, 18 }, + Package() { 0x0014FFFF, 3, 0, 19 }, + // [CMS9]: Uncore 9 CMS0CHA8-15 Device + Package() { 0x0015FFFF, 0, 0, 16 }, + Package() { 0x0015FFFF, 1, 0, 17 }, + Package() { 0x0015FFFF, 2, 0, 18 }, + Package() { 0x0015FFFF, 3, 0, 19 }, + // [CDL2]: Uncore 9 CHASADALL Device + Package() { 0x001DFFFF, 0, 0, 16 }, + Package() { 0x001DFFFF, 1, 0, 17 }, + Package() { 0x001DFFFF, 2, 0, 18 }, + Package() { 0x001DFFFF, 3, 0, 19 }, + // [PCU2]: Uncore 9 PCUCR Devices + Package() { 0x001EFFFF, 0, 0, 16 }, + Package() { 0x001EFFFF, 1, 0, 17 }, + Package() { 0x001EFFFF, 2, 0, 18 }, + Package() { 0x001EFFFF, 3, 0, 19 }, + // [VCU2]: Uncore 9 VCUCR Device + Package() { 0x001FFFFF, 0, 0, 16 }, + Package() { 0x001FFFFF, 1, 0, 17 }, + Package() { 0x001FFFFF, 2, 0, 18 }, + Package() { 0x001FFFFF, 3, 0, 19 }, + }) + + Name (AH44, Package() { + // [RR1A]: PCI Express Port 1A on PC13 + Package() { 0x0000FFFF, 0, 0, 135 }, + // [RR1B]: PCI Express Port 1B on PC13 + Package() { 0x0001FFFF, 0, 0, 135 }, + // [RR1C]: PCI Express Port 1C on PC13 + Package() { 0x0002FFFF, 0, 0, 135 }, + // [RR1D]: PCI Express Port 1D on PC13 + Package() { 0x0003FFFF, 0, 0, 135 }, + // [CHC0]: Uncore 9 CHAUTIL0-7 Device + Package() { 0x0008FFFF, 0, 0, 128 }, + Package() { 0x0008FFFF, 1, 0, 132 }, + Package() { 0x0008FFFF, 2, 0, 133 }, + Package() { 0x0008FFFF, 3, 0, 134 }, + // [CHC1]: Uncore 9 CHAUTIL8-15 Device + Package() { 0x0009FFFF, 0, 0, 128 }, + Package() { 0x0009FFFF, 1, 0, 132 }, + Package() { 0x0009FFFF, 2, 0, 133 }, + Package() { 0x0009FFFF, 3, 0, 134 }, + // [CHC2]: Uncore 9 CHAUTIL16-23 Device + Package() { 0x000AFFFF, 0, 0, 128 }, + Package() { 0x000AFFFF, 1, 0, 132 }, + Package() { 0x000AFFFF, 2, 0, 133 }, + Package() { 0x000AFFFF, 3, 0, 134 }, + // [CHC3]: Uncore 9 CHAUTIL24-27 Device + Package() { 0x000BFFFF, 0, 0, 128 }, + Package() { 0x000BFFFF, 1, 0, 132 }, + Package() { 0x000BFFFF, 2, 0, 133 }, + Package() { 0x000BFFFF, 3, 0, 134 }, + // [CHC4]: Uncore 9 CHASAD0-7 Device + Package() { 0x000EFFFF, 0, 0, 128 }, + Package() { 0x000EFFFF, 1, 0, 132 }, + Package() { 0x000EFFFF, 2, 0, 133 }, + Package() { 0x000EFFFF, 3, 0, 134 }, + // [CHC5]: Uncore 9 CHASAD8-15 Device + Package() { 0x000FFFFF, 0, 0, 128 }, + Package() { 0x000FFFFF, 1, 0, 132 }, + Package() { 0x000FFFFF, 2, 0, 133 }, + Package() { 0x000FFFFF, 3, 0, 134 }, + // [CHC6]: Uncore 9 CHASAD16-23 Device + Package() { 0x0010FFFF, 0, 0, 128 }, + Package() { 0x0010FFFF, 1, 0, 132 }, + Package() { 0x0010FFFF, 2, 0, 133 }, + Package() { 0x0010FFFF, 3, 0, 134 }, + // [CHC7]: Uncore 9 CHASAD24-27 Device + Package() { 0x0011FFFF, 0, 0, 128 }, + Package() { 0x0011FFFF, 1, 0, 132 }, + Package() { 0x0011FFFF, 2, 0, 133 }, + Package() { 0x0011FFFF, 3, 0, 134 }, + // [CMS8]: Uncore 9 CMSCHA0-7 Device + Package() { 0x0014FFFF, 0, 0, 128 }, + Package() { 0x0014FFFF, 1, 0, 132 }, + Package() { 0x0014FFFF, 2, 0, 133 }, + Package() { 0x0014FFFF, 3, 0, 134 }, + // [CMS9]: Uncore 9 CMS0CHA8-15 Device + Package() { 0x0015FFFF, 0, 0, 128 }, + Package() { 0x0015FFFF, 1, 0, 132 }, + Package() { 0x0015FFFF, 2, 0, 133 }, + Package() { 0x0015FFFF, 3, 0, 134 }, + // [CDL2]: Uncore 9 CHASADALL Device + Package() { 0x001DFFFF, 0, 0, 128 }, + Package() { 0x001DFFFF, 1, 0, 132 }, + Package() { 0x001DFFFF, 2, 0, 133 }, + Package() { 0x001DFFFF, 3, 0, 134 }, + // [PCU2]: Uncore 9 PCUCR Devices + Package() { 0x001EFFFF, 0, 0, 128 }, + Package() { 0x001EFFFF, 1, 0, 132 }, + Package() { 0x001EFFFF, 2, 0, 133 }, + Package() { 0x001EFFFF, 3, 0, 134 }, + // [VCU2]: Uncore 9 VCUCR Device + Package() { 0x001FFFFF, 0, 0, 128 }, + Package() { 0x001FFFFF, 1, 0, 132 }, + Package() { 0x001FFFFF, 2, 0, 133 }, + Package() { 0x001FFFFF, 3, 0, 134 }, + }) + + Name (PR45, Package() { + // [SL1F]: PCI Express Slot 31 on 1A on PC13 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR45, Package() { + // [SL1F]: PCI Express Slot 31 on 1A on PC13 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH45, Package() { + // [SL1F]: PCI Express Slot 31 on 1A on PC13 + Package() { 0x0000FFFF, 0, 0, 128 }, + Package() { 0x0000FFFF, 1, 0, 132 }, + Package() { 0x0000FFFF, 2, 0, 133 }, + Package() { 0x0000FFFF, 3, 0, 134 }, + }) + + Name (PR46, Package() { + // [SL20]: PCI Express Slot 32 on 1B on PC13 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR46, Package() { + // [SL20]: PCI Express Slot 32 on 1B on PC13 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH46, Package() { + // [SL20]: PCI Express Slot 32 on 1B on PC13 + Package() { 0x0000FFFF, 0, 0, 129 }, + Package() { 0x0000FFFF, 1, 0, 134 }, + Package() { 0x0000FFFF, 2, 0, 132 }, + Package() { 0x0000FFFF, 3, 0, 133 }, + }) + + Name (PR47, Package() { + // [SL21]: PCI Express Slot 33 on 1C on PC13 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR47, Package() { + // [SL21]: PCI Express Slot 33 on 1C on PC13 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH47, Package() { + // [SL21]: PCI Express Slot 33 on 1C on PC13 + Package() { 0x0000FFFF, 0, 0, 130 }, + Package() { 0x0000FFFF, 1, 0, 133 }, + Package() { 0x0000FFFF, 2, 0, 134 }, + Package() { 0x0000FFFF, 3, 0, 132 }, + }) + + Name (PR48, Package() { + // [SL22]: PCI Express Slot 34 on 1D on PC13 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR48, Package() { + // [SL22]: PCI Express Slot 34 on 1D on PC13 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH48, Package() { + // [SL22]: PCI Express Slot 34 on 1D on PC13 + Package() { 0x0000FFFF, 0, 0, 131 }, + Package() { 0x0000FFFF, 1, 0, 134 }, + Package() { 0x0000FFFF, 2, 0, 132 }, + Package() { 0x0000FFFF, 3, 0, 133 }, + }) + + Name (PR49, Package() { + // [RR2A]: PCI Express Port 2A on PC14 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [RR2B]: PCI Express Port 2B on PC14 + Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [RR2C]: PCI Express Port 2C on PC14 + Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [RR2D]: PCI Express Port 2D on PC14 + Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [M2M4]: Uncore 10 M2MEM0 Device + Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M2M5]: Uncore 10 M2MEM10 Device + Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCM4]: Uncore 10 MCMAIN Device + Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCD4]: Uncore 10 MCDECS2 Device + Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCM5]: Uncore 10 MCMAIN Device + Package() { 0x000CFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000CFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000CFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000CFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCD5]: Uncore 10 MCDECS12 Device + Package() { 0x000DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [UMC4]: Uncore 10 Unicast MC0 DDRIO0 Device + Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [UMC5]: Uncore 10 Unicast MC1 DDRIO0 Device + Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR49, Package() { + // [RR2A]: PCI Express Port 2A on PC14 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [RR2B]: PCI Express Port 2B on PC14 + Package() { 0x0001FFFF, 0, 0, 16 }, + // [RR2C]: PCI Express Port 2C on PC14 + Package() { 0x0002FFFF, 0, 0, 16 }, + // [RR2D]: PCI Express Port 2D on PC14 + Package() { 0x0003FFFF, 0, 0, 16 }, + // [M2M4]: Uncore 10 M2MEM0 Device + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + // [M2M5]: Uncore 10 M2MEM10 Device + Package() { 0x0009FFFF, 0, 0, 16 }, + Package() { 0x0009FFFF, 1, 0, 17 }, + Package() { 0x0009FFFF, 2, 0, 18 }, + Package() { 0x0009FFFF, 3, 0, 19 }, + // [MCM4]: Uncore 10 MCMAIN Device + Package() { 0x000AFFFF, 0, 0, 16 }, + Package() { 0x000AFFFF, 1, 0, 17 }, + Package() { 0x000AFFFF, 2, 0, 18 }, + Package() { 0x000AFFFF, 3, 0, 19 }, + // [MCD4]: Uncore 10 MCDECS2 Device + Package() { 0x000BFFFF, 0, 0, 16 }, + Package() { 0x000BFFFF, 1, 0, 17 }, + Package() { 0x000BFFFF, 2, 0, 18 }, + Package() { 0x000BFFFF, 3, 0, 19 }, + // [MCM5]: Uncore 10 MCMAIN Device + Package() { 0x000CFFFF, 0, 0, 16 }, + Package() { 0x000CFFFF, 1, 0, 17 }, + Package() { 0x000CFFFF, 2, 0, 18 }, + Package() { 0x000CFFFF, 3, 0, 19 }, + // [MCD5]: Uncore 10 MCDECS12 Device + Package() { 0x000DFFFF, 0, 0, 16 }, + Package() { 0x000DFFFF, 1, 0, 17 }, + Package() { 0x000DFFFF, 2, 0, 18 }, + Package() { 0x000DFFFF, 3, 0, 19 }, + // [UMC4]: Uncore 10 Unicast MC0 DDRIO0 Device + Package() { 0x0016FFFF, 0, 0, 16 }, + Package() { 0x0016FFFF, 1, 0, 17 }, + Package() { 0x0016FFFF, 2, 0, 18 }, + Package() { 0x0016FFFF, 3, 0, 19 }, + // [UMC5]: Uncore 10 Unicast MC1 DDRIO0 Device + Package() { 0x0017FFFF, 0, 0, 16 }, + Package() { 0x0017FFFF, 1, 0, 17 }, + Package() { 0x0017FFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 3, 0, 19 }, + }) + + Name (AH49, Package() { + // [RR2A]: PCI Express Port 2A on PC14 + Package() { 0x0000FFFF, 0, 0, 143 }, + // [RR2B]: PCI Express Port 2B on PC14 + Package() { 0x0001FFFF, 0, 0, 143 }, + // [RR2C]: PCI Express Port 2C on PC14 + Package() { 0x0002FFFF, 0, 0, 143 }, + // [RR2D]: PCI Express Port 2D on PC14 + Package() { 0x0003FFFF, 0, 0, 143 }, + // [M2M4]: Uncore 10 M2MEM0 Device + Package() { 0x0008FFFF, 0, 0, 136 }, + Package() { 0x0008FFFF, 1, 0, 140 }, + Package() { 0x0008FFFF, 2, 0, 141 }, + Package() { 0x0008FFFF, 3, 0, 142 }, + // [M2M5]: Uncore 10 M2MEM10 Device + Package() { 0x0009FFFF, 0, 0, 136 }, + Package() { 0x0009FFFF, 1, 0, 140 }, + Package() { 0x0009FFFF, 2, 0, 141 }, + Package() { 0x0009FFFF, 3, 0, 142 }, + // [MCM4]: Uncore 10 MCMAIN Device + Package() { 0x000AFFFF, 0, 0, 136 }, + Package() { 0x000AFFFF, 1, 0, 140 }, + Package() { 0x000AFFFF, 2, 0, 141 }, + Package() { 0x000AFFFF, 3, 0, 142 }, + // [MCD4]: Uncore 10 MCDECS2 Device + Package() { 0x000BFFFF, 0, 0, 136 }, + Package() { 0x000BFFFF, 1, 0, 140 }, + Package() { 0x000BFFFF, 2, 0, 141 }, + Package() { 0x000BFFFF, 3, 0, 142 }, + // [MCM5]: Uncore 10 MCMAIN Device + Package() { 0x000CFFFF, 0, 0, 136 }, + Package() { 0x000CFFFF, 1, 0, 140 }, + Package() { 0x000CFFFF, 2, 0, 141 }, + Package() { 0x000CFFFF, 3, 0, 142 }, + // [MCD5]: Uncore 10 MCDECS12 Device + Package() { 0x000DFFFF, 0, 0, 136 }, + Package() { 0x000DFFFF, 1, 0, 140 }, + Package() { 0x000DFFFF, 2, 0, 141 }, + Package() { 0x000DFFFF, 3, 0, 142 }, + // [UMC4]: Uncore 10 Unicast MC0 DDRIO0 Device + Package() { 0x0016FFFF, 0, 0, 136 }, + Package() { 0x0016FFFF, 1, 0, 140 }, + Package() { 0x0016FFFF, 2, 0, 141 }, + Package() { 0x0016FFFF, 3, 0, 142 }, + // [UMC5]: Uncore 10 Unicast MC1 DDRIO0 Device + Package() { 0x0017FFFF, 0, 0, 136 }, + Package() { 0x0017FFFF, 1, 0, 140 }, + Package() { 0x0017FFFF, 2, 0, 141 }, + Package() { 0x0017FFFF, 3, 0, 142 }, + }) + + Name (PR4A, Package() { + // [SL23]: PCI Express Slot 35 on 2A on PC14 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR4A, Package() { + // [SL23]: PCI Express Slot 35 on 2A on PC14 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH4A, Package() { + // [SL23]: PCI Express Slot 35 on 2A on PC14 + Package() { 0x0000FFFF, 0, 0, 136 }, + Package() { 0x0000FFFF, 1, 0, 140 }, + Package() { 0x0000FFFF, 2, 0, 141 }, + Package() { 0x0000FFFF, 3, 0, 142 }, + }) + + Name (PR4B, Package() { + // [SL24]: PCI Express Slot 36 on 2B on PC14 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR4B, Package() { + // [SL24]: PCI Express Slot 36 on 2B on PC14 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH4B, Package() { + // [SL24]: PCI Express Slot 36 on 2B on PC14 + Package() { 0x0000FFFF, 0, 0, 137 }, + Package() { 0x0000FFFF, 1, 0, 142 }, + Package() { 0x0000FFFF, 2, 0, 140 }, + Package() { 0x0000FFFF, 3, 0, 141 }, + }) + + Name (PR4C, Package() { + // [SL25]: PCI Express Slot 37 on 2C on PC14 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR4C, Package() { + // [SL25]: PCI Express Slot 37 on 2C on PC14 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH4C, Package() { + // [SL25]: PCI Express Slot 37 on 2C on PC14 + Package() { 0x0000FFFF, 0, 0, 138 }, + Package() { 0x0000FFFF, 1, 0, 141 }, + Package() { 0x0000FFFF, 2, 0, 142 }, + Package() { 0x0000FFFF, 3, 0, 140 }, + }) + + Name (PR4D, Package() { + // [SL26]: PCI Express Slot 38 on 2D on PC14 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR4D, Package() { + // [SL26]: PCI Express Slot 38 on 2D on PC14 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH4D, Package() { + // [SL26]: PCI Express Slot 38 on 2D on PC14 + Package() { 0x0000FFFF, 0, 0, 139 }, + Package() { 0x0000FFFF, 1, 0, 142 }, + Package() { 0x0000FFFF, 2, 0, 140 }, + Package() { 0x0000FFFF, 3, 0, 141 }, + }) + + Name (PR4E, Package() { + // [RR3A]: PCI Express Port 3A on PC15 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [RR3B]: PCI Express Port 3B on PC15 + Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [RR3C]: PCI Express Port 3C on PC15 + Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [RR3D]: PCI Express Port 3D on PC15 + Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [KTI6]: Uncore 11 KTI6 + Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [KTI7]: Uncore 11 KTI7 + Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [KTI8]: Uncore 11 KTI8 + Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M3K2]: Uncore 11 M3K2 + Package() { 0x0012FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0012FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0012FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0012FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M2U2]: Uncore 11 M2U2 + Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M2D2]: Uncore 11 M2D2 + Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M22]: Uncore 11 M22 + Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR4E, Package() { + // [RR3A]: PCI Express Port 3A on PC15 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [RR3B]: PCI Express Port 3B on PC15 + Package() { 0x0001FFFF, 0, 0, 16 }, + // [RR3C]: PCI Express Port 3C on PC15 + Package() { 0x0002FFFF, 0, 0, 16 }, + // [RR3D]: PCI Express Port 3D on PC15 + Package() { 0x0003FFFF, 0, 0, 16 }, + // [KTI6]: Uncore 11 KTI6 + Package() { 0x000EFFFF, 0, 0, 16 }, + Package() { 0x000EFFFF, 1, 0, 17 }, + Package() { 0x000EFFFF, 2, 0, 18 }, + Package() { 0x000EFFFF, 3, 0, 19 }, + // [KTI7]: Uncore 11 KTI7 + Package() { 0x000FFFFF, 0, 0, 16 }, + Package() { 0x000FFFFF, 1, 0, 17 }, + Package() { 0x000FFFFF, 2, 0, 18 }, + Package() { 0x000FFFFF, 3, 0, 19 }, + // [KTI8]: Uncore 11 KTI8 + Package() { 0x0010FFFF, 0, 0, 16 }, + Package() { 0x0010FFFF, 1, 0, 17 }, + Package() { 0x0010FFFF, 2, 0, 18 }, + Package() { 0x0010FFFF, 3, 0, 19 }, + // [M3K2]: Uncore 11 M3K2 + Package() { 0x0012FFFF, 0, 0, 16 }, + Package() { 0x0012FFFF, 1, 0, 17 }, + Package() { 0x0012FFFF, 2, 0, 18 }, + Package() { 0x0012FFFF, 3, 0, 19 }, + // [M2U2]: Uncore 11 M2U2 + Package() { 0x0015FFFF, 0, 0, 16 }, + Package() { 0x0015FFFF, 1, 0, 17 }, + Package() { 0x0015FFFF, 2, 0, 18 }, + Package() { 0x0015FFFF, 3, 0, 19 }, + // [M2D2]: Uncore 11 M2D2 + Package() { 0x0016FFFF, 0, 0, 16 }, + Package() { 0x0016FFFF, 1, 0, 17 }, + Package() { 0x0016FFFF, 2, 0, 18 }, + Package() { 0x0016FFFF, 3, 0, 19 }, + // [M22]: Uncore 11 M22 + Package() { 0x0017FFFF, 0, 0, 16 }, + Package() { 0x0017FFFF, 1, 0, 17 }, + Package() { 0x0017FFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 3, 0, 19 }, + }) + + Name (AH4E, Package() { + // [RR3A]: PCI Express Port 3A on PC15 + Package() { 0x0000FFFF, 0, 0, 151 }, + // [RR3B]: PCI Express Port 3B on PC15 + Package() { 0x0001FFFF, 0, 0, 151 }, + // [RR3C]: PCI Express Port 3C on PC15 + Package() { 0x0002FFFF, 0, 0, 151 }, + // [RR3D]: PCI Express Port 3D on PC15 + Package() { 0x0003FFFF, 0, 0, 151 }, + // [KTI6]: Uncore 11 KTI6 + Package() { 0x000EFFFF, 0, 0, 144 }, + Package() { 0x000EFFFF, 1, 0, 148 }, + Package() { 0x000EFFFF, 2, 0, 149 }, + Package() { 0x000EFFFF, 3, 0, 150 }, + // [KTI7]: Uncore 11 KTI7 + Package() { 0x000FFFFF, 0, 0, 144 }, + Package() { 0x000FFFFF, 1, 0, 148 }, + Package() { 0x000FFFFF, 2, 0, 149 }, + Package() { 0x000FFFFF, 3, 0, 150 }, + // [KTI8]: Uncore 11 KTI8 + Package() { 0x0010FFFF, 0, 0, 144 }, + Package() { 0x0010FFFF, 1, 0, 148 }, + Package() { 0x0010FFFF, 2, 0, 149 }, + Package() { 0x0010FFFF, 3, 0, 150 }, + // [M3K2]: Uncore 11 M3K2 + Package() { 0x0012FFFF, 0, 0, 144 }, + Package() { 0x0012FFFF, 1, 0, 148 }, + Package() { 0x0012FFFF, 2, 0, 149 }, + Package() { 0x0012FFFF, 3, 0, 150 }, + // [M2U2]: Uncore 11 M2U2 + Package() { 0x0015FFFF, 0, 0, 144 }, + Package() { 0x0015FFFF, 1, 0, 148 }, + Package() { 0x0015FFFF, 2, 0, 149 }, + Package() { 0x0015FFFF, 3, 0, 150 }, + // [M2D2]: Uncore 11 M2D2 + Package() { 0x0016FFFF, 0, 0, 144 }, + Package() { 0x0016FFFF, 1, 0, 148 }, + Package() { 0x0016FFFF, 2, 0, 149 }, + Package() { 0x0016FFFF, 3, 0, 150 }, + // [M22]: Uncore 11 M22 + Package() { 0x0017FFFF, 0, 0, 144 }, + Package() { 0x0017FFFF, 1, 0, 148 }, + Package() { 0x0017FFFF, 2, 0, 149 }, + Package() { 0x0017FFFF, 3, 0, 150 }, + }) + + Name (PR4F, Package() { + // [SL27]: PCI Express Slot 39 on 3A on PC15 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR4F, Package() { + // [SL27]: PCI Express Slot 39 on 3A on PC15 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH4F, Package() { + // [SL27]: PCI Express Slot 39 on 3A on PC15 + Package() { 0x0000FFFF, 0, 0, 144 }, + Package() { 0x0000FFFF, 1, 0, 148 }, + Package() { 0x0000FFFF, 2, 0, 149 }, + Package() { 0x0000FFFF, 3, 0, 150 }, + }) + + Name (PR50, Package() { + // [SL28]: PCI Express Slot 40 on 3B on PC15 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR50, Package() { + // [SL28]: PCI Express Slot 40 on 3B on PC15 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH50, Package() { + // [SL28]: PCI Express Slot 40 on 3B on PC15 + Package() { 0x0000FFFF, 0, 0, 145 }, + Package() { 0x0000FFFF, 1, 0, 150 }, + Package() { 0x0000FFFF, 2, 0, 148 }, + Package() { 0x0000FFFF, 3, 0, 149 }, + }) + + Name (PR51, Package() { + // [SL29]: PCI Express Slot 41 on 3C on PC15 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR51, Package() { + // [SL29]: PCI Express Slot 41 on 3C on PC15 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH51, Package() { + // [SL29]: PCI Express Slot 41 on 3C on PC15 + Package() { 0x0000FFFF, 0, 0, 146 }, + Package() { 0x0000FFFF, 1, 0, 149 }, + Package() { 0x0000FFFF, 2, 0, 150 }, + Package() { 0x0000FFFF, 3, 0, 148 }, + }) + + Name (PR52, Package() { + // [SL2A]: PCI Express Slot 42 on 3D on PC15 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR52, Package() { + // [SL2A]: PCI Express Slot 42 on 3D on PC15 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH52, Package() { + // [SL2A]: PCI Express Slot 42 on 3D on PC15 + Package() { 0x0000FFFF, 0, 0, 147 }, + Package() { 0x0000FFFF, 1, 0, 150 }, + Package() { 0x0000FFFF, 2, 0, 148 }, + Package() { 0x0000FFFF, 3, 0, 149 }, + }) + + Name (PR53, Package() { + // [MCP4]: PCI Express Port 4 on PC16 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR53, Package() { + // [MCP4]: PCI Express Port 4 on PC16 + Package() { 0x0000FFFF, 0, 0, 16 }, + }) + + Name (AH53, Package() { + // [MCP4]: PCI Express Port 4 on PC16 + Package() { 0x0000FFFF, 0, 0, 159 }, + }) + + Name (PR54, Package() { + // [SL2B]: PCI Express Slot 43 on 4 on PC16 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR54, Package() { + // [SL2B]: PCI Express Slot 43 on 4 on PC16 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH54, Package() { + // [SL2B]: PCI Express Slot 43 on 4 on PC16 + Package() { 0x0000FFFF, 0, 0, 152 }, + Package() { 0x0000FFFF, 1, 0, 156 }, + Package() { 0x0000FFFF, 2, 0, 157 }, + Package() { 0x0000FFFF, 3, 0, 158 }, + }) + + Name (PR55, Package() { + // [MCP5]: PCI Express Port 5 on PC17 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR55, Package() { + // [MCP5]: PCI Express Port 5 on PC17 + Package() { 0x0000FFFF, 0, 0, 16 }, + }) + + Name (AH55, Package() { + // [MCP5]: PCI Express Port 5 on PC17 + Package() { 0x0000FFFF, 0, 0, 167 }, + }) + + Name (PR56, Package() { + // [SL2C]: PCI Express Slot 44 on 4 on PC17 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR56, Package() { + // [SL2C]: PCI Express Slot 44 on 4 on PC17 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH56, Package() { + // [SL2C]: PCI Express Slot 44 on 4 on PC17 + Package() { 0x0000FFFF, 0, 0, 160 }, + Package() { 0x0000FFFF, 1, 0, 164 }, + Package() { 0x0000FFFF, 2, 0, 165 }, + Package() { 0x0000FFFF, 3, 0, 166 }, + }) + + Name (PR57, Package() { + // [SRP0]: PCI Express Port 0 on PC18 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [CB3B]: CB3DMA on PC18 + // [CB3F]: CB3DMA on PC18 + Package() { 0x0004FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + // [CB3C]: CB3DMA on PC18 + // [CB3G]: CB3DMA on PC18 + Package() { 0x0004FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + // [CB3D]: CB3DMA on PC18 + // [CB3H]: CB3DMA on PC18 + Package() { 0x0004FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CB3E]: CB3DMA on PC18 + // [CB3A]: CB3DMA on PC18 + Package() { 0x0004FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [IIM3]: IIOMISC on PC03 + Package() { 0x0005FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0005FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0005FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0005FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [UBX3]: Uncore 12 UBOX Device + Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR57, Package() { + // [SRP0]: PCI Express Port 0 on PC18 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [CB3B]: CB3DMA on PC18 + // [CB3F]: CB3DMA on PC18 + Package() { 0x0004FFFF, 1, 0, 17 }, + // [CB3C]: CB3DMA on PC18 + // [CB3G]: CB3DMA on PC18 + Package() { 0x0004FFFF, 2, 0, 18 }, + // [CB3D]: CB3DMA on PC18 + // [CB3H]: CB3DMA on PC18 + Package() { 0x0004FFFF, 3, 0, 19 }, + // [CB3E]: CB3DMA on PC18 + // [CB3A]: CB3DMA on PC18 + Package() { 0x0004FFFF, 0, 0, 16 }, + // [IIM3]: IIOMISC on PC03 + Package() { 0x0005FFFF, 0, 0, 16 }, + Package() { 0x0005FFFF, 1, 0, 17 }, + Package() { 0x0005FFFF, 2, 0, 18 }, + Package() { 0x0005FFFF, 3, 0, 19 }, + // [UBX3]: Uncore 12 UBOX Device + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + }) + + Name (AH57, Package() { + // [SRP0]: PCI Express Port 0 on PC18 + Package() { 0x0000FFFF, 0, 0, 175 }, + // [CB3B]: CB3DMA on PC18 + // [CB3F]: CB3DMA on PC18 + Package() { 0x0004FFFF, 1, 0, 171 }, + // [CB3C]: CB3DMA on PC18 + // [CB3G]: CB3DMA on PC18 + Package() { 0x0004FFFF, 2, 0, 170 }, + // [CB3D]: CB3DMA on PC18 + // [CB3H]: CB3DMA on PC18 + Package() { 0x0004FFFF, 3, 0, 171 }, + // [CB3E]: CB3DMA on PC18 + // [CB3A]: CB3DMA on PC18 + Package() { 0x0004FFFF, 0, 0, 170 }, + // [IIM3]: IIOMISC on PC03 + Package() { 0x0005FFFF, 0, 0, 16 }, + Package() { 0x0005FFFF, 1, 0, 17 }, + Package() { 0x0005FFFF, 2, 0, 18 }, + Package() { 0x0005FFFF, 3, 0, 19 }, + // [UBX3]: Uncore 12 UBOX Device + Package() { 0x0008FFFF, 0, 0, 168 }, + Package() { 0x0008FFFF, 1, 0, 172 }, + Package() { 0x0008FFFF, 2, 0, 173 }, + Package() { 0x0008FFFF, 3, 0, 174 }, + }) + + Name (PR58, Package() { + // [SL2D]: PCI Express Slot 45 on P0 on PC18 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR58, Package() { + // [SL2D]: PCI Express Slot 45 on P0 on PC18 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH58, Package() { + // [SL2D]: PCI Express Slot 45 on P0 on PC18 + Package() { 0x0000FFFF, 0, 0, 168 }, + Package() { 0x0000FFFF, 1, 0, 172 }, + Package() { 0x0000FFFF, 2, 0, 173 }, + Package() { 0x0000FFFF, 3, 0, 174 }, + }) + + Name (PR59, Package() { + // [SR1A]: PCI Express Port 1A on PC19 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [SR1B]: PCI Express Port 1B on PC19 + Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [SR1C]: PCI Express Port 1C on PC19 + Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [SR1D]: PCI Express Port 1D on PC19 + Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [CHD0]: Uncore 13 CHAUTIL0-7 Device + Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHD1]: Uncore 13 CHAUTIL8-15 Device + Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHD2]: Uncore 13 CHAUTIL16-23 Device + Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHD3]: Uncore 13 CHAUTIL24-27 Device + Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHD4]: Uncore 13 CHASAD0-7 Device + Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHD5]: Uncore 13 CHASAD8-15 Device + Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHD6]: Uncore 13 CHASAD16-23 Device + Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CHD7]: Uncore 13 CHASAD24-27 Device + Package() { 0x0011FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0011FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0011FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0011FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CM12]: Uncore 13 CMSCHA0-7 Device + Package() { 0x0014FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0014FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0014FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0014FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CM13]: Uncore 13 CMS0CHA8-15 Device + Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CM14]: Uncore 13 CMS0CHA16-23 Device + Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CM15]: Uncore 13 CMS0CHA24-27 Device + Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [CDL3]: Uncore 13 CHASADALL Device + Package() { 0x001DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x001DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x001DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x001DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [PCU3]: Uncore 13 PCUCR Devices + Package() { 0x001EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x001EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x001EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x001EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [VCU3]: Uncore 13 VCUCR Device + Package() { 0x001FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x001FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x001FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x001FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR59, Package() { + // [SR1A]: PCI Express Port 1A on PC19 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [SR1B]: PCI Express Port 1B on PC19 + Package() { 0x0001FFFF, 0, 0, 16 }, + // [SR1C]: PCI Express Port 1C on PC19 + Package() { 0x0002FFFF, 0, 0, 16 }, + // [SR1D]: PCI Express Port 1D on PC19 + Package() { 0x0003FFFF, 0, 0, 16 }, + // [CHD0]: Uncore 13 CHAUTIL0-7 Device + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + // [CHD1]: Uncore 13 CHAUTIL8-15 Device + Package() { 0x0009FFFF, 0, 0, 16 }, + Package() { 0x0009FFFF, 1, 0, 17 }, + Package() { 0x0009FFFF, 2, 0, 18 }, + Package() { 0x0009FFFF, 3, 0, 19 }, + // [CHD2]: Uncore 13 CHAUTIL16-23 Device + Package() { 0x000AFFFF, 0, 0, 16 }, + Package() { 0x000AFFFF, 1, 0, 17 }, + Package() { 0x000AFFFF, 2, 0, 18 }, + Package() { 0x000AFFFF, 3, 0, 19 }, + // [CHD3]: Uncore 13 CHAUTIL24-27 Device + Package() { 0x000BFFFF, 0, 0, 16 }, + Package() { 0x000BFFFF, 1, 0, 17 }, + Package() { 0x000BFFFF, 2, 0, 18 }, + Package() { 0x000BFFFF, 3, 0, 19 }, + // [CHD4]: Uncore 13 CHASAD0-7 Device + Package() { 0x000EFFFF, 0, 0, 16 }, + Package() { 0x000EFFFF, 1, 0, 17 }, + Package() { 0x000EFFFF, 2, 0, 18 }, + Package() { 0x000EFFFF, 3, 0, 19 }, + // [CHD5]: Uncore 13 CHASAD8-15 Device + Package() { 0x000FFFFF, 0, 0, 16 }, + Package() { 0x000FFFFF, 1, 0, 17 }, + Package() { 0x000FFFFF, 2, 0, 18 }, + Package() { 0x000FFFFF, 3, 0, 19 }, + // [CHD6]: Uncore 13 CHASAD16-23 Device + Package() { 0x0010FFFF, 0, 0, 16 }, + Package() { 0x0010FFFF, 1, 0, 17 }, + Package() { 0x0010FFFF, 2, 0, 18 }, + Package() { 0x0010FFFF, 3, 0, 19 }, + // [CHD7]: Uncore 13 CHASAD24-27 Device + Package() { 0x0011FFFF, 0, 0, 16 }, + Package() { 0x0011FFFF, 1, 0, 17 }, + Package() { 0x0011FFFF, 2, 0, 18 }, + Package() { 0x0011FFFF, 3, 0, 19 }, + // [CM12]: Uncore 13 CMSCHA0-7 Device + Package() { 0x0014FFFF, 0, 0, 16 }, + Package() { 0x0014FFFF, 1, 0, 17 }, + Package() { 0x0014FFFF, 2, 0, 18 }, + Package() { 0x0014FFFF, 3, 0, 19 }, + // [CM13]: Uncore 13 CMS0CHA8-15 Device + Package() { 0x0015FFFF, 0, 0, 16 }, + Package() { 0x0015FFFF, 1, 0, 17 }, + Package() { 0x0015FFFF, 2, 0, 18 }, + Package() { 0x0015FFFF, 3, 0, 19 }, + // [CM14]: Uncore 13 CMS0CHA16-23 Device + Package() { 0x0016FFFF, 0, 0, 16 }, + Package() { 0x0016FFFF, 1, 0, 17 }, + Package() { 0x0016FFFF, 2, 0, 18 }, + Package() { 0x0016FFFF, 3, 0, 19 }, + // [CM15]: Uncore 13 CMS0CHA24-27 Device + Package() { 0x0017FFFF, 0, 0, 16 }, + Package() { 0x0017FFFF, 1, 0, 17 }, + Package() { 0x0017FFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 3, 0, 19 }, + // [CDL3]: Uncore 13 CHASADALL Device + Package() { 0x001DFFFF, 0, 0, 16 }, + Package() { 0x001DFFFF, 1, 0, 17 }, + Package() { 0x001DFFFF, 2, 0, 18 }, + Package() { 0x001DFFFF, 3, 0, 19 }, + // [PCU3]: Uncore 13 PCUCR Devices + Package() { 0x001EFFFF, 0, 0, 16 }, + Package() { 0x001EFFFF, 1, 0, 17 }, + Package() { 0x001EFFFF, 2, 0, 18 }, + Package() { 0x001EFFFF, 3, 0, 19 }, + // [VCU3]: Uncore 13 VCUCR Device + Package() { 0x001FFFFF, 0, 0, 16 }, + Package() { 0x001FFFFF, 1, 0, 17 }, + Package() { 0x001FFFFF, 2, 0, 18 }, + Package() { 0x001FFFFF, 3, 0, 19 }, + }) + + Name (AH59, Package() { + // [SR1A]: PCI Express Port 1A on PC19 + Package() { 0x0000FFFF, 0, 0, 183 }, + // [SR1B]: PCI Express Port 1B on PC19 + Package() { 0x0001FFFF, 0, 0, 183 }, + // [SR1C]: PCI Express Port 1C on PC19 + Package() { 0x0002FFFF, 0, 0, 183 }, + // [SR1D]: PCI Express Port 1D on PC19 + Package() { 0x0003FFFF, 0, 0, 183 }, + // [CHD0]: Uncore 13 CHAUTIL0-7 Device + Package() { 0x0008FFFF, 0, 0, 176 }, + Package() { 0x0008FFFF, 1, 0, 180 }, + Package() { 0x0008FFFF, 2, 0, 181 }, + Package() { 0x0008FFFF, 3, 0, 182 }, + // [CHD1]: Uncore 13 CHAUTIL8-15 Device + Package() { 0x0009FFFF, 0, 0, 176 }, + Package() { 0x0009FFFF, 1, 0, 180 }, + Package() { 0x0009FFFF, 2, 0, 181 }, + Package() { 0x0009FFFF, 3, 0, 182 }, + // [CHD2]: Uncore 13 CHAUTIL16-23 Device + Package() { 0x000AFFFF, 0, 0, 176 }, + Package() { 0x000AFFFF, 1, 0, 180 }, + Package() { 0x000AFFFF, 2, 0, 181 }, + Package() { 0x000AFFFF, 3, 0, 182 }, + // [CHD3]: Uncore 13 CHAUTIL24-27 Device + Package() { 0x000BFFFF, 0, 0, 176 }, + Package() { 0x000BFFFF, 1, 0, 180 }, + Package() { 0x000BFFFF, 2, 0, 181 }, + Package() { 0x000BFFFF, 3, 0, 182 }, + // [CHD4]: Uncore 13 CHASAD0-7 Device + Package() { 0x000EFFFF, 0, 0, 176 }, + Package() { 0x000EFFFF, 1, 0, 180 }, + Package() { 0x000EFFFF, 2, 0, 181 }, + Package() { 0x000EFFFF, 3, 0, 182 }, + // [CHD5]: Uncore 13 CHASAD8-15 Device + Package() { 0x000FFFFF, 0, 0, 176 }, + Package() { 0x000FFFFF, 1, 0, 180 }, + Package() { 0x000FFFFF, 2, 0, 181 }, + Package() { 0x000FFFFF, 3, 0, 182 }, + // [CHD6]: Uncore 13 CHASAD16-23 Device + Package() { 0x0010FFFF, 0, 0, 176 }, + Package() { 0x0010FFFF, 1, 0, 180 }, + Package() { 0x0010FFFF, 2, 0, 181 }, + Package() { 0x0010FFFF, 3, 0, 182 }, + // [CHD7]: Uncore 13 CHASAD24-27 Device + Package() { 0x0011FFFF, 0, 0, 176 }, + Package() { 0x0011FFFF, 1, 0, 180 }, + Package() { 0x0011FFFF, 2, 0, 181 }, + Package() { 0x0011FFFF, 3, 0, 182 }, + // [CM12]: Uncore 13 CMSCHA0-7 Device + Package() { 0x0014FFFF, 0, 0, 176 }, + Package() { 0x0014FFFF, 1, 0, 180 }, + Package() { 0x0014FFFF, 2, 0, 181 }, + Package() { 0x0014FFFF, 3, 0, 182 }, + // [CM13]: Uncore 13 CMS0CHA8-15 Device + Package() { 0x0015FFFF, 0, 0, 176 }, + Package() { 0x0015FFFF, 1, 0, 180 }, + Package() { 0x0015FFFF, 2, 0, 181 }, + Package() { 0x0015FFFF, 3, 0, 182 }, + // [CM14]: Uncore 13 CMS0CHA16-23 Device + Package() { 0x0016FFFF, 0, 0, 176 }, + Package() { 0x0016FFFF, 1, 0, 180 }, + Package() { 0x0016FFFF, 2, 0, 181 }, + Package() { 0x0016FFFF, 3, 0, 182 }, + // [CM15]: Uncore 13 CMS0CHA24-27 Device + Package() { 0x0017FFFF, 0, 0, 176 }, + Package() { 0x0017FFFF, 1, 0, 180 }, + Package() { 0x0017FFFF, 2, 0, 181 }, + Package() { 0x0017FFFF, 3, 0, 182 }, + // [CDL3]: Uncore 13 CHASADALL Device + Package() { 0x001DFFFF, 0, 0, 176 }, + Package() { 0x001DFFFF, 1, 0, 180 }, + Package() { 0x001DFFFF, 2, 0, 181 }, + Package() { 0x001DFFFF, 3, 0, 182 }, + // [PCU3]: Uncore 13 PCUCR Devices + Package() { 0x001EFFFF, 0, 0, 176 }, + Package() { 0x001EFFFF, 1, 0, 180 }, + Package() { 0x001EFFFF, 2, 0, 181 }, + Package() { 0x001EFFFF, 3, 0, 182 }, + // [VCU3]: Uncore 13 VCUCR Device + Package() { 0x001FFFFF, 0, 0, 176 }, + Package() { 0x001FFFFF, 1, 0, 180 }, + Package() { 0x001FFFFF, 2, 0, 181 }, + Package() { 0x001FFFFF, 3, 0, 182 }, + }) + + Name (PR5A, Package() { + // [SL2E]: PCI Express Slot 46 on 1A on PC19 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR5A, Package() { + // [SL2E]: PCI Express Slot 46 on 1A on PC19 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH5A, Package() { + // [SL2E]: PCI Express Slot 46 on 1A on PC19 + Package() { 0x0000FFFF, 0, 0, 176 }, + Package() { 0x0000FFFF, 1, 0, 180 }, + Package() { 0x0000FFFF, 2, 0, 181 }, + Package() { 0x0000FFFF, 3, 0, 182 }, + }) + + Name (PR5B, Package() { + // [SL2F]: PCI Express Slot 47 on 1B on PC19 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR5B, Package() { + // [SL2F]: PCI Express Slot 47 on 1B on PC19 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH5B, Package() { + // [SL2F]: PCI Express Slot 47 on 1B on PC19 + Package() { 0x0000FFFF, 0, 0, 177 }, + Package() { 0x0000FFFF, 1, 0, 182 }, + Package() { 0x0000FFFF, 2, 0, 180 }, + Package() { 0x0000FFFF, 3, 0, 181 }, + }) + + Name (PR5C, Package() { + // [SL30]: PCI Express Slot 48 on 1C on PC19 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR5C, Package() { + // [SL30]: PCI Express Slot 48 on 1C on PC19 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH5C, Package() { + // [SL30]: PCI Express Slot 48 on 1C on PC19 + Package() { 0x0000FFFF, 0, 0, 178 }, + Package() { 0x0000FFFF, 1, 0, 181 }, + Package() { 0x0000FFFF, 2, 0, 182 }, + Package() { 0x0000FFFF, 3, 0, 180 }, + }) + + Name (PR5D, Package() { + // [SL31]: PCI Express Slot 49 on 1D on PC19 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR5D, Package() { + // [SL31]: PCI Express Slot 49 on 1D on PC19 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH5D, Package() { + // [SL31]: PCI Express Slot 49 on 1D on PC19 + Package() { 0x0000FFFF, 0, 0, 179 }, + Package() { 0x0000FFFF, 1, 0, 182 }, + Package() { 0x0000FFFF, 2, 0, 180 }, + Package() { 0x0000FFFF, 3, 0, 181 }, + }) + + Name (PR5E, Package() { + // [SR2A]: PCI Express Port 2A on PC20 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [SR2B]: PCI Express Port 2B on PC20 + Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [SR2C]: PCI Express Port 2C on PC20 + Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [SR2D]: PCI Express Port 2D on PC20 + Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [M2M6]: Uncore 14 M2MEM0 Device + Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M2M7]: Uncore 14 M2MEM10 Device + Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCM6]: Uncore 14 MCMAIN Device + Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCD6]: Uncore 14 MCDECS2 Device + Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCM7]: Uncore 14 MCMAIN Device + Package() { 0x000CFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000CFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000CFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000CFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [MCD7]: Uncore 14 MCDECS12 Device + Package() { 0x000DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [UMC6]: Uncore 14 Unicast MC0 DDRIO0 Device + Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [UMC7]: Uncore 14 Unicast MC1 DDRIO0 Device + Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR5E, Package() { + // [SR2A]: PCI Express Port 2A on PC20 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [SR2B]: PCI Express Port 2B on PC20 + Package() { 0x0001FFFF, 0, 0, 16 }, + // [SR2C]: PCI Express Port 2C on PC20 + Package() { 0x0002FFFF, 0, 0, 16 }, + // [SR2D]: PCI Express Port 2D on PC20 + Package() { 0x0003FFFF, 0, 0, 16 }, + // [M2M6]: Uncore 14 M2MEM0 Device + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + // [M2M7]: Uncore 14 M2MEM10 Device + Package() { 0x0009FFFF, 0, 0, 16 }, + Package() { 0x0009FFFF, 1, 0, 17 }, + Package() { 0x0009FFFF, 2, 0, 18 }, + Package() { 0x0009FFFF, 3, 0, 19 }, + // [MCM6]: Uncore 14 MCMAIN Device + Package() { 0x000AFFFF, 0, 0, 16 }, + Package() { 0x000AFFFF, 1, 0, 17 }, + Package() { 0x000AFFFF, 2, 0, 18 }, + Package() { 0x000AFFFF, 3, 0, 19 }, + // [MCD6]: Uncore 14 MCDECS2 Device + Package() { 0x000BFFFF, 0, 0, 16 }, + Package() { 0x000BFFFF, 1, 0, 17 }, + Package() { 0x000BFFFF, 2, 0, 18 }, + Package() { 0x000BFFFF, 3, 0, 19 }, + // [MCM7]: Uncore 14 MCMAIN Device + Package() { 0x000CFFFF, 0, 0, 16 }, + Package() { 0x000CFFFF, 1, 0, 17 }, + Package() { 0x000CFFFF, 2, 0, 18 }, + Package() { 0x000CFFFF, 3, 0, 19 }, + // [MCD7]: Uncore 14 MCDECS12 Device + Package() { 0x000DFFFF, 0, 0, 16 }, + Package() { 0x000DFFFF, 1, 0, 17 }, + Package() { 0x000DFFFF, 2, 0, 18 }, + Package() { 0x000DFFFF, 3, 0, 19 }, + // [UMC6]: Uncore 14 Unicast MC0 DDRIO0 Device + Package() { 0x0016FFFF, 0, 0, 16 }, + Package() { 0x0016FFFF, 1, 0, 17 }, + Package() { 0x0016FFFF, 2, 0, 18 }, + Package() { 0x0016FFFF, 3, 0, 19 }, + // [UMC7]: Uncore 14 Unicast MC1 DDRIO0 Device + Package() { 0x0017FFFF, 0, 0, 16 }, + Package() { 0x0017FFFF, 1, 0, 17 }, + Package() { 0x0017FFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 3, 0, 19 }, + }) + + Name (AH5E, Package() { + // [SR2A]: PCI Express Port 2A on PC20 + Package() { 0x0000FFFF, 0, 0, 191 }, + // [SR2B]: PCI Express Port 2B on PC20 + Package() { 0x0001FFFF, 0, 0, 191 }, + // [SR2C]: PCI Express Port 2C on PC20 + Package() { 0x0002FFFF, 0, 0, 191 }, + // [SR2D]: PCI Express Port 2D on PC20 + Package() { 0x0003FFFF, 0, 0, 191 }, + // [M2M6]: Uncore 14 M2MEM0 Device + Package() { 0x0008FFFF, 0, 0, 184 }, + Package() { 0x0008FFFF, 1, 0, 188 }, + Package() { 0x0008FFFF, 2, 0, 189 }, + Package() { 0x0008FFFF, 3, 0, 190 }, + // [M2M7]: Uncore 14 M2MEM10 Device + Package() { 0x0009FFFF, 0, 0, 184 }, + Package() { 0x0009FFFF, 1, 0, 188 }, + Package() { 0x0009FFFF, 2, 0, 189 }, + Package() { 0x0009FFFF, 3, 0, 190 }, + // [MCM6]: Uncore 14 MCMAIN Device + Package() { 0x000AFFFF, 0, 0, 184 }, + Package() { 0x000AFFFF, 1, 0, 188 }, + Package() { 0x000AFFFF, 2, 0, 189 }, + Package() { 0x000AFFFF, 3, 0, 190 }, + // [MCD6]: Uncore 14 MCDECS2 Device + Package() { 0x000BFFFF, 0, 0, 184 }, + Package() { 0x000BFFFF, 1, 0, 188 }, + Package() { 0x000BFFFF, 2, 0, 189 }, + Package() { 0x000BFFFF, 3, 0, 190 }, + // [MCM7]: Uncore 14 MCMAIN Device + Package() { 0x000CFFFF, 0, 0, 184 }, + Package() { 0x000CFFFF, 1, 0, 188 }, + Package() { 0x000CFFFF, 2, 0, 189 }, + Package() { 0x000CFFFF, 3, 0, 190 }, + // [MCD7]: Uncore 14 MCDECS12 Device + Package() { 0x000DFFFF, 0, 0, 184 }, + Package() { 0x000DFFFF, 1, 0, 188 }, + Package() { 0x000DFFFF, 2, 0, 189 }, + Package() { 0x000DFFFF, 3, 0, 190 }, + // [UMC6]: Uncore 14 Unicast MC0 DDRIO0 Device + Package() { 0x0016FFFF, 0, 0, 184 }, + Package() { 0x0016FFFF, 1, 0, 188 }, + Package() { 0x0016FFFF, 2, 0, 189 }, + Package() { 0x0016FFFF, 3, 0, 190 }, + // [UMC7]: Uncore 14 Unicast MC1 DDRIO0 Device + Package() { 0x0017FFFF, 0, 0, 184 }, + Package() { 0x0017FFFF, 1, 0, 188 }, + Package() { 0x0017FFFF, 2, 0, 189 }, + Package() { 0x0017FFFF, 3, 0, 190 }, + }) + + Name (PR5F, Package() { + // [SL32]: PCI Express Slot 50 on 2A on PC20 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR5F, Package() { + // [SL32]: PCI Express Slot 50 on 2A on PC20 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH5F, Package() { + // [SL32]: PCI Express Slot 50 on 2A on PC20 + Package() { 0x0000FFFF, 0, 0, 184 }, + Package() { 0x0000FFFF, 1, 0, 188 }, + Package() { 0x0000FFFF, 2, 0, 189 }, + Package() { 0x0000FFFF, 3, 0, 190 }, + }) + + Name (PR60, Package() { + // [SL33]: PCI Express Slot 51 on 2B on PC20 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR60, Package() { + // [SL33]: PCI Express Slot 51 on 2B on PC20 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH60, Package() { + // [SL33]: PCI Express Slot 51 on 2B on PC20 + Package() { 0x0000FFFF, 0, 0, 185 }, + Package() { 0x0000FFFF, 1, 0, 190 }, + Package() { 0x0000FFFF, 2, 0, 188 }, + Package() { 0x0000FFFF, 3, 0, 189 }, + }) + + Name (PR61, Package() { + // [SL34]: PCI Express Slot 52 on 2C on PC20 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR61, Package() { + // [SL34]: PCI Express Slot 52 on 2C on PC20 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH61, Package() { + // [SL34]: PCI Express Slot 52 on 2C on PC20 + Package() { 0x0000FFFF, 0, 0, 186 }, + Package() { 0x0000FFFF, 1, 0, 189 }, + Package() { 0x0000FFFF, 2, 0, 190 }, + Package() { 0x0000FFFF, 3, 0, 188 }, + }) + + Name (PR62, Package() { + // [SL35]: PCI Express Slot 53 on 2D on PC20 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR62, Package() { + // [SL35]: PCI Express Slot 53 on 2D on PC20 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH62, Package() { + // [SL35]: PCI Express Slot 53 on 2D on PC20 + Package() { 0x0000FFFF, 0, 0, 187 }, + Package() { 0x0000FFFF, 1, 0, 190 }, + Package() { 0x0000FFFF, 2, 0, 188 }, + Package() { 0x0000FFFF, 3, 0, 189 }, + }) + + Name (PR63, Package() { + // [SR3A]: PCI Express Port 3A on PC21 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [SR3B]: PCI Express Port 3B on PC21 + Package() { 0x0001FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [SR3C]: PCI Express Port 3C on PC21 + Package() { 0x0002FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [SR3D]: PCI Express Port 3D on PC21 + Package() { 0x0003FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + // [KTI9]: Uncore 15 KTI9 + Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [KT10]: Uncore 15 KT10 + Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [KT11]: Uncore 15 KT11 + Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M3K3]: Uncore 15 M3K3 + Package() { 0x0012FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0012FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0012FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0012FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M2U3]: Uncore 15 M2U3 + Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M2D3]: Uncore 15 M2D3 + Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + // [M23]: Uncore 15 M23 + Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR63, Package() { + // [SR3A]: PCI Express Port 3A on PC21 + Package() { 0x0000FFFF, 0, 0, 16 }, + // [SR3B]: PCI Express Port 3B on PC21 + Package() { 0x0001FFFF, 0, 0, 16 }, + // [SR3C]: PCI Express Port 3C on PC21 + Package() { 0x0002FFFF, 0, 0, 16 }, + // [SR3D]: PCI Express Port 3D on PC21 + Package() { 0x0003FFFF, 0, 0, 16 }, + // [KTI9]: Uncore 15 KTI9 + Package() { 0x000EFFFF, 0, 0, 16 }, + Package() { 0x000EFFFF, 1, 0, 17 }, + Package() { 0x000EFFFF, 2, 0, 18 }, + Package() { 0x000EFFFF, 3, 0, 19 }, + // [KT10]: Uncore 15 KT10 + Package() { 0x000FFFFF, 0, 0, 16 }, + Package() { 0x000FFFFF, 1, 0, 17 }, + Package() { 0x000FFFFF, 2, 0, 18 }, + Package() { 0x000FFFFF, 3, 0, 19 }, + // [KT11]: Uncore 15 KT11 + Package() { 0x0010FFFF, 0, 0, 16 }, + Package() { 0x0010FFFF, 1, 0, 17 }, + Package() { 0x0010FFFF, 2, 0, 18 }, + Package() { 0x0010FFFF, 3, 0, 19 }, + // [M3K3]: Uncore 15 M3K3 + Package() { 0x0012FFFF, 0, 0, 16 }, + Package() { 0x0012FFFF, 1, 0, 17 }, + Package() { 0x0012FFFF, 2, 0, 18 }, + Package() { 0x0012FFFF, 3, 0, 19 }, + // [M2U3]: Uncore 15 M2U3 + Package() { 0x0015FFFF, 0, 0, 16 }, + Package() { 0x0015FFFF, 1, 0, 17 }, + Package() { 0x0015FFFF, 2, 0, 18 }, + Package() { 0x0015FFFF, 3, 0, 19 }, + // [M2D3]: Uncore 15 M2D3 + Package() { 0x0016FFFF, 0, 0, 16 }, + Package() { 0x0016FFFF, 1, 0, 17 }, + Package() { 0x0016FFFF, 2, 0, 18 }, + Package() { 0x0016FFFF, 3, 0, 19 }, + // [M23]: Uncore 15 M23 + Package() { 0x0017FFFF, 0, 0, 16 }, + Package() { 0x0017FFFF, 1, 0, 17 }, + Package() { 0x0017FFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 3, 0, 19 }, + }) + + Name (AH63, Package() { + // [SR3A]: PCI Express Port 3A on PC21 + Package() { 0x0000FFFF, 0, 0, 199 }, + // [SR3B]: PCI Express Port 3B on PC21 + Package() { 0x0001FFFF, 0, 0, 199 }, + // [SR3C]: PCI Express Port 3C on PC21 + Package() { 0x0002FFFF, 0, 0, 199 }, + // [SR3D]: PCI Express Port 3D on PC21 + Package() { 0x0003FFFF, 0, 0, 199 }, + // [KTI9]: Uncore 15 KTI9 + Package() { 0x000EFFFF, 0, 0, 192 }, + Package() { 0x000EFFFF, 1, 0, 196 }, + Package() { 0x000EFFFF, 2, 0, 197 }, + Package() { 0x000EFFFF, 3, 0, 198 }, + // [KT10]: Uncore 15 KT10 + Package() { 0x000FFFFF, 0, 0, 192 }, + Package() { 0x000FFFFF, 1, 0, 196 }, + Package() { 0x000FFFFF, 2, 0, 197 }, + Package() { 0x000FFFFF, 3, 0, 198 }, + // [KT11]: Uncore 15 KT11 + Package() { 0x0010FFFF, 0, 0, 192 }, + Package() { 0x0010FFFF, 1, 0, 196 }, + Package() { 0x0010FFFF, 2, 0, 197 }, + Package() { 0x0010FFFF, 3, 0, 198 }, + // [M3K3]: Uncore 15 M3K3 + Package() { 0x0012FFFF, 0, 0, 192 }, + Package() { 0x0012FFFF, 1, 0, 196 }, + Package() { 0x0012FFFF, 2, 0, 197 }, + Package() { 0x0012FFFF, 3, 0, 198 }, + // [M2U3]: Uncore 15 M2U3 + Package() { 0x0015FFFF, 0, 0, 192 }, + Package() { 0x0015FFFF, 1, 0, 196 }, + Package() { 0x0015FFFF, 2, 0, 197 }, + Package() { 0x0015FFFF, 3, 0, 198 }, + // [M2D3]: Uncore 15 M2D3 + Package() { 0x0016FFFF, 0, 0, 192 }, + Package() { 0x0016FFFF, 1, 0, 196 }, + Package() { 0x0016FFFF, 2, 0, 197 }, + Package() { 0x0016FFFF, 3, 0, 198 }, + // [M23]: Uncore 15 M23 + Package() { 0x0017FFFF, 0, 0, 192 }, + Package() { 0x0017FFFF, 1, 0, 196 }, + Package() { 0x0017FFFF, 2, 0, 197 }, + Package() { 0x0017FFFF, 3, 0, 198 }, + }) + + Name (PR64, Package() { + // [SL36]: PCI Express Slot 54 on 3A on PC21 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR64, Package() { + // [SL36]: PCI Express Slot 54 on 3A on PC21 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH64, Package() { + // [SL36]: PCI Express Slot 54 on 3A on PC21 + Package() { 0x0000FFFF, 0, 0, 192 }, + Package() { 0x0000FFFF, 1, 0, 196 }, + Package() { 0x0000FFFF, 2, 0, 197 }, + Package() { 0x0000FFFF, 3, 0, 198 }, + }) + + Name (PR65, Package() { + // [SL37]: PCI Express Slot 55 on 3B on PC21 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR65, Package() { + // [SL37]: PCI Express Slot 55 on 3B on PC21 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH65, Package() { + // [SL37]: PCI Express Slot 55 on 3B on PC21 + Package() { 0x0000FFFF, 0, 0, 193 }, + Package() { 0x0000FFFF, 1, 0, 198 }, + Package() { 0x0000FFFF, 2, 0, 196 }, + Package() { 0x0000FFFF, 3, 0, 197 }, + }) + + Name (PR66, Package() { + // [SL38]: PCI Express Slot 56 on 3C on PC21 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR66, Package() { + // [SL38]: PCI Express Slot 56 on 3C on PC21 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH66, Package() { + // [SL38]: PCI Express Slot 56 on 3C on PC21 + Package() { 0x0000FFFF, 0, 0, 194 }, + Package() { 0x0000FFFF, 1, 0, 197 }, + Package() { 0x0000FFFF, 2, 0, 198 }, + Package() { 0x0000FFFF, 3, 0, 196 }, + }) + + Name (PR67, Package() { + // [SL39]: PCI Express Slot 57 on 3D on PC21 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR67, Package() { + // [SL39]: PCI Express Slot 57 on 3D on PC21 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH67, Package() { + // [SL39]: PCI Express Slot 57 on 3D on PC21 + Package() { 0x0000FFFF, 0, 0, 195 }, + Package() { 0x0000FFFF, 1, 0, 198 }, + Package() { 0x0000FFFF, 2, 0, 196 }, + Package() { 0x0000FFFF, 3, 0, 197 }, + }) + + Name (PR68, Package() { + // [MCP6]: PCI Express Port 4 on PC22 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR68, Package() { + // [MCP6]: PCI Express Port 4 on PC22 + Package() { 0x0000FFFF, 0, 0, 16 }, + }) + + Name (AH68, Package() { + // [MCP6]: PCI Express Port 4 on PC22 + Package() { 0x0000FFFF, 0, 0, 207 }, + }) + + Name (PR69, Package() { + // [SL3A]: PCI Express Slot 58 on 4 on PC22 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR69, Package() { + // [SL3A]: PCI Express Slot 58 on 4 on PC22 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH69, Package() { + // [SL3A]: PCI Express Slot 58 on 4 on PC22 + Package() { 0x0000FFFF, 0, 0, 200 }, + Package() { 0x0000FFFF, 1, 0, 204 }, + Package() { 0x0000FFFF, 2, 0, 205 }, + Package() { 0x0000FFFF, 3, 0, 206 }, + }) + + Name (PR6A, Package() { + // [MCP7]: PCI Express Port 5 on PC23 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR6A, Package() { + // [MCP7]: PCI Express Port 5 on PC23 + Package() { 0x0000FFFF, 0, 0, 16 }, + }) + + Name (AH6A, Package() { + // [MCP7]: PCI Express Port 5 on PC23 + Package() { 0x0000FFFF, 0, 0, 215 }, + }) + + Name (PR6B, Package() { + // [SL3B]: PCI Express Slot 59 on 4 on PC23 + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR6B, Package() { + // [SL3B]: PCI Express Slot 59 on 4 on PC23 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (AH6B, Package() { + // [SL3B]: PCI Express Slot 59 on 4 on PC23 + Package() { 0x0000FFFF, 0, 0, 208 }, + Package() { 0x0000FFFF, 1, 0, 212 }, + Package() { 0x0000FFFF, 2, 0, 213 }, + Package() { 0x0000FFFF, 3, 0, 214 }, + }) + + Name (PR6C, Package() { + // [FPG0]: FPGA Device + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR6C, Package() { + // [FPG0]: FPGA Device + Package() { 0x0000FFFF, 0, 0, 16 }, + }) + + Name (PR6D, Package() { + // [FPG1]: FPGA Device + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + }) + + Name (AR6D, Package() { + // [FPG1]: FPGA Device + Package() { 0x0000FFFF, 1, 0, 17 }, + }) + + Name (PR6E, Package() { + // [FPG2]: FPGA Device + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + }) + + Name (AR6E, Package() { + // [FPG2]: FPGA Device + Package() { 0x0000FFFF, 2, 0, 18 }, + }) + + Name (PR6F, Package() { + // [FPG3]: FPGA Device + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR6F, Package() { + // [FPG3]: FPGA Device + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + Name (PR70, Package() { + // [FKT0]: FPGA Device + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + }) + + Name (AR70, Package() { + // [FKT0]: FPGA Device + Package() { 0x0000FFFF, 0, 0, 16 }, + }) + + Name (PR71, Package() { + // [FKT1]: FPGA Device + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + }) + + Name (AR71, Package() { + // [FKT1]: FPGA Device + Package() { 0x0000FFFF, 1, 0, 17 }, + }) + + Name (PR72, Package() { + // [FKT2]: FPGA Device + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + }) + + Name (AR72, Package() { + // [FKT2]: FPGA Device + Package() { 0x0000FFFF, 2, 0, 18 }, + }) + + Name (PR73, Package() { + // [FKT3]: FPGA Device + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (AR73, Package() { + // [FKT3]: FPGA Device + Package() { 0x0000FFFF, 3, 0, 19 }, + }) + + // Socket 0 Root bridge (Stack 0) + Device (PC00) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x00) + Method (_BBN, 0, NotSerialized) { + return (BB00) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR00) + } + If (LEqual(AP00, One)) { + Return (AH00) + } + Return (AR00) + } + + #include "PC00.asi" + #include "HostBus.asl" + + // Legacy PCI Express Port 0 on PC00 + Device (DMI0) { + Name (_ADR, 0x00000000) + } + + // CB3DMA on PC00 + Device (CB0A) { + Name (_ADR, 0x00040000) + } + + // CB3DMA on PC00 + Device (CB0B) { + Name (_ADR, 0x00040001) + } + + // CB3DMA on PC00 + Device (CB0C) { + Name (_ADR, 0x00040002) + } + + // CB3DMA on PC00 + Device (CB0D) { + Name (_ADR, 0x00040003) + } + + // CB3DMA on PC00 + Device (CB0E) { + Name (_ADR, 0x00040004) + } + + // CB3DMA on PC00 + Device (CB0F) { + Name (_ADR, 0x00040005) + } + + // CB3DMA on PC00 + Device (CB0G) { + Name (_ADR, 0x00040006) + } + + // CB3DMA on PC00 + Device (CB0H) { + Name (_ADR, 0x00040007) + } + + // IIOMISC on PC00 + Device (IIM0) { + Name (_ADR, 0x00050000) + } + + // Uncore 0 UBOX Device + Device (UBX0) { + Name (_ADR, 0x00080000) + } + + // High definition Audio Controller + Device (ALZA) { + Name (_ADR, 0x000E0000) + } + + // Display Controller + Device (DISP) { + Name (_ADR, 0x000F0000) + } + + // HECI #1 + Device (IHC1) { + Name (_ADR, 0x00100000) + } + + // HECI #2 + Device (IHC2) { + Name (_ADR, 0x00100001) + } + + // IDE-Redirection (IDE-R) + Device (IIDR) { + Name (_ADR, 0x00100002) + } + + // Keyboard and Text (KT) Redirection + Device (IMKT) { + Name (_ADR, 0x00100003) + } + + // HECI #3 + Device (IHC3) { + Name (_ADR, 0x00100004) + } + + // MROM 0 function function + Device (MRO0) { + Name (_ADR, 0x00110000) + } + + // MROM 1 function function + Device (MRO1) { + Name (_ADR, 0x00110001) + } + + // sSATA Host controller 2 on PCH + Device (SAT2) { + Name (_ADR, 0x00110005) + } + + // xHCI controller 1 on PCH + Device (XHCI) { + Name (_ADR, 0x00140000) + } + + // USB Device Controller (OTG) on PCH + Device (OTG0) { + Name (_ADR, 0x00140001) + } + + // Thermal Subsystem on PCH + Device (TERM) { + Name (_ADR, 0x00140002) + } + + // Camera IO Host Controller on PCH + Device (CAMR) { + Name (_ADR, 0x00140003) + } + + // Northpeak Phantom (ACPI) Function on PCH + Device (NTHP) { + Name (_ADR, 0x00140004) + } + + // HECI #1 on PCH + Device (HEC1) { + Name (_ADR, 0x00160000) + } + + // HECI #2 on PCH + Device (HEC2) { + Name (_ADR, 0x00160001) + } + + // ME IDE redirect on PCH + Device (IDER) { + Name (_ADR, 0x00160002) + } + + // MEKT on PCH + Device (MEKT) { + Name (_ADR, 0x00160003) + } + + // HECI #3 on PCH + Device (HEC3) { + Name (_ADR, 0x00160004) + } + + // SATA controller 1 on PCH + Device (SAT1) { + Name (_ADR, 0x00170000) + } + + // NAND Cycle Router on PCH + Device (NAN1) { + Name (_ADR, 0x00180000) + } + + // PCIE PCH Root Port #17 + Device (RP17) { + #include "RP17_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR01) + } + Return (AR01) + } + + // PCIE PCH Slot #17 + Device (SLTH) { + Name (_ADR, 0x00000000) + } + } + + // PCIE PCH Root Port #18 + Device (RP18) { + #include "RP18_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR02) + } + Return (AR02) + } + + // PCIE PCH Slot #18 + Device (SLTI) { + Name (_ADR, 0x00000000) + } + } + + // PCIE PCH Root Port #19 + Device (RP19) { + #include "RP19_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR03) + } + Return (AR03) + } + + // PCIE PCH Slot #19 + Device (SLTJ) { + Name (_ADR, 0x00000000) + } + } + + // PCIE PCH Root Port #20 + Device (RP20) { + #include "RP20_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR04) + } + Return (AR04) + } + + // PCIE PCH Slot #20 + Device (SLTK) { + Name (_ADR, 0x00000000) + } + } + + // PCIE PCH Root Port #1 + Device (RP01) { + #include "RP01_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR05) + } + Return (AR05) + } + } + + // PCIE PCH Root Port #2 + Device (RP02) { + #include "RP02_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR06) + } + Return (AR06) + } + } + + // PCIE PCH Root Port #3 + Device (RP03) { + #include "RP03_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR07) + } + Return (AR07) + } + } + + // PCIE PCH Root Port #4 + Device (RP04) { + #include "RP04_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR08) + } + Return (AR08) + } + } + + // PCIE PCH Root Port #5 + Device (RP05) { + #include "RP05_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR09) + } + Return (AR09) + } + } + + // PCIE PCH Root Port #6 + Device (RP06) { + #include "RP06_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR0A) + } + Return (AR0A) + } + } + + // PCIE PCH Root Port #7 + Device (RP07) { + #include "RP07_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR0B) + } + Return (AR0B) + } + } + + // PCIE PCH Root Port #8 + Device (RP08) { + #include "RP08_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR0C) + } + Return (AR0C) + } + } + + // PCIE PCH Root Port #9 + Device (RP09) { + #include "RP09_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR0D) + } + Return (AR0D) + } + + // PCIE PCH Slot #9 + Device (SLT9) { + Name (_ADR, 0x00000000) + } + } + + // PCIE PCH Root Port #10 + Device (RP10) { + #include "RP10_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR0E) + } + Return (AR0E) + } + + // PCIE PCH Slot #10 + Device (SLTA) { + Name (_ADR, 0x00000000) + } + } + + // PCIE PCH Root Port #11 + Device (RP11) { + #include "RP11_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR0F) + } + Return (AR0F) + } + + // PCIE PCH Slot #11 + Device (SLTB) { + Name (_ADR, 0x00000000) + } + } + + // PCIE PCH Root Port #12 + Device (RP12) { + #include "RP12_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR10) + } + Return (AR10) + } + + // PCIE PCH Slot #12 + Device (SLTC) { + Name (_ADR, 0x00000000) + } + } + + // PCIE PCH Root Port #13 + Device (RP13) { + #include "RP13_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR11) + } + Return (AR11) + } + + // PCIE PCH Slot #13 + Device (SLTD) { + Name (_ADR, 0x00000000) + } + } + + // PCIE PCH Root Port #14 + Device (RP14) { + #include "RP14_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR12) + } + Return (AR12) + } + + // PCIE PCH Slot #14 + Device (SLTE) { + Name (_ADR, 0x00000000) + } + } + + // PCIE PCH Root Port #15 + Device (RP15) { + #include "RP15_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR13) + } + Return (AR13) + } + + // PCIE PCH Slot #15 + Device (SLTF) { + Name (_ADR, 0x00000000) + } + } + + // PCIE PCH Root Port #16 + Device (RP16) { + #include "RP16_ADR.asl" + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR14) + } + Return (AR14) + } + + // PCIE PCH Slot #16 + Device (SLTG) { + Name (_ADR, 0x00000000) + } + } + + // UART #0 on PCH + Device (UAR0) { + Name (_ADR, 0x001E0000) + } + + // UART #1 on PCH + Device (UAR1) { + Name (_ADR, 0x001E0001) + } + + // SPI #0 on PCH + Device (SPI0) { + Name (_ADR, 0x001E0002) + } + + // SPI #1 on PCH + Device (SPI1) { + Name (_ADR, 0x001E0003) + } + + // ISA Bridge on PCH + Device (LPC0) { + Name (_ADR, 0x001F0000) + + #include "PchLpc.asi" + } + + // Power Management Controller on PCH + Device (PMC1) { + Name (_ADR, 0x001F0002) + } + + // HD Audio Subsystem Controller on PCH + Device (CAVS) { + Name (_ADR, 0x001F0003) + } + + // SMBus controller on PCH + Device (SMBS) { + Name (_ADR, 0x001F0004) + } + + // SPI controller on PCH + Device (SPIC) { + Name (_ADR, 0x001F0005) + } + + // GbE Controller on PCH + Device (GBE1) { + Name (_ADR, 0x001F0006) + } + + // Northpeak Controller on PCH + Device (NTPK) { + Name (_ADR, 0x001F0007) + } + } + + // Socket 0 Root bridge (Stack 1) + Device (PC01) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x01) + Method (_BBN, 0, NotSerialized) { + return (BB01) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR15) + } + If (LEqual(AP01, One)) { + Return (AH15) + } + Return (AR15) + } + + #include "PC01.asi" + + // PCI Express Port 1A on PC01 + Device (BR1A) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR16) + } + If (LEqual(AP01, One)) { + Return (AH16) + } + Return (AR16) + } + + #include "PcieHp.asi" + #include "PcieNonHpDev.asi" + } + + // PCI Express Port 1B on PC01 + Device (BR1B) { + Name (_ADR, 0x00010000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR17) + } + If (LEqual(AP01, One)) { + Return (AH17) + } + Return (AR17) + } + + #include "PcieHp.asi" + #include "PcieNonHpDev.asi" + } + + // PCI Express Port 1C on PC01 + Device (BR1C) { + Name (_ADR, 0x00020000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR18) + } + If (LEqual(AP01, One)) { + Return (AH18) + } + Return (AR18) + } + + #include "PcieHp.asi" + #include "PcieNonHpDev.asi" + } + + // PCI Express Port 1D on PC01 + Device (BR1D) { + Name (_ADR, 0x00030000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR19) + } + If (LEqual(AP01, One)) { + Return (AH19) + } + Return (AR19) + } + + #include "PcieHp.asi" + #include "PcieNonHpDev.asi" + } + + // Uncore 1 CHAUTIL0-7 Device + Device (CHA0) { + Name (_ADR, 0x00080000) + } + + // Uncore 1 CHAUTIL8-15 Device + Device (CHA1) { + Name (_ADR, 0x00090000) + } + + // Uncore 1 CHAUTIL16-23 Device + Device (CHA2) { + Name (_ADR, 0x000A0000) + } + + // Uncore 1 CHAUTIL24-27 Device + Device (CHA3) { + Name (_ADR, 0x000B0000) + } + + // Uncore 1 CHASAD0-7 Device + Device (CHA4) { + Name (_ADR, 0x000E0000) + } + + // Uncore 1 CHASAD8-15 Device + Device (CHA5) { + Name (_ADR, 0x000F0000) + } + + // Uncore 1 CHASAD16-23 Device + Device (CHA6) { + Name (_ADR, 0x00100000) + } + + // Uncore 1 CHASAD24-27 Device + Device (CHA7) { + Name (_ADR, 0x00110000) + } + + // Uncore 1 CMSCHA0-7 Device + Device (CMS0) { + Name (_ADR, 0x00140000) + } + + // Uncore 1 CMS0CHA8-15 Device + Device (CMS1) { + Name (_ADR, 0x00150000) + } + + // Uncore 1 CMS0CHA16-23 Device + Device (CMS2) { + Name (_ADR, 0x00160000) + } + + // Uncore 1 CMS0CHA24-27 Device + Device (CMS3) { + Name (_ADR, 0x00170000) + } + + // Uncore 1 CHASADALL Device + Device (CDL0) { + Name (_ADR, 0x001D0000) + } + + // Uncore 1 PCUCR Devices + Device (PCU0) { + Name (_ADR, 0x001E0000) + } + + // Uncore 1 VCUCR Device + Device (VCU0) { + Name (_ADR, 0x001F0000) + } + } + + // Socket 0 Root bridge (Stack 2) + Device (PC02) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x02) + Method (_BBN, 0, NotSerialized) { + return (BB02) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR1A) + } + If (LEqual(AP02, One)) { + Return (AH1A) + } + Return (AR1A) + } + + #include "PC02.asi" + + // PCI Express Port 2A on PC02 + Device (BR2A) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR1B) + } + If (LEqual(AP02, One)) { + Return (AH1B) + } + Return (AR1B) + } + + #include "PcieHp.asi" + #include "PcieNonHpDev.asi" + + // EVA PCIe Uplink + Device (EPCU) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x0B, 0x00}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR1C) + } + If (LEqual(AP02, One)) { + Return (AH1C) + } + Return (AR1C) + } + + // EVA Virtual Switch Port 0 + Device (VSP0) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x0B, 0x00}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR1D) + } + If (LEqual(AP02, One)) { + Return (AH1D) + } + Return (AR1D) + } + + // EVA CPM0 + Device (CPM0) { + Name (_ADR, 0x00000000) + } + } + + // EVA Virtual Switch Port 1 + Device (VSP1) { + Name (_ADR, 0x00010000) + Method (_PRW, 0) { + Return (Package (0x02) {0x0B, 0x00}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR1E) + } + If (LEqual(AP02, One)) { + Return (AH1E) + } + Return (AR1E) + } + + // EVA CPM1 + Device (CPM1) { + Name (_ADR, 0x00000000) + } + } + + // EVA Virtual Switch Port 2 + Device (VSP2) { + Name (_ADR, 0x00020000) + Method (_PRW, 0) { + Return (Package (0x02) {0x0B, 0x00}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR1F) + } + If (LEqual(AP02, One)) { + Return (AH1F) + } + Return (AR1F) + } + + // EVA CPM2 + Device (CPM2) { + Name (_ADR, 0x00000000) + } + } + + // EVA Virtual Switch Port 3 + Device (VSP3) { + Name (_ADR, 0x00030000) + Method (_PRW, 0) { + Return (Package (0x02) {0x0B, 0x00}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR20) + } + If (LEqual(AP02, One)) { + Return (AH20) + } + Return (AR20) + } + + // EVA Fort Park 0 + Device (FPK0) { + Name (_ADR, 0x00000000) + } + + // EVA Fort Park 1 + Device (FPK1) { + Name (_ADR, 0x00000001) + } + + // EVA Fort Park 2 + Device (FPK2) { + Name (_ADR, 0x00000002) + } + + // EVA Fort Park 3 + Device (FPK3) { + Name (_ADR, 0x00000003) + } + } + } + } + + // PCI Express Port 2B on PC02 + Device (BR2B) { + Name (_ADR, 0x00010000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR21) + } + If (LEqual(AP02, One)) { + Return (AH21) + } + Return (AR21) + } + + #include "PcieHp.asi" + #include "PcieNonHpDev.asi" + } + + // PCI Express Port 2C on PC02 + Device (BR2C) { + Name (_ADR, 0x00020000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR22) + } + If (LEqual(AP02, One)) { + Return (AH22) + } + Return (AR22) + } + + #include "PcieHp.asi" + #include "PcieNonHpDev.asi" + } + + // PCI Express Port 2D on PC02 + Device (BR2D) { + Name (_ADR, 0x00030000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR23) + } + If (LEqual(AP02, One)) { + Return (AH23) + } + Return (AR23) + } + + #include "PcieHp.asi" + #include "PcieNonHpDev.asi" + } + + // Uncore 2 M2MEM0 Device + Device (M2M0) { + Name (_ADR, 0x00080000) + } + + // Uncore 2 M2MEM10 Device + Device (M2M1) { + Name (_ADR, 0x00090000) + } + + // Uncore 2 MCMAIN Device + Device (MCM0) { + Name (_ADR, 0x000A0000) + } + + // Uncore 2 MCDECS2 Device + Device (MCD0) { + Name (_ADR, 0x000B0000) + } + + // Uncore 2 MCMAIN Device + Device (MCM1) { + Name (_ADR, 0x000C0000) + } + + // Uncore 2 MCDECS12 Device + Device (MCD1) { + Name (_ADR, 0x000D0000) + } + + // Uncore 2 Unicast MC0 DDRIO0 Device + Device (UMC0) { + Name (_ADR, 0x00160000) + } + + // Uncore 2 Unicast MC1 DDRIO0 Device + Device (UMC1) { + Name (_ADR, 0x00170000) + } + } + + // Socket 0 Root bridge (Stack 3) + Device (PC03) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x03) + Method (_BBN, 0, NotSerialized) { + return (BB03) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR24) + } + If (LEqual(AP03, One)) { + Return (AH24) + } + Return (AR24) + } + + #include "PC03.asi" + + // PCI Express Port 3A on PC03 + Device (BR3A) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR25) + } + If (LEqual(AP03, One)) { + Return (AH25) + } + Return (AR25) + } + + #include "PcieHp.asi" + #include "PcieNonHpDev.asi" + } + + // PCI Express Port 3B on PC03 + Device (BR3B) { + Name (_ADR, 0x00010000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR26) + } + If (LEqual(AP03, One)) { + Return (AH26) + } + Return (AR26) + } + + #include "PcieHp.asi" + #include "PcieNonHpDev.asi" + } + + // PCI Express Port 3C on PC03 + Device (BR3C) { + Name (_ADR, 0x00020000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR27) + } + If (LEqual(AP03, One)) { + Return (AH27) + } + Return (AR27) + } + + #include "PcieHp.asi" + #include "PcieNonHpDev.asi" + } + + // PCI Express Port 3D on PC03 + Device (BR3D) { + Name (_ADR, 0x00030000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR28) + } + If (LEqual(AP03, One)) { + Return (AH28) + } + Return (AR28) + } + + #include "PcieHp.asi" + #include "PcieNonHpDev.asi" + } + + // KTI0 + Device (KTI0) { + Name (_ADR, 0x000E0000) + } + + // KTI1 + Device (KTI1) { + Name (_ADR, 0x000F0000) + } + + // KTI2 + Device (KTI2) { + Name (_ADR, 0x00100000) + } + + // M3K0 + Device (M3K0) { + Name (_ADR, 0x00120000) + } + + // M2U0 + Device (M2U0) { + Name (_ADR, 0x00150000) + } + + // M2D0 + Device (M2D0) { + Name (_ADR, 0x00160000) + } + + // M20 + Device (M20) { + Name (_ADR, 0x00170000) + } + } + + // Socket 0 Root bridge (Stack 4) + Device (PC04) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x04) + Method (_BBN, 0, NotSerialized) { + return (BB04) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR29) + } + If (LEqual(AP04, One)) { + Return (AH29) + } + Return (AR29) + } + + #include "PC04.asi" + + // PCI Express Port 4 on PC04 + Device (MCP0) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR2A) + } + If (LEqual(AP04, One)) { + Return (AH2A) + } + Return (AR2A) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + } + } + + // Socket 0 Root bridge (Stack 5) + Device (PC05) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x05) + Method (_BBN, 0, NotSerialized) { + return (BB05) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR2B) + } + If (LEqual(AP05, One)) { + Return (AH2B) + } + Return (AR2B) + } + + #include "PC05.asi" + + // PCI Express Port 5 on PC05 + Device (MCP1) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR2C) + } + If (LEqual(AP05, One)) { + Return (AH2C) + } + Return (AR2C) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + } + } + + // Socket 1 Root bridge (Stack 0) + Device (PC06) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x06) + Method (_BBN, 0, NotSerialized) { + return (BB06) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR2D) + } + If (LEqual(AP06, One)) { + Return (AH2D) + } + Return (AR2D) + } + + #include "PC06.asi" + #include "Sck1Ejd.asi" + + // PCI Express Port 0 on PC06 + Device (QRP0) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR2E) + } + If (LEqual(AP06, One)) { + Return (AH2E) + } + Return (AR2E) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC06Ejd.asi" + } + + // CB3DMA on PC06 + Device (CB1B) { + Name (_ADR, 0x00040001) + } + + // CB3DMA on PC06 + Device (CB1C) { + Name (_ADR, 0x00040002) + } + + // CB3DMA on PC06 + Device (CB1D) { + Name (_ADR, 0x00040003) + } + + // CB3DMA on PC06 + Device (CB1E) { + Name (_ADR, 0x00040004) + } + + // CB3DMA on PC06 + Device (CB1F) { + Name (_ADR, 0x00040005) + } + + // CB3DMA on PC06 + Device (CB1G) { + Name (_ADR, 0x00040006) + } + + // CB3DMA on PC06 + Device (CB1H) { + Name (_ADR, 0x00040007) + } + + // IIOMISC on PC01 + Device (IIM1) { + Name (_ADR, 0x00050000) + } + + // Uncore 4 UBOX Device + Device (UBX1) { + Name (_ADR, 0x00080000) + } + + // CB3DMA on PC06 + Device (CB1A) { + Name (_ADR, 0x00040000) + } + } + + // Socket 1 Root bridge (Stack 1) + Device (PC07) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x07) + Method (_BBN, 0, NotSerialized) { + return (BB07) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR2F) + } + If (LEqual(AP07, One)) { + Return (AH2F) + } + Return (AR2F) + } + + #include "PC07.asi" + #include "Sck1Ejd.asi" + + // PCI Express Port 1A on PC07 + Device (QR1A) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR30) + } + If (LEqual(AP07, One)) { + Return (AH30) + } + Return (AR30) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC06Ejd.asi" + } + + // PCI Express Port 1B on PC07 + Device (QR1B) { + Name (_ADR, 0x00010000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR31) + } + If (LEqual(AP07, One)) { + Return (AH31) + } + Return (AR31) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC06Ejd.asi" + } + + // PCI Express Port 1C on PC07 + Device (QR1C) { + Name (_ADR, 0x00020000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR32) + } + If (LEqual(AP07, One)) { + Return (AH32) + } + Return (AR32) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC06Ejd.asi" + } + + // PCI Express Port 1D on PC07 + Device (QR1D) { + Name (_ADR, 0x00030000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR33) + } + If (LEqual(AP07, One)) { + Return (AH33) + } + Return (AR33) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC06Ejd.asi" + } + + // Uncore 5 CHAUTIL0-7 Device + Device (CHB0) { + Name (_ADR, 0x00080000) + } + + // Uncore 5 CHAUTIL8-15 Device + Device (CHB1) { + Name (_ADR, 0x00090000) + } + + // Uncore 5 CHAUTIL16-23 Device + Device (CHB2) { + Name (_ADR, 0x000A0000) + } + + // Uncore 5 CHAUTIL24-27 Device + Device (CHB3) { + Name (_ADR, 0x000B0000) + } + + // Uncore 5 CHASAD0-7 Device + Device (CHB4) { + Name (_ADR, 0x000E0000) + } + + // Uncore 5 CHASAD8-15 Device + Device (CHB5) { + Name (_ADR, 0x000F0000) + } + + // Uncore 5 CHASAD16-23 Device + Device (CHB6) { + Name (_ADR, 0x00100000) + } + + // Uncore 5 CHASAD24-27 Device + Device (CHB7) { + Name (_ADR, 0x00110000) + } + + // Uncore 5 CMSCHA0-7 Device + Device (CMS4) { + Name (_ADR, 0x00140000) + } + + // Uncore 5 CMS0CHA8-15 Device + Device (CMS5) { + Name (_ADR, 0x00150000) + } + + // Uncore 5 CMS0CHA16-23 Device + Device (CMS6) { + Name (_ADR, 0x00160000) + } + + // Uncore 5 CMS0CHA24-27 Device + Device (CMS7) { + Name (_ADR, 0x00170000) + } + + // Uncore 5 CHASADALL Device + Device (CDL1) { + Name (_ADR, 0x001D0000) + } + + // Uncore 5 PCUCR Devices + Device (PCU1) { + Name (_ADR, 0x001E0000) + } + + // Uncore 5 VCUCR Device + Device (VCU1) { + Name (_ADR, 0x001F0000) + } + } + + // Socket 1 Root bridge (Stack 2) + Device (PC08) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x08) + Method (_BBN, 0, NotSerialized) { + return (BB08) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR34) + } + If (LEqual(AP08, One)) { + Return (AH34) + } + Return (AR34) + } + + #include "PC08.asi" + #include "Sck1Ejd.asi" + + // PCI Express Port 2A on PC08 + Device (QR2A) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR35) + } + If (LEqual(AP08, One)) { + Return (AH35) + } + Return (AR35) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC06Ejd.asi" + } + + // PCI Express Port 2B on PC08 + Device (QR2B) { + Name (_ADR, 0x00010000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR36) + } + If (LEqual(AP08, One)) { + Return (AH36) + } + Return (AR36) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC06Ejd.asi" + } + + // PCI Express Port 2C on PC08 + Device (QR2C) { + Name (_ADR, 0x00020000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR37) + } + If (LEqual(AP08, One)) { + Return (AH37) + } + Return (AR37) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC06Ejd.asi" + } + + // PCI Express Port 2D on PC08 + Device (QR2D) { + Name (_ADR, 0x00030000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR38) + } + If (LEqual(AP08, One)) { + Return (AH38) + } + Return (AR38) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC06Ejd.asi" + } + + // Uncore 6 M2MEM0 Device + Device (M2M2) { + Name (_ADR, 0x00080000) + } + + // Uncore 6 M2MEM10 Device + Device (M2M3) { + Name (_ADR, 0x00090000) + } + + // Uncore 6 MCMAIN Device + Device (MCM2) { + Name (_ADR, 0x000A0000) + } + + // Uncore 6 MCDECS2 Device + Device (MCD2) { + Name (_ADR, 0x000B0000) + } + + // Uncore 6 MCMAIN Device + Device (MCM3) { + Name (_ADR, 0x000C0000) + } + + // Uncore 6 MCDECS12 Device + Device (MCD3) { + Name (_ADR, 0x000D0000) + } + + // Uncore 6 Unicast MC0 DDRIO0 Device + Device (UMC2) { + Name (_ADR, 0x00160000) + } + + // Uncore 6 Unicast MC1 DDRIO0 Device + Device (UMC3) { + Name (_ADR, 0x00170000) + } + } + + // Socket 1 Root bridge (Stack 3) + Device (PC09) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x09) + Method (_BBN, 0, NotSerialized) { + return (BB09) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR39) + } + If (LEqual(AP09, One)) { + Return (AH39) + } + Return (AR39) + } + + #include "PC09.asi" + #include "Sck1Ejd.asi" + + // PCI Express Port 3A on PC09 + Device (QR3A) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR3A) + } + If (LEqual(AP09, One)) { + Return (AH3A) + } + Return (AR3A) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC06Ejd.asi" + } + + // PCI Express Port 3B on PC09 + Device (QR3B) { + Name (_ADR, 0x00010000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR3B) + } + If (LEqual(AP09, One)) { + Return (AH3B) + } + Return (AR3B) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC06Ejd.asi" + } + + // PCI Express Port 3C on PC09 + Device (QR3C) { + Name (_ADR, 0x00020000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR3C) + } + If (LEqual(AP09, One)) { + Return (AH3C) + } + Return (AR3C) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC06Ejd.asi" + } + + // PCI Express Port 3D on PC09 + Device (QR3D) { + Name (_ADR, 0x00030000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR3D) + } + If (LEqual(AP09, One)) { + Return (AH3D) + } + Return (AR3D) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC06Ejd.asi" + } + + // Uncore 7 KTI3 + Device (KTI3) { + Name (_ADR, 0x000E0000) + } + + // Uncore 7 KTI4 + Device (KTI4) { + Name (_ADR, 0x000F0000) + } + + // Uncore 7 KTI5 + Device (KTI5) { + Name (_ADR, 0x00100000) + } + + // Uncore 7 M3K1 + Device (M3K1) { + Name (_ADR, 0x00120000) + } + + // Uncore 7 M2U1 + Device (M2U1) { + Name (_ADR, 0x00150000) + } + + // Uncore 7 M2D1 + Device (M2D1) { + Name (_ADR, 0x00160000) + } + + // Uncore 7 M21 + Device (M21) { + Name (_ADR, 0x00170000) + } + } + + // Socket 1 Root bridge (Stack 4) + Device (PC10) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x0A) + Method (_BBN, 0, NotSerialized) { + return (BB10) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR3E) + } + If (LEqual(AP10, One)) { + Return (AH3E) + } + Return (AR3E) + } + + #include "PC10.asi" + #include "Sck1Ejd.asi" + + // PCI Express Port 13 on PC10 + Device (MCP2) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR3F) + } + If (LEqual(AP10, One)) { + Return (AH3F) + } + Return (AR3F) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC06Ejd.asi" + } + } + + // Socket 1 Root bridge (Stack 5) + Device (PC11) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x0B) + Method (_BBN, 0, NotSerialized) { + return (BB11) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR40) + } + If (LEqual(AP11, One)) { + Return (AH40) + } + Return (AR40) + } + + #include "PC11.asi" + #include "Sck1Ejd.asi" + + // PCI Express Port 14 on PC11 + Device (MCP3) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR41) + } + If (LEqual(AP11, One)) { + Return (AH41) + } + Return (AR41) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC06Ejd.asi" + } + } + + // Socket 2 Root bridge (Stack 0) + Device (PC12) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x0C) + Method (_BBN, 0, NotSerialized) { + return (BB12) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR42) + } + If (LEqual(AP12, One)) { + Return (AH42) + } + Return (AR42) + } + + #include "PC12.asi" + #include "Sck2Ejd.asi" + + // PCI Express Port 0 on PC12 + Device (RRP0) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR43) + } + If (LEqual(AP12, One)) { + Return (AH43) + } + Return (AR43) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC12Ejd.asi" + } + + // CB3DMA on PC12 + Device (CB2B) { + Name (_ADR, 0x00040001) + } + + // CB3DMA on PC12 + Device (CB2C) { + Name (_ADR, 0x00040002) + } + + // CB3DMA on PC12 + Device (CB2D) { + Name (_ADR, 0x00040003) + } + + // CB3DMA on PC12 + Device (CB2E) { + Name (_ADR, 0x00040004) + } + + // CB3DMA on PC12 + Device (CB2F) { + Name (_ADR, 0x00040005) + } + + // CB3DMA on PC12 + Device (CB2G) { + Name (_ADR, 0x00040006) + } + + // CB3DMA on PC12 + Device (CB2H) { + Name (_ADR, 0x00040007) + } + + // IIOMISC on PC02 + Device (IIM2) { + Name (_ADR, 0x00050000) + } + + // Uncore 8 UBOX Device + Device (UBX2) { + Name (_ADR, 0x00080000) + } + + // CB3DMA on PC12 + Device (CB2A) { + Name (_ADR, 0x00040000) + } + } + + // Socket 2 Root bridge (Stack 1) + Device (PC13) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x0D) + Method (_BBN, 0, NotSerialized) { + return (BB13) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR44) + } + If (LEqual(AP13, One)) { + Return (AH44) + } + Return (AR44) + } + + #include "PC13.asi" + #include "Sck2Ejd.asi" + + // PCI Express Port 1A on PC13 + Device (RR1A) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR45) + } + If (LEqual(AP13, One)) { + Return (AH45) + } + Return (AR45) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC12Ejd.asi" + } + + // PCI Express Port 1B on PC13 + Device (RR1B) { + Name (_ADR, 0x00010000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR46) + } + If (LEqual(AP13, One)) { + Return (AH46) + } + Return (AR46) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC12Ejd.asi" + } + + // PCI Express Port 1C on PC13 + Device (RR1C) { + Name (_ADR, 0x00020000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR47) + } + If (LEqual(AP13, One)) { + Return (AH47) + } + Return (AR47) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC12Ejd.asi" + } + + // PCI Express Port 1D on PC13 + Device (RR1D) { + Name (_ADR, 0x00030000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR48) + } + If (LEqual(AP13, One)) { + Return (AH48) + } + Return (AR48) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC12Ejd.asi" + } + + // Uncore 9 CHAUTIL0-7 Device + Device (CHC0) { + Name (_ADR, 0x00080000) + } + + // Uncore 9 CHAUTIL8-15 Device + Device (CHC1) { + Name (_ADR, 0x00090000) + } + + // Uncore 9 CHAUTIL16-23 Device + Device (CHC2) { + Name (_ADR, 0x000A0000) + } + + // Uncore 9 CHAUTIL24-27 Device + Device (CHC3) { + Name (_ADR, 0x000B0000) + } + + // Uncore 9 CHASAD0-7 Device + Device (CHC4) { + Name (_ADR, 0x000E0000) + } + + // Uncore 9 CHASAD8-15 Device + Device (CHC5) { + Name (_ADR, 0x000F0000) + } + + // Uncore 9 CHASAD16-23 Device + Device (CHC6) { + Name (_ADR, 0x00100000) + } + + // Uncore 9 CHASAD24-27 Device + Device (CHC7) { + Name (_ADR, 0x00110000) + } + + // Uncore 9 CMSCHA0-7 Device + Device (CMS8) { + Name (_ADR, 0x00140000) + } + + // Uncore 9 CMS0CHA8-15 Device + Device (CMS9) { + Name (_ADR, 0x00150000) + } + + // Uncore 9 CHASADALL Device + Device (CDL2) { + Name (_ADR, 0x001D0000) + } + + // Uncore 9 PCUCR Devices + Device (PCU2) { + Name (_ADR, 0x001E0000) + } + + // Uncore 9 VCUCR Device + Device (VCU2) { + Name (_ADR, 0x001F0000) + } + } + + // Socket 2 Root bridge (Stack 2) + Device (PC14) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x0E) + Method (_BBN, 0, NotSerialized) { + return (BB14) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR49) + } + If (LEqual(AP14, One)) { + Return (AH49) + } + Return (AR49) + } + + #include "PC14.asi" + #include "Sck2Ejd.asi" + + // PCI Express Port 2A on PC14 + Device (RR2A) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR4A) + } + If (LEqual(AP14, One)) { + Return (AH4A) + } + Return (AR4A) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC12Ejd.asi" + } + + // PCI Express Port 2B on PC14 + Device (RR2B) { + Name (_ADR, 0x00010000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR4B) + } + If (LEqual(AP14, One)) { + Return (AH4B) + } + Return (AR4B) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC12Ejd.asi" + } + + // PCI Express Port 2C on PC14 + Device (RR2C) { + Name (_ADR, 0x00020000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR4C) + } + If (LEqual(AP14, One)) { + Return (AH4C) + } + Return (AR4C) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC12Ejd.asi" + } + + // PCI Express Port 2D on PC14 + Device (RR2D) { + Name (_ADR, 0x00030000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR4D) + } + If (LEqual(AP14, One)) { + Return (AH4D) + } + Return (AR4D) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC12Ejd.asi" + } + + // Uncore 10 M2MEM0 Device + Device (M2M4) { + Name (_ADR, 0x00080000) + } + + // Uncore 10 M2MEM10 Device + Device (M2M5) { + Name (_ADR, 0x00090000) + } + + // Uncore 10 MCMAIN Device + Device (MCM4) { + Name (_ADR, 0x000A0000) + } + + // Uncore 10 MCDECS2 Device + Device (MCD4) { + Name (_ADR, 0x000B0000) + } + + // Uncore 10 MCMAIN Device + Device (MCM5) { + Name (_ADR, 0x000C0000) + } + + // Uncore 10 MCDECS12 Device + Device (MCD5) { + Name (_ADR, 0x000D0000) + } + + // Uncore 10 Unicast MC0 DDRIO0 Device + Device (UMC4) { + Name (_ADR, 0x00160000) + } + + // Uncore 10 Unicast MC1 DDRIO0 Device + Device (UMC5) { + Name (_ADR, 0x00170000) + } + } + + // Socket 2 Root bridge (Stack 3) + Device (PC15) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x0F) + Method (_BBN, 0, NotSerialized) { + return (BB15) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR4E) + } + If (LEqual(AP15, One)) { + Return (AH4E) + } + Return (AR4E) + } + + #include "PC15.asi" + #include "Sck2Ejd.asi" + + // PCI Express Port 3A on PC15 + Device (RR3A) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR4F) + } + If (LEqual(AP15, One)) { + Return (AH4F) + } + Return (AR4F) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC12Ejd.asi" + } + + // PCI Express Port 3B on PC15 + Device (RR3B) { + Name (_ADR, 0x00010000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR50) + } + If (LEqual(AP15, One)) { + Return (AH50) + } + Return (AR50) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC12Ejd.asi" + } + + // PCI Express Port 3C on PC15 + Device (RR3C) { + Name (_ADR, 0x00020000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR51) + } + If (LEqual(AP15, One)) { + Return (AH51) + } + Return (AR51) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC12Ejd.asi" + } + + // PCI Express Port 3D on PC15 + Device (RR3D) { + Name (_ADR, 0x00030000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR52) + } + If (LEqual(AP15, One)) { + Return (AH52) + } + Return (AR52) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC12Ejd.asi" + } + + // Uncore 11 KTI6 + Device (KTI6) { + Name (_ADR, 0x000E0000) + } + + // Uncore 11 KTI7 + Device (KTI7) { + Name (_ADR, 0x000F0000) + } + + // Uncore 11 KTI8 + Device (KTI8) { + Name (_ADR, 0x00100000) + } + + // Uncore 11 M3K2 + Device (M3K2) { + Name (_ADR, 0x00120000) + } + + // Uncore 11 M2U2 + Device (M2U2) { + Name (_ADR, 0x00150000) + } + + // Uncore 11 M2D2 + Device (M2D2) { + Name (_ADR, 0x00160000) + } + + // Uncore 11 M22 + Device (M22) { + Name (_ADR, 0x00170000) + } + } + + // Socket 2 Root bridge (Stack 4) + Device (PC16) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x10) + Method (_BBN, 0, NotSerialized) { + return (BB16) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR53) + } + If (LEqual(AP16, One)) { + Return (AH53) + } + Return (AR53) + } + + #include "PC16.asi" + #include "Sck2Ejd.asi" + + // PCI Express Port 4 on PC16 + Device (MCP4) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR54) + } + If (LEqual(AP16, One)) { + Return (AH54) + } + Return (AR54) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC12Ejd.asi" + } + } + + // Socket 2 Root bridge (Stack 5) + Device (PC17) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x11) + Method (_BBN, 0, NotSerialized) { + return (BB17) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR55) + } + If (LEqual(AP17, One)) { + Return (AH55) + } + Return (AR55) + } + + #include "PC17.asi" + #include "Sck2Ejd.asi" + + // PCI Express Port 5 on PC17 + Device (MCP5) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR56) + } + If (LEqual(AP17, One)) { + Return (AH56) + } + Return (AR56) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC12Ejd.asi" + } + } + + // Socket 3 Root bridge (Stack 0) + Device (PC18) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x12) + Method (_BBN, 0, NotSerialized) { + return (BB18) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR57) + } + If (LEqual(AP18, One)) { + Return (AH57) + } + Return (AR57) + } + + #include "PC18.asi" + #include "Sck3Ejd.asi" + + // PCI Express Port 0 on PC18 + Device (SRP0) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR58) + } + If (LEqual(AP18, One)) { + Return (AH58) + } + Return (AR58) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC18Ejd.asi" + } + + // CB3DMA on PC18 + Device (CB3B) { + Name (_ADR, 0x00040001) + } + + // CB3DMA on PC18 + Device (CB3C) { + Name (_ADR, 0x00040002) + } + + // CB3DMA on PC18 + Device (CB3D) { + Name (_ADR, 0x00040003) + } + + // CB3DMA on PC18 + Device (CB3E) { + Name (_ADR, 0x00040004) + } + + // CB3DMA on PC18 + Device (CB3F) { + Name (_ADR, 0x00040005) + } + + // CB3DMA on PC18 + Device (CB3G) { + Name (_ADR, 0x00040006) + } + + // CB3DMA on PC18 + Device (CB3H) { + Name (_ADR, 0x00040007) + } + + // IIOMISC on PC03 + Device (IIM3) { + Name (_ADR, 0x00050000) + } + + // Uncore 12 UBOX Device + Device (UBX3) { + Name (_ADR, 0x00080000) + } + + // CB3DMA on PC18 + Device (CB3A) { + Name (_ADR, 0x00040000) + } + } + + // Socket 3 Root bridge (Stack 1) + Device (PC19) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x13) + Method (_BBN, 0, NotSerialized) { + return (BB19) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR59) + } + If (LEqual(AP19, One)) { + Return (AH59) + } + Return (AR59) + } + + #include "PC19.asi" + #include "Sck3Ejd.asi" + + // PCI Express Port 1A on PC19 + Device (SR1A) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR5A) + } + If (LEqual(AP19, One)) { + Return (AH5A) + } + Return (AR5A) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC18Ejd.asi" + } + + // PCI Express Port 1B on PC19 + Device (SR1B) { + Name (_ADR, 0x00010000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR5B) + } + If (LEqual(AP19, One)) { + Return (AH5B) + } + Return (AR5B) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC18Ejd.asi" + } + + // PCI Express Port 1C on PC19 + Device (SR1C) { + Name (_ADR, 0x00020000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR5C) + } + If (LEqual(AP19, One)) { + Return (AH5C) + } + Return (AR5C) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC18Ejd.asi" + } + + // PCI Express Port 1D on PC19 + Device (SR1D) { + Name (_ADR, 0x00030000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR5D) + } + If (LEqual(AP19, One)) { + Return (AH5D) + } + Return (AR5D) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC18Ejd.asi" + } + + // Uncore 13 CHAUTIL0-7 Device + Device (CHD0) { + Name (_ADR, 0x00080000) + } + + // Uncore 13 CHAUTIL8-15 Device + Device (CHD1) { + Name (_ADR, 0x00090000) + } + + // Uncore 13 CHAUTIL16-23 Device + Device (CHD2) { + Name (_ADR, 0x000A0000) + } + + // Uncore 13 CHAUTIL24-27 Device + Device (CHD3) { + Name (_ADR, 0x000B0000) + } + + // Uncore 13 CHASAD0-7 Device + Device (CHD4) { + Name (_ADR, 0x000E0000) + } + + // Uncore 13 CHASAD8-15 Device + Device (CHD5) { + Name (_ADR, 0x000F0000) + } + + // Uncore 13 CHASAD16-23 Device + Device (CHD6) { + Name (_ADR, 0x00100000) + } + + // Uncore 13 CHASAD24-27 Device + Device (CHD7) { + Name (_ADR, 0x00110000) + } + + // Uncore 13 CMSCHA0-7 Device + Device (CM12) { + Name (_ADR, 0x00140000) + } + + // Uncore 13 CMS0CHA8-15 Device + Device (CM13) { + Name (_ADR, 0x00150000) + } + + // Uncore 13 CMS0CHA16-23 Device + Device (CM14) { + Name (_ADR, 0x00160000) + } + + // Uncore 13 CMS0CHA24-27 Device + Device (CM15) { + Name (_ADR, 0x00170000) + } + + // Uncore 13 CHASADALL Device + Device (CDL3) { + Name (_ADR, 0x001D0000) + } + + // Uncore 13 PCUCR Devices + Device (PCU3) { + Name (_ADR, 0x001E0000) + } + + // Uncore 13 VCUCR Device + Device (VCU3) { + Name (_ADR, 0x001F0000) + } + } + + // Socket 3 Root bridge (Stack 2) + Device (PC20) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x14) + Method (_BBN, 0, NotSerialized) { + return (BB20) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR5E) + } + If (LEqual(AP20, One)) { + Return (AH5E) + } + Return (AR5E) + } + + #include "PC20.asi" + #include "Sck3Ejd.asi" + + // PCI Express Port 2A on PC20 + Device (SR2A) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR5F) + } + If (LEqual(AP20, One)) { + Return (AH5F) + } + Return (AR5F) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC18Ejd.asi" + } + + // PCI Express Port 2B on PC20 + Device (SR2B) { + Name (_ADR, 0x00010000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR60) + } + If (LEqual(AP20, One)) { + Return (AH60) + } + Return (AR60) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC18Ejd.asi" + } + + // PCI Express Port 2C on PC20 + Device (SR2C) { + Name (_ADR, 0x00020000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR61) + } + If (LEqual(AP20, One)) { + Return (AH61) + } + Return (AR61) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC18Ejd.asi" + } + + // PCI Express Port 2D on PC20 + Device (SR2D) { + Name (_ADR, 0x00030000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR62) + } + If (LEqual(AP20, One)) { + Return (AH62) + } + Return (AR62) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC18Ejd.asi" + } + + // Uncore 14 M2MEM0 Device + Device (M2M6) { + Name (_ADR, 0x00080000) + } + + // Uncore 14 M2MEM10 Device + Device (M2M7) { + Name (_ADR, 0x00090000) + } + + // Uncore 14 MCMAIN Device + Device (MCM6) { + Name (_ADR, 0x000A0000) + } + + // Uncore 14 MCDECS2 Device + Device (MCD6) { + Name (_ADR, 0x000B0000) + } + + // Uncore 14 MCMAIN Device + Device (MCM7) { + Name (_ADR, 0x000C0000) + } + + // Uncore 14 MCDECS12 Device + Device (MCD7) { + Name (_ADR, 0x000D0000) + } + + // Uncore 14 Unicast MC0 DDRIO0 Device + Device (UMC6) { + Name (_ADR, 0x00160000) + } + + // Uncore 14 Unicast MC1 DDRIO0 Device + Device (UMC7) { + Name (_ADR, 0x00170000) + } + } + + // Socket 3 Root bridge (Stack 3) + Device (PC21) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x15) + Method (_BBN, 0, NotSerialized) { + return (BB21) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR63) + } + If (LEqual(AP21, One)) { + Return (AH63) + } + Return (AR63) + } + + #include "PC21.asi" + #include "Sck3Ejd.asi" + + // PCI Express Port 3A on PC21 + Device (SR3A) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR64) + } + If (LEqual(AP21, One)) { + Return (AH64) + } + Return (AR64) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC18Ejd.asi" + } + + // PCI Express Port 3B on PC21 + Device (SR3B) { + Name (_ADR, 0x00010000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR65) + } + If (LEqual(AP21, One)) { + Return (AH65) + } + Return (AR65) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC18Ejd.asi" + } + + // PCI Express Port 3C on PC21 + Device (SR3C) { + Name (_ADR, 0x00020000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR66) + } + If (LEqual(AP21, One)) { + Return (AH66) + } + Return (AR66) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC18Ejd.asi" + } + + // PCI Express Port 3D on PC21 + Device (SR3D) { + Name (_ADR, 0x00030000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR67) + } + If (LEqual(AP21, One)) { + Return (AH67) + } + Return (AR67) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC18Ejd.asi" + } + + // Uncore 15 KTI9 + Device (KTI9) { + Name (_ADR, 0x000E0000) + } + + // Uncore 15 KT10 + Device (KT10) { + Name (_ADR, 0x000F0000) + } + + // Uncore 15 KT11 + Device (KT11) { + Name (_ADR, 0x00100000) + } + + // Uncore 15 M3K3 + Device (M3K3) { + Name (_ADR, 0x00120000) + } + + // Uncore 15 M2U3 + Device (M2U3) { + Name (_ADR, 0x00150000) + } + + // Uncore 15 M2D3 + Device (M2D3) { + Name (_ADR, 0x00160000) + } + + // Uncore 15 M23 + Device (M23) { + Name (_ADR, 0x00170000) + } + } + + // Socket 3 Root bridge (Stack 4) + Device (PC22) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x16) + Method (_BBN, 0, NotSerialized) { + return (BB22) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR68) + } + If (LEqual(AP22, One)) { + Return (AH68) + } + Return (AR68) + } + + #include "PC22.asi" + #include "Sck3Ejd.asi" + + // PCI Express Port 4 on PC22 + Device (MCP6) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR69) + } + If (LEqual(AP22, One)) { + Return (AH69) + } + Return (AR69) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC18Ejd.asi" + } + } + + // Socket 3 Root bridge (Stack 5) + Device (PC23) { + Name (_HID, EISAID("PNP0A08")) + Name (_CID, EISAID("PNP0A03")) + Name (_UID, 0x17) + Method (_BBN, 0, NotSerialized) { + return (BB23) + } + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR6A) + } + If (LEqual(AP23, One)) { + Return (AH6A) + } + Return (AR6A) + } + + #include "PC23.asi" + #include "Sck3Ejd.asi" + + // PCI Express Port 5 on PC23 + Device (MCP7) { + Name (_ADR, 0x00000000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR6B) + } + If (LEqual(AP23, One)) { + Return (AH6B) + } + Return (AR6B) + } + + #include "PcieHp.asi" + #include "PcieHpDev.asi" + #include "PC18Ejd.asi" + + } + } +} + +Scope (\_GPE) { + // [BR1A]: PCI Express Port 1A on PC01 + // [BR1B]: PCI Express Port 1B on PC01 + // [BR1C]: PCI Express Port 1C on PC01 + // [BR1D]: PCI Express Port 1D on PC01 + // [BR2A]: PCI Express Port 2A on PC02 + // [BR2B]: PCI Express Port 2B on PC02 + // [BR2C]: PCI Express Port 2C on PC02 + // [BR2D]: PCI Express Port 2D on PC02 + // [BR3A]: PCI Express Port 3A on PC03 + // [BR3B]: PCI Express Port 3B on PC03 + // [BR3C]: PCI Express Port 3C on PC03 + // [BR3D]: PCI Express Port 3D on PC03 + // [MCP0]: PCI Express Port 4 on PC04 + // [MCP1]: PCI Express Port 5 on PC05 + // [QRP0]: PCI Express Port 0 on PC06 + // [QR1A]: PCI Express Port 1A on PC07 + // [QR1B]: PCI Express Port 1B on PC07 + // [QR1C]: PCI Express Port 1C on PC07 + // [QR1D]: PCI Express Port 1D on PC07 + // [QR2A]: PCI Express Port 2A on PC08 + // [QR2B]: PCI Express Port 2B on PC08 + // [QR2C]: PCI Express Port 2C on PC08 + // [QR2D]: PCI Express Port 2D on PC08 + // [QR3A]: PCI Express Port 3A on PC09 + // [QR3B]: PCI Express Port 3B on PC09 + // [QR3C]: PCI Express Port 3C on PC09 + // [QR3D]: PCI Express Port 3D on PC09 + // [MCP2]: PCI Express Port 13 on PC10 + // [MCP3]: PCI Express Port 14 on PC11 + // [RRP0]: PCI Express Port 0 on PC12 + // [RR1A]: PCI Express Port 1A on PC13 + // [RR1B]: PCI Express Port 1B on PC13 + // [RR1C]: PCI Express Port 1C on PC13 + // [RR1D]: PCI Express Port 1D on PC13 + // [RR2A]: PCI Express Port 2A on PC14 + // [RR2B]: PCI Express Port 2B on PC14 + // [RR2C]: PCI Express Port 2C on PC14 + // [RR2D]: PCI Express Port 2D on PC14 + // [RR3A]: PCI Express Port 3A on PC15 + // [RR3B]: PCI Express Port 3B on PC15 + // [RR3C]: PCI Express Port 3C on PC15 + // [RR3D]: PCI Express Port 3D on PC15 + // [MCP4]: PCI Express Port 4 on PC16 + // [MCP5]: PCI Express Port 5 on PC17 + // [SRP0]: PCI Express Port 0 on PC18 + // [SR1A]: PCI Express Port 1A on PC19 + // [SR1B]: PCI Express Port 1B on PC19 + // [SR1C]: PCI Express Port 1C on PC19 + // [SR1D]: PCI Express Port 1D on PC19 + // [SR2A]: PCI Express Port 2A on PC20 + // [SR2B]: PCI Express Port 2B on PC20 + // [SR2C]: PCI Express Port 2C on PC20 + // [SR2D]: PCI Express Port 2D on PC20 + // [SR3A]: PCI Express Port 3A on PC21 + // [SR3B]: PCI Express Port 3B on PC21 + // [SR3C]: PCI Express Port 3C on PC21 + // [SR3D]: PCI Express Port 3D on PC21 + // [MCP6]: PCI Express Port 4 on PC22 + // [MCP7]: PCI Express Port 5 on PC23 + Method (_L09, 0x0, NotSerialized) { + #include "Gpe.asl" + Notify (\_SB.PC01.BR1A, 0x02) + Notify (\_SB.PC01.BR1B, 0x02) + Notify (\_SB.PC01.BR1C, 0x02) + Notify (\_SB.PC01.BR1D, 0x02) + Notify (\_SB.PC02.BR2A, 0x02) + Notify (\_SB.PC02.BR2B, 0x02) + Notify (\_SB.PC02.BR2C, 0x02) + Notify (\_SB.PC02.BR2D, 0x02) + Notify (\_SB.PC03.BR3A, 0x02) + Notify (\_SB.PC03.BR3B, 0x02) + Notify (\_SB.PC03.BR3C, 0x02) + Notify (\_SB.PC03.BR3D, 0x02) + Notify (\_SB.PC04.MCP0, 0x02) + Notify (\_SB.PC05.MCP1, 0x02) + Notify (\_SB.PC06.QRP0, 0x02) + Notify (\_SB.PC07.QR1A, 0x02) + Notify (\_SB.PC07.QR1B, 0x02) + Notify (\_SB.PC07.QR1C, 0x02) + Notify (\_SB.PC07.QR1D, 0x02) + Notify (\_SB.PC08.QR2A, 0x02) + Notify (\_SB.PC08.QR2B, 0x02) + Notify (\_SB.PC08.QR2C, 0x02) + Notify (\_SB.PC08.QR2D, 0x02) + Notify (\_SB.PC09.QR3A, 0x02) + Notify (\_SB.PC09.QR3B, 0x02) + Notify (\_SB.PC09.QR3C, 0x02) + Notify (\_SB.PC09.QR3D, 0x02) + Notify (\_SB.PC10.MCP2, 0x02) + Notify (\_SB.PC11.MCP3, 0x02) + Notify (\_SB.PC12.RRP0, 0x02) + Notify (\_SB.PC13.RR1A, 0x02) + Notify (\_SB.PC13.RR1B, 0x02) + Notify (\_SB.PC13.RR1C, 0x02) + Notify (\_SB.PC13.RR1D, 0x02) + Notify (\_SB.PC14.RR2A, 0x02) + Notify (\_SB.PC14.RR2B, 0x02) + Notify (\_SB.PC14.RR2C, 0x02) + Notify (\_SB.PC14.RR2D, 0x02) + Notify (\_SB.PC15.RR3A, 0x02) + Notify (\_SB.PC15.RR3B, 0x02) + Notify (\_SB.PC15.RR3C, 0x02) + Notify (\_SB.PC15.RR3D, 0x02) + Notify (\_SB.PC16.MCP4, 0x02) + Notify (\_SB.PC17.MCP5, 0x02) + Notify (\_SB.PC18.SRP0, 0x02) + Notify (\_SB.PC19.SR1A, 0x02) + Notify (\_SB.PC19.SR1B, 0x02) + Notify (\_SB.PC19.SR1C, 0x02) + Notify (\_SB.PC19.SR1D, 0x02) + Notify (\_SB.PC20.SR2A, 0x02) + Notify (\_SB.PC20.SR2B, 0x02) + Notify (\_SB.PC20.SR2C, 0x02) + Notify (\_SB.PC20.SR2D, 0x02) + Notify (\_SB.PC21.SR3A, 0x02) + Notify (\_SB.PC21.SR3B, 0x02) + Notify (\_SB.PC21.SR3C, 0x02) + Notify (\_SB.PC21.SR3D, 0x02) + Notify (\_SB.PC22.MCP6, 0x02) + Notify (\_SB.PC23.MCP7, 0x02) + } + + // [EPCU]: EVA PCIe Uplink + // [VSP0]: EVA Virtual Switch Port 0 + // [VSP1]: EVA Virtual Switch Port 1 + // [VSP2]: EVA Virtual Switch Port 2 + // [VSP3]: EVA Virtual Switch Port 3 + Method (_L0B, 0x0, NotSerialized) { + Notify (\_SB.PC02.BR2A.EPCU, 0x02) + Notify (\_SB.PC02.BR2A.EPCU.VSP0, 0x02) + Notify (\_SB.PC02.BR2A.EPCU.VSP1, 0x02) + Notify (\_SB.PC02.BR2A.EPCU.VSP2, 0x02) + Notify (\_SB.PC02.BR2A.EPCU.VSP3, 0x02) + } + +} + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck1Ejd.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck1Ejd.asi new file mode 100644 index 0000000000..4bb04b1e23 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck1Ejd.asi @@ -0,0 +1,15 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + // Eject device if SCK1 is removed. + Name(_EJD,"\\_SB.SCK1") // Dependent on SCK1 diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck2Ejd.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck2Ejd.asi new file mode 100644 index 0000000000..46da40ef3f --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck2Ejd.asi @@ -0,0 +1,15 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + // Eject device if SCK2 is removed. + Name(_EJD,"\\_SB.SCK2") // Dependent on SCK2 diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck3Ejd.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck3Ejd.asi new file mode 100644 index 0000000000..2c8608960b --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck3Ejd.asi @@ -0,0 +1,15 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + // Eject device if SCK3 is removed. + Name(_EJD,"\\_SB.SCK3") // Dependent on SCK3 diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore0.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore0.asi new file mode 100644 index 0000000000..c07eb6d288 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore0.asi @@ -0,0 +1,39 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (PRU0, Package() { + Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 } + }) + + Name (ARU0, Package() { + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 } + }) + + + Device (UNC0) { + Name (_UID, "UNCORE0") + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PRU0) + } + Return (ARU0) + } + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore1.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore1.asi new file mode 100644 index 0000000000..f404ff64c0 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore1.asi @@ -0,0 +1,181 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (PRU1, Package() { + Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + + Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x0011FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0011FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0011FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0011FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x0014FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0014FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0014FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0014FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x001DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x001DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x001DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x001DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x001EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x001EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x001EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x001EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x001FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x001FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x001FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x001FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + }) + + Name (ARU1, Package() { + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + + Package() { 0x0009FFFF, 0, 0, 16 }, + Package() { 0x0009FFFF, 1, 0, 17 }, + Package() { 0x0009FFFF, 2, 0, 18 }, + Package() { 0x0009FFFF, 3, 0, 19 }, + + Package() { 0x000AFFFF, 0, 0, 16 }, + Package() { 0x000AFFFF, 1, 0, 17 }, + Package() { 0x000AFFFF, 2, 0, 18 }, + Package() { 0x000AFFFF, 3, 0, 19 }, + + Package() { 0x000BFFFF, 0, 0, 16 }, + Package() { 0x000BFFFF, 1, 0, 17 }, + Package() { 0x000BFFFF, 2, 0, 18 }, + Package() { 0x000BFFFF, 3, 0, 19 }, + + Package() { 0x000EFFFF, 0, 0, 16 }, + Package() { 0x000EFFFF, 1, 0, 17 }, + Package() { 0x000EFFFF, 2, 0, 18 }, + Package() { 0x000EFFFF, 3, 0, 19 }, + + Package() { 0x000FFFFF, 0, 0, 16 }, + Package() { 0x000FFFFF, 1, 0, 17 }, + Package() { 0x000FFFFF, 2, 0, 18 }, + Package() { 0x000FFFFF, 3, 0, 19 }, + + Package() { 0x0010FFFF, 0, 0, 16 }, + Package() { 0x0010FFFF, 1, 0, 17 }, + Package() { 0x0010FFFF, 2, 0, 18 }, + Package() { 0x0010FFFF, 3, 0, 19 }, + + Package() { 0x0011FFFF, 0, 0, 16 }, + Package() { 0x0011FFFF, 1, 0, 17 }, + Package() { 0x0011FFFF, 2, 0, 18 }, + Package() { 0x0011FFFF, 3, 0, 19 }, + + Package() { 0x0014FFFF, 0, 0, 16 }, + Package() { 0x0014FFFF, 1, 0, 17 }, + Package() { 0x0014FFFF, 2, 0, 18 }, + Package() { 0x0014FFFF, 3, 0, 19 }, + + Package() { 0x0015FFFF, 0, 0, 16 }, + Package() { 0x0015FFFF, 1, 0, 17 }, + Package() { 0x0015FFFF, 2, 0, 18 }, + Package() { 0x0015FFFF, 3, 0, 19 }, + + Package() { 0x0016FFFF, 0, 0, 16 }, + Package() { 0x0016FFFF, 1, 0, 17 }, + Package() { 0x0016FFFF, 2, 0, 18 }, + Package() { 0x0016FFFF, 3, 0, 19 }, + + Package() { 0x0017FFFF, 0, 0, 16 }, + Package() { 0x0017FFFF, 1, 0, 17 }, + Package() { 0x0017FFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 3, 0, 19 }, + + Package() { 0x001DFFFF, 0, 0, 16 }, + Package() { 0x001DFFFF, 1, 0, 17 }, + Package() { 0x001DFFFF, 2, 0, 18 }, + Package() { 0x001DFFFF, 3, 0, 19 }, + + Package() { 0x001EFFFF, 0, 0, 16 }, + Package() { 0x001EFFFF, 1, 0, 17 }, + Package() { 0x001EFFFF, 2, 0, 18 }, + Package() { 0x001EFFFF, 3, 0, 19 }, + + Package() { 0x001FFFFF, 0, 0, 16 }, + Package() { 0x001FFFFF, 1, 0, 17 }, + Package() { 0x001FFFFF, 2, 0, 18 }, + Package() { 0x001FFFFF, 3, 0, 19 }, + }) + + // + // Devices 8 - 31 on PStack + // + Device (UNC1) { + Name (_UID, "UNCORE1") + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PRU1) + } + Return (ARU1) + } + } diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore2.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore2.asi new file mode 100644 index 0000000000..577a3c2537 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore2.asi @@ -0,0 +1,131 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (PRU2, Package() { + // + // PCIe2 PortA/NTB + // + Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x000CFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000CFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000CFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000CFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x000DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + + Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + }) + + Name (ARU2, Package() { + // + // PCIe2 PortA/NTB + // + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, + + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + + Package() { 0x0009FFFF, 0, 0, 16 }, + Package() { 0x0009FFFF, 1, 0, 17 }, + Package() { 0x0009FFFF, 2, 0, 18 }, + Package() { 0x0009FFFF, 3, 0, 19 }, + + Package() { 0x000AFFFF, 0, 0, 16 }, + Package() { 0x000AFFFF, 1, 0, 17 }, + Package() { 0x000AFFFF, 2, 0, 18 }, + Package() { 0x000AFFFF, 3, 0, 19 }, + + Package() { 0x000BFFFF, 0, 0, 16 }, + Package() { 0x000BFFFF, 1, 0, 17 }, + Package() { 0x000BFFFF, 2, 0, 18 }, + Package() { 0x000BFFFF, 3, 0, 19 }, + + Package() { 0x000CFFFF, 0, 0, 16 }, + Package() { 0x000CFFFF, 1, 0, 17 }, + Package() { 0x000CFFFF, 2, 0, 18 }, + Package() { 0x000CFFFF, 3, 0, 19 }, + + Package() { 0x000DFFFF, 0, 0, 16 }, + Package() { 0x000DFFFF, 1, 0, 17 }, + Package() { 0x000DFFFF, 2, 0, 18 }, + Package() { 0x000DFFFF, 3, 0, 19 }, + + + Package() { 0x0016FFFF, 0, 0, 16 }, + Package() { 0x0016FFFF, 1, 0, 17 }, + Package() { 0x0016FFFF, 2, 0, 18 }, + Package() { 0x0016FFFF, 3, 0, 19 }, + + Package() { 0x0017FFFF, 0, 0, 16 }, + Package() { 0x0017FFFF, 1, 0, 17 }, + Package() { 0x0017FFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 3, 0, 19 }, + + }) + + // + // Devices 8 - 31 on each stack + // + Device (UNC2) { + Name (_UID, "UNCORE2") + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PRU2) + } + Return (ARU2) + } + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore3.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore3.asi new file mode 100644 index 0000000000..7f20255d04 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore3.asi @@ -0,0 +1,104 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name (PRU3, Package() { + + Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + + Package() { 0x0012FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0012FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0012FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0012FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 }, + Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 }, + Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 }, + Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }, + + }) + + Name (ARU3, Package() { + Package() { 0x000EFFFF, 0, 0, 16 }, + Package() { 0x000EFFFF, 1, 0, 17 }, + Package() { 0x000EFFFF, 2, 0, 18 }, + Package() { 0x000EFFFF, 3, 0, 19 }, + + Package() { 0x000FFFFF, 0, 0, 16 }, + Package() { 0x000FFFFF, 1, 0, 17 }, + Package() { 0x000FFFFF, 2, 0, 18 }, + Package() { 0x000FFFFF, 3, 0, 19 }, + + Package() { 0x0010FFFF, 0, 0, 16 }, + Package() { 0x0010FFFF, 1, 0, 17 }, + Package() { 0x0010FFFF, 2, 0, 18 }, + Package() { 0x0010FFFF, 3, 0, 19 }, + + Package() { 0x0012FFFF, 0, 0, 16 }, + Package() { 0x0012FFFF, 1, 0, 17 }, + Package() { 0x0012FFFF, 2, 0, 18 }, + Package() { 0x0012FFFF, 3, 0, 19 }, + + Package() { 0x0015FFFF, 0, 0, 16 }, + Package() { 0x0015FFFF, 1, 0, 17 }, + Package() { 0x0015FFFF, 2, 0, 18 }, + Package() { 0x0015FFFF, 3, 0, 19 }, + + Package() { 0x0016FFFF, 0, 0, 16 }, + Package() { 0x0016FFFF, 1, 0, 17 }, + Package() { 0x0016FFFF, 2, 0, 18 }, + Package() { 0x0016FFFF, 3, 0, 19 }, + + Package() { 0x0017FFFF, 0, 0, 16 }, + Package() { 0x0017FFFF, 1, 0, 17 }, + Package() { 0x0017FFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 3, 0, 19 }, + }) + + // + // Devices 8 - 31 on each stack + // + Device (UNC3) { + Name (_UID, "UNCORE3") + Name (_ADR, 0x00000000) + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PRU3) + } + Return (ARU3) + } + } + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/WFPPlatform.asl b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/WFPPlatform.asl new file mode 100644 index 0000000000..d995817140 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/WFPPlatform.asl @@ -0,0 +1,195 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +DefinitionBlock ("WFPPlatform.asl","DSDT",2,"INTEL","PLATWFP ",3) +{ + + #include "CommonPlatform.asi" + #include "PlatformPciTree_WFP.asi" + #include "AMLUPD.asl" + #include "DSDT.ASL" + #include "Pch.asl" //This is in another package (PchPkg) + #include "Platform.asl" + #include "PlatformGpe.asi" + #include "PcieSeg.asi" + + Scope (\_SB.PC00.XHCI.RHUB) { + + + + // + // Method for creating generic _PLD buffers + // _PLD contains lots of data, but for purpose of internal validation we care only about + // ports' visibility and pairing (this requires group position) + // so these are the only 2 configurable parameters (User Visible, Group Position) + // + Method(GPLD, 2, Serialized) { + Name(PCKG, Package() { Buffer(0x10) {} } ) + CreateField(DerefOf(Index(PCKG,0)), 0, 7, REV) + Store(1,REV) + CreateField(DerefOf(Index(PCKG,0)), 64, 1, VISI) + Store(Arg0, VISI) + CreateField(DerefOf(Index(PCKG,0)), 87, 8, GPOS) + Store(Arg1, GPOS) + + + return (PCKG) + } + + // + // Method for creating generic _UPC buffers + // Similar to _PLD, for internal testing we only care about 1 parameter (port connectable) + // + Method(GUPC, 1, Serialized) { + Name(PCKG, Package(4) { 0, 0xFF, 0, 0 } ) + Store(Arg0,Index(PCKG,0)) + + + return (PCKG) + } + + + + } //end scope RHUB + + Scope (\_SB.PC00.XHCI.RHUB.HS01) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,1)) } //Rear Panel A [CONN27] - Upper - usb2 port + } + + Scope (\_SB.PC00.XHCI.RHUB.HS02) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,2)) } //Rear Panel A [CONN27] - Center - usb2 port + } + + Scope (\_SB.PC00.XHCI.RHUB.HS03) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,3)) } //Rear Panel A [CONN27] - Bottom - usb2 port + } + + Scope (\_SB.PC00.XHCI.RHUB.HS04) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,4)) } //Internal A1 [CONN9] - Right - usb2 port + } + + Scope (\_SB.PC00.XHCI.RHUB.HS05) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,5)) } //Front Panel [CONN20] - Right - usb2 port + } + + Scope (\_SB.PC00.XHCI.RHUB.HS06) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,6)) } //Front Panel [CONN20] - Left - usb2 port + } + + Scope (\_SB.PC00.XHCI.RHUB.HS07) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,7)) } //Internal Type A3 [CONN4] - ? - usb2 port + } + + Scope (\_SB.PC00.XHCI.RHUB.HS08) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,8)) } //Internal Type A3 [CONN4] - ? - usb2 port + } + + Scope (\_SB.PC00.XHCI.RHUB.HS09) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,9)) } //Jacksonville [CONN22] - Bottom - usb2 port + } + + Scope (\_SB.PC00.XHCI.RHUB.HS10) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,10)) } //Usb daughter card [CONN14] - ? - usb2 port + } + + Scope (\_SB.PC00.XHCI.RHUB.HS11) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(0,11)) } //Jacksonville [CONN22] - Center - usb2 port + } + + Scope (\_SB.PC00.XHCI.RHUB.HS12) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(0,12)) } //Usb daughter card [CONN14] - ? - usb2 port + } + + Scope (\_SB.PC00.XHCI.RHUB.HS13) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,13)) } //Internal A1 [CONN4] - Left - usb2 port + } + + Scope (\_SB.PC00.XHCI.RHUB.HS14) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,14)) } //Usb daughter card [CONN14] - ? - usb2 port + } + + Scope (\_SB.PC00.XHCI.RHUB.USR1) { + Method(_UPC) { Return (GUPC(0)) } + Method(_PLD) { Return (GPLD(0,0)) } + } + + Scope (\_SB.PC00.XHCI.RHUB.USR2) { + Method(_UPC) { Return (GUPC(0)) } + Method(_PLD) { Return (GPLD(0,0)) } + } + + Scope (\_SB.PC00.XHCI.RHUB.SS01) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,1)) } //Rear Panel A [CONN27] - Upper - usb3 port + } + + Scope (\_SB.PC00.XHCI.RHUB.SS02) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,2)) } //Rear Panel A [CONN27] - Center - usb3 port + } + + Scope (\_SB.PC00.XHCI.RHUB.SS03) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,3)) } //Rear Panel A [CONN27] - Bottom - usb3 port + } + + Scope (\_SB.PC00.XHCI.RHUB.SS04) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,4)) } //Internal A1 [CONN9] - Right - usb3 port + } + + Scope (\_SB.PC00.XHCI.RHUB.SS05) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,5)) } //Front Panel [CONN20] - Right - usb3 port + } + + Scope (\_SB.PC00.XHCI.RHUB.SS06) { + Method(_UPC) { Return (GUPC(1)) } + Method(_PLD) { Return (GPLD(1,6)) } //Front Panel [CONN20] - Left - usb3 port + } + + Scope (\_SB.PC00.XHCI.RHUB.SS07) { + Method(_UPC) { Return (GUPC(0)) } + Method(_PLD) { Return (GPLD(0,0)) } //N/A + } + + Scope (\_SB.PC00.XHCI.RHUB.SS08) { + Method(_UPC) { Return (GUPC(0)) } + Method(_PLD) { Return (GPLD(0,0)) } //N/A + } + + Scope (\_SB.PC00.XHCI.RHUB.SS09) { + Method(_UPC) { Return (GUPC(0)) } + Method(_PLD) { Return (GPLD(0,0)) } //N/A + } + + Scope (\_SB.PC00.XHCI.RHUB.SS10) { + Method(_UPC) { Return (GUPC(0)) } + Method(_PLD) { Return (GPLD(0,0)) } //N/A + } + +} // end of DSDT diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/GitEdk2MinMtOlympus.bat b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/GitEdk2MinMtOlympus.bat new file mode 100644 index 0000000000..d1d488c131 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/GitEdk2MinMtOlympus.bat @@ -0,0 +1,86 @@ +@REM @file +@REM +@REM Copyright (c) 2018, Intel Corporation. All rights reserved.
+@REM This program and the accompanying materials +@REM are licensed and made available under the terms and conditions of the BSD License +@REM which accompanies this distribution. The full text of the license may be found at +@REM http://opensource.org/licenses/bsd-license.php +@REM +@REM THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +@REM WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +@REM + +@echo off + +pushd ..\..\..\..\..\ + +@REM Set WORKSPACE environment. +set WORKSPACE=%cd% +echo. +echo Set WORKSPACE as: %WORKSPACE% +echo. + +@REM Check whether Git has been installed and been added to system path. +git --help >nul 2>nul +if %ERRORLEVEL% NEQ 0 ( + echo. + echo The 'git' command is not recognized. + echo Please make sure that Git is installed and has been added to system path. + echo. + goto :EOF +) + +@REM Create the Conf directory under WORKSPACE +if not exist %WORKSPACE%\Conf ( + mkdir Conf +) + +@REM Set other environments. +@REM Basic Rule: +@REM Platform override Silicon override Core +@REM Source override Binary + +set PACKAGES_PATH=%WORKSPACE%\edk2-platforms\Platform\Intel;%WORKSPACE%\edk2-platforms\Silicon\Intel;%WORKSPACE%\edk2-non-osi\Silicon\Intel;%WORKSPACE%\edk2;%WORKSPACE% + +set EDK_TOOLS_BIN=%WORKSPACE%\edk2-BaseTools-win32 + +@if not defined PYTHON_HOME ( + @if exist C:\Python27 ( + set PYTHON_HOME=C:\Python27 + ) +) + +set EDK_SETUP_OPTION= +@rem if python is installed, disable the binary base tools. +if defined PYTHON_HOME ( + set EDK_TOOLS_BIN= + set EDK_SETUP_OPTION=--nt32 +) +pushd %WORKSPACE%\edk2 +call edksetup.bat %EDK_SETUP_OPTION% +popd +pushd %WORKSPACE% +@rem if python is installed, nmake BaseTools source and enable BaseTools source build +@if defined PYTHON_HOME ( + nmake -f %BASE_TOOLS_PATH%\Makefile +) +popd + +set openssl_path=%WORKSPACE% + +popd + +goto :EOF + +:Help +echo. +echo Usage: +echo GitEdk2.bat [-w Workspace_Directory] (optional) [-b Branch_Name] (optional) +echo. +echo -w A absolute/relative path to be the workspace. +echo Default value is the current directory. +echo. +echo -b The branch name of the repository. Currently, only master, udk2015, +echo trunk (same as master) and bp13 (same as udk2015) are supported. +echo Default value is master. +echo. diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BasePlatformHookLib/BasePlatformHookLib.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BasePlatformHookLib/BasePlatformHookLib.c new file mode 100644 index 0000000000..038fe7ad71 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BasePlatformHookLib/BasePlatformHookLib.c @@ -0,0 +1,300 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include + +#define R_ICH_IOPORT_PCI_INDEX 0xCF8 +#define R_ICH_IOPORT_PCI_DATA 0xCFC +#define R_ICH_LPC_IO_DEC 0x80 + +#define PCI_DEVICE_NUMBER_ICH_LPC 31 +#define PCI_FUNCTION_NUMBER_ICH_LPC 0 + +#define PCI_CF8_ADDR(Bus, Dev, Func, Off) \ + (((Off) & 0xFF) | (((Func) & 0x07) << 8) | (((Dev) & 0x1F) << 11) | (((Bus) & 0xFF) << 16) | (1 << 31)) +#define ICH_LPC_CF8_ADDR(Offset) PCI_CF8_ADDR(0, PCI_DEVICE_NUMBER_ICH_LPC, PCI_FUNCTION_NUMBER_ICH_LPC, Offset) + +#include "SioRegs.h" + +#include +#include + +// +// --------------------------------------------- +// UART Register Offsets +// --------------------------------------------- +// +#define BAUD_LOW_OFFSET 0x00 +#define BAUD_HIGH_OFFSET 0x01 +#define IER_OFFSET 0x01 +#define LCR_SHADOW_OFFSET 0x01 +#define FCR_SHADOW_OFFSET 0x02 +#define IR_CONTROL_OFFSET 0x02 +#define FCR_OFFSET 0x02 +#define EIR_OFFSET 0x02 +#define BSR_OFFSET 0x03 +#define LCR_OFFSET 0x03 +#define MCR_OFFSET 0x04 +#define LSR_OFFSET 0x05 +#define MSR_OFFSET 0x06 + +// +// --------------------------------------------- +// UART Register Bit Defines +// --------------------------------------------- +// +#define LSR_TXRDY 0x20 +#define LSR_RXDA 0x01 +#define DLAB 0x01 + +#define UART_DATA 8 +#define UART_STOP 1 +#define UART_PARITY 0 +#define UART_BREAK_SET 0 + +UINT16 gComBase = 0x3f8; +UINTN gBps = 115200; +UINT8 gData = 8; +UINT8 gStop = 1; +UINT8 gParity = 0; +UINT8 gBreakSet = 0; + + +/** + + Read AHB register. + + @param RegIndex: register index. + + @retval value of register. + +**/ +UINT32 +ReadAHBDword( + UINT32 RegIndex +){ + UINT8 bValue; + UINT32 rdValue = 0; + + IoWrite8 (SIO_INDEX_PORT, REG_LOGICAL_DEVICE); + IoWrite8 (0xED, 0);//short delay. + IoWrite8 (SIO_DATA_PORT, SIO_SMI); + IoWrite8 (0xED, 0);//short delay. + + IoWrite8 (SIO_INDEX_PORT, 0x30); + IoWrite8 (0xED, 0);//short delay. + IoWrite8 (SIO_DATA_PORT, 1); + IoWrite8 (0xED, 0);//short delay. + + IoWrite8 (SIO_INDEX_PORT, 0xf8); + bValue = IoRead8(SIO_DATA_PORT); + bValue &= 0xfc; + bValue |= 2; // 4 byte window. + IoWrite8 (SIO_DATA_PORT, bValue); + IoWrite8 (0xED, 0);//short delay. + + IoWrite8 (SIO_INDEX_PORT, 0xf0); + IoWrite8 (0xED, 0);//short delay. + IoWrite8 (SIO_DATA_PORT, (UINT8)((RegIndex >> 24)& 0xff)); + + IoWrite8 (SIO_INDEX_PORT, 0xf1); + IoWrite8 (0xED, 0);//short delay. + IoWrite8 (SIO_DATA_PORT, (UINT8)((RegIndex >> 16)& 0xff)); + + IoWrite8 (SIO_INDEX_PORT, 0xf2); + IoWrite8 (0xED, 0);//short delay. + IoWrite8 (SIO_DATA_PORT, (UINT8)((RegIndex >> 8) & 0xff)); + + IoWrite8 (SIO_INDEX_PORT, 0xf3); + IoWrite8 (0xED, 0);//short delay. + IoWrite8 (SIO_DATA_PORT, (UINT8)((RegIndex )& 0xff)); + + // trigger read + IoWrite8 (SIO_INDEX_PORT, 0xfe); + IoRead8 (SIO_DATA_PORT); + + + IoWrite8 (SIO_INDEX_PORT, 0xf4); + rdValue += IoRead8 (SIO_DATA_PORT); + rdValue <<= 8; + + IoWrite8 (SIO_INDEX_PORT, 0xf5); + rdValue += IoRead8 (SIO_DATA_PORT); + rdValue <<= 8; + + IoWrite8 (SIO_INDEX_PORT, 0xf6); + rdValue += IoRead8 (SIO_DATA_PORT); + rdValue <<= 8; + + IoWrite8 (SIO_INDEX_PORT, 0xf7); + rdValue += IoRead8 (SIO_DATA_PORT); + + + return rdValue; + +} + + +/** + + GC_TODO: add routine description + + @param Exist - GC_TODO: add arg description + + @retval RETURN_SUCCESS - GC_TODO: add retval description + +**/ +UINT32 +IsSioExist ( + VOID +) +{ + UINT32 SioExit; + UINT32 DeviceID; + + SioExit = 0; + + IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK); + IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK); + + IoWrite8 (SIO_INDEX_PORT, REG_LOGICAL_DEVICE); + IoWrite8 (SIO_DATA_PORT, SIO_UART1); + + if(IoRead8(SIO_DATA_PORT) == SIO_UART1){ + DeviceID=0; + SioExit |= EXIST; + } + + IoWrite8 (SIO_INDEX_PORT, SIO_LOCK); + + return SioExit; +} + +/** + + GC_TODO: add routine description + + @param None + + @retval None + +**/ +VOID +InitializeSio ( + VOID + ) +{ + + UINT32 SioExist; + UINT32 SioEnable; + UINT32 Decode; + UINT32 Enable; + + // + // Enable LPC decode + // Set COMA/COMB base + // + + Decode = ((V_PCH_LPC_IOD_COMA_3F8 << N_PCH_LPC_IOD_COMA) | (V_PCH_LPC_IOD_COMB_2F8 << N_PCH_LPC_IOD_COMB)); + Enable = ( B_PCH_LPC_IOE_ME2 | B_PCH_LPC_IOE_SE | B_PCH_LPC_IOE_ME1 \ + | B_PCH_LPC_IOE_KE | B_PCH_LPC_IOE_CBE | B_PCH_LPC_IOE_CAE); + IoWrite32 (R_ICH_IOPORT_PCI_INDEX, (UINT32) (ICH_LPC_CF8_ADDR (R_ICH_LPC_IO_DEC))); + + IoWrite32 (R_ICH_IOPORT_PCI_DATA, Decode | (Enable << 16)); + + MmioWrite16 (PCH_PCR_ADDRESS(PID_DMI, R_PCH_PCR_DMI_LPCIOD), (UINT16)Decode); + MmioWrite16 (PCH_PCR_ADDRESS(PID_DMI, R_PCH_PCR_DMI_LPCIOE), (UINT16)Enable); + SioExist = IsSioExist (); + SioEnable = SioExist; + + if (SioEnable == EXIST) { + IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK); + IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK); + + // + //COM1 + // + IoWrite8 (SIO_INDEX_PORT, REG_LOGICAL_DEVICE); + IoWrite8 (SIO_DATA_PORT, SIO_UART1); + + // + //active COM1 + // + IoWrite8 (SIO_INDEX_PORT, ACTIVATE); + IoWrite8 (SIO_DATA_PORT, 1); + + IoWrite8 (SIO_INDEX_PORT, SIO_LOCK); + + } +} + +/** + Performs platform specific initialization required for the CPU to access + the hardware associated with a SerialPortLib instance. This function does + not initialize the serial port hardware itself. Instead, it initializes + hardware devices that are required for the CPU to access the serial port + hardware. This function may be called more than once. + + @retval RETURN_SUCCESS The platform specific initialization succeeded. + @retval RETURN_DEVICE_ERROR The platform specific initialization could not be completed. + +**/ +RETURN_STATUS +EFIAPI +PlatformHookSerialPortInitialize ( + VOID + ) +{ + UINTN Divisor; + UINT8 OutputData; + UINT8 Data; + + InitializeSio(); + // + // Some init is done by the platform status code initialization. + // + // + // Map 5..8 to 0..3 + // + Data = (UINT8) (gData - (UINT8) 5); + + // + // Calculate divisor for baud generator + // + Divisor = 115200 / gBps; + + // + // Set communications format + // + OutputData = (UINT8) ((DLAB << 7) | ((gBreakSet << 6) | ((gParity << 3) | ((gStop << 2) | Data)))); + IoWrite8 (gComBase + LCR_OFFSET, OutputData); + + // + // Configure baud rate + // + IoWrite8 (gComBase + BAUD_HIGH_OFFSET, (UINT8) (Divisor >> 8)); + IoWrite8 (gComBase + BAUD_LOW_OFFSET, (UINT8) (Divisor & 0xff)); + + // + // Switch back to bank 0 + // + OutputData = (UINT8) ((~DLAB << 7) | ((gBreakSet << 6) | ((gParity << 3) | ((gStop << 2) | Data)))); + IoWrite8 (gComBase + LCR_OFFSET, OutputData); + + return RETURN_SUCCESS; +} + diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BasePlatformHookLib/BasePlatformHookLib.inf new file mode 100644 index 0000000000..ebd4421ea4 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BasePlatformHookLib/BasePlatformHookLib.inf @@ -0,0 +1,44 @@ +### @file +# +# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +### + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = BasePlatformHookLib + FILE_GUID = E22ADCC6-ED90-4A90-9837-C8E7FF9E963D + VERSION_STRING = 1.0 + MODULE_TYPE = BASE + LIBRARY_CLASS = PlatformHookLib +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + PciLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + PurleyOpenBoardPkg/PlatPkg.dec + PurleySktPkg/SocketPkg.dec + LewisburgPkg/PchRcPkg.dec + PurleyRcPkg/RcPkg.dec + +[FixedPcd] + +[Sources] + BasePlatformHookLib.c diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c new file mode 100644 index 0000000000..c1926d4924 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c @@ -0,0 +1,41 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +MtOlympusBoardUpdateAcpiTable ( + IN OUT EFI_ACPI_COMMON_HEADER *Table, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ); + +EFI_STATUS +EFIAPI +BoardUpdateAcpiTable ( + IN OUT EFI_ACPI_COMMON_HEADER *Table, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ) +{ + MtOlympusBoardUpdateAcpiTable (Table, Version); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf new file mode 100644 index 0000000000..031e6576bf --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf @@ -0,0 +1,47 @@ +### @file +# +# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +### + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = DxeBoardAcpiTableLib + FILE_GUID = 6562E0AE-90D8-4D41-8C97-81286B4BE7D2 + VERSION_STRING = 1.0 + MODULE_TYPE = BASE + LIBRARY_CLASS = BoardAcpiTableLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + PciLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + PurleyOpenBoardPkg/PlatPkg.dec + LewisburgPkg/PchRcPkg.dec + +[Pcd] + gOemSkuTokenSpaceGuid.PcdAcpiGnvsAddress + +[Sources] + DxeMtOlympusAcpiTableLib.c + DxeBoardAcpiTableLib.c + diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/DxeMtOlympusAcpiTableLib.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/DxeMtOlympusAcpiTableLib.c new file mode 100644 index 0000000000..310740e6fb --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/DxeMtOlympusAcpiTableLib.c @@ -0,0 +1,58 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +GLOBAL_REMOVE_IF_UNREFERENCED BIOS_ACPI_PARAM *mGlobalNvsArea; + +VOID +MtOlympusUpdateGlobalNvs ( + VOID + ) +{ + + // + // Allocate and initialize the NVS area for SMM and ASL communication. + // + mGlobalNvsArea = (VOID *)(UINTN)PcdGet64 (PcdAcpiGnvsAddress); + + // + // Update global NVS area for ASL and SMM init code to use + // + + +} + +EFI_STATUS +EFIAPI +MtOlympusBoardUpdateAcpiTable ( + IN OUT EFI_ACPI_COMMON_HEADER *Table, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ) +{ + if (Table->Signature == EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) { + MtOlympusUpdateGlobalNvs (); + } + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c new file mode 100644 index 0000000000..f8b6aab8f9 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c @@ -0,0 +1,67 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +MtOlympusBoardEnableAcpi ( + IN BOOLEAN EnableSci + ); + +EFI_STATUS +EFIAPI +MtOlympusBoardDisableAcpi ( + IN BOOLEAN DisableSci + ); + +EFI_STATUS +EFIAPI +SiliconEnableAcpi ( + IN BOOLEAN EnableSci + ); + +EFI_STATUS +EFIAPI +SiliconDisableAcpi ( + IN BOOLEAN DisableSci + ); + +EFI_STATUS +EFIAPI +BoardEnableAcpi ( + IN BOOLEAN EnableSci + ) +{ + SiliconEnableAcpi (EnableSci); + return MtOlympusBoardEnableAcpi (EnableSci); +} + +EFI_STATUS +EFIAPI +BoardDisableAcpi ( + IN BOOLEAN DisableSci + ) +{ + SiliconDisableAcpi (DisableSci); + return MtOlympusBoardDisableAcpi (DisableSci); +} + + diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf new file mode 100644 index 0000000000..22c7fbe335 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf @@ -0,0 +1,47 @@ +### @file +# +# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +### + +[Defines] + INF_VERSION = 0x00010017 + BASE_NAME = SmmBoardAcpiEnableLib + FILE_GUID = 549E69AE-D3B3-485B-9C17-AF16E20A58AD + VERSION_STRING = 1.0 + MODULE_TYPE = BASE + LIBRARY_CLASS = BoardAcpiEnableLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + PciLib + MmPciLib + PchCycleDecodingLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + PurleyOpenBoardPkg/PlatPkg.dec + LewisburgPkg/PchRcPkg.dec + +[Sources] + SmmMtOlympusAcpiEnableLib.c + SmmSiliconAcpiEnableLib.c + SmmBoardAcpiEnableLib.c + diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmMtOlympusAcpiEnableLib.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmMtOlympusAcpiEnableLib.c new file mode 100644 index 0000000000..19b1fd7bb7 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmMtOlympusAcpiEnableLib.c @@ -0,0 +1,42 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +MtOlympusBoardEnableAcpi ( + IN BOOLEAN EnableSci + ) +{ + // enable additional board register + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +MtOlympusBoardDisableAcpi ( + IN BOOLEAN DisableSci + ) +{ + // enable additional board register + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c new file mode 100644 index 0000000000..65aa7b067a --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c @@ -0,0 +1,125 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Clear Port 80h + + SMI handler to enable ACPI mode + + Dispatched on reads from APM port with value EFI_ACPI_ENABLE_SW_SMI + + Disables the SW SMI Timer. + ACPI events are disabled and ACPI event status is cleared. + SCI mode is then enabled. + + Clear SLP SMI status + Enable SLP SMI + + Disable SW SMI Timer + + Clear all ACPI event status and disable all ACPI events + + Disable PM sources except power button + Clear status bits + + Disable GPE0 sources + Clear status bits + + Disable GPE1 sources + Clear status bits + + Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4) + + Enable SCI +**/ +EFI_STATUS +EFIAPI +SiliconEnableAcpi ( + IN BOOLEAN EnableSci + ) +{ + UINT32 SmiEn; + UINT16 Pm1En; + UINT16 Pm1Cnt; + UINT16 PchPmBase; + + // + // Init Power Management I/O Base aka ACPI Base + // + PchAcpiBaseGet (&PchPmBase); + + SmiEn = IoRead32 (PchPmBase + R_PCH_SMI_EN); + + // + // Disable SW SMI Timer and legacy USB + // + SmiEn &= ~(B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SMI_EN_LEGACY_USB | B_PCH_SMI_EN_LEGACY_USB2); + + // + // And enable SMI on write to B_PCH_ACPI_PM1_CNT_SLP_EN when SLP_TYP is written + // + SmiEn |= B_PCH_SMI_EN_ON_SLP_EN; + IoWrite32 (PchPmBase + R_PCH_SMI_EN, SmiEn); + + // + // Disable PM sources except power button + // + Pm1En = B_PCH_ACPI_PM1_EN_PWRBTN; + IoWrite16 (PchPmBase + R_PCH_ACPI_PM1_EN, Pm1En); + + // + // Enable SCI + // + Pm1Cnt = IoRead16 (PchPmBase + R_PCH_ACPI_PM1_CNT); + Pm1Cnt |= B_PCH_ACPI_PM1_CNT_SCI_EN; + IoWrite16 (PchPmBase + R_PCH_ACPI_PM1_CNT, Pm1Cnt); + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +SiliconDisableAcpi ( + IN BOOLEAN DisableSci + ) +{ + UINT16 Pm1Cnt; + UINT16 PchPmBase; + + // + // Init Power Management I/O Base aka ACPI Base + // + PchAcpiBaseGet (&PchPmBase); + + Pm1Cnt = IoRead16 (PchPmBase + R_PCH_ACPI_PM1_CNT); + + // + // Disable SCI + // + Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SCI_EN; + + IoWrite16 (PchPmBase + R_PCH_ACPI_PM1_CNT, Pm1Cnt); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/AllLanesEparam.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/AllLanesEparam.c new file mode 100644 index 0000000000..ef1675d7a9 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/AllLanesEparam.c @@ -0,0 +1,49 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef MINIBIOS_BUILD +#include +#include +#include +#include +#endif + +#include + +#define SPEED_REC_96GT 0 +#define SPEED_REC_104GT 1 +#define ADAPTIVE_CTLE 0x3f + +#pragma pack(1) + +ALL_LANES_EPARAM_LINK_INFO KtiMtOlympusAllLanesEparamTable[] = { + // + // SocketID, Freq, Link, TXEQL, CTLEPEAK + // + + // + // Socket 0 + // + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK0), 0x2E39343F, ADAPTIVE_CTLE}, + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK1), 0x2F39353F, ADAPTIVE_CTLE}, + + // + // Socket 1 + // + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK0), 0x2D37353F, ADAPTIVE_CTLE}, + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK1), 0x2F3A343F, ADAPTIVE_CTLE} +}; + +#pragma pack() + +UINT32 KtiMtOlympusAllLanesEparamTableSize = sizeof(KtiMtOlympusAllLanesEparamTable); diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/GpioTable.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/GpioTable.c new file mode 100644 index 0000000000..e278156afa --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/GpioTable.c @@ -0,0 +1,302 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include + +#include +#include +#include + +#include +#include +#include + +GPIO_INIT_CONFIG mGpioTableMicrosoftWcs[] = +{ +// Group A + {GPIO_SKL_H_GPP_A0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone }},//GPP_A_0_LPC_RCIN_N_ESPI_ALERT1_N + { GPIO_SKL_H_GPP_A1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_1_LAD_0_ESPI_IO_0 + { GPIO_SKL_H_GPP_A2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_2_LAD_1_ESPI_IO_1 + { GPIO_SKL_H_GPP_A3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_3_LAD_2_ESPI_IO_2 + { GPIO_SKL_H_GPP_A4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_4_LAD_3_ESPI_IO_3 + { GPIO_SKL_H_GPP_A5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_5_LPC_LFRAME_N_ESPI_CS0_N + { GPIO_SKL_H_GPP_A6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_6_IRQ_LPC_SERIRQ_ESPI_CS1_N + { GPIO_SKL_H_GPP_A7, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_7_IRQ_LPC_PIRQA_N_ESPI_ALERT0_N + { GPIO_SKL_H_GPP_A8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_8_FM_LPC_CLKRUN_N + { GPIO_SKL_H_GPP_A9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_9_CLK_24M_66M_LPC0_ESPI + { GPIO_SKL_H_GPP_A10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_10_TP_PCH_GPP_A_10 + { GPIO_SKL_H_GPP_A11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_11_FM_LPC_PME_N + { GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_A_12_IRQ_PCH_SCI_WHEA_N + { GPIO_SKL_H_GPP_A13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_A_13_FM_EUP_LOT6_N MSFT_WCS_override: Reset Type + { GPIO_SKL_H_GPP_A14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_14_ESPI_RESET_N + { GPIO_SKL_H_GPP_A15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_15_SUSACK_N + { GPIO_SKL_H_GPP_A16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_16_TP_PCH_GPP_A_16 + { GPIO_SKL_H_GPP_A17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_17_FM_KTI_SLOW_MODE_N + { GPIO_SKL_H_GPP_A18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_A_18_FM_BIOS_ADV_FUNCTIONS + //{GPIO_SKL_H_GPP_A19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetNormal,GpioTermNone}},//GPP_A_19_FM_ME_RCVR_N + { GPIO_SKL_H_GPP_A20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_A_20_TP_PCH_GPP_A_20 MSFT_WCS_override: Reset Type + { GPIO_SKL_H_GPP_A21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_21_TP_PCH_GPP_A_21 + { GPIO_SKL_H_GPP_A22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_22_TP_PCH_GPP_A_22 + { GPIO_SKL_H_GPP_A23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_A_23_TP_PCH_GPP_A_23 + // Group B + { GPIO_SKL_H_GPP_B0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_0_CORE_VID_0 + { GPIO_SKL_H_GPP_B1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_1_CORE_VID_1 + { GPIO_SKL_H_GPP_B2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_2_VRALERT_N + { GPIO_SKL_H_GPP_B3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_3_FM_QAT_ENABLE_N + { GPIO_SKL_H_GPP_B4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_4_TP_PCH_GPP_B_4 + { GPIO_SKL_H_GPP_B5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_5_PU_PCH_GPP_B_5 + { GPIO_SKL_H_GPP_B6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_B_6_PU_PCH_GPP_B_6 + { GPIO_SKL_H_GPP_B7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_B_7_PU_PCH_GPP_B_7 + { GPIO_SKL_H_GPP_B8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_8_PU_PCH_GPP_B_8 + { GPIO_SKL_H_GPP_B9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_9_PU_PCH_GPP_B_9 + { GPIO_SKL_H_GPP_B10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_10_PU_PCH_GPP_B_10 + { GPIO_SKL_H_GPP_B11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_11_FM_PMBUS_ALERT_B_EN + { GPIO_SKL_H_GPP_B12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_12_TP_SLP_S0_N + { GPIO_SKL_H_GPP_B13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_13_RST_PLTRST_N + { GPIO_SKL_H_GPP_B14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_B_14_FM_PCH_BIOS_RCVR_SPKR + { GPIO_SKL_H_GPP_B15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_15_FM_CPU_ERR0_LVT3_N + { GPIO_SKL_H_GPP_B16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_16_FM_CPU_ERR1_LVT3_N + { GPIO_SKL_H_GPP_B17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_17_TP_PCH_GPP_B_17 + { GPIO_SKL_H_GPP_B18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_B_18_PU_NO_REBOOT MSFT_WCS_override: Reset Type + { GPIO_SKL_H_GPP_B19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_19_TP_PCH_GPP_B_19 + { GPIO_SKL_H_GPP_B20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_B_20_FM_BIOS_POST_CMPLT_N + { GPIO_SKL_H_GPP_B21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_21_TP_LINK_WIDTH_ID5 + { GPIO_SKL_H_GPP_B22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_B_22_FM_PCH_BOOT_BIOS_DEVICE + { GPIO_SKL_H_GPP_B23, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_B_23_FM_PCH_BMC_THERMTRIP_EXI_STRAP_N + // Group C + { GPIO_SKL_H_GPP_C0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_C_0_SMB_HOST_STBY_LVC3_SCL + { GPIO_SKL_H_GPP_C1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_C_1_SMB_HOST_STBY_LVC3_SDA + { GPIO_SKL_H_GPP_C2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_C_2_PU_PCH_TLS_ENABLE_STRAP + { GPIO_SKL_H_GPP_C3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_C_3_SMB_SMLINK0_STBY_LVC3_SCL + { GPIO_SKL_H_GPP_C4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_C_4_SMB_SMLINK0_STBY_LVC3_SDA + { GPIO_SKL_H_GPP_C5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_C_5_IRQ_SML0_ALERT_N MSFT_WCS_override: Reset Type + { GPIO_SKL_H_GPP_C6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_C_6_SMB_PMBUS_SML1_STBY_LVC3_SCL + { GPIO_SKL_H_GPP_C7, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_C_7_SMB_PMBUS_SML1_STBY_LVC3_SDA + { GPIO_SKL_H_GPP_C8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_8_FM_PASSWORD_CLEAR_N + { GPIO_SKL_H_GPP_C9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_9_FM_MFG_MODE + { GPIO_SKL_H_GPP_C10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_10_FM_PCH_SATA_RAID_KEY + { GPIO_SKL_H_GPP_C11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_11_TP_FP_AUD_DETECT_N + { GPIO_SKL_H_GPP_C12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_C_12_FM_BOARD_REV_ID0 + { GPIO_SKL_H_GPP_C13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_C_13_FM_BOARD_REV_ID1 + { GPIO_SKL_H_GPP_C14, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioResetNormal, GpioTermNone } },//GPP_C_14_FM_BMC_PCH_SCI_LPC_N + { GPIO_SKL_H_GPP_C15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_15_TP_LINK_WIDTH_ID0 + { GPIO_SKL_H_GPP_C16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_16_TP_LINK_WIDTH_ID1 + { GPIO_SKL_H_GPP_C17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_17_TP_LINK_WIDTH_ID2 + { GPIO_SKL_H_GPP_C18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_18_TP_LINK_WIDTH_ID3 + { GPIO_SKL_H_GPP_C19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_19_TP_LINK_WIDTH_ID4 , MSFT_WCS_override for AVA Slot3_PRSNT_N_2_4 + { GPIO_SKL_H_GPP_C20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_20_FM_THROTTLE_N + { GPIO_SKL_H_GPP_C21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_C_21_RST_PCH_MIC_MUX_N + { GPIO_SKL_H_GPP_C22, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone } },//GPP_C_22_IRQ_BMC_PCH_SMI_LPC_N + { GPIO_SKL_H_GPP_C23, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone } },//GPP_C_23_FM_CPU_CATERR_DLY_LVT3_N + // Group D + { GPIO_SKL_H_GPP_D0, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntNmi, GpioResetNormal, GpioTermNone } },//GPP_D_0_IRQ_BMC_PCH_NMI + { GPIO_SKL_H_GPP_D1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_1_FP_PWR_LED_N + { GPIO_SKL_H_GPP_D2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_D_2_FM_TBT_FORCE_PWR + { GPIO_SKL_H_GPP_D3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_D_3 [PVDDQ_KLM_PINALERT_N] + { GPIO_SKL_H_GPP_D4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_D_4_FM_PLD_PCH_DATA + { GPIO_SKL_H_GPP_D5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_5_TP_PCH_GPP_D_5 + { GPIO_SKL_H_GPP_D6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_6_TP_PCH_GPP_D_6 + { GPIO_SKL_H_GPP_D7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_7_TP_PCH_GPP_D_7 + { GPIO_SKL_H_GPP_D8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_8_TP_PCH_GPP_D_8 + { GPIO_SKL_H_GPP_D9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_9_TP_PCH_GPP_D_9 + { GPIO_SKL_H_GPP_D10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_10_FM_M2_SSD_DEVSLP , MSFT_WCS_override for AVA Slot3_PRSNT_N_2_6 + { GPIO_SKL_H_GPP_D11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_11_FM_LA_TRIGGER_N + { GPIO_SKL_H_GPP_D12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_12_SGPIO_SSATA_DATA1 + { GPIO_SKL_H_GPP_D13, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_13_SMB_SMLINK5_STBY_LVC3_SCL + { GPIO_SKL_H_GPP_D14, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_14_SMB_SMLINK5_STBY_LVC3_SDA + { GPIO_SKL_H_GPP_D15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_15_SSATA_SDATAOUT0 + { GPIO_SKL_H_GPP_D16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_16_TP_PCH_GPP_D_16 + { GPIO_SKL_H_GPP_D17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_17_TP_PCH_GPP_D_17 + { GPIO_SKL_H_GPP_D18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_D_18_TP_PCH_GPP_D_18 + { GPIO_SKL_H_GPP_D19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_D_19_FM_PS_PWROK_DLY_SEL + { GPIO_SKL_H_GPP_D20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_20_TP_PCH_GPP_D_20 + { GPIO_SKL_H_GPP_D21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_21_SPC_IE_LVC3_RX + { GPIO_SKL_H_GPP_D22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_22_SPC_IE_LVC3_TX + { GPIO_SKL_H_GPP_D23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_D_23_TP_PCH_GPP_D_23 + // Group E + { GPIO_SKL_H_GPP_E0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_0_TP_PCH_GPP_E_0 + { GPIO_SKL_H_GPP_E1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_1_TP_PCH_GPP_E_1 + { GPIO_SKL_H_GPP_E2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_2_TP_PCH_GPP_E_2 + { GPIO_SKL_H_GPP_E3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_3_FM_ADR_TRIGGER_N + { GPIO_SKL_H_GPP_E4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_4_TP_PCH_GPP_E_4 + { GPIO_SKL_H_GPP_E5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_5_TP_PCH_GPP_E_5 + { GPIO_SKL_H_GPP_E6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_6_TP_PCH_GPP_E_6 + { GPIO_SKL_H_GPP_E7, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutLow, GpioIntLevel | GpioIntSmi, GpioResetNormal, GpioTermNone } },//GPP_E_7_FM_ADR_SMI_GPIO_N MSFT_WCS_override: INT config and reset type + { GPIO_SKL_H_GPP_E8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_8_LED_PCH_SATA_HDD_N + { GPIO_SKL_H_GPP_E9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_9_FM_OC0_USB_N + { GPIO_SKL_H_GPP_E10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_10_FM_OC1_USB_N + { GPIO_SKL_H_GPP_E11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_11_FM_OC2_USB_N + { GPIO_SKL_H_GPP_E12, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_E_12_FM_OC3_USB_N + // Group F + { GPIO_SKL_H_GPP_F0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_0_TP_PCH_GPP_F_0 + { GPIO_SKL_H_GPP_F1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_1_TP_PCH_GPP_F_1 + { GPIO_SKL_H_GPP_F2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_2_TP_PCH_GPP_F_2 + { GPIO_SKL_H_GPP_F3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_3_TP_PCH_GPP_F_3 + { GPIO_SKL_H_GPP_F4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_4_TP_PCH_GPP_F_4 + { GPIO_SKL_H_GPP_F5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_F_5_IRQ_TPM_SPI_N + { GPIO_SKL_H_GPP_F6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_F_6_JTAG_PCH_PLD_TCK + { GPIO_SKL_H_GPP_F7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_F_7_JTAG_PCH_PLD_TDI + { GPIO_SKL_H_GPP_F8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_F_8_JTAG_PCH_PLD_TMS + { GPIO_SKL_H_GPP_F9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_F_9_JTAG_PCH_PLD_TDO + { GPIO_SKL_H_GPP_F10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_10_SGPIO_SATA_CLOCK + { GPIO_SKL_H_GPP_F11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_11_SGPIO_SATA_LOAD, MSFT_WCS_override for AVA Slot5_PRSNT_N_2_1 + { GPIO_SKL_H_GPP_F12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_12_SGPIO_SATA_DATA1, MSFT_WCS_override for AVA Slot4_PRSNT_N_2_1 + { GPIO_SKL_H_GPP_F13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_13_SGPIO_SATA_DATA0, MSFT_WCS_override for AVA Slot3_PRSNT_N_2_1 + { GPIO_SKL_H_GPP_F14, { GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_14_LED_PCH_SSATA_HDD_N + { GPIO_SKL_H_GPP_F15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_15_FM_OC4_USB_N + { GPIO_SKL_H_GPP_F16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_16_FM_OC5_USB_N + { GPIO_SKL_H_GPP_F17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_17_FM_OC6_USB_N + { GPIO_SKL_H_GPP_F18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_18_FM_OC7_USB_N + { GPIO_SKL_H_GPP_F19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_19_SMB_GBE_STBY_LVC3_SCL + { GPIO_SKL_H_GPP_F20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_20_SMB_GBE_STBY_LVC3_SDA + { GPIO_SKL_H_GPP_F21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_21_TP_PCH_GPP_F_21 + { GPIO_SKL_H_GPP_F22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_22_SGPIO_SSATA_CLOCK + { GPIO_SKL_H_GPP_F23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_F_23_SGPIO_SSATA_LOAD + // Group G + { GPIO_SKL_H_GPP_G0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_0_FAN_TACH_0_FAN_TACH0IE, MSFT_WCS_override for AVA Slot5_PRSNT_N_2_3 + { GPIO_SKL_H_GPP_G1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_1_FAN_TACH_1_FAN_TACH1IE, MSFT_WCS_override for AVA Slot5_PRSNT_N_2_4 + { GPIO_SKL_H_GPP_G2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_2_FAN_TACH_2_FAN_TACH2IE, MSFT_WCS_override for AVA Slot5_PRSNT_N_2_6 + { GPIO_SKL_H_GPP_G3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_3_FAN_TACH_3_FAN_TACH3IE + { GPIO_SKL_H_GPP_G4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_4_FAN_TACH_4_FAN_TACH4IE + { GPIO_SKL_H_GPP_G5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_5_FAN_TACH_5_FAN_TACH5IE + { GPIO_SKL_H_GPP_G6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_6_FAN_TACH_6_FAN_TACH6IE + { GPIO_SKL_H_GPP_G7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_7_FAN_TACH_7_FAN_TACH7IE + { GPIO_SKL_H_GPP_G8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_G_8_FAN_PWM_0_FAN_PWM0IE MSFT_WCS_override: Reset Type + { GPIO_SKL_H_GPP_G9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_9_FAN_PWM_1_FAN_PWM1IE + { GPIO_SKL_H_GPP_G10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_G_10_FAN_PWM_2_FAN_PWM2IE MSFT_WCS_override: Reset Type + { GPIO_SKL_H_GPP_G11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_G_11_FAN_PWM_3_FAN_PWM3IE MSFT_WCS_override: Reset Type + { GPIO_SKL_H_GPP_G12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_G_12_FM_BOARD_SKU_ID0 + { GPIO_SKL_H_GPP_G13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_G_13_FM_BOARD_SKU_ID1 + { GPIO_SKL_H_GPP_G14, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_G_14_FM_BOARD_SKU_ID2 + { GPIO_SKL_H_GPP_G15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_G_15_FM_BOARD_SKU_ID3 + { GPIO_SKL_H_GPP_G16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_G_16_FM_BOARD_SKU_ID4 + { GPIO_SKL_H_GPP_G17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_17_ADR_COMPLETE + { GPIO_SKL_H_GPP_G18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_18_FM_NMI_EVENT_N + { GPIO_SKL_H_GPP_G19, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_19_FM_SMI_ACTIVE_N + { GPIO_SKL_H_GPP_G20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_20_IRQ_SML1_PMBUS_ALERT_N + { GPIO_SKL_H_GPP_G21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_21_FM_SATAEXPRESS_DEVSLP + { GPIO_SKL_H_GPP_G22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_22_FM_BIOS_IMAGE_SWAP_N + { GPIO_SKL_H_GPP_G23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_G_23_FM_SSATA_PCIE_SEL + // Group H + { GPIO_SKL_H_GPP_H0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_0_PU_PCH_GPP_H_0 + { GPIO_SKL_H_GPP_H1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_1_FM_SWAP_OVERRIDE_N + { GPIO_SKL_H_GPP_H2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_2_FM_PCH_MGPIO_TEST0 + { GPIO_SKL_H_GPP_H3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_3_FM_PCH_MGPIO_TEST1 + { GPIO_SKL_H_GPP_H4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_4_FM_PCH_MGPIO_TEST4 + { GPIO_SKL_H_GPP_H5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_5_FM_CLKREQ_M2_SSD_N + { GPIO_SKL_H_GPP_H6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_6_FM_OCULINK1_PCIE_SSD0_PRSNT_N + { GPIO_SKL_H_GPP_H7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_7_FM_OCULINK1_PCIE_SSD1_PRSNT_N + { GPIO_SKL_H_GPP_H8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_8_FM_CLKREQ_NIC1_N + { GPIO_SKL_H_GPP_H9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_9_FM_PCH_MGPIO_TEST5 + { GPIO_SKL_H_GPP_H10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_10_SMB_SMLINK2_STBY_LVC3_SCL + { GPIO_SKL_H_GPP_H11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_11_SMB_SMLINK2_STBY_LVC3_SDA + { GPIO_SKL_H_GPP_H12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_12_FM_ESPI_FLASH_MODE + { GPIO_SKL_H_GPP_H13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_13_SMB_SMLINK3_STBY_LVC3_SCL + { GPIO_SKL_H_GPP_H14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_14_SMB_SMLINK3_STBY_LVC3_SDA + { GPIO_SKL_H_GPP_H15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_H_15_PU_ADR_TIMER_HOLD_OFF_N + { GPIO_SKL_H_GPP_H16, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_16_SMB_SMLINK4_STBY_LVC3_SCL + { GPIO_SKL_H_GPP_H17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_H_17_SMB_SMLINK4_STBY_LVC3_SDA + { GPIO_SKL_H_GPP_H18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_H_18_FM_LT_KEY_DOWNGRADE_N + { GPIO_SKL_H_GPP_H19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_H_19_TP_PCH_GPP_H_19 + { GPIO_SKL_H_GPP_H20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_H_20_FM_PCH_MGPIO_TEST2 + { GPIO_SKL_H_GPP_H21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_H_21_FM_PCH_MGPIO_TEST3 MSFT_WCS_override: Reset Type + { GPIO_SKL_H_GPP_H22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_H_22_TP_PCH_GPP_H_22 + { GPIO_SKL_H_GPP_H23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetNormal, GpioTermNone } },//GPP_H_23_FM_SSATA_PCIE_M2_SEL , MSFT_WCS_override for AVA Slot4_PRSNT_N_2_3 + // Group I + { GPIO_SKL_H_GPP_I0, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_0_GBE_TDO + { GPIO_SKL_H_GPP_I1, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_1_GBE_TCK + { GPIO_SKL_H_GPP_I2, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_2_GBE_TMS + { GPIO_SKL_H_GPP_I3, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_3_GBE_TDI + { GPIO_SKL_H_GPP_I4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_4_FP_LED_STATUS_GREEN_PCH_N + { GPIO_SKL_H_GPP_I5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_5_FP_LED_STATUS_AMBER_PCH_N + { GPIO_SKL_H_GPP_I6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_6_FP_ID_LED_PCH_N + { GPIO_SKL_H_GPP_I7, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_7_JTAG_GBE_TRST_N + { GPIO_SKL_H_GPP_I8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_8_FP_ID_BTN_PCH_N + { GPIO_SKL_H_GPP_I9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_9_FM_MEM_THERM_EVENT_PCH_N + { GPIO_SKL_H_GPP_I10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_I_10_TP_PCH_GPP_I_10 + // Group GPD + { GPIO_SKL_H_GPD0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_0_FM_FIVRBREAK_N + { GPIO_SKL_H_GPD1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_1_ACPRESENT + { GPIO_SKL_H_GPD2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_2_LAN_WAKEB + { GPIO_SKL_H_GPD3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_3_PWRBTNB + { GPIO_SKL_H_GPD4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_4_SLP_S3B + { GPIO_SKL_H_GPD5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_5_SLP_S4B + { GPIO_SKL_H_GPD6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_6_SLP_AB + { GPIO_SKL_H_GPD7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_7_TP_GPD_7 + { GPIO_SKL_H_GPD8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_8_CLK_33K_PCH_SUSCLK_PLD + { GPIO_SKL_H_GPD9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_9_TP_SLP_WLAN + { GPIO_SKL_H_GPD10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_10_SLP_S5B_N + { GPIO_SKL_H_GPD11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPD_11_FM_PHY_DISABLE_N + // Group J + { GPIO_SKL_H_GPP_J0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_0_LED_GBE_0_ACTIVITY + { GPIO_SKL_H_GPP_J1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_1_LED_GBE_0_SPEED + { GPIO_SKL_H_GPP_J2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_2_LED_GBE_1_ACTIVITY + { GPIO_SKL_H_GPP_J3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_3_LED_GBE_1_SPEED + { GPIO_SKL_H_GPP_J4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_4_LED_GBE_2_ACTIVITY, MSFT_WCS_override for AVA Slot3_PRSNT_N_2_3 + { GPIO_SKL_H_GPP_J5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_5_LED_GBE_2_SPEED, MSFT_WCS_override for AVA Slot4_PRSNT_N_2_6 + { GPIO_SKL_H_GPP_J6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_J_6_LED_GBE_3_ACTIVITY MSFT_WCS_override: Reset Type + { GPIO_SKL_H_GPP_J7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_J_7_LED_GBE_3_SPEED MSFT_WCS_override: Reset Type + { GPIO_SKL_H_GPP_J8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_8_SMB_GBE0_LVC3_R_SCL + { GPIO_SKL_H_GPP_J9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_9_SMB_GBE0_LVC3_R_SDA + { GPIO_SKL_H_GPP_J10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_10_SMB_GBE1_LVC3_R_SCL + { GPIO_SKL_H_GPP_J11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_11_SMB_GBE1_LVC3_R_SDA + { GPIO_SKL_H_GPP_J12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_12_SMB_GBE2_LVC3_R_SCL + { GPIO_SKL_H_GPP_J13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_13_SMB_GBE2_LVC3_R_SDA + { GPIO_SKL_H_GPP_J14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_14_SMB_GBE3_LVC3_R_SCL + { GPIO_SKL_H_GPP_J15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_15_SMB_GBE3_LVC3_R_SDA, MSFT_WCS_override for AVA Slot4_PRSNT_N_2_4 + { GPIO_SKL_H_GPP_J16, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_16_FM_T1_LVC3_MOD_ABS0 + { GPIO_SKL_H_GPP_J17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_17_LED_GBE_0_LOW_SPEED + { GPIO_SKL_H_GPP_J18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_J_18_FM_L1_LVC3_MOD_ABS0 MSFT_WCS_override: Reset Type + { GPIO_SKL_H_GPP_J19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_19_LED_GBE_1_LOW_SPEED + { GPIO_SKL_H_GPP_J20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_20_FM_T2_LVC3_MOD_ABS0 + { GPIO_SKL_H_GPP_J21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_21_LED_GBE_2_LOW_SPEED + { GPIO_SKL_H_GPP_J22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_22_FM_L2_LVC3_MOD_ABS0 + { GPIO_SKL_H_GPP_J23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_J_23_LED_GBE_3_LOW_SPEED + // Group K + { GPIO_SKL_H_GPP_K0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_0_CLK_50M_CKMNG_PCH + { GPIO_SKL_H_GPP_K1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_1_RMII_PCH_BMC_RXD<0> + { GPIO_SKL_H_GPP_K2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_2_RMII_PCH_BMC_RXD<1> + { GPIO_SKL_H_GPP_K3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_3_GBE_NCSI_CRS_DV_R + { GPIO_SKL_H_GPP_K4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_4_RMII_BMC_PCH_TX_EN + { GPIO_SKL_H_GPP_K5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_5_RMII_BMC_PCH_TXD<0> + { GPIO_SKL_H_GPP_K6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_6_RMII_BMC_PCH_TXD<1> + { GPIO_SKL_H_GPP_K7, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_7_RMII_PCH_BMC_RX_ER + { GPIO_SKL_H_GPP_K8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_8_PD_RMII_PCH_ARB_IN + { GPIO_SKL_H_GPP_K9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_9_PU_RMII_PCH_ARB_OUT + { GPIO_SKL_H_GPP_K10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone } },//GPP_K_10_RST_PCIE_PCH_PERST_N + //{GPIO_SKL_H_GPP_K11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, GpioTermNone}},//GPP_K_11_PD_1P8_3P3_RCOMP + // Group L + //{GPIO_SKL_H_GPP_L0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis,GpioResetDeep, GpioTermNone}},//GPP_L_0 + //{GPIO_SKL_H_GPP_L1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis,GpioResetDeep, GpioTermNone}},//GPP_L_1 + { GPIO_SKL_H_GPP_L2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_2_VISA2CH0_D0 + { GPIO_SKL_H_GPP_L3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_3_VISA2CH0_D1 + { GPIO_SKL_H_GPP_L4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_4_VISA2CH0_D2 + { GPIO_SKL_H_GPP_L5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_5_VISA2CH0_D3 + { GPIO_SKL_H_GPP_L6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_6_VISA2CH0_D4 + { GPIO_SKL_H_GPP_L7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_7_VISA2CH0_D5 + { GPIO_SKL_H_GPP_L8, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_8_VISA2CH0_D6 + { GPIO_SKL_H_GPP_L9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_9_VISA2CH0_D7 + { GPIO_SKL_H_GPP_L10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_10_VISA2CH0_CLK + { GPIO_SKL_H_GPP_L11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_11_VISA2CH1_D0 + { GPIO_SKL_H_GPP_L12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_12_VISA2CH1_D1 + { GPIO_SKL_H_GPP_L13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_13_VISA2CH1_D2 + { GPIO_SKL_H_GPP_L14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_14_VISA2CH1_D3 + { GPIO_SKL_H_GPP_L15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_15_VISA2CH1_D4 + { GPIO_SKL_H_GPP_L16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_16_VISA2CH1_D5 + { GPIO_SKL_H_GPP_L17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_17_VISA2CH1_D6 + { GPIO_SKL_H_GPP_L18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_18_VISA2CH1_D7 + { GPIO_SKL_H_GPP_L19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone } },//GPP_L_19_VISA2CH1_CLK +}; + +UINTN mGpioTableSizeMicrosoftWcs = sizeof(mGpioTableMicrosoftWcs); diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/IioBifur.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/IioBifur.c new file mode 100644 index 0000000000..f64e016dda --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/IioBifur.c @@ -0,0 +1,94 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + + +#define ENABLE 1 +#define DISABLE 0 +#define NO_SLT_IMP 0xFF +#define SLT_IMP 1 +#define HIDE 1 +#define NOT_HIDE 0 +#define VPP_PORT_0 0 +#define VPP_PORT_1 1 +#define VPP_PORT_MAX 0xFF +#define VPP_ADDR_MAX 0xFF +#define PWR_VAL_MAX 0xFF +#define PWR_SCL_MAX 0xFF + + +IIO_BIFURCATION_ENTRY mIioBifurcationTable[] = +{ + { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 }, //Slot3: skt0/Iou0 Port1A x16 + { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, //PCH uplink x16 + { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_x4x4x4x4 }, //Slot1: skt0/Iou2 Port3A/3B, Slot2: skt0/Iou Port3C/3D (x8 slots) + { Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 }, //MCP x16 + { Iio_Socket0, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 }, //MCP x16 + { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxx8xxx8 }, //Slot4: skt1/IOU0 x16 Port1A/1B, 1C/1D for 2 x8 FPGAs + { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxx8x4x4 }, //OCulink x8: skt1/Iou1 Port2C/2D, M.2 slots skt1/Iou1 Port1A, 2B (x4x4) + { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 }, //Slot5: skt1/IOU2 x16 + { Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 }, //MCP + { Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 }, //MCP +}; + +UINT8 mIioBifurcationTableEntries = sizeof(mIioBifurcationTable)/sizeof(IIO_BIFURCATION_ENTRY); + +IIO_SLOT_CONFIG_ENTRY mIioSlotTable[] = { + // Port | Slot | Inter | Power Limit | Power Limit | Hot | Vpp | Vpp | PcieSSD | PcieSSD | PcieSSD | Hidden + // Index | | lock | Scale | Value | Plug | Port | Addr | Cap | VppPort | VppAddr | + { PORT_1A_INDEX, 3, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_0, VPP_ADDR_MAX, HIDE }, //S0Slt3 +// { PORT_1B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, ENABLE, VPP_PORT_1, 0x4C, HIDE }, +// { PORT_1C_INDEX, 1, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, ENABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE }, + { PORT_2A_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE }, + // Slot 2 supports HP: PCA9555 (CPU0) Addres 0x40, SCH (Rev 0.604) P 118 (MRL in J65) + { PORT_3A_INDEX, 1, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, ENABLE, VPP_PORT_0, 0x40, ENABLE, VPP_PORT_0, 0x40, NOT_HIDE }, + { PORT_3B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_1, 0x40, HIDE }, + { PORT_3C_INDEX, 2, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_0, 0x42, HIDE }, + { PORT_3D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_1, 0x42, HIDE }, + { SOCKET_1_INDEX + + PORT_0_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE }, + // Slot 4 supports HP: PCA9554 (CPU1) Address 0x40, SCH (Rev 0.604) P 121 (MRL in J287) + { SOCKET_1_INDEX + + PORT_1A_INDEX, 4, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE }, //x16 +// { SOCKET_1_INDEX + +// PORT_1B_INDEX, NO_SLT_IMP, ENABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, ENABLE, VPP_PORT_1, 0x40, HIDE }, +// { SOCKET_1_INDEX + +// PORT_1C_INDEX, NO_SLT_IMP, ENABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, ENABLE, VPP_PORT_0, 0x42, HIDE }, +// { SOCKET_1_INDEX + +// PORT_1D_INDEX, NO_SLT_IMP, ENABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, ENABLE, VPP_PORT_1, 0x42, HIDE }, + { SOCKET_1_INDEX + + PORT_2A_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_1, VPP_ADDR_MAX, ENABLE, VPP_PORT_0, 0x44, NOT_HIDE }, //x4 + { SOCKET_1_INDEX + + PORT_2B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, ENABLE, VPP_PORT_1, 0x44, HIDE }, //x4 + { SOCKET_1_INDEX + + PORT_2C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, ENABLE, VPP_PORT_0, 0x46, HIDE }, //x8 + { SOCKET_1_INDEX + +// PORT_2D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, ENABLE, VPP_PORT_1, 0x46, HIDE }, +// { SOCKET_1_INDEX + + PORT_3A_INDEX, 5, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, ENABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE }, //x16 +// { SOCKET_1_INDEX + +// PORT_3C_INDEX, 7, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, ENABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE }, + // Note: On Neon City, Slot 3 is assigned to PCH's PCIE port +}; + +UINT8 mIioSlotTableEntries = sizeof(mIioSlotTable)/sizeof(IIO_SLOT_CONFIG_ENTRY); \ No newline at end of file diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPostMemLib.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPostMemLib.c new file mode 100644 index 0000000000..54a1ad6edf --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPostMemLib.c @@ -0,0 +1,51 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +MtOlympusBoardInitBeforeSiliconInit ( + VOID + ); + +EFI_STATUS +EFIAPI +MtOlympusBoardInitAfterSiliconInit ( + VOID + ); + +EFI_STATUS +EFIAPI +BoardInitBeforeSiliconInit ( + VOID + ) +{ + MtOlympusBoardInitBeforeSiliconInit (); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitAfterSiliconInit ( + VOID + ) +{ + MtOlympusBoardInitAfterSiliconInit (); + return EFI_SUCCESS; +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPostMemLib.inf b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPostMemLib.inf new file mode 100644 index 0000000000..50d52af4d6 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPostMemLib.inf @@ -0,0 +1,44 @@ +### @file +# +# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +### + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiBoardPostMemInitLib + FILE_GUID = 30F407D6-6B92-412A-B2DA-8E73E2B386E6 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = BoardInitLib + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + PcdLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + PurleyRcPkg/RcPkg.dec + PurleySktPkg/SocketPkg.dec + +[Sources] + PeiMtOlympusInitPostMemLib.c + PeiBoardInitPostMemLib.c + +[FixedPcd] + +[Pcd] + diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPreMemLib.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPreMemLib.c new file mode 100644 index 0000000000..306465c8af --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPreMemLib.c @@ -0,0 +1,117 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +MtOlympusBoardDetect ( + VOID + ); + +EFI_BOOT_MODE +EFIAPI +MtOlympusBoardBootModeDetect ( + VOID + ); + +EFI_STATUS +EFIAPI +MtOlympusBoardDebugInit ( + VOID + ); + +EFI_STATUS +EFIAPI +MtOlympusBoardInitBeforeMemoryInit ( + VOID + ); + +EFI_STATUS +EFIAPI +MtOlympusBoardInitAfterMemoryInit ( + VOID + ); + +EFI_STATUS +EFIAPI +BoardDetect ( + VOID + ) +{ + MtOlympusBoardDetect (); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardDebugInit ( + VOID + ) +{ + MtOlympusBoardDebugInit (); + return EFI_SUCCESS; +} + +EFI_BOOT_MODE +EFIAPI +BoardBootModeDetect ( + VOID + ) +{ + return MtOlympusBoardBootModeDetect (); +} + +EFI_STATUS +EFIAPI +BoardInitBeforeMemoryInit ( + VOID + ) +{ + MtOlympusBoardInitBeforeMemoryInit (); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitAfterMemoryInit ( + VOID + ) +{ + MtOlympusBoardInitAfterMemoryInit (); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitBeforeTempRamExit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitAfterTempRamExit ( + VOID + ) +{ + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPreMemLib.inf new file mode 100644 index 0000000000..2451e6aa79 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiBoardInitPreMemLib.inf @@ -0,0 +1,77 @@ +### @file +# +# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +### + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiBoardInitPreMemLib + FILE_GUID = 73AA24AE-FB20-43F9-A3BA-448953A03A78 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = BoardInitLib + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + PcdLib + GpioLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + PurleyRcPkg/RcPkg.dec + PurleySktPkg/SocketPkg.dec + LewisburgPkg/PchRcPkg.dec + PurleyOpenBoardPkg/PlatPkg.dec + +[Sources] + PeiMtOlympusDetect.c + PeiMtOlympusInitPreMemLib.c + PeiBoardInitPreMemLib.c + GpioTable.c + UsbOC.c + IioBifur.c + AllLanesEparam.c + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable + gOemSkuTokenSpaceGuid.PcdMemTsegSize + gOemSkuTokenSpaceGuid.PcdMemIedSize + + gOemSkuTokenSpaceGuid.PcdSetupData + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData + + gOemSkuTokenSpaceGuid.PcdUsb20OverCurrentMappings + gOemSkuTokenSpaceGuid.PcdUsb30OverCurrentMappings + gOemSkuTokenSpaceGuid.PcdIioBifurcationTable + gOemSkuTokenSpaceGuid.PcdIioBifurcationTableEntries + gOemSkuTokenSpaceGuid.PcdIioSlotTable + gOemSkuTokenSpaceGuid.PcdIioSlotTableEntries + gOemSkuTokenSpaceGuid.PcdAllLanesEparamTable + gOemSkuTokenSpaceGuid.PcdAllLanesEparamTableSize + +[FixedPcd] + gEfiPchTokenSpaceGuid.PcdPchAcpiIoPortBaseAddress + gEfiPchTokenSpaceGuid.PcdTcoBaseAddress + diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusDetect.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusDetect.c new file mode 100644 index 0000000000..6968969f54 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusDetect.c @@ -0,0 +1,33 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +MtOlympusBoardDetect ( + VOID + ) +{ + DEBUG ((EFI_D_INFO, "MtOlympusBoardDetect\n")); + return EFI_SUCCESS; +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitLib.h b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitLib.h new file mode 100644 index 0000000000..6996cbfc50 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitLib.h @@ -0,0 +1,23 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PEI_MT_OLYMPUS_BOARD_INIT_LIB_H_ +#define _PEI_MT_OLYMPUS_BOARD_INIT_LIB_H_ + +#include +#include +#include +#include +#include + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitPostMemLib.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitPostMemLib.c new file mode 100644 index 0000000000..95101fe473 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitPostMemLib.c @@ -0,0 +1,91 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "PeiMtOlympusInitLib.h" + +VOID +GetIioUdsHob ( + IN IIO_UDS **UdsHobPtr + ) +{ + EFI_GUID UniversalDataGuid = IIO_UNIVERSAL_DATA_GUID; + EFI_HOB_GUID_TYPE *GuidHob; + + ASSERT(UdsHobPtr); + + *UdsHobPtr = NULL; + + GuidHob = GetFirstGuidHob (&UniversalDataGuid); + if (GuidHob){ + *UdsHobPtr = GET_GUID_HOB_DATA (GuidHob); + return; + } + + ASSERT(FALSE); +} + +EFI_STATUS +EFIAPI +MtOlympusBoardInitBeforeSiliconInit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +MtOlympusBoardInitAfterSiliconInit ( + VOID + ) +{ + IIO_UDS *IioUds; + + DEBUG((EFI_D_ERROR, "MtOlympusBoardInitAfterSiliconInit\n")); + + GetIioUdsHob(&IioUds); + + DEBUG ((EFI_D_ERROR, "Memory TOLM: %X\n", IioUds->PlatformData.MemTolm)); + DEBUG ( + (EFI_D_ERROR, + "PCIE BASE: %lX Size : %X\n", + IioUds->PlatformData.PciExpressBase, + IioUds->PlatformData.PciExpressSize) + ); + DEBUG ( + (EFI_D_ERROR, + "PCI32 BASE: %X Limit: %X\n", + IioUds->PlatformData.PlatGlobalMmiolBase, + IioUds->PlatformData.PlatGlobalMmiolLimit) + ); + DEBUG ( + (EFI_D_ERROR, + "PCI64 BASE: %lX Limit: %lX\n", + IioUds->PlatformData.PlatGlobalMmiohBase, + IioUds->PlatformData.PlatGlobalMmiohLimit) + ); + DEBUG ((EFI_D_ERROR, "UC START: %lX End : %lX\n", IioUds->PlatformData.PlatGlobalMmiohBase, (IioUds->PlatformData.PlatGlobalMmiohLimit + 1))); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitPreMemLib.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitPreMemLib.c new file mode 100644 index 0000000000..879227def8 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/PeiMtOlympusInitPreMemLib.c @@ -0,0 +1,576 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "PeiMtOlympusInitLib.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "SioRegs.h" + +extern GPIO_INIT_CONFIG mGpioTableMicrosoftWcs; +extern UINTN mGpioTableSizeMicrosoftWcs; + +extern PCH_USB_OVERCURRENT_PIN Usb20OverCurrentMappings[PCH_MAX_USB2_PORTS]; +extern PCH_USB_OVERCURRENT_PIN Usb30OverCurrentMappings[PCH_MAX_USB3_PORTS]; + +extern IIO_BIFURCATION_ENTRY mIioBifurcationTable[]; +extern UINT8 mIioBifurcationTableEntries; +extern IIO_SLOT_CONFIG_ENTRY mIioSlotTable[]; +extern UINT8 mIioSlotTableEntries; +extern ALL_LANES_EPARAM_LINK_INFO KtiMtOlympusAllLanesEparamTable[]; +extern UINT32 KtiMtOlympusAllLanesEparamTableSize; + +/** + + Initialize the GPIO IO selection, GPIO USE selection, and GPIO signal inversion registers. + + @param PeiServices - PeiService point. + @param CpuIo - CpuIo PPI to read/write IO ports. + + @retval EFI_SUCCESS - Init succeed. + +**/ +VOID +LpcSioEarlyInit ( + VOID + ) +{ + PchLpcGenIoRangeSet ((0x600 & 0xFF0), 0x10, LPC_ESPI_FIRST_SLAVE); + + IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK); + IoWrite8 (SIO_INDEX_PORT, SIO_UNLOCK); + + // + //mailbox + // + IoWrite8 (SIO_INDEX_PORT, REG_LOGICAL_DEVICE); + IoWrite8 (SIO_DATA_PORT, SIO_MAILBOX); + + IoWrite8 (SIO_INDEX_PORT, BASE_ADDRESS_HIGH0); + IoWrite8 (SIO_DATA_PORT, (UINT8)(0x600 >> 8)); + + IoWrite8 (SIO_INDEX_PORT, BASE_ADDRESS_LOW0); + IoWrite8 (SIO_DATA_PORT, (UINT8)(0x600 & 0xFF)); + // + //active mailbox + // + IoWrite8 (SIO_INDEX_PORT, ACTIVATE); + IoWrite8 (SIO_DATA_PORT, 1); + + IoWrite8 (SIO_INDEX_PORT, SIO_LOCK); +} + + +VOID +EarlyPlatformPchInit ( + IN EFI_PEI_SERVICES **PeiServices, + IN SYSTEM_CONFIGURATION *SystemConfiguration, + IN PCH_RC_CONFIGURATION *PchRcConfiguration + ) +{ + UINT16 Data16; + UINT8 Data8; + UINTN LpcBaseAddress; + UINT8 TcoRebootHappened; + UINTN PmcBaseAddress; + UINTN SpiBaseAddress; + UINTN P2sbBase; + + DEBUG((DEBUG_ERROR, "EarlyPlatformPchInit - Start\n")); + + LpcBaseAddress = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + PmcBaseAddress = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_PMC, + PCI_FUNCTION_NUMBER_PCH_PMC + ); + SpiBaseAddress = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI + ); + + // + // Program bar + // + P2sbBase = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_P2SB, + PCI_FUNCTION_NUMBER_PCH_P2SB + ); + + MmioWrite32 (P2sbBase + R_PCH_P2SB_SBREG_BAR, PCH_PCR_BASE_ADDRESS); + MmioOr8 (P2sbBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE); + + // + // LPC I/O Configuration + // + PchLpcIoDecodeRangesSet ( + (V_PCH_LPC_IOD_LPT_378 << N_PCH_LPC_IOD_LPT) | + (V_PCH_LPC_IOD_COMB_3E8 << N_PCH_LPC_IOD_COMB) | + (V_PCH_LPC_IOD_COMA_3F8 << N_PCH_LPC_IOD_COMA) + ); + + PchLpcIoEnableDecodingSet ( + B_PCH_LPC_IOE_ME2 | + B_PCH_LPC_IOE_SE | + B_PCH_LPC_IOE_ME1 | + B_PCH_LPC_IOE_KE | + B_PCH_LPC_IOE_HGE | + B_PCH_LPC_IOE_LGE | + B_PCH_LPC_IOE_FDE | + B_PCH_LPC_IOE_PPE | + B_PCH_LPC_IOE_CBE | + B_PCH_LPC_IOE_CAE, + LPC_ESPI_FIRST_SLAVE + ); + + // + // Enable the upper 128-byte bank of RTC RAM + // + PchPcrAndThenOr32 (PID_RTC, R_PCH_PCR_RTC_CONF, (UINT32)~0, B_PCH_PCR_RTC_CONF_UCMOS_EN); + + // + // Disable the Watchdog timer expiration from causing a system reset + // + PchPcrAndThenOr32 (PID_ITSS, R_PCH_PCR_ITSS_GIC, (UINT32)~0, B_PCH_PCR_ITSS_GIC_AME); + + // + // Halt the TCO timer + // + Data16 = IoRead16 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO1_CNT); + Data16 |= B_PCH_TCO_CNT_TMR_HLT; + IoWrite16 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO1_CNT, Data16); + + // + // Read the Second TO status bit + // + Data8 = IoRead8 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO2_STS); + DEBUG((EFI_D_ERROR, "pre read:%x\n", Data8)); + + Data8 = IoRead8 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO2_STS); + DEBUG((EFI_D_ERROR, "read:%x\n", Data8)); + if ((Data8 & B_PCH_TCO2_STS_SECOND_TO) == B_PCH_TCO2_STS_SECOND_TO) { + TcoRebootHappened = 1; + DEBUG ((EFI_D_ERROR, "EarlyPlatformPchInit - TCO Second TO status bit is set. This might be a TCO reboot\n")); + } else { + TcoRebootHappened = 0; + } + + // + // Clear the Second TO status bit + // + Data8 |= B_PCH_TCO2_STS_SECOND_TO; + IoWrite8 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO2_STS, Data8); + + // + // Disable SERR NMI and IOCHK# NMI in port 61 + // + Data8 = IoRead8 (R_PCH_NMI_SC); + Data8 |= (B_PCH_NMI_SC_PCI_SERR_EN | B_PCH_NMI_SC_IOCHK_NMI_EN); + IoWrite8 (R_PCH_NMI_SC, Data8); + + PchPcrAndThenOr32 (PID_ITSS, R_PCH_PCR_ITSS_GIC, (UINT32)~B_PCH_PCR_ITSS_GIC_AME, 0); + + // + // Clear EISS bit to allow for SPI use + // + MmioAnd8 (SpiBaseAddress + R_PCH_SPI_BC, (UINT8)~B_PCH_SPI_BC_EISS); + + DEBUG((DEBUG_ERROR, "EarlyPlatformPchInit - End\n")); +} + + +/** + + Initialize POC register by Variable. + + @param *SystemConfiguration - Pointer to SystemConfiguration variables. + + @retval EFI_SUCCESS - Success. + +**/ +EFI_STATUS +UpdatePlatformInfo ( + IN SYSTEM_CONFIGURATION *SystemConfiguration, + IN SOCKET_CONFIGURATION *SocketConfiguration + ) +{ + SOCKET_PROCESSORCORE_CONFIGURATION *SocketProcessorCoreConfig; + SOCKET_IIO_CONFIGURATION *SocketIioConfig; + UINT32 PcIoApicEnable; +#if MAX_SOCKET <= 4 + UINTN Index; +#endif + + DEBUG((EFI_D_ERROR, "platform update platform info entry\n")); + + SocketProcessorCoreConfig = &SocketConfiguration->SocketProcessorCoreConfiguration; + SocketIioConfig = &SocketConfiguration->IioConfig; + +#if MAX_SOCKET <= 4 + for (Index = 0; Index < 24; Index++) { + if (SocketIioConfig->DevPresIoApicIio[Index]) { + PcIoApicEnable |= (1 << Index); + } + } + +#else + // Enable all 32 IOxAPIC + PcIoApicEnable = 0xFFFFFFFF; +#endif + PcdSet32 (PcdPcIoApicEnable, PcIoApicEnable); + // + // Check to make sure TsegSize is in range, if not use default. + // + if (SocketProcessorCoreConfig->TsegSize > MAX_PROCESSOR_TSEG) { + SocketProcessorCoreConfig->TsegSize = MAX_PROCESSOR_TSEG; // if out of range make default 64M + } + PcdSet32 (PcdMemTsegSize, (0x400000 << SocketProcessorCoreConfig->TsegSize)); + if (SocketProcessorCoreConfig->IedSize > 0) { + PcdSet32 (PcdMemIedSize, (0x400000 << (SocketProcessorCoreConfig->IedSize - 1))); + } else { + PcdSet32 (PcdMemIedSize, 0); + } + + // + // Minimum SMM range in TSEG should be larger than 3M + // + ASSERT (PcdGet32 (PcdMemTsegSize) - PcdGet32 (PcdMemIedSize) >= 0x300000); + + return EFI_SUCCESS; +} + +/** + Clear any SMI status or wake status left from boot. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +ClearPchSmiAndWake ( + VOID + ) +{ + UINT16 ABase; + UINT16 Pm1Sts; + + + // + // Clear any SMI or wake state from the boot + // + Pm1Sts |= + ( + B_PCH_ACPI_PM1_STS_PWRBTN + ); + PchAcpiBaseGet (&ABase); + // + // Write them back + // + IoWrite16 (ABase + R_PCH_ACPI_PM1_STS, Pm1Sts); + + // + // Clear the GPE and PM enable + // + IoWrite16 (ABase + R_PCH_ACPI_PM1_EN, 0); + IoWrite32 (ABase + R_PCH_ACPI_GPE0_EN_127_96, 0); + + return EFI_SUCCESS; +} + +EFI_STATUS +PlatformInitGpios ( + VOID +) +{ + EFI_STATUS Status; + GPIO_INIT_CONFIG *GpioTable; + UINTN TableSize; + + TableSize = mGpioTableSizeMicrosoftWcs; + DEBUG ((DEBUG_ERROR, "UBA:Size of GpioTable 0x%X, blocks: 0x%X.\n", TableSize, (TableSize/sizeof (GPIO_INIT_CONFIG)) )); + + GpioTable = &mGpioTableMicrosoftWcs; + DEBUG ((DEBUG_ERROR, "UBA: ConfigureGpio() MtOlympus Start.\n")); + Status = GpioConfigurePads (TableSize/sizeof (GPIO_INIT_CONFIG), GpioTable); + DEBUG ((DEBUG_ERROR, "UBA: ConfigureGpio() MtOlympus End.\n")); + + return EFI_SUCCESS; +} + +VOID +SetUsbConfig ( + VOID + ) +{ + PcdSet64 (PcdUsb20OverCurrentMappings, (UINT64)(UINTN)Usb20OverCurrentMappings); + PcdSet64 (PcdUsb30OverCurrentMappings, (UINT64)(UINTN)Usb30OverCurrentMappings); +} + +VOID +IioPortBifurcationConfig ( + VOID + ) +{ + PcdSet64 (PcdIioBifurcationTable, (UINT64)(UINTN)mIioBifurcationTable); + PcdSet8 (PcdIioBifurcationTableEntries, mIioBifurcationTableEntries); + PcdSet64 (PcdIioSlotTable, (UINT64)(UINTN)mIioSlotTable); + PcdSet8 (PcdIioSlotTableEntries, mIioSlotTableEntries); +} + +VOID +AllLanesEparamTableConfig ( + VOID + ) +{ + PcdSet64 (PcdAllLanesEparamTable, (UINT64)(UINTN)KtiMtOlympusAllLanesEparamTable); + PcdSet32 (PcdAllLanesEparamTableSize, KtiMtOlympusAllLanesEparamTableSize); +} + +EFI_STATUS +PchLanConfig ( + IN SYSTEM_CONFIGURATION *SystemConfig +) +{ + GpioSetOutputValue (GPIO_SKL_H_GPP_I9, (UINT32)SystemConfig->LomDisableByGpio); + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +MtOlympusBoardInitBeforeMemoryInit ( + VOID + ) +{ + EFI_STATUS Status; + SETUP_DATA SetupData; + SYSTEM_CONFIGURATION SystemConfiguration; + PCH_RC_CONFIGURATION PchRcConfiguration; + SOCKET_CONFIGURATION SocketConfiguration; + UINT16 ABase; + UINT16 Pm1Sts; + UINT32 Pm1Cnt; + CONST EFI_PEI_SERVICES ** PeiServices; + + PeiServices = GetPeiServicesTablePointer (); + + ZeroMem (&SetupData, sizeof(SETUP_DATA)); + CopyMem (&SetupData.SocketConfig.IioConfig, PcdGetPtr(PcdSocketIioConfigData), sizeof(SOCKET_IIO_CONFIGURATION)); + CopyMem (&SetupData.SocketConfig.CommonRcConfig, PcdGetPtr(PcdSocketCommonRcConfigData), sizeof(SOCKET_COMMONRC_CONFIGURATION)); + CopyMem (&SetupData.SocketConfig.CsiConfig, PcdGetPtr(PcdSocketMpLinkConfigData), sizeof(SOCKET_MP_LINK_CONFIGURATION)); + CopyMem (&SetupData.SocketConfig.MemoryConfig, PcdGetPtr(PcdSocketMemoryConfigData), sizeof(SOCKET_MEMORY_CONFIGURATION)); + CopyMem (&SetupData.SocketConfig.PowerManagementConfig, PcdGetPtr(PcdSocketPowerManagementConfigData), sizeof(SOCKET_POWERMANAGEMENT_CONFIGURATION)); + CopyMem (&SetupData.SocketConfig.SocketProcessorCoreConfiguration, PcdGetPtr(PcdSocketProcessorCoreConfigData), sizeof(SOCKET_PROCESSORCORE_CONFIGURATION)); + CopyMem (&SetupData.SystemConfig, PcdGetPtr(PcdSetupData), sizeof(SYSTEM_CONFIGURATION)); + CopyMem (&SetupData.PchRcConfig, PcdGetPtr(PcdPchRcConfigurationData), sizeof(PCH_RC_CONFIGURATION)); + + CopyMem (&SocketConfiguration, &(SetupData.SocketConfig), sizeof (SOCKET_CONFIGURATION)); + CopyMem (&PchRcConfiguration, &(SetupData.PchRcConfig), sizeof (PCH_RC_CONFIGURATION)); + CopyMem (&SystemConfiguration, &(SetupData.SystemConfig), sizeof (SYSTEM_CONFIGURATION)); + + /// + /// Set LPC SIO + /// + MmioOr16( + (MmPciBase(DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, PCI_FUNCTION_NUMBER_PCH_LPC) + R_PCH_LPC_IOE), + B_PCH_LPC_IOE_SE + ); + + LpcSioEarlyInit (); + + Status = PlatformInitGpios (); + ASSERT_EFI_ERROR (Status); + + SetUsbConfig (); + IioPortBifurcationConfig (); + AllLanesEparamTableConfig (); + + /// + /// Do Early PCH init + /// + EarlyPlatformPchInit ((EFI_PEI_SERVICES**)PeiServices, &SystemConfiguration, &PchRcConfiguration); + + /// + /// Clear PCH SMI and Wake + /// Clear all pending SMI. On S3 clear power button enable so it will not generate an SMI. + /// + Status = ClearPchSmiAndWake(); + ASSERT_EFI_ERROR (Status); + ///---------------------------------------------------------------------------------- + /// + /// BIOS should check the WAK_STS bit in PM1_STS[15] (PCH register ABASE+00h) before memory + /// initialization to determine if ME has reset the system while the host was in a sleep state. + /// If WAK_STS is not set, BIOS should ensure a non-sleep exit path is taken by overwriting + /// PM1_CNT[12:10] (PCH register ABASE+04h) to 111b to force an s5 exit. + /// + PchAcpiBaseGet (&ABase); + Pm1Sts = IoRead16 (ABase + R_PCH_ACPI_PM1_STS); + if ((Pm1Sts & B_PCH_ACPI_PM1_STS_WAK) == 0) { + Pm1Cnt = IoRead32 (ABase + R_PCH_ACPI_PM1_CNT); + Pm1Cnt |= V_PCH_ACPI_PM1_CNT_S5; + IoWrite32 (ABase + R_PCH_ACPI_PM1_CNT, Pm1Cnt); + } + + UpdatePlatformInfo (&SystemConfiguration, &SocketConfiguration); + + // + // Do platform specific on-board Zoar init + // + PchLanConfig (&SystemConfiguration); + + return EFI_SUCCESS; +} + +/** + + Turn off system if needed. + + @param PeiServices Pointer to PEI Services + @param CpuIo Pointer to CPU I/O Protocol + + @retval None. + +**/ +VOID +CheckPowerOffNow ( + VOID + ) +{ + + UINT16 Pm1Sts; + + // + // Read and check the ACPI registers + // + Pm1Sts = IoRead16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_STS); + DEBUG ((EFI_D_ERROR, "CheckPowerOffNow()- Pm1Sts= 0x%04x\n", Pm1Sts )); + + if ((Pm1Sts & B_PCH_ACPI_PM1_STS_PWRBTN) == B_PCH_ACPI_PM1_STS_PWRBTN) { + IoWrite16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_STS, B_PCH_ACPI_PM1_STS_PWRBTN); + IoWrite16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_CNT, V_PCH_ACPI_PM1_CNT_S5); + IoWrite16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_CNT, V_PCH_ACPI_PM1_CNT_S5 + B_PCH_ACPI_PM1_CNT_SLP_EN); + } +} + +EFI_STATUS +EFIAPI +MtOlympusBoardInitAfterMemoryInit ( + VOID + ) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + UINT16 Pm1Cnt; + + Status = PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + // + // Check if user wants to turn off in PEI phase + // + if (BootMode != BOOT_ON_S3_RESUME) { + CheckPowerOffNow (); + } else { + Pm1Cnt = IoRead16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_CNT); + Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SLP_TYP; + IoWrite16 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_CNT, Pm1Cnt); + } + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +MtOlympusBoardDebugInit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +EFI_BOOT_MODE +EFIAPI +MtOlympusBoardBootModeDetect ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/UsbOC.c b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/UsbOC.c new file mode 100644 index 0000000000..7ff9d875ad --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/Library/BoardInitLib/UsbOC.c @@ -0,0 +1,51 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include + +#include +#include +#include + +PCH_USB_OVERCURRENT_PIN Usb20OverCurrentMappings[PCH_MAX_USB2_PORTS] = { + PchUsbOverCurrentPinSkip, //1 BMC,skip + PchUsbOverCurrentPinSkip, //2 BMC,skip + PchUsbOverCurrentPin0, //3 USB REAR PANEL, OC0 + PchUsbOverCurrentPin1, //4 USB REAR PANEL, OC1 + PchUsbOverCurrentPin1, //5 USB REAR PANEL, OC1 + PchUsbOverCurrentPinSkip, //6 Internal USB3.0, NC, skip(org OC2 in schematic) + PchUsbOverCurrentPinSkip, //7 NC, skip + PchUsbOverCurrentPin4, //8 Internal USB2.0, OC4 + PchUsbOverCurrentPinSkip, //9 NC, skip + PchUsbOverCurrentPinSkip, //10 NC, skip + PchUsbOverCurrentPin6, //11 USB FRONT PANEL, OC6 + PchUsbOverCurrentPin5, //12 USB STORAGE FRONT PANNEL, OC5 + PchUsbOverCurrentPin6, //13 USB FRONT PANEL, OC6 + PchUsbOverCurrentPin5, //14 USB STORAGE FRONT PANNEL, OC5 + PchUsbOverCurrentPinSkip, + PchUsbOverCurrentPinSkip + }; + +PCH_USB_OVERCURRENT_PIN Usb30OverCurrentMappings[PCH_MAX_USB3_PORTS] = { + PchUsbOverCurrentPin6, //1 USB FRONT PANEL, OC6 + PchUsbOverCurrentPin6, //2 USB FRONT PANEL, OC6 + PchUsbOverCurrentPin0, //3 USB REAR PANEL, OC0 + PchUsbOverCurrentPin1, //4 USB REAR PANEL, OC1 + PchUsbOverCurrentPin1, //5 USB REAR PANEL, OC1 + PchUsbOverCurrentPinSkip, //6 Internal USB3.0, NC, skip(org OC2 in schematic) + PchUsbOverCurrentPinSkip, + PchUsbOverCurrentPinSkip, + PchUsbOverCurrentPinSkip, + PchUsbOverCurrentPinSkip + }; + diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.dsc b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.dsc new file mode 100644 index 0000000000..2967c3950a --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.dsc @@ -0,0 +1,225 @@ +### @file +# +# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +### + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + DEFINE BOARD_NAME = BoardMtOlympus + DEFINE BOARD_PKG = PurleyOpenBoardPkg + DEFINE SILICON_BIN_PKG = PurleySiliconBinPkg + DEFINE RC_PKG = PurleyRcPkg + DEFINE SKT_PKG = PurleySktPkg + DEFINE PCH_PKG = LewisburgPkg + DEFINE DXE_ARCH = X64 + DEFINE PEI_ARCH = IA32 + + PLATFORM_NAME = Purley + PLATFORM_GUID = D7EAF54D-C9B9-4075-89F0-71943DBCFA61 + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010005 + OUTPUT_DIRECTORY = Build/$(BOARD_PKG)/$(BOARD_NAME) + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + + # + # Set the global variables + # + EDK_GLOBAL UEFI_PREFIX = + EDK_GLOBAL PI_PERFIX = + + EDK_GLOBAL BOARD_PKG = $(BOARD_PKG) + EDK_GLOBAL SILICON_BIN_PKG = $(SILICON_BIN_PKG) + EDK_GLOBAL SKT_PKG = $(SKT_PKG) + EDK_GLOBAL PCH_PKG = $(PCH_PKG) + + FLASH_DEFINITION = $(BOARD_PKG)/$(BOARD_NAME)/PlatformPkg.fdf + + FIX_LOAD_TOP_MEMORY_ADDRESS = 0 + + +################################################################################ +# +# SKU Identification section - list of all SKU IDs supported by this +# Platform. +# +################################################################################ +[SkuIds] + 0|DEFAULT # The entry: 0|DEFAULT is reserved and always required. + +[DefaultStores] + 0|STANDARD # UEFI Standard default 0|STANDARD is reserved. + 1|MANUFACTURING # UEFI Manufacturing default 1|MANUFACTURING is reserved. + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ + +[PcdsFeatureFlag] + # + # Platform On/Off features are defined here + # + !include $(BOARD_PKG)/$(BOARD_NAME)/PlatformPkgConfig.dsc + +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc + +!include $(RC_PKG)/RcCommonLib.dsc +!include $(SKT_PKG)/SktCommonLib.dsc +!include $(PCH_PKG)/PchCommonLib.dsc + +[LibraryClasses.common] + PlatformBootManagerLib|MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf + TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf + + CompressLib|MinPlatformPkg/Library/CompressLib/CompressLib.inf + + PciSegmentInfoLib|MinPlatformPkg/Pci/Library/PciSegmentInfoLibSimple/PciSegmentInfoLibSimple.inf + AslUpdateLib|MinPlatformPkg/Acpi/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf + + # + # Board + # + SiliconPolicyInitLib|$(BOARD_PKG)/Policy/Library/SiliconPolicyInitLib/SiliconPolicyInitLib.inf + SiliconPolicyUpdateLib|$(BOARD_PKG)/Policy/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLib.inf + PlatformHookLib|$(BOARD_PKG)/$(BOARD_NAME)/Library/BasePlatformHookLib/BasePlatformHookLib.inf + BoardInitLib|MinPlatformPkg/PlatformInit/Library/BoardInitLibNull/BoardInitLibNull.inf + + +!if gAdvancedFeaturePkgTokenSpaceGuid.PcdIpmiEnable == TRUE + IpmiLib|$(BOARD_PKG)/Features/Ipmi/Library/IpmiLibKcs/IpmiLibKcs.inf + IpmiCommandLib|AdvancedFeaturePkg/Ipmi/Library/IpmiCommandLib/IpmiCommandLib.inf + IpmiPlatformHookLib|$(BOARD_PKG)/Features/Ipmi/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf +!endif + +## -------------------------------------------------------------- +## End of section, don't put library after CpPcCommonFeature.dsc +## -------------------------------------------------------------- + +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc +!include $(RC_PKG)/RcPeiLib.dsc +!include $(SKT_PKG)/SktPeiLib.dsc +!include $(PCH_PKG)/PchPeiLib.dsc + +[LibraryClasses.IA32] +!if $(TARGET) == DEBUG + TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf +!endif + TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/PeiTestPointLib.inf + +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc +!include $(RC_PKG)/RcDxeLib.dsc +!include $(SKT_PKG)/SktDxeLib.dsc +!include $(PCH_PKG)/PchDxeLib.dsc + +[LibraryClasses.X64] + BoardAcpiTableLib|$(BOARD_PKG)/$(BOARD_NAME)/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf +!if $(TARGET) == DEBUG + TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/DxeTestPointCheckLib.inf +!endif + TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/DxeTestPointLib.inf + +[LibraryClasses.X64.DXE_SMM_DRIVER] +!if $(TARGET) == DEBUG + TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/SmmTestPointCheckLib.inf +!endif + TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/SmmTestPointLib.inf + +!include $(BOARD_PKG)/$(BOARD_NAME)/PlatformPkgPcd.dsc + +[Components.IA32] + +!include MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc +!include AdvancedFeaturePkg/Include/Dsc/CoreAdvancedPeiInclude.dsc + + $(SILICON_BIN_PKG)/FvTempMemorySilicon/$(TARGET)/FvTempMemorySilicon.inf + $(SILICON_BIN_PKG)/FvPreMemorySilicon/$(TARGET)/FvPreMemorySilicon.inf + $(SILICON_BIN_PKG)/FvPostMemorySilicon/$(TARGET)/FvPostMemorySilicon.inf + +!if gAdvancedFeaturePkgTokenSpaceGuid.PcdIpmiEnable == TRUE + AdvancedFeaturePkg/Ipmi/IpmiInit/PeiIpmiInit.inf + AdvancedFeaturePkg/Ipmi/Frb/FrbPei.inf +!endif + + $(BOARD_PKG)/Policy/SystemBoard/SystemBoardPei.inf + + MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf { + + BoardInitLib|$(BOARD_PKG)/$(BOARD_NAME)/Library/BoardInitLib/PeiBoardInitPreMemLib.inf + } + MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf { + + BoardInitLib|$(BOARD_PKG)/$(BOARD_NAME)/Library/BoardInitLib/PeiBoardInitPostMemLib.inf + } + MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf + MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf + +[Components.X64] + +!include MinPlatformPkg/Include/Dsc/CoreDxeInclude.dsc +!include AdvancedFeaturePkg/Include/Dsc/CoreAdvancedDxeInclude.dsc + + $(SILICON_BIN_PKG)/FvLateSilicon/$(TARGET)/FvLateSilicon.inf + +!if gAdvancedFeaturePkgTokenSpaceGuid.PcdIpmiEnable == TRUE + AdvancedFeaturePkg/Ipmi/IpmiInit/DxeIpmiInit.inf + AdvancedFeaturePkg/Ipmi/Frb/FrbDxe.inf + AdvancedFeaturePkg/Ipmi/OsWdt/OsWdt.inf + AdvancedFeaturePkg/Ipmi/SolStatus/SolStatus.inf + AdvancedFeaturePkg/Ipmi/IpmiFru/IpmiFru.inf + AdvancedFeaturePkg/Ipmi/BmcElog/BmcElog.inf + AdvancedFeaturePkg/Ipmi/BmcAcpi/BmcAcpi.inf +!endif + + $(SILICON_BIN_PKG)/Microcode/Microcode.inf + + $(BOARD_PKG)/Policy/IioUdsDataDxe/IioUdsDataDxe.inf + $(BOARD_PKG)/Policy/PlatformCpuPolicy/PlatformCpuPolicy.inf + $(BOARD_PKG)/Pci/PciPlatform/PciPlatform.inf + $(BOARD_PKG)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf { + + MSFT:*_*_*_ASLCC_FLAGS = /D PURLEY_FLAG /D PCH_SPT + GCC:*_*_*_ASLCC_FLAGS = -D PURLEY_FLAG -D PCH_SPT + } + +# This is for prebuild only. No need to include in final FDF. + $(BOARD_PKG)/Acpi/BoardAcpiDxe/Dsdt.inf { + + MSFT:*_*_*_ASLCC_FLAGS = /D PURLEY_FLAG /D PCH_SPT + GCC:*_*_*_ASLCC_FLAGS = -D PURLEY_FLAG -D PCH_SPT + } + + MinPlatformPkg/Flash/SpiFvbService/SpiFvbServiceSmm.inf + MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf + MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.inf { + + BoardAcpiEnableLib|$(BOARD_PKG)/$(BOARD_NAME)/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf + } + + MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf + MinPlatformPkg/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf + +!if gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosEnable == TRUE + AdvancedFeaturePkg/Smbios/SmbiosBasicDxe/SmbiosBasicDxe.inf +!endif + + PurleyOpenBoardPkg/Policy/S3NvramSave/S3NvramSave.inf + + ShellBinPkg/UefiShell/UefiShell.inf + +!include $(BOARD_PKG)/$(BOARD_NAME)/PlatformPkgBuildOption.dsc diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.fdf b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.fdf new file mode 100644 index 0000000000..319545dda4 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.fdf @@ -0,0 +1,638 @@ +### @file +# +# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +### + +[Defines] + +# Note: FlashNv PCD naming conventions are as follows: +# Note: This should be 100% true of all PCD's in the gCpPlatFlashTokenSpaceGuid space, and for +# Others should be examined with an effort to work toward this guideline. +# PcdFlash*Base is an address, usually in the range of 0xf* of FD's, note change in FDF spec +# PcdFlash*Size is a hex count of the length of the FD or FV +# All Fv will have the form 'PcdFlashFv', and all Fd will have the form 'PcdFlashFd' +# +# Also all values will have a PCD assigned so that they can be used in the system, and +# the FlashMap edit tool can be used to change the values here, without effecting the code. +# This requires all code to only use the PCD tokens to recover the values. + +[FD.Platform] +BaseAddress = 0xFF000000 | gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress +Size = 0x01000000 | gEfiPchTokenSpaceGuid.PcdFlashAreaSize +ErasePolarity = 1 +BlockSize = 0x10000 +NumBlocks = 0x100 + +0x00000000|0x00500000 +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize +FV = FvAdvanced + +0x00500000|0x00100000 +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize +FV = FvSecurity + +0x00600000|0x00100000 +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize +FV = FvOsBoot + +0x00700000|0x00200000 +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUSize +FV = FvLateSiliconCompressed + +0x00900000|0x00400000 +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize +FV = FvUefiBoot + +0x00D00000|0x0007C000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +#NV_VARIABLE_STORE +DATA = { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid = + # { 0xFFF12B8D, 0x7696, 0x4C8B, { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }} + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0x100000 + 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, + #Signature "_FVH" #Attributes + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, + #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0x1A, 0x09, 0x00, 0x00, 0x00, 0x02, + #Blockmap[0]: 16 Blocks * 0x10000 Bytes / Block + 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, + #Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER + !if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE + # Signature: gEfiAuthenticatedVariableGuid = { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 } } + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, + !else + # Signature: gEfiVariableGuid = { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, + !endif + #Size: 0x7c000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x7BFFB8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0xBF, 0x07, 0x00, + #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +0x00D7C000|0x00002000 +#NV_EVENT_LOG + +0x00D7E000|0x00002000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +#NV_FTW_WORKING +DATA = { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid = + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }} + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved + 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 + 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +0x00D80000|0x00080000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize +#NV_FTW_SPARE + + +0x00E00000|0x00010000 +gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase|gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize +FV = MICROCODE_FV + +0x00E10000|0x00010000 +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize +FV = FvPostMemory + +0x00E20000|0x00030000 +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize +FILE = $(SILICON_BIN_PKG)/FvPostMemorySilicon/$(TARGET)/FvPostMemorySilicon.Fv + +0x00E50000|0x00060000 +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize +FV = FvPreMemory + +0x00EB0000|0x00130000 +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize +FILE = $(SILICON_BIN_PKG)/FvPreMemorySilicon/$(TARGET)/FvPreMemorySilicon.Fv + +0x00FE0000|0x00020000 +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize +FILE = $(SILICON_BIN_PKG)/FvTempMemorySilicon/$(TARGET)/FvTempMemorySilicon.Fv + +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase = gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress + gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize + +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress + gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase + 0x60 +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize - 0x60 + +SET gEfiCpuTokenSpaceGuid.PcdCpuMicrocodePatchAddress = gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress + gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase + 0x60 +SET gEfiCpuTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize - 0x60 + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +[FV.FvLateSiliconCompressed] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = BA793112-EA2E-47C4-9AFE-A8FCFE603D6D + +FILE FV_IMAGE = A626BB34-2455-4FCA-8DFB-FEE96DB0DC5F { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = $(SILICON_BIN_PKG)/FvLateSilicon/$(TARGET)/FvLateSilicon.Fv + } + } + +[FV.MICROCODE_FV] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = FALSE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + +FILE RAW = 197DB236-F856-4924-90F8-CDF12FB875F3 { + $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/X64/Microcode.bin +} + +[FV.FvPreMemory] +FvAlignment = 16 +FvForceRebase = TRUE +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 6522280D-28F9-4131-ADC4-F40EBFA45864 + + ## + # PEI Apriori file example, more PEIM module added later. + ## +INF MdeModulePkg/Core/Pei/PeiMain.inf + +!include MinPlatformPkg/Include/Fdf/CorePreMemoryInclude.fdf + +INF $(BOARD_PKG)/Policy/SystemBoard/SystemBoardPei.inf + +INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf +INF MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf + +[FV.FvPostMemory] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = C54E3E8D-9FF5-4D52-AF03-58018EB55F63 + +!include MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf + +INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf +INF MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf + +[FV.FvUefiBootUncompact] +BlockSize = 0x10000 +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0 + + ## + # DXE Phase modules + ## + + ## + # DXE Apriori file example, more DXE module added later. + ## + +!include MinPlatformPkg/Include/Fdf/CoreUefiBootInclude.fdf + +INF PurleyOpenBoardPkg/Policy/S3NvramSave/S3NvramSave.inf + +INF $(BOARD_PKG)/Policy/IioUdsDataDxe/IioUdsDataDxe.inf +INF $(BOARD_PKG)/Policy/PlatformCpuPolicy/PlatformCpuPolicy.inf +INF $(BOARD_PKG)/Pci/PciPlatform/PciPlatform.inf + +INF MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf + +INF ShellBinPkg/UefiShell/UefiShell.inf + +[FV.FvUefiBoot] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 27A72E80-3118-4c0c-8673-AA5B4EFA9613 + +FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvUefiBootUncompact + } + } + +[FV.FvOsBootUncompact] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 5AB52883-85DF-445B-99F7-E0C1D517A905 + +!include MinPlatformPkg/Include/Fdf/CoreOsBootInclude.fdf + +INF MinPlatformPkg/Flash/SpiFvbService/SpiFvbServiceSmm.inf +INF MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf +INF MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.inf + +INF RuleOverride = DRIVER_ACPITABLE $(BOARD_PKG)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf + +INF MinPlatformPkg/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf + +[FV.FvOsBoot] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 5e2363c4-3e9e-4203-b873-bb40df46c8e6 + +FILE FV_IMAGE = AC09A11F-BD9F-4C87-B656-F4868EEA89B8 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvOsBootUncompact + } + } + +[FV.FvSecurityPreMem] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = A91F91A0-0CCD-4E1C-9FD8-4DAE39F348FA + +!include MinPlatformPkg/Include/Fdf/CoreSecurityPreMemoryInclude.fdf + +[FV.FvSecurityPostMem] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 04B00029-2391-44C1-97BA-3FA8A42E9D3A + +!include MinPlatformPkg/Include/Fdf/CoreSecurityPostMemoryInclude.fdf + +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE +INF MinPlatformPkg/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf +!endif + +[FV.FvSecurityLate] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = CCBC50ED-0902-413E-BC2C-409C906F4A80 + +!include MinPlatformPkg/Include/Fdf/CoreSecurityLateInclude.fdf + +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE +INF MinPlatformPkg/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf +!endif + +[FV.FvSecurity] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 8CBBA80C-FE21-4749-B015-6EDFC34B6BE7 + +FILE FV_IMAGE = A63B2BBF-7A02-4862-BF22-A1BA5258DD68 { + SECTION FV_IMAGE = FvSecurityPreMem + } + +FILE FV_IMAGE = 47B40638-0087-4938-97CF-B56983A1A07B { + SECTION FV_IMAGE = FvSecurityPostMem + } + +FILE FV_IMAGE = 605CBDF4-61DB-4B77-BAED-65232B8EC6D6 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvSecurityLate + } + } + +[FV.FvAdvancedPreMem] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = EBC45843-B180-44D3-A485-0031A75DB16D + +!include AdvancedFeaturePkg/Include/Fdf/CoreAdvancedPreMemoryInclude.fdf + + +!if gAdvancedFeaturePkgTokenSpaceGuid.PcdIpmiEnable == TRUE +INF AdvancedFeaturePkg/Ipmi/IpmiInit/PeiIpmiInit.inf +INF AdvancedFeaturePkg/Ipmi/Frb/FrbPei.inf +!endif + +[FV.FvAdvancedPostMem] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 05411CAD-6C35-4675-B6CA-8748032144B4 + +!include AdvancedFeaturePkg/Include/Fdf/CoreAdvancedPostMemoryInclude.fdf + +[FV.FvAdvancedLate] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 7397B828-4645-4B20-A13F-17890736932A + +!include AdvancedFeaturePkg/Include/Fdf/CoreAdvancedLateInclude.fdf + +!if gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosEnable == TRUE +INF AdvancedFeaturePkg/Smbios/SmbiosBasicDxe/SmbiosBasicDxe.inf +!endif + + +!if gAdvancedFeaturePkgTokenSpaceGuid.PcdIpmiEnable == TRUE +INF AdvancedFeaturePkg/Ipmi/IpmiInit/DxeIpmiInit.inf +INF AdvancedFeaturePkg/Ipmi/Frb/FrbDxe.inf +INF AdvancedFeaturePkg/Ipmi/OsWdt/OsWdt.inf +INF AdvancedFeaturePkg/Ipmi/SolStatus/SolStatus.inf +INF AdvancedFeaturePkg/Ipmi/IpmiFru/IpmiFru.inf +INF AdvancedFeaturePkg/Ipmi/BmcElog/BmcElog.inf +INF RuleOverride = DRIVER_ACPITABLE AdvancedFeaturePkg/Ipmi/BmcAcpi/BmcAcpi.inf +!endif + +[FV.FvAdvanced] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 59584CB6-0740-4EE6-A335-A46B370A101A + +FILE FV_IMAGE = 0112F63C-E0EA-4CA7-BFAA-9574DB03B230 { + SECTION FV_IMAGE = FvAdvancedPreMem + } + +FILE FV_IMAGE = 4F4083C4-5690-4417-A6B7-2E9AFEE92DD4 { + SECTION FV_IMAGE = FvAdvancedPostMem + } + +FILE FV_IMAGE = 07FC4960-5322-4DDC-A6A4-A17DE492DFE3 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvAdvancedLate + } + } + +[FV.FvDummy] +FvAlignment = 16 +FvForceRebase = FALSE +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + +# Add dummy FV here to build the PCD in FV into PCD database. +INF RuleOverride = BIN_FV $(SILICON_BIN_PKG)/FvTempMemorySilicon/$(TARGET)/FvTempMemorySilicon.inf +INF RuleOverride = BIN_FV $(SILICON_BIN_PKG)/FvPreMemorySilicon/$(TARGET)/FvPreMemorySilicon.inf +INF RuleOverride = BIN_FV $(SILICON_BIN_PKG)/FvPostMemorySilicon/$(TARGET)/FvPostMemorySilicon.inf +INF RuleOverride = BIN_FV $(SILICON_BIN_PKG)/FvLateSilicon/$(TARGET)/FvLateSilicon.inf + + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ + +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgBuildOption.dsc b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgBuildOption.dsc new file mode 100644 index 0000000000..151cbdc533 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgBuildOption.dsc @@ -0,0 +1,95 @@ +### @file +# +# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +### + +[BuildOptions.Common.EDKII] +# Append build options for EDK and EDKII drivers (= is Append, == is Replace) + + DEFINE CRB_EDKII_BUILD_OPTIONS = -D CRB_FLAG + DEFINE EDKII_CPU_BUILD_OPTIONS = -D PURLEY_FLAG + DEFINE TRAD_BUILD_OPTION = -D TRAD_FLAG=1 + DEFINE SUS_WELL_RESTORE_BUILD_OPTION = -D SUS_WELL_RESTORE=1 + DEFINE PCH_BUILD_OPTION = -D PCH_SERVER_BIOS_FLAG=1 + DEFINE SERVER_BUILD_OPTION = -D SERVER_BIOS_FLAG=1 + DEFINE PCH_PKG_OPTIONS = -D PCH_SPT + DEFINE MAX_SOCKET_OPTIONS = -D MAX_SOCKET=2 + + DEFINE EDKII_ALL_PPO_OPTIONS = $(EDKII_CPU_BUILD_OPTIONS) + DEFINE PCH_BIOS_BUILD_OPTIONS = $(TRAD_BUILD_OPTION) $(ULT_BUILD_OPTION) $(PCH_BUILD_OPTION) $(SUS_WELL_RESTORE_BUILD_OPTION) $(SERVER_BUILD_OPTION) + DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS = $(CRB_EDKII_BUILD_OPTIONS) $(PCH_BIOS_BUILD_OPTIONS) $(PCH_PKG_OPTIONS) $(EDKII_ALL_PPO_OPTIONS) $(SPARING_SCRATCHPAD_OPTION) $(TRACE_HUB_DEBUG_BUILD_OPTIONS) $(TRACE_HUB_INIT_BUILD_OPTIONS) $(MAX_SOCKET_OPTIONS) -D EFI_PCI_IOV_SUPPORT -D WHEA_SUPPORT -D SKX_HOST -D CLX_HOST + +!if $(TARGET) == "DEBUG" + DEFINE DEBUG_BUILD_FLAG = -D SERIAL_DBG_MSG=1 +!else + DEFINE DEBUG_BUILD_FLAG = -D MDEPKG_NDEBUG -D SILENT_MODE +!endif + + DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS) $(DEBUG_BUILD_FLAG) +# +# PC_BUILD_END +# + + + DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + + + *_*_IA32_CC_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_IA32_VFRPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_IA32_APP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_IA32_PP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_IA32_ASLPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_IA32_ASLCC_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + + *_*_X64_CC_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_X64_VFRPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_X64_APP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_X64_PP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_X64_ASLPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_X64_ASLCC_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + + + +# +# Enable source level debugging for RELEASE build +# +!if $(TARGET) == "RELEASE" + DEFINE EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS = /Zi + DEFINE EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS = /Zi /Gm + DEFINE EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS = /DEBUG + + MSFT:*_*_*_ASM_FLAGS = $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS) + MSFT:*_*_*_CC_FLAGS = $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS) + MSFT:*_*_*_DLINK_FLAGS = $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS) +!endif + + +# +# Override the existing iasl path in tools_def.template +# + MSFT:*_*_*_ASL_PATH == c:/Iasl/iasl.exe + +# +# Override the VFR compile flags to speed the build time +# + +*_*_*_VFR_FLAGS == -n + +# Force PE/COFF sections to be aligned at 4KB boundaries to support page level protection +[BuildOptions.common.EDKII.DXE_SMM_DRIVER, BuildOptions.common.EDKII.SMM_CORE] + MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096 + GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000 + +# Force PE/COFF sections to be aligned at 4KB boundaries to support MemoryAttribute table +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096 + GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000 diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgConfig.dsc b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgConfig.dsc new file mode 100644 index 0000000000..220b6fcff0 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgConfig.dsc @@ -0,0 +1,61 @@ +### @file +# +# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +### + +# +# TRUE is ENABLE. FALSE is DISABLE. +# + + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 + + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 1 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 2 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 3 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 4 + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5 + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE +!endif + + !if $(TARGET) == DEBUG + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE + !else + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE + !endif + + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|TRUE + + gAdvancedFeaturePkgTokenSpaceGuid.PcdNetworkEnable|TRUE + gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosEnable|TRUE + gAdvancedFeaturePkgTokenSpaceGuid.PcdIpmiEnable|TRUE + diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgPcd.dsc b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgPcd.dsc new file mode 100644 index 0000000000..a5b7f28fb2 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkgPcd.dsc @@ -0,0 +1,341 @@ +### @file +# +# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +### + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ +[PcdsFeatureFlag.common] + gPlatformTokenSpaceGuid.PcdLockCsrSsidSvidRegister|FALSE +!if $(TARGET) == RELEASE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE +!else + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE +!endif + # Server doesn't support capsle update on Reset. + gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALSE + gEfiCpuTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE + gEfiCpuTokenSpaceGuid.PcdCpuHotPlugSupport|TRUE + gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE + + +#S3 add + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE +#S3 add + + gEfiCpuTokenSpaceGuid.PcdCpuConroeFamilyFlag|FALSE + gEfiCpuTokenSpaceGuid.PcdCpuCedarMillFamilyFlag|FALSE + gEfiCpuTokenSpaceGuid.PcdCpuPrescottFamilyFlag|FALSE + gEfiCpuTokenSpaceGuid.PcdCpuNehalemFamilyFlag|FALSE + gEfiCpuTokenSpaceGuid.PcdCpuIvyBridgeFamilyFlag|FALSE + gEfiCpuTokenSpaceGuid.PcdCpuSandyBridgeFamilyFlag|FALSE + gEfiCpuTokenSpaceGuid.PcdCpuHaswellFamilyFlag|TRUE + gEfiCpuTokenSpaceGuid.PcdCpuSkylakeFamilyFlag|TRUE + + gEfiCpuTokenSpaceGuid.PcdCpuGateA20MDisableFlag|FALSE + gEfiCpuTokenSpaceGuid.PcdCpuSmmDebug|TRUE + gEfiCpuTokenSpaceGuid.PcdCpuSelectLfpAsBspFlag|TRUE + gEfiCpuTokenSpaceGuid.PcdCpuSocketIdReassignmentFlag|TRUE + + ## This PCD specified whether ACPI SDT protocol is installed. + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + +[PcdsFeatureFlag.X64] + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|FALSE + +[PcdsFeatureFlag] + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowerGrayOutReadOnlyMenu|TRUE + +[PcdsDynamicExDefault] +!include $(BOARD_PKG)/$(BOARD_NAME)/StructureConfig.dsc + +[PcdsFixedAtBuild.X64] + gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleOutputDevicePath|{0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x01, 0x00, 0x00, 0x00, 0x01, 0x01, 0x06, 0x00, 0x00, 0x01, 0x01, 0x01, 0x06, 0x00, 0x00, 0x01, 0x7F, 0xFF, 0x04, 0x00} + +[PcdsFixedAtBuild.IA32] + gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionBase|0x00FFA00000 + gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionSize|0x0000600000 + +[PcdsFixedAtBuild.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|TRUE +!if $(TARGET) == "RELEASE" + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0 + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x03 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 +!endif + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0 +#S3 modified + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000 + gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE +#S3 modified + + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0 + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x0 + gEfiMdePkgTokenSpaceGuid.PcdFSBClock|133333333 + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x100000 + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxFvSupported|32 + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPpiSupported|128 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|0x1700000 + + gEfiCpuTokenSpaceGuid.PcdCpuIEDRamSize|0x400000 + gEfiCpuTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 + gEfiCpuTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512 + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512 + gEfiCpuTokenSpaceGuid.PcdPlatformType|2 + gEfiCpuTokenSpaceGuid.PcdPlatformCpuMaxCoreFrequency|4000 + gEfiCpuTokenSpaceGuid.PcdPlatformCpuMaxFsbFrequency|1066 + gEfiCpuTokenSpaceGuid.PcdCpuSmmStackSize|0x10000 + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x10000 + + ## Specifies delay value in microseconds after sending out an INIT IPI. + # @Prompt Configure delay value after send an INIT IPI + gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10 + + ## Specifies max supported number of Logical Processors. + # @Prompt Configure max supported number of Logical Processorss + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512 + gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x1000 +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 +!endif + + gPlatformTokenSpaceGuid.PcdBusStack|0x06 + gPlatformTokenSpaceGuid.PcdUboDev|0x08 + gPlatformTokenSpaceGuid.PcdUboFunc|0x02 + gPlatformTokenSpaceGuid.PcdUboCpuBusNo0|0xCC + + gEfiCpuTokenSpaceGuid.PcdCpuIEDEnabled|TRUE + + ## Defines the ACPI register set base address. + # The invalid 0xFFFF is as its default value. It must be configured to the real value. + # @Prompt ACPI Timer IO Port Address + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress | 0x0500 + + ## Defines the PCI Bus Number of the PCI device that contains the BAR and Enable for ACPI hardware registers. + # @Prompt ACPI Hardware PCI Bus Number + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber | 0x00 + + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00000002 + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4C544E49 + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x20091013 + + ## Defines the PCI Device Number of the PCI device that contains the BAR and Enable for ACPI hardware registers. + # The invalid 0xFF is as its default value. It must be configured to the real value. + # @Prompt ACPI Hardware PCI Device Number + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber | 0x1F + + ## Defines the PCI Function Number of the PCI device that contains the BAR and Enable for ACPI hardware registers. + # The invalid 0xFF is as its default value. It must be configured to the real value. + # @Prompt ACPI Hardware PCI Function Number + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber | 0x02 + + ## Defines the PCI Register Offset of the PCI device that contains the Enable for ACPI hardware registers. + # The invalid 0xFFFF is as its default value. It must be configured to the real value. + # @Prompt ACPI Hardware PCI Register Offset + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset |0x0044 + + ## Defines the bit mask that must be set to enable the APIC hardware register BAR. + # @Prompt ACPI Hardware PCI Bar Enable BitMask + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask | 0x80 + + ## Defines the PCI Register Offset of the PCI device that contains the BAR for ACPI hardware registers. + # The invalid 0xFFFF is as its default value. It must be configured to the real value. + # @Prompt ACPI Hardware PCI Bar Register Offset + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset |0x0040 + + ## Defines the offset to the 32-bit Timer Value register that resides within the ACPI BAR. + # @Prompt Offset to 32-bit Timer register in ACPI BAR + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset |0x0008 + + ## Defines the bit mask to retrieve ACPI IO Port Base Address + # @Prompt ACPI IO Port Base Address Mask + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask |0xFFFC + + # Indicates the max nested level + gEfiCpRcPkgTokenSpaceGuid.PcdMaxNestedLevel|0x00000010 + + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount|$(MAX_SOCKET) + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|$(MAX_SOCKET) + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|28 + + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE + + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize|0x70 + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0x80 + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x1470 + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0xA0 + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x80 + + # + # The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags + # + # BIT0: If set, expresses that for all synchronous SMM entries,SMM will validate that input and output buffers lie entirely within the expected fixed memory regions. + # BIT1: If set, expresses that for all synchronous SMM entries, SMM will validate that input and output pointers embedded within the fixed communication buffer only refer to address ranges \ + # that lie entirely within the expected fixed memory regions. + # BIT2: Firmware setting this bit is an indication that it will not allow reconfiguration of system resources via non-architectural mechanisms. + # BIT3-31: Reserved + # + gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07 + +[PcdsFixedAtBuild.X64] + gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeMask|0x0eB8 + gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear|2015 + gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear|2099 + # Change PcdBootManagerMenuFile to UiApp +## + + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 } + + gEfiCpuTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable |TRUE + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable |TRUE + + gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x04 + gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0000 + gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000004A5 + + gMinPlatformPkgTokenSpaceGuid.PcdAcpiEnableSwSmi|0xA0 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiDisableSwSmi|0xA1 + + gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000 + gMinPlatformPkgTokenSpaceGuid.PcdIoApicAddress|0xFEC00000 + gMinPlatformPkgTokenSpaceGuid.PcdIoApicId|0x08 + + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|32 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicIdBase|0x09 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicInterruptBase|24 + + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x500 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x504 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x550 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x508 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x580 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0 + + gMinPlatformPkgTokenSpaceGuid.PcdHpetTimerBlockId|0x8086A701 + +[PcdsPatchableInModule.common] + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000042 + +!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable == TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1 +!endif + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 + gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 + gPcAtChipsetPkgTokenSpaceGuid.PcdHpetBaseAddress|0xFED00000 + + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIobase |0x1000 + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIoLimit |0xFFFF + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase |0x90000000 + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit |0xFBFFFFFF + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase |0x380000000000 + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit |0x3803FFFFFFFF + + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600 + + gEfiCpuTokenSpaceGuid.PcdCpuSmmUseDelayIndication|FALSE + gEfiCpuTokenSpaceGuid.PcdCpuSmmUseBlockIndication|FALSE + gEfiCpuTokenSpaceGuid.PcdCpuSmmUseSmmEnableIndication|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE + + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress|0xFF800000 + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize|0x01400000 + +[PcdsDynamicExDefault.common.DEFAULT] + gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureUserConfiguration|0x002CF6CF + gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureUserConfigurationEx1|0 + gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|30000 + gEfiCpuTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|200000 + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE + + gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0 + + gEfiPchTokenSpaceGuid.PcdWakeOnRTCS5|FALSE + gEfiPchTokenSpaceGuid.PcdRtcWakeupTimeHour|0 + gEfiPchTokenSpaceGuid.PcdRtcWakeupTimeMinute|0 + gEfiPchTokenSpaceGuid.PcdRtcWakeupTimeSecond|0 + + gOemSkuTokenSpaceGuid.PcdOemSkuUplinkPortIndex|0x5 + +[PcdsDynamicExHii.common.DEFAULT] + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|3 # Variable: L"Timeout" + gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport" + + +[PcdsDynamicExDefault] + + gOemSkuTokenSpaceGuid.PcdForceTo1SConfigMode|FALSE + +## *** PURLEY_PPO *** - Added in 8th segment in PcdPcieMmcfgTablePtr to fix size assert in PcieAddressLib.c +## | MMCFG Table Header | Segment 0 | Segment 1 | Segment 2 | Segment 3 | Segment 4 | Segment 5 | Segment 6 | Segment 7 | Segment 8 + gEfiCpRcPkgTokenSpaceGuid.PcdPcieMmcfgTablePtr|{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} + + gEfiCpuTokenSpaceGuid.PcdCpuEnergyPolicy|0 + gEfiCpuTokenSpaceGuid.PcdCpuAcpiLvl2Addr|0 + gEfiCpuTokenSpaceGuid.PcdCpuPackageCStateLimit|0 + gEfiCpuTokenSpaceGuid.PcdCpuCoreCStateValue|0 + gEfiCpuTokenSpaceGuid.PcdCpuClockModulationDutyCycle|0 + gEfiCpuTokenSpaceGuid.PcdCpuHwCoordination|TRUE + gEfiCpuTokenSpaceGuid.PcdCpuDcuMode|0 + gEfiCpuTokenSpaceGuid.PcdCpuTurboOverride|0x0 + gEfiCpuTokenSpaceGuid.PcdCpuProcessorMsrLockCtrl|0 + gEfiCpuTokenSpaceGuid.PcdCpuIioLlcWaysBitMask|0x0 + gEfiCpuTokenSpaceGuid.PcdCpuExpandedIioLlcWaysBitMask|0x0 + gEfiCpuTokenSpaceGuid.PcdCpuRemoteWaysBitMask|0x0 + gEfiCpuTokenSpaceGuid.PcdPchTraceHubEn|0x0 + gEfiCpuTokenSpaceGuid.PcdCpuQlruCfgBitMask|0x0 + gEfiCpuTokenSpaceGuid.PcdSbspSelection|0xFF +# gEfiCpuTokenSpaceGuid.PcdCpuSocketId|{0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x1,0x0,0x0,0x0,0x1,0x0,0x0,0x0,0x2,0x0,0x0,0x0,0x2,0x0,0x0,0x0,0x3,0x0,0x0,0x0,0x3,0x0,0x0,0x0} + gEfiCpuTokenSpaceGuid.PcdCpuPmStructAddr|0x0 + gEfiCpuTokenSpaceGuid.PcdCpuRRQCountThreshold|0x0 + + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize|0x1F + + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L""|VOID*|36 + + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|{0x49, 0x4E, 0x54, 0x45, 0x4C, 0x20} + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x2046573030363253 + + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0 + +[PcdsDynamicExDefault.X64] + + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1 + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|0 + + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31 + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100 + + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|800 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|600 + + gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress|0 diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/StructureConfig.dsc b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/StructureConfig.dsc new file mode 100644 index 0000000000..aa2d4de4f1 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/StructureConfig.dsc @@ -0,0 +1,6222 @@ +### @file +# +# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +### + +#[PcdsDynamicEx.common.DEFAULT.MANUFACTURING] +# gOemSkuTokenSpaceGuid.PcdSetupData|L"Setup"|ec87d643-eba4-4bb5-a1e5-3f3e36b20da9|0x00 +# gOemSkuTokenSpaceGuid.PcdSetupData.serialDebugMsgLvl|0x1 +# gOemSkuTokenSpaceGuid.PcdSetupData.TagecMem|0x1 +# gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData|L"PchRcConfiguration"|d19a26a3-17f1-48c3-8a1e-11eb0a7f6e4e|0x00 +# gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchHdAudio|0x0 +# gOemSkuTokenSpaceGuid.PcdSocketIioConfigData|L"SocketIioConfig"|dd84017e-7f52-48f9-b16e-50ed9e0dbe27|0x00 +# gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData|L"SocketCommonRcConfig"|4402ca38-808f-4279-bcec-5baf8d59092f|0x00 +# gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData|L"SocketMpLinkConfig"|2b9b22de-2ad4-4abc-957d-5f18c504a05c|0x00 +# gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData|L"SocketMemoryConfig"|98cf19ed-4109-4681-b79d-9196757c7824|0x00 +# gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData|L"SocketPowerManagementConfig"|A1047342-BDBA-4DAE-A67A-40979B65C7F8|0x00 +# gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProchotLock|0x1 +# gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PkgCstEntryValCtl|0x0 +# gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboPowerLimitLock|0x1 +# gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData|L"SocketProcessorCoreConfig"|07013588-C789-4E12-A7C3-88FAFAE79F7C|0x00 +# gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorVmxEnable|0x0 +# gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorMsrLockControl|0x0 + +#[PcdsDynamicEx.common.DEFAULT.STANDARD] + #gOemSkuTokenSpaceGuid.PcdSetupData|L"Setup"|ec87d643-eba4-4bb5-a1e5-3f3e36b20da9|0x00 + gOemSkuTokenSpaceGuid.PcdSetupData|{0x0} + gOemSkuTokenSpaceGuid.PcdSetupData.CloudProfile|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.Use1GPageTable|0x1 + #gOemSkuTokenSpaceGuid.PcdSetupData.ResetOnMemMapChange|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.FanPwmOffset|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.WakeOnLanSupport|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationBreakpointType|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.bsdBreakpoint|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.ForceSetup|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.BiosGuardEnabled|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.RtoPopulateBGDirectory|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.EnableAntiFlashWearout|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.SkipXmlComprs|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.DfxAdvDebugJumper|0x2 + gOemSkuTokenSpaceGuid.PcdSetupData.serialDebugMsgLvl|0x4 + gOemSkuTokenSpaceGuid.PcdSetupData.serialDebugTrace|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.serialDebugMsgLvlTrainResults|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.VideoSelect|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.Ps2PortSwap|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.Numlock|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.WakeOnLanS5|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.BootNetwork|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.ARIEnable|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.SRIOVEnable|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.SystemPageSize|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.MRIOVEnable|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.WakeOnRTCS4S5|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.RTCWakeupTimeHour|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.RTCWakeupTimeMinute|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.RTCWakeupTimeSecond|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.LegacyPxeRom|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.EfiNetworkSupport|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.LomDisableByGpio|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.ReserveMem|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.ReserveStartAddr|0x100000 + gOemSkuTokenSpaceGuid.PcdSetupData.TagecMem|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationResetType|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationCountOuter|0x1f4 + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationCountInner|0x1f4 + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationStopOnError|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationBootWhenDone|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationSkxPciError|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationSkxPciLinkError|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationSkxPciLinkRecoveryCountError|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationSkxPciLinkRecoveryCountThreshold|0x4 + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationPchPciError|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.ValidationKtiError|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.XhciWakeOnUsbEnabled|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbLegacySupport|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmul6064|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbMassResetDelay|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbNonBoot|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu1|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu2|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu3|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu4|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu5|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu6|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu7|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu8|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu9|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu10|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu11|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu12|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu13|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu14|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu15|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbEmu16|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.PcieClockGating|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.GbePciePortNum|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.RamDebugInterface|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.TraceHubDebugInterface|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.SystemErrorEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.PoisonEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.ViralEn|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.ClearViralStatus|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.CloakingEn|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UboxToPcuMcaEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.CaterrGpioSmiEn|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.FatalErrSpinLoopEn|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.EmcaEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.LmceEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.EmcaIgnOptin|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.EmcaCsmiEn|0x2 + gOemSkuTokenSpaceGuid.PcdSetupData.EmcaMsmiEn|0x2 + gOemSkuTokenSpaceGuid.PcdSetupData.ElogCorrErrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.ElogMemErrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.ElogProcErrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.WheaSupportEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.WheaLogMemoryEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.WheaLogProcEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.WheaLogPciEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.McaBankErrInjEn|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.WheaErrorInjSupportEn|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.WheaErrInjEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.WheaPcieErrInjEn|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.PcieErrInjActionTable|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.MeSegErrorInjEn|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.ParityCheckEn|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.McBankWarmBootClearError|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.KTIFailoverSmiEn|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.MemErrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.CorrMemErrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.LeakyBktHiLeakyBktLo|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.SpareIntSelect|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.FnvErrorEn|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.FnvErrorLowPrioritySignal|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.FnvErrorHighPrioritySignal|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.IioErrorEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.IoMcaEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.IioErrorPinEn|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.IioErrRegistersClearEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.LerEn|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.DisableMAerrorLoggingDueToLER|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.IioIrpErrorEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.irpp0_parityError|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.irpp0_qtOverflow|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.irpp0_unexprsp|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.irpp0_csraccunaligned|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.irpp0_unceccCs0|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.irpp0_unceccCs1|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.irpp0_rcvdpoison|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.irpp0_crreccCs0|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.irpp0_crreccCs1|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.IioMiscErrorEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.IioVtdErrorEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.IioDmaErrorEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.IioDmiErrorEn|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.PcieErrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.IioPcieAddCorrErrorEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.IioPcieAddUnCorrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.IioPcieAerSpecCompEn|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.PcieCorrErrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.PcieUncorrErrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.PcieFatalErrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.PcieCorErrCntr|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.PcieCorErrMaskBitMap|0x3f + gOemSkuTokenSpaceGuid.PcdSetupData.PcieCorErrThres|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.PcieAerCorrErrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.PcieAerAdNfatErrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.PcieAerNfatErrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.PcieAerFatErrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.SerrPropEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.PerrPropEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.OsSigOnSerrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.OsSigOnPerrEn|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.ConsoleRedirection|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.FlowControl|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.BaudRate|0x5 + gOemSkuTokenSpaceGuid.PcdSetupData.TerminalType|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.Parity|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.DataBits|0x8 + gOemSkuTokenSpaceGuid.PcdSetupData.StopBits|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.TerminalResolution|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.LegacyOsRedirection|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.BootAllOptions|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.OverclockingSupport|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.FilterPll|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.CoreMaxOcRatio|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.CoreVoltageMode|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.CoreVoltageOverride|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.CoreExtraTurboVoltage|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.CoreVoltageOffset|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.CoreVoltageOffsetPrefix|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.ClrMaxOcRatio|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.ClrVoltageMode|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.ClrVoltageOverride|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.ClrExtraTurboVoltage|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.ClrVoltageOffset|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.ClrVoltageOffsetPrefix|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UncoreVoltageOffset|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.UncoreVoltageOffsetPrefix|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.IoaVoltageOffset|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.IoaVoltageOffsetPrefix|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.IodVoltageOffset|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.IodVoltageOffsetPrefix|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.VccIoVoltage|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.SvidEnable|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.SvidVoltageOverride|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.CpuVccInVoltage|0x167 + gOemSkuTokenSpaceGuid.PcdSetupData.FivrFaultsEnable|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.FivrEfficiencyEnable|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.SerialBaudRate|0x1c200 + gOemSkuTokenSpaceGuid.PcdSetupData.UefiOptimizedBootToggle|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.EfiWindowsInt10Workaround|0x0 + gOemSkuTokenSpaceGuid.PcdSetupData.SetShellFirst|0x1 + gOemSkuTokenSpaceGuid.PcdSetupData.UsbStackSupport|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData|{0} + #gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData|L"PchRcConfiguration"|d19a26a3-17f1-48c3-8a1e-11eb0a7f6e4e|0x00 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.FirmwareConfiguration|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchDciEn|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchDciAutoDetect|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.BoardCapability|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DeepSxMode|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.Gp27WakeFromDeepSx|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSmbus|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSerm|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchDisplay|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPciClockRun|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSirqMode|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableClockSpreadSpec|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.StateAfterG3|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.IchPort80Route|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchCrossThrottling|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchCrid|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PciePllSsc|0xff + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.UsbPrecondition|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbManualMode|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.Btcg|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.Usb3PinsTermination|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableUsb3Pin[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableUsb3Pin[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableUsb3Pin[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableUsb3Pin[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableUsb3Pin[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableUsb3Pin[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableUsb3Pin[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableUsb3Pin[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableUsb3Pin[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.EnableUsb3Pin[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbPerPortCtl|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[0]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[1]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[2]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[3]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[4]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[5]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[6]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[7]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[8]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[9]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[10]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[11]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[12]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbHsPort[13]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbSsPort[0]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbSsPort[1]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbSsPort[2]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbSsPort[3]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbSsPort[4]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbSsPort[5]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbSsPort[6]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbSsPort[7]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbSsPort[8]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchUsbSsPort[9]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.XhciIdleL1|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.XhciDisMSICapability|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.XhciOcMapEnabled|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchHdAudio|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchHdAudioCodecSelect|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchHdAudioPme|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.RtoHdaVcType|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSata|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataInterfaceMode|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataTestMode|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataSalp|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataAlternateId|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataRaidLoadEfiDriver|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.RstPcieStorageRemap[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.RstPcieStorageRemapPort[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.RstPcieStorageRemap[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.RstPcieStorageRemapPort[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.RstPcieStorageRemap[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.RstPcieStorageRemapPort[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataPort[0]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataHotPlug[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataExternal[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataMechanicalSw[0]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataSpinUp[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataType[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataTopology[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataPort[1]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataHotPlug[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataExternal[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataMechanicalSw[1]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataSpinUp[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataType[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataTopology[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataPort[2]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PxDevSlp[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataHotPlug[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataExternal[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataMechanicalSw[2]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataSpinUp[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataType[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataTopology[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataPort[3]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataHotPlug[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataExternal[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataMechanicalSw[3]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataSpinUp[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataType[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataTopology[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataPort[4]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataHotPlug[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataExternal[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataMechanicalSw[4]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataSpinUp[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataType[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataTopology[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataPort[5]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataHotPlug[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataMechanicalSw[5]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataExternal[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataSpinUp[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataType[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataTopology[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataPort[6]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataHotPlug[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataMechanicalSw[6]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataExternal[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataSpinUp[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataType[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataTopology[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataPort[7]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataHotPlug[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataMechanicalSw[7]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataExternal[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataSpinUp[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataType[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataTopology[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataHddlk|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataLedl|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataRaidR0|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataRaidR1|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataRaidR10|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataRaidR5|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataRaidIrrt|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataRaidOub|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataRaidIooe|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataRaidSrt|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.SataRaidOromDelay|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchsSata|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataInterfaceMode|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataTestMode|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataSalp|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataAlternateId|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataRaidLoadEfiDriver|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataPort[0]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataHotPlug[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataExternal[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataSpinUp[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataType[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataTopology[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataPort[1]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataHotPlug[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataExternal[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataSpinUp[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataType[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataTopology[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataPort[2]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataHotPlug[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataExternal[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataSpinUp[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataType[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataTopology[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataPort[3]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataHotPlug[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataExternal[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataSpinUp[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataType[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataTopology[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataPort[4]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataHotPlug[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataExternal[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataSpinUp[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataType[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataTopology[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataPort[5]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataHotPlug[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataExternal[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataSpinUp[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataType[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataTopology[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataHddlk|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataLedl|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataRaidR0|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataRaidR1|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataRaidR10|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataRaidR5|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataRaidIrrt|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataRaidOub|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataRaidIooe|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataRaidSrt|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.sSataRaidOromDelay|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchWakeOnLan|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSlpLanLowDc|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchLanK1Off|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PciDelayOptimizationEcr|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieComplianceTestMode|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieGlobalAspm|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieUX16CompletionTimeout|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieUX8CompletionTimeout|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieUX16MaxPayloadSize|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieUX8MaxPayloadSize|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieDmiExtSync|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieDmiStopAndScreamEnable|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.XTpmLen|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSBDE|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSBDEPort|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFunctionSwapping|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxReadRequestSize|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[0]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[0]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[1]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[1]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[2]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[2]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[3]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[3]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[4]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[4]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[5]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[5]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[6]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[6]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[7]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[7]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[8]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[8]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[9]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[9]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[10]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[10]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[11]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[11]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[12]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[12]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[13]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[13]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[14]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[14]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[15]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[15]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[16]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[16]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[17]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[17]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[18]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[18]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCm[19]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieLaneCp[19]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqOverride|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqCoeffCm[0]|0x6 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqCoeffCp[0]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqCoeffCm[1]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqCoeffCp[1]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqCoeffCm[2]|0x8 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqCoeffCp[2]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqCoeffCm[3]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqCoeffCp[3]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqCoeffCm[4]|0xa + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieSwEqCoeffCp[4]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[0]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[0]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[0]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[0]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[0]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[0]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSize[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTimeout[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[0]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMode[0]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideValue[0]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMultiplier[0]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMode[0]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideValue[0]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMultiplier[0]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[1]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[1]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[1]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[1]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[1]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[1]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSize[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTimeout[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[1]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMode[1]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideValue[1]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMultiplier[1]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMode[1]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideValue[1]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMultiplier[1]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[2]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[2]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[2]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[2]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[2]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[2]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSize[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTimeout[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[2]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMode[2]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideValue[2]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMultiplier[2]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMode[2]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideValue[2]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMultiplier[2]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[3]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[3]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[3]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[3]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[3]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[3]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSize[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTimeout[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[3]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMode[3]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideValue[3]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMultiplier[3]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMode[3]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideValue[3]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMultiplier[3]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[4]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[4]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[4]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[4]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[4]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[4]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSize[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTimeout[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[4]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMode[4]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideValue[4]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMultiplier[4]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMode[4]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideValue[4]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMultiplier[4]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[5]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[5]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[5]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[5]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[5]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[5]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSize[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTimeout[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[5]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMode[5]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideValue[5]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMultiplier[5]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMode[5]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideValue[5]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMultiplier[5]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[6]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[6]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[6]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[6]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[6]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[6]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSize[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTimeout[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[6]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMode[6]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideValue[6]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMultiplier[6]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMode[6]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideValue[6]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMultiplier[6]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[7]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[7]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[7]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[7]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[7]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[7]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSize[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTimeout[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[7]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMode[7]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideValue[7]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMultiplier[7]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMode[7]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideValue[7]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMultiplier[7]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[8]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[8]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[8]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[8]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[8]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[8]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSize[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTimeout[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[8]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMode[8]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideValue[8]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMultiplier[8]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMode[8]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideValue[8]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMultiplier[8]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[9]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[9]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[9]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[9]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[9]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[9]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSize[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTimeout[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[9]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMode[9]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideValue[9]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMultiplier[9]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMode[9]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideValue[9]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMultiplier[9]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[10]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[10]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[10]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[10]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[10]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[10]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSize[10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTimeout[10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[10]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMode[10]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideValue[10]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMultiplier[10]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMode[10]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideValue[10]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMultiplier[10]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[11]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[11]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[11]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[11]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[11]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[11]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSize[11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTimeout[11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[11]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMode[11]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideValue[11]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMultiplier[11]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMode[11]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideValue[11]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMultiplier[11]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[12]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[12]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[12]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[12]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[12]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[12]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSize[12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTimeout[12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[12]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMode[12]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideValue[12]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMultiplier[12]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMode[12]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideValue[12]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMultiplier[12]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[13]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[13]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[13]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[13]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[13]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[13]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSize[13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTimeout[13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[13]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMode[13]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideValue[13]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMultiplier[13]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMode[13]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideValue[13]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMultiplier[13]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[14]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[14]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[14]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[14]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[14]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[14]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSize[14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTimeout[14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[14]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMode[14]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideValue[14]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMultiplier[14]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMode[14]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideValue[14]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMultiplier[14]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[15]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[15]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[15]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[15]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[15]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[15]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSize[15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTimeout[15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[15]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMode[15]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideValue[15]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMultiplier[15]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMode[15]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideValue[15]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMultiplier[15]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[16]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[16]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[16]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[16]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[16]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[16]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSize[16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTimeout[16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[16]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMode[16]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideValue[16]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMultiplier[16]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMode[16]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideValue[16]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMultiplier[16]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[17]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[17]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[17]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[17]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAER[17]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[17]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSize[17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTimeout[17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[17]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMode[17]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideValue[17]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMultiplier[17]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMode[17]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideValue[17]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMultiplier[17]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[18]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[18]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[18]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[18]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[18]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSize[18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTimeout[18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[18]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMode[18]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideValue[18]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMultiplier[18]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMode[18]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideValue[18]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMultiplier[18]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEn[19]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortAspm[19]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortL1SubStates[19]|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortEqPh3Method[19]|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortACS[19]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortURE[19]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortFEE[19]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortNFE[19]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCEE[19]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSFE[19]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSNE[19]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSCE[19]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortPMCE[19]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortHPE[19]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortSpeed[19]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMSIE[19]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieTopology[19]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortMaxPayLoadSize[19]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PcieRootPortCompletionTimeout[19]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[19]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMode[19]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideValue[19]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieSnoopLatencyOverrideMultiplier[19]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMode[19]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideValue[19]|0x3c + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieNonSnoopLatencyOverrideMultiplier[19]|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrConfigLock[19]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSmmBwp|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.ThermalDeviceEnable|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.ThermalDeviceEnable|0x3 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.TraceHubEnableMode|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.MemRegion0BufferSize|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.MemRegion1BufferSize|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.Dwr_Enable|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.Dwr_Stall|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_PMCGBL|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_CPUTHRM|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_PCHTHRM|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_PBO|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_MEPBO|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_MEWDT|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_MEGBL|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_CTWDT|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_PMCWDT|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_ME_UERR|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_SYSPWR|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_OCWDT|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_IEPBO|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_IEWDT|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_IEGBLN|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_IE_UERRN|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrEn_ACRU_ERR_2H_EN|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrPmcEn_HOST_RESET_TIMEOUT|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrPmcEn_SX_ENTRY_TIMEOUT|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrPmcEn_HOST_RST_PROM|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrPmcEn_HSMB_MSG|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrPmcEn_IE_MTP_TIMEOUT|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrPmcEn_MTP_TIMEOUT|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DwrPmcEn_ESPI_ERROR_DETECT|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchP2sbDevReveal|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchP2sbUnlock|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.TestDmiAspmCtrl|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PmcReadDisable|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.TestSmbusSpdWriteDisable|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchAllUnLock|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchTraceHubHide|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchRtcLock|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchBiosLock|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchGbeFlashLockDown|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchThermalUnlock|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.FlashLockDown|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchEvaMrom0HookEnable|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchEvaMrom1HookEnable|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.TestMctpBroadcastCycle|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.DmiLinkDownHangBypass|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchAdrEn|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.AdrTimerEn|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.AdrTimerVal|0x4 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.AdrMultiplierVal|0x63 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.AdrGpioSel|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSataLtrEnable|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSataLtrOverride|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSataSnoopLatencyOverrideValue|0x28 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSataSnoopLatencyOverrideMultiplier|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSataLtrConfigLock|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSSataLtrEnable|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSSataLtrOverride|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSSataSnoopLatencyOverrideValue|0x28 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSSataSnoopLatencyOverrideMultiplier|0x2 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchSSataLtrConfigLock|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[0]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[0]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[1]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[1]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[2]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[2]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[3]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[3]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[4]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[4]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[5]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[5]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[6]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[6]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[7]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[7]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[8]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[8]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[9]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[9]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[10]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[10]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[11]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[11]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[12]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[12]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[13]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[13]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[14]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[14]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[15]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[15]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[16]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[16]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[17]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[17]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[18]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[18]|0x0 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieLtrEnable[19]|0x1 + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData.PchPcieForceLtrOverride[19]|0x0 + #gOemSkuTokenSpaceGuid.PcdSocketIioConfigData|L"SocketIioConfig"|dd84017e-7f52-48f9-b16e-50ed9e0dbe27|0x00 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData|{0x0} + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Pci64BitResourceAllocation|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieBiosTrainEnable|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieHotPlugEnable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAcpiHotPlugEnable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MultiCastEnable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.McastBaseAddrRegion|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.McastIndexPosition|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.McastNumGroup|0x8 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[4]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[5]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[6]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[7]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[8]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[9]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[10]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[11]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[12]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[13]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[14]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[15]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[16]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[17]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[18]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[19]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[20]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[21]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[22]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[23]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[24]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[25]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[26]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[27]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[28]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[29]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[30]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[31]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[32]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[33]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[34]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[35]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[36]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[37]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[38]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[39]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[40]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[41]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[42]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[43]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[44]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[45]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[46]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[47]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[48]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[49]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[50]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[51]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[52]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[53]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[54]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[55]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[56]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[57]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[58]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[59]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[60]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[61]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[62]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[63]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[64]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[65]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[66]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[67]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[68]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[69]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[70]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[71]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[72]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[73]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[74]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[75]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[76]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[77]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[78]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[79]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[80]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[81]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[82]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HidePEXPMenu[83]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NoSnoopRdCfg|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NoSnoopWrCfg|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MaxReadCompCombSize|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ProblematicPort|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DmiAllocatingFlow|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAllocatingFlow|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.HaltOnDmiDegraded|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RxClockWA|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.GlobalPme2AckTOCtrl|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MctpEn|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PCUF6Hide|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EN1K|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DualCvIoFlow|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CoherentReadPart|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CoherentReadFull|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CompletionTimeoutGlobal|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CompletionTimeoutGlobalValue|0x9 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieGlobalAspm|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.StopAndScream|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SnoopResponseHoldOff|0xf + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PCIe_LTR|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieExtendedTagField|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PCIe_AtomicOpReq|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxReadRequestSize|0x7 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieRelaxedOrdering|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigIOU0[0]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigIOU1[0]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigIOU2[0]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigMCP0[0]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigMCP1[0]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CompletionTimeout[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CompletionTimeoutValue[0]|0x9 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RpCorrectableErrorEsc[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RpUncorrectableNonFatalErrorEsc[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RpUncorrectableFatalErrorEsc[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigIOU0[1]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigIOU1[1]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigIOU2[1]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigMCP0[1]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigMCP1[1]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CompletionTimeout[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CompletionTimeoutValue[1]|0x9 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RpCorrectableErrorEsc[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RpUncorrectableNonFatalErrorEsc[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RpUncorrectableFatalErrorEsc[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigIOU0[2]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigIOU1[2]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigIOU2[2]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigMCP0[2]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigMCP1[2]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CompletionTimeout[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CompletionTimeoutValue[2]|0x9 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RpCorrectableErrorEsc[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RpUncorrectableNonFatalErrorEsc[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RpUncorrectableFatalErrorEsc[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigIOU0[3]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigIOU1[3]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigIOU2[3]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigMCP0[3]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ConfigMCP1[3]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CompletionTimeout[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CompletionTimeoutValue[3]|0x9 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RpCorrectableErrorEsc[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RpUncorrectableNonFatalErrorEsc[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RpUncorrectableFatalErrorEsc[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[4]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[5]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[6]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[7]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[8]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[9]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[10]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[11]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[12]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[13]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[14]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[15]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[16]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[17]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[18]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[19]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[20]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[21]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[22]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DevPresIoApicIio[23]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VTdSupport|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InterruptRemap|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PassThroughDma|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ATS|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IioPresent[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IioPresent[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IioPresent[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IioPresent[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IioPresent[4]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PostedInterrupt|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CoherencySupport|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[0]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[0]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[0]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[0]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[0]|0x14 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[1]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[1]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[1]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[1]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[1]|0x14 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[2]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[2]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[2]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[2]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[2]|0x14 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[3]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[3]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[3]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[3]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[3]|0x14 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[4]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[4]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[4]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[4]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[4]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[4]|0x14 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[4]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[4]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[5]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[5]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[5]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[5]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[5]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[5]|0x14 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[5]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[5]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[6]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[6]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[6]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[6]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[6]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[6]|0x14 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[6]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[6]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[7]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[7]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[7]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[7]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[7]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[7]|0x14 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[7]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[7]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[8]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[8]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[8]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[8]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[8]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[8]|0x14 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[8]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[8]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[9]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[9]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[9]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[9]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[9]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[9]|0x14 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[9]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[9]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[10]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[10]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[10]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[10]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[10]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[10]|0x14 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[10]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[10]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDEnabled[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDPortEnable[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarSz[11]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[11]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDCfgBarAttr[11]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz1[11]|0x19 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar1Attr[11]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBarSz2[11]|0x14 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[11]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.VMDMemBar2Attr[11]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAICEnabled[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieSlotOprom1|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieSlotOprom2|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieSlotOprom3|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieSlotOprom4|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieSlotOprom5|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieSlotOprom6|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieSlotOprom7|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieSlotOprom8|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisableTPH|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PrioritizeTPH|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.CbRelaxedOrdering|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[4]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[5]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[6]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[7]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[8]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[9]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[10]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[11]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[12]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[13]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[14]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[15]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[16]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[17]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[18]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[19]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[20]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[21]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[22]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[23]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[24]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[25]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[26]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[27]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[28]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[29]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[30]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3DmaEn[31]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.Cb3NoSnoopEn[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoEnable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoLtssmLogger|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoLtssmLoggerStop|0x99 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoLtssmLoggerSpeed|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoLtssmLoggerMask|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoJitterLogger|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[84]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[85]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[86]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[87]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[88]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[89]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[90]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[91]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[92]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[93]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[94]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[95]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[96]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[97]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[98]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[99]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[100]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[101]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[102]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[103]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[104]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[105]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[106]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[107]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[108]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[109]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[110]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[111]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[112]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[113]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[114]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[115]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[116]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[117]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[118]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[119]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[120]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[121]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[122]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[123]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[124]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[125]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[126]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[127]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[128]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[129]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[130]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[131]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[132]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[133]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[134]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[135]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[136]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[137]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[138]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[139]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[140]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[141]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[142]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[143]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[144]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[145]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[146]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[147]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[148]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[149]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[150]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[151]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[152]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[153]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[154]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[155]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[156]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[157]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[158]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[159]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[160]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[161]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[162]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[163]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[164]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[165]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[166]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[167]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[168]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[169]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[170]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[171]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[172]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[173]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[174]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[175]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[176]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[177]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[178]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[179]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[180]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[181]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[182]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[183]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[184]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[185]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[186]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[187]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[188]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[189]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[190]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoSocketDevFuncHide[191]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[0]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[0]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[0]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[0]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[0]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[0]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[0]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[0]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[0]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[1]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[1]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[1]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[1]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[1]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[1]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[1]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[1]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[1]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[2]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[2]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[2]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[2]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[2]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[2]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[2]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[2]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[2]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[3]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[3]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[3]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[3]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[3]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[3]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[3]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[3]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[3]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[4]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[4]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[4]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[4]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[4]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[4]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[4]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[4]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[4]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[5]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[5]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[5]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[5]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[5]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[5]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[5]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[5]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[5]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[6]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[6]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[6]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[6]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[6]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[6]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[6]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[6]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[6]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[7]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[7]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[7]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[7]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[7]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[7]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[7]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[7]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[7]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[8]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[8]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[8]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[8]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[8]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[8]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[8]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[8]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[8]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[9]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[9]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[9]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[9]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[9]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[9]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[9]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[9]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[9]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[10]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[10]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[10]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[10]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[10]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[10]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[10]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[10]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[10]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[11]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[11]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[11]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[11]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[11]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[11]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[11]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[11]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[11]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[12]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[12]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[12]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[12]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[12]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[12]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[12]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[12]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[12]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[13]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[13]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[13]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[13]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[13]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[13]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[13]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[13]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[13]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[14]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[14]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[14]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[14]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[14]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[14]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[14]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[14]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[14]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[15]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[15]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[15]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[15]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[15]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[15]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[15]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[15]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[15]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[16]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[16]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[16]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[16]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[16]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[16]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[16]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[16]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[16]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[17]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[17]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[17]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[17]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[17]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[17]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[17]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[17]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[17]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[18]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[18]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[18]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[18]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[18]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[18]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[18]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[18]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[18]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[19]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[19]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[19]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[19]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[19]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[19]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[19]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[19]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[19]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[20]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[20]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[20]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[20]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[20]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[20]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[20]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[20]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[20]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[21]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[21]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[21]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[21]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[21]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[21]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[21]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[21]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[21]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[22]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[22]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[22]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[22]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[22]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[22]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[22]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[22]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[22]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[23]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[23]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[23]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[23]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[23]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[23]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[23]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[23]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[23]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[24]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[24]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[24]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[24]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[24]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[24]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[24]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[24]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[24]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[25]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[25]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[25]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[25]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[25]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[25]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[25]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[25]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[25]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[26]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[26]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[26]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[26]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[26]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[26]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[26]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[26]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[26]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[27]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[27]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[27]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[27]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[27]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[27]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[27]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[27]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[27]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[28]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[28]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[28]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[28]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[28]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[28]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[28]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[28]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[28]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[29]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[29]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[29]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[29]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[29]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[29]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[29]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[29]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[29]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[30]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[30]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[30]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[30]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[30]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[30]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[30]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[30]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[30]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[31]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[31]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[31]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[31]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[31]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[31]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[31]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[31]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[31]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[32]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[32]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[32]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[32]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[32]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[32]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[32]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[32]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[32]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[33]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[33]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[33]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[33]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[33]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[33]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[33]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[33]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[33]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[34]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[34]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[34]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[34]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[34]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[34]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[34]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[34]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[34]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[35]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[35]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[35]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[35]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[35]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[35]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[35]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[35]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[35]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[36]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[36]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[36]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[36]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[36]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[36]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[36]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[36]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[36]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[37]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[37]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[37]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[37]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[37]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[37]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[37]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[37]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[37]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[38]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[38]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[38]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[38]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[38]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[38]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[38]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[38]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[38]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[39]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[39]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[39]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[39]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[39]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[39]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[39]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[39]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[39]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[40]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[40]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[40]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[40]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[40]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[40]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[40]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[40]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[40]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[41]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[41]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[41]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[41]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[41]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[41]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[41]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[41]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[41]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[42]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[42]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[42]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[42]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[42]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[42]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[42]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[42]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[42]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[43]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[43]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[43]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[43]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[43]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[43]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[43]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[43]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[43]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[44]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[44]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[44]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[44]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[44]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[44]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[44]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[44]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[44]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[45]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[45]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[45]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[45]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[45]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[45]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[45]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[45]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[45]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[46]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[46]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[46]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[46]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[46]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[46]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[46]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[46]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[46]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[47]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[47]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[47]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[47]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[47]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[47]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[47]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[47]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[47]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[48]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[48]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[48]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[48]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[48]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[48]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[48]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[48]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[48]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[49]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[49]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[49]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[49]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[49]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[49]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[49]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[49]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[49]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[50]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[50]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[50]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[50]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[50]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[50]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[50]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[50]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[50]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[51]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[51]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[51]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[51]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[51]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[51]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[51]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[51]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[51]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[52]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[52]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[52]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[52]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[52]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[52]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[52]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[52]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[52]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[53]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[53]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[53]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[53]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[53]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[53]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[53]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[53]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[53]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[54]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[54]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[54]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[54]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[54]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[54]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[54]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[54]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[54]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[55]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[55]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[55]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[55]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[55]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[55]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[55]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[55]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[55]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[56]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[56]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[56]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[56]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[56]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[56]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[56]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[56]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[56]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[57]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[57]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[57]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[57]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[57]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[57]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[57]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[57]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[57]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[58]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[58]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[58]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[58]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[58]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[58]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[58]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[58]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[58]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[59]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[59]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[59]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[59]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[59]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[59]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[59]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[59]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[59]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[60]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[60]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[60]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[60]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[60]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[60]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[60]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[60]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[60]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[61]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[61]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[61]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[61]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[61]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[61]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[61]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[61]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[61]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[62]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[62]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[62]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[62]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[62]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[62]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[62]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[62]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[62]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[63]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[63]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[63]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[63]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[63]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[63]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[63]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[63]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[63]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[64]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[64]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[64]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[64]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[64]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[64]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[64]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[64]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[64]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[65]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[65]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[65]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[65]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[65]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[65]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[65]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[65]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[65]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[66]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[66]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[66]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[66]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[66]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[66]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[66]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[66]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[66]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[67]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[67]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[67]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[67]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[67]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[67]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[67]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[67]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[67]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[68]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[68]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[68]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[68]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[68]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[68]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[68]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[68]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[68]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[69]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[69]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[69]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[69]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[69]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[69]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[69]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[69]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[69]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[70]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[70]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[70]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[70]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[70]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[70]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[70]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[70]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[70]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[71]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[71]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[71]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[71]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[71]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[71]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[71]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[71]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[71]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[72]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[72]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[72]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[72]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[72]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[72]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[72]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[72]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[72]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[73]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[73]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[73]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[73]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[73]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[73]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[73]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[73]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[73]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[74]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[74]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[74]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[74]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[74]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[74]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[74]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[74]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[74]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[75]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[75]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[75]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[75]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[75]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[75]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[75]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[75]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[75]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[76]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[76]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[76]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[76]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[76]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[76]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[76]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[76]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[76]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[77]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[77]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[77]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[77]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[77]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[77]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[77]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[77]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[77]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[78]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[78]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[78]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[78]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[78]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[78]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[78]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[78]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[78]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[79]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[79]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[79]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[79]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[79]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[79]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[79]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[79]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[79]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[80]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[80]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[80]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[80]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[80]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[80]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[80]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[80]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[80]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[81]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[81]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[81]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[81]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[81]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[81]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[81]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[81]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[81]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[82]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[82]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[82]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[82]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[82]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[82]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[82]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[82]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[82]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3OverrideMode[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Precursor[83]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Cursor[83]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh2_Postcursor[83]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Precursor[83]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Cursor[83]|0x29 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3ManualPh3_Postcursor[83]|0xb + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoGen3TestCard[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoDnTxPreset[83]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoRxPreset[83]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.RtoUpTxPreset[83]|0xff + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.InboundConfiguration[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[0]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[0]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[0]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[0]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[0]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[1]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[1]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[1]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[1]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[1]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[1]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[0]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[0]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[0]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[0]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[0]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[0]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[0]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[0]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[0]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[2]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[2]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[2]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[2]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[2]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[2]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[3]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[3]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[3]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[3]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[3]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[3]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[4]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[4]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[4]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[4]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[4]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[4]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[4]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[4]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[4]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[5]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[5]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[5]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[5]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[5]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[5]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[5]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[5]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[5]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[1]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[1]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[1]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[1]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[1]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[1]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[1]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[1]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[1]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[6]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[6]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[6]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[6]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[6]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[6]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[6]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[6]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[6]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[7]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[7]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[7]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[7]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[7]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[7]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[7]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[7]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[7]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[8]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[8]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[8]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[8]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[8]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[8]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[8]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[8]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[8]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[9]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[9]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[9]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[9]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[9]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[9]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[9]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[9]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[9]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[2]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[2]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[2]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[2]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[2]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[2]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[2]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[2]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[2]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[10]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[10]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[10]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[10]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[10]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[10]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[10]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[10]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[10]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[11]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[11]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[11]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[11]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[11]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[11]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[11]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[11]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[11]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[12]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[12]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[12]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[12]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[12]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[12]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[12]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[12]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[12]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[13]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[13]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[13]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[13]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[13]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[13]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[13]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[13]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[13]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[14]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[14]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[14]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[14]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[14]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[14]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[14]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[14]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[14]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[15]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[15]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[15]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[15]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[15]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[15]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[15]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[15]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[15]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[16]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[16]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[16]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[16]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[16]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[16]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[16]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[16]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[16]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[17]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[17]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[17]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[17]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[17]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[17]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[17]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[17]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[17]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[18]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[18]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[18]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[18]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[18]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[18]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[18]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[18]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[18]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[19]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[19]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[19]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[19]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[19]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[19]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[19]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[19]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[19]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[20]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[20]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[20]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[20]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[20]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[20]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[20]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[20]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[20]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[21]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[21]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[21]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[21]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[21]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[21]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[21]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[21]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[21]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[22]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[22]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[22]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[22]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[22]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[22]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[22]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[22]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[22]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[3]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[3]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[3]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[3]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[3]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[3]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[3]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[3]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[3]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[23]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[23]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[23]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[23]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[23]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[23]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[23]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[23]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[23]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[24]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[24]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[24]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[24]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[24]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[24]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[24]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[24]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[24]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[24]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[25]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[25]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[25]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[25]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[25]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[25]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[25]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[25]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[25]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[25]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[26]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[26]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[26]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[26]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[26]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[26]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[26]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[26]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[26]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[4]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[4]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[4]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[4]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[4]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[4]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[4]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[4]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[4]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[26]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[27]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[27]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[27]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[27]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[27]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[27]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[27]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[27]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[27]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[27]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[28]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[28]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[28]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[28]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[28]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[28]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[28]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[28]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[28]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[28]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[29]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[29]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[29]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[29]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[29]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[29]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[29]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[29]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[29]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[29]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[30]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[30]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[30]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[30]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[30]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[30]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[30]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[30]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[30]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[5]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[5]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[5]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[5]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[5]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[5]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[5]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[5]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[5]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[30]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[31]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[31]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[31]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[31]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[31]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[31]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[31]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[31]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[31]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[31]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[32]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[32]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[32]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[32]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[32]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[32]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[32]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[32]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[32]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[32]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[33]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[33]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[33]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[33]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[33]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[33]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[33]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[33]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[33]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[33]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[34]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[34]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[34]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[34]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[34]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[34]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[34]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[34]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[34]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[34]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[35]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[35]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[35]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[35]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[35]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[35]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[35]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[35]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[35]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[35]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[36]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[36]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[36]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[36]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[36]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[36]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[36]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[36]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[36]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[36]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[37]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[37]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[37]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[37]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[37]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[37]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[37]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[37]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[37]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[37]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[38]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[38]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[38]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[38]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[38]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[38]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[38]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[38]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[38]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[38]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[39]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[39]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[39]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[39]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[39]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[39]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[39]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[39]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[39]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[39]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[40]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[40]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[40]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[40]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[40]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[40]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[40]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[40]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[40]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[40]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[41]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[41]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[41]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[41]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[41]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[41]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[41]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[41]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[41]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[41]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[42]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[42]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[42]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[42]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[42]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[42]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[42]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[42]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[42]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[42]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[43]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[43]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[43]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[43]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[43]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[43]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[43]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[43]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[43]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[6]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[6]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[6]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[6]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[6]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[6]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[6]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[6]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[6]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[43]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[44]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[44]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[44]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[44]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[44]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[44]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[44]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[44]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[44]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[44]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[45]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[45]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[45]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[45]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[45]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[45]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[45]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[45]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[45]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[45]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[46]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[46]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[46]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[46]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[46]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[46]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[46]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[46]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[46]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[46]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[47]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[47]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[47]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[47]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[47]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[47]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[47]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[47]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[47]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[7]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[7]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[7]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[7]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[7]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[7]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[7]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[7]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[7]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[47]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[48]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[48]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[48]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[48]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[48]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[48]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[48]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[48]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[48]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[48]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[49]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[49]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[49]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[49]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[49]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[49]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[49]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[49]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[49]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[49]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[50]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[50]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[50]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[50]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[50]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[50]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[50]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[50]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[50]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[50]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[51]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[51]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[51]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[51]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[51]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[51]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[51]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[51]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[51]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[8]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[8]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[8]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[8]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[8]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[8]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[8]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[8]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[8]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[51]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[52]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[52]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[52]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[52]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[52]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[52]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[52]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[52]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[52]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[52]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[53]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[53]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[53]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[53]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[53]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[53]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[53]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[53]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[53]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[53]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[54]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[54]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[54]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[54]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[54]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[54]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[54]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[54]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[54]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[54]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[55]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[55]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[55]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[55]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[55]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[55]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[55]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[55]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[55]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[55]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[56]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[56]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[56]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[56]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[56]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[56]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[56]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[56]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[56]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[56]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[57]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[57]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[57]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[57]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[57]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[57]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[57]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[57]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[57]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[57]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[58]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[58]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[58]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[58]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[58]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[58]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[58]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[58]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[58]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[58]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[59]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[59]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[59]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[59]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[59]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[59]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[59]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[59]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[59]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[59]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[60]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[60]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[60]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[60]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[60]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[60]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[60]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[60]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[60]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[60]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[61]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[61]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[61]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[61]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[61]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[61]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[61]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[61]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[61]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[61]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[62]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[62]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[62]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[62]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[62]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[62]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[62]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[62]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[62]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[62]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[63]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[63]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[63]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[63]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[63]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[63]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[63]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[63]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[63]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[63]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[64]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[64]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[64]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[64]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[64]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[64]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[64]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[64]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[64]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[9]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[9]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[9]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[9]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[9]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[9]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[9]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[9]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[9]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[64]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[65]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[65]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[65]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[65]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[65]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[65]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[65]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[65]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[65]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[65]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[66]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[66]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[66]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[66]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[66]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[66]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[66]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[66]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[66]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[66]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[67]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[67]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[67]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[67]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[67]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[67]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[67]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[67]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[67]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[67]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[68]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[68]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[68]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[68]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[68]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[68]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[68]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[68]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[68]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[10]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[10]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[10]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[10]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[10]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[10]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[10]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[10]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[10]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[68]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[69]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[69]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[69]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[69]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[69]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[69]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[69]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[69]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[69]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[69]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[70]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[70]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[70]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[70]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[70]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[70]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[70]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[70]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[70]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[70]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[71]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[71]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[71]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[71]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[71]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[71]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[71]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[71]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[71]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[71]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[72]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[72]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[72]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[72]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[72]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[72]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[72]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[72]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[72]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbPpd[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeOverride[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSplitBar[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar23[11]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar4[11]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar5[11]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizePBar45[11]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar23[11]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar4[11]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar5[11]|0xc + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbBarSizeSBar45[11]|0x16 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbSBar01Prefetch[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.NtbXlinkCtlOverride[11]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[72]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[73]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[73]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[73]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[73]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[73]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[73]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[73]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[73]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[73]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[73]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[74]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[74]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[74]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[74]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[74]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[74]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[74]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[74]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[74]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[74]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[75]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[75]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[75]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[75]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[75]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[75]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[75]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[75]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[75]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[75]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[76]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[76]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[76]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[76]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[76]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[76]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[76]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[76]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[76]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[76]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[77]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[77]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[77]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[77]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[77]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[77]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[77]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[77]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[77]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[77]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[78]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[78]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[78]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[78]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[78]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[78]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[78]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[78]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[78]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[78]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[79]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[79]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[79]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[79]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[79]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[79]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[79]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[79]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[79]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[79]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[80]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[80]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[80]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[80]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[80]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[80]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[80]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[80]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[80]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[80]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[81]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[81]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[81]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[81]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[81]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[81]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[81]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[81]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[81]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[81]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[82]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[82]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[82]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[82]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[82]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[82]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[82]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[82]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[82]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[82]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortDisable[83]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPCAP[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SLOTHPSUP[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieLinkDis[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkSpeed[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PciePortLinkMaxWidth[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DeEmphasis[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieCommonClock[83]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieMaxPayload[83]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieDState[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieAspm[83]|0x2 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL0sLatency[83]|0x3 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieL1Latency[83]|0x4 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MsiEn[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ExtendedSync[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ComplianceMode[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.EOI[83]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSIFATEN[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSINFATEN[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.MSICOREN[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPMEn[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DISL0STx[83]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PWrtDis[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.P2PRdDis[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.DisPMETOAck[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIHP[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ACPIPM[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PcieUnsupportedRequests[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.SRIS[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.TXEQ[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.ECRC[83]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.IODC[83]|0x6 + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData.PEXPHIDE[83]|0x0 + #gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData|L"SocketCommonRcConfig"|4402ca38-808f-4279-bcec-5baf8d59092f|0x00 + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData|{0x0} + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData.MmcfgBase|0x3 + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData.MmcfgSize|0x2 + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData.MmiohBase|0x0 + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData.MmiohSize|0x0 + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData.IsocEn|0x2 + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData.NumaEn|0x1 + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData.LockStep|0x0 + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData.MirrorMode|0x0 + #gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData|L"SocketMpLinkConfig"|2b9b22de-2ad4-4abc-957d-5f18c504a05c|0x00 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData|{0} + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.DegradePrecedence|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.QpiLinkSpeedMode|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.QpiLinkSpeed|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.KtiLinkL0pEn|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.KtiLinkL1En|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.KtiFailoverEn|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.IoDcMode|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.DirectoryModeEn|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.SncEn|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.XptPrefetchEn|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.KtiPrefetchEn|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.RdCurForXptPrefetchEn|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.KtiLinkVnaOverride|0x7f + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.KtiCrcMode|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.KtiLbEn|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.LegacyVgaSoc|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.LegacyVgaStack|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.MmioP2pDis|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.QpiCpuSktHotPlugEn|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.KtiCpuSktHotPlugTopology|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.KtiSkuMismatchCheck|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.DebugPrintLevel|0xf + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.IrqThreshold|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.BusRatio[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.BusRatio[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.BusRatio[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.BusRatio[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu0P0KtiPortDisable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu0P0KtiLinkVnaOverride|0x7f + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu0P0KtiLinkSpeed|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu0P1KtiPortDisable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu0P1KtiLinkVnaOverride|0x7f + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu0P1KtiLinkSpeed|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu0P2KtiPortDisable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu0P2KtiLinkVnaOverride|0x7f + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu0P2KtiLinkSpeed|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu1P0KtiPortDisable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu1P0KtiLinkVnaOverride|0x7f + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu1P0KtiLinkSpeed|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu1P1KtiPortDisable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu1P1KtiLinkVnaOverride|0x7f + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu1P1KtiLinkSpeed|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu1P2KtiPortDisable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu1P2KtiLinkVnaOverride|0x7f + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData.Cpu1P2KtiLinkSpeed|0x2 + #gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData|L"SocketMemoryConfig"|98cf19ed-4109-4681-b79d-9196757c7824|0x00 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData|{0x0} + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Srat|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.SratMemoryHotPlug|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.SratCpuHotPlug|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.EnforcePOR|0x3 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.pprType|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.pprErrInjTest|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.DdrFreqLimit|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.imcBclk|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.promoteMrcWarnings|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.promoteWarnings|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.haltOnMemErr|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.MultiThreaded|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.EccSupport|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.spdCrcCheck|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.logParsing|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.lrdimmModuleDelay|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.HwMemTest|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.MemTestLoops|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.DdrMemoryType|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.RankMargin|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.EnableBacksideRMT|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.EnableBacksideCMDRMT|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.rmtPatternLength|0x7fff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.rmtPatternLengthExt|0x7fff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.perbitmargin|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.AttemptFastBoot|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.AttemptFastBootCold|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.MemTestOnFastBoot|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.RmtOnColdFastBoot|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.bdatEn|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ScrambleEnDDRT|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ScrambleEn|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.allowCorrectableError|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.WrCRC|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.dimmIsolation|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.WritePreamble|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ReadPreamble|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ScrambleSeedLow|0xa02b + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ScrambleSeedHigh|0xd395 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ADREn|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved_12|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.check_pm_sts|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.check_platform_detect|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.CustomRefreshRateEn|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.CustomRefreshRate|0x14 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.mcBgfThreshold|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.dllResetTestLoops|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.oppReadInWmm|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.normOppInterval|0x400 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.caParity|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.smbSpeed|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.mrcRepeatTest|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.memFlowsExt|0xffffffff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.memFlows|0xffffffff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.rankMaskEn|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Blockgnt2cmd1cyc|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Disddrtopprd|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck0ch0|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck0ch1|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck0ch2|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck0ch3|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck0ch4|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck0ch5|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck1ch0|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck1ch1|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck1ch2|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck1ch3|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck1ch4|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck1ch5|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck2ch0|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck2ch1|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck2ch2|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck2ch3|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck2ch4|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck2ch5|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck3ch0|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck3ch1|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck3ch2|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck3ch3|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck3ch4|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.sck3ch5|0xff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.PagePolicy|0x3 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.DutyCycleTraining|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.readVrefCenter|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.eyeDiagram|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.turnaroundOpt|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.oneRankTimingMode|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.pda|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.wrVrefCenter|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.thermalthrottlingsupport|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.thermalmemtrip|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.memhotSupport|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.CkeProgramming|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.SrefProgramming|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.PkgcSrefEn|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.CkeIdleTimer|0x14 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ApdEn|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.PpdEn|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.DdrtCkeEn|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.OppSrefEn|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.DdrtSrefEn|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.MdllOffEn|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.CkMode|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.XMPMode|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.XMPMode|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.XMPMode|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Vdd|0x4b0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.commandTiming|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tREFI|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tCAS|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tRP|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tRCD|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tRAS|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tWR|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tRFC|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tRRD|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tRTP|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tWTR|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tFAW|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tRC|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.tCWL|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.volMemMode|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.memInterleaveGran1LM|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ImcInterleaving|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ChannelInterleaving|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.RankInterleaving|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.SocketInterleaveBelow4GB|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved_1|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved_7|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved_2|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved_3|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved_4|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved_5|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.crQosConfig|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseAllDIMMs|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[8]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[9]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[10]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[11]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[12]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[13]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[14]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[15]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[16]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[17]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[18]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[19]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[20]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[21]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[22]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.setSecureEraseSktCh[23]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.partialmirrorsad0|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.partialmirror|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.partialmirrorsize[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.partialmirrorsize[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.partialmirrorsize[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.partialmirrorsize[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.PartialMirrorUefi|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.PartialMirrorUefiPercent|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.RankSparing|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.multiSparingRanks|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.DemandScrubMode|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.spareErrTh|0x7fff + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.leakyBktLo|0x28 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.leakyBktHi|0x29 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.SddcPlusOneEn|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.SddcPlusOneEn|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.ADDDCEn|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.AdddcErrInjEn|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.DieSparing|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.DieSparingAggressivenessLevel|0x80 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.PatrolScrub|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.PatrolScrubDuration|0x18 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.PatrolScrubAddrMode|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved_11|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.RtoMaxNodeInterleave|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.RtoHighAddressStartBitPosition|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.RtoLowMemChannel|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.RtoCfgMask2LM|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.Reserved_13|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.mdllSden|0x2 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.BwLimitTfOvrd|0x0 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.DramRaplExtendedRange|0x1 + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData.CmsEnableDramPm|0x1 + #gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData|L"SocketPowerManagementConfig"|A1047342-BDBA-4DAE-A67A-40979B65C7F8|0x00 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData|{0x0} + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SPTWorkaround|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.AcpiS3Enable|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.AcpiS4Enable|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProcessorHWPMEnable|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProcessorHWPMInterrupt|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProcessorEPPEnable|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProcessorEppProfile|0x55 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProcessorAPSrocketing|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProcessorScalability|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProcessorPPOBudget|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.WFRWAEnable|0x2 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.UFSDisable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProcessorEistEnable|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ConfigTDPLevel|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PStateDomain|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProcessorEistPsdFunc|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProcessorSinglePCTLEn|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProcessorSPD|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.BootPState|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.EETurboDisable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboMode|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.EnableXe|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.OverclockingLock|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimitRatio[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimitCores[0]|0xff + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimitRatio[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimitCores[1]|0xff + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimitRatio[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimitCores[2]|0xff + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimitRatio[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimitCores[3]|0xff + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimitRatio[4]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimitCores[4]|0xff + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimitRatio[5]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimitCores[5]|0xff + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimitRatio[6]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimitCores[6]|0xff + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimitRatio[7]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboRatioLimitCores[7]|0xff + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.LOT26UnusedVrPowerDownEnable|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProcessorAutonomousCstateEnable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.C6Enable|0xff + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProcessorC1eEnable|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.OSCx|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PackageCState|0xff + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.C2C3TT|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.DynamicL1|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PkgCLatNeg|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.LTRSwInput|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CStateLatencyCtrlValid[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CStateLatencyCtrlMultiplier[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CStateLatencyCtrlValue[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CStateLatencyCtrlValid[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CStateLatencyCtrlMultiplier[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CStateLatencyCtrlValue[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CStateLatencyCtrlValid[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CStateLatencyCtrlMultiplier[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CStateLatencyCtrlValue[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TStateEnable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.OnDieThermalThrottling|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProchotLock|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.EnableProcHot|0x3 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.EnableThermalMonitor|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProchotResponseRatio|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TCCActivationOffset|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SAPMControl|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PwrPerfTuning|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.ProcessorOutofBandAlternateEPB|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.AltEngPerfBIAS|0x7 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PwrPerfSwitch|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.WorkLdConfig|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.EngAvgTimeWdw1|0x17 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.P0TtlTimeLow1|0x23 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.P0TtlTimeHigh1|0x3a + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CurrentConfig|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.CurrentLimit|0x438 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PpcccLock|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PkgCstEntryValCtl|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SnpLatVld|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SnpLatOvrd|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SnpLatMult|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SnpLatVal|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.NonSnpLatVld|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.NonSnpLatOvrd|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.NonSnpLatMult|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.NonSnpLatVal|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.UncrPerfPlmtOvrdEn|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.EetOverrideEn|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.IoBwPlmtOvrdEn|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.IomApmOvrdEn|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.QpiApmOvrdEn|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PerfPlimitDifferential|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PerfPLimitClipC|0x1f + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PerfPLmtThshld|0xf + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PerfPLimitEn|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.FastRaplDutyCycle|0x40 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.TurboPowerLimitLock|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PowerLimit1En|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PowerLimit1Power|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PowerLimit1Time|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PowerLimit2En|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PowerLimit2Power|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PowerLimit2Time|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PmaxOffset|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti0In[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti1In[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti2In[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio0In[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio1In[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio2In[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio3In[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio4In[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio5In[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti0In[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti1In[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti2In[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio0In[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio1In[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio2In[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio3In[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio4In[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio5In[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti0In[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti1In[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti2In[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio0In[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio1In[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio2In[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio3In[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio4In[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio5In[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti0In[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti1In[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti2In[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio0In[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio1In[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio2In[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio3In[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio4In[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.PcieIio5In[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Iio0PkgcClkGateDis[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Iio1PkgcClkGateDis[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Iio2PkgcClkGateDis[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti01PkgcClkGateDis[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti23PkgcClkGateDis[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc1PkgcClkGateDis[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc0PkgcClkGateDis[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti01pllOffEna[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti23pllOffEna[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.P0pllOffEna[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.P1pllOffEna[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.P2pllOffEna[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc0pllOffEna[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc1pllOffEna[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SetvidDecayDisable[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SapmCtlLock[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Iio0PkgcClkGateDis[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Iio1PkgcClkGateDis[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Iio2PkgcClkGateDis[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti01PkgcClkGateDis[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti23PkgcClkGateDis[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc1PkgcClkGateDis[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc0PkgcClkGateDis[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti01pllOffEna[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti23pllOffEna[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.P0pllOffEna[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.P1pllOffEna[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.P2pllOffEna[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc0pllOffEna[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc1pllOffEna[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SetvidDecayDisable[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SapmCtlLock[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Iio0PkgcClkGateDis[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Iio1PkgcClkGateDis[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Iio2PkgcClkGateDis[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti01PkgcClkGateDis[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti23PkgcClkGateDis[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc1PkgcClkGateDis[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc0PkgcClkGateDis[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti01pllOffEna[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti23pllOffEna[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.P0pllOffEna[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.P1pllOffEna[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.P2pllOffEna[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc0pllOffEna[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc1pllOffEna[2]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SetvidDecayDisable[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SapmCtlLock[2]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Iio0PkgcClkGateDis[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Iio1PkgcClkGateDis[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Iio2PkgcClkGateDis[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti01PkgcClkGateDis[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti23PkgcClkGateDis[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc1PkgcClkGateDis[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc0PkgcClkGateDis[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti01pllOffEna[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Kti23pllOffEna[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.P0pllOffEna[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.P1pllOffEna[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.P2pllOffEna[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc0pllOffEna[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.Mc1pllOffEna[3]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SetvidDecayDisable[3]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData.SapmCtlLock[3]|0x0 + #gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData|L"SocketProcessorCoreConfig"|07013588-C789-4E12-A7C3-88FAFAE79F7C|0x00 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData|{0x0} + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.PchTraceHubEn|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorHyperThreadingDisable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.IedSize|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.IedTraceSize|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.TsegSize|0x5 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.AllowMixedPowerOnCpuRatio|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.CheckCpuBist|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ThreeStrikeTimer|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.FastStringEnable|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.MachineCheckEnable|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.CpuidMaxValue|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ExecuteDisableBit|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorLtsxEnable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorVmxEnable|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorSmxEnable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.LockChipset|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.BiosAcmErrorReset|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorMsrLockControl|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.PpinControl|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.DebugInterface|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.MlcStreamerPrefetcherEnable|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.MlcSpatialPrefetcherEnable|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.DCUStreamerPrefetcherEnable|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.DCUIPPrefetcherEnable|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.DCUModeSelection|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.BspSelection|0xff + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.MTRRDefTypeUncachable|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorX2apic|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ForceX2ApicIds|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.AesEnable|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ForcePhysicalModeEnable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorVirtualWireMode|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.PCIeDownStreamPECIWrite|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.PeciInTrustControlBit|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.IioLlcWaysMask|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ExpandedIioLlcWaysMask|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.RemoteWaysMask|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.QlruCfgMask_Hi|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.QlruCfgMask_Lo|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.TargetedSmi|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.eSmmSaveState|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.SmbusErrorRecovery|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.CoreDisableMask[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.IotEn[0]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.OclaMinWay[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.OclaMaxTorEntry[0]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.CoreDisableMask[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.IotEn[1]|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.OclaMinWay[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.OclaMaxTorEntry[1]|0x1 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorFlexibleRatioOverrideEnable|0x0 + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData.ProcessorFlexibleRatio|0x17 diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/bld.bat b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/bld.bat new file mode 100644 index 0000000000..a6e0605cce --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/bld.bat @@ -0,0 +1,145 @@ +@REM @file +@REM +@REM Copyright (c) 2018, Intel Corporation. All rights reserved.
+@REM This program and the accompanying materials +@REM are licensed and made available under the terms and conditions of the BSD License +@REM which accompanies this distribution. The full text of the license may be found at +@REM http://opensource.org/licenses/bsd-license.php +@REM +@REM THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +@REM WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +@REM + +@echo off + +REM Run setlocal to take a snapshot of the environment variables. endlocal is called to restore the environment. +setlocal +set SCRIPT_ERROR=0 + +REM ---- Do NOT use :: for comments Inside of code blocks() ---- + +::********************************************************************** +:: Initial Setup +::********************************************************************** + +:parseCmdLine +if "%1"=="" goto :argumentCheck + +if /I "%1"=="debug" set TARGET=DEBUG +if /I "%1"=="release" set TARGET=RELEASE + +if /I "%1"=="cleantree" ( + set BUILD_TYPE=cleantree + call :cleantree + goto :EOF +) + +shift +GOTO :parseCmdLine + +:argumentCheck: + +if /I "%TARGET%" == "" ( + echo Info: debug/release argument is empty, use DEBUG as default + set TARGET=DEBUG +) + +REM Art to notify which board you're working on +echo. +type logo.txt +echo. + +:: +:: Build configuration +:: +set BUILD_REPORT_FLAGS= +set BUILD_CMD_LINE= +set BUILD_LOG=%WORKSPACE%\Build\build.log +set BUILD_REPORT=%WORKSPACE%\Build\BuildReport.txt + +del %BUILD_LOG% *.efi *.log 2>NUL + +echo -------------------------------------------------------------------------------------------- +echo. +echo Purley Build Start +echo. +echo -------------------------------------------------------------------------------------------- + + +:doPreBuild +echo. +echo -------------------------------------------------------------------- +echo. +echo Prebuild Start +echo. +echo -------------------------------------------------------------------- +call prebuild.bat +if %SCRIPT_ERROR% NEQ 0 EXIT /b %ERRORLEVEL% + +echo -------------------------------------------------------------------- +echo. +echo Prebuild End +echo. +echo -------------------------------------------------------------------- +if %ERRORLEVEL% NEQ 0 EXIT /b %ERRORLEVEL% +timeout 1 + +:buildBios +set BUILD_CMD_LINE=%BUILD_CMD_LINE% -D MAX_SOCKET=%MAX_SOCKET% -y %BUILD_REPORT% +echo -------------------------------------------------------------------- +echo. +echo Build Start +echo. +echo -------------------------------------------------------------------- +echo. +echo build %BUILD_CMD_LINE% --log=%BUILD_LOG% %BUILD_REPORT_FLAGS% +call build %BUILD_CMD_LINE% --log=%BUILD_LOG% %BUILD_REPORT_FLAGS% +echo -------------------------------------------------------------------- +echo. +echo Build End +echo. +echo -------------------------------------------------------------------- +if %ERRORLEVEL% NEQ 0 EXIT /b %ERRORLEVEL% +timeout 1 + +:postBuild + +echo -------------------------------------------------------------------- +echo. +echo PostBuild Start +echo. +echo -------------------------------------------------------------------- +echo. +call postbuild.bat +timeout 1 +echo -------------------------------------------------------------------- +echo. +echo PostBuild End +echo. +echo -------------------------------------------------------------------- +if %ERRORLEVEL% NEQ 0 EXIT /b %ERRORLEVEL% + +echo %date% %time% +echo. + +echo -------------------------------------------------------------------------------------------- +echo. +echo Purley Build End +echo. +echo -------------------------------------------------------------------------------------------- + +if %ERRORLEVEL% NEQ 0 EXIT /b %ERRORLEVEL% +:done +endlocal & EXIT /b %SCRIPT_ERROR% + +::-------------------------------------------------------- +::-- Function section starts below here +::-------------------------------------------------------- +:cleantree +choice /t 3 /d y /m "Confirm: clean tree of intermediate files created in tree during build" +if %ERRORLEVEL% EQU 2 goto :EOF +goto :EOF + + +:ErrorHandler: +echo Error handler \ No newline at end of file diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/logo.txt b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/logo.txt new file mode 100644 index 0000000000..979ddb6691 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/logo.txt @@ -0,0 +1,11 @@ + + _____ ______ _________ ________ ___ ___ ___ _____ ______ ________ ___ ___ ________ +|\ _ \ _ \ |\___ ___\ |\ __ \ |\ \ |\ \ / /||\ _ \ _ \ |\ __ \ |\ \|\ \ |\ ____\ +\ \ \\\__\ \ \ \|___ \ \_| \ \ \|\ \ \ \ \ \ \ \/ / /\ \ \\\__\ \ \ \ \ \|\ \ \ \ \\\ \ \ \ \___|_ + \ \ \\|__| \ \ \ \ \ \ \ \\\ \ \ \ \ \ \ / / \ \ \\|__| \ \ \ \ ____\ \ \ \\\ \ \ \_____ \ + \ \ \ \ \ \ \ \ \ \ \ \\\ \ \ \ \____ \/ / / \ \ \ \ \ \ \ \ \___| \ \ \\\ \ \|____|\ \ + \ \__\ \ \__\ \ \__\ \ \_______\ \ \_______\ __/ / / \ \__\ \ \__\ \ \__\ \ \_______\ ____\_\ \ + \|__| \|__| \|__| \|_______| \|_______||\___/ / \|__| \|__| \|__| \|_______| |\_________\ + \|___|/ \|_________| + + diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/postbuild.bat b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/postbuild.bat new file mode 100644 index 0000000000..807b9421ac --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/postbuild.bat @@ -0,0 +1,101 @@ +@REM @file +@REM +@REM Copyright (c) 2018, Intel Corporation. All rights reserved.
+@REM This program and the accompanying materials +@REM are licensed and made available under the terms and conditions of the BSD License +@REM which accompanies this distribution. The full text of the license may be found at +@REM http://opensource.org/licenses/bsd-license.php +@REM +@REM THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +@REM WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +@REM + +@set SCRIPT_ERROR=0 + +set /a postbuildstep=0 + +@echo. +@echo BoardPostBuild.%postbuildstep% python PatchBinFv.py +@set /a postbuildstep=%postbuildstep%+1 +echo python %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\PatchBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\Silicon\Intel\PurleySiliconBinPkg %WORKSPACE%\Build\BuildReport.txt FvTempMemorySilicon +call python %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\PatchBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\Silicon\Intel\PurleySiliconBinPkg %WORKSPACE%\Build\BuildReport.txt FvTempMemorySilicon +if %ERRORLEVEL% NEQ 0 ( + set SCRIPT_ERROR=1 + echo PatchBinFv Error. Exit + goto :EOF +) +echo python %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\PatchBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\Silicon\Intel\PurleySiliconBinPkg %WORKSPACE%\Build\BuildReport.txt FvPreMemorySilicon +call python %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\PatchBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\Silicon\Intel\PurleySiliconBinPkg %WORKSPACE%\Build\BuildReport.txt FvPreMemorySilicon +if %ERRORLEVEL% NEQ 0 ( + set SCRIPT_ERROR=1 + echo PatchBinFv Error. Exit + goto :EOF +) +echo python %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\PatchBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\Silicon\Intel\PurleySiliconBinPkg %WORKSPACE%\Build\BuildReport.txt FvPostMemorySilicon +call python %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\PatchBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\Silicon\Intel\PurleySiliconBinPkg %WORKSPACE%\Build\BuildReport.txt FvPostMemorySilicon +if %ERRORLEVEL% NEQ 0 ( + set SCRIPT_ERROR=1 + echo PatchBinFv Error. Exit + goto :EOF +) +echo python %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\PatchBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\Silicon\Intel\PurleySiliconBinPkg %WORKSPACE%\Build\BuildReport.txt FvLateSilicon +call python %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\PatchBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\Silicon\Intel\PurleySiliconBinPkg %WORKSPACE%\Build\BuildReport.txt FvLateSilicon +if %ERRORLEVEL% NEQ 0 ( + set SCRIPT_ERROR=1 + echo PatchBinFv Error. Exit + goto :EOF +) + +@echo. +@echo BoardPostBuild.%postbuildstep% python RebaseBinFv.py +@set /a postbuildstep=%postbuildstep%+1 +echo python %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\RebaseBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\Silicon\Intel\PurleySiliconBinPkg %WORKSPACE%\Build\BuildReport.txt FvPreMemorySilicon gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase +call python %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\RebaseBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\Silicon\Intel\PurleySiliconBinPkg %WORKSPACE%\Build\BuildReport.txt FvPreMemorySilicon gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase +if %ERRORLEVEL% NEQ 0 ( + set SCRIPT_ERROR=1 + echo RebaseBinFv Error. Exit + goto :EOF +) + +echo python %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\RebaseBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\Silicon\Intel\PurleySiliconBinPkg %WORKSPACE%\Build\BuildReport.txt FvPostMemorySilicon gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase +call python %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\RebaseBinFv.py %TARGET% %WORKSPACE%\edk2-non-osi\Silicon\Intel\PurleySiliconBinPkg %WORKSPACE%\Build\BuildReport.txt FvPostMemorySilicon gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase +if %ERRORLEVEL% NEQ 0 ( + set SCRIPT_ERROR=1 + echo RebaseBinFv Error. Exit + goto :EOF +) + +@echo. +@echo BoardPostBuild.%postbuildstep% re-generate FDS +@set /a postbuildstep=%postbuildstep%+1 +echo build fds +@REM call build fds +if %ERRORLEVEL% NEQ 0 ( + set SCRIPT_ERROR=1 + echo gen FDS Error. Exit + goto :EOF +) + +@echo. +@echo BoardPostBuild.%postbuildstep% python PatchBfv.py +@set /a postbuildstep=%postbuildstep%+1 +echo python %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\PatchBfv.py %WORKSPACE%\Build\%BOARD_PKG%\%BOARD_NAME%\%TARGET%_%TOOL_CHAIN_TAG%\FV\PLATFORM.fd %WORKSPACE%\Build\BuildReport.txt gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase +call python %WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools\PatchFv\PatchBfv.py %WORKSPACE%\Build\%BOARD_PKG%\%BOARD_NAME%\%TARGET%_%TOOL_CHAIN_TAG%\FV\PLATFORM.fd %WORKSPACE%\Build\BuildReport.txt gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase +if %ERRORLEVEL% NEQ 0 ( + set SCRIPT_ERROR=1 + echo PatchBfv Error. Exit + goto :EOF +) + +:_done + +@echo. +@cd %WORKSPACE% +@if "%SCRIPT_ERROR%" == "0" ( + @echo PostBuild SUCCEEDED. +) else ( + @echo PostBuild FAILED. + Pause 0 +) + +EXIT /B %SCRIPT_ERROR% diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/prebuild.bat b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/prebuild.bat new file mode 100644 index 0000000000..7c444fb06d --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/prebuild.bat @@ -0,0 +1,213 @@ +@REM @file +@REM +@REM Copyright (c) 2018, Intel Corporation. All rights reserved.
+@REM This program and the accompanying materials +@REM are licensed and made available under the terms and conditions of the BSD License +@REM which accompanies this distribution. The full text of the license may be found at +@REM http://opensource.org/licenses/bsd-license.php +@REM +@REM THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +@REM WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +@REM + +@set SCRIPT_ERROR=0 + +set /a prebuildstep=0 + +call :check_BuildTools +if %SCRIPT_ERROR% NEQ 0 GOTO :done + +call :setBuildEnv +if %SCRIPT_ERROR% NEQ 0 GOTO :done + +call :createTargetTxt +if %SCRIPT_ERROR% NEQ 0 GOTO :done + +call :genPlatformOffsetHeaderFile +if %SCRIPT_ERROR% NEQ 0 GOTO :done + +:prebuildFinish +echo. +echo ACTIVE_PLATFORM = %WORKSPACE%\edk2-platforms\Platform\Intel\%BOARD_PKG%\%BOARD_NAME%\PlatformPkg.dsc +echo EDK_TOOLS_PATH = %EDK_TOOLS_PATH% +echo TARGET = %TARGET% +echo TARGET_ARCH = IA32 X64 +echo TOOL_CHAIN_TAG = %TOOL_CHAIN_TAG% +echo WORKSPACE = %WORKSPACE% +echo PACKAGES_PATH = %PACKAGES_PATH% +echo MAX_CONCURRENT_THREAD_NUMBER = %BUILD_MAX_CON_THREAD_NUM% +echo. +echo Build Path = %OUTPUT_DIR% +echo. + +REM Remove environment variable because it's no longer needed. +set BUILD_MAX_CON_THREAD_NUM= + +:done +REM Use done label to exit batch file and run any final steps; GOTO :EOF immediately exits. +EXIT /B %SCRIPT_ERROR% + +::-------------------------------------------------------- +::-- Function section starts below here +::-------------------------------------------------------- + +:cleanup_check_VSTools +set COMPILER_VERSION_STRING= +del cloutput.txt > nul +REM cleanup_check_VSTools is called below. When a label is called, 'GOTO :EOF' is used to return to caller. +GOTO :EOF + +:check_BuildTools +echo PreBuild.%prebuildstep% check_BuildTools +echo ..VSTools +set /a prebuildstep=%prebuildstep%+1 +set TOOL_CHAIN_TAG= +@if not defined TOOL_CHAIN_TAG ( + echo. + echo Prebuild: TOOL_CHAIN_TAG is not set before + echo. + + @if defined VS140COMNTOOLS ( + echo. + echo Set the VS2015 environment. + echo. + set CL_SEL=VS2015 + if /I "%VS140COMNTOOLS%" == "C:\Program Files\Microsoft Visual Studio 14.0\Common7\Tools\" ( + set TOOL_CHAIN_TAG=VS2015 + ) else ( + set TOOL_CHAIN_TAG=VS2015x86 + ) + if /I "%PROCESSOR_ARCHITECTURE%" == "AMD64" ( + set CL_CMDLINE="%VS140COMNTOOLS:~0,-14%VC\bin\amd64\cl.exe" + ) else ( + set CL_CMDLINE="%VS140COMNTOOLS:~0,-14%VC\bin\cl.exe" + ) + ) else if defined VS120COMNTOOLS ( + echo. + echo Set the VS2013 environment. + echo. + set CL_SEL=VS2013 + if /I "%VS120COMNTOOLS%" == "C:\Program Files\Microsoft Visual Studio 12.0\Common7\Tools\" ( + set TOOL_CHAIN_TAG=VS2013 + ) else ( + set TOOL_CHAIN_TAG=VS2013x86 + ) + if /I "%PROCESSOR_ARCHITECTURE%" == "AMD64" ( + set CL_CMDLINE="%VS120COMNTOOLS:~0,-14%VC\bin\amd64\cl.exe" + ) else ( + set CL_CMDLINE="%VS120COMNTOOLS:~0,-14%VC\bin\cl.exe" + ) + ) else ( + echo. + echo !!! ERROR !!! VS2015 or VS2013 not installed correctly. !!! + echo. + goto :ErrorExit + ) +) + +echo ..WinDDK +set CHECK_PATH_WINDDK=C:\WINDDK\3790.1830 +if not exist %CHECK_PATH_WINDDK%\bin\bin16\link16.exe ( + echo. + echo !!! ERROR !!! Could not find 16-bit linker at %CHECK_PATH_WINDDK%\bin\bin16\link16.exe. !!! + echo. + set SCRIPT_ERROR=1 +) +set CHECK_PATH_WINDDK= + +echo ..iASL +set CHECK_PATH_IASL=c:\Iasl +if not exist %CHECK_PATH_IASL%\iasl.exe ( + echo. + echo !!! ERROR !!! Could not find iASL compiler at %CHECK_PATH_IASL%\iasl.exe. !!! + echo. + set SCRIPT_ERROR=1 +) +set CHECK_PATH_IASL= + +echo ..NASM +set CHECK_PATH_NASM=c:\NASM +if not exist %CHECK_PATH_NASM%\nasm.exe ( + echo. + echo !!! ERROR !!! Could not find NASM compiler at %CHECK_PATH_NASM%\nasm.exe. !!! + echo. + set SCRIPT_ERROR=1 +) +set CHECK_PATH_NASM= + +echo ..Python +set CHECK_PATH_PYTHON=c:\Python27 +if not exist %CHECK_PATH_PYTHON%\python.exe ( + echo. + echo !!! ERROR !!! Could not find Python at %CHECK_PATH_PYTHON%\python.exe. !!! + echo. + set SCRIPT_ERROR=1 +) +set CHECK_PATH_PYTHON= +set PYTHON_HOME=C:\Python27 + +GOTO :EOF + +:setBuildEnv +echo PreBuild.%prebuildstep% SetBuildEnv +set /a prebuildstep=%prebuildstep%+1 + +@set BOARD_PKG=PurleyOpenBoardPkg +@set BOARD_NAME=BoardMtOlympus +@set MAX_SOCKET=2 + +echo. +echo BOARD_NAME=%BOARD_NAME% +echo BOARD_PKG=%BOARD_PKG% +echo MAX_SOCKET=%MAX_SOCKET% +echo TARGET=%TARGET% + +@set OUTPUT_DIR=%WORKSPACE%\Build\%BOARD_PKG%\%BOARD_NAME%\%TARGET%_%TOOL_CHAIN_TAG% + +if not exist %OUTPUT_DIR% mkdir %OUTPUT_DIR% +GOTO :EOF + +:createTargetTxt +echo PreBuild.%prebuildstep% CreateTargetTxt +set /a prebuildstep=%prebuildstep%+1 +set /a BUILD_MAX_CON_THREAD_NUM = %NUMBER_OF_PROCESSORS%-1 +@REM set /a BUILD_MAX_CON_THREAD_NUM = 1 +findstr /V "ACTIVE_PLATFORM TARGET TARGET_ARCH TOOL_CHAIN_TAG BUILD_RULE_CONF MAX_CONCURRENT_THREAD_NUMBER" %WORKSPACE%\Conf\target.txt > %OUTPUT_DIR%\target.txt 2>NUL +echo ACTIVE_PLATFORM = %WORKSPACE%/edk2-platforms/Platform/Intel/%BOARD_PKG%/%BOARD_NAME%/PlatformPkg.dsc >> %OUTPUT_DIR%\target.txt +echo TARGET = %TARGET% >> %OUTPUT_DIR%\target.txt +echo TARGET_ARCH = IA32 X64 >> %OUTPUT_DIR%\target.txt +echo TOOL_CHAIN_TAG = %TOOL_CHAIN_TAG% >> %OUTPUT_DIR%\target.txt +echo BUILD_RULE_CONF = Conf/build_rule.txt >> %OUTPUT_DIR%\target.txt +echo MAX_CONCURRENT_THREAD_NUMBER = %BUILD_MAX_CON_THREAD_NUM% >> %OUTPUT_DIR%\target.txt +if exist %WORKSPACE%\Conf\target.txt ( + del /f %WORKSPACE%\Conf\target.txt +) +move /Y %OUTPUT_DIR%\target.txt %WORKSPACE%\Conf\ > nul +if not exist %OUTPUT_DIR%\X64 mkdir %OUTPUT_DIR%\X64 +GOTO :EOF + + +:genPlatformOffsetHeaderFile +echo. +echo PreBuild.%prebuildstep% GenPlatformOffsetHeaderFile +set /a prebuildstep=%prebuildstep%+1 + +echo Info: re-generating PlatformOffset header files + +set PRE_BUILD_CMD_LINE=%BUILD_CMD_LINE% -D MAX_SOCKET=%MAX_SOCKET% +set PRE_BUILD_LOG=%WORKSPACE%\Build\prebuild.log +set PRE_BUILD_REPORT=%WORKSPACE%\Build\preBuildReport.txt + +echo build %PRE_BUILD_CMD_LINE% -m %BOARD_PKG%\Acpi\BoardAcpiDxe\Dsdt.inf -y %PRE_BUILD_REPORT% --log=%PRE_BUILD_LOG% +call build %PRE_BUILD_CMD_LINE% -m %BOARD_PKG%\Acpi\BoardAcpiDxe\Dsdt.inf -y %PRE_BUILD_REPORT% --log=%PRE_BUILD_LOG% +if %ERRORLEVEL% NEQ 0 EXIT /b %ERRORLEVEL% + +@REM PSYS == FIX0 +@REM MCTL == FIX8 +set AML_FILTER="\"PSYS\" .MCTL\" .FIX[0-9,A-Z]\"" +echo AML_FILTER=%AML_FILTER% +%WORKSPACE%\edk2-platforms\Platform\Intel\MinPlatformPkg\Tools\AmlGenOffset\AmlGenOffset.py -d --aml_filter %AML_FILTER% -o %WORKSPACE%\edk2-platforms\Platform\Intel\%BOARD_PKG%\Acpi\BoardAcpiDxe\AmlOffsetTable.c %OUTPUT_DIR%\X64\PurleyOpenBoardPkg\Acpi\BoardAcpiDxe\DSDT\OUTPUT\Dsdt\WFPPlatform.offset.h +echo. +echo GenOffset done + +GOTO :EOF \ No newline at end of file diff --git a/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/IpmiLibKcs.c b/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/IpmiLibKcs.c new file mode 100644 index 0000000000..143618d464 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/IpmiLibKcs.c @@ -0,0 +1,369 @@ +/** @file + IPMI library - KCS. + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "KcsBmc.h" + +#define MAX_TEMP_DATA 160 + +// +// Structure of IPMI Command buffer +// +#define EFI_IPMI_COMMAND_HEADER_SIZE 2 + +typedef struct { + UINT8 Lun : 2; + UINT8 NetFunction : 6; + UINT8 Command; + UINT8 CommandData[MAX_TEMP_DATA - EFI_IPMI_COMMAND_HEADER_SIZE]; +} EFI_IPMI_COMMAND; + +// +// Structure of IPMI Command response buffer +// +#define EFI_IPMI_RESPONSE_HEADER_SIZE 2 + +typedef struct { + UINT8 Lun : 2; + UINT8 NetFunction : 6; + UINT8 Command; + UINT8 ResponseData[MAX_TEMP_DATA - EFI_IPMI_RESPONSE_HEADER_SIZE]; +} EFI_IPMI_RESPONSE; + + +#define IPMI_INSTANCE_INFO_HOB_GUID { \ + 0x38ee71f, 0x1c78, 0x4874, { 0xba, 0xe3, 0xf8, 0xa2, 0x57, 0x75, 0x28, 0x52 } \ + } + +EFI_GUID mIpmiInstanceGuid = IPMI_INSTANCE_INFO_HOB_GUID; + +#define SM_IPMI_BMC_SIGNATURE SIGNATURE_32 ('i', 'p', 'm', 'i') +typedef UINT32 EFI_BMC_STATUS; +typedef struct { + UINTN Signature; + UINT64 KcsTimeoutPeriod; + UINT16 IpmiIoBase; + UINT8 SlaveAddress; + EFI_BMC_STATUS BmcStatus; + UINT64 ErrorStatus; + UINT8 SoftErrorCount; + UINT8 TempData[MAX_TEMP_DATA]; +} IPMI_INSTANCE; + +#define EFI_BMC_OK 0 +#define EFI_BMC_SOFTFAIL 1 +#define EFI_BMC_HARDFAIL 2 +#define EFI_BMC_UPDATE_IN_PROGRESS 3 +#define EFI_BMC_NOTREADY 4 + +EFI_STATUS +UpdateErrorStatus ( + IN UINT8 BmcError, + IPMI_INSTANCE *IpmiInstance + ) +/*++ + +Routine Description: + + Check if the completion code is a Soft Error and increment the count. The count + is not updated if the BMC is in Force Update Mode. + +Arguments: + + BmcError - Completion code to check + IpmiInstance - BMC instance data + +Returns: + + EFI_SUCCESS - Status + +--*/ +{ + UINT8 Errors[] = { + IPMI_COMP_CODE_NODE_BUSY, IPMI_COMP_CODE_TIMEOUT, IPMI_COMP_CODE_OUT_OF_SPACE, IPMI_COMP_CODE_OUT_OF_RANGE, + IPMI_COMP_CODE_CMD_RESP_NOT_PROVIDED, IPMI_COMP_CODE_FAIL_DUP_REQUEST, IPMI_COMP_CODE_SDR_REP_IN_UPDATE_MODE, + IPMI_COMP_CODE_DEV_IN_FW_UPDATE_MODE, IPMI_COMP_CODE_BMC_INIT_IN_PROGRESS, IPMI_COMP_CODE_UNSPECIFIED + }; + UINT16 CodeCount; + UINT8 i; + + CodeCount = sizeof (Errors) / sizeof (Errors[0]); + for (i = 0; i < CodeCount; i++) { + if (BmcError == Errors[i]) { + // + // Don't change Bmc Status flag if the BMC is in Force Update Mode. + // + if (IpmiInstance->BmcStatus != EFI_BMC_UPDATE_IN_PROGRESS) { + IpmiInstance->BmcStatus = EFI_BMC_SOFTFAIL; + } + + IpmiInstance->SoftErrorCount++; + break; + } + } + + return EFI_SUCCESS; +} + +VOID +UpdateBmcStatusOnResponse ( + IN IPMI_INSTANCE *IpmiInstance, + IN EFI_IPMI_COMMAND *IpmiCommand, + IN EFI_STATUS EfiStatus, + IN EFI_IPMI_RESPONSE *IpmiResponse + ) +{ + IPMI_GET_DEVICE_ID_RESPONSE *BmcInfo; + IPMI_SELF_TEST_RESULT_RESPONSE *TestResult; + + if ((IpmiCommand->NetFunction == IPMI_NETFN_APP) && (IpmiCommand->Command == IPMI_APP_GET_DEVICE_ID)) { + if (EFI_ERROR(EfiStatus)) { + IpmiInstance->BmcStatus = EFI_BMC_HARDFAIL; + } else { + BmcInfo = (VOID *)IpmiResponse->ResponseData; + if (BmcInfo->UpdateMode) { + IpmiInstance->BmcStatus = EFI_BMC_UPDATE_IN_PROGRESS; + } + } + } else if ((IpmiCommand->NetFunction == IPMI_NETFN_APP) && (IpmiCommand->Command == IPMI_APP_GET_DEVICE_ID)) { + if (EFI_ERROR(EfiStatus)) { + IpmiInstance->BmcStatus = EFI_BMC_HARDFAIL; + } else { + TestResult = (VOID *)IpmiResponse->ResponseData; + switch (TestResult->Result) { + case IPMI_APP_SELFTEST_NO_ERROR: + case IPMI_APP_SELFTEST_NOT_IMPLEMENTED: + IpmiInstance->BmcStatus = EFI_BMC_OK; + break; + case IPMI_APP_SELFTEST_ERROR: + // + // Three of the possible errors result in BMC hard failure; FRU Corruption, + // BootBlock Firmware corruption, and Operational Firmware Corruption. All + // other errors are BMC soft failures. + // + if ((TestResult->Param & (IPMI_APP_SELFTEST_FRU_CORRUPT | IPMI_APP_SELFTEST_FW_BOOTBLOCK_CORRUPT | IPMI_APP_SELFTEST_FW_CORRUPT)) != 0) { + IpmiInstance->BmcStatus = EFI_BMC_HARDFAIL; + } else { + IpmiInstance->BmcStatus = EFI_BMC_SOFTFAIL; + } + break; + + case IPMI_APP_SELFTEST_FATAL_HW_ERROR: + IpmiInstance->BmcStatus = EFI_BMC_HARDFAIL; + break; + + default: + break; + } + } + } +} + +/** + This service enables submitting commands via Ipmi. + + @param[in] NetFunction Net function of the command. + @param[in] Command IPMI Command. + @param[in] RequestData Command Request Data. + @param[in] RequestDataSize Size of Command Request Data. + @param[out] ResponseData Command Response Data. The completion code is the first byte of response data. + @param[in, out] ResponseDataSize Size of Command Response Data. + + @retval EFI_SUCCESS The command byte stream was successfully submit to the device and a response was successfully received. + @retval EFI_NOT_FOUND The command was not successfully sent to the device or a response was not successfully received from the device. + @retval EFI_NOT_READY Ipmi Device is not ready for Ipmi command access. + @retval EFI_DEVICE_ERROR Ipmi Device hardware error. + @retval EFI_TIMEOUT The command time out. + @retval EFI_UNSUPPORTED The command was not successfully sent to the device. + @retval EFI_OUT_OF_RESOURCES The resource allcation is out of resource or data size error. +**/ +EFI_STATUS +EFIAPI +IpmiSubmitCommand ( + IN UINT8 NetFunction, + IN UINT8 Command, + IN UINT8 *RequestData, + IN UINT32 RequestDataSize, + OUT UINT8 *ResponseData, + IN OUT UINT32 *ResponseDataSize + ) +{ + UINT8 DataSize; + EFI_STATUS Status; + EFI_IPMI_COMMAND *IpmiCommand; + EFI_IPMI_RESPONSE *IpmiResponse; + VOID *Hob; + IPMI_INSTANCE *IpmiInstance; + + DEBUG ((DEBUG_INFO, "IpmiSubmitCommand\n")); + + Hob = GetFirstGuidHob (&mIpmiInstanceGuid); + if (Hob != NULL) { + IpmiInstance = GET_GUID_HOB_DATA(Hob); + } else { + IpmiInstance = BuildGuidHob (&mIpmiInstanceGuid, sizeof(IPMI_INSTANCE)); + ASSERT(IpmiInstance != NULL); + if (IpmiInstance == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + IpmiInstance->Signature = SM_IPMI_BMC_SIGNATURE; + IpmiInstance->KcsTimeoutPeriod = PcdGet64(PcdIpmiKcsTimeoutPeriod); + IpmiInstance->SlaveAddress = PcdGet8(PcdIpmiBmcSlaveAddress); + IpmiInstance->IpmiIoBase = PcdGet16(PcdIpmiIoBaseAddress); + DEBUG((DEBUG_INFO,"IPMI KcsTimeoutPeriod=0x%x\n", IpmiInstance->KcsTimeoutPeriod)); + DEBUG((DEBUG_INFO,"IPMI SlaveAddress=0x%x\n", IpmiInstance->SlaveAddress)); + DEBUG((DEBUG_INFO,"IPMI IpmiIoBase=0x%x\n", IpmiInstance->IpmiIoBase)); + + IpmiInstance->BmcStatus = EFI_BMC_NOTREADY; + IpmiInstance->ErrorStatus = 0x00; + IpmiInstance->SoftErrorCount = 0x00; + + MicroSecondDelay(10*1000); + + Status = PlatformIpmiIoRangeSet (IpmiInstance->IpmiIoBase); + DEBUG ((DEBUG_INFO, "IPMI PlatformIpmiIoRangeSet - %r!\n", Status)); + if (EFI_ERROR(Status)) { + return Status; + } + } + + IpmiCommand = (VOID *)IpmiInstance->TempData; + IpmiResponse = (VOID *)IpmiInstance->TempData; + + // + // Send IPMI command to BMC + // + IpmiCommand->Lun = 0; + IpmiCommand->NetFunction = NetFunction; + IpmiCommand->Command = Command; + + // + // Ensure that the buffer is valid before attempting to copy the command data + // buffer into the IpmiCommand structure. + // + if (RequestDataSize > 0) { + if (RequestData == NULL) { + return EFI_INVALID_PARAMETER; + } + + CopyMem ( + IpmiCommand->CommandData, + RequestData, + RequestDataSize + ); + } + + Status = SendDataToBmcPort ( + IpmiInstance->KcsTimeoutPeriod, + IpmiInstance->IpmiIoBase, + (UINT8 *)IpmiCommand, + (UINT8)(RequestDataSize + EFI_IPMI_COMMAND_HEADER_SIZE) + ); + + if (Status != EFI_SUCCESS) { + IpmiInstance->BmcStatus = EFI_BMC_SOFTFAIL; + IpmiInstance->SoftErrorCount++; + UpdateBmcStatusOnResponse (IpmiInstance, IpmiCommand, Status, NULL); + return Status; + } + + // + // Get Response to IPMI Command from BMC. + // + DataSize = MAX_TEMP_DATA; + Status = ReceiveBmcDataFromPort ( + IpmiInstance->KcsTimeoutPeriod, + IpmiInstance->IpmiIoBase, + (UINT8 *)IpmiResponse, + &DataSize + ); + + if (Status != EFI_SUCCESS) { + IpmiInstance->BmcStatus = EFI_BMC_SOFTFAIL; + IpmiInstance->SoftErrorCount++; + UpdateBmcStatusOnResponse (IpmiInstance, IpmiCommand, Status, NULL); + return Status; + } + + // + // If we got this far without any error codes, but the DataSize is 0 then the + // command response failed, so do not continue. + // + if (DataSize < 3) { + Status = EFI_DEVICE_ERROR; + IpmiInstance->BmcStatus = EFI_BMC_SOFTFAIL; + IpmiInstance->SoftErrorCount++; + UpdateBmcStatusOnResponse (IpmiInstance, IpmiCommand, Status, NULL); + return Status; + } + + if ((IpmiResponse->ResponseData[0] != IPMI_COMP_CODE_NORMAL) && + (IpmiInstance->BmcStatus == EFI_BMC_UPDATE_IN_PROGRESS)) { + // + // If the completion code is not normal and the BMC is in Force Update + // mode, then update the error status and return EFI_UNSUPPORTED. + // + UpdateErrorStatus ( + IpmiResponse->ResponseData[0], + IpmiInstance + ); + UpdateBmcStatusOnResponse (IpmiInstance, IpmiCommand, Status, IpmiResponse); + return EFI_UNSUPPORTED; + } else if (IpmiResponse->ResponseData[0] != IPMI_COMP_CODE_NORMAL) { + // + // Otherwise if the BMC is in normal mode, but the completion code + // is not normal, then update the error status and return device error. + // + UpdateErrorStatus ( + IpmiResponse->ResponseData[0], + IpmiInstance + ); + UpdateBmcStatusOnResponse (IpmiInstance, IpmiCommand, Status, IpmiResponse); + return EFI_DEVICE_ERROR; + } + + // + // Verify the response data buffer passed in is big enough. + // + if ((UINTN)(DataSize - EFI_IPMI_RESPONSE_HEADER_SIZE) > *ResponseDataSize) { + return EFI_BUFFER_TOO_SMALL; + } + + // + // Copy data over to the response data buffer. + // + if ((ResponseData != NULL) && (ResponseDataSize != NULL) && (*ResponseDataSize != 0)) { + *ResponseDataSize = DataSize - EFI_IPMI_RESPONSE_HEADER_SIZE; + CopyMem ( + ResponseData, + IpmiResponse->ResponseData, + *ResponseDataSize + ); + } + IpmiInstance->BmcStatus = EFI_BMC_OK; + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/IpmiLibKcs.inf b/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/IpmiLibKcs.inf new file mode 100644 index 0000000000..c4796d594a --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/IpmiLibKcs.inf @@ -0,0 +1,46 @@ +### @file +# Component description file for IPMI KCS Library. +# +# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +### + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = IpmiLibKcs + FILE_GUID = 9879DB3A-C2CD-4615-ACDA-95C1B2EC00B3 + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = IpmiLib + +[sources] + IpmiLibKcs.c + KcsBmc.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + AdvancedFeaturePkg/AdvancedFeaturePkg.dec + PurleyOpenBoardPkg/PlatPkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + HobLib + PcdLib + TimerLib + IoLib + IpmiPlatformHookLib + +[Pcd] + gEfiIpmiPkgTokenSpaceGuid.PcdIpmiKcsTimeoutPeriod + gEfiIpmiPkgTokenSpaceGuid.PcdIpmiBmcSlaveAddress + gAdvancedFeaturePkgTokenSpaceGuid.PcdIpmiIoBaseAddress \ No newline at end of file diff --git a/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/KcsBmc.c b/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/KcsBmc.c new file mode 100644 index 0000000000..4f766517ec --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/KcsBmc.c @@ -0,0 +1,491 @@ +/** @file + KCS Transport Hook. + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "KcsBmc.h" +#include + +EFI_STATUS +KcsErrorExit ( + UINT64 KcsTimeoutPeriod, + UINT16 KcsPort + ) +/*++ + +Routine Description: + + Check the KCS error status + +Arguments: + + KcsPort - The base port of KCS + +Returns: + + EFI_DEVICE_ERROR - The device error happened + EFI_SUCCESS - Successfully check the KCS error status + +--*/ +{ + EFI_STATUS Status; + UINT8 KcsData; + EFI_KCS_STATUS KcsStatus; + UINT8 BmcStatus; + UINT8 RetryCount; + UINT64 TimeOut; + + TimeOut = 0; + RetryCount = 0; + while (RetryCount < KCS_ABORT_RETRY_COUNT) { + + do { + MicroSecondDelay(KCS_DELAY_UNIT); + KcsStatus.RawData = IoRead8 (KcsPort + 1); + if (KcsStatus.RawData == 0xFF || (TimeOut >= KcsTimeoutPeriod)) { + RetryCount = KCS_ABORT_RETRY_COUNT; + break; + } + TimeOut++; + } while (KcsStatus.Status.Ibf); + + if (RetryCount >= KCS_ABORT_RETRY_COUNT) { + break; + } + + KcsData = KCS_ABORT; + IoWrite8 ((KcsPort + 1), KcsData); + + TimeOut = 0; + do { + MicroSecondDelay(KCS_DELAY_UNIT); + KcsStatus.RawData = IoRead8 (KcsPort + 1); + if (KcsStatus.RawData == 0xFF || (TimeOut >= KcsTimeoutPeriod)) { + Status = EFI_DEVICE_ERROR; + goto LabelError; + } + TimeOut++; + } while (KcsStatus.Status.Ibf); + + KcsData = IoRead8 (KcsPort); + + KcsData = 0x0; + IoWrite8 (KcsPort, KcsData); + + TimeOut = 0; + do { + MicroSecondDelay(KCS_DELAY_UNIT); + KcsStatus.RawData = IoRead8 (KcsPort + 1); + if (KcsStatus.RawData == 0xFF || (TimeOut >= KcsTimeoutPeriod)) { + Status = EFI_DEVICE_ERROR; + goto LabelError; + } + TimeOut++; + } while (KcsStatus.Status.Ibf); + + if (KcsStatus.Status.State == KcsReadState) { + TimeOut = 0; + do { + MicroSecondDelay(KCS_DELAY_UNIT); + KcsStatus.RawData = IoRead8 (KcsPort + 1); + if (KcsStatus.RawData == 0xFF || (TimeOut >= KcsTimeoutPeriod)) { + Status = EFI_DEVICE_ERROR; + goto LabelError; + } + TimeOut++; + } while (!KcsStatus.Status.Obf); + + BmcStatus = IoRead8 (KcsPort); + + KcsData = KCS_READ; + IoWrite8 (KcsPort, KcsData); + + TimeOut = 0; + do { + MicroSecondDelay(KCS_DELAY_UNIT); + KcsStatus.RawData = IoRead8 (KcsPort + 1); + if (KcsStatus.RawData == 0xFF || (TimeOut >= KcsTimeoutPeriod)) { + Status = EFI_DEVICE_ERROR; + goto LabelError; + } + TimeOut++; + } while (KcsStatus.Status.Ibf); + + if (KcsStatus.Status.State == KcsIdleState) { + TimeOut = 0; + do { + MicroSecondDelay(KCS_DELAY_UNIT); + KcsStatus.RawData = IoRead8 (KcsPort + 1); + if (KcsStatus.RawData == 0xFF || (TimeOut >= KcsTimeoutPeriod)) { + Status = EFI_DEVICE_ERROR; + goto LabelError; + } + TimeOut++; + } while (!KcsStatus.Status.Obf); + + KcsData = IoRead8 (KcsPort); + break; + + } else { + RetryCount++; + continue; + } + + } else { + RetryCount++; + continue; + } + } + + if (RetryCount >= KCS_ABORT_RETRY_COUNT) { + Status = EFI_DEVICE_ERROR; + goto LabelError; + } + + return EFI_SUCCESS; + +LabelError: + + return Status; +} + +EFI_STATUS +KcsCheckStatus ( + UINT64 KcsTimeoutPeriod, + UINT16 KcsPort, + KCS_STATE KcsState, + BOOLEAN *Idle + ) +/*++ + +Routine Description: + + Ckeck KCS status + +Arguments: + + KcsPort - The base port of KCS + KcsState - The state of KCS to be checked + Idle - If the KCS is idle + +Returns: + + EFI_SUCCESS - Checked the KCS status successfully + +--*/ +{ + EFI_STATUS Status = 0; + EFI_KCS_STATUS KcsStatus = { 0 }; + UINT8 KcsData = 0; + UINT64 TimeOut = 0; + + if(Idle == NULL ){ + return EFI_INVALID_PARAMETER; + } + + *Idle = FALSE; + + do { + MicroSecondDelay(KCS_DELAY_UNIT); + KcsStatus.RawData = IoRead8 (KcsPort + 1); + if (KcsStatus.RawData == 0xFF || (TimeOut >= KcsTimeoutPeriod)) { + Status = EFI_DEVICE_ERROR; + goto LabelError; + } + TimeOut++; + } while (KcsStatus.Status.Ibf); + + if (KcsState == KcsWriteState) { + KcsData = IoRead8 (KcsPort); + } + + if (KcsStatus.Status.State != KcsState) { + if ((KcsStatus.Status.State == KcsIdleState) && (KcsState == KcsReadState)) { + *Idle = TRUE; + } else { + Status = KcsErrorExit (KcsTimeoutPeriod, KcsPort); + goto LabelError; + } + } + + if (KcsState == KcsReadState) { + TimeOut = 0; + do { + MicroSecondDelay(KCS_DELAY_UNIT); + KcsStatus.RawData = IoRead8 (KcsPort + 1); + if (KcsStatus.RawData == 0xFF || (TimeOut >= KcsTimeoutPeriod)) { + Status = EFI_DEVICE_ERROR; + goto LabelError; + } + TimeOut++; + } while (!KcsStatus.Status.Obf); + } + + if (KcsState == KcsWriteState || Idle) { + KcsData = IoRead8 (KcsPort); + } + + return EFI_SUCCESS; + +LabelError: + + return Status; +} + +EFI_STATUS +SendDataToBmc ( + UINT64 KcsTimeoutPeriod, + UINT16 KcsPort, + UINT8 *Data, + UINT8 DataSize + ) +/*++ + +Routine Description: + + Send data to BMC + +Arguments: + + Data - The data pointer to be sent + DataSize - The data size + +Returns: + + EFI_SUCCESS - Send out the data successfully + +--*/ +{ + EFI_KCS_STATUS KcsStatus; + UINT8 KcsData; + UINT16 KcsIoBase; + EFI_STATUS Status; + UINT8 i; + BOOLEAN Idle; + UINT64 TimeOut = 0; + + DEBUG ((DEBUG_INFO, "SendDataToBmc (%ld, 0x%x) - ", KcsTimeoutPeriod, KcsPort)); + for (i = 0; i < DataSize; i++) { + DEBUG ((DEBUG_INFO, "%02x ", Data[i])); + } + DEBUG ((DEBUG_INFO, "\n")); + + KcsIoBase = KcsPort; + + do { + MicroSecondDelay(KCS_DELAY_UNIT); + KcsStatus.RawData = IoRead8 (KcsIoBase + 1); + if ((KcsStatus.RawData == 0xFF) || (TimeOut >= KcsTimeoutPeriod)) + { + if ((Status = KcsErrorExit (KcsTimeoutPeriod, KcsIoBase)) != EFI_SUCCESS) + { + DEBUG ((DEBUG_INFO, "KcsErrorExit - %r\n", Status)); + return Status; + } + } + TimeOut++; + } while (KcsStatus.Status.Ibf); + + KcsData = KCS_WRITE_START; + IoWrite8 ((KcsIoBase + 1), KcsData); + if ((Status = KcsCheckStatus (KcsTimeoutPeriod, KcsIoBase, KcsWriteState, &Idle)) != EFI_SUCCESS) { + DEBUG ((DEBUG_INFO, "KcsCheckStatus 1 - %r\n", Status)); + return Status; + } + + for (i = 0; i < DataSize; i++) { + if (i == (DataSize - 1)) { + if ((Status = KcsCheckStatus (KcsTimeoutPeriod, KcsIoBase, KcsWriteState, &Idle)) != EFI_SUCCESS) { + DEBUG ((DEBUG_INFO, "KcsCheckStatus 2 - %r\n", Status)); + return Status; + } + + KcsData = KCS_WRITE_END; + IoWrite8 ((KcsIoBase + 1), KcsData); + } + + Status = KcsCheckStatus (KcsTimeoutPeriod, KcsIoBase, KcsWriteState, &Idle); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "KcsCheckStatus 3 - %r\n", Status)); + return Status; + } + + IoWrite8 (KcsIoBase, Data[i]); + } + + return EFI_SUCCESS; +} + +EFI_STATUS +ReceiveBmcData ( + UINT64 KcsTimeoutPeriod, + UINT16 KcsPort, + UINT8 *Data, + UINT8 *DataSize + ) +/*++ + +Routine Description: + + Routine Description: + + Receive data from BMC + +Arguments: + + Data - The buffer pointer + DataSize - The buffer size + +Returns: + + EFI_SUCCESS - Received data successfully + +--*/ +{ + UINT8 KcsData; + UINT16 KcsIoBase; + EFI_STATUS Status; + BOOLEAN Idle; + UINT8 Count; + + Count = 0; + KcsIoBase = KcsPort; + + DEBUG ((DEBUG_INFO, "ReceiveBmcData (%ld, 0x%x)...\n", KcsTimeoutPeriod, KcsPort)); + + while (TRUE) { + + if ((Status = KcsCheckStatus (KcsTimeoutPeriod, KcsIoBase, KcsReadState, &Idle)) != EFI_SUCCESS) { + DEBUG ((DEBUG_INFO, "KcsCheckStatus - %r\n", Status)); + return Status; + } + + if (Idle) { + DEBUG ((DEBUG_INFO, "DataSize - 0x%x\n", Count)); + *DataSize = Count; + break; + } + + if (Count > *DataSize) { + DEBUG ((DEBUG_INFO, "ERROR: Count(0x%x) > *DataSize(0x%x)\n", Count, *DataSize)); + return EFI_DEVICE_ERROR; + } + + Data[Count] = IoRead8 (KcsIoBase); + + Count++; + + KcsData = KCS_READ; + IoWrite8 (KcsIoBase, KcsData); + } + + DEBUG ((DEBUG_INFO, "ReceiveBmcData (%ld, 0x%x) - ", KcsTimeoutPeriod, KcsPort)); + for (Count = 0; Count < *DataSize; Count++) { + DEBUG ((DEBUG_INFO, "%02x ", Data[Count])); + } + DEBUG ((DEBUG_INFO, "\n")); + + return EFI_SUCCESS; +} + +EFI_STATUS +ReceiveBmcDataFromPort ( + UINT64 KcsTimeoutPeriod, + UINT16 KcsPort, + UINT8 *Data, + UINT8 *DataSize + ) +/*++ + +Routine Description: + + Receive data from BMC + +Arguments: + + Data - The buffer pointer to receive data + DataSize - The buffer size + +Returns: + + EFI_SUCCESS - Received the data successfully + +--*/ +{ + EFI_STATUS Status; + UINT16 KcsIoBase; + UINT8 i; + UINT8 MyDataSize; + + MyDataSize = *DataSize; + + KcsIoBase = KcsPort; + + for (i = 0; i < KCS_ABORT_RETRY_COUNT; i++) { + Status = ReceiveBmcData (KcsTimeoutPeriod, KcsIoBase, Data, DataSize); + if (EFI_ERROR (Status)) { + if ((Status = KcsErrorExit (KcsTimeoutPeriod, KcsIoBase)) != EFI_SUCCESS) { + return Status; + } + + *DataSize = MyDataSize; + } else { + return Status; + } + } + + return EFI_DEVICE_ERROR; +} + +EFI_STATUS +SendDataToBmcPort ( + UINT64 KcsTimeoutPeriod, + UINT16 KcsPort, + UINT8 *Data, + UINT8 DataSize + ) +/*++ + +Routine Description: + + Send data to BMC + +Arguments: + + Data - The data pointer to be sent + DataSize - The data size + +Returns: + + EFI_SUCCESS - Send out the data successfully + +--*/ +{ + EFI_STATUS Status; + UINT16 KcsIoBase; + UINT8 i; + + KcsIoBase = KcsPort; + + for (i = 0; i < KCS_ABORT_RETRY_COUNT; i++) { + Status = SendDataToBmc (KcsTimeoutPeriod, KcsIoBase, Data, DataSize); + if (EFI_ERROR (Status)) { + if ((Status = KcsErrorExit (KcsTimeoutPeriod, KcsIoBase)) != EFI_SUCCESS) { + return Status; + } + } else { + return Status; + } + } + + return EFI_DEVICE_ERROR; +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/KcsBmc.h b/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/KcsBmc.h new file mode 100644 index 0000000000..8a7e90a108 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiLibKcs/KcsBmc.h @@ -0,0 +1,214 @@ +/** @file + KCS Transport Hook head file. + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _EFI_KCS_BMC_H +#define _EFI_KCS_BMC_H + +#include +#include +#include + +#define KCS_WRITE_START 0x61 +#define KCS_WRITE_END 0x62 +#define KCS_READ 0x68 +#define KCS_GET_STATUS 0x60 +#define KCS_ABORT 0x60 +#define KCS_DELAY_UNIT 50 // [s] Each KSC IO delay + +#define KCS_ABORT_RETRY_COUNT 1 + +typedef enum { + KcsIdleState, + KcsReadState, + KcsWriteState, + KcsErrorState +} KCS_STATE; + +typedef union { + UINT8 RawData; + struct { + UINT8 Obf : 1; + UINT8 Ibf : 1; + UINT8 SmAtn : 1; + UINT8 CD : 1; + UINT8 Oem1 : 1; + UINT8 Oem2 : 1; + UINT8 State : 2; + } Status; +} EFI_KCS_STATUS; + + +// +//External Fucntion List +// +EFI_STATUS +SendDataToBmcPort ( + UINT64 KcsTimeoutPeriod, + UINT16 KcsPort, + UINT8 *Data, + UINT8 DataSize + ) +/*++ + +Routine Description: + + Send data to BMC + +Arguments: + + Data - The data pointer to be sent + DataSize - The data size + +Returns: + + EFI_SUCCESS - Send out the data successfully + +--*/ +; + +EFI_STATUS +ReceiveBmcDataFromPort ( + UINT64 KcsTimeoutPeriod, + UINT16 KcsPort, + UINT8 *Data, + UINT8 *DataSize + ) +/*++ + +Routine Description: + + Routine Description: + + Receive data from BMC + +Arguments: + + Data - The buffer pointer + DataSize - The buffer size + +Returns: + + EFI_SUCCESS - Received data successfully + +--*/ +; + +// +//Internal Fucntion List +// +EFI_STATUS +KcsErrorExit ( + UINT64 KcsTimeoutPeriod, + UINT16 KcsPort + ) +/*++ + +Routine Description: + + Check the KCS error status + +Arguments: + + KcsPort - The base port of KCS + +Returns: + + EFI_DEVICE_ERROR - The device error happened + EFI_SUCCESS - Successfully check the KCS error status + +--*/ +; + +EFI_STATUS +KcsCheckStatus ( + UINT64 KcsTimeoutPeriod, + UINT16 KcsPort, + KCS_STATE KcsState, + BOOLEAN *Idle + ) +/*++ + +Routine Description: + + Ckeck KCS status + +Arguments: + + KcsPort - The base port of KCS + KcsState - The state of KCS to be checked + Idle - If the KCS is idle + Context - The context for this operation + +Returns: + + EFI_SUCCESS - Checked the KCS status successfully + +--*/ +; + + +EFI_STATUS +SendDataToBmc ( + UINT64 KcsTimeoutPeriod, + UINT16 KcsPort, + UINT8 *Data, + UINT8 DataSize + ) +/*++ + +Routine Description: + + Send data to BMC + +Arguments: + + Data - The data pointer to be sent + DataSize - The data size + +Returns: + + EFI_SUCCESS - Send out the data successfully + +--*/ +; + + +EFI_STATUS +ReceiveBmcData ( + UINT64 KcsTimeoutPeriod, + UINT16 KcsPort, + UINT8 *Data, + UINT8 *DataSize + ) +/*++ + +Routine Description: + + Routine Description: + + Receive data from BMC + +Arguments: + + Data - The buffer pointer + DataSize - The buffer size + +Returns: + + EFI_SUCCESS - Received data successfully + +--*/ +; + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.c b/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.c new file mode 100644 index 0000000000..988e5f24ce --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.c @@ -0,0 +1,45 @@ +/** @file + IPMI platform hook. + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include + +#include +#include +// +// Prototype definitions for IPMI Platform Update Library +// + +EFI_STATUS +EFIAPI +PlatformIpmiIoRangeSet( + UINT16 IpmiIoBase +) +/*++ + + Routine Description: + + This function sets IPMI Io range + + Arguments: + + IpmiIoBase + + Returns: + + Status + +--*/ +{ + return PchLpcGenIoRangeSet((IpmiIoBase & 0xFF0), 0x10, LPC_ESPI_FIRST_SLAVE); +} \ No newline at end of file diff --git a/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf b/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf new file mode 100644 index 0000000000..73427edeea --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Features/Ipmi/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf @@ -0,0 +1,35 @@ +### @file +# Component description file for IPMI platform hook Library. +# +# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +### + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = IpmiPlatformHookLib + FILE_GUID = E886B3EA-AAF3-4804-810C-C8F69897C580 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = IpmiPlatformHookLib + +[sources] + IpmiPlatformHookLib.c + +[Packages] + MdePkg/MdePkg.dec + AdvancedFeaturePkg/AdvancedFeaturePkg.dec + LewisburgPkg/PchRcPkg.dec + +[LibraryClasses] + DebugLib + PchCycleDecodingLib + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Include/Acpi/GlobalNvs.asi b/Platform/Intel/PurleyOpenBoardPkg/Include/Acpi/GlobalNvs.asi new file mode 100644 index 0000000000..fa97877d69 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Include/Acpi/GlobalNvs.asi @@ -0,0 +1,288 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + // + // BIOS parameter BIOS_ACPI_PARAM + // + OperationRegion (PSYS, SystemMemory, 0x30584946, 0x400) // (FIX0 - Patched by ACPI Platform Driver during POST) + Field (PSYS, ByteAcc, NoLock, Preserve) { + // IOAPIC Start + PLAT , 32, // Platform ID + Offset (0x04), // +#if MAX_SOCKET > 4 + AP00 , 1, // PC00 IOAPIC Enable + AP01 , 1, // PC01 IOAPIC Enable + AP02 , 1, // PC02 IOAPIC Enable + AP03 , 1, // PC03 IOAPIC Enable + AP04 , 1, // PC04 IOAPIC Enable + AP05 , 1, // PC05 IOAPIC Enable + AP06 , 1, // PC06 IOAPIC Enable + AP07 , 1, // PC07 IOAPIC Enable + AP08 , 1, // PC08 IOAPIC Enable + AP09 , 1, // PC09 IOAPIC Enable + AP10 , 1, // PC10 IOAPIC Enable + AP11 , 1, // PC11 IOAPIC Enable + AP12 , 1, // PC12 IOAPIC Enable + AP13 , 1, // PC13 IOAPIC Enable + AP14 , 1, // PC14 IOAPIC Enable + AP15 , 1, // PC15 IOAPIC Enable + AP16 , 1, // PC16 IOAPIC Enable + AP17 , 1, // PC17 IOAPIC Enable + AP18 , 1, // PC18 IOAPIC Enable + AP19 , 1, // PC19 IOAPIC Enable + AP20 , 1, // PC20 IOAPIC Enable + AP21 , 1, // PC21 IOAPIC Enable + AP22 , 1, // PC22 IOAPIC Enable + AP23 , 1, // PC23 IOAPIC Enable + AP24 , 1, // PC24 IOAPIC Enable + AP25 , 1, // 8S PC25 IOAPIC Enable + AP26 , 1, // 8S PC26 IOAPIC Enable + AP27 , 1, // 8S PC27 IOAPIC Enable + AP28 , 1, // 8S PC28 IOAPIC Enable + AP29 , 1, // 8S PC29 IOAPIC Enable + AP30 , 1, // 8S PC30 IOAPIC Enable + AP31 , 1, // 8S PC31 IOAPIC Enable +#else + APC0 , 1, // PCH IOAPIC Enable + AP00 , 1, // PC00 IOAPIC Enable + AP01 , 1, // PC01 IOAPIC Enable + AP02 , 1, // PC02 IOAPIC Enable + AP03 , 1, // PC03 IOAPIC Enable + AP04 , 1, // PC04 IOAPIC Enable + AP05 , 1, // PC05 IOAPIC Enable + AP06 , 1, // PC06 IOAPIC Enable + AP07 , 1, // PC07 IOAPIC Enable + AP08 , 1, // PC08 IOAPIC Enable + AP09 , 1, // PC09 IOAPIC Enable + AP10 , 1, // PC10 IOAPIC Enable + AP11 , 1, // PC11 IOAPIC Enable + AP12 , 1, // PC12 IOAPIC Enable + AP13 , 1, // PC13 IOAPIC Enable + AP14 , 1, // PC14 IOAPIC Enable + AP15 , 1, // PC15 IOAPIC Enable + AP16 , 1, // PC16 IOAPIC Enable + AP17 , 1, // PC17 IOAPIC Enable + AP18 , 1, // PC18 IOAPIC Enable + AP19 , 1, // PC19 IOAPIC Enable + AP20 , 1, // PC20 IOAPIC Enable + AP21 , 1, // PC21 IOAPIC Enable + AP22 , 1, // PC22 IOAPIC Enable + AP23 , 1, // PC23 IOAPIC Enable + RESA , 7, // Unused +#endif + Offset (0x08), + SKOV , 1, // Override ApicId socket field + , 7, // Unused + // IOAPIC End + + // Power Managment Start + Offset (0x09), + , 1, // + CSEN , 1, // C State Enable + C3EN , 1, // OS C3 Report Enbale + C6EN , 1, // C6 Enable + C7EN , 1, // C7 Enable + MWOS , 1, // MWAIT support Enable + PSEN , 1, // P State Enable + EMCA , 1, // EMCA Enable + Offset (0x0A), + HWAL , 2, // PSD HW_ALL Enable + KPRS , 1, // KB present Flag + MPRS , 1, // Mouse present Flag + TSEN , 1, // T State Enable Flag + FGTS , 1, // Fine grained T state Flag + OSCX , 1, // OS C States + RESX , 1, // Unused + // Power Management End + + // RAS Start + Offset (0x0B), + CPHP , 8, // Bit field for determining CPU hotplug event is happening, Update every time CPU Hotpug event is registered as valid + // Bit0 CPU0 O*L Request + // Bit1 CPU1 O*L Request + // Bit2 CPU2 O*L Request + // Bit3 CPU3 O*L Request + // Bit4-7 Reserved + IIOP , 8, // Bit field for determining IIO hotplug event is happening, Update every time IIO Hotpug event is registered as valid + // Bit0 IIO1 O*L Request + // Bit1 IIO2 O*L Request + // Bit2 IIO3 O*L Request + // Bit3-7 Reserved + IIOH , 64, // IIO bit Mask, what IIOs are present for STA method, Update every time IIO hotplug event happens and at boot time (Patched by ACPI Platform Driver during POST) + PRBM , 32, // Processor Bit mask, what sockets are present for STA method, Update every time hotplug event happen and at boot time (Patched by ACPI Platform Driver during POST) + P0ID , 32, // Processor 0 APIC ID base + P1ID , 32, // Processor 1 APIC ID base + P2ID , 32, // Processor 2 APIC ID base + P3ID , 32, // Processor 3 APIC ID base + P4ID , 32, // Processor 4 APIC ID base + P5ID , 32, // Processor 5 APIC ID base + P6ID , 32, // Processor 6 APIC ID base + P7ID , 32, // Processor 7 APIC ID base + P0BM , 64, // Processor 0 Bit mask, what cores are present for STA method + P1BM , 64, // Processor 1 Bit mask, what cores are present for STA method + P2BM , 64, // Processor 2 Bit mask, what cores are present for STA method + P3BM , 64, // Processor 3 Bit mask, what cores are present for STA method + P4BM , 64, // Processor 4 Bit mask, what cores are present for STA method + P5BM , 64, // Processor 5 Bit mask, what cores are present for STA method + P6BM , 64, // Processor 6 Bit mask, what cores are present for STA method + P7BM , 64, // Processor 7 Bit mask, what cores are present for STA method + MEBM , 16, // Memory controller bit mask what memory controllers are present, for STA Method + MEBC , 16, // Memory controller change event mask what memory controllers have been changed, for notify + CFMM , 32, // MMCFG Base + TSSZ , 32, // TSEG Size. + M0BS , 64, // Memory Controller Base 0 + M1BS , 64, // Memory Controller Base 1 + M2BS , 64, // Memory Controller Base 2 + M3BS , 64, // Memory Controller Base 3 + M4BS , 64, // Memory Controller Base 4 + M5BS , 64, // Memory Controller Base 5 + M6BS , 64, // Memory Controller Base 6 + M7BS , 64, // Memory Controller Base 7 + M0RN , 64, // Memory Controller Range 0 + M1RN , 64, // Memory Controller Range 1 + M2RN , 64, // Memory Controller Range 2 + M3RN , 64, // Memory Controller Range 3 + M4RN , 64, // Memory Controller Range 4 + M5RN , 64, // Memory Controller Range 5 + M6RN , 64, // Memory Controller Range 6 + M7RN , 64, // Memory Controller Range 7 + SMI0 , 32, // Parameter0 used for faked SMI request + SMI1 , 32, // Parameter1 used for faked SMI request + SMI2 , 32, // Parameter2 used for faked SMI request + SMI3 , 32, // Parameter3 used for faked SMI request + SCI0 , 32, // Parameter0 used for faked SCI request + SCI1 , 32, // Parameter1 used for faked SCI request + SCI2 , 32, // Parameter2 used for faked SCI request + SCI3 , 32, // Parameter3 used for faked SCI request + MADD , 64, // Migration ActionRegion GAS address. (Migration support written for 8 CPU socket system. In a 4 socket system, CPU4-7 and MEM8-15 are invalid.) + CUU0 , 128, // CPU0 UUID + CUU1 , 128, // CPU1 UUID + CUU2 , 128, // CPU2 UUID + CUU3 , 128, // CPU3 UUID + CUU4 , 128, // CPU4 UUID + CUU5 , 128, // CPU5 UUID + CUU6 , 128, // CPU6 UUID + CUU7 , 128, // CPU7 UUID + CPSP , 8, // CPU spare bitmap. 1 == IsSpare. + ME00 , 128, // MEM0 UUID + ME01 , 128, // MEM1 UUID + ME10 , 128, // MEM2 UUID + ME11 , 128, // MEM3 UUID + ME20 , 128, // MEM4 UUID + ME21 , 128, // MEM5 UUID + ME30 , 128, // MEM6 UUID + ME31 , 128, // MEM7 UUID + ME40 , 128, // MEM8 UUID + ME41 , 128, // MEM9 UUID + ME50 , 128, // MEM10 UUID + ME51 , 128, // MEM11 UUID + ME60 , 128, // MEM12 UUID + ME61 , 128, // MEM13 UUID + ME70 , 128, // MEM14 UUID + ME71 , 128, // MEM15 UUID + MESP , 16, // Memory module spare bitmap. 1 == IsSpare. + LDIR , 64, // L1 Directory Address + PRID , 32, // Processor ID + AHPE , 8, // ACPI PCIe hot plug enable. + // RAS End + + // VTD Start + DHRD , 192, // DHRD + ATSR , 192, // ATSR + RHSA , 192, // RHSA + // VTD End + + // BIOS Guard Start + CNBS , 8, // CPU SKU number bit shift + // BIOS Guard End + + // USB3 Start + XHMD , 8, // copy of setup item PchUsb30Mode + SBV1 , 8, // USB Sideband Deferring GPE Vector (HOST_ALERT#1) + SBV2 , 8, // USB Sideband Deferring GPE Vector (HOST_ALERT#2) + // USB3 End + + // HWPM Start + , 2, // HWPM State Enable option from setup + , 1, // Aunomous C-state Enable option from setup + HWPI , 1, // HWP Interrupt + , 4, // Reserved bits + // HWPM End + + // PCIe Multi-Seg Start + BB00 , 8, // Bus Base for PC00 + BB01 , 8, // Bus Base for PC01 + BB02 , 8, // Bus Base for PC02 + BB03 , 8, // Bus Base for PC03 + BB04 , 8, // Bus Base for PC04 + BB05 , 8, // Bus Base for PC05 + BB06 , 8, // Bus Base for PC06 + BB07 , 8, // Bus Base for PC07 + BB08 , 8, // Bus Base for PC08 + BB09 , 8, // Bus Base for PC09 + BB10 , 8, // Bus Base for PC10 + BB11 , 8, // Bus Base for PC11 + BB12 , 8, // Bus Base for PC12 + BB13 , 8, // Bus Base for PC13 + BB14 , 8, // Bus Base for PC14 + BB15 , 8, // Bus Base for PC15 + BB16 , 8, // Bus Base for PC16 + BB17 , 8, // Bus Base for PC17 + BB18 , 8, // Bus Base for PC18 + BB19 , 8, // Bus Base for PC19 + BB20 , 8, // Bus Base for PC20 + BB21 , 8, // Bus Base for PC21 + BB22 , 8, // Bus Base for PC22 + BB23 , 8, // Bus Base for PC23 + BB24 , 8, // Bus Base for PC24 + BB25 , 8, // Bus Base for PC25 + BB26 , 8, // Bus Base for PC26 + BB27 , 8, // Bus Base for PC27 + BB28 , 8, // Bus Base for PC28 + BB29 , 8, // Bus Base for PC29 + BB30 , 8, // Bus Base for PC30 + BB31 , 8, // Bus Base for PC31 + BB32 , 8, // Bus Base for PC32 + BB33 , 8, // Bus Base for PC33 + BB34 , 8, // Bus Base for PC34 + BB35 , 8, // Bus Base for PC35 + BB36 , 8, // Bus Base for PC36 + BB37 , 8, // Bus Base for PC37 + BB38 , 8, // Bus Base for PC38 + BB39 , 8, // Bus Base for PC39 + BB40 , 8, // Bus Base for PC40 + BB41 , 8, // Bus Base for PC41 + BB42 , 8, // Bus Base for PC42 + BB43 , 8, // Bus Base for PC43 + BB44 , 8, // Bus Base for PC44 + BB45 , 8, // Bus Base for PC45 + BB46 , 8, // Bus Base for PC46 + BB47 , 8, // Bus Base for PC47 + SGEN , 8, // PCIe_MultiSeg_Support enable/disable + SG00 , 8, // Segment ID for Segment Group 0 + SG01 , 8, // Segment ID for Segment Group 1 + SG02 , 8, // Segment ID for Segment Group 2 + SG03 , 8, // Segment ID for Segment Group 3 + SG04 , 8, // Segment ID for Segment Group 4 + SG05 , 8, // Segment ID for Segment Group 5 + SG06 , 8, // Segment ID for Segment Group 6 + SG07 , 8, // Segment ID for Segment Group 7 + // PCIe Multi-Seg End + + // Performance start + CLOD , 8, // SncAnd2Cluster, i.e. 1=SNC enable and 2 Clusters, 0 otherwise + // Performance End + + } + + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.h b/Platform/Intel/PurleyOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.h new file mode 100644 index 0000000000..65dbf7cebb --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.h @@ -0,0 +1,134 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _EFI_GLOBAL_NVS_AREA_H_ +#define _EFI_GLOBAL_NVS_AREA_H_ + +// +// Global NVS Area definition +// +#pragma pack (1) + +typedef struct { + // IOAPIC Start + UINT32 PlatformId; + UINT32 IoApicEnable; + UINT8 ApicIdOverrided :1; + UINT8 RES0 :7; + // IOAPIC End + + // Power Management Start + UINT8 Rsvd_Pms_0 :1; + UINT8 CStateEnable :1; + UINT8 C3Enable :1; + UINT8 C6Enable :1; + UINT8 C7Enable :1; + UINT8 MonitorMwaitEnable :1; + UINT8 PStateEnable :1; + UINT8 EmcaEn :1; + UINT8 HWAllEnable :2; + UINT8 KBPresent :1; + UINT8 MousePresent :1; + UINT8 TStateEnable :1; + UINT8 TStateFineGrained: 1; + UINT8 OSCX :1; + UINT8 RESX :1; + // Power Management End + + // RAS Start + UINT8 CpuChangeMask; + UINT8 IioChangeMask; + UINT64 IioPresentBitMask; + UINT32 SocketBitMask; //make sure this is at 4byte boundary + UINT32 ProcessorApicIdBase[8]; + UINT64 ProcessorBitMask[8]; + UINT16 MemoryBoardBitMask; + UINT16 MemoryBoardChgEvent; + UINT32 MmCfg; + UINT32 TsegSize; + UINT64 MemoryBoardBase[8]; + UINT64 MemoryBoardRange[8]; + UINT32 SmiRequestParam[4]; + UINT32 SciRequestParam[4]; + UINT64 MigrationActionRegionAddress; + UINT8 Cpu0Uuid[16]; + UINT8 Cpu1Uuid[16]; + UINT8 Cpu2Uuid[16]; + UINT8 Cpu3Uuid[16]; + UINT8 Cpu4Uuid[16]; + UINT8 Cpu5Uuid[16]; + UINT8 Cpu6Uuid[16]; + UINT8 Cpu7Uuid[16]; + UINT8 CpuSpareMask; + UINT8 Mem0Uuid[16]; + UINT8 Mem1Uuid[16]; + UINT8 Mem2Uuid[16]; + UINT8 Mem3Uuid[16]; + UINT8 Mem4Uuid[16]; + UINT8 Mem5Uuid[16]; + UINT8 Mem6Uuid[16]; + UINT8 Mem7Uuid[16]; + UINT8 Mem8Uuid[16]; + UINT8 Mem9Uuid[16]; + UINT8 Mem10Uuid[16]; + UINT8 Mem11Uuid[16]; + UINT8 Mem12Uuid[16]; + UINT8 Mem13Uuid[16]; + UINT8 Mem14Uuid[16]; + UINT8 Mem15Uuid[16]; + UINT16 MemSpareMask; + UINT64 EmcaL1DirAddr; + UINT32 ProcessorId; + UINT8 PcieAcpiHotPlugEnable; + // RAS End + + // VTD Start + UINT64 DrhdAddr[3]; + UINT64 AtsrAddr[3]; + UINT64 RhsaAddr[3]; + // VTD End + + // BIOS Guard Start + UINT8 CpuSkuNumOfBitShift; + // BIOS Guard End + + // USB3 Start + UINT8 XhciMode; + UINT8 HostAlertVector1; + UINT8 HostAlertVector2; + // USB3 End + + // HWPM Start + UINT8 HWPMEnable:2; //HWPM + UINT8 AutoCstate:1; //HWPM + UINT8 HwpInterrupt:1; //HWP Interrupt + UINT8 RES1:4; //reserved bits + // HWPM End + + // PCIe Multi-Seg Start + // for 8S support needs max 32 IIO IOxAPIC being enabled! + UINT8 BusBase[48]; // MAX_SOCKET * MAX_IIO_STACK. Note: hardcode due to ASL constraint. + UINT8 PCIe_MultiSeg_Support; // Enable /Disable switch + // for 8S support needs matching to MAX_SOCKET! + UINT8 PcieSegNum[8]; // Segment number array. Must match MAX_SOCKET. Note: hardcode due to ASL constraint. + // PCIe Multi-seg end + + // Performance Start + UINT8 SncAnd2Cluster; //1=SncEn and NumCluster=2, otherwise 0 + // Performance End + + } BIOS_ACPI_PARAM; + +#pragma pack () + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Include/Guid/PchRcVariable.h b/Platform/Intel/PurleyOpenBoardPkg/Include/Guid/PchRcVariable.h new file mode 100644 index 0000000000..fd0b553337 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Include/Guid/PchRcVariable.h @@ -0,0 +1,420 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __PCH_RC_CONFIG_DATA_H__ +#define __PCH_RC_CONFIG_DATA_H__ + +#include +#define HDAUDIO_FEATURES 3 +#define HDAUDIO_PP_MODULES 2 + + +/// sSATA max ports for Wellsburg +#define PCH_SSATA_MAX_PORTS 6 + +#pragma pack(1) +typedef struct { + + UINT8 BiosGuard; + UINT8 Dwr_Enable; + UINT8 Dwr_Stall; + UINT8 Dwr_BmcRootPort; + + UINT8 DwrEn_PMCGBL; + UINT8 DwrEn_CPUTHRM; + UINT8 DwrEn_PCHTHRM; + UINT8 DwrEn_PBO; + UINT8 DwrEn_MEPBO; + UINT8 DwrEn_MEWDT; + UINT8 DwrEn_MEGBL; + UINT8 DwrEn_CTWDT; + UINT8 DwrEn_PMCWDT; + UINT8 DwrEn_ME_UERR; + UINT8 DwrEn_SYSPWR; + UINT8 DwrEn_OCWDT; + UINT8 DwrEn_IEPBO; + UINT8 DwrEn_IEWDT; + UINT8 DwrEn_IEGBLN; + UINT8 DwrEn_IE_UERRN; + UINT8 DwrEn_ACRU_ERR_2H_EN; + + UINT8 DwrPmcEn_HOST_RESET_TIMEOUT; + UINT8 DwrPmcEn_SX_ENTRY_TIMEOUT; + UINT8 DwrPmcEn_HOST_RST_PROM; + UINT8 DwrPmcEn_HSMB_MSG; + UINT8 DwrPmcEn_IE_MTP_TIMEOUT; + UINT8 DwrPmcEn_MTP_TIMEOUT; + UINT8 DwrPmcEn_ESPI_ERROR_DETECT; + + UINT8 Dwr_MeResetPrepDone; + UINT8 Dwr_IeResetPrepDone; + + // + // PCH_DEVICE_ENABLES + // + UINT8 BoardCapability; + UINT8 DeepSxMode; + UINT8 Gp27WakeFromDeepSx; + UINT8 GbeRegionInvalid; + UINT8 LomLanSupported; + UINT8 PchWakeOnLan; + UINT8 PchSlpLanLowDc; + UINT8 PchSmbus; + UINT8 PchPciClockRun; + UINT8 PchDisplay; + UINT8 PchCrid; + UINT8 PchRtcLock; + UINT8 PchBiosLock; + UINT8 PchAllUnLock; + UINT8 PchThermalUnlock; + UINT8 PchSerm; + UINT8 PchGbeFlashLockDown; + UINT8 PchSmmBwp; + + UINT8 Hpet; + UINT8 PchPort80Route; + UINT8 EnableClockSpreadSpec; + UINT8 IchPort80Route; + UINT8 PchSirqMode; + + // + // Usb Config + // + UINT8 PchUsbManualMode; + UINT8 PchGpioLockDown; + UINT8 RouteUsb2PinsToWhichHc; + UINT8 RouteUsb2Pin0; + UINT8 RouteUsb2Pin1; + UINT8 RouteUsb2Pin2; + UINT8 RouteUsb2Pin3; + UINT8 RouteUsb2Pin4; + UINT8 RouteUsb2Pin5; + UINT8 RouteUsb2Pin6; + UINT8 RouteUsb2Pin7; + UINT8 RouteUsb2Pin8; + UINT8 RouteUsb2Pin9; + UINT8 RouteUsb2Pin10; + UINT8 RouteUsb2Pin11; + UINT8 RouteUsb2Pin12; + UINT8 RouteUsb2Pin13; + UINT8 Usb3PinsTermination; + UINT8 EnableUsb3Pin[10]; + UINT8 PchUsbHsPort[16]; + UINT8 PchUsbSsPort[10]; + UINT8 PchUsbPortDisable; + UINT8 UsbSensorHub; + UINT8 UsbSsicSupport[2]; + UINT8 XhciDisMSICapability; + UINT8 PchUsbPerPortCtl; + UINT8 PchUsb30Port[6]; + UINT8 UsbPrecondition; + UINT8 XhciIdleL1; + UINT8 Btcg; + UINT8 PchUsbDegradeBar; + // + // XHCI OC Map + // + UINT8 XhciOcMapEnabled; + // + // xDCI Config + // + UINT8 PchXdciSupport; + // + // Sata CONFIG + // + UINT8 PchSata; + // + // Sata Interface Mode + // 0 - IDE 1 - RAID 2 - AHCI + // + UINT8 SataInterfaceMode; + UINT8 SataPort[PCH_MAX_SATA_PORTS]; + UINT8 SataHotPlug[PCH_MAX_SATA_PORTS]; + UINT8 SataMechanicalSw[PCH_MAX_SATA_PORTS]; + UINT8 SataSpinUp[PCH_MAX_SATA_PORTS]; + UINT8 SataExternal[PCH_MAX_SATA_PORTS]; + UINT8 SataType[PCH_MAX_SATA_PORTS]; + UINT8 SataRaidR0; + UINT8 SataRaidR1; + UINT8 SataRaidR10; + UINT8 SataRaidR5; + UINT8 SataRaidIrrt; + UINT8 SataRaidOub; + UINT8 SataHddlk; + UINT8 SataLedl; + UINT8 SataRaidIooe; + UINT8 SataRaidSrt; + UINT8 SataRaidLoadEfiDriver; + UINT8 SataRaidOromDelay; + UINT8 SataAlternateId; + UINT8 SataSalp; + UINT8 SataTestMode; + UINT8 PxDevSlp[PCH_MAX_SATA_PORTS]; + UINT8 EnableDitoConfig[PCH_MAX_SATA_PORTS]; + UINT16 DitoVal[PCH_MAX_SATA_PORTS]; + UINT8 DmVal[PCH_MAX_SATA_PORTS]; + UINT8 SataTopology[PCH_MAX_SATA_PORTS]; + + // + // sSata CONFIG + // + UINT8 PchsSata; + // + // Sata Interface Mode + // 0 - IDE 1 - RAID 2 - AHCI + // + UINT8 sSataInterfaceMode; + UINT8 sSataPort[PCH_SSATA_MAX_PORTS]; + UINT8 sSataHotPlug[PCH_SSATA_MAX_PORTS]; + UINT8 sSataSpinUp[PCH_SSATA_MAX_PORTS]; + UINT8 sSataExternal[PCH_SSATA_MAX_PORTS]; + UINT8 sPxDevSlp[PCH_SSATA_MAX_PORTS]; + UINT8 sSataType[PCH_SSATA_MAX_PORTS]; + UINT8 sSataRaidR0; + UINT8 sSataRaidR1; + UINT8 sSataRaidR10; + UINT8 sSataRaidR5; + UINT8 sSataRaidIrrt; + UINT8 sSataRaidOub; + UINT8 sSataHddlk; + UINT8 sSataLedl; + UINT8 sSataRaidIooe; + UINT8 sSataRaidSrt; + UINT8 sSataRaidLoadEfiDriver; + UINT8 sSataRaidOromDelay; + UINT8 sSataAlternateId; + UINT8 sSataSalp; + UINT8 sSataTestMode; + UINT8 sEnableDitoConfig[PCH_SSATA_MAX_PORTS]; + UINT8 sDmVal[PCH_SSATA_MAX_PORTS]; + UINT8 sDitoVal[PCH_SSATA_MAX_PORTS]; + UINT8 sSataTopology[PCH_SSATA_MAX_PORTS]; + + + + + //PCH THERMAL SENSOR + UINT8 ThermalDeviceEnable; + UINT8 PchCrossThrottling; + + UINT8 PchDmiExtSync; + UINT8 PcieDmiExtSync; + // AcpiDebug Setup Options + UINT8 PciDelayOptimizationEcr; + UINT8 PchPcieGlobalAspm; + + UINT8 PcieDmiStopAndScreamEnable; + UINT8 DmiLinkDownHangBypass; + UINT8 XTpmLen; + UINT8 PcieRootPort8xhDecode; + UINT8 Pcie8xhDecodePortIndex; + UINT8 PcieRootPortPeerMemoryWriteEnable; + UINT8 PcieComplianceTestMode; + + + UINT8 PcieRootPortSBDE; + UINT8 PcieSBDEPort; + + UINT8 RstPcieStorageRemap[PCH_MAX_RST_PCIE_STORAGE_CR]; + UINT8 RstPcieStorageRemapPort[PCH_MAX_RST_PCIE_STORAGE_CR]; + UINT8 PcieRootPortFunctionSwapping; + UINT8 PcieRootPortEn[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortAspm[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortURE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortFEE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortNFE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortCEE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortMSIE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortMaxPayLoadSize[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortAER[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieTopology[PCH_MAX_PCIE_ROOT_PORTS]; + + UINT8 PcieLaneCm[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieLaneCp[PCH_MAX_PCIE_ROOT_PORTS]; + + UINT8 PcieSwEqOverride; + UINT8 PcieSwEqCoeffCm[PCH_PCIE_SWEQ_COEFFS_MAX]; + UINT8 PcieSwEqCoeffCp[PCH_PCIE_SWEQ_COEFFS_MAX]; + UINT8 PchPcieUX8MaxPayloadSize; + UINT8 PchPcieUX16MaxPayloadSize; + UINT8 PcieRootPortCompletionTimeout[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieClockGatingDisabled; + UINT8 PcieUsbGlitchWa; + UINT8 PcieRootPortPIE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortACS[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortEqPh3Method[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortMaxReadRequestSize; + UINT8 PcieRootPortSFE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortSNE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortSCE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortPMCE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortHPE[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortSpeed[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PcieRootPortTHS[PCH_MAX_PCIE_ROOT_PORTS]; + + // + // PCI Bridge Resources + // + UINT8 PcieRootPortL1SubStates[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 MemoryThermalManagement; + UINT8 ExttsViaTsOnBoard; + UINT8 ExttsViaTsOnDimm; + UINT8 FixupPlatformSpecificSoftstraps; + + // + // SMBUS Configuration + // + UINT8 TestSmbusSpdWriteDisable; + + + // + // HD-Audio Configuration + // + UINT8 PchHdAudio; + UINT8 PchHdAudioDsp; + UINT8 PchHdAudioPme; + UINT8 PchHdAudioIoBufferOwnership; + UINT8 PchHdAudioIoBufferVoltage; + UINT8 PchHdAudioCodecSelect; + UINT8 PchHdAudioFeature[HDAUDIO_FEATURES]; + UINT8 PchHdAudioPostProcessingMod[HDAUDIO_PP_MODULES]; + + UINT8 RtoHdaVcType; + // + // DMI Configuration + // + UINT8 TestDmiAspmCtrl; + + + // + // + // PCIe LTR Configuration + // + UINT8 PchPcieLtrEnable[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PchPcieLtrConfigLock[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PchPcieSnoopLatencyOverrideMode[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PchPcieSnoopLatencyOverrideMultiplier[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PchPcieNonSnoopLatencyOverrideMode[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PchPcieNonSnoopLatencyOverrideMultiplier[PCH_MAX_PCIE_ROOT_PORTS]; + UINT16 PchPcieSnoopLatencyOverrideValue[PCH_MAX_PCIE_ROOT_PORTS]; + UINT16 PchPcieNonSnoopLatencyOverrideValue[PCH_MAX_PCIE_ROOT_PORTS]; + + UINT8 PchPcieForceLtrOverride[PCH_MAX_PCIE_ROOT_PORTS]; + UINT8 PchSataLtrOverride; + UINT8 PchSataLtrEnable; + UINT16 PchSataSnoopLatencyOverrideValue; + UINT8 PchSataSnoopLatencyOverrideMultiplier; + UINT8 PchSataLtrConfigLock; + + UINT8 PchSSataLtrOverride; + UINT16 PchSSataSnoopLatencyOverrideValue; + UINT8 PchSSataSnoopLatencyOverrideMultiplier; + UINT8 PchSSataLtrEnable; + UINT8 PchSSataLtrConfigLock; + + UINT8 PchPcieUX16CompletionTimeout; + UINT8 PchPcieUX8CompletionTimeout; + + // + // Interrupt Configuration + // + UINT8 PchIoApic24119Entries; + + // + // DPTF SETUP items begin + // + UINT8 EnableDptf; + UINT8 EnablePchDevice; + + // + // CPU + // + UINT8 DebugDciEnable; + UINT8 DebugInterfaceEnable; + + // + // Miscellaneous options + // + UINT8 OsDebugPort; + UINT8 SlpLanLowDc; + UINT8 PchLanK1Off; + UINT8 PchWakeOnWlan; + UINT8 PchWakeOnWlanDeepSx; + UINT8 StateAfterG3; + UINT8 PciePllSsc; + UINT8 FirmwareConfiguration; + UINT8 PchDciEn; + UINT8 PchDciAutoDetect; + + // Acpi.sd + UINT8 CSNotifyEC; + UINT8 EcLowPowerMode; + + // + // TraceHub Setup Options + // + UINT8 TraceHubEnableMode; + UINT8 MemRegion0BufferSize; + UINT8 MemRegion1BufferSize; + + // + // PCH P2SB hide and lock options + // + UINT8 PchP2sbDevReveal; + UINT8 PchP2sbUnlock; + + // + // PCH SPI hide and lock options + // + UINT8 FlashLockDown; + + // + // PCH PMC option + // + UINT8 PmcReadDisable; + + + // + // ADR Configuration + // + UINT8 PchAdrEn; + UINT8 AdrTimerEn; + UINT8 AdrTimerVal; + UINT8 AdrMultiplierVal; + UINT8 AdrGpioSel; + UINT8 AdrHostPartitionReset; + + // + // Audio DSP Configuration + // + UINT8 PchAudioDsp; + UINT8 PchAudioDspD3PowerGating; + UINT8 PchAudioDspAcpiMode; + UINT8 PchAudioDspBluetooth; + UINT8 PchAudioDspAcpiInterruptMode; + + // + // Miscellaneous options + // + + UINT8 PchEvaMrom0HookEnable; + UINT8 PchEvaMrom1HookEnable; + UINT8 TestMctpBroadcastCycle; + UINT8 PchEvaLockDown; + UINT8 PchTraceHubHide; +} PCH_RC_CONFIGURATION; +#pragma pack() + +#endif + + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Include/Guid/SetupVariable.h b/Platform/Intel/PurleyOpenBoardPkg/Include/Guid/SetupVariable.h new file mode 100644 index 0000000000..3d6267fac1 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Include/Guid/SetupVariable.h @@ -0,0 +1,545 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __SETUP_VARIABLE_H__ +#define __SETUP_VARIABLE_H__ + +#include "UncoreCommonIncludes.h" +// --------------------------------------------------------------------------- +// +// Driver Configuration +// +// --------------------------------------------------------------------------- +// + +#define MAX_PCH_PCI_EXPRESS_ROOT_PORTS 8 +#define PASSWORD_MAX_SIZE 16 +#define SHA256_DIGEST_LENGTH 32 +#define EFI_VARIABLE_BOOTSERVICE_ACCESS 0x00000002 + +#pragma pack(1) + +typedef struct { + + UINT8 UserPassword[SHA256_DIGEST_LENGTH]; + UINT8 AdminPassword[SHA256_DIGEST_LENGTH]; + UINT8 Access; + + // + // Keyboard + // + UINT8 Numlock; + UINT8 Ps2PortSwap; + + // + // TPM + // + UINT8 TpmEnable; + UINT8 TpmState; + UINT8 MorState; + + // + // Breakpoints + // + UINT8 ValidationBreakpointType; + UINT16 bsdBreakpoint; + + // + // Power State + // + UINT8 PowerState; + + // + // Wake On Lan + // + UINT8 WakeOnLanS5; + + // + // Boot from Network + // + UINT8 BootNetwork; + + // + // Video + // + UINT8 VideoSelect; + UINT8 EfiWindowsInt10Workaround; + UINT8 UefiOptimizedBootToggle; + + // + // Fan PWM Offset + // + UINT8 FanPwmOffset; + + // + // PCI Minimum Secondary Bus Number + // + UINT8 PCIe_MultiSeg_Support; + + // + UINT8 WakeOnLanSupport; + // + // Enable/disable for PCIe LOM by using GPO44/45 + // NOT PCH LAN + // + UINT8 LomDisableByGpio; + + UINT8 FpkPortConfig[4]; + UINT8 FpkPortConfigPrev[4]; + UINT8 FpkPortPresent[4]; + + // RTC WAKE + // + UINT8 WakeOnRTCS4S5; + UINT8 RTCWakeupTimeHour; + UINT8 RTCWakeupTimeMinute; + UINT8 RTCWakeupTimeSecond; + // PCI_EXPRESS_CONFIG, ROOT PORTS + // + // AJW: these cross the line, but depend on Platform Info + UINT8 PcieClockGating; + UINT8 PcieDmiAspm; + UINT8 PcieSBDE; + UINT8 GbePciePortNum; + UINT8 PciePortConfig1; + UINT8 PciePortConfig2; + UINT8 PciePortConfig3; + UINT8 PciePortConfig4; + UINT8 PciePortConfig5; + + // GBE + UINT8 GbeEnabled; + + // PCH Stepping + UINT8 PchStepping; + + // + // XHCI Wake On USB + // + UINT8 XhciWakeOnUsbEnabled; + + // + // EventLog + // +// +// SKX_TODO: add these for RAS, may be best to find new home for them in a new setup variable and setup page +// + UINT8 SystemErrorEn; + //Viral, and IoMca are not supported in EP. Will need to wrap in an EX flag + //UINT8 ViralEn; + UINT8 PoisonEn; + UINT8 ViralEn; + UINT8 ClearViralStatus; + UINT8 CloakingEn; + UINT8 UboxToPcuMcaEn; + UINT8 FatalErrSpinLoopEn; + + UINT8 EmcaEn; + UINT8 EmcaIgnOptin; + UINT8 EmcaCsmiEn; + UINT8 EmcaMsmiEn; + UINT8 ElogCorrErrEn; + UINT8 ElogMemErrEn; + UINT8 ElogProcErrEn; + UINT8 LmceEn; + + UINT8 WheaSupportEn; + UINT8 WheaLogMemoryEn; + UINT8 WheaLogProcEn; + + UINT8 WheaLogPciEn; + + UINT8 WheaErrorInjSupportEn; + UINT8 McaBankErrInjEn; + UINT8 WheaErrInjEn; + UINT8 WheaPcieErrInjEn; + UINT8 MeSegErrorInjEn; + UINT8 PcieErrInjActionTable; + UINT8 ParityCheckEn; + + UINT8 MemErrEn; + UINT8 CorrMemErrEn; + UINT32 LeakyBktHiLeakyBktLo; + UINT8 SpareIntSelect; + UINT8 FnvErrorEn; + UINT8 FnvErrorLowPrioritySignal; // 0 - No Log, 1 - SMI, 2 - ERR0#, 3 - BOTH + UINT8 FnvErrorHighPrioritySignal; // 0 - No Log, 1 - SMI, 2 - ERR0#, 3 - BOTH + UINT8 Reserved_1; + UINT8 Reserved_2; + UINT8 Reserved_3; + + UINT8 IioErrorEn; + UINT8 IoMcaEn; + UINT8 IioErrRegistersClearEn; + UINT8 IioErrorPinEn; + UINT8 LerEn; + UINT8 DisableMAerrorLoggingDueToLER; + UINT8 IioIrpErrorEn; + UINT8 IioMiscErrorEn; + UINT8 IioVtdErrorEn; + UINT8 IioDmaErrorEn; + UINT8 IioDmiErrorEn; + UINT8 IioPcieAddCorrErrorEn; + UINT8 IioPcieAddUnCorrEn; + UINT8 IioPcieAerSpecCompEn; + + UINT8 PcieErrEn; + UINT8 PcieCorrErrEn; + UINT8 PcieUncorrErrEn; + UINT8 PcieFatalErrEn; + UINT8 PcieCorErrCntr; + UINT8 PcieCorErrMaskBitMap; + UINT16 PcieCorErrThres; + UINT8 PcieAerCorrErrEn; + UINT8 PcieAerAdNfatErrEn; + UINT8 PcieAerNfatErrEn; + UINT8 PcieAerFatErrEn; + UINT8 SerrPropEn; + UINT8 PerrPropEn; + UINT8 OsSigOnSerrEn; + UINT8 OsSigOnPerrEn; + + UINT8 CaterrGpioSmiEn; + +// Endof RAS add + //Viral, and IoMca are not supported in EP. Will need to wrap in an EX flag + //UINT8 IoMcaEn; + + UINT8 McBankWarmBootClearError; + UINT8 KTIFailoverSmiEn; + + UINT8 irpp0_parityError; + UINT8 irpp0_qtOverflow; + UINT8 irpp0_unexprsp; + UINT8 irpp0_csraccunaligned; + UINT8 irpp0_unceccCs1; + UINT8 irpp0_unceccCs0; + UINT8 irpp0_rcvdpoison; + UINT8 irpp0_crreccCs1; + UINT8 irpp0_crreccCs0; + + UINT8 PropagateSerr; + UINT8 PropagatePerr; + + // + // Boot Options + // + UINT8 serialDebugMsgLvl; + UINT8 serialDebugTrace; + UINT8 serialDebugMsgLvlTrainResults; + UINT8 ResetOnMemMapChange; + UINT8 ForceSetup; + UINT8 BiosGuardEnabled; + UINT8 BiosGuardPlatformSupported; + UINT8 EnableAntiFlashWearout; + UINT8 AntiFlashWearoutSupported; + UINT8 RtoPopulateBGDirectory; + + UINT8 Use1GPageTable; + // + // UINT8 QuietBoot; + // + UINT8 FastBoot; + + // + // Reserve Memory that is hidden from the OS. + // + UINT8 ReserveMem; + UINT64 ReserveStartAddr; + + // + // Reserve TAGEC Memory + // + UINT8 TagecMem; + + //Usb Configdata + UINT8 UsbMassDevNum; + UINT8 UsbLegacySupport; + UINT8 UsbEmul6064; + UINT8 UsbMassResetDelay; + UINT8 UsbNonBoot; + UINT8 UsbEmu1; + UINT8 UsbEmu2; + UINT8 UsbEmu3; + UINT8 UsbEmu4; + UINT8 UsbEmu5; + UINT8 UsbEmu6; + UINT8 UsbEmu7; + UINT8 UsbEmu8; + UINT8 UsbEmu9; + UINT8 UsbEmu10; + UINT8 UsbEmu11; + UINT8 UsbEmu12; + UINT8 UsbEmu13; + UINT8 UsbEmu14; + UINT8 UsbEmu15; + UINT8 UsbEmu16; + UINT8 UsbStackSupport; + + // Console Redirection + UINT8 ConsoleRedirection; + UINT8 FlowControl; + UINT64 BaudRate; + UINT8 TerminalType; + UINT8 LegacyOsRedirection; + UINT8 TerminalResolution; + UINT8 DataBits; + UINT8 Parity; + UINT8 StopBits; + +#ifdef EFI_PCI_IOV_SUPPORT + UINT8 SystemPageSize; + UINT8 ARIEnable; + UINT8 ARIForward; + UINT8 SRIOVEnable; + UINT8 MRIOVEnable; +#endif + // + // RAS + // + +// +// Network setup entries - start here <><><><><> +// + UINT8 LegacyPxeRom; + UINT8 EfiNetworkSupport; +// +// Network setup entries - end here <><><><><> +// + +// +// SERIALPORT BAUD RATE: Begin +// + UINT32 SerialBaudRate; +// +// SERIALPORT BAUD RATE: END +// + + UINT8 BootAllOptions; + UINT8 SetShellFirst; + + // + // Overclocking related setup variables + // + UINT8 PlatformOCSupport; + UINT8 FilterPll; + UINT8 OverclockingSupport; + + UINT8 CoreMaxOcRatio; + UINT8 CoreVoltageMode; + UINT16 CoreVoltageOverride; + UINT16 CoreVoltageOffset; + UINT8 CoreVoltageOffsetPrefix; + UINT16 CoreExtraTurboVoltage; + + // + // OC related + // + UINT8 MemoryVoltage; + UINT8 MemoryVoltageDefault; + UINT8 tCL; + + // + // CLR Related + // + UINT8 ClrMaxOcRatio; + UINT8 ClrVoltageMode; + UINT16 ClrVoltageOverride; + UINT16 ClrVoltageOffset; + UINT8 ClrVoltageOffsetPrefix; + UINT16 ClrExtraTurboVoltage; + + // + // Uncore Related + // + UINT16 UncoreVoltageOffset; + UINT8 UncoreVoltageOffsetPrefix; + UINT16 IoaVoltageOffset; + UINT8 IoaVoltageOffsetPrefix; + UINT16 IodVoltageOffset; + UINT8 IodVoltageOffsetPrefix; + + // + // SVID and FIVR Related + // + UINT8 SvidEnable; + UINT16 SvidVoltageOverride; + UINT8 FivrFaultsEnable; + UINT8 FivrEfficiencyEnable; + + UINT8 SataInterfaceRAIDMode; + UINT8 sSataInterfaceRAIDMode; + + UINT16 C01MemoryVoltage; + UINT16 C23MemoryVoltage; + + UINT16 CpuVccInVoltage; + + UINT8 VccIoVoltage; + + UINT8 CloudProfile; + UINT16 VariablePlatId; + + //XTU 3.0 + + UINT8 FlexRatioOverrideDefault; + UINT8 RatioLimit1Default; + UINT8 RatioLimit2Default; + UINT8 RatioLimit3Default; + UINT8 RatioLimit4Default; + UINT8 OverclockingLockDefault; + UINT8 DdrRefClkDefault; + UINT8 DdrRatioDefault; + UINT8 tCLDefault; + UINT8 tCWLDefault; + UINT16 tFAWDefault; + UINT16 tRASDefault; + UINT16 tRCDefault; + UINT8 tRCDDefault; + UINT16 tREFIDefault; + UINT16 tRFCDefault; + UINT8 tRPDefault; + UINT8 tRPabDefault; + UINT8 tRRDDefault; + UINT8 tRTPDefault; + UINT8 tWRDefault; + UINT8 tWTRDefault; + UINT8 NModeDefault; + UINT8 CoreMaxOcRatioDefault; + UINT8 CoreVoltageModeDefault; + UINT16 CoreVoltageOverrideDefault; + UINT16 CoreVoltageOffsetDefault; + UINT8 CoreVoltageOffsetPrefixDefault; + UINT16 CoreExtraTurboVoltageDefault; + UINT8 GtOcSupportDefault; + UINT8 GtOcFrequencyDefault; + UINT16 GtExtraTurboVoltageDefault; + UINT16 GtOcVoltageDefault; + UINT8 GtVoltageModeDefault; + UINT16 GtVoltageOverrideDefault; + UINT16 GtVoltageOffsetDefault; + UINT8 GtVoltageOffsetPrefixDefault; + UINT8 ClrMaxOcRatioDefault; + UINT8 ClrVoltageModeDefault; + UINT16 ClrVoltageOverrideDefault; + UINT16 ClrVoltageOffsetDefault; + UINT8 ClrVoltageOffsetPrefixDefault; + UINT16 ClrExtraTurboVoltageDefault; + UINT16 UncoreVoltageOffsetDefault; + UINT8 UncoreVoltageOffsetPrefixDefault; + UINT16 IoaVoltageOffsetDefault; + UINT8 IoaVoltageOffsetPrefixDefault; + UINT16 IodVoltageOffsetDefault; + UINT8 IodVoltageOffsetPrefixDefault; + UINT8 SvidEnableDefault; + UINT16 SvidVoltageOverrideDefault; + UINT8 FivrFaultsEnableDefault; + UINT8 FivrEfficiencyEnableDefault; + UINT16 VrCurrentLimitDefault; + UINT8 EnableGvDefault; + UINT8 TurboModeDefault; + UINT8 PowerLimit1TimeDefault; + UINT16 PowerLimit1Default; + UINT16 PowerLimit2Default; + + + UINT8 RatioLimit1; //ratiolimit handling has changed in SKX. knobs might need to change too. Will have to revisit again. + UINT8 RatioLimit2; + UINT8 RatioLimit3; + UINT8 RatioLimit4; + UINT8 CpuRatio; // need to understand what is the difference between maxnonturboratio and cpuratio. if cpuratiooverride is 0, then cpuratio is same as maxnonturboratio. add this to platform cpu policy or socketsetup. + UINT8 CpuRatioOverride; + UINT8 IsTurboRatioDefaultsInitalized; // related to initializing all the vardefault. is this flow needed for HEDT/intended only for clients? no need for set up creation. + + + UINT8 DdrRefClk; //cant find any in purley. new one? + UINT8 PcieRatioDisabled;//need to check if this is applicable to HEDT. also no need to create a setup variable. + UINT8 NMode ; + UINT8 Pmtt; + + UINT16 GtVoltageOffset; //existing but no set up option + UINT16 VrCurrentLimit;//done + //UINT8 SpdProfileSelected; same as XMPMode + UINT8 NModeSupport; + UINT8 WDTSupportforNextOSBoot; // no setup option needed + UINT16 TimeforNextOSBoot; // no setup optiom needed + UINT8 PlatformUnstable; // no set up option needed. this decides if all the vardefaults are needed. + UINT8 GtVoltageMode; //existing but no set up option + UINT8 DdrRatio; + UINT8 GtOcFrequency; + UINT16 GtExtraTurboVoltage; //existing but no set up option + UINT16 GtVoltageOverride; //existing but no set up option + UINT8 GtVoltageOffsetPrefix; + UINT8 GtOcSupport; + // + // CPU releated + // + UINT8 FlexOverrideEnable; + UINT8 FlexRatioOverride; + UINT8 PowerLimit3Override; + UINT32 PowerLimit3; + UINT8 PowerLimit3Time; + UINT8 PowerLimit3DutyCycle; + UINT8 PowerLimit3Lock; + UINT8 MemoryVoltageOverride; + + // + // ICC Related + // + UINT8 BClkOverride; + UINT8 BclkAdjustable; + UINT8 DmiPegRatio; + UINT8 SkipXmlComprs; + UINT8 DfxAdvDebugJumper; + UINT8 DfxAltPostCode; + + // + // Validation Related + // + UINT8 ValidationResetType; + UINT16 ValidationCountOuter; + UINT16 ValidationCountInner; + UINT8 ValidationStopOnError; + UINT8 ValidationBootWhenDone; + UINT8 ValidationSkxPciError; + UINT8 ValidationSkxPciLinkError; + UINT8 ValidationPchPciError; + UINT8 ValidationSkxPciLinkRecoveryCountError; + UINT16 ValidationSkxPciLinkRecoveryCountThreshold; + UINT8 ValidationKtiError; + + UINT8 TraceHubDebugInterface; + UINT8 RamDebugInterface; + UINT8 StorageOpROMSuppression; +// +// PC_SIO_END +// + UINT8 RsaSupport; + +} SYSTEM_CONFIGURATION; + +#pragma pack() + +#define EFI_HDD_PRESENT 0x01 +#define EFI_HDD_NOT_PRESENT 0x00 +#define EFI_CD_PRESENT 0x02 +#define EFI_CD_NOT_PRESENT 0x00 + +#define EFI_HDD_WARNING_ON 0x01 +#define EFI_CD_WARNING_ON 0x02 +#define EFI_SMART_WARNING_ON 0x04 +#define EFI_HDD_WARNING_OFF 0x00 +#define EFI_CD_WARNING_OFF 0x00 +#define EFI_SMART_WARNING_OFF 0x00 + +#endif // #ifndef _SETUP_VARIABLE diff --git a/Platform/Intel/PurleyOpenBoardPkg/Include/IioBifurcationSlotTable.h b/Platform/Intel/PurleyOpenBoardPkg/Include/IioBifurcationSlotTable.h new file mode 100644 index 0000000000..92b3057cdb --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Include/IioBifurcationSlotTable.h @@ -0,0 +1,106 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef IIOBIFURCATIONSLOTTABLE_H +#define IIOBIFURCATIONSLOTTABLE_H + +#include "IioPlatformData.h" + +#define QAT_ENABLED 0 // QAT is active-low +#define RISER_PRESENT 0 +#define RISER_NOT_PRESENT 1 +#define RISER_HP_EN 1 +#define RISER_WINGED_IN 0 +#define RISER_SLOT9_DISABLE 1 + +typedef struct { + UINT8 Socket; + UINT8 IouNumber; + UINT8 Bifurcation; +} IIO_BIFURCATION_ENTRY; + +typedef union { + struct { + UINT8 PresentSignal:1; + UINT8 HPConf:1; + UINT8 WingConf:1; + UINT8 Slot9En:1; + } Bits; + UINT8 Data; +} PCIE_RISER_ID; + +enum { + Iio_PortA = 0, + Iio_PortB = 1, + Iio_PortC = 2, + Iio_PortD = 3 +}; +typedef enum { + Iio_Iou0 =0, + Iio_Iou1, + Iio_Iou2, + Iio_Mcp0, + Iio_Mcp1, + Iio_IouMax +} IIO_IOUS; + +typedef enum { + Iio_Socket0 = 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + VPP_PORT_0 = 0, + VPP_PORT_1, + VPP_PORT_2, + VPP_PORT_3 +} VPP_PORT; +/// +/// Platform Port/Socket assignments. +/// + +#define ENABLE 1 +#define DISABLE 0 +#define NO_SLT_IMP 0xFF +#define SLT_IMP 1 +#define HIDE 1 +#define NOT_HIDE 0 +#define VPP_PORT_0 0 +#define VPP_PORT_1 1 +#define VPP_PORT_MAX 0xFF +#define VPP_ADDR_MAX 0xFF +#define PWR_VAL_MAX 0xFF +#define PWR_SCL_MAX 0xFF + +typedef struct { + UINT8 PortIndex; + UINT8 SlotNumber; // 0xff if slot not implemented , Slot number if slot implemented + BOOLEAN InterLockPresent; + UINT8 SlotPowerLimitScale; + UINT8 SlotPowerLimitValue; + BOOLEAN HotPlugCapable; + UINT8 VppPort; // 0xff if Vpp not enabled + UINT8 VppAddress; + BOOLEAN PcieSSDCapable; + UINT8 PcieSSDVppPort; // 0xff if Vpp not enabled + UINT8 PcieSSDVppAddress; + BOOLEAN Hidden; +} IIO_SLOT_CONFIG_ENTRY; + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Include/Platform.h b/Platform/Intel/PurleyOpenBoardPkg/Include/Platform.h new file mode 100644 index 0000000000..8871b01fd0 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Include/Platform.h @@ -0,0 +1,98 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "Uefi.h" +#include "Guid/SetupVariable.h" +#include "UncoreCommonIncludes.h" +#include + +#ifndef __PLATFORM_H__ +#define __PLATFORM_H__ + +// +// Assigning default ID and base addresses here, these definitions are used by ACPI tables +// + +#define PCH_INTERRUPT_BASE 0 + +#if MAX_SOCKET > 4 +#define PCH_IOAPIC 0 +#else +#define PCH_IOAPIC (1 << 0) +#endif + +// +// This structure stores the base and size of the ACPI reserved memory used when +// resuming from S3. This region must be allocated by the platform code. +// +typedef struct { + UINT32 AcpiReservedMemoryBase; + UINT32 AcpiReservedMemorySize; + UINT32 SystemMemoryLength; +} RESERVED_ACPI_S3_RANGE; + +#define RESERVED_ACPI_S3_RANGE_OFFSET (EFI_PAGE_SIZE - sizeof (RESERVED_ACPI_S3_RANGE)) + +// +// SMBUS Data +// +#define PCH_SMBUS_BASE_ADDRESS 0x0780 + +// +// CMOS usage +// + +#define CMOS_WARM_RESET_COUNTER_OFFSET 0xBD // 1 byte CMOS Space for passing warm reset counter to Dxe + // due to reset in MRC Dxe always thinks that warm reset occurs + // counter > 1 -> means WarmReset + +// +// ACPI and legacy I/O register offsets from PMBASE +// +#define R_ACPI_PM1_STS 0x00 +#define R_ACPI_PM1_EN 0x02 +#define R_ACPI_PM1_CNT 0x04 +#define R_ACPI_PM1_TMR 0x08 +#define R_ACPI_PROC_CNT 0x10 +#define R_ACPI_PM2_CNT 0x50 +#define R_ACPI_GPE0_STS 0x20 +#define R_ACPI_GPE0_EN 0x28 +#define R_ACPI_SMI_EN 0x30 +#define R_ACPI_SMI_STS 0x34 +#define R_ACPI_ALT_GP_SMI_EN 0x38 +#define R_ACPI_ALT_GP_SMI_STS 0x3A + +#define R_ACPI_LV2 0x14 + +#define R_IOPORT_CMOS_STANDARD_INDEX 0x70 +#define R_IOPORT_CMOS_STANDARD_DATA 0x71 + +#define R_IOPORT_CMOS_UPPER_INDEX 0x72 +#define R_IOPORT_CMOS_UPPER_DATA 0x73 + +#define R_IOPORT_CMOS_IDX_DIAGNOSTIC_STATUS 0x0E + +// +// Misc PCI register offsets and sizes +// +#define R_EFI_PCI_SVID 0x2C +#define V_EFI_PCI_SVID_SIZE 0x2 +#define R_EFI_PCI_SID 0x2E +#define V_EFI_PCI_SID_SIZE 0x2 + +// +// Need min. of 24 MB PEI phase +// +#define PEI_MIN_MEMORY_SIZE (EFI_PHYSICAL_ADDRESS) ((320 * 0x100000)) + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Include/Ppi/SystemBoard.h b/Platform/Intel/PurleyOpenBoardPkg/Include/Ppi/SystemBoard.h new file mode 100644 index 0000000000..902c8931b9 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Include/Ppi/SystemBoard.h @@ -0,0 +1,69 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PEI_SYSTEM_BOARD__H_ +#define _PEI_SYSTEM_BOARD__H_ + +#include +#include +#include +#include +#include +#include +#include + +/// +/// The forward declaration for SYSTEM_BOARD_INFO_PPI. +/// +typedef struct _SYSTEM_BOARD_PPI SYSTEM_BOARD_PPI; + +/** + + SystemIioPortBifurcationInit is used to updating the IIO_GLOBALS Data Structure with IIO + SLOT config data + Bifurcation config data + + @param *mSB - pointer to this protocol + + @retval *IioUds updated with SLOT and Bifurcation information updated. + +**/ +typedef +VOID + (EFIAPI *PEI_SYSTEM_IIO_PORT_BIF_INIT) ( + IN IIO_GLOBALS *IioGlobalData + ); +/** + + GetUplinkPortInformation is used to get board based uplink port information + + @param IioIndex - Socket ID + + @retval PortIndex for uplink. + +**/ +typedef +UINT8 + (EFIAPI *PEI_GET_UPLINK_PORT_INFORMATION) ( + IN UINT8 IioIndex + ); + + +struct _SYSTEM_BOARD_PPI { + PEI_SYSTEM_IIO_PORT_BIF_INIT SystemIioPortBifurcationInit; // Update OEM IIO Port Bifurcation based on PlatformConfiguration + PEI_GET_UPLINK_PORT_INFORMATION GetUplinkPortInformation; // Get Uplink port information +}; + +extern EFI_GUID gEfiPeiSystemBoardPpiGuid; + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Include/Protocol/PciIovPlatform.h b/Platform/Intel/PurleyOpenBoardPkg/Include/Protocol/PciIovPlatform.h new file mode 100644 index 0000000000..cce27a5fe7 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Include/Protocol/PciIovPlatform.h @@ -0,0 +1,76 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCI_IOV_PLATFORM_H_ +#define _PCI_IOV_PLATFORM_H_ + + +// +// Protocol for GUID. +// + +typedef struct _EFI_PCI_IOV_PLATFORM_PROTOCOL EFI_PCI_IOV_PLATFORM_PROTOCOL; + +typedef UINT32 EFI_PCI_IOV_PLATFORM_POLICY; + +#define EFI_PCI_IOV_POLICY_ARI 0x0001 +#define EFI_PCI_IOV_POLICY_SRIOV 0x0002 +#define EFI_PCI_IOV_POLICY_MRIOV 0x0004 + +typedef +EFI_STATUS +(EFIAPI * EFI_PCI_IOV_PLATFORM_GET_SYSTEM_LOWEST_PAGE_SIZE) ( + IN EFI_PCI_IOV_PLATFORM_PROTOCOL *This, + OUT UINT32 *SystemLowestPageSize +) +/** + + The GetSystemLowestPageSize() function retrieves the system lowest page size. + + @param This - Pointer to the EFI_PCI_IOV_PLATFORM_PROTOCOL instance. + @param SystemLowestPageSize - The system lowest page size. (This system supports a + page size of 2^(n+12) if bit n is set.) + + @retval EFI_SUCCESS - The function completed successfully. + @retval EFI_INVALID_PARAMETER - SystemLowestPageSize is NULL. + +**/ +; + +typedef +EFI_STATUS +(EFIAPI * EFI_PCI_IOV_PLATFORM_GET_PLATFORM_POLICY) ( + IN EFI_PCI_IOV_PLATFORM_PROTOCOL *This, + OUT EFI_PCI_IOV_PLATFORM_POLICY *PciIovPolicy +) +/** + + The GetPlatformPolicy() function retrieves the platform policy regarding PCI IOV. + + @param This - Pointer to the EFI_PCI_IOV_PLATFORM_PROTOCOL instance. + @param PciIovPolicy - The platform policy for PCI IOV configuration. + + @retval EFI_SUCCESS - The function completed successfully. + @retval EFI_INVALID_PARAMETER - PciPolicy is NULL. + +**/ +; + +typedef struct _EFI_PCI_IOV_PLATFORM_PROTOCOL { + EFI_PCI_IOV_PLATFORM_GET_SYSTEM_LOWEST_PAGE_SIZE GetSystemLowestPageSize; + EFI_PCI_IOV_PLATFORM_GET_PLATFORM_POLICY GetPlatformPolicy; +} EFI_PCI_IOV_PLATFORM_PROTOCOL; + +extern EFI_GUID gEfiPciIovPlatformProtocolGuid; + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Include/SetupTable.h b/Platform/Intel/PurleyOpenBoardPkg/Include/SetupTable.h new file mode 100644 index 0000000000..99ada898c7 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Include/SetupTable.h @@ -0,0 +1,27 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SETUP_TABLE_H_ +#define _SETUP_TABLE_H_ + +#include +#include +#include + +typedef struct { + SOCKET_CONFIGURATION SocketConfig; + SYSTEM_CONFIGURATION SystemConfig; + PCH_RC_CONFIGURATION PchRcConfig; +} SETUP_DATA; + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Include/SioRegs.h b/Platform/Intel/PurleyOpenBoardPkg/Include/SioRegs.h new file mode 100644 index 0000000000..d3ac4c95a5 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Include/SioRegs.h @@ -0,0 +1,41 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SIO_REG_H_ +#define _SIO_REG_H_ + +typedef struct { + UINT8 Index; + UINT8 Value; +} SIO_INDEX_DATA; + +#define REG_LOGICAL_DEVICE 0x07 +#define ACTIVATE 0x30 + +#define BASE_ADDRESS_HIGH0 0x60 +#define BASE_ADDRESS_LOW0 0x61 +#define INTERRUPT_TYPE 0x71 + +#define SIO_INDEX_PORT 0x2E +#define SIO_DATA_PORT 0x2F + +#define SIO_UART1 0x02 +#define SIO_SMI 0x0D +#define SIO_MAILBOX 0x0E + +#define SIO_UNLOCK 0xA5 +#define SIO_LOCK 0xAA + +#define EXIST BIT4 + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/IoApic.h b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/IoApic.h new file mode 100644 index 0000000000..55ca9f68fd --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/IoApic.h @@ -0,0 +1,28 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _IOAPIC_H_ +#define _IOAPIC_H_ + +#define EFI_IO_APIC_INDEX_OFFSET 0x00 +#define EFI_IO_APIC_DATA_OFFSET 0x10 +#define EFI_IO_APIC_IRQ_ASSERTION_OFFSET 0x20 +#define EFI_IO_APIC_EOI_OFFSET 0x40 + +#define EFI_IO_APIC_ID_REGISTER 0x0 +#define EFI_IO_APIC_ID_BITSHIFT 24 +#define EFI_IO_APIC_VER_REGISTER 0x1 +#define EFI_IO_APIC_BOOT_CONFIG_REGISTER 0x3 +#define EFI_IO_APIC_FSB_INT_DELIVERY 0x1 + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciIovPlatformPolicy.c b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciIovPlatformPolicy.c new file mode 100644 index 0000000000..6737bbbcf0 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciIovPlatformPolicy.c @@ -0,0 +1,102 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include "PciPlatform.h" +#include + +#ifdef EFI_PCI_IOV_SUPPORT + +/** + + The GetSystemLowestPageSize() function retrieves the system lowest page size. + + @param This - Pointer to the EFI_PCI_IOV_PLATFORM_PROTOCOL instance. + @param SystemLowestPageSize - The system lowest page size. (This system supports a + page size of 2^(n+12) if bit n is set.) + + @retval EFI_SUCCESS - The function completed successfully. + @retval EFI_INVALID_PARAMETER - SystemLowestPageSize is NULL. + +**/ +EFI_STATUS +EFIAPI +GetSystemLowestPageSize ( + IN EFI_PCI_IOV_PLATFORM_PROTOCOL *This, + OUT UINT32 *SystemLowestPageSize +) +{ + UINT8 SystemPageSize; + + CopyMem (&SystemPageSize, (UINT8 *)PcdGetPtr(PcdSetupData) + OFFSET_OF(SYSTEM_CONFIGURATION, SystemPageSize), sizeof(UINT8)); + + if (SystemLowestPageSize != NULL) { + // + // Page size is 4K + // + //*SystemLowestPageSize = 1; + *SystemLowestPageSize = SystemPageSize; + } + return EFI_SUCCESS; +} + +/** + + The GetIovPlatformPolicy() function retrieves the platform policy regarding PCI IOV. + + @param This - Pointer to the EFI_PCI_IOV_PLATFORM_PROTOCOL instance. + @param PciIovPolicy - The platform policy for PCI IOV configuration. + + @retval EFI_SUCCESS - The function completed successfully. + @retval EFI_INVALID_PARAMETER - PciPolicy is NULL. + +**/ +EFI_STATUS +EFIAPI +GetIovPlatformPolicy ( + IN EFI_PCI_IOV_PLATFORM_PROTOCOL *This, + OUT EFI_PCI_IOV_PLATFORM_POLICY *PciIovPolicy +) +{ + UINT8 PolicyEnable; + UINT8 ARIEnable; + UINT8 SRIOVEnable; + UINT8 MRIOVEnable; + + PolicyEnable = 0; + + CopyMem (&ARIEnable, (UINT8 *)PcdGetPtr(PcdSetupData) + OFFSET_OF(SYSTEM_CONFIGURATION, ARIEnable), sizeof(UINT8)); + CopyMem (&SRIOVEnable, (UINT8 *)PcdGetPtr(PcdSetupData) + OFFSET_OF(SYSTEM_CONFIGURATION, SRIOVEnable), sizeof(UINT8)); + CopyMem (&MRIOVEnable, (UINT8 *)PcdGetPtr(PcdSetupData) + OFFSET_OF(SYSTEM_CONFIGURATION, MRIOVEnable), sizeof(UINT8)); + + if (ARIEnable == TRUE) { + PolicyEnable = PolicyEnable | EFI_PCI_IOV_POLICY_ARI; + } + + if (SRIOVEnable == TRUE) { + PolicyEnable = PolicyEnable | EFI_PCI_IOV_POLICY_SRIOV; + } + + if (MRIOVEnable == TRUE) { + PolicyEnable = PolicyEnable | EFI_PCI_IOV_POLICY_MRIOV; + } + + if (PciIovPolicy != NULL) { + //*PciIovPolicy = EFI_PCI_IOV_POLICY_ARI | EFI_PCI_IOV_POLICY_SRIOV; + *PciIovPolicy = PolicyEnable; + } + return EFI_SUCCESS; +} + +#endif + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciIovPlatformPolicy.h b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciIovPlatformPolicy.h new file mode 100644 index 0000000000..8b358d14a3 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciIovPlatformPolicy.h @@ -0,0 +1,57 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef PCI_IOV_PLATFORM_POLICY_H_ +#define PCI_IOV_PLATFORM_POLICY_H_ + +/** + + The GetSystemLowestPageSize() function retrieves the system lowest page size. + + @param This - Pointer to the EFI_PCI_IOV_PLATFORM_PROTOCOL instance. + @param SystemLowestPageSize - The system lowest page size. (This system supports a + page size of 2^(n+12) if bit n is set.) + + @retval EFI_SUCCESS - The function completed successfully. + @retval EFI_INVALID_PARAMETER - SystemLowestPageSize is NULL. + +**/ +EFI_STATUS +EFIAPI +GetSystemLowestPageSize ( + IN EFI_PCI_IOV_PLATFORM_PROTOCOL *This, + OUT UINT32 *SystemLowestPageSize +) +; + + +/** + + The GetPlatformPolicy() function retrieves the platform policy regarding PCI IOV. + + @param This - Pointer to the EFI_PCI_IOV_PLATFORM_PROTOCOL instance. + @param PciIovPolicy - The platform policy for PCI IOV configuration. + + @retval EFI_SUCCESS - The function completed successfully. + @retval EFI_INVALID_PARAMETER - PciPolicy is NULL. + +**/ +EFI_STATUS +EFIAPI +GetIovPlatformPolicy ( + IN EFI_PCI_IOV_PLATFORM_PROTOCOL *This, + OUT EFI_PCI_IOV_PLATFORM_POLICY *PciIovPolicy +) +; + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatform.c b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatform.c new file mode 100644 index 0000000000..9f042c2b76 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatform.c @@ -0,0 +1,189 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include "PciPlatform.h" +#include +#ifdef EFI_PCI_IOV_SUPPORT +#include "PciIovPlatformPolicy.h" +#endif + +PCI_PLATFORM_PRIVATE_DATA mPciPrivateData; + +BOOLEAN FirstCall = TRUE; +UINT8 sSataRaidLoadEfiDriverOption; +UINT8 SataRaidLoadEfiDriverOption; +UINT8 BootNetworkOption; + +/** + + Set the PciPolicy as EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_NO_ALIAS. + + @param This - The pointer to the Protocol itself. + PciPolicy - the returned Policy. + + @retval EFI_UNSUPPORTED - Function not supported. + @retval EFI_INVALID_PARAMETER - Invalid PciPolicy value. + +**/ +EFI_STATUS +EFIAPI +GetPlatformPolicy ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + OUT EFI_PCI_PLATFORM_POLICY *PciPolicy + ) +{ + if (PciPolicy == NULL) { + return EFI_INVALID_PARAMETER; + } + + return EFI_UNSUPPORTED; +} + +/** + + Return a PCI ROM image for the onboard device represented by PciHandle. + + @param This - Protocol instance pointer. + PciHandle - PCI device to return the ROM image for. + RomImage - PCI Rom Image for onboard device. + RomSize - Size of RomImage in bytes. + + @retval EFI_SUCCESS - RomImage is valid. + @retval EFI_NOT_FOUND - No RomImage. + +**/ +EFI_STATUS +EFIAPI +GetPciRom ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE PciHandle, + OUT VOID **RomImage, + OUT UINTN *RomSize + ) +{ + return EFI_NOT_FOUND; +} + +/** + + GC_TODO: Add function description + + @param This - GC_TODO: add argument description + @param Function - GC_TODO: add argument description + @param Phase - GC_TODO: add argument description + + @retval EFI_INVALID_PARAMETER - GC_TODO: Add description for return value + @retval EFI_INVALID_PARAMETER - GC_TODO: Add description for return value + @retval EFI_UNSUPPORTED - GC_TODO: Add description for return value + @retval EFI_SUCCESS - GC_TODO: Add description for return value + +**/ +EFI_STATUS +EFIAPI +RegisterPciCallback ( + IN EFI_PCI_CALLBACK_PROTOCOL *This, + IN EFI_PCI_CALLBACK_FUNC Function, + IN EFI_PCI_ENUMERATION_PHASE Phase + ) +{ + LIST_ENTRY *NodeEntry; + PCI_CALLBACK_DATA *PciCallbackData; + + if (Function == NULL) { + return EFI_INVALID_PARAMETER; + } + + if ( (Phase & (EfiPciEnumerationDeviceScanning | EfiPciEnumerationBusNumberAssigned \ + | EfiPciEnumerationResourceAssigned)) == 0) { + return EFI_INVALID_PARAMETER; + } + // + // Check if the node has been added + // + NodeEntry = GetFirstNode (&mPciPrivateData.PciCallbackList); + while (!IsNull (&mPciPrivateData.PciCallbackList, NodeEntry)) { + PciCallbackData = PCI_CALLBACK_DATA_FROM_LINK (NodeEntry); + if (PciCallbackData->Function == Function) { + return EFI_UNSUPPORTED; + } + + NodeEntry = GetNextNode (&mPciPrivateData.PciCallbackList, NodeEntry); + } + + PciCallbackData = NULL; + PciCallbackData = AllocateZeroPool (sizeof (PCI_CALLBACK_DATA)); + ASSERT (PciCallbackData != NULL); + + if(PciCallbackData != NULL){ + PciCallbackData->Signature = PCI_CALLBACK_DATA_SIGNATURE; + PciCallbackData->Function = Function; + PciCallbackData->Phase = Phase; + InsertTailList (&mPciPrivateData.PciCallbackList, &PciCallbackData->Link); + return EFI_SUCCESS; + } else { + return EFI_UNSUPPORTED; + } +} + + +/** + + Main Entry point of the Pci Platform Driver. + + @param ImageHandle - Handle to the image. + @param SystemTable - Handle to System Table. + + @retval EFI_STATUS - Status of the function calling. + +**/ +EFI_STATUS +EFIAPI +PciPlatformDriverEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + ZeroMem (&mPciPrivateData, sizeof (mPciPrivateData)); + InitializeListHead (&mPciPrivateData.PciCallbackList); + + mPciPrivateData.PciPlatform.PlatformNotify = PhaseNotify; + mPciPrivateData.PciPlatform.PlatformPrepController = PlatformPrepController; + mPciPrivateData.PciPlatform.GetPlatformPolicy = GetPlatformPolicy; + mPciPrivateData.PciPlatform.GetPciRom = GetPciRom; + mPciPrivateData.PciCallback.RegisterPciCallback = RegisterPciCallback; +#ifdef EFI_PCI_IOV_SUPPORT + mPciPrivateData.PciIovPlatform.GetSystemLowestPageSize = GetSystemLowestPageSize; + mPciPrivateData.PciIovPlatform.GetPlatformPolicy = GetIovPlatformPolicy; +#endif + + // + // Install on a new handle + // + Status = gBS->InstallMultipleProtocolInterfaces ( + &mPciPrivateData.PciPlatformHandle, + &gEfiPciPlatformProtocolGuid, + &mPciPrivateData.PciPlatform, + &gEfiPciCallbackProtocolGuid, + &mPciPrivateData.PciCallback, +#ifdef EFI_PCI_IOV_SUPPORT + &gEfiPciIovPlatformProtocolGuid, + &mPciPrivateData.PciIovPlatform, +#endif + NULL + ); + + return Status; +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatform.h b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatform.h new file mode 100644 index 0000000000..f36fdda6e6 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatform.h @@ -0,0 +1,207 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef PCI_PLATFORM_H_ +#define PCI_PLATFORM_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// +// Global variables for Option ROMs +// + +#define INVALID 0xBD + +#define PCI_CALLBACK_DATA_SIGNATURE SIGNATURE_32 ('P', 'c', 'i', 'c') + +typedef struct { + UINT32 Signature; + LIST_ENTRY Link; + EFI_PCI_CALLBACK_FUNC Function; + EFI_PCI_ENUMERATION_PHASE Phase; +} PCI_CALLBACK_DATA; + +typedef struct { + EFI_HANDLE PciPlatformHandle; + EFI_HANDLE RootBridgeHandle; + EFI_PCI_PLATFORM_PROTOCOL PciPlatform; + EFI_PCI_CALLBACK_PROTOCOL PciCallback; +#ifdef EFI_PCI_IOV_SUPPORT + EFI_PCI_IOV_PLATFORM_PROTOCOL PciIovPlatform; +#endif + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo; + EFI_CPU_IO2_PROTOCOL *CpuIo; + EFI_LIST_ENTRY PciCallbackList; + EFI_PCI_CALLBACK_CONTEXT Context; + EFI_PCI_ENUMERATION_PHASE PciEnumerationPhase; + UINT8 BusAssignedTime; +} PCI_PLATFORM_PRIVATE_DATA; + +#define PCI_CALLBACK_DATA_FROM_LINK(_node) \ + CR ( \ + _node, \ + PCI_CALLBACK_DATA, \ + Link, \ + PCI_CALLBACK_DATA_SIGNATURE \ + ) + +extern PCI_PLATFORM_PRIVATE_DATA mPciPrivateData; +extern EFI_GUID gPchSataEfiLoadProtocolGuid; + +/** + + Perform initialization by the phase indicated. + + @param This - Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance. + @param HostBridge - The associated PCI host bridge handle. + @param Phase - The phase of the PCI controller enumeration. + @param ChipsetPhase - Defines the execution phase of the PCI chipset driver. + + @retval EFI_SUCCESS - Must return with success. + +**/ +EFI_STATUS +EFIAPI +PhaseNotify ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ) +; + +/** + + The PlatformPrepController() function can be used to notify the platform driver so that + it can perform platform-specific actions. No specific actions are required. + Several notification points are defined at this time. More synchronization points may be + added as required in the future. The PCI bus driver calls the platform driver twice for + every PCI controller-once before the PCI Host Bridge Resource Allocation Protocol driver + is notified, and once after the PCI Host Bridge Resource Allocation Protocol driver has + been notified. + This member function may not perform any error checking on the input parameters. It also + does not return any error codes. If this member function detects any error condition, it + needs to handle those errors on its own because there is no way to surface any errors to + the caller. + + @param This - Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance. + @param HostBridge - The associated PCI host bridge handle. + @param RootBridge - The associated PCI root bridge handle. + @param PciAddress - The address of the PCI device on the PCI bus. + @param Phase - The phase of the PCI controller enumeration. + @param ChipsetPhase - Defines the execution phase of the PCI chipset driver. + + @retval EFI_SUCCESS - The function completed successfully. + +**/ +EFI_STATUS +EFIAPI +PlatformPrepController ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_HANDLE RootBridge, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ) +; + +/** + + Set the PciPolicy as EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_NO_ALIAS. + + @param This - The pointer to the Protocol itself. + PciPolicy - the returned Policy. + + @retval EFI_UNSUPPORTED - Function not supported. + @retval EFI_INVALID_PARAMETER - Invalid PciPolicy value. + +**/ +EFI_STATUS +EFIAPI +GetPlatformPolicy ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + OUT EFI_PCI_PLATFORM_POLICY *PciPolicy + ) +; + +/** + + Return a PCI ROM image for the onboard device represented by PciHandle. + + @param This - Protocol instance pointer. + PciHandle - PCI device to return the ROM image for. + RomImage - PCI Rom Image for onboard device. + RomSize - Size of RomImage in bytes. + + @retval EFI_SUCCESS - RomImage is valid. + @retval EFI_NOT_FOUND - No RomImage. + +**/ +EFI_STATUS +EFIAPI +GetPciRom ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE PciHandle, + OUT VOID **RomImage, + OUT UINTN *RomSize + ) +; + +/** + + Register a callback during PCI bus enumeration + + @param This - Protocol instance pointer. + @param Function - Callback function pointer. + @param Phase - PCI enumeration phase. + + @retval EFI_SUCCESS - Function has registed successfully + @retval EFI_UNSUPPORTED - The function has been regisered + @retval EFI_InVALID_PARAMETER - The parameter is incorrect + +**/ +EFI_STATUS +EFIAPI +RegisterPciCallback ( + IN EFI_PCI_CALLBACK_PROTOCOL *This, + IN EFI_PCI_CALLBACK_FUNC Function, + IN EFI_PCI_ENUMERATION_PHASE Phase + ) +; + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatform.inf b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatform.inf new file mode 100644 index 0000000000..b46bbf713a --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatform.inf @@ -0,0 +1,78 @@ +### @file +# +# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +### + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PciPlatform + FILE_GUID = E2441B64-7EF4-41fe-B3A3-8CAA7F8D3017 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = PciPlatformDriverEntry + +[Sources] + PciPlatform.c + PciPlatform.h + PciPlatformHooks.c + PciPlatformHooks.h + PciIovPlatformPolicy.c + PciIovPlatformPolicy.h + PciSupportLib.c + +[Packages] + MdePkg/MdePkg.dec + LewisburgPkg/PchRcPkg.dec + PurleyOpenBoardPkg/PlatPkg.dec + PurleySktPkg/SocketPkg.dec + MdeModulePkg/MdeModulePkg.dec + PurleyRcPkg/RcPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + IoLib + BaseMemoryLib + DebugLib + UefiRuntimeServicesTableLib + UefiBootServicesTableLib + HobLib + S3PciLib + PcdLib + +[Protocols] + gEfiPciCallbackProtocolGuid + gEfiCpuIo2ProtocolGuid + gEfiFirmwareVolume2ProtocolGuid + gEfiPciIoProtocolGuid + gEfiPciPlatformProtocolGuid + gEfiIioUdsProtocolGuid + gEfiPciRootBridgeIoProtocolGuid + gEfiPciIovPlatformProtocolGuid + gEfiIioSystemProtocolGuid + gEfiPciHostBridgeResourceAllocationProtocolGuid + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport + gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport + gOemSkuTokenSpaceGuid.PcdSetupData + gMinPlatformPkgTokenSpaceGuid.PcdIoApicId + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicIdBase + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxNestedLevel + +[Depex] + TRUE + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatformHooks.c b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatformHooks.c new file mode 100644 index 0000000000..9310df3e67 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatformHooks.c @@ -0,0 +1,533 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_IIO_UDS_PROTOCOL *mIioUds = NULL; +EFI_IIO_SYSTEM_PROTOCOL *IioSystemProtocol = NULL; +IIO_GLOBALS *IioGlobalData = NULL; + +VOID +ChipsetCallback ( + IN EFI_HANDLE RootBridgeHandle, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_ENUMERATION_PHASE Phase, + EFI_PCI_CALLBACK_CONTEXT *Context + ) +{ + EFI_LIST_ENTRY *NodeEntry; + PCI_CALLBACK_DATA *PciCallbackData; + + // + // Check if the node has been added + // + // DEBUG ((DEBUG_ERROR, "PCI Callback (%d,%d,%d)\n",PciAddress.Bus, PciAddress.Device, PciAddress.Function )); + // + Context->PciRootBridgeIo = mPciPrivateData.PciRootBridgeIo; + NodeEntry = GetFirstNode (&mPciPrivateData.PciCallbackList); + while (!IsNull (&mPciPrivateData.PciCallbackList, NodeEntry)) { + PciCallbackData = PCI_CALLBACK_DATA_FROM_LINK (NodeEntry); + if (PciCallbackData->Phase & Phase) { + (PciCallbackData->Function) (RootBridgeHandle, PciAddress, Phase, Context); + } + + NodeEntry = GetNextNode (&mPciPrivateData.PciCallbackList, NodeEntry); + } +} + +/** + + GC_TODO: add routine description + + @param StartBus - GC_TODO: add arg description + + @retval EFI_SUCCESS - GC_TODO: add retval description + +**/ +EFI_STATUS +PciTreeTraverse ( + IN UINT8 StartBus + ) +{ + UINT64 PciAddress; + UINT8 Device; + UINT8 Func; + UINT8 SecondaryBus; + BOOLEAN MultiFunc; + + for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) { + MultiFunc = FALSE; + for (Func = 0; Func <= PCI_MAX_FUNC; Func++) { + if (IsPciDevicePresent ( + mPciPrivateData.PciRootBridgeIo, + &mPciPrivateData.Context.PciHeader, + StartBus, + Device, + Func + )) { + if ((Func == 0) && IS_PCI_MULTI_FUNC(&(mPciPrivateData.Context.PciHeader))) { + MultiFunc = TRUE; + } + PciAddress = EFI_PCI_ADDRESS (StartBus, Device, Func, 0); + ChipsetCallback ( + mPciPrivateData.RootBridgeHandle, + *(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &PciAddress, + mPciPrivateData.PciEnumerationPhase, + &(mPciPrivateData.Context) + ); + if (IS_PCI_BRIDGE (&(mPciPrivateData.Context.PciHeader))) { + PciAddress = EFI_PCI_ADDRESS (StartBus, Device, Func, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET); + mPciPrivateData.PciRootBridgeIo->Pci.Read ( + mPciPrivateData.PciRootBridgeIo, + EfiPciWidthUint8, + *(UINT64 *) &PciAddress, + 1, + &SecondaryBus + ); + if ((SecondaryBus > 0) && (SecondaryBus < 0xFF)) { + PciTreeTraverse (SecondaryBus); + } + } + } + + if (MultiFunc == FALSE) { + // + // Skip sub functions, this is not a multi function device + // + Func = PCI_MAX_FUNC; + } + } + } + + return EFI_SUCCESS; +} + +/** + + Program Io Apic Id + + @param IoApicAddress and IoApicId + + @retval None + +**/ +VOID +ProgramIoApicId ( + IN UINT32 IoApicAddress, + IN UINT8 IoApicId + ) +{ + + UINT32 Data; + + mPciPrivateData.CpuIo->Mem.Read ( + mPciPrivateData.CpuIo, + EfiCpuIoWidthUint32, + IoApicAddress + EFI_IO_APIC_INDEX_OFFSET, + 1, + &Data + ); + + // + // IOAPIC is not there + // + if (Data == (UINT32) -1) { + return ; + } + // + // Set up IO APIC ID and enable FSB delivery + // Use CPU IO protocol since the IO APIC ranges + // are not included in PCI apertures + // + Data = EFI_IO_APIC_ID_REGISTER; + mPciPrivateData.CpuIo->Mem.Write ( + mPciPrivateData.CpuIo, + EfiCpuIoWidthUint32, + IoApicAddress + EFI_IO_APIC_INDEX_OFFSET, + 1, + &Data + ); + + Data = IoApicId << EFI_IO_APIC_ID_BITSHIFT; + mPciPrivateData.CpuIo->Mem.Write ( + mPciPrivateData.CpuIo, + EfiCpuIoWidthUint32, + IoApicAddress + EFI_IO_APIC_DATA_OFFSET, + 1, + &Data + ); + + Data = EFI_IO_APIC_BOOT_CONFIG_REGISTER; + mPciPrivateData.CpuIo->Mem.Write ( + mPciPrivateData.CpuIo, + EfiCpuIoWidthUint32, + IoApicAddress + EFI_IO_APIC_INDEX_OFFSET, + 1, + &Data + ); + + Data = EFI_IO_APIC_FSB_INT_DELIVERY; + mPciPrivateData.CpuIo->Mem.Write ( + mPciPrivateData.CpuIo, + EfiCpuIoWidthUint32, + IoApicAddress + EFI_IO_APIC_DATA_OFFSET, + 1, + &Data + ); +} + +#ifdef EFI_PCI_IOV_SUPPORT +/** + + Initialize the Pci Iov Platform Data. + + @param ImageHandle - Handle to the image. + @param SystemTable - Handle to System Table. + + @retval EFI_STATUS - Status of the function calling. + +**/ +EFI_STATUS +EFIAPI +PciPlatformInitPciIovData ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PCI_IOV_PLATFORM_POLICY PciIovPolicy; + UINT32 SystemPageSize; + EFI_PCI_IOV_PLATFORM_PROTOCOL *gPciIovPlatformProtocol; + + Status = gBS->LocateProtocol ( + &gEfiPciIovPlatformProtocolGuid, + NULL, + &gPciIovPlatformProtocol + ); + if (!EFI_ERROR (Status)) { + Status = gPciIovPlatformProtocol->GetSystemLowestPageSize ( + gPciIovPlatformProtocol, + &SystemPageSize + ); + if (!EFI_ERROR (Status)) { + Status = PcdSet32S (PcdSrIovSystemPageSize, (1 << SystemPageSize)); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + } else { + return Status; + } + Status = gPciIovPlatformProtocol->GetPlatformPolicy ( + gPciIovPlatformProtocol, + &PciIovPolicy + ); + if (!EFI_ERROR (Status)) { + if (PciIovPolicy & EFI_PCI_IOV_POLICY_ARI) { + Status = PcdSetBoolS (PcdAriSupport, TRUE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + } else { + Status = PcdSetBoolS (PcdAriSupport, FALSE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + } + if (PciIovPolicy & EFI_PCI_IOV_POLICY_SRIOV) { + Status = PcdSetBoolS (PcdSrIovSupport, TRUE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + } else { + Status = PcdSetBoolS (PcdSrIovSupport, FALSE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + } + if (PciIovPolicy & EFI_PCI_IOV_POLICY_MRIOV) { + Status = PcdSetBoolS (PcdMrIovSupport, TRUE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + } else { + Status = PcdSetBoolS (PcdMrIovSupport, FALSE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + } + } else { + return Status; + } + DEBUG (( + EFI_D_INFO, + " Initialized SR-IOV Platform Data: PCIIovPolicy = 0x%x; SystemPageSize = 0x%x;\n", + PciIovPolicy, SystemPageSize + )); + } else { + DEBUG (( + EFI_D_INFO, + " Using default values for SystemPageSize;\n" + )); + } + return Status; +} +#endif + +/** + + Platform Pci Express init. + + @param HostBridgeInstance - Pointer to Host Bridge private data + does not support 64 bit memory addresses. + + @retval EFI_SUCCESS - Success. + +**/ +EFI_STATUS +PciPlatformEarlyInit ( + VOID + ) +{ + EFI_STATUS Status; + // + // Locate the IIO Protocol Interface + // + Status = gBS->LocateProtocol (&gEfiIioUdsProtocolGuid,NULL,&mIioUds); + ASSERT_EFI_ERROR (Status); + Status = gBS->LocateProtocol (&gEfiIioSystemProtocolGuid, NULL, &IioSystemProtocol); + ASSERT_EFI_ERROR (Status); + + IioGlobalData = IioSystemProtocol->IioGlobalData; + +#ifdef EFI_PCI_IOV_SUPPORT + Status = PciPlatformInitPciIovData(); // Update IOV PCD values +#endif + return EFI_SUCCESS; +} + + +/** + + Init pci device registers after the device resources have been allocated, so + that devices behind a bus could be accessed. + + @param HostBridgeInstance - PCI_HOST_BRIDGE_INSTANCE. + + @retval EFI_SUCCESS - Function has completed successfully. + +**/ +EFI_STATUS +PciPlatformPostInit ( + VOID + ) +{ + // + // Program all the IOAPIC in system + // + UINT8 Socket, Stack, IoApicId; + UINT8 Step; + UINT8 MaxSocket; + +#if MAX_SOCKET <= 4 + Step = 6; + MaxSocket = 4; +#else + Step = 4; + MaxSocket = 8; +#endif + + Stack = 0; + IoApicId = 0; + ProgramIoApicId (mIioUds->IioUdsPtr->PlatformData.IIO_resource[0].StackRes[0].IoApicBase, PcdGet8(PcdIoApicId)); + for (Socket = 0; Socket < MAX_SOCKET; Socket++) { + if (!(mIioUds->IioUdsPtr->SystemStatus.socketPresentBitMap & (1 << Socket))) + continue; + + for (Stack = 0; Stack < MAX_IIO_STACK; Stack++) { + if (!(mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[Socket].stackPresentBitmap & (1 << Stack))) + continue; + + if ((Socket < MaxSocket) && (Stack < Step)) { + IoApicId = PcdGet8(PcdPcIoApicIdBase) + Step * Socket + Stack; + } + + if ((Socket == 0) && (Stack == 0)) { + ProgramIoApicId ((mIioUds->IioUdsPtr->PlatformData.IIO_resource[Socket].StackRes[Stack].IoApicBase + 0x1000), IoApicId); + } else { + ProgramIoApicId (mIioUds->IioUdsPtr->PlatformData.IIO_resource[Socket].StackRes[Stack].IoApicBase, IoApicId); + } + } + } + return EFI_SUCCESS; +} + +/** + + The PlatformPrepController() function can be used to notify the platform driver so that + it can perform platform-specific actions. No specific actions are required. + Several notification points are defined at this time. More synchronization points may be + added as required in the future. The PCI bus driver calls the platform driver twice for + every PCI controller-once before the PCI Host Bridge Resource Allocation Protocol driver + is notified, and once after the PCI Host Bridge Resource Allocation Protocol driver has + been notified. + This member function may not perform any error checking on the input parameters. It also + does not return any error codes. If this member function detects any error condition, it + needs to handle those errors on its own because there is no way to surface any errors to + the caller. + + @param This - Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance. + @param HostBridge - The associated PCI host bridge handle. + @param RootBridge - The associated PCI root bridge handle. + @param PciAddress - The address of the PCI device on the PCI bus. + @param Phase - The phase of the PCI controller enumeration. + @param ChipsetPhase - Defines the execution phase of the PCI chipset driver. + + @retval EFI_SUCCESS - The function completed successfully. + @retval EFI_UNSUPPORTED - Not supported. + +**/ +EFI_STATUS +EFIAPI +PlatformPrepController ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_HANDLE RootBridge, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ) +{ + if (mPciPrivateData.RootBridgeHandle == NULL) { + mPciPrivateData.RootBridgeHandle = RootBridge; + } + + return EFI_SUCCESS; +} + +/** + + Perform initialization by the phase indicated. + + @param This - Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance. + @param HostBridge - The associated PCI host bridge handle. + @param Phase - The phase of the PCI controller enumeration. + @param ChipsetPhase - Defines the execution phase of the PCI chipset driver. + + @retval EFI_SUCCESS - Must return with success. + +**/ +EFI_STATUS +EFIAPI +PhaseNotify ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ) +{ + EFI_STATUS Status; + UINT8 i; + UINT8 Stack; + + if (ChipsetPhase == ChipsetEntry) { + return EFI_SUCCESS; + } + // + // If for multiple host bridges, need special consideration + // + switch (Phase) { + + case EfiPciHostBridgeBeginEnumeration: + // + // Pre-initialization before PCI bus enumeration + // No bus number and no PCI resource + // + Status = gBS->LocateProtocol ( + &gEfiPciRootBridgeIoProtocolGuid, + NULL, + &(mPciPrivateData.PciRootBridgeIo) + ); + ASSERT_EFI_ERROR (Status); + + Status = gBS->LocateProtocol ( + &gEfiCpuIo2ProtocolGuid, + NULL, + &(mPciPrivateData.CpuIo) + ); + ASSERT_EFI_ERROR (Status); + mPciPrivateData.Context.CpuIo = mPciPrivateData.CpuIo; + + DEBUG ((DEBUG_ERROR, "PCI Platform Pre-Initialization (Before bus scanning)\n")); + PciPlatformEarlyInit (); + break; + + case EfiPciHostBridgeEndBusAllocation: + // + // There are two rounds PCI bus scanning + // First round will initilize the PCI hotplug device + // Second round will be the final one + // + if (mPciPrivateData.BusAssignedTime == 0) { + mPciPrivateData.PciEnumerationPhase = EfiPciEnumerationDeviceScanning; + for (i = 0 ; i < MaxIIO ; i++) { + if (mIioUds->IioUdsPtr->PlatformData.IIO_resource[i].Valid) { + for(Stack = 0; Stack < MAX_IIO_STACK; Stack ++) { + PciTreeTraverse (mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[i].StackBus[Stack]); + } + } + } + mPciPrivateData.BusAssignedTime++; + DEBUG ((DEBUG_ERROR, "PCI Platform bus assigned\n")); + } + break; + + case EfiPciHostBridgeBeginResourceAllocation: + // + // PCI bus number has been assigned, but resource is still empty + // + DEBUG ((DEBUG_ERROR, "PCI Platform Mid-Initialization (After bus number assignment)\n")); + mPciPrivateData.PciEnumerationPhase = EfiPciEnumerationBusNumberAssigned; + for (i = 0 ; i < MaxIIO ; i++) { + if (mIioUds->IioUdsPtr->PlatformData.IIO_resource[i].Valid) { + for(Stack = 0; Stack < MAX_IIO_STACK; Stack ++) { + PciTreeTraverse (mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[i].StackBus[Stack]); + } + } + } + //PciPlatformMidInit (); + break; + + case EfiPciHostBridgeEndResourceAllocation: + // + // Resource enumeration is done. + // Both bus number and resource have been assigned + // Do any post initialization. + // + DEBUG ((DEBUG_ERROR, "PCI Platform Post-Initialization (After resource alloction)\n")); + mPciPrivateData.PciEnumerationPhase = EfiPciEnumerationResourceAssigned; + for (i = 0 ; i < MaxIIO ; i++) { + if (mIioUds->IioUdsPtr->PlatformData.IIO_resource[i].Valid) { + for(Stack = 0; Stack < MAX_IIO_STACK; Stack ++) { + PciTreeTraverse (mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[i].StackBus[Stack]); + } + } + } + PciPlatformPostInit (); + break; + + default: + return EFI_UNSUPPORTED; + } + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatformHooks.h b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatformHooks.h new file mode 100644 index 0000000000..8d4734bb80 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciPlatformHooks.h @@ -0,0 +1,30 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef PCI_PLATFORM_HOOKS_H_ +#define PCI_PLATFORM_HOOKS_H_ + +VOID +ChipsetCallback ( + IN EFI_HANDLE RootBridgeHandle, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_ENUMERATION_PHASE Phase, + EFI_PCI_CALLBACK_CONTEXT *Context + ); + +EFI_STATUS +PciTreeTraverse ( + IN UINT8 StartBus + ); + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciSupportLib.c b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciSupportLib.c new file mode 100644 index 0000000000..dbd744b9d2 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciSupportLib.c @@ -0,0 +1,109 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "PiDxe.h" +#include +#include +#include +#include +#include +#include "IndustryStandard/Pci.h" +#include "PciSupportLib.h" + +PCIE_STACK mPcieStack; + + +/** + + This routine is used to check whether the pci device is present + + @retval None + +**/ +BOOLEAN +IsPciDevicePresent ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, + PCI_TYPE00 *Pci, + UINT8 Bus, + UINT8 Device, + UINT8 Func + ) +// TODO: PciRootBridgeIo - add argument and description to function comment +// TODO: Pci - add argument and description to function comment +// TODO: Bus - add argument and description to function comment +// TODO: Device - add argument and description to function comment +// TODO: Func - add argument and description to function comment +// TODO: EFI_SUCCESS - add return value to function comment +// TODO: EFI_NOT_FOUND - add return value to function comment +{ + UINT64 Address; + UINT32 Dummy; + EFI_STATUS Status; + + Dummy=0xFFFFFFFF; + // + // Create PCI address map in terms of Bus, Device and Func + // + Address = EFI_PCI_ADDRESS (Bus, Device, Func, 0); + + // + // Read the Vendor Id register + // + Status = PciRootBridgeIo->Pci.Read ( + PciRootBridgeIo, + EfiPciWidthUint32, + Address, + 1, + Pci + ); + if ((Pci->Hdr).VendorId == 0xffff) { + /// PCIe card could have been assigned a temporary bus number. + /// An write cycle can be used to try to rewrite the Bus number in the card + /// Try to write the Vendor Id register, and recheck if the card is present. + Status = PciRootBridgeIo->Pci.Write( + PciRootBridgeIo, + EfiPciWidthUint32, + Address, + 1, + &Dummy + ); + + // Retry the previous read after the PCI cycle has been tried. + Status = PciRootBridgeIo->Pci.Read ( + PciRootBridgeIo, + EfiPciWidthUint32, + Address, + 1, + Pci + ); + } + + if (!EFI_ERROR (Status) && (Pci->Hdr).VendorId != 0xffff) { + + // + // Read the entire config header for the device + // + + Status = PciRootBridgeIo->Pci.Read ( + PciRootBridgeIo, + EfiPciWidthUint32, + Address, + sizeof (PCI_TYPE00) / sizeof (UINT32), + Pci + ); + + return TRUE; + } + + return FALSE; +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciSupportLib.h b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciSupportLib.h new file mode 100644 index 0000000000..78fd013498 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Pci/PciPlatform/PciSupportLib.h @@ -0,0 +1,50 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _EFI_PCI_SUPPORT_H_ +#define _EFI_PCI_SUPPORT_H_ + +#include + +#include + +typedef struct { + UINT8 PcieCapPtr; + UINT8 Function; + UINT8 Device; + UINT8 Bus; + UINT16 PcieLnkCap; + UINT16 PcieDevCap; + //Added to Support AtomicOp Request-->Start + UINT16 PcieDevCap2; + //Added to Support AtomicOp Request-->End +} PCIE_CAP_INFO; + +typedef struct { + INTN Top; + PCIE_CAP_INFO PcieCapInfo[FixedPcdGet32(PcdMaxNestedLevel)]; +} PCIE_STACK; + +extern PCIE_STACK mPcieStack; + +BOOLEAN +IsPciDevicePresent ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo, + PCI_TYPE00 *Pci, + UINT8 Bus, + UINT8 Device, + UINT8 Func + ); + + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/PlatPkg.dec b/Platform/Intel/PurleyOpenBoardPkg/PlatPkg.dec new file mode 100644 index 0000000000..221269e1f4 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/PlatPkg.dec @@ -0,0 +1,146 @@ +### @file +# +# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +### + +[Defines] + DEC_SPECIFICATION = 0x00010005 + PACKAGE_NAME = PlatPkg + PACKAGE_GUID = 454FB726-6A01-49ce-B222-749CD093D3C5 + PACKAGE_VERSION = 0.91 + +[Includes] + Include + +[Guids] + gEfiMemoryConfigDataGuid = { 0x80dbd530, 0xb74c, 0x4f11, { 0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31 } } + gCpPlatFlashTokenSpaceGuid = { 0xc9c39664, 0x96dd, 0x4c5c, { 0xaf, 0xd7, 0xcd, 0x65, 0x76, 0x29, 0xcf, 0xb0 } } + gOemSkuTokenSpaceGuid = { 0x9e37d253, 0xabf8, 0x4985, { 0x8e, 0x23, 0xba, 0xca, 0x10, 0x39, 0x56, 0x13 } } + gEfiIpmiPkgTokenSpaceGuid = { 0xe96431d, 0xc68e, 0x4212, { 0xa1, 0x70, 0x16, 0xa6, 0x8, 0x55, 0x12, 0xc6 } } + +[Ppis] + gEfiPeiSystemBoardPpiGuid = { 0xc8d85e8c, 0xdc1c, 0x4f8c, { 0xad, 0xa7, 0x58, 0xc1, 0xd1, 0x07, 0xa3, 0x04 } } + gEfiSiliconRcHobsReadyPpi = { 0xecf149b5, 0xbf4e, 0x4ac8, { 0x8a, 0x8c, 0xce, 0x87, 0xcb, 0xac, 0x93, 0xd3 } } + +[Protocols] + gEfiPciIovPlatformProtocolGuid = { 0xf3a4b484, 0x9b26, 0x4eea, { 0x90, 0xe5, 0xa2, 0x06, 0x54, 0x0c, 0xa5, 0x25 } } + gEfiDxeSystemBoardProtocolGuid = { 0xa57c1118, 0x6afc, 0x46d2, { 0xba, 0xe6, 0x92, 0x92, 0x62, 0xd3, 0xeb, 0x1e } } + +[PcdsFixedAtBuild] + + gPlatformTokenSpaceGuid.PcdCmosDebugPrintLevelReg|0x4C|UINT8|0x30000032 + + # Choose the default serial debug message level when CMOS is bad; in the later BIOS phase, the setup default is applied + # 0 - Disable; 1 - Minimum; 2 - Normal; 3 - Max + gPlatformTokenSpaceGuid.PcdSerialDbgLvlAtBadCmos|0x1|UINT8|0x30000033 + +[PcdsDynamicEx] + gPlatformTokenSpaceGuid.PcdDfxAdvDebugJumper|FALSE|BOOLEAN|0x6000001D + + ## This value is used to save memory address of MRC data structure. + gPlatformTokenSpaceGuid.PcdSyshostMemoryAddress|0x00000000|UINT64|0x30000040 + + gOemSkuTokenSpaceGuid.PcdForceTo1SConfigMode|FALSE|BOOLEAN|0x00000205 + + gOemSkuTokenSpaceGuid.PcdAcpiGnvsAddress|0|UINT64|0x00000206 + + gOemSkuTokenSpaceGuid.PcdOemSkuUplinkPortIndex|0xFF|UINT8|0x00000207 + + gOemSkuTokenSpaceGuid.PcdMemTsegSize|0x0|UINT32|0x00000208 + gOemSkuTokenSpaceGuid.PcdMemIedSize|0x0|UINT32|0x00000209 + + gOemSkuTokenSpaceGuid.PcdUsb20OverCurrentMappings|0|UINT64|0x0000020A + gOemSkuTokenSpaceGuid.PcdUsb30OverCurrentMappings|0|UINT64|0x0000020B + + gOemSkuTokenSpaceGuid.PcdIioBifurcationTable|0|UINT64|0x0000020C + gOemSkuTokenSpaceGuid.PcdIioBifurcationTableEntries|0|UINT8|0x0000020D + gOemSkuTokenSpaceGuid.PcdIioSlotTable|0|UINT64|0x0000020E + gOemSkuTokenSpaceGuid.PcdIioSlotTableEntries|0|UINT8|0x0000020F + + gOemSkuTokenSpaceGuid.PcdAllLanesEparamTable|0|UINT64|0x00000210 + gOemSkuTokenSpaceGuid.PcdAllLanesEparamTableSize|0|UINT32|0x00000211 + gOemSkuTokenSpaceGuid.PcdPerLaneEparamTable|0|UINT64|0x00000212 + gOemSkuTokenSpaceGuid.PcdPerLaneEparamTableSize|0|UINT32|0x00000213 + gOemSkuTokenSpaceGuid.PcdBoardTypeBitmask|0|UINT32|0x00000214 + + gOemSkuTokenSpaceGuid.PcdSetupData|{0x0}|SYSTEM_CONFIGURATION|0x000F0001 { # SYSTEM_CONFIGURATION <== PLATFORM_SETUP_VARIABLE_NAME|gEfiSetupVariableGuid + + Guid/SetupVariable.h + + MdePkg/MdePkg.dec + PurleyRcPkg/RcPkg.dec + PurleySktPkg/SocketPkg.dec + LewisburgPkg/PchRcPkg.dec + PurleyOpenBoardPkg/PlatPkg.dec + } + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData|{0x0}|PCH_RC_CONFIGURATION|0x000F0002 { # PCH_RC_CONFIGURATION <== PCH_RC_CONFIGURATION_NAME|gEfiPchRcVariableGuid + + Guid/PchRcVariable.h + + MdePkg/MdePkg.dec + PurleyRcPkg/RcPkg.dec + PurleySktPkg/SocketPkg.dec + LewisburgPkg/PchRcPkg.dec + PurleyOpenBoardPkg/PlatPkg.dec + } + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData|{0x0}|SOCKET_IIO_CONFIGURATION|0x000F0003 { # SOCKET_IIO_CONFIGURATION <== SOCKET_IIO_CONFIGURATION_NAME|gEfiSocketIioVariableGuid + + Guid/SocketIioVariable.h + + MdePkg/MdePkg.dec + PurleyRcPkg/RcPkg.dec + PurleySktPkg/SocketPkg.dec + } + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData|{0x0}|SOCKET_COMMONRC_CONFIGURATION|0x000F0004 { # SOCKET_COMMONRC_CONFIGURATION <== SOCKET_COMMONRC_CONFIGURATION_NAME|gEfiSocketCommonRcVariableGuid + + Guid/SocketCommonRcVariable.h + + MdePkg/MdePkg.dec + PurleyRcPkg/RcPkg.dec + PurleySktPkg/SocketPkg.dec + } + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData|{0x0}|SOCKET_MP_LINK_CONFIGURATION|0x000F0005 { # SOCKET_MP_LINK_CONFIGURATION <== SOCKET_MP_LINK_CONFIGURATION_NAME|gEfiSocketMpLinkVariableGuid + + Guid/SocketMpLinkVariable.h + + MdePkg/MdePkg.dec + PurleyRcPkg/RcPkg.dec + PurleySktPkg/SocketPkg.dec + } + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData|{0x0}|SOCKET_MEMORY_CONFIGURATION|0x000F0006 { # SOCKET_MEMORY_CONFIGURATION <== SOCKET_MEMORY_CONFIGURATION_NAME|gEfiSocketMemoryVariableGuid + + Guid/SocketMemoryVariable.h + + MdePkg/MdePkg.dec + PurleyRcPkg/RcPkg.dec + PurleySktPkg/SocketPkg.dec + } + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData|{0x0}|SOCKET_POWERMANAGEMENT_CONFIGURATION|0x000F0007 { # SOCKET_POWERMANAGEMENT_CONFIGURATION <== SOCKET_POWERMANAGEMENT_CONFIGURATION_NAME|gEfiSocketPowermanagementVarGuid + + Guid/SocketPowermanagementVariable.h + + MdePkg/MdePkg.dec + PurleyRcPkg/RcPkg.dec + PurleySktPkg/SocketPkg.dec + } + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData|{0x0}|SOCKET_PROCESSORCORE_CONFIGURATION|0x000F0008 { # SOCKET_PROCESSORCORE_CONFIGURATION <== SOCKET_PROCESSORCORE_CONFIGURATION_NAME|gEfiSocketProcessorCoreVarGuid + + Guid/SocketProcessorCoreVariable.h + + MdePkg/MdePkg.dec + PurleyRcPkg/RcPkg.dec + PurleySktPkg/SocketPkg.dec + } + +[PcdsDynamic, PcdsDynamicEx] + gEfiIpmiPkgTokenSpaceGuid.PcdIpmiKcsTimeoutPeriod|5000|UINT64|0x90000020 + gEfiIpmiPkgTokenSpaceGuid.PcdIpmiBmcSlaveAddress|0x20|UINT8|0x90000021 diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/IioUdsDataDxe/IioUdsDataDxe.c b/Platform/Intel/PurleyOpenBoardPkg/Policy/IioUdsDataDxe/IioUdsDataDxe.c new file mode 100644 index 0000000000..132731a38c --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/IioUdsDataDxe/IioUdsDataDxe.c @@ -0,0 +1,92 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// +// Statements that include other files +// +#include "IioUdsDataDxe.h" + +#define STRING_WIDTH_40 40 + +// +// Instantiation of Driver's private data. +// +EFI_IIO_UDS_DRIVER_PRIVATE mIioUdsPrivateData; +IIO_UDS *IioUdsData; // Pointer to UDS in Allocated Memory Pool + +/** + + Entry point for the driver. + + @param ImageHandle - Image Handle. + @param SystemTable - EFI System Table. + + @retval EFI_SUCCESS - Function has completed successfully. + +**/ +EFI_STATUS +EFIAPI +IioUdsDataInit ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HOB_GUID_TYPE *GuidHob; + IIO_UDS *UdsHobPtr; + EFI_GUID UniversalDataGuid = IIO_UNIVERSAL_DATA_GUID; + + // + // Time to get the IIO_UDS HOB data stored in the PEI driver + // + GuidHob = GetFirstGuidHob (&UniversalDataGuid); + ASSERT (GuidHob != NULL); + if (GuidHob == NULL) { + return EFI_NOT_FOUND; + } + UdsHobPtr = GET_GUID_HOB_DATA(GuidHob); + + // + // Allocate Memory Pool for Universal Data Storage so that protocol can expose it + // + Status = gBS->AllocatePool ( EfiReservedMemoryType, sizeof (IIO_UDS), (VOID **) &IioUdsData ); + ASSERT_EFI_ERROR (Status); + + // + // Initialize the Pool Memory with the data from the Hand-Off-Block + // + CopyMem(IioUdsData, UdsHobPtr, sizeof(IIO_UDS)); + + // + // Build the IIO_UDS driver instance for protocol publishing + // + ZeroMem (&mIioUdsPrivateData, sizeof (mIioUdsPrivateData)); + + mIioUdsPrivateData.Signature = EFI_IIO_UDS_DRIVER_PRIVATE_SIGNATURE; + mIioUdsPrivateData.IioUds.IioUdsPtr = IioUdsData; + mIioUdsPrivateData.IioUds.EnableVc = NULL; + + // + // Install the IioUds Protocol. + // + Status = gBS->InstallMultipleProtocolInterfaces ( + &mIioUdsPrivateData.Handle, + &gEfiIioUdsProtocolGuid, + &mIioUdsPrivateData.IioUds, + NULL + ); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/IioUdsDataDxe/IioUdsDataDxe.h b/Platform/Intel/PurleyOpenBoardPkg/Policy/IioUdsDataDxe/IioUdsDataDxe.h new file mode 100644 index 0000000000..9453ac618d --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/IioUdsDataDxe/IioUdsDataDxe.h @@ -0,0 +1,87 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PLATFORM_TYPES_H_ +#define _PLATFORM_TYPES_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + + + + +#define EFI_PLATFORM_TYPE_DRIVER_PRIVATE_SIGNATURE SIGNATURE_32 ('T', 'Y', 'P', 'P') +#define EFI_IIO_UDS_DRIVER_PRIVATE_SIGNATURE SIGNATURE_32 ('S', 'D', 'U', 'I') + + +typedef unsigned char BYTE; //!< 8-bit quantities +typedef unsigned short WORD; //!< 16-bit quantities +typedef unsigned long DWORD; //!< 32-bit quantities + +typedef enum +{ +#ifndef SUCCESS + SUCCESS = 0x00, //!< Packet it good! .data[] is valid +#endif + DEFER = 0x01, //!< Packet is defered. .data[1] = BufID + W_EARLY_NACK = 0x02, //!< Packet mastered on the SMBus by the MCU was NACKed earlier than expected + NOT_RESP = 0x03, //!< Packet mastered on the SMBus by the MCU was NACKed during the address byte + BUFFER_OVERRUN = 0x04, //!< Too many BYTE s were stuffed into the buffer. + NO_BUFFER = 0x05, //!< All the buffers are used + INVALID_BUF = 0x06, //!< Command passed a buffer id that was not in range + BUF_NOT_IN_QUEUE = 0x07, //!< Command passed a buffer id is not being used. + ARBITRATION_LOST = 0x08, //!< While the MCU was mastering a packet on the SMBus it lost arbitration. + TIMEOUT = 0x0B, //!< SMBus timed out. + CHECKSUM_ERR = 0x0C, //!< Operation encountered a checksum mismatch + DATA_NACK = 0x0D, //!< Still don't know what these mean? + BUS_ERR = 0x0E, //!< ? + FAIL = 0x0F, //!< Generic error + BUSY = 0x10, //!< ? + R_EARLY_NACK = 0x11, //!< ? + INVALID_LCD_COL_OFF = 0x12, //!< The cursor on the LCD was set to a column that was out of range. + INVALID_LCD_ROW_OFF = 0x13, //!< The cursor on the LCD was set to a row that was out of range. + INVALID_CK410_SEL = 0x14, //!< ? + CMD_NOT_SUPPORTED = 0x15, //!< This command is not supported + MORE_DATA_AVAILABLE = 0x16, //!< Do the command again to get more data +} STATUS; + +typedef struct { + BYTE byte_count; + STATUS status; + BYTE data[31]; +} BUFFER_RSLT; + +typedef struct { + UINTN Signature; + EFI_HANDLE Handle; // Handle for protocol this driver installs on + EFI_IIO_UDS_PROTOCOL IioUds; // Policy protocol this driver installs +} EFI_IIO_UDS_DRIVER_PRIVATE; + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/IioUdsDataDxe/IioUdsDataDxe.inf b/Platform/Intel/PurleyOpenBoardPkg/Policy/IioUdsDataDxe/IioUdsDataDxe.inf new file mode 100644 index 0000000000..74a2453bbd --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/IioUdsDataDxe/IioUdsDataDxe.inf @@ -0,0 +1,44 @@ +### @file +# +# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +### + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = IioUdsDataDxe + FILE_GUID = 036125ED-DD4C-4BF7-AC8D-83FE11CDD5DB + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = IioUdsDataInit + +[Sources] + IioUdsDataDxe.c + IioUdsDataDxe.h + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + PurleyOpenBoardPkg/PlatPkg.dec + PurleySktPkg/SocketPkg.dec + PurleyRcPkg/RcPkg.dec + LewisburgPkg/PchRcPkg.dec + +[LibraryClasses] + HobLib + BaseMemoryLib + UefiDriverEntryPoint + +[Protocols] + gEfiIioUdsProtocolGuid + +[Depex] + TRUE diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicyInitLib/SiliconPolicyInitLib.c b/Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicyInitLib/SiliconPolicyInitLib.c new file mode 100644 index 0000000000..429bda6ae4 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicyInitLib/SiliconPolicyInitLib.c @@ -0,0 +1,136 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include + +/** + Performs silicon pre-mem policy initialization. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a PPI, etc. + + The returned data must be used as input data for SiliconPolicyDonePreMem(), + and SiliconPolicyUpdateLib.SiliconPolicyUpdatePreMem(). + + 1) In FSP path, the input Policy should be FspmUpd. + Value of FspmUpd has been initialized by FSP binary default value. + Only a subset of FspmUpd needs to be updated for different silicon sku. + The return data is same FspmUpd. + + 2) In non-FSP path, the input policy could be NULL. + The return data is the initialized policy. + + @param[in, out] Policy Pointer to policy. + + @return the initialized policy. +**/ +VOID * +EFIAPI +SiliconPolicyInitPreMem ( + IN OUT VOID *Policy OPTIONAL + ) +{ + EFI_STATUS Status; + PCH_POLICY_PPI *PchPolicyPpi; + + // + // Call PchCreatePolicyDefaults to initialize platform policy structure + // and get all intel default policy settings. + // + Status = PchCreatePolicyDefaults (&PchPolicyPpi); + ASSERT_EFI_ERROR (Status); + + return PchPolicyPpi; +} + +/* + The silicon pre-mem policy is finalized. + Silicon code can do initialization based upon the policy data. + + The input Policy must be returned by SiliconPolicyInitPreMem(). + + @param[in] Policy Pointer to policy. + + @retval RETURN_SUCCESS The policy is handled consumed by silicon code. +*/ +RETURN_STATUS +EFIAPI +SiliconPolicyDonePreMem ( + IN VOID *Policy + ) +{ + EFI_STATUS Status; + + // + // Install PchPolicyPpi. + // While installed, RC assumes the Policy is ready and finalized. So please + // update and override any setting before calling this function. + // + Status = PchInstallPolicyPpi (Policy); + ASSERT_EFI_ERROR (Status); + + return Status; +} + +/** + Performs silicon post-mem policy initialization. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a PPI, etc. + + The returned data must be used as input data for SiliconPolicyDonePostMem(), + and SiliconPolicyUpdateLib.SiliconPolicyUpdatePostMem(). + + 1) In FSP path, the input Policy should be FspsUpd. + Value of FspsUpd has been initialized by FSP binary default value. + Only a subset of FspsUpd needs to be updated for different silicon sku. + The return data is same FspsUpd. + + 2) In non-FSP path, the input policy could be NULL. + The return data is the initialized policy. + + @param[in, out] Policy Pointer to policy. + + @return the initialized policy. +**/ +VOID * +EFIAPI +SiliconPolicyInitPostMem ( + IN OUT VOID *Policy OPTIONAL + ) +{ + return Policy; +} + +/* + The silicon post-mem policy is finalized. + Silicon code can do initialization based upon the policy data. + + The input Policy must be returned by SiliconPolicyInitPostMem(). + + @param[in] Policy Pointer to policy. + + @retval RETURN_SUCCESS The policy is handled consumed by silicon code. +*/ +RETURN_STATUS +EFIAPI +SiliconPolicyDonePostMem ( + IN VOID *Policy + ) +{ + return RETURN_SUCCESS; +} \ No newline at end of file diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicyInitLib/SiliconPolicyInitLib.inf b/Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicyInitLib/SiliconPolicyInitLib.inf new file mode 100644 index 0000000000..69c32d39bf --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicyInitLib/SiliconPolicyInitLib.inf @@ -0,0 +1,47 @@ +### @file +# +# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +### + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SiliconPolicyInitLib + FILE_GUID = B494DF39-A5F8-48A1-B2D0-EF523AD91C55 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + LIBRARY_CLASS = SiliconPolicyInitLib + +[Sources] + SiliconPolicyInitLib.c + +################################################################################ +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +################################################################################ +[Packages] + MdePkg/MdePkg.dec + LewisburgPkg/PchRcPkg.dec + PurleySktPkg/SocketPkg.dec + +[LibraryClasses] + BaseMemoryLib + BaseLib + DebugLib + DebugPrintErrorLevelLib + HobLib + IoLib + MemoryAllocationLib + PeiServicesLib + PchPolicyLib + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicyUpdateLib/PchPolicyUpdateUsb.c b/Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicyUpdateLib/PchPolicyUpdateUsb.c new file mode 100644 index 0000000000..a2780dcd5f --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicyUpdateLib/PchPolicyUpdateUsb.c @@ -0,0 +1,105 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// +// EDK and EDKII have different GUID formats +// +#include +#include +#include "PlatformHost.h" +#include +#include +#include + + +VOID +UpdatePchUsbConfig ( + IN PCH_USB_CONFIG *PchUsbConfig, + IN SYSTEM_CONFIGURATION *SetupVariables, + IN PCH_RC_CONFIGURATION *PchRcVariables, + IN VOID *Usb20OverCurrentMappings, + IN VOID *Usb30OverCurrentMappings + ) +/*++ + +Routine Description: + + This function performs PCH USB Platform Policy initialzation + +Arguments: + PchUsbConfig Pointer to PCH_USB_CONFIG data buffer + SetupVariables Pointer to Setup variable + PlatformType PlatformType specified + PlatformFlavor PlatformFlavor specified + BoardType BoardType specified + +Returns: + +--*/ +{ + UINTN PortIndex; + + PchUsbConfig->UsbPrecondition = PchRcVariables->UsbPrecondition; + + for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb2PortNum (); PortIndex++) { + if (PchRcVariables->PchUsbHsPort[PortIndex] == 1) { + PchUsbConfig->PortUsb20[PortIndex].Enable = TRUE; + } else { + PchUsbConfig->PortUsb20[PortIndex].Enable = FALSE; + } + } + for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex++) { + if (PchRcVariables->PchUsbSsPort[PortIndex] == 1) { + PchUsbConfig->PortUsb30[PortIndex].Enable = TRUE; + } else { + PchUsbConfig->PortUsb30[PortIndex].Enable = FALSE; + } + } + + // + // xDCI (USB device) related settings from setup variable + // + if(PchRcVariables->PchXdciSupport == 1) { + PchUsbConfig->XdciConfig.Enable= TRUE; + } else { + PchUsbConfig->XdciConfig.Enable= FALSE; + } + + // + // XHCI USB Over Current Pins disabled, update it based on setup option. + // + PchUsbConfig->XhciOcMapEnabled = PchRcVariables->XhciOcMapEnabled; + + // + // XHCI Wake On USB configured based on user input through setup option + // + PchUsbConfig->XhciWakeOnUsb = SetupVariables->XhciWakeOnUsbEnabled; + // + // XHCI option to disable MSIs + // + PchUsbConfig->XhciDisMSICapability = PchRcVariables->XhciDisMSICapability; + + // + // Platform Board programming per the layout of each port. + // + // OC Map for USB2 Ports + for (PortIndex=0;PortIndexPortUsb20[PortIndex].OverCurrentPin = (UINT8)((PCH_USB_OVERCURRENT_PIN *)Usb20OverCurrentMappings)[PortIndex]; + } + + // OC Map for USB3 Ports + for (PortIndex=0;PortIndexPortUsb30[PortIndex].OverCurrentPin = (UINT8)((PCH_USB_OVERCURRENT_PIN *)Usb30OverCurrentMappings)[PortIndex]; + } + +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLib.c b/Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLib.c new file mode 100644 index 0000000000..53466d0c1b --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLib.c @@ -0,0 +1,665 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include + +#include "Guid/SetupVariable.h" +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// +// Haddock Creek +// +#define DIMM_SMB_SPD_P0C0D0_HC 0xA2 +#define DIMM_SMB_SPD_P0C0D1_HC 0xA0 +#define DIMM_SMB_SPD_P0C1D0_HC 0xA6 +#define DIMM_SMB_SPD_P0C1D1_HC 0xA4 +#define DIMM_SMB_SPD_P0C0D2_HC 0xAA +#define DIMM_SMB_SPD_P0C1D2_HC 0xA8 + +// +// Sawtooth Peak +// Single SPD EEPROM at 0xA2 serves both C0D0 and C1D0 (LPDDR is 1DPC only) +// +#define DIMM_SMB_SPD_P0C0D0_STP 0xA2 +#define DIMM_SMB_SPD_P0C0D1_STP 0xA0 +#define DIMM_SMB_SPD_P0C1D0_STP 0xA2 +#define DIMM_SMB_SPD_P0C1D1_STP 0xA0 + +// +// Aden Hills +// DDR4 System (1DPC) +// +#define DIMM_SMB_SPD_P0C0D0_AH 0xA0 +#define DIMM_SMB_SPD_P0C0D1_AH 0xA4 +#define DIMM_SMB_SPD_P0C1D0_AH 0xA2 +#define DIMM_SMB_SPD_P0C1D1_AH 0xA6 + + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusHCRsvdAddresses[] = { + DIMM_SMB_SPD_P0C0D0_HC, + DIMM_SMB_SPD_P0C0D1_HC, + DIMM_SMB_SPD_P0C1D0_HC, + DIMM_SMB_SPD_P0C1D1_HC +}; + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusSTPRsvdAddresses[] = { + DIMM_SMB_SPD_P0C0D0_STP, + DIMM_SMB_SPD_P0C0D1_STP, + DIMM_SMB_SPD_P0C1D0_STP, + DIMM_SMB_SPD_P0C1D1_STP +}; + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusAHRsvdAddresses[] = { + DIMM_SMB_SPD_P0C0D0_AH, + DIMM_SMB_SPD_P0C0D1_AH, + DIMM_SMB_SPD_P0C1D0_AH, + DIMM_SMB_SPD_P0C1D1_AH +}; + +VOID +UpdatePchUsbConfig ( + IN PCH_USB_CONFIG *PchUsbConfig, + IN SYSTEM_CONFIGURATION *SetupVariables, + IN PCH_RC_CONFIGURATION *PchRcVariables, + IN VOID *Usb20OverCurrentMappings, + IN VOID *Usb30OverCurrentMappings + ); + +static +VOID +InstallPlatformVerbTables ( + IN UINTN CodecType + ) +{ + +} + +EFI_STATUS +EFIAPI +UpdatePeiPchPolicy ( + IN OUT PCH_POLICY_PPI *PchPolicy + ) +/*++ + +Routine Description: + + This function performs PCH PEI Policy initialzation. + +Arguments: + + PchPolicy The PCH Policy PPI instance + +Returns: + + EFI_SUCCESS The PPI is installed and initialized. + EFI ERRORS The PPI is not successfully installed. + EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver + +--*/ +{ + UINT8 Index; + UINTN LpcBaseAddress; + UINT8 MaxSataPorts; + UINT8 *SmBusReservedTable; + UINT8 SmBusReservedNum; + PCH_USB_OVERCURRENT_PIN *Usb20OverCurrentMappings=NULL; + PCH_USB_OVERCURRENT_PIN *Usb30OverCurrentMappings=NULL; + UINT8 VTdSupport; + SYSTEM_CONFIGURATION *SetupVariables; + PCH_RC_CONFIGURATION *PchRcVariables; + + DEBUG((EFI_D_ERROR, "platform common UpdatePeiPchPolicy entry\n")); + + SetupVariables = PcdGetPtr(PcdSetupData); + PchRcVariables = PcdGetPtr(PcdPchRcConfigurationData); + + LpcBaseAddress = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + + PchPolicy->Port80Route = PchRcVariables->IchPort80Route; + + // + // DeviceEnables + // + if (PchIsGbeAvailable ()) { + PchPolicy->LanConfig.Enable = TRUE; + PchPolicy->LanConfig.K1OffEnable = PchRcVariables->PchLanK1Off; + } else { + PchPolicy->LanConfig.Enable = FALSE; + } + + PchPolicy->SataConfig.Enable = PchRcVariables->PchSata; + + PchPolicy->sSataConfig.Enable = PchRcVariables->PchsSata; + PchPolicy->SmbusConfig.Enable = TRUE; + // + // CLOCKRUN in LPC has to be disabled: + // - if a device is connected to LPC0 + // - for LBG A0 stepping + // + PchPolicy->PmConfig.PciClockRun = FALSE; + PchPolicy->PchConfig.Crid = PchRcVariables->PchCrid; + PchPolicy->PchConfig.Serm = PchRcVariables->PchSerm; + + + // + // SMBUS reserved addresses + // + SmBusReservedTable = NULL; + SmBusReservedNum = 0; + PchPolicy->SmbusConfig.SmbusIoBase = PCH_SMBUS_BASE_ADDRESS; + SmBusReservedTable = mSmbusSTPRsvdAddresses; + SmBusReservedNum = sizeof (mSmbusSTPRsvdAddresses); + + if (SmBusReservedTable != NULL) { + PchPolicy->SmbusConfig.NumRsvdSmbusAddresses = SmBusReservedNum; + CopyMem ( + PchPolicy->SmbusConfig.RsvdSmbusAddressTable, + SmBusReservedTable, + SmBusReservedNum + ); + } + + // + // SATA Config + // + PchPolicy->SataConfig.SataMode = PchRcVariables->SataInterfaceMode; + MaxSataPorts = GetPchMaxSataPortNum (); + + for (Index = 0; Index < MaxSataPorts; Index++) { + if (PchRcVariables->SataTestMode == TRUE) + { + PchPolicy->SataConfig.PortSettings[Index].Enable = TRUE; + } else { + PchPolicy->SataConfig.PortSettings[Index].Enable = PchRcVariables->SataPort[Index]; + } + PchPolicy->SataConfig.PortSettings[Index].HotPlug = PchRcVariables->SataHotPlug[Index]; + PchPolicy->SataConfig.PortSettings[Index].SpinUp = PchRcVariables->SataSpinUp[Index]; + PchPolicy->SataConfig.PortSettings[Index].External = PchRcVariables->SataExternal[Index]; + PchPolicy->SataConfig.PortSettings[Index].DevSlp = PchRcVariables->PxDevSlp[Index]; + PchPolicy->SataConfig.PortSettings[Index].EnableDitoConfig = PchRcVariables->EnableDitoConfig[Index]; + PchPolicy->SataConfig.PortSettings[Index].DmVal = PchRcVariables->DmVal[Index]; + PchPolicy->SataConfig.PortSettings[Index].DitoVal = PchRcVariables->DitoVal[Index]; + PchPolicy->SataConfig.PortSettings[Index].SolidStateDrive = PchRcVariables->SataType[Index]; + } + + if (PchPolicy->SataConfig.SataMode == PchSataModeRaid) { + PchPolicy->SataConfig.Rst.RaidAlternateId = PchRcVariables->SataAlternateId; + PchPolicy->SataConfig.Rst.EfiRaidDriverLoad = PchRcVariables->SataRaidLoadEfiDriver; + } + PchPolicy->SataConfig.Rst.Raid0 = PchRcVariables->SataRaidR0; + PchPolicy->SataConfig.Rst.Raid1 = PchRcVariables->SataRaidR1; + PchPolicy->SataConfig.Rst.Raid10 = PchRcVariables->SataRaidR10; + PchPolicy->SataConfig.Rst.Raid5 = PchRcVariables->SataRaidR5; + PchPolicy->SataConfig.Rst.Irrt = PchRcVariables->SataRaidIrrt; + PchPolicy->SataConfig.Rst.OromUiBanner = PchRcVariables->SataRaidOub; + PchPolicy->SataConfig.Rst.HddUnlock = PchRcVariables->SataHddlk; + PchPolicy->SataConfig.Rst.LedLocate = PchRcVariables->SataLedl; + PchPolicy->SataConfig.Rst.IrrtOnly = PchRcVariables->SataRaidIooe; + PchPolicy->SataConfig.Rst.SmartStorage = PchRcVariables->SataRaidSrt; + PchPolicy->SataConfig.Rst.OromUiDelay = PchRcVariables->SataRaidOromDelay; + + PchPolicy->SataConfig.EnclosureSupport = TRUE; + + PchPolicy->SataConfig.SalpSupport = PchRcVariables->SataSalp; + PchPolicy->SataConfig.TestMode = PchRcVariables->SataTestMode; + + for (Index = 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) { + if ((PchRcVariables->PchSata == TRUE) && (PchRcVariables->SataInterfaceMode == PchSataModeRaid)) { + PchPolicy->SataConfig.RstPcieStorageRemap[Index].Enable = PchRcVariables->RstPcieStorageRemap[Index]; + PchPolicy->SataConfig.RstPcieStorageRemap[Index].RstPcieStoragePort = PchRcVariables->RstPcieStorageRemapPort[Index]; + } else { + PchPolicy->SataConfig.RstPcieStorageRemap[Index].Enable = FALSE; + } + } + + // + // sSATA Config + // + PchPolicy->sSataConfig.SataMode = PchRcVariables->sSataInterfaceMode; + MaxSataPorts = GetPchMaxsSataPortNum (); + + for (Index = 0; Index < MaxSataPorts; Index++) { + if (PchRcVariables->sSataTestMode == TRUE) + { + PchPolicy->sSataConfig.PortSettings[Index].Enable = TRUE; + } else { + PchPolicy->sSataConfig.PortSettings[Index].Enable = PchRcVariables->sSataPort[Index]; + } + PchPolicy->sSataConfig.PortSettings[Index].HotPlug = PchRcVariables->sSataHotPlug[Index]; + PchPolicy->sSataConfig.PortSettings[Index].SpinUp = PchRcVariables->sSataSpinUp[Index]; + PchPolicy->sSataConfig.PortSettings[Index].External = PchRcVariables->sSataExternal[Index]; + PchPolicy->sSataConfig.PortSettings[Index].DevSlp = PchRcVariables->sPxDevSlp[Index]; + PchPolicy->sSataConfig.PortSettings[Index].EnableDitoConfig = PchRcVariables->sEnableDitoConfig[Index]; + PchPolicy->sSataConfig.PortSettings[Index].DmVal = PchRcVariables->sDmVal[Index]; + PchPolicy->sSataConfig.PortSettings[Index].DitoVal = PchRcVariables->sDitoVal[Index]; + PchPolicy->sSataConfig.PortSettings[Index].SolidStateDrive = PchRcVariables->sSataType[Index]; + } + + if (PchPolicy->sSataConfig.SataMode == PchSataModeRaid) { + PchPolicy->sSataConfig.Rst.RaidAlternateId = PchRcVariables->sSataAlternateId; + PchPolicy->sSataConfig.Rst.EfiRaidDriverLoad = PchRcVariables->sSataRaidLoadEfiDriver; + } + PchPolicy->sSataConfig.Rst.Raid0 = PchRcVariables->sSataRaidR0; + PchPolicy->sSataConfig.Rst.Raid1 = PchRcVariables->sSataRaidR1; + PchPolicy->sSataConfig.Rst.Raid10 = PchRcVariables->sSataRaidR10; + PchPolicy->sSataConfig.Rst.Raid5 = PchRcVariables->sSataRaidR5; + PchPolicy->sSataConfig.Rst.Irrt = PchRcVariables->sSataRaidIrrt; + PchPolicy->sSataConfig.Rst.OromUiBanner = PchRcVariables->sSataRaidOub; + PchPolicy->sSataConfig.Rst.HddUnlock = PchRcVariables->sSataHddlk; + PchPolicy->sSataConfig.Rst.LedLocate = PchRcVariables->sSataLedl; + PchPolicy->sSataConfig.Rst.IrrtOnly = PchRcVariables->sSataRaidIooe; + PchPolicy->sSataConfig.Rst.SmartStorage = PchRcVariables->sSataRaidSrt; + PchPolicy->sSataConfig.Rst.OromUiDelay = PchRcVariables->sSataRaidOromDelay; + + PchPolicy->sSataConfig.EnclosureSupport = TRUE; + + PchPolicy->sSataConfig.SalpSupport = PchRcVariables->sSataSalp; + PchPolicy->sSataConfig.TestMode = PchRcVariables->sSataTestMode; + // + // Initiate DMI Configuration + // + if (SetupVariables->PcieDmiAspm != PLATFORM_POR) { + if (SetupVariables->PcieDmiAspm != 0xFF) { + PchPolicy->DmiConfig.DmiAspm = TRUE; + } else { + PchPolicy->DmiConfig.DmiAspm = FALSE; + } + } + DEBUG((DEBUG_ERROR, "PchPolicy->DmiConfig.DmiAspm =%x\n", PchPolicy->DmiConfig.DmiAspm)); + // + // PCI express config + // + PchPolicy->PcieConfig.DisableRootPortClockGating = SetupVariables->PcieClockGating; + PchPolicy->PcieConfig.EnablePort8xhDecode = PchRcVariables->PcieRootPort8xhDecode; + PchPolicy->PcieConfig.PchPciePort8xhDecodePortIndex = PchRcVariables->Pcie8xhDecodePortIndex; + PchPolicy->PcieConfig.EnablePeerMemoryWrite = PchRcVariables->PcieRootPortPeerMemoryWriteEnable; + PchPolicy->PcieConfig.ComplianceTestMode = PchRcVariables->PcieComplianceTestMode; + + for (Index = 0; Index < GetPchMaxPciePortNum (); Index++) { + PchPolicy->PcieConfig.RootPort[Index].Enable = PchRcVariables->PcieRootPortEn[Index]; + PchPolicy->PcieConfig.RootPort[Index].PhysicalSlotNumber = (UINT8) Index; + if (PchRcVariables->PchPcieGlobalAspm > PchPcieAspmDisabled) { + // Disabled a.k.a. Per individual port + PchPolicy->PcieConfig.RootPort[Index].Aspm = PchRcVariables->PchPcieGlobalAspm; + } else { + PchPolicy->PcieConfig.RootPort[Index].Aspm = PchRcVariables->PcieRootPortAspm[Index]; + } + PchPolicy->PcieConfig.RootPort[Index].L1Substates = PchRcVariables->PcieRootPortL1SubStates[Index]; + PchPolicy->PcieConfig.RootPort[Index].AcsEnabled = PchRcVariables->PcieRootPortACS[Index]; + PchPolicy->PcieConfig.RootPort[Index].PmSci = PchRcVariables->PcieRootPortPMCE[Index]; + PchPolicy->PcieConfig.RootPort[Index].HotPlug = PchRcVariables->PcieRootPortHPE[Index]; + PchPolicy->PcieConfig.RootPort[Index].AdvancedErrorReporting = PchRcVariables->PcieRootPortAER[Index]; + PchPolicy->PcieConfig.RootPort[Index].UnsupportedRequestReport = PchRcVariables->PcieRootPortURE[Index]; + PchPolicy->PcieConfig.RootPort[Index].FatalErrorReport = PchRcVariables->PcieRootPortFEE[Index]; + PchPolicy->PcieConfig.RootPort[Index].NoFatalErrorReport = PchRcVariables->PcieRootPortNFE[Index]; + PchPolicy->PcieConfig.RootPort[Index].CorrectableErrorReport = PchRcVariables->PcieRootPortCEE[Index]; + PchPolicy->PcieConfig.RootPort[Index].SystemErrorOnFatalError = PchRcVariables->PcieRootPortSFE[Index]; + PchPolicy->PcieConfig.RootPort[Index].SystemErrorOnNonFatalError = PchRcVariables->PcieRootPortSNE[Index]; + PchPolicy->PcieConfig.RootPort[Index].SystemErrorOnCorrectableError = PchRcVariables->PcieRootPortSCE[Index]; + PchPolicy->PcieConfig.RootPort[Index].TransmitterHalfSwing = PchRcVariables->PcieRootPortTHS[Index]; + PchPolicy->PcieConfig.RootPort[Index].CompletionTimeout = PchRcVariables->PcieRootPortCompletionTimeout[Index]; + PchPolicy->PcieConfig.RootPort[Index].PcieSpeed = PchRcVariables->PcieRootPortSpeed[Index]; + + PchPolicy->PcieConfig.RootPort[Index].MaxPayload = PchRcVariables->PcieRootPortMaxPayLoadSize[Index]; + PchPolicy->PcieConfig.RootPort[Index].Gen3EqPh3Method = PchRcVariables->PcieRootPortEqPh3Method[Index]; + } + + for (Index = 0; Index < GetPchMaxPciePortNum (); ++Index) { + PchPolicy->PcieConfig.EqPh3LaneParam[Index].Cm = PchRcVariables->PcieLaneCm[Index]; + PchPolicy->PcieConfig.EqPh3LaneParam[Index].Cp = PchRcVariables->PcieLaneCp[Index]; + } + if (PchRcVariables->PcieSwEqOverride) { + for (Index = 0; Index < PCH_PCIE_SWEQ_COEFFS_MAX; Index++) { + PchPolicy->PcieConfig2.SwEqCoeffList[Index].Cm = PchRcVariables->PcieSwEqCoeffCm[Index]; + PchPolicy->PcieConfig2.SwEqCoeffList[Index].Cp = PchRcVariables->PcieSwEqCoeffCp[Index]; + } + } + + PchPolicy->PcieConfig.MaxReadRequestSize = PchRcVariables->PcieRootPortMaxReadRequestSize; + /// + /// Update Competion Timeout settings for Upling ports for Server PCH + /// + PchPolicy->PcieConfig.PchPcieUX16CompletionTimeout = PchRcVariables->PchPcieUX16CompletionTimeout; + PchPolicy->PcieConfig.PchPcieUX8CompletionTimeout = PchRcVariables->PchPcieUX8CompletionTimeout; + /// + /// Update Max Payload Size settings for Upling ports for Server PCH + /// + PchPolicy->PcieConfig.PchPcieUX16MaxPayload = PchRcVariables->PchPcieUX16MaxPayloadSize; + PchPolicy->PcieConfig.PchPcieUX8MaxPayload = PchRcVariables->PchPcieUX8MaxPayloadSize; + CopyMem (&VTdSupport, (UINT8 *)PcdGetPtr(PcdSocketIioConfigData) + OFFSET_OF(SOCKET_IIO_CONFIGURATION, VTdSupport), sizeof(VTdSupport)); + PchPolicy->PcieConfig.VTdSupport = VTdSupport; + + /// + /// Assign ClkReq signal to root port. (Base 0) + /// For LP, Set 0 - 5 + /// For H, Set 0 - 15 + /// Note that if GbE is enabled, ClkReq assigned to GbE will not be available for Root Port. (TODO for Purley) + /// + // + // HdAudioConfig + // + PchPolicy->HdAudioConfig.Enable = PchRcVariables->PchHdAudio; + PchPolicy->HdAudioConfig.DspEnable = FALSE; + PchPolicy->HdAudioConfig.Pme = PchRcVariables->PchHdAudioPme; + PchPolicy->HdAudioConfig.IoBufferOwnership = PchRcVariables->PchHdAudioIoBufferOwnership; + PchPolicy->HdAudioConfig.IoBufferVoltage = PchRcVariables->PchHdAudioIoBufferVoltage; + PchPolicy->HdAudioConfig.ResetWaitTimer = 300; + PchPolicy->HdAudioConfig.IDispCodecDisconnect = TRUE; //iDisp is permanently disabled + for(Index = 0; Index < HDAUDIO_FEATURES; Index++) { + PchPolicy->HdAudioConfig.DspFeatureMask |= (UINT32)(PchRcVariables->PchHdAudioFeature[Index] ? (1 << Index) : 0); + } + + for(Index = 0; Index < HDAUDIO_PP_MODULES; Index++) { + PchPolicy->HdAudioConfig.DspPpModuleMask |= (UINT32)(PchRcVariables->PchHdAudioPostProcessingMod[Index] ? (1 << Index) : 0); + } + + if (PchPolicy->HdAudioConfig.Enable) { + InstallPlatformVerbTables (PchRcVariables->PchHdAudioCodecSelect); + } + + PchPolicy->HdAudioConfig.VcType = PchRcVariables->RtoHdaVcType; + // + // LockDown + // + + + PchPolicy->LockDownConfig.RtcLock = PchRcVariables->PchRtcLock; + PchPolicy->LockDownConfig.BiosLock = PchRcVariables->PchBiosLock; + PchPolicy->LockDownConfig.SpiEiss = TRUE; + PchPolicy->LockDownConfig.GlobalSmi = TRUE; + PchPolicy->LockDownConfig.BiosInterface = TRUE; + PchPolicy->LockDownConfig.EvaLockDown = PchRcVariables->PchEvaLockDown; + PchPolicy->LockDownConfig.GpioLockDown = PchRcVariables->PchGpioLockDown; + PchPolicy->LockDownConfig.TcoLock = TRUE; + + if(PchRcVariables->PchP2sbUnlock) { + PchPolicy->P2sbConfig.SbiUnlock = TRUE; + PchPolicy->P2sbConfig.PsfUnlock = TRUE; + } else { + PchPolicy->P2sbConfig.SbiUnlock = FALSE; + PchPolicy->P2sbConfig.PsfUnlock = FALSE; + } + PchPolicy->P2sbConfig.P2SbReveal = PchRcVariables->PchP2sbDevReveal; + + // + // Update SPI policies + // + PchPolicy->SpiConfig.ShowSpiController = TRUE; + + // + // PMC Policy + // + PchPolicy->PmConfig.PmcReadDisable = PchRcVariables->PmcReadDisable; + + + if (PchRcVariables->PchAdrEn != PLATFORM_POR) { + PchPolicy->AdrConfig.PchAdrEn = PchRcVariables->PchAdrEn; + } + PchPolicy->AdrConfig.AdrGpioSel = PchRcVariables->AdrGpioSel; + if (PchRcVariables->AdrHostPartitionReset != PLATFORM_POR) { + PchPolicy->AdrConfig.AdrHostPartitionReset = PchRcVariables->AdrHostPartitionReset; + } + if (PchRcVariables->AdrTimerEn != PLATFORM_POR) { + PchPolicy->AdrConfig.AdrTimerEn = PchRcVariables->AdrTimerEn; + } + if (PchRcVariables->AdrTimerVal != ADR_TMR_SETUP_DEFAULT_POR) { + PchPolicy->AdrConfig.AdrTimerVal = PchRcVariables->AdrTimerVal; + } + if (PchRcVariables->AdrMultiplierVal != ADR_MULT_SETUP_DEFAULT_POR) { + PchPolicy->AdrConfig.AdrMultiplierVal = PchRcVariables->AdrMultiplierVal; + } + + // + // Thermal Config + // + if ((PchRcVariables->MemoryThermalManagement != FALSE) && + ((PchRcVariables->ExttsViaTsOnBoard != FALSE) || (PchRcVariables->ExttsViaTsOnDimm != FALSE))) + { + PchPolicy->ThermalConfig.MemoryThrottling.Enable = TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].PmsyncEnable = TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].PmsyncEnable = TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].C0TransmitEnable = TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].C0TransmitEnable = TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].PinSelection = 1; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].PinSelection = 0; + } else { + PchPolicy->ThermalConfig.MemoryThrottling.Enable = FALSE; + } + + // + // IOAPIC Config + // + PchPolicy->IoApicConfig.IoApicEntry24_119 = PchRcVariables->PchIoApic24119Entries; + PchPolicy->IoApicConfig.BdfValid = 1; + PchPolicy->IoApicConfig.BusNumber = 0xF0; + PchPolicy->IoApicConfig.DeviceNumber = 0x1F; + PchPolicy->IoApicConfig.FunctionNumber = 0; + + + // + // Misc PM Config + // + PchPolicy->PmConfig.PchDeepSxPol = PchRcVariables->DeepSxMode; + PchPolicy->PmConfig.WakeConfig.WolEnableOverride = PchRcVariables->PchWakeOnLan; + PchPolicy->PmConfig.WakeConfig.WoWlanEnable = PchRcVariables->PchWakeOnWlan; + PchPolicy->PmConfig.WakeConfig.WoWlanDeepSxEnable = PchRcVariables->PchWakeOnWlanDeepSx; + PchPolicy->PmConfig.WakeConfig.Gp27WakeFromDeepSx = PchRcVariables->Gp27WakeFromDeepSx; + PchPolicy->PmConfig.SlpLanLowDc = PchRcVariables->PchSlpLanLowDc; + PchPolicy->PmConfig.PowerResetStatusClear.MeWakeSts = TRUE; + PchPolicy->PmConfig.PowerResetStatusClear.MeHrstColdSts = TRUE; + PchPolicy->PmConfig.PowerResetStatusClear.MeHrstWarmSts = TRUE; + PchPolicy->PmConfig.PciePllSsc = PchRcVariables->PciePllSsc; + + PchPolicy->PmConfig.DirtyWarmReset = PchRcVariables->Dwr_Enable; + + PchPolicy->PmConfig.StallDirtyWarmReset = PchRcVariables->Dwr_Stall; + PchPolicy->PmConfig.Dwr_BmcRootPort = PchRcVariables->Dwr_BmcRootPort; + + PchPolicy->PmConfig.PchGbl2HostEn.Bits.PMCGBL = PchRcVariables->DwrEn_PMCGBL; + PchPolicy->PmConfig.PchGbl2HostEn.Bits.MEWDT = PchRcVariables->DwrEn_MEWDT; + PchPolicy->PmConfig.PchGbl2HostEn.Bits.IEWDT = PchRcVariables->DwrEn_IEWDT; + + PchPolicy->PmConfig.Dwr_MeResetPrepDone = PchRcVariables->Dwr_MeResetPrepDone; + PchPolicy->PmConfig.Dwr_IeResetPrepDone = PchRcVariables->Dwr_IeResetPrepDone; + + // + // DefaultSvidSid Config + // + PchPolicy->PchConfig.SubSystemVendorId = V_PCH_INTEL_VENDOR_ID; + PchPolicy->PchConfig.SubSystemId = V_PCH_DEFAULT_SID; + PchPolicy->PchConfig.EnableClockSpreadSpec = PchRcVariables->EnableClockSpreadSpec; + // + // Thermal Config + // + PchPolicy->ThermalConfig.ThermalThrottling.TTLevels.PchCrossThrottling = PchRcVariables->PchCrossThrottling; + PchPolicy->ThermalConfig.ThermalThrottling.DmiHaAWC.SuggestedSetting = TRUE; + if (PchRcVariables->ThermalDeviceEnable == PchThermalDeviceAuto) { + if (PchStepping () == LbgA0) { + PchPolicy->ThermalConfig.ThermalDeviceEnable = PchThermalDeviceDisabled; + } else { + PchPolicy->ThermalConfig.ThermalDeviceEnable = PchThermalDeviceEnabledPci; + } + } else { + PchPolicy->ThermalConfig.ThermalDeviceEnable = PchRcVariables->ThermalDeviceEnable; + } + + PchPolicy->ThermalConfig.ThermalThrottling.TTLevels.SuggestedSetting = TRUE; + PchPolicy->ThermalConfig.ThermalThrottling.SataTT.SuggestedSetting = TRUE; + PchPolicy->ThermalConfig.ThermalThrottling.sSataTT.SuggestedSetting = TRUE; + + // + // DCI (EXI) + // + PchPolicy->DciConfig.DciEn = PchRcVariables->PchDciEn; + PchPolicy->DciConfig.DciAutoDetect = PchRcVariables->PchDciAutoDetect; + + + // + // Initialize Serial IRQ Config + // + PchPolicy->SerialIrqConfig.SirqEnable = TRUE; + PchPolicy->SerialIrqConfig.StartFramePulse = PchSfpw4Clk; + if (PchRcVariables->PchSirqMode == 0) { + PchPolicy->SerialIrqConfig.SirqMode = PchQuietMode; + } else { + PchPolicy->SerialIrqConfig.SirqMode = PchContinuousMode; + } + + // + // Port 61h emulation + // + PchPolicy->Port61hSmmConfig.Enable = TRUE; + + // + // DMI configuration + // + PchPolicy->DmiConfig.DmiLinkDownHangBypass = PchRcVariables->DmiLinkDownHangBypass; + PchPolicy->DmiConfig.DmiStopAndScreamEnable = PchRcVariables->PcieDmiStopAndScreamEnable; + + // + // Update Pch Usb Config + // + Usb20OverCurrentMappings = (PCH_USB_OVERCURRENT_PIN *)(UINTN)PcdGet64 (PcdUsb20OverCurrentMappings); + Usb30OverCurrentMappings = (PCH_USB_OVERCURRENT_PIN *)(UINTN)PcdGet64 (PcdUsb30OverCurrentMappings); + UpdatePchUsbConfig ( + &PchPolicy->UsbConfig, + SetupVariables, + PchRcVariables, + Usb20OverCurrentMappings, + Usb30OverCurrentMappings + ); + + // + // Update TraceHub config based on setup options + // + PchPolicy->PchTraceHubConfig.EnableMode = PchRcVariables->TraceHubEnableMode; + + switch (PchRcVariables->MemRegion0BufferSize) { + case 0: + PchPolicy->PchTraceHubConfig.MemReg0Size = 0; // No memory + break; + case 1: + PchPolicy->PchTraceHubConfig.MemReg0Size = 0x100000; // 1MB + break; + case 2: + PchPolicy->PchTraceHubConfig.MemReg0Size = 0x800000; // 8MB + break; + case 3: + PchPolicy->PchTraceHubConfig.MemReg0Size = 0x4000000; // 64MB + break; + } + + switch (PchRcVariables->MemRegion1BufferSize) { + case 0: + PchPolicy->PchTraceHubConfig.MemReg1Size = 0; // No memory + break; + case 1: + PchPolicy->PchTraceHubConfig.MemReg1Size = 0x100000; // 1MB + break; + case 2: + PchPolicy->PchTraceHubConfig.MemReg1Size = 0x800000; // 8MB + break; + case 3: + PchPolicy->PchTraceHubConfig.MemReg1Size = 0x4000000; // 64MB + break; + } + + PchPolicy->PchTraceHubConfig.PchTraceHubHide = PchRcVariables->PchTraceHubHide; + return EFI_SUCCESS; +} + + +/** + Performs silicon pre-mem policy update. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a PPI, etc. + + The input Policy must be returned by SiliconPolicyDonePreMem(). + + 1) In FSP path, the input Policy should be FspmUpd. + A platform may use this API to update the FSPM UPD policy initialized + by the silicon module or the default UPD data. + The output of FSPM UPD data from this API is the final UPD data. + + 2) In non-FSP path, the board may use additional way to get + the silicon policy data field based upon the input Policy. + + @param[in, out] Policy Pointer to policy. + + @return the updated policy. +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePreMem ( + IN OUT VOID *Policy + ) +{ + UpdatePeiPchPolicy (Policy); + return Policy; +} + +/** + Performs silicon post-mem policy update. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a PPI, etc. + + The input Policy must be returned by SiliconPolicyDonePostMem(). + + 1) In FSP path, the input Policy should be FspsUpd. + A platform may use this API to update the FSPS UPD policy initialized + by the silicon module or the default UPD data. + The output of FSPS UPD data from this API is the final UPD data. + + 2) In non-FSP path, the board may use additional way to get + the silicon policy data field based upon the input Policy. + + @param[in, out] Policy Pointer to policy. + + @return the updated policy. +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePostMem ( + IN OUT VOID *Policy + ) +{ + return Policy; +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLib.inf b/Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLib.inf new file mode 100644 index 0000000000..ffa9eed0da --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLib.inf @@ -0,0 +1,62 @@ +### @file +# +# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +### + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SiliconPolicyUpdateLib + FILE_GUID = 6EA9585C-3C15-47da-9FFC-25E9E4EA4D0C + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + LIBRARY_CLASS = SiliconPolicyUpdateLib + +[Sources] + SiliconPolicyUpdateLib.c + PchPolicyUpdateUsb.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + LewisburgPkg/PchRcPkg.dec + PurleySktPkg/SocketPkg.dec + PurleyRcPkg/RcPkg.dec + PurleyOpenBoardPkg/PlatPkg.dec + +[LibraryClasses] + HobLib + MmPciLib + IoLib + PcdLib + PchGbeLib + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData + gOemSkuTokenSpaceGuid.PcdUsb20OverCurrentMappings + gOemSkuTokenSpaceGuid.PcdUsb30OverCurrentMappings + + gOemSkuTokenSpaceGuid.PcdSetupData + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData + +[FixedPcd] + +[Ppis] + +[Guids] + gEfiAcpiVariableGuid diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/PlatformCpuPolicy/PlatformCpuPolicy.c b/Platform/Intel/PurleyOpenBoardPkg/Policy/PlatformCpuPolicy/PlatformCpuPolicy.c new file mode 100644 index 0000000000..4b8a979fc2 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/PlatformCpuPolicy/PlatformCpuPolicy.c @@ -0,0 +1,661 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "PlatformHost.h" +#include + +CHAR16 mCpuSocketStr[8][5] = {L"CPU0", L"CPU1", L"CPU2", L"CPU3", L"CPU4", L"CPU5", L"CPU6", L"CPU7"}; +CHAR16 mCpuAssetTagStr[] = L"UNKNOWN"; +IIO_UDS *mIioUds; + +/** + + GC_TODO: add routine description + + @param None + + @retval None + +**/ +VOID +CheckAndReAssignSocketId( + VOID + ) +{ +#define APICID_MASK_BIT14_8 0x7F //current Si support programmable APICID up to 15bits + CPU_SOCKET_ID_INFO *pcdSktIdPtr; + UINT32 i, IntraPackageIdBits; + UINTN PcdSize; + EFI_STATUS Status; + UINT32 MaxSocketCount; + + MaxSocketCount = FixedPcdGet32(PcdMaxCpuSocketCount); + DEBUG ((EFI_D_ERROR, "::SocketCount %08x\n", MaxSocketCount)); + pcdSktIdPtr = (CPU_SOCKET_ID_INFO *)PcdGetPtr(PcdCpuSocketId); + PcdSize = PcdGetSize (PcdCpuSocketId); //MAX_SOCKET * sizeof(CPU_SOCKET_ID_INFO); + ASSERT(PcdSize == (MAX_SOCKET * sizeof(CPU_SOCKET_ID_INFO))); + Status = PcdSetPtrS (PcdCpuSocketId, &PcdSize, (VOID *)pcdSktIdPtr); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return; + DEBUG ((EFI_D_INFO, "::SockeId Pcd at %08x, size %x\n", PcdGetPtr(PcdCpuSocketId), PcdSize)); + + for(i = 0; i < MAX_SOCKET; i++) { + if(mIioUds->PlatformData.CpuQpiInfo[i].Valid) { + pcdSktIdPtr[i].DefaultSocketId = mIioUds->PlatformData.CpuQpiInfo[i].SocId; + pcdSktIdPtr[i].NewSocketId = mIioUds->PlatformData.CpuQpiInfo[i].SocId; + } else { + pcdSktIdPtr[i].DefaultSocketId = (UINT32)-1; //make sure Default and New are same + pcdSktIdPtr[i].NewSocketId = (UINT32)-1; + } + } + + AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 1, &IntraPackageIdBits, NULL, NULL, NULL); + //assign new socketId + for(i = 0; i < MAX_SOCKET; i++) { + + if(pcdSktIdPtr[i].DefaultSocketId == (UINT32)-1) continue; + + switch(IntraPackageIdBits) { + case 4: //socket bit starts from bit4 of ApicId + case 5: //socket bit starts from bit5 of ApicId + if(MAX_SOCKET == 4) { + pcdSktIdPtr[i].NewSocketId |= (APICID_MASK_BIT14_8 << (8 - IntraPackageIdBits)); + } else { + //3bit in lower 8bit as skt field, to avoid ApicID= FFs, leave bit8 untouched for 8S + pcdSktIdPtr[i].NewSocketId |= (0x7E << (8 - IntraPackageIdBits)); //leave bit8 to 0 so we don't have FFs in ApicId + } + break; + + case 6: //socket bit starts from bit6 of ApicId + if(MAX_SOCKET == 4) { + //only 2bit in lower 8bit as skt field, to avoid ApicID= FFs, leave bit8 untouched for 4S + pcdSktIdPtr[i].NewSocketId |= (0x7E << (8 - IntraPackageIdBits)); + } else { + //only 2bit in lower 8bit as skt field, to avoid ApicID= FFs, leave bit9 untouched for 8S + pcdSktIdPtr[i].NewSocketId |= (0x7C << (8 - IntraPackageIdBits)); + } + break; + + default: + DEBUG ((EFI_D_INFO, "::Need more info to make sure we can support!!!\n")); + break; + + } //end switch + } +} + + +/** + + This is the EFI driver entry point for the CpuPolicy Driver. This + driver is responsible for getting microcode patches from FV. + + @param ImageHandle - Handle for the image of this driver. + @param SystemTable - Pointer to the EFI System Table. + + @retval EFI_SUCCESS - Protocol installed sucessfully. + +**/ +EFI_STATUS +EFIAPI +PlatformCpuPolicyEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + SETUP_DATA SetupData; + UINT32 CpuPolicy; + UINT32 CpuPolicyEx1; + EFI_HANDLE Handle; + UINT32 CsrSapmCtl = 0; + UINT32 CsrPerfPlimitCtl = 0; + UINT8 ConfigTDPCtrl; + UINT8 PCPSOptions = 0; + UINT32 AdvPwrMgtCtl; + UINT8 socket; + UINT32 *UpiInPkgCEntry = NULL; + UINT32 *PcieInPkgCEntry = NULL; + UINT32 MsrPowerCtlLow = 0; + UINT32 MsrTurboPowerLimitHigh = 0; + UINT32 MsrTurboPowerLimitLow = 0; + UINT32 MsrPriPlaneCurrentCfgCtlHigh = 0; + UINT32 MsrPriPlaneCurrentCfgCtlLow = 0; + UINT32 CsrDynamicPerfPowerCtl = 0; + UINT32 CsrPcieIltrOvrd = 0; + UINT32 MsrPerfBiasConfig = 0; + MSR_REGISTER *CStateLatencyCtrl = NULL; + UINT32 CpuFamilyModelStepping; + UINT64 i; + UINT64 *Addr; + EFI_PPM_STRUCT *ppm = NULL; + XE_STRUCT *XePtr = NULL; + TURBO_RATIO_LIMIT_RATIO_CORES *TurboRatioLimitRatioCores = NULL; + UINT8 PackageCStateSetting = 0; + UINT8 CpuCStateValue = 0; + + EFI_GUID UniversalDataGuid = IIO_UNIVERSAL_DATA_GUID; + EFI_HOB_GUID_TYPE *GuidHob; + + GuidHob = GetFirstGuidHob (&UniversalDataGuid); + ASSERT (GuidHob != NULL); + if(GuidHob == NULL) { + return EFI_NOT_FOUND; + } + mIioUds = GET_GUID_HOB_DATA(GuidHob); + + AsmCpuid (1, &CpuFamilyModelStepping, NULL, NULL, NULL); + + Status = gBS->AllocatePool ( + EfiBootServicesData, + sizeof(EFI_PPM_STRUCT), + &Addr + ); + if(Status != EFI_SUCCESS) { + DEBUG ((EFI_D_INFO, "::Failed to allocate mem for PPM Struct\n")); + ASSERT_EFI_ERROR (Status); //may need to create a default + } else { + ZeroMem(Addr, sizeof(EFI_PPM_STRUCT)); + i = (UINT32)(*(UINT64 *)(&Addr)); + ppm = (EFI_PPM_STRUCT *)(Addr); + Status = PcdSet64S (PcdCpuPmStructAddr, i); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + DEBUG ((EFI_D_INFO, "::PPM mem allocate @ %x %X %X\n", i, PcdGet64(PcdCpuPmStructAddr), ppm)); + UpiInPkgCEntry = (UINT32 *)(((EFI_PPM_STRUCT *)Addr)->Cst.PkgCstEntryCriteriaMaskKti); + PcieInPkgCEntry = (UINT32 *)(((EFI_PPM_STRUCT *)Addr)->Cst.PkgCstEntryCriteriaMaskPcie); + XePtr = (XE_STRUCT *)(&((EFI_PPM_STRUCT *)Addr)->Xe); + TurboRatioLimitRatioCores = (TURBO_RATIO_LIMIT_RATIO_CORES *)(&((EFI_PPM_STRUCT *)Addr)->TurboRatioLimitRatioCores); + //DEBUG ((EFI_D_INFO, ":: PkgC @ %X XE @ %X\n", PkgCstEntryCriteriaMask, XePtr)); + + CStateLatencyCtrl = (MSR_REGISTER *)(ppm->Cst.LatencyCtrl); + + } + + // + // Read the current system configuration variable store. + // + ZeroMem (&SetupData, sizeof(SETUP_DATA)); + CopyMem (&SetupData.SocketConfig.IioConfig, PcdGetPtr(PcdSocketIioConfigData), sizeof(SOCKET_IIO_CONFIGURATION)); + CopyMem (&SetupData.SocketConfig.CommonRcConfig, PcdGetPtr(PcdSocketCommonRcConfigData), sizeof(SOCKET_COMMONRC_CONFIGURATION)); + CopyMem (&SetupData.SocketConfig.CsiConfig, PcdGetPtr(PcdSocketMpLinkConfigData), sizeof(SOCKET_MP_LINK_CONFIGURATION)); + CopyMem (&SetupData.SocketConfig.MemoryConfig, PcdGetPtr(PcdSocketMemoryConfigData), sizeof(SOCKET_MEMORY_CONFIGURATION)); + CopyMem (&SetupData.SocketConfig.PowerManagementConfig, PcdGetPtr(PcdSocketPowerManagementConfigData), sizeof(SOCKET_POWERMANAGEMENT_CONFIGURATION)); + CopyMem (&SetupData.SocketConfig.SocketProcessorCoreConfiguration, PcdGetPtr(PcdSocketProcessorCoreConfigData), sizeof(SOCKET_PROCESSORCORE_CONFIGURATION)); + CopyMem (&SetupData.SystemConfig, PcdGetPtr(PcdSetupData), sizeof(SYSTEM_CONFIGURATION)); + CopyMem (&SetupData.PchRcConfig, PcdGetPtr(PcdPchRcConfigurationData), sizeof(PCH_RC_CONFIGURATION)); + + { + + if (SetupData.SocketConfig.PowerManagementConfig.PackageCState == PPM_AUTO) { + PackageCStateSetting = 3; //POR Default = C6 + } else { + PackageCStateSetting = SetupData.SocketConfig.PowerManagementConfig.PackageCState; + } + + // Temporary override to prevent accidental enabling until CR dungeon approves + if (SetupData.SocketConfig.PowerManagementConfig.PackageCState != 0) { + DEBUG((EFI_D_ERROR, "Crystal Ridge Configuration Warning: Package c-states are not disabled\n")); + } + + if ((SetupData.SocketConfig.PowerManagementConfig.C6Enable == PPM_AUTO) || + SetupData.SocketConfig.PowerManagementConfig.ProcessorAutonomousCstateEnable) { + CpuCStateValue |= C6_ENABLE; //POR Default = Enabled + } else { + CpuCStateValue |= (SetupData.SocketConfig.PowerManagementConfig.C6Enable * C6_ENABLE); + } + + Status = PcdSet8S (PcdCpuCoreCStateValue, CpuCStateValue); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + + // + // If ACC enabled, then override C1E to be enabled + // + if (SetupData.SocketConfig.PowerManagementConfig.ProcessorAutonomousCstateEnable) { + SetupData.SocketConfig.PowerManagementConfig.ProcessorC1eEnable = TRUE; + } + + // + // Verify that the value being set is within the valid range 0 to MAX_SOCKET - 1 + // + if (SetupData.SocketConfig.SocketProcessorCoreConfiguration.BspSelection > MAX_SOCKET) + SetupData.SocketConfig.SocketProcessorCoreConfiguration.BspSelection= 0xFF; + Status = PcdSet8S (PcdSbspSelection, SetupData.SocketConfig.SocketProcessorCoreConfiguration.BspSelection); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + // + // Map CPU setup options to PcdCpuProcessorFeatureUserConfiguration + // + CpuPolicy = (SetupData.SocketConfig.SocketProcessorCoreConfiguration.ProcessorHyperThreadingDisable ? 0 : PCD_CPU_HT_BIT) | + (SetupData.SocketConfig.PowerManagementConfig.ProcessorEistEnable ? PCD_CPU_EIST_BIT : 0) | + (SetupData.SocketConfig.PowerManagementConfig.ProcessorC1eEnable ? PCD_CPU_C1E_BIT : 0) | + (SetupData.SocketConfig.SocketProcessorCoreConfiguration.ProcessorVmxEnable ? PCD_CPU_VT_BIT : 0) | + (SetupData.SocketConfig.SocketProcessorCoreConfiguration.ProcessorSmxEnable ? PCD_CPU_LT_BIT : 0) | + (SetupData.SocketConfig.SocketProcessorCoreConfiguration.FastStringEnable ? PCD_CPU_FAST_STRING_BIT : 0) | + (SetupData.SocketConfig.SocketProcessorCoreConfiguration.CpuidMaxValue ? PCD_CPU_MAX_CPUID_VALUE_LIMIT_BIT : 0) | + (SetupData.SocketConfig.SocketProcessorCoreConfiguration.ExecuteDisableBit ? PCD_CPU_EXECUTE_DISABLE_BIT : 0) | + (SetupData.SocketConfig.SocketProcessorCoreConfiguration.MachineCheckEnable ? PCD_CPU_MACHINE_CHECK_BIT : 0) | + (SetupData.SocketConfig.SocketProcessorCoreConfiguration.DCUStreamerPrefetcherEnable ? PCD_CPU_DCU_PREFETCHER_BIT : 0) | + (SetupData.SocketConfig.SocketProcessorCoreConfiguration.DCUIPPrefetcherEnable ? PCD_CPU_IP_PREFETCHER_BIT : 0) | + PCD_CPU_MONITOR_MWAIT_BIT | //never disable Mwait + (SetupData.SocketConfig.PowerManagementConfig.TurboMode ? PCD_CPU_TURBO_MODE_BIT : 0) | + (SetupData.SocketConfig.PowerManagementConfig.EnableThermalMonitor ? PCD_CPU_THERMAL_MANAGEMENT_BIT : 0); + + if (SetupData.SocketConfig.PowerManagementConfig.TStateEnable && (SetupData.SocketConfig.PowerManagementConfig.OnDieThermalThrottling > 0)) { + CpuPolicy |= (SetupData.SocketConfig.PowerManagementConfig.TStateEnable ? PCD_CPU_TSTATE_BIT : 0); + } + + CpuPolicyEx1 = (SetupData.SocketConfig.SocketProcessorCoreConfiguration.MlcStreamerPrefetcherEnable ? PCD_CPU_MLC_STREAMER_PREFETCHER_BIT : 0) | + (SetupData.SocketConfig.SocketProcessorCoreConfiguration.MlcSpatialPrefetcherEnable ? PCD_CPU_MLC_SPATIAL_PREFETCHER_BIT : 0) | + (SetupData.SocketConfig.SocketProcessorCoreConfiguration.ThreeStrikeTimer ? PCD_CPU_THREE_STRIKE_COUNTER_BIT : 0) | + PCD_CPU_ENERGY_PERFORMANCE_BIAS_BIT | + (SetupData.SocketConfig.SocketProcessorCoreConfiguration.ProcessorX2apic ? PCD_CPU_X2APIC_BIT : 0) | + (SetupData.SocketConfig.SocketProcessorCoreConfiguration.AesEnable ? PCD_CPU_AES_BIT : 0) | + (SetupData.SocketConfig.SocketProcessorCoreConfiguration.PCIeDownStreamPECIWrite ? PCD_CPU_PECI_DOWNSTREAM_WRITE_BIT : 0) | + PCD_CPU_C_STATE_BIT; + + + PCPSOptions = (SetupData.SocketConfig.PowerManagementConfig.ProcessorSinglePCTLEn ? PCD_CPU_PCPS_SINGLEPCTL : 0) | + (SetupData.SocketConfig.PowerManagementConfig.ProcessorSPD ? PCD_CPU_PCPS_SPD : 0) | + (SetupData.SocketConfig.PowerManagementConfig.PStateDomain ? PCD_CPU_PCPS_PSTATEDOMAIN : 0) | + (UINT8) SetupData.SocketConfig.PowerManagementConfig.ProcessorEistPsdFunc; + + ppm->PcpsCtrl = PCPSOptions; + ppm->OverclockingLock = SetupData.SocketConfig.PowerManagementConfig.OverclockingLock; + + ppm->FastRaplDutyCycle = SetupData.SocketConfig.PowerManagementConfig.FastRaplDutyCycle; + + if(mIioUds->PlatformData.EVMode) + CpuPolicy &= ~PCD_CPU_LT_BIT; + + if (SetupData.SocketConfig.PowerManagementConfig.ProcessorEistEnable) { + Status = PcdSetBoolS (PcdCpuHwCoordination, SetupData.SocketConfig.PowerManagementConfig.ProcessorEistPsdFunc ? FALSE : TRUE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + } + + Status = PcdSet16S (PcdCpuAcpiLvl2Addr, PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_ACPI_LV2); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + Status = PcdSet8S (PcdCpuPackageCStateLimit, PackageCStateSetting); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + + if ((SetupData.SocketConfig.PowerManagementConfig.TStateEnable) && (SetupData.SocketConfig.PowerManagementConfig.OnDieThermalThrottling > 0)) { + Status = PcdSet8S (PcdCpuClockModulationDutyCycle, SetupData.SocketConfig.PowerManagementConfig.OnDieThermalThrottling); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + ppm->TCCActivationOffset = SetupData.SocketConfig.PowerManagementConfig.TCCActivationOffset; + } + Status = PcdSet8S (PcdCpuDcuMode, SetupData.SocketConfig.SocketProcessorCoreConfiguration.DCUModeSelection); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + + if((CpuFamilyModelStepping >> 4) == CPU_FAMILY_SKX) { + Status = PcdSetBoolS (PcdCpuSmmRuntimeCtlHooks, TRUE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + } else { + Status = PcdSetBoolS (PcdCpuSmmRuntimeCtlHooks, FALSE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + } + DEBUG ((EFI_D_INFO, ":: PcdCpuSmmRuntimeCtlHooks= %x\n", PcdGetBool(PcdCpuSmmRuntimeCtlHooks))); + + if(mIioUds->PlatformData.EVMode || SetupData.SystemConfig.LmceEn) { + Status = PcdSet8S (PcdCpuProcessorMsrLockCtrl, 0); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + } else { + Status = PcdSet8S (PcdCpuProcessorMsrLockCtrl, SetupData.SocketConfig.SocketProcessorCoreConfiguration.ProcessorMsrLockControl); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + } + + Status = PcdSet64S(PcdCpuIioLlcWaysBitMask, SetupData.SocketConfig.SocketProcessorCoreConfiguration.IioLlcWaysMask); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + Status = PcdSet64S(PcdCpuExpandedIioLlcWaysBitMask, SetupData.SocketConfig.SocketProcessorCoreConfiguration.ExpandedIioLlcWaysMask); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + Status = PcdSet64S(PcdCpuRemoteWaysBitMask, SetupData.SocketConfig.SocketProcessorCoreConfiguration.RemoteWaysMask); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + Status = PcdSet8S(PcdPchTraceHubEn, SetupData.SocketConfig.SocketProcessorCoreConfiguration.PchTraceHubEn); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + Status = PcdSet64S(PcdCpuQlruCfgBitMask, ((UINT64) SetupData.SocketConfig.SocketProcessorCoreConfiguration.QlruCfgMask_Hi << 32) | (UINT64)SetupData.SocketConfig.SocketProcessorCoreConfiguration.QlruCfgMask_Lo ); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + Status = PcdSet64S(PcdCpuRRQCountThreshold, mIioUds->PlatformData.RemoteRequestThreshold); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + + //CSR SAPM CTL + CsrSapmCtl = 0; + + for( socket = 0; socket < MAX_SOCKET; socket++) { + CsrSapmCtl = (( SetupData.SocketConfig.PowerManagementConfig.Iio0PkgcClkGateDis[socket] << IIO012_PKGC_CLK_GATE_DISABLE_SHIFT) | + ( SetupData.SocketConfig.PowerManagementConfig.Iio1PkgcClkGateDis[socket] << (IIO012_PKGC_CLK_GATE_DISABLE_SHIFT + 1)) | + ( SetupData.SocketConfig.PowerManagementConfig.Iio2PkgcClkGateDis[socket] << (IIO012_PKGC_CLK_GATE_DISABLE_SHIFT + 2)) ); + + CsrSapmCtl |= (( SetupData.SocketConfig.PowerManagementConfig.Kti23PkgcClkGateDis[socket] << KTI23_PKGC_CLK_GATE_DISABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.Kti01PkgcClkGateDis[socket] << KTI01_PKGC_CLK_GATE_DISABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.Kti01pllOffEna[socket] << KTI_PLL_OFF_EN_SHIFT) | + ( SetupData.SocketConfig.PowerManagementConfig.Kti23pllOffEna[socket] << (KTI_PLL_OFF_EN_SHIFT + 1) ) ); + + CsrSapmCtl |= (( SetupData.SocketConfig.PowerManagementConfig.Mc1PkgcClkGateDis[socket] << MC1_PKGC_CLK_GATE_DISABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.Mc0PkgcClkGateDis[socket] << MC0_PKGC_CLK_GATE_DISABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.Mc0pllOffEna[socket] << MEM_PLL_OFF_EN_SHIFT) | + ( SetupData.SocketConfig.PowerManagementConfig.Mc1pllOffEna[socket] << (MEM_PLL_OFF_EN_SHIFT + 1) )); + + if (SetupData.SocketConfig.MemoryConfig.OppSrefEn == 1) { + CsrSapmCtl |= ((1 << MC0_PKGC_IO_VOLTAGE_REDUCTION_DISABLE_SHIFT) | (1 << MC1_PKGC_IO_VOLTAGE_REDUCTION_DISABLE_SHIFT) | + (1 << MC0_PKGC_DIG_VOLTAGE_REDUCTION_DISABLE_SHIFT) | (1 << MC1_PKGC_DIG_VOLTAGE_REDUCTION_DISABLE_SHIFT)) ; + } + + CsrSapmCtl |= (( SetupData.SocketConfig.PowerManagementConfig.P0pllOffEna[socket] << IIO_PLL_OFF_EN_SHIFT) | + ( SetupData.SocketConfig.PowerManagementConfig.P1pllOffEna[socket] << (IIO_PLL_OFF_EN_SHIFT + 1) ) | + ( SetupData.SocketConfig.PowerManagementConfig.P2pllOffEna[socket] << (IIO_PLL_OFF_EN_SHIFT + 2) ) | + ( SetupData.SocketConfig.PowerManagementConfig.SetvidDecayDisable[socket] << SETVID_DECAY_DISABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.SapmCtlLock[socket] << SAPMCTL_LOCK_SHIFT) ); + + ppm->SapmCtl[socket] = CsrSapmCtl; + } + + ppm->PmaxConfig = (SetupData.SocketConfig.PowerManagementConfig.UsePmaxOffsetTable ? USER_PMAX_USE_OFFSET_TABLE : 0 ) | + SetupData.SocketConfig.PowerManagementConfig.PmaxOffset | + (SetupData.SocketConfig.PowerManagementConfig.PmaxSign ? USER_PMAX_NEGATIVE_BIT : 0); + + CsrPerfPlimitCtl = ( SetupData.SocketConfig.PowerManagementConfig.PerfPLmtThshld << PERF_PLIMIT_THRESHOLD_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.PerfPLimitClipC << PERF_PLIMIT_CLIP_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.PerfPlimitDifferential << PERF_PLIMIT_DIFFERENTIAL_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.PerfPLimitEn << REPERF_PLIMIT_EN_SHIFT ); + ppm->PerPLimitCtl = CsrPerfPlimitCtl; + + ConfigTDPCtrl = ( SetupData.SocketConfig.PowerManagementConfig.ConfigTDPLevel << CONFIG_TDP_LEVEL_SHIFT ); + + ppm->ConfigTDP = ConfigTDPCtrl; + + for( socket = 0; socket < MAX_SOCKET; socket++) { + UpiInPkgCEntry[socket] = (SetupData.SocketConfig.PowerManagementConfig.Kti0In[socket] | + (SetupData.SocketConfig.PowerManagementConfig.Kti1In[socket] << 1) | + (SetupData.SocketConfig.PowerManagementConfig.Kti2In[socket] << 2) ); + + if (SetupData.SocketConfig.PowerManagementConfig.PcieIio0In[socket]) { + PcieInPkgCEntry[socket] |= SET_PCIEx_MASK; + } + if (SetupData.SocketConfig.PowerManagementConfig.PcieIio1In[socket]) { + PcieInPkgCEntry[socket] |= (SET_PCIEx_MASK << 4); + } + if (SetupData.SocketConfig.PowerManagementConfig.PcieIio2In[socket]) { + PcieInPkgCEntry[socket] |= (SET_PCIEx_MASK << 8); + } + if (SetupData.SocketConfig.PowerManagementConfig.PcieIio3In[socket]) { + PcieInPkgCEntry[socket] |= (SET_PCIEx_MASK << 12); + } + if (SetupData.SocketConfig.PowerManagementConfig.PcieIio4In[socket]) { + PcieInPkgCEntry[socket] |= (SET_PCIEx_MASK << 16); + } + if (SetupData.SocketConfig.PowerManagementConfig.PcieIio5In[socket]) { + PcieInPkgCEntry[socket] |= (SET_PCIEx_MASK << 20); + } + + } + + AdvPwrMgtCtl = (SetupData.SocketConfig.PowerManagementConfig.SapmctlValCtl? PCD_CPU_SAPM_CTL_VAL_CTL : 0) | + (SetupData.SocketConfig.PowerManagementConfig.CurrentConfig? PCD_CPU_CURRENT_CONFIG : 0) | + (SetupData.SocketConfig.PowerManagementConfig.BootPState? PCU_CPU_EFFICIENT_BOOT : 0) | + (SetupData.SocketConfig.SocketProcessorCoreConfiguration.ProcessorMsrLockControl? CPU_MSR_LOCK : 0) | + (SetupData.SocketConfig.PowerManagementConfig.TurboPowerLimitCsrLock? TURBO_LIMIT_CSR_LOCK : 0); + + AdvPwrMgtCtl |= SetupData.SocketConfig.PowerManagementConfig.PkgCstEntryValCtl; //PCD_CPU_PKG_CST_ENTRY_VAL_CTL + + if (SetupData.SocketConfig.PowerManagementConfig.ProcessorEistEnable == 0) { + AdvPwrMgtCtl |= PCU_CPU_EFFICIENT_BOOT; + } + + if (((CpuFamilyModelStepping >> 4) == CPU_FAMILY_HSX) && SetupData.SocketConfig.PowerManagementConfig.PriPlnCurCfgValCtl) { + AdvPwrMgtCtl |= PCD_CPU_PRI_PLN_CURR_CFG_CTL; + } + + if ((PackageCStateSetting > 0) && SetupData.SocketConfig.PowerManagementConfig.DynamicL1) { + AdvPwrMgtCtl |= DYNAMIC_L1_DISABLE; + } + + if (SetupData.SocketConfig.PowerManagementConfig.SPTWorkaround) { + AdvPwrMgtCtl |= SPT_PCH_WORKAROUND; + } + + if (SetupData.SocketConfig.PowerManagementConfig.VccSAandVccIOdisable) { + AdvPwrMgtCtl |= VCCSA_VCCIO_DISABLE; + } + ppm->AdvPwrMgtCtlFlags = AdvPwrMgtCtl; + + // MSR_POWER_CTL 0x1FC + MsrPowerCtlLow = ( SetupData.SocketConfig.PowerManagementConfig.PkgCLatNeg << PCH_NEG_DISABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.LTRSwInput << LTR_SW_DISABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.PwrPerfTuning << PWR_PERF_TUNING_CFG_MODE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.PwrPerfSwitch << PWR_PERF_TUNING_ENABLE_DYN_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.SAPMControl << PWR_PERF_TUNING_DISABLE_SAPM_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.EETurboDisable << EE_TURBO_DISABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.ProchotLock << PROCHOT_LOCK_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.ProcessorC1eEnable << C1E_ENABLE_SHIFT ) | + ( (SetupData.SocketConfig.PowerManagementConfig.EnableProcHot & 0x1) << DIS_PROCHOT_OUT_SHIFT ) | + ( (SetupData.SocketConfig.PowerManagementConfig.EnableProcHot & 0x2) >> 1 ); + + // 5332865 BIOS needs to set bit 25 in MSR 0x1FC when enabling HWP autonomous out of band mode + if (SetupData.SocketConfig.PowerManagementConfig.ProcessorHWPMEnable == 2) { //if HWPM = OOB Mode + MsrPowerCtlLow |= ( 1 << PWR_PERF_TUNING_CFG_MODE_SHIFT ); + } + + ppm->PowerCtl.Dwords.Low = MsrPowerCtlLow; + + ppm->ProchotRatio = SetupData.SocketConfig.PowerManagementConfig.ProchotResponseRatio; + + if ((CpuFamilyModelStepping >> 4) == CPU_FAMILY_HSX) { + // PRIMARY_PLANE_CURRENT_CONFIG_CONTROL 0x601 + MsrPriPlaneCurrentCfgCtlHigh = ( SetupData.SocketConfig.PowerManagementConfig.Psi3Code << PSI3_CODE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.Psi3Thshld << PSI3_THSHLD_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.Psi2Code << PSI2_CODE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.Psi2Thshld << PSI2_THSHLD_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.Psi1Code << PSI1_CODE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.Psi1Thshld << PSI1_THSHLD_SHIFT ); + } + + MsrPriPlaneCurrentCfgCtlLow = ( SetupData.SocketConfig.PowerManagementConfig.PpcccLock << PPCCC_LOCK_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.CurrentLimit << CURRENT_LIMIT_SHIFT ); + + ppm->PP0CurrentCfg.Dwords.High = MsrPriPlaneCurrentCfgCtlHigh; + ppm->PP0CurrentCfg.Dwords.Low = MsrPriPlaneCurrentCfgCtlLow; + + // MSR_TURBO_POWER_LIMIT 0x610 + // CSR_TURBO_POWER_LIMIT 1:30:0:0xe8 + MsrTurboPowerLimitHigh = ( SetupData.SocketConfig.PowerManagementConfig.TurboPowerLimitLock << POWER_LIMIT_LOCK_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.PowerLimit2En << POWER_LIMIT_ENABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.PkgClmpLim2 << PKG_CLMP_LIM_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.PowerLimit2Power ); + + MsrTurboPowerLimitLow = ( SetupData.SocketConfig.PowerManagementConfig.PowerLimit1Time << POWER_LIMIT_1_TIME_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.PowerLimit1En << POWER_LIMIT_ENABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.PowerLimit1Power ); + + if ((CpuFamilyModelStepping >> 4) == CPU_FAMILY_HSX) { + MsrTurboPowerLimitLow |= ( SetupData.SocketConfig.PowerManagementConfig.PkgClmpLim1 << PKG_CLMP_LIM_SHIFT ); + MsrTurboPowerLimitHigh |= ( SetupData.SocketConfig.PowerManagementConfig.PkgClmpLim2 << PKG_CLMP_LIM_SHIFT ); + } + + if ((CpuFamilyModelStepping >> 4) == CPU_FAMILY_SKX) { + MsrTurboPowerLimitHigh |= ( SetupData.SocketConfig.PowerManagementConfig.PowerLimit2Time << POWER_LIMIT_1_TIME_SHIFT ); + } + + ppm->TurboPowerLimit.Dwords.Low = MsrTurboPowerLimitLow; + ppm->TurboPowerLimit.Dwords.High = MsrTurboPowerLimitHigh; + + // DYNAMIC_PERF_POWER_CTL (CSR 1:30:2:0x64) + CsrDynamicPerfPowerCtl = ( SetupData.SocketConfig.PowerManagementConfig.UncrPerfPlmtOvrdEn << UNCORE_PERF_PLIMIT_OVERRIDE_ENABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.EetOverrideEn << EET_OVERRIDE_ENABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.IoBwPlmtOvrdEn << IO_BW_PLIMIT_OVERRIDE_ENABLE_SHIFT ) | + //( SetupData.SocketConfig.PowerManagementConfig.ImcApmOvrdEn << IMC_APM_OVERRIDE_ENABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.IomApmOvrdEn << IOM_APM_OVERRIDE_ENABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.QpiApmOvrdEn << QPI_APM_OVERRIDE_ENABLE_SHIFT ); //4986218: Remove both changes from 4168487 + + if((CpuFamilyModelStepping >> 4) == CPU_FAMILY_HSX) { + CsrDynamicPerfPowerCtl |= (( SetupData.SocketConfig.PowerManagementConfig.EepLOverride << EEP_L_OVERRIDE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.EepLOverrideEn << EEP_L_OVERRIDE_ENABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.ITurboOvrdEn << I_TURBO_OVERRIDE_ENABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.CstDemotOvrdEN << CST_DEMOTION_OVERRIDE_ENABLE_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.TrboDemotOvrdEn << TURBO_DEMOTION_OVERRIDE_ENABLE_SHIFT )); + } + + ppm->DynamicPerPowerCtl = CsrDynamicPerfPowerCtl; + + // CSR_PCIE_ILTR_OVRD (CSR 1:30:1:78) + // SW_LTR_OVRD (MSR 0xa02) -- not used + CsrPcieIltrOvrd = ( SetupData.SocketConfig.PowerManagementConfig.SnpLatVld << SNOOP_LATENCY_VLD_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.SnpLatOvrd << FORCE_SNOOP_OVRD_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.SnpLatMult << SNOOP_LATENCY_MUL_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.SnpLatVal << SNOOP_LATENCY_Value_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.NonSnpLatVld << NON_SNOOP_LATENCY_VLD_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.NonSnpLatOvrd << FORCE_NON_SNOOP_OVRD_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.NonSnpLatMult << NON_SNOOP_LATENCY_MUL_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.NonSnpLatVal << NON_SNOOP_LATENCY_Value_SHIFT ); + + ppm-> PcieIltrOvrd = CsrPcieIltrOvrd; + + if((CpuFamilyModelStepping >> 4) == CPU_FAMILY_SKX) { //Need to check if programming needs to be limited only if Turbo mode is enabled. + for(i = 0; i < 8; i++) { + TurboRatioLimitRatioCores->RatioLimitRatio[i] = SetupData.SocketConfig.PowerManagementConfig.TurboRatioLimitRatio[i]; + + TurboRatioLimitRatioCores->RatioLimitRatioMask[i] = 0xFF; + if (SetupData.SocketConfig.PowerManagementConfig.TurboRatioLimitRatio[i] > 0) { + TurboRatioLimitRatioCores->RatioLimitRatioMask[i] = 0; + } + + TurboRatioLimitRatioCores->RatioLimitCoresMask[i] = 0xFF; + TurboRatioLimitRatioCores->RatioLimitCores[i] = 0; + if (SetupData.SocketConfig.PowerManagementConfig.TurboRatioLimitCores[i] != 0xFF) { + TurboRatioLimitRatioCores->RatioLimitCoresMask[i] = 0; + TurboRatioLimitRatioCores->RatioLimitCores[i] = SetupData.SocketConfig.PowerManagementConfig.TurboRatioLimitCores[i]; + } + } + } + + MsrPerfBiasConfig = ( SetupData.SocketConfig.PowerManagementConfig.EngAvgTimeWdw1 << AVG_TIME_Window_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.P0TtlTimeLow1 << PO_TOTAL_TIME_THSHLD_LOW_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.P0TtlTimeHigh1 << PO_TOTAL_TIME_THSHLD_HIGH_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.AltEngPerfBIAS << ALT_ENERGY_PERF_BIAS_SHIFT) | + ( SetupData.SocketConfig.PowerManagementConfig.WorkLdConfig << WORKLD_CONFIG_SHIFT ); + + ppm->PerfBiasConfig.Dwords.Low = MsrPerfBiasConfig; + + // + //ProcessorHWPM-init as disabled. + // + ppm->Hwpm.HWPMNative = 0; + ppm->Hwpm.HWPMOOB = 0; + ppm->Hwpm.HWPMEnable = SetupData.SocketConfig.PowerManagementConfig.ProcessorHWPMEnable; + ppm->Hwpm.AutoCState = SetupData.SocketConfig.PowerManagementConfig.ProcessorAutonomousCstateEnable; + ppm->Hwpm.HWPMInterrupt = SetupData.SocketConfig.PowerManagementConfig.ProcessorHWPMInterrupt; + ppm->Hwpm.EPPEnable = SetupData.SocketConfig.PowerManagementConfig.ProcessorEPPEnable; + ppm->Hwpm.EPPProfile = SetupData.SocketConfig.PowerManagementConfig.ProcessorEppProfile; + + if ((SetupData.SocketConfig.PowerManagementConfig.ProcessorHWPMEnable == 1) || + (SetupData.SocketConfig.PowerManagementConfig.ProcessorHWPMEnable == 3)) { + ppm->Hwpm.HWPMNative = SetupData.SocketConfig.PowerManagementConfig.ProcessorHWPMEnable; + }else if (SetupData.SocketConfig.PowerManagementConfig.ProcessorHWPMEnable == 2){ + ppm->Hwpm.HWPMOOB = SetupData.SocketConfig.PowerManagementConfig.ProcessorHWPMEnable; + ppm->Hwpm.HWPMInterrupt = 0; + }else if (SetupData.SocketConfig.PowerManagementConfig.ProcessorHWPMEnable == 0){ + ppm->Hwpm.HWPMNative = 0; + ppm->Hwpm.HWPMOOB = 0; + ppm->Hwpm.HWPMInterrupt = 0; + ppm->Hwpm.EPPEnable = 0; + } + + ppm->Hwpm.APSrocketing = SetupData.SocketConfig.PowerManagementConfig.ProcessorAPSrocketing; + ppm->Hwpm.Scalability = SetupData.SocketConfig.PowerManagementConfig.ProcessorScalability; + ppm->Hwpm.PPOBudget = SetupData.SocketConfig.PowerManagementConfig.ProcessorPPOBudget; + ppm->Hwpm.OutofBandAlternateEPB = SetupData.SocketConfig.PowerManagementConfig.ProcessorOutofBandAlternateEPB; + + if(SetupData.SocketConfig.SocketProcessorCoreConfiguration.ProcessorX2apic && SetupData.SocketConfig.SocketProcessorCoreConfiguration.ForceX2ApicIds && + (CpuPolicyEx1 & PCD_CPU_X2APIC_BIT)) { //if user want to reprogram > 8bit ApicId (must be X2Apic too) + CheckAndReAssignSocketId(); + } + + for(i = 0; i < NUM_CST_LAT_MSR; i++) { //3 CStateLatencyCtrl CSRs + ppm->Cst.LatencyCtrl[i].Dwords.Low = ( SetupData.SocketConfig.PowerManagementConfig.CStateLatencyCtrlValid[i] << VALID_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.CStateLatencyCtrlMultiplier[i] << MULTIPLIER_SHIFT ) | + ( SetupData.SocketConfig.PowerManagementConfig.CStateLatencyCtrlValue[i] << VALUE_SHIFT ); + } + + if(SetupData.SocketConfig.PowerManagementConfig.C2C3TT) { //if option is not AUTO + ppm->C2C3TT = (UINT32)SetupData.SocketConfig.PowerManagementConfig.C2C3TT; + } else { + ppm->C2C3TT = 0x10; + } + + } //end - else + + CpuPolicy |= PCD_CPU_L3_CACHE_BIT; + + Status = PcdSet32S (PcdCpuProcessorFeatureUserConfiguration, CpuPolicy); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + Status = PcdSet32S (PcdCpuProcessorFeatureUserConfigurationEx1, CpuPolicyEx1); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + if (SetupData.SystemConfig.McBankWarmBootClearError == 1) { + Status = PcdSetBoolS (PcdIsPowerOnReset, TRUE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + } else { + Status = PcdSetBoolS (PcdIsPowerOnReset, FALSE); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) return Status; + } + + // + // Cpu Driver could be dispatched after this protocol installed. + // + Handle = NULL; + Status = gBS->InstallProtocolInterface ( + &Handle, + &gIntelCpuPcdsSetDoneProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/PlatformCpuPolicy/PlatformCpuPolicy.inf b/Platform/Intel/PurleyOpenBoardPkg/Policy/PlatformCpuPolicy/PlatformCpuPolicy.inf new file mode 100644 index 0000000000..a06647e9e3 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/PlatformCpuPolicy/PlatformCpuPolicy.inf @@ -0,0 +1,88 @@ +### @file +# +# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +### + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformCpuPolicy + FILE_GUID = 76A7B4FC-C8D5-462d-A4D2-6E88338A772A + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = PlatformCpuPolicyEntryPoint + +[Sources] + PlatformCpuPolicy.c + +[Packages] + UefiCpuPkg/UefiCpuPkg.dec + MdePkg/MdePkg.dec + PurleyOpenBoardPkg/PlatPkg.dec + PurleySktPkg/SocketPkg.dec + PurleyRcPkg/RcPkg.dec + PurleySktPkg/Override/IA32FamilyCpuPkg/IA32FamilyCpuPkg.dec + LewisburgPkg/PchRcPkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + PcdLib + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + BaseLib + MemoryAllocationLib + BaseMemoryLib + HobLib + IoLib + +[Protocols] + gIntelCpuPcdsSetDoneProtocolGuid + +[Pcd] + gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureUserConfiguration + gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureUserConfigurationEx1 + gEfiCpuTokenSpaceGuid.PcdCpuEnergyPolicy + gEfiCpuTokenSpaceGuid.PcdCpuAcpiLvl2Addr + gEfiCpuTokenSpaceGuid.PcdCpuPackageCStateLimit + gEfiCpuTokenSpaceGuid.PcdCpuCoreCStateValue + gEfiCpuTokenSpaceGuid.PcdCpuClockModulationDutyCycle + gEfiCpuTokenSpaceGuid.PcdCpuHwCoordination + gEfiCpuTokenSpaceGuid.PcdPlatformCpuSocketCount + gEfiCpuTokenSpaceGuid.PcdPlatformCpuSocketNames + gEfiCpuTokenSpaceGuid.PcdPlatformCpuAssetTags + gEfiCpuTokenSpaceGuid.PcdIsPowerOnReset + gEfiCpuTokenSpaceGuid.PcdCpuDcuMode + gEfiCpuTokenSpaceGuid.PcdCpuTurboOverride + gEfiCpuTokenSpaceGuid.PcdCpuProcessorMsrLockCtrl + gEfiCpuTokenSpaceGuid.PcdCpuIioLlcWaysBitMask + gEfiCpuTokenSpaceGuid.PcdCpuExpandedIioLlcWaysBitMask + gEfiCpuTokenSpaceGuid.PcdPchTraceHubEn + gEfiCpuTokenSpaceGuid.PcdCpuQlruCfgBitMask + gEfiCpuTokenSpaceGuid.PcdSbspSelection + gEfiCpuTokenSpaceGuid.PcdCpuPmStructAddr + gEfiCpuTokenSpaceGuid.PcdCpuSocketId + gEfiPchTokenSpaceGuid.PcdPchAcpiIoPortBaseAddress + gEfiCpuTokenSpaceGuid.PcdCpuRemoteWaysBitMask + gEfiCpuTokenSpaceGuid.PcdCpuRRQCountThreshold + gEfiCpuTokenSpaceGuid.PcdCpuSmmRuntimeCtlHooks + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + gOemSkuTokenSpaceGuid.PcdSetupData + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData + +[Depex] + gEfiVariableArchProtocolGuid + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/S3NvramSave/S3NvramSave.c b/Platform/Intel/PurleyOpenBoardPkg/Policy/S3NvramSave/S3NvramSave.c new file mode 100644 index 0000000000..27d5efbeef --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/S3NvramSave/S3NvramSave.c @@ -0,0 +1,262 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "S3NvramSave.h" +#include +#include +#include + +/** + + This function will retrieve the S3 data from HOBs produced by MRC + and will save it to NVRAM if the data is absent or different from + the previously saved data. + + @param VOID + + @retval VOID + +**/ +VOID +SaveS3StructToNvram ( + VOID + ) +{ + EFI_STATUS Status; + UINTN BufferSize; + UINTN CurrentHobSize; + UINTN S3ChunkSize; + CHAR16 EfiMemoryConfigVariable[] = L"MemoryConfig0"; + EFI_HOB_GUID_TYPE *GuidHob = NULL; + VOID *HobData = NULL; + VOID *VariableData = NULL; + + UINTN CompressedDataSize; + UINT32 ScratchSize; + VOID *CompressedData = NULL; + VOID *Scratch = NULL; + EFI_DECOMPRESS_PROTOCOL *Decompress = NULL; + VOID *CompressedVariableData = NULL; + UINTN CompressedBufferSize; + EDKII_VARIABLE_LOCK_PROTOCOL *VariableLock = NULL; + + // + // Get first S3 data HOB + // + GuidHob = GetFirstGuidHob (&gEfiMemoryConfigDataHobGuid); + + Status = gBS->LocateProtocol (&gEfiDecompressProtocolGuid, NULL, (VOID **) &Decompress); + DEBUG((DEBUG_INFO, "[SaveMemoryConfigEntryPoint] Locate Decompress protocol - %r\n", Status)); + if(EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return; + } + + Status = gBS->LocateProtocol(&gEdkiiVariableLockProtocolGuid, NULL, (VOID **)&VariableLock); + DEBUG((DEBUG_INFO, "[SaveMemoryConfigEntryPoint] Locate Variable Lock protocol - %r\n", Status)); + ASSERT_EFI_ERROR(Status); + + while (TRUE) { + if (GuidHob == NULL) { + break; + } + HobData = GET_GUID_HOB_DATA(GuidHob); + CurrentHobSize = GET_GUID_HOB_DATA_SIZE (GuidHob); + + DEBUG((EFI_D_INFO, " Current Hob Size(bytes) is: %d\n", CurrentHobSize)); + // + // Use the HOB data to save Memory Configuration Data + // + BufferSize = CurrentHobSize; + Status = gBS->AllocatePool ( + EfiBootServicesData, + BufferSize, + (VOID**)&VariableData + ); + + ASSERT (VariableData != NULL); + S3ChunkSize = MAX_HOB_ENTRY_SIZE / 8; + DEBUG((EFI_D_INFO, " S3ChunkSize Hob Size(bytes): %d\n", S3ChunkSize)); + + while (CurrentHobSize) { + if (S3ChunkSize > CurrentHobSize) { + S3ChunkSize = CurrentHobSize; + } + BufferSize = S3ChunkSize; + CompressedDataSize = 0; + ScratchSize = 0; + Status = gRT->GetVariable ( + EfiMemoryConfigVariable, + &gEfiMemoryConfigDataGuid, + NULL, + &CompressedDataSize, + NULL + ); + + if(Status == EFI_BUFFER_TOO_SMALL) { + Status = gBS->AllocatePool ( + EfiBootServicesData, + CompressedDataSize, + (VOID**)&CompressedData + ); + ASSERT (Status == EFI_SUCCESS); + } + + if(!EFI_ERROR (Status)) + { + Status = gRT->GetVariable ( + EfiMemoryConfigVariable, + &gEfiMemoryConfigDataGuid, + NULL, + &CompressedDataSize, + CompressedData + ); + + if (!EFI_ERROR (Status)) { + Status = Decompress->GetInfo ( + Decompress, + CompressedData, + (UINT32)CompressedDataSize, + (UINT32*)&BufferSize, + &ScratchSize + ); + } + + if (!EFI_ERROR (Status)) { + Status = gBS->AllocatePool ( + EfiBootServicesData, + ScratchSize, + (VOID**)&Scratch + ); + } + + if (!EFI_ERROR (Status)) { + Status = Decompress->Decompress ( + Decompress, + CompressedData, + (UINT32)CompressedDataSize, + VariableData, + (UINT32)BufferSize, + Scratch, + ScratchSize + ); + } + + if (EFI_ERROR (Status)) { + DEBUG((EFI_D_ERROR, "Getting variables error: 0x%x\n", Status)); + ASSERT (Status == EFI_SUCCESS); + } + + if(Scratch != NULL) { + gBS->FreePool (Scratch); + Scratch = NULL; + } + } + + if(CompressedData != NULL) { + gBS->FreePool (CompressedData); + CompressedData = NULL; + } + + if ( (EFI_ERROR(Status)) || (CompareMem (HobData, VariableData, S3ChunkSize) != 0) ) { + Status = gBS->AllocatePool ( + EfiBootServicesData, + BufferSize, + (VOID**)&CompressedVariableData + ); + ASSERT (CompressedVariableData != NULL); + if (Status == EFI_SUCCESS) { + CompressedBufferSize = BufferSize; + Status = Compress(HobData, S3ChunkSize, CompressedVariableData, &CompressedBufferSize); + if (Status == EFI_BUFFER_TOO_SMALL){ + gBS->FreePool(CompressedVariableData); + Status = gBS->AllocatePool( + EfiBootServicesData, + CompressedBufferSize, + (VOID**)&CompressedVariableData + ); + ASSERT (CompressedVariableData != NULL); + Status = Compress(HobData, S3ChunkSize, CompressedVariableData, &CompressedBufferSize); + } + if(Status == EFI_SUCCESS) { + Status = gRT->SetVariable ( + EfiMemoryConfigVariable, + &gEfiMemoryConfigDataGuid, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, + CompressedBufferSize, + CompressedVariableData + ); + } + if(CompressedVariableData != NULL) { + gBS->FreePool(CompressedVariableData); + CompressedVariableData = NULL; + } + } + + if (EFI_ERROR (Status)) { + DEBUG((EFI_D_ERROR, "Set variable error. Status: 0x%x\n", Status)); + ASSERT_EFI_ERROR (Status); + } + } + // + // Lock the Memory Config Variable + // + Status = VariableLock->RequestToLock(VariableLock, EfiMemoryConfigVariable, &gEfiMemoryConfigDataGuid); + ASSERT_EFI_ERROR(Status); + HobData = (UINT8 *) (HobData) + S3ChunkSize; + + CurrentHobSize -= S3ChunkSize; + EfiMemoryConfigVariable[12]++; // Increment number in the string + } + // + // Get next S3 Config data hob, if none left, results NULL + // + GuidHob = GET_NEXT_HOB (GuidHob); // Increment to next HOB + GuidHob = GetNextGuidHob (&gEfiMemoryConfigDataHobGuid, GuidHob); // Now search for next MemConfig HOB + + if(VariableData != NULL) { + gBS->FreePool(VariableData); + VariableData = NULL; + } + } + + return; +} + +EFI_STATUS +EFIAPI +S3NvramSaveEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +/** + + This is the main entry point of the S3 NVRAM Save module. + + @param ImageHandle - Handle for the image of this driver. + @param SystemTable - Pointer to the EFI System Table. + + @retval EFI_SUCCESS - Module launched successfully. + +**/ +{ + EFI_STATUS Status = EFI_SUCCESS; + + // + // Save the s3 strututre from MRC into NVRAM if needed + // + SaveS3StructToNvram(); + + return Status; + +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/S3NvramSave/S3NvramSave.h b/Platform/Intel/PurleyOpenBoardPkg/Policy/S3NvramSave/S3NvramSave.h new file mode 100644 index 0000000000..2627266fd5 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/S3NvramSave/S3NvramSave.h @@ -0,0 +1,37 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include + +#include "SysHost.h" + +extern EFI_GUID gEfiMemoryConfigDataHobGuid; +extern EFI_GUID gEfiMemoryConfigDataGuid; + +#define MAX_HOB_ENTRY_SIZE 60*1024 + +EFI_STATUS +EFIAPI +S3NvramSaveEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +); + +VOID +SaveS3StructToNvram ( + VOID +); diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/S3NvramSave/S3NvramSave.inf b/Platform/Intel/PurleyOpenBoardPkg/Policy/S3NvramSave/S3NvramSave.inf new file mode 100644 index 0000000000..a06c1ff2c5 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/S3NvramSave/S3NvramSave.inf @@ -0,0 +1,66 @@ +### @file +# +# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +### + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = S3NvramSave + FILE_GUID = 62DC08AC-A651-4EE9-AF81-EAA9261E9780 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = S3NvramSaveEntry + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[Sources] + S3NvramSave.h + S3NvramSave.c + +[LibraryClasses] + UefiDriverEntryPoint + MemoryAllocationLib + UefiRuntimeServicesTableLib + UefiBootServicesTableLib + HobLib + BaseMemoryLib + CompressLib + +[Protocols] + gEfiDecompressProtocolGuid + gEdkiiVariableLockProtocolGuid + +[Guids] + gEfiMemoryConfigDataGuid + gEfiMemoryConfigDataHobGuid + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + PurleyOpenBoardPkg/PlatPkg.dec + PurleySktPkg/SocketPkg.dec + PurleyRcPkg/RcPkg.dec + +[Depex] + gEfiVariableArchProtocolGuid AND + gEfiVariableWriteArchProtocolGuid AND + gEfiDecompressProtocolGuid AND + gEdkiiVariableLockProtocolGuid + diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/SystemBoardCommon.c b/Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/SystemBoardCommon.c new file mode 100644 index 0000000000..6f28e1e7d4 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/SystemBoardCommon.c @@ -0,0 +1,631 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include + +VOID +SetBifurcations( + IN OUT IIO_GLOBALS *IioGlobalData, + IN IIO_BIFURCATION_ENTRY *BifurcationTable, + IN UINT8 BifurcationEntries +) +{ + UINT8 Socket; + UINT8 Iou; + UINT8 Index; + + for (Index = 0; Index < BifurcationEntries ; Index++) { + Socket = BifurcationTable[Index].Socket; + Iou = BifurcationTable[Index].IouNumber; + switch (Iou) { + case Iio_Iou0: + if (IioGlobalData->SetupData.ConfigIOU0[Socket]==IIO_BIFURCATE_AUTO) { + IioGlobalData->SetupData.ConfigIOU0[Socket] = BifurcationTable[Index].Bifurcation; + } + break; + case Iio_Iou1: + if (IioGlobalData->SetupData.ConfigIOU1[Socket] == IIO_BIFURCATE_AUTO) { + IioGlobalData->SetupData.ConfigIOU1[Socket] = BifurcationTable[Index].Bifurcation; + } + break; + case Iio_Iou2: + if (IioGlobalData->SetupData.ConfigIOU2[Socket]==IIO_BIFURCATE_AUTO) { + IioGlobalData->SetupData.ConfigIOU2[Socket] = BifurcationTable[Index].Bifurcation; + } + break; + case Iio_Mcp0: + if (IioGlobalData->SetupData.ConfigMCP0[Socket] == IIO_BIFURCATE_AUTO) { + IioGlobalData->SetupData.ConfigMCP0[Socket] = BifurcationTable[Index].Bifurcation; + } + break; + case Iio_Mcp1: + if (IioGlobalData->SetupData.ConfigMCP1[Socket] == IIO_BIFURCATE_AUTO) { + IioGlobalData->SetupData.ConfigMCP1[Socket] = BifurcationTable[Index].Bifurcation; + } + break; + default: + DEBUG((EFI_D_ERROR, "Invalid bifurcation table: Bad Iou (%d)", Iou)); + ASSERT(Iou); + break; + } + } +} + +VOID +EnableHotPlug ( + IN OUT IIO_GLOBALS *IioGlobalData, + IN UINT8 Port, + IN UINT8 VppPort, + IN UINT8 VppAddress, + IN UINT8 PortOwnership + ) +{ + IioGlobalData->SetupData.SLOTHPCAP[Port]= ENABLE; + IioGlobalData->SetupData.SLOTAIP[Port] = ENABLE; // Attention Indicator Present + IioGlobalData->SetupData.SLOTPIP[Port] = ENABLE; // Power Indicator Present + IioGlobalData->SetupData.SLOTMRLSP[Port]= ENABLE; // MRL Sensor Present + IioGlobalData->SetupData.SLOTABP[Port] = ENABLE; // Attention Button Present + IioGlobalData->SetupData.SLOTPCP[Port] = ENABLE; // Power Controlled Present + + if (PortOwnership == PCIEAIC_OCL_OWNERSHIP){ + IioGlobalData->SetupData.SLOTAIP[Port] = DISABLE; // Attention Indicator Present + IioGlobalData->SetupData.SLOTPIP[Port] = DISABLE; // Power Indicator Present + } + if (PortOwnership == VMD_OWNERSHIP){ + IioGlobalData->SetupData.SLOTABP[Port] = DISABLE; + IioGlobalData->SetupData.SLOTPCP[Port] = DISABLE; + IioGlobalData->SetupData.SLOTMRLSP[Port]= DISABLE; + } + // + // Set SLTCAP settings based on VMD/PCIe SSD Ownership + // + if ((PortOwnership == PCIEAIC_OCL_OWNERSHIP) || + (PortOwnership == VMD_OWNERSHIP)){ + IioGlobalData->SetupData.SLOTHPSUP[Port]= ENABLE; // HotPlug Surprise + } + + if (VppPort!= VPP_PORT_MAX) { + IioGlobalData->SetupData.VppEnable[Port]= ENABLE; + IioGlobalData->SetupData.VppPort[Port]= VppPort; + IioGlobalData->SetupData.VppAddress[Port] = VppAddress; + } else { + DEBUG((EFI_D_ERROR, "PCIE HOT Plug. Missing VPP values on slot table\n")); + } +} + +VOID +ConfigSlots ( + IN OUT IIO_GLOBALS *IioGlobalData, + IN IIO_SLOT_CONFIG_ENTRY *Slot, + IN UINT8 SlotEntries + ) +{ + UINT8 Index; + UINT8 Port; + + for (Index =0; Index < SlotEntries; Index ++) { + Port=Slot[Index].PortIndex; + if (Slot[Index].Hidden != NOT_HIDE) { + IioGlobalData->SetupData.HidePEXPMenu[Port] = HIDE; + IioGlobalData->SetupData.PEXPHIDE[Port]= HIDE; + } + /// Check if slot is assigned. + if (Slot[Index].SlotNumber!= NO_SLT_IMP){ + IioGlobalData->SetupData.SLOTIMP[Port]= SLT_IMP; + IioGlobalData->SetupData.SLOTPSP[Port]=Slot[Index].SlotNumber; + IioGlobalData->SetupData.SLOTEIP[Port]=Slot[Index].InterLockPresent; + if (Slot[Index].SlotPowerLimitScale!= PWR_SCL_MAX) { + IioGlobalData->SetupData.SLOTSPLS[Port] = Slot[Index].SlotPowerLimitScale; + IioGlobalData->SetupData.SLOTSPLV[Port] = Slot[Index].SlotPowerLimitValue; + } + if (Slot[Index].HotPlugCapable != DISABLE) { + EnableHotPlug(IioGlobalData, Port, Slot[Index].VppPort, Slot[Index].VppAddress, REGULAR_PCIE_OWNERSHIP); + } + } + } +} + +/** + Verify if and Slot should be implemented based on IOUX bifurcation settings. + + @param IioGlobalData Pointer to Iio Globals. + @param Port - Port Index + + @retval TRUE/FALSE to determine if an slot shoudl be implemented or not + based on the IOUX bifurcation settings in case user want to do an + override and VMD is enabled. + +**/ +BOOLEAN +SlotImplemented( + IN OUT IIO_GLOBALS *IioGlobalData, + IN UINT8 Port + ){ + UINT8 IioIndex; + UINT8 PortIndex; + UINT8 Stack; + BOOLEAN SlotImp = FALSE; + + IioIndex = Port/NUMBER_PORTS_PER_SOCKET; + PortIndex = (Port - (NUMBER_PORTS_PER_SOCKET * IioIndex)); + // Stack = (((PortIndex + 3)/4) - 1) + (IioIndex*VMD_STACK_PER_SOCKET); + Stack = IioGlobalData->IioVar.IioVData.StackPerPort[IioIndex][PortIndex]; + DEBUG((DEBUG_INFO, "SlotImplemented:IioIndex = %x, Stack = %x, Port = %x, PortIndex =%x\n", IioIndex, Stack, Port, PortIndex)); + + switch(Stack){ + case IIO_PSTACK0: + if (IioGlobalData->SetupData.ConfigIOU0[IioIndex] == IIO_BIFURCATE_x4x4x4x4){ + SlotImp = TRUE; + } else if (IioGlobalData->SetupData.ConfigIOU0[IioIndex] == IIO_BIFURCATE_x4x4xxx8){ + if ((PortIndex == PORT_1D_INDEX) || (PortIndex == PORT_1C_INDEX) || (PortIndex == PORT_1A_INDEX)){ + SlotImp = TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU0[IioIndex] == IIO_BIFURCATE_xxx8x4x4){ + if ((PortIndex == PORT_1C_INDEX) || (PortIndex == PORT_1B_INDEX) || (PortIndex == PORT_1A_INDEX)){ + SlotImp = TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU0[IioIndex] == IIO_BIFURCATE_xxx8xxx8){ + if ((PortIndex == PORT_1C_INDEX) || (PortIndex == PORT_1A_INDEX)){ + SlotImp = TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU0[IioIndex] == IIO_BIFURCATE_xxxxxx16){ + if (PortIndex == PORT_1A_INDEX){ + SlotImp = TRUE; + } + } + break; + case IIO_PSTACK1: + if (IioGlobalData->SetupData.ConfigIOU1[IioIndex] == IIO_BIFURCATE_x4x4x4x4){ + SlotImp = TRUE; + } else if (IioGlobalData->SetupData.ConfigIOU1[IioIndex] == IIO_BIFURCATE_x4x4xxx8){ + if ((PortIndex == PORT_2D_INDEX) || (PortIndex == PORT_2C_INDEX) || (PortIndex == PORT_2A_INDEX)){ + SlotImp = TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU1[IioIndex] == IIO_BIFURCATE_xxx8x4x4){ + if ((PortIndex == PORT_2C_INDEX) || (PortIndex == PORT_2B_INDEX) || (PortIndex == PORT_2A_INDEX)){ + SlotImp = TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU1[IioIndex] == IIO_BIFURCATE_xxx8xxx8){ + if ((PortIndex == PORT_2C_INDEX) || (PortIndex == PORT_2A_INDEX)){ + SlotImp = TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU1[IioIndex] == IIO_BIFURCATE_xxxxxx16){ + if (PortIndex == PORT_2A_INDEX){ + SlotImp = TRUE; + } + } + break; + case IIO_PSTACK2: + if (IioGlobalData->SetupData.ConfigIOU2[IioIndex] == IIO_BIFURCATE_x4x4x4x4){ + SlotImp = TRUE; + } else if (IioGlobalData->SetupData.ConfigIOU2[IioIndex] == IIO_BIFURCATE_x4x4xxx8){ + if ((PortIndex == PORT_3D_INDEX) || (PortIndex == PORT_3C_INDEX) || (PortIndex == PORT_3A_INDEX)){ + SlotImp = TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU2[IioIndex] == IIO_BIFURCATE_xxx8x4x4){ + if ((PortIndex == PORT_3C_INDEX) || (PortIndex == PORT_3B_INDEX) || (PortIndex == PORT_3A_INDEX)){ + SlotImp = TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU2[IioIndex] == IIO_BIFURCATE_xxx8xxx8){ + if ((PortIndex == PORT_3C_INDEX) || (PortIndex == PORT_3A_INDEX)){ + SlotImp = TRUE; + } + } else if (IioGlobalData->SetupData.ConfigIOU2[IioIndex] == IIO_BIFURCATE_xxxxxx16){ + if (PortIndex == PORT_3A_INDEX){ + SlotImp = TRUE; + } + } + break; + } + DEBUG((DEBUG_INFO, "SlotImplemented: = %x\n", SlotImp)); + return SlotImp; +} + +/** + Verify if VMD is enabled and override Slot conofgiration + based on the VMD settings + + @param IioGlobalData Pointer to Iio Globals. + @param Slot - Slot configuarion settings + @param SlotEntries - Number of slot entries + + @retval None + +**/ +VOID +OverrideConfigSlots ( + IN OUT IIO_GLOBALS *IioGlobalData, + IN IIO_SLOT_CONFIG_ENTRY *Slot, + IN UINT8 SlotEntries + ) +{ + UINT8 Index; + UINT8 Port; + UINT8 IioIndex; + UINT8 VmdPort; + UINT8 Stack; + + for (Index =0; Index < SlotEntries; Index ++) { + Port = Slot[Index].PortIndex; + // + // Check if Slot is capable of PcieSSD Solution and override the SLOT Config values + // + if (Slot[Index].PcieSSDCapable){ + IioIndex = Port/NUMBER_PORTS_PER_SOCKET; + Stack = ((((Port - (NUMBER_PORTS_PER_SOCKET * IioIndex))+ 3)/4) - 1) + (IioIndex*VMD_STACK_PER_SOCKET); + DEBUG((DEBUG_INFO, "Stack = %x, Port = %x\n", Stack, Port)); + + // + // check if VMD will own Pcie Root Port + // + if(IioGlobalData->SetupData.VMDEnabled[Stack]){ + VmdPort = ((IioIndex * VMD_PORTS_PER_SOCKET) + (Port - (NUMBER_PORTS_PER_SOCKET * IioIndex))) - 1; + if (IioGlobalData->SetupData.VMDPortEnable[VmdPort]){ + IioGlobalData->IioVar.IioOutData.PciePortOwnership[Port] = VMD_OWNERSHIP; + } + } else { + + DEBUG((DEBUG_INFO, "IioGlobalData->SetupData.PcieAICEnabled[%x] = %x\n",Stack, IioGlobalData->SetupData.PcieAICEnabled[Stack])); + // + // Check if Pcie AIC Card will be present on Pcie Root Port + // + if(IioGlobalData->SetupData.PcieAICEnabled[Stack]){ + // + // Force to have this port enabled by default for hot-plug. + // + IioGlobalData->SetupData.PciePortDisable[(IioIndex * NUMBER_PORTS_PER_SOCKET) + Port] = ENABLE; + IioGlobalData->IioVar.IioOutData.PciePortOwnership[Port] = PCIEAIC_OCL_OWNERSHIP; + DEBUG((DEBUG_ERROR, "Port = %x, PciePortDisable = %x\n",Port,IioGlobalData->SetupData.PciePortDisable[(IioIndex * NUMBER_PORTS_PER_SOCKET) + Port])); + } + } // No _VMD Ownership + + DEBUG((DEBUG_INFO, "PciePortOwnerShip[%x] = %x\n",Port, IioGlobalData->IioVar.IioOutData.PciePortOwnership[Port])); + + // if PcieSSDSupport required do slot override settings accordingly + if((IioGlobalData->IioVar.IioOutData.PciePortOwnership[Port] != REGULAR_PCIE_OWNERSHIP) && + (SlotImplemented(IioGlobalData, Port) == TRUE)){ + IioGlobalData->SetupData.SLOTIMP[Port]= SLT_IMP; + IioGlobalData->SetupData.SLOTPSP[Port]= 0x50 + Port; // Just program a value for PCIEACI_OCL/VMD + IioGlobalData->SetupData.SLOTEIP[Port]= DISABLE; + + if (Slot[Index].SlotPowerLimitScale!= PWR_SCL_MAX) { + IioGlobalData->SetupData.SLOTSPLS[Port] = Slot[Index].SlotPowerLimitScale; + IioGlobalData->SetupData.SLOTSPLV[Port] = Slot[Index].SlotPowerLimitValue; + } + DEBUG((DEBUG_INFO,"Slot[Index].PcieSSDVppPort = %x\n", Slot[Index].PcieSSDVppPort)); + // Enable hot-plug if slot/port supports it + if (Slot[Index].PcieSSDVppPort != VPP_PORT_MAX) { + DEBUG((DEBUG_INFO, "IioGlobalData->SetupData.VMDHotPlugEnable[%x] = %x\n",Stack,IioGlobalData->SetupData.VMDHotPlugEnable[Stack])); + DEBUG((DEBUG_INFO, "IioGlobalData->SetupData.PcieAICHotPlugEnable[%x] = %x\n",Stack,IioGlobalData->SetupData.PcieAICHotPlugEnable[Stack])); + // Check if hot-plug is enabled for VMD or PCIeAIC case. + if (((IioGlobalData->IioVar.IioOutData.PciePortOwnership[Port] == VMD_OWNERSHIP) && (IioGlobalData->SetupData.VMDHotPlugEnable[Stack])) || + ((IioGlobalData->IioVar.IioOutData.PciePortOwnership[Port] == PCIEAIC_OCL_OWNERSHIP) && (IioGlobalData->SetupData.PcieAICHotPlugEnable[Stack]))) { + EnableHotPlug(IioGlobalData, Port, Slot[Index].PcieSSDVppPort, Slot[Index].PcieSSDVppAddress, IioGlobalData->IioVar.IioOutData.PciePortOwnership[Port]); + DEBUG((DEBUG_INFO,"Enable HotPlug Done\n")); + } + } + // + // Unhide the port in order to get configured and it will be hide later for VMDLateSetup if VMD own the Pcie Root Port + // + IioGlobalData->SetupData.PEXPHIDE[Port]= NOT_HIDE; + }// PcieSSDSupport + }// PcieSSDCapable + }// Per Slot +} + + +/** + Auto determine which PCIe Root port to be hidden if its + lanes are assigned to its preceding root port...use the + Setup option variable of ConfigIOU to determine which ports + are to be hidden on each IOU for corresponding IIO + + @param IOUx - IOUx Index + @param IioIndex - Index to Iio + @param IioGlobalData Pointer to Iio Globals. + + @retval None + +**/ +VOID +CalculatePEXPHideFromIouBif ( + IN UINT8 Iou, + IN UINT8 IioIndex, + IN OUT IIO_GLOBALS *IioGlobalData +) +{ + + UINT8 *PXPHide, *HidePEXPMenu; + UINT8 CurrentIOUConfigValue; + UINT8 PXPOffset; + PXPHide = IioGlobalData->SetupData.PEXPHIDE; + HidePEXPMenu = IioGlobalData->SetupData.HidePEXPMenu; + CurrentIOUConfigValue =0; + + PXPOffset=IioIndex * NUMBER_PORTS_PER_SOCKET; + + switch (Iou) { + case Iio_Iou0: + CurrentIOUConfigValue = IioGlobalData->SetupData.ConfigIOU0[IioIndex]; + PXPOffset+= PORT_1A_INDEX; + break; + case Iio_Iou1: + CurrentIOUConfigValue = IioGlobalData->SetupData.ConfigIOU1[IioIndex]; + PXPOffset+= PORT_2A_INDEX; + break; + case Iio_Iou2: + CurrentIOUConfigValue = IioGlobalData->SetupData.ConfigIOU2[IioIndex]; + PXPOffset+= PORT_3A_INDEX; + break; + case Iio_Mcp0: + CurrentIOUConfigValue = IioGlobalData->SetupData.ConfigMCP0[IioIndex]; + PXPOffset+= PORT_4A_INDEX; + break; + case Iio_Mcp1: + CurrentIOUConfigValue = IioGlobalData->SetupData.ConfigMCP1[IioIndex]; + PXPOffset += PORT_5A_INDEX; + break; + } + + switch(CurrentIOUConfigValue){ + case IIO_BIFURCATE_xxxxxxxx: + PXPHide[PXPOffset + Iio_PortA] = HIDE; // hide A + PXPHide[PXPOffset + Iio_PortB] = HIDE; // hide B + PXPHide[PXPOffset + Iio_PortC] = HIDE; // hide C + PXPHide[PXPOffset + Iio_PortD] = HIDE; // hide D + HidePEXPMenu[PXPOffset + Iio_PortA] = HIDE; // hide the Setup menu for A + HidePEXPMenu[PXPOffset + Iio_PortB] = HIDE; // hide the Setup menu for B + HidePEXPMenu[PXPOffset + Iio_PortC] = HIDE; // hide the Setup menu for C + HidePEXPMenu[PXPOffset + Iio_PortD] = HIDE; // hide the Setup menu for D + break; + case IIO_BIFURCATE_x4x4xxx8: + PXPHide[PXPOffset + Iio_PortA] = NOT_HIDE; // show A + PXPHide[PXPOffset + Iio_PortB] = HIDE; // hide B + PXPHide[PXPOffset + Iio_PortC] = NOT_HIDE; // show C + PXPHide[PXPOffset + Iio_PortD] = NOT_HIDE; // show D + HidePEXPMenu[PXPOffset + Iio_PortA] = NOT_HIDE; // show the Setup menu for B + HidePEXPMenu[PXPOffset + Iio_PortB] = HIDE; // hide the Setup menu for B + HidePEXPMenu[PXPOffset + Iio_PortC] = NOT_HIDE; // show the Setup menu for D + HidePEXPMenu[PXPOffset + Iio_PortD] = NOT_HIDE; // show the Setup menu for B + break; + case IIO_BIFURCATE_xxx8x4x4: + PXPHide[PXPOffset + Iio_PortA] = NOT_HIDE; // show A + PXPHide[PXPOffset + Iio_PortB] = NOT_HIDE; // show B + PXPHide[PXPOffset + Iio_PortC] = NOT_HIDE; // show C + PXPHide[PXPOffset + Iio_PortD] = HIDE; // hide port D + HidePEXPMenu[PXPOffset + Iio_PortA] = NOT_HIDE; // show the Setup menu for A + HidePEXPMenu[PXPOffset + Iio_PortB] = NOT_HIDE; // show the Setup menu for B + HidePEXPMenu[PXPOffset + Iio_PortC] = NOT_HIDE; // show the Setup menu for C + HidePEXPMenu[PXPOffset + Iio_PortD] = HIDE; // hide the Setup menu for D + break; + case IIO_BIFURCATE_xxx8xxx8: + PXPHide[PXPOffset + Iio_PortA] = NOT_HIDE; // show A + PXPHide[PXPOffset + Iio_PortB] = HIDE; // hide B + PXPHide[PXPOffset + Iio_PortC] = NOT_HIDE; // show C + PXPHide[PXPOffset + Iio_PortD] = HIDE; // hide D + HidePEXPMenu[PXPOffset + Iio_PortA] = NOT_HIDE; // show the Setup menu for A + HidePEXPMenu[PXPOffset + Iio_PortB] = HIDE; // hide the Setup menu for B + HidePEXPMenu[PXPOffset + Iio_PortC] = NOT_HIDE; // show the Setup menu for C + HidePEXPMenu[PXPOffset + Iio_PortD] = HIDE; // hide the Setup menu for D + break; + case IIO_BIFURCATE_xxxxxx16: + PXPHide[PXPOffset + Iio_PortA] = NOT_HIDE; // show A + PXPHide[PXPOffset + Iio_PortB] = HIDE; // hide B + PXPHide[PXPOffset + Iio_PortC] = HIDE; // hide C + PXPHide[PXPOffset + Iio_PortD] = HIDE; // hide D + HidePEXPMenu[PXPOffset + Iio_PortA] = NOT_HIDE; // show the Setup menu for A + HidePEXPMenu[PXPOffset + Iio_PortB] = HIDE; // hide the Setup menu for B + HidePEXPMenu[PXPOffset + Iio_PortC] = HIDE; // hide the Setup menu for C + HidePEXPMenu[PXPOffset + Iio_PortD] = HIDE; // hide the Setup menu for D + break; + default: + PXPHide[PXPOffset + Iio_PortA] = NOT_HIDE; // show A + PXPHide[PXPOffset + Iio_PortB] = NOT_HIDE; // show B + PXPHide[PXPOffset + Iio_PortC] = NOT_HIDE; // show C + PXPHide[PXPOffset + Iio_PortD] = NOT_HIDE; // show port D + HidePEXPMenu[PXPOffset + Iio_PortA] = NOT_HIDE; // show the Setup menu for A + HidePEXPMenu[PXPOffset + Iio_PortB] = NOT_HIDE; // show the Setup menu for B + HidePEXPMenu[PXPOffset + Iio_PortC] = NOT_HIDE; // show the Setup menu for C + HidePEXPMenu[PXPOffset + Iio_PortD] = NOT_HIDE; // show the Setup menu for D + break; + } + + // + // Change PEXPHIDE setting to hide all PCIe port of a IOU if IIO_BIFURCATE_xxxxxxxx is set. + // And set ConfigIOUx/ConfigMCPx to default bifucation control value + // Bifurcation_Control[2:0] in IOU Bifurcation Control (PCIE_IOU_BIF_CTRL) register should be 000b ~ 100b. + // + if (CurrentIOUConfigValue == IIO_BIFURCATE_xxxxxxxx) { + switch (Iou) { + case Iio_Iou0: + IioGlobalData->SetupData.ConfigIOU0[IioIndex] = IIO_BIFURCATE_x4x4x4x4; + break; + case Iio_Iou1: + IioGlobalData->SetupData.ConfigIOU1[IioIndex] = IIO_BIFURCATE_x4x4x4x4; + break; + case Iio_Iou2: + IioGlobalData->SetupData.ConfigIOU2[IioIndex] = IIO_BIFURCATE_x4x4x4x4; + break; + case Iio_Mcp0: + IioGlobalData->SetupData.ConfigMCP0[IioIndex] = IIO_BIFURCATE_x4x4x4x4; + break; + case Iio_Mcp1: + IioGlobalData->SetupData.ConfigMCP1[IioIndex] = IIO_BIFURCATE_x4x4x4x4; + break; + default: + break; + } + } +} + + +VOID +DumpPort( + IIO_GLOBALS *IioGlobalData, + UINT8 Port, + UINT8 NumberOfPorts +) +{ + UINT8 Index; + DEBUG((EFI_D_INFO, "IDX, Port Hide, Slot Impl, Slot Number, HotPlug, PcieSSD, VppPort, VppAddress, Interlock\n")); + for (Index = Port; Index < (Port + NumberOfPorts); Index++ ) { + DEBUG((EFI_D_INFO, "%3d| %2d | %2d | %3d | %3d | %3d | 0x%02x | 0x%02x | %2d \n", \ + Index, \ + IioGlobalData->SetupData.PEXPHIDE[Index], \ + IioGlobalData->SetupData.SLOTIMP[Index], \ + IioGlobalData->SetupData.SLOTPSP[Index], \ + IioGlobalData->SetupData.SLOTHPCAP[Index], \ + IioGlobalData->IioVar.IioOutData.PciePortOwnership[Index], \ + IioGlobalData->SetupData.VppPort[Index], \ + IioGlobalData->SetupData.VppAddress[Index],\ + IioGlobalData->SetupData.SLOTEIP[Index])); + } + } +/// Dump iio configuration. Dump the current IIO configuration to the serial +/// log. +VOID +DumpIioConfiguration( + IN UINT8 iio, + IN IIO_GLOBALS *IioGlobalData +) +{ + UINT8 Iou; + UINT8 PortIndex; + UINT8 Bifurcation; + UINT8 IouPorts; + PortIndex = iio * NUMBER_PORTS_PER_SOCKET; + /// First dump the socket number; + DEBUG((EFI_D_INFO, "Socket number: %d \n", iio)); + + /// Dump DMI configuration: + if ((iio == 0) && (PortIndex == 0)){ + DEBUG((EFI_D_INFO, "PORT 0: DMI Port\n")); + } else { + DEBUG((EFI_D_INFO, "PORT 0: DMI Port working as PCIE\n")); + DumpPort(IioGlobalData, PortIndex, 1); + } + IouPorts=4; + /// Dump IOU bifurcations: + for (Iou = Iio_Iou0; Iou< Iio_IouMax; Iou ++) { + /// Reset port index. + PortIndex = iio * NUMBER_PORTS_PER_SOCKET; + // Get the bifurcation + switch (Iou) { + case Iio_Iou0: + Bifurcation = IioGlobalData->SetupData.ConfigIOU0[iio]; + PortIndex += PORT_1A_INDEX; + DEBUG((EFI_D_INFO, "IUO0: Root Port 1, Bifurcation: %d\n", Bifurcation)); + break; + case Iio_Iou1: + Bifurcation = IioGlobalData->SetupData.ConfigIOU1[iio]; + PortIndex += PORT_2A_INDEX; + DEBUG((EFI_D_INFO, "IUO1: Root Port 2, Bifurcation: %d\n", Bifurcation)); + break; + case Iio_Iou2: + Bifurcation = IioGlobalData->SetupData.ConfigIOU2[iio]; + PortIndex += PORT_3A_INDEX; + DEBUG((EFI_D_INFO, "IUO2: Root Port 3, Bifurcation: %d\n", Bifurcation)); + break; + case Iio_Mcp0: + Bifurcation = IioGlobalData->SetupData.ConfigMCP0[iio]; + PortIndex += PORT_4A_INDEX; + DEBUG((EFI_D_INFO, "MCP0, Bifurcation: %d\n", Bifurcation)); + break; + case Iio_Mcp1: + Bifurcation = IioGlobalData->SetupData.ConfigMCP1[iio]; + PortIndex += PORT_5A_INDEX; + DEBUG((EFI_D_INFO, "MCP1, Bifurcation: %d\n", Bifurcation)); + break; + default: + DEBUG((EFI_D_INFO, "Iou no detected = %d",Iou)); + break; + } + DumpPort(IioGlobalData, PortIndex, IouPorts); + } + +} + +UINT8 +GetUplinkPortInformationCommon ( + IN UINT8 IioIndex +) +{ + UINT8 UplinkPortIndex = 0xFF; + + if (IioIndex == 0) { + UplinkPortIndex = PcdGet8(PcdOemSkuUplinkPortIndex); + } + + return UplinkPortIndex; +} +/** + + SystemIioPortBifurcationInit - Program the UDS data structure with OEM IIO init values + for SLOTs and Bifurcation. + + @param mSB - pointer to this protocol + @param IioUds - Pointer to the IIO UDS datastructure. + + @retval EFI_SUCCESS + +**/ +VOID +SystemIioPortBifurcationInitCommon ( + IIO_GLOBALS *IioGlobalData, + IIO_BIFURCATION_ENTRY **BifurcationTable, + UINT8 *BifurcationEntries, + IIO_SLOT_CONFIG_ENTRY **SlotTable, + UINT8 *SlotEntries +) +{ + + UINT8 PortIndex;//, iio; + + /// This function outline: + //// 1 Based on platform apply the default bifurcation and slot configuration. + //// 2 Apply dynamic overrides based on GPIO and other configurations. + //// 3 Hide unused ports due bifurcation. + + for (PortIndex = 0; PortIndex < MAX_SOCKET*NUMBER_PORTS_PER_SOCKET; PortIndex++) { + IioGlobalData->SetupData.PEXPHIDE[PortIndex] = 0; + IioGlobalData->SetupData.HidePEXPMenu[PortIndex] = 0; + } + + *BifurcationEntries = 0; + *SlotEntries = 0; + + *BifurcationTable = (IIO_BIFURCATION_ENTRY *)(UINTN)PcdGet64 (PcdIioBifurcationTable); + *BifurcationEntries = PcdGet8 (PcdIioBifurcationTableEntries); + *SlotTable = (IIO_SLOT_CONFIG_ENTRY *)(UINTN)PcdGet64 (PcdIioSlotTable); + *SlotEntries = PcdGet8 (PcdIioSlotTableEntries); +} + +VOID +SystemHideIioPortsCommon( + IIO_GLOBALS *IioGlobalData, + UINT8 IioIndex +) +{ + CalculatePEXPHideFromIouBif(Iio_Iou0, IioIndex, IioGlobalData); + CalculatePEXPHideFromIouBif(Iio_Iou1, IioIndex, IioGlobalData); + CalculatePEXPHideFromIouBif(Iio_Iou2, IioIndex, IioGlobalData); + CalculatePEXPHideFromIouBif(Iio_Mcp0, IioIndex, IioGlobalData); + CalculatePEXPHideFromIouBif(Iio_Mcp1, IioIndex, IioGlobalData); + DumpIioConfiguration(IioIndex, IioGlobalData); +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/SystemBoardPei.c b/Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/SystemBoardPei.c new file mode 100644 index 0000000000..5a1d4618e4 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/SystemBoardPei.c @@ -0,0 +1,261 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "SystemBoardPei.h" + +#include +#include + +#include + +extern IIO_BIFURCATION_ENTRY mIioBifurcationTable[]; +extern UINT8 mIioBifurcationTableEntries; +extern IIO_SLOT_CONFIG_ENTRY mIioSlotTable[]; +extern UINT8 mIioSlotTableEntries; + +// +// System board PPI structure +// +static SYSTEM_BOARD_PPI mSystemBoardPpi = { + SystemIioPortBifurcationInit, // Set IIO Bifurcation ports configuration + GetUplinkPortInformation, +}; + +static EFI_PEI_PPI_DESCRIPTOR mSystemBoardPpiDesc = { + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gEfiPeiSystemBoardPpiGuid, + &mSystemBoardPpi +}; + +/** + + GetUplinkPortInformation - Get uplink port information + + @param IioIndex - socket ID. + + @retval PortIndex for uplink port + +**/ +UINT8 +EFIAPI +GetUplinkPortInformation ( + IN UINT8 IioIndex +) +{ + UINT8 UplinkPortIndex; + + UplinkPortIndex = GetUplinkPortInformationCommon(IioIndex); + return UplinkPortIndex; +} + +/** + + SystemIioPortBifurcationInit - Program the UDS data structure with OEM IIO init values + for SLOTs and Bifurcation. + + @param mSB - pointer to this protocol + @param IioUds - Pointer to the IIO UDS datastructure. + + @retval EFI_SUCCESS + +**/ +VOID +InternalSystemIioPortBifurcationInitCommon ( + IN OUT IIO_GLOBALS *IioGlobalData, + IN OUT IIO_BIFURCATION_ENTRY **BifurcationTable, + IN OUT UINT8 *BifurcationEntries, + IN OUT IIO_SLOT_CONFIG_ENTRY **SlotTable, + IN OUT UINT8 *SlotEntries +) +{ + + UINT8 PortIndex;//, iio; + + /// This function outline: + //// 1 Based on platform apply the default bifurcation and slot configuration. + //// 2 Apply dynamic overrides based on GPIO and other configurations. + //// 3 Hide unused ports due bifurcation. + + for (PortIndex = 0; PortIndex < MAX_SOCKET*NUMBER_PORTS_PER_SOCKET; PortIndex++) { + IioGlobalData->SetupData.PEXPHIDE[PortIndex] = 0; + IioGlobalData->SetupData.HidePEXPMenu[PortIndex] = 0; + } + + *BifurcationEntries = 0; + *SlotEntries = 0; + + // Purley Intel boards are not Multi-PCH + IioGlobalData->IioVar.IioVData.MultiPch = 0; + + *BifurcationTable = (IIO_BIFURCATION_ENTRY *)(UINTN)PcdGet64 (PcdIioBifurcationTable); + *BifurcationEntries = PcdGet8 (PcdIioBifurcationTableEntries); + *SlotTable = (IIO_SLOT_CONFIG_ENTRY *)(UINTN)PcdGet64 (PcdIioSlotTable); + *SlotEntries = PcdGet8 (PcdIioSlotTableEntries); +} + +/** + + SystemIioPortBifurcationInit - Program the IIO_GLOBALS data structure with OEM IIO init values + for SLOTs and Bifurcation. + + @param mSB - pointer to this protocol + @param IioUds - Pointer to the IIO UDS datastructure. + + @retval EFI_SUCCESS + +**/ +VOID +SystemIioPortBifurcationInit ( + IN IIO_GLOBALS *IioGlobalData +) +{ + + UINT8 IioIndex; + IIO_BIFURCATION_ENTRY *BifurcationTable = NULL; + UINT8 BifurcationEntries; + IIO_SLOT_CONFIG_ENTRY *SlotTable = NULL; + UINT8 SlotEntries; + + // This function outline: + // 1. Based on platform apply the default bifurcation and slot configuration. + // 2. Apply dynamic overrides based on GPIO and other configurations. + // 3. Hide unused ports due bifurcation. + + SystemIioPortBifurcationInitCommon(IioGlobalData, &BifurcationTable, &BifurcationEntries, &SlotTable, &SlotEntries); + /// Set the default bifurcations for this platform. + SetBifurcations(IioGlobalData, BifurcationTable, BifurcationEntries); + ConfigSlots(IioGlobalData, SlotTable, SlotEntries); + OverrideConfigSlots(IioGlobalData, SlotTable, SlotEntries); + + // All overrides have been applied now. + // Hide root ports whose lanes are assigned preceding ports. + for (IioIndex = Iio_Socket0; IioIndex < MaxIIO; IioIndex++) { + if (IioGlobalData->IioVar.IioVData.SocketPresent[IioIndex]) { + SystemHideIioPortsCommon(IioGlobalData, IioIndex); + } + } +} + + +/** + + This function dump raw data. + + @param Data raw data + @param Size raw data size + +**/ +VOID +InternalDumpData ( + IN UINT8 *Data, + IN UINTN Size + ) +{ + UINTN Index; + for (Index = 0; Index < Size; Index++) { + DEBUG ((EFI_D_INFO, "%02x", (UINTN)Data[Index])); + } +} + +/** + + This function dump raw data with colume format. + + @param Data raw data + @param Size raw data size + +**/ +VOID +InternalDumpHex ( + IN UINT8 *Data, + IN UINTN Size + ) +{ + UINTN Index; + UINTN Count; + UINTN Left; + +#define COLUME_SIZE (16 * 2) + + Count = Size / COLUME_SIZE; + Left = Size % COLUME_SIZE; + for (Index = 0; Index < Count; Index++) { + DEBUG ((EFI_D_INFO, "%04x: ", Index * COLUME_SIZE)); + InternalDumpData (Data + Index * COLUME_SIZE, COLUME_SIZE); + DEBUG ((EFI_D_INFO, "\n")); + } + + if (Left != 0) { + DEBUG ((EFI_D_INFO, "%04x: ", Index * COLUME_SIZE)); + InternalDumpData (Data + Index * COLUME_SIZE, Left); + DEBUG ((EFI_D_INFO, "\n")); + } +} + +VOID +DumpConfig ( + VOID + ) +{ + DEBUG ((DEBUG_INFO, "PcdSetupData - 0x%x\n", PcdGetSize (PcdSetupData))); + InternalDumpHex (PcdGetPtr (PcdSetupData), PcdGetSize (PcdSetupData)); + DEBUG ((DEBUG_INFO, "PcdPchRcConfigurationData - 0x%x\n", PcdGetSize (PcdPchRcConfigurationData))); + InternalDumpHex (PcdGetPtr (PcdPchRcConfigurationData), PcdGetSize (PcdPchRcConfigurationData)); + DEBUG ((DEBUG_INFO, "PcdSocketIioConfigData - 0x%x\n", PcdGetSize (PcdSocketIioConfigData))); + InternalDumpHex (PcdGetPtr (PcdSocketIioConfigData), PcdGetSize (PcdSocketIioConfigData)); + DEBUG ((DEBUG_INFO, "PcdSocketCommonRcConfigData - 0x%x\n", PcdGetSize (PcdSocketCommonRcConfigData))); + InternalDumpHex (PcdGetPtr (PcdSocketCommonRcConfigData), PcdGetSize (PcdSocketCommonRcConfigData)); + DEBUG ((DEBUG_INFO, "PcdSocketMpLinkConfigData - 0x%x\n", PcdGetSize (PcdSocketMpLinkConfigData))); + InternalDumpHex (PcdGetPtr (PcdSocketMpLinkConfigData), PcdGetSize (PcdSocketMpLinkConfigData)); + DEBUG ((DEBUG_INFO, "PcdSocketMemoryConfigData - 0x%x\n", PcdGetSize (PcdSocketMemoryConfigData))); + InternalDumpHex (PcdGetPtr (PcdSocketMemoryConfigData), PcdGetSize (PcdSocketMemoryConfigData)); + DEBUG ((DEBUG_INFO, "PcdSocketPowerManagementConfigData - 0x%x\n", PcdGetSize (PcdSocketPowerManagementConfigData))); + InternalDumpHex (PcdGetPtr (PcdSocketPowerManagementConfigData), PcdGetSize (PcdSocketPowerManagementConfigData)); + DEBUG ((DEBUG_INFO, "PcdSocketProcessorCoreConfigData - 0x%x\n", PcdGetSize (PcdSocketProcessorCoreConfigData))); + InternalDumpHex (PcdGetPtr (PcdSocketProcessorCoreConfigData), PcdGetSize (PcdSocketProcessorCoreConfigData)); +} + +// +// PEI entry point - SystemBoardPpi entry point +// +/** + + PEI system board PPI intialization main entry point. This will setup up a PPI that will handle providing system board level + configuration for the platform. + + @param FileHandle Pointer to the PEIM FFS file header. + @param PeiServices General purpose services available to every PEIM. + + @retval EFI_SUCCESS Operation completed successfully. + @retval Otherwise System board initialization failed. +**/ +EFI_STATUS +EFIAPI +SystemBoardPeiEntry ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + + DEBUG ((EFI_D_ERROR, "--> SystemBoard PEI BoardDetection\n")); + + //DumpConfig (); + + // + // Initialize system board information PPI + // + Status = PeiServicesInstallPpi(&mSystemBoardPpiDesc); + ASSERT_EFI_ERROR (Status); + return Status; +} diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/SystemBoardPei.h b/Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/SystemBoardPei.h new file mode 100644 index 0000000000..bf2c9201c1 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/SystemBoardPei.h @@ -0,0 +1,188 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.
+This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _EFI_SYSTEM_BOARD_PPI_H_ +#define _EFI_SYSTEM_BOARD_PPI_H_ + +#include +#include +#include + + +// GUID +#include +#include + +// PPI +#include +#include +#include +#include + + +// Library +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +// CMOS access Port address +#define LAST_CMOS_BYTE 0x7F +#define NMI_OFF 0x80 +#define B_PCH_RTC_REGB_SRBRST 0x02 // Value to be reset to during POST +#define R_PCH_RTC_REGD 0x0D // CMOS Register D Status +#define R_PCH_RTC_REGE 0x0E // CMOS Register E Status +#define B_PCH_RTC_REGE_INVTIM 0x04 // CMOS invalid time found + +#define TIMER1_CONTROL_PORT 0x43 +#define TIMER1_COUNT_PORT 0x41 +#define LOAD_COUNTER1_LSB 0x54 +#define COUNTER1_COUNT 0x12 +// +// Reset Generator I/O Port +// +#define RESET_GENERATOR_PORT 0xCF9 + +//-----------------------------------------------------------------------; +// PCH: Chipset Configuration Register Equates +//-----------------------------------------------------------------------; +#define ICH_RCRB_IRQ0 0 +#define ICH_RCRB_IRQA 1 +#define ICH_RCRB_IRQB 2 +#define ICH_RCRB_IRQC 3 +#define ICH_RCRB_IRQD 4 +#define ICH_RCRB_PIRQA 0 +#define ICH_RCRB_PIRQB 1 +#define ICH_RCRB_PIRQC 2 +#define ICH_RCRB_PIRQD 3 +#define ICH_RCRB_PIRQE 4 +#define ICH_RCRB_PIRQF 5 +#define ICH_RCRB_PIRQG 6 +#define ICH_RCRB_PIRQH 7 + +// +// From WBG Soft Straps WIP.xlsx +// +#define WBG_DOWNSKU_STRAP_DSKU 0x80046000 +#define WBG_DOWNSKU_STRAP_BSKU 0x8004E003 +#define WBG_DOWNSKU_STRAP_TSKU 0x00044000 + +#define PCHSTRAP_9 9 +#define PCHSTRAP_10 10 +#define PCHSTRAP_16 16 +#define PCHSTRAP_17 17 + +#define RESET_PORT 0x0CF9 +#define CLEAR_RESET_BITS 0x0F1 +#define COLD_RESET 0x02 // Set bit 1 for cold reset +#define RST_CPU 0x04 // Setting this bit triggers a reset of the CPU +#define FULL_RESET 0x08 // Set bit 4 with bit 1 for full reset + +// +// PPI functions +// + +VOID +SetBifurcations( + IN OUT IIO_GLOBALS *IioGlobalData, + IN IIO_BIFURCATION_ENTRY *BifurcationTable, + IN UINT8 BifurcationEntries +); + +VOID +EnableHotPlug ( + IN OUT IIO_GLOBALS *IioGlobalData, + IN UINT8 Port, + IN UINT8 VppPort, + IN UINT8 VppAddress, + IN UINT8 PortOwnership + ); + + +VOID +ConfigSlots ( + IN OUT IIO_GLOBALS *IioGlobalData, + IN IIO_SLOT_CONFIG_ENTRY *Slot, + IN UINT8 SlotEntries + ); + +VOID +OverrideConfigSlots ( + IN OUT IIO_GLOBALS *IioGlobalData, + IN IIO_SLOT_CONFIG_ENTRY *Slot, + IN UINT8 SlotEntries + ); + +VOID +CalculatePEXPHideFromIouBif ( + IN UINT8 Iou, + IN UINT8 IioIndex, + IN OUT IIO_GLOBALS *IioGlobalData +); + +VOID +DumpIioConfiguration( + IN UINT8 iio, + IN IIO_GLOBALS *IioGlobalData +); + +VOID +OverrideDefaultBifSlots( + IN IIO_GLOBALS *IioGlobalData +); + +UINT8 +GetUplinkPortInformationCommon ( + IN UINT8 IioIndex +); + +VOID +SystemIioPortBifurcationInitCommon ( + IIO_GLOBALS *IioGlobalData, + IIO_BIFURCATION_ENTRY **BifurcationTable, + UINT8 *BifurcationEntries, + IIO_SLOT_CONFIG_ENTRY **SlotTable, + UINT8 *SlotEntries +); + +VOID +SystemHideIioPortsCommon( + IIO_GLOBALS *IioGlobalData, + UINT8 IioIndex +); + +UINT8 +GetUplinkPortInformation ( + IN UINT8 IioIndex +); + +VOID +SystemIioPortBifurcationInit ( + IN IIO_GLOBALS *IioGlobalData + ); + +#endif diff --git a/Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/SystemBoardPei.inf b/Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/SystemBoardPei.inf new file mode 100644 index 0000000000..6b1202bfa8 --- /dev/null +++ b/Platform/Intel/PurleyOpenBoardPkg/Policy/SystemBoard/SystemBoardPei.inf @@ -0,0 +1,84 @@ +### @file +# +# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +### + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SystemBoardPei + FILE_GUID = C0989520-2F0D-470a-9BE4-2969E0EC5641 + MODULE_TYPE = PEIM + ENTRY_POINT = SystemBoardPeiEntry + +[Sources] + SystemBoardPei.c + SystemBoardCommon.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + LewisburgPkg/PchRcPkg.dec + PurleyOpenBoardPkg/PlatPkg.dec + PurleySktPkg/SocketPkg.dec + PurleyRcPkg/RcPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + MemoryAllocationLib + PeiServicesLib + PeimEntryPoint + DebugLib + HobLib + IoLib + PciLib + PcdLib + PeiServicesTablePointerLib + PciExpressLib + PchInfoLib + GpioLib + TimerLib + PchCycleDecodingLib + PchSbiAccessLib + PchInfoLib + PchP2sbLib + PchPcrLib + MmPciLib + PcdLib + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gOemSkuTokenSpaceGuid.PcdIioBifurcationTable + gOemSkuTokenSpaceGuid.PcdIioBifurcationTableEntries + gOemSkuTokenSpaceGuid.PcdIioSlotTable + gOemSkuTokenSpaceGuid.PcdIioSlotTableEntries + gOemSkuTokenSpaceGuid.PcdOemSkuUplinkPortIndex + + gOemSkuTokenSpaceGuid.PcdSetupData + gOemSkuTokenSpaceGuid.PcdPchRcConfigurationData + gOemSkuTokenSpaceGuid.PcdSocketIioConfigData + gOemSkuTokenSpaceGuid.PcdSocketCommonRcConfigData + gOemSkuTokenSpaceGuid.PcdSocketMpLinkConfigData + gOemSkuTokenSpaceGuid.PcdSocketMemoryConfigData + gOemSkuTokenSpaceGuid.PcdSocketPowerManagementConfigData + gOemSkuTokenSpaceGuid.PcdSocketProcessorCoreConfigData + + +[Ppis] + gEfiPeiSystemBoardPpiGuid ## PRODUCES + gEfiPeiSmbus2PpiGuid + gPchPlatformPolicyPpiGuid + +[Depex] + gEfiPeiPcdPpiGuid AND + gEfiPeiReadOnlyVariable2PpiGuid + -- cgit v1.2.3