From 9d636f57f40641dc4d2bb6294e51acc301e58db4 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Tue, 6 Oct 2015 12:51:07 +0000 Subject: ArmPkg/AArch64Mmu: remove cache maintenance for page tables All our page tables are allocated from memory whose cacheability attributes are inherited by the cacheability bits in the MMU control register, so there is no need for explicit cache maintenance after updating the page tables. And even if there were, Set/Way operations are not appropriate anyway for ensuring that these changes make it to main memory. So just remove the explicit cache maintenance completely. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18570 6f19259b-4bc3-4df7-8a09-765794883524 --- ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c index b2ab5aa7bb..3765d61ccd 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c @@ -493,12 +493,6 @@ SetMemoryAttributes ( return Status; } - // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks - // flush and invalidate pages - ArmCleanInvalidateDataCache (); - - ArmInvalidateInstructionCache (); - // Invalidate all TLB entries so changes are synced ArmInvalidateTlb (); -- cgit v1.2.3