From a08d03e7d2d58467cf199ee022fd85040408da00 Mon Sep 17 00:00:00 2001 From: Guo Mang Date: Thu, 2 Jun 2016 13:04:00 +0800 Subject: ChvRefCodePkg: Add includes files Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang --- .../CherryViewSoc/CPU/Include/CpuDataStruct.h | 122 +++++ .../CherryViewSoc/CPU/Include/CpuPpmLib.h | 187 +++++++ ChvRefCodePkg/CherryViewSoc/CPU/Include/CpuRegs.h | 597 +++++++++++++++++++++ .../CherryViewSoc/CPU/Include/Guid/HtBistHob.h | 21 + .../CPU/Include/Guid/PlatformCpuInfo.h | 196 +++++++ .../Include/Guid/PowerManagementAcpiTableStorage.h | 24 + .../CPU/Include/Library/StallSmmLib.h | 38 ++ .../CherryViewSoc/CPU/Include/MchPpmLib.h | 80 +++ .../CherryViewSoc/CPU/Include/MmioAccess.h | 84 +++ .../CherryViewSoc/CPU/Include/Ppi/Cache.h | 59 ++ .../CPU/Include/Ppi/CpuPlatformPolicyPpi.h | 73 +++ .../CherryViewSoc/CPU/Include/PpmCommon.h | 114 ++++ ChvRefCodePkg/CherryViewSoc/CPU/Include/Pram.h | 41 ++ .../Include/Protocol/CpuPlatformPolicyProtocol.h | 241 +++++++++ .../CPU/Include/Protocol/PpmPlatformPolicy.h | 125 +++++ .../CPU/Include/Protocol/PpmProcessorSupport2.h | 561 +++++++++++++++++++ 16 files changed, 2563 insertions(+) create mode 100644 ChvRefCodePkg/CherryViewSoc/CPU/Include/CpuDataStruct.h create mode 100644 ChvRefCodePkg/CherryViewSoc/CPU/Include/CpuPpmLib.h create mode 100644 ChvRefCodePkg/CherryViewSoc/CPU/Include/CpuRegs.h create mode 100644 ChvRefCodePkg/CherryViewSoc/CPU/Include/Guid/HtBistHob.h create mode 100644 ChvRefCodePkg/CherryViewSoc/CPU/Include/Guid/PlatformCpuInfo.h create mode 100644 ChvRefCodePkg/CherryViewSoc/CPU/Include/Guid/PowerManagementAcpiTableStorage.h create mode 100644 ChvRefCodePkg/CherryViewSoc/CPU/Include/Library/StallSmmLib.h create mode 100644 ChvRefCodePkg/CherryViewSoc/CPU/Include/MchPpmLib.h create mode 100644 ChvRefCodePkg/CherryViewSoc/CPU/Include/MmioAccess.h create mode 100644 ChvRefCodePkg/CherryViewSoc/CPU/Include/Ppi/Cache.h create mode 100644 ChvRefCodePkg/CherryViewSoc/CPU/Include/Ppi/CpuPlatformPolicyPpi.h create mode 100644 ChvRefCodePkg/CherryViewSoc/CPU/Include/PpmCommon.h create mode 100644 ChvRefCodePkg/CherryViewSoc/CPU/Include/Pram.h create mode 100644 ChvRefCodePkg/CherryViewSoc/CPU/Include/Protocol/CpuPlatformPolicyProtocol.h create mode 100644 ChvRefCodePkg/CherryViewSoc/CPU/Include/Protocol/PpmPlatformPolicy.h create mode 100644 ChvRefCodePkg/CherryViewSoc/CPU/Include/Protocol/PpmProcessorSupport2.h diff --git a/ChvRefCodePkg/CherryViewSoc/CPU/Include/CpuDataStruct.h b/ChvRefCodePkg/CherryViewSoc/CPU/Include/CpuDataStruct.h new file mode 100644 index 0000000000..3406f3991e --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/CPU/Include/CpuDataStruct.h @@ -0,0 +1,122 @@ +/** @file + The definition of CPU Data Structure. + + Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _CPU_DATA_STRUCT_H +#define _CPU_DATA_STRUCT_H + +#include +// +// The data saved in SMRAM. +// In S3 path, CPUS3 runs before SMMS3. SMRAM is open at that time. +// + +#define EFI_SMRAM_CPU_NVS_HEADER_GUID \ + { \ + 0x429501d9, 0xe447, 0x40f4, 0x86, 0x7b, 0x75, 0xc9, 0x3a, 0x1d, 0xb5, 0x4e \ + } + +typedef struct { + // + // Guid as Signature. + // + EFI_GUID HeaderGuid; + EFI_PHYSICAL_ADDRESS AcpiCpuPointer; + ACPI_CPU_DATA_COMPATIBILITY AcpiCpuData; + + // + // It points the data defined below. + // + EFI_PHYSICAL_ADDRESS GdtrProfileOffset; + EFI_PHYSICAL_ADDRESS GdtOffset; + EFI_PHYSICAL_ADDRESS IdtrProfileOffset; + EFI_PHYSICAL_ADDRESS IdtOffset; + EFI_PHYSICAL_ADDRESS CpuPrivateDataOffset; + EFI_PHYSICAL_ADDRESS S3BootScriptTableOffset; + EFI_PHYSICAL_ADDRESS S3BspMtrrTableOffset; + EFI_PHYSICAL_ADDRESS MicrocodePointerBufferOffset; // It is pointer to pointer array. + EFI_PHYSICAL_ADDRESS MicrocodeDataBufferOffset; // It is pointer to the data. + + // + // We need put all the data buffer here as well. + // These data will be copied to original location in S3. + // + + // + // DataBuffer size + // + UINT32 GdtrProfileSize; + UINT32 GdtSize; + UINT32 IdtrProfileSize; + UINT32 IdtSize; + UINT32 CpuPrivateDataSize; + UINT32 S3BootScriptTableSize; + UINT32 S3BspMtrrTableSize; + UINT32 MicrocodePointerBufferSize; + UINT32 MicrocodeDataBufferSize; +} SMRAM_CPU_DATA; + +typedef struct { + UINT32 RegEax; + UINT32 RegEbx; + UINT32 RegEcx; + UINT32 RegEdx; +} EFI_CPUID_REGISTER; + +typedef struct { + UINT32 HeaderVersion; + UINT32 UpdateRevision; + UINT32 Date; + UINT32 ProcessorId; + UINT32 Checksum; + UINT32 LoaderRevision; + UINT32 ProcessorFlags; + UINT32 DataSize; + UINT32 TotalSize; + UINT8 Reserved[12]; +} EFI_CPU_MICROCODE_HEADER; + +typedef struct { + UINT32 ExtSigCount; + UINT32 ExtChecksum; + UINT8 Reserved[12]; + UINT32 ProcessorId; + UINT32 ProcessorFlags; + UINT32 Checksum; +} EFI_CPU_MICROCODE_EXT_HEADER; + +typedef struct { + UINT32 ExtendedSignatureCount; + UINT32 ExtendedTableChecksum; + UINT8 Reserved[12]; +} EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER; + +typedef struct { + UINT32 ProcessorSignature; + UINT32 ProcessorFlag; + UINT32 ProcessorChecksum; +} EFI_CPU_MICROCODE_EXTENDED_TABLE; + +typedef struct { + UINT32 Stepping : 4; + UINT32 Model : 4; + UINT32 Family : 4; + UINT32 Type : 2; + UINT32 Reserved1 : 2; + UINT32 ExtendedModel : 4; + UINT32 ExtendedFamily : 8; + UINT32 Reserved2 : 4; +} EFI_CPU_VERSION; + +#endif diff --git a/ChvRefCodePkg/CherryViewSoc/CPU/Include/CpuPpmLib.h b/ChvRefCodePkg/CherryViewSoc/CPU/Include/CpuPpmLib.h new file mode 100644 index 0000000000..ed28d8592b --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/CPU/Include/CpuPpmLib.h @@ -0,0 +1,187 @@ +/** @file + IST/PPM reference code definitions. + + Acronyms: + PPM Platform Power Management + GV Geyserville + TM Thermal Monitor + IST Intel(R) Speedstep technology + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _CPU_PPM_LIB_H_ +#define _CPU_PPM_LIB_H_ + +// +// Statements that include other files +// +#include + +#include +#include + +// +// CPUID definitions +// +#define CPUID_EXT_FAMILY 0x0FF00000 +#define CPUID_EXT_MODEL 0x000F0000 +#define CPUID_FAMILY 0x00000F00 +#define CPUID_MODEL 0x000000F0 +#define CPUID_STEPPING 0x0000000F +#define CPUID_FAMILY_MODEL 0x00000FF0 +#define CPUID_FAMILY_MODEL_STEPPING 0x00000FFF +#define CPUID_FULL_FAMILY_MODEL 0x0FFF0FF0 +#define CPUID_FULL_FAMILY_MODEL_STEPPING 0x0FFF0FFF +#define CPUID_FULL_FAMILY_MODEL_VALLEVIEW 0x00030670 // Valleyview +// +// Structure declarations +// + +// +// UINT64 workaround +// +// The MS compiler doesn't handle QWORDs very well. I'm breaking +// them into DWORDs to circumvent the problems. Converting back +// shouldn't be a big deal. +// +#pragma pack(1) +typedef union _MSR_REGISTER { + UINT64 Qword; + + struct _DWORDS { + UINT32 Low; + UINT32 High; + } Dwords; + + struct _BYTES { + UINT8 FirstByte; + UINT8 SecondByte; + UINT8 ThirdByte; + UINT8 FouthByte; + UINT8 FifthByte; + UINT8 SixthByte; + UINT8 SeventhByte; + UINT8 EighthByte; + } Bytes; + +} MSR_REGISTER; +#pragma pack() + +typedef struct _EFI_MSR_VALUES{ + UINT16 Index; + UINT64 Value; +} EFI_MSR_VALUES; + +// +// Function prototypes +// +/** + Initializes the processor power management library. This must be called + prior to any of the library functions being used. + + At this time, we don't properly publish the PPM processor support protocol, + we simply return it if this library implements the protocol. + + If the processor is not supported, the input will not be modified. + + @param[in, out] This Pointer to the PPM support protocol instance + + @retval EFI_SUCCESS Library was initialized successfully + @retval EFI_NOT_SUPPORTED The library does not support the current processor + +**/ +EFI_STATUS +InitializePenrynPowerManagementLib ( + IN OUT PPM_PROCESSOR_SUPPORT_PROTOCOL_2 **This + ); +/** + Initializes the processor power management library. This must be called + prior to any of the library functions being used. + + At this time, we don't properly publish the PPM processor support protocol, + we simply return it if this library implements the protocol. + + If the processor is not supported, the input will not be modified. + + @param[in, out] This Pointer to the PPM support protocol instance + + @retval EFI_SUCCESS Library was initialized successfully + @retval EFI_NOT_SUPPORTED The library does not support the current processor + +**/ +EFI_STATUS +InitializeMeromPowerManagementLib ( + IN OUT PPM_PROCESSOR_SUPPORT_PROTOCOL_2 **This + ); + +/** + Initializes the processor power management library. This must be called + prior to any of the library functions being used. + + At this time, we don't properly publish the PPM processor support protocol, + we simply return it if this library implements the protocol. + + If the processor is not supported, the input will not be modified. + + @param[in, out] This Pointer to the PPM support protocol instance + + @retval EFI_SUCCESS Library was initialized successfully + @retval EFI_NOT_SUPPORTED The library does not support the current processor + +**/ +EFI_STATUS +InitializeYonahPowerManagementLib ( + IN OUT PPM_PROCESSOR_SUPPORT_PROTOCOL_2 **This + ); + +/** + Initializes the processor power management library. This must be called + prior to any of the library functions being used. + + At this time, we don't properly publish the PPM processor support protocol, + we simply return it if this library implements the protocol. + + If the processor is not supported, the input will not be modified. + + @param[in, out] This Pointer to the PPM support protocol instance + + @retval EFI_SUCCESS Library was initialized successfully + @retval EFI_NOT_SUPPORTED The library does not support the current processor + +**/ +EFI_STATUS +InitializeDothanPowerManagementLib ( + IN OUT PPM_PROCESSOR_SUPPORT_PROTOCOL_2 **This + ); + +/** + Initializes the processor power management library for Cherryview processors. + This must be called prior to any of the library functions being used. + + At this time, we don't properly publish the PPM processor support protocol, + we simply return it if this library implements the protocol. + + If the processor is not supported, the input will not be modified. + + @param[in, out] This Pointer to the PPM support protocol instance + + @retval EFI_SUCCESS Library was initialized successfully + @retval EFI_NOT_SUPPORTED The library does not support the current processor + +**/ +EFI_STATUS +InitializeCherryviewPowerManagementLib ( + IN OUT PPM_PROCESSOR_SUPPORT_PROTOCOL_2 **This + ); + +#endif diff --git a/ChvRefCodePkg/CherryViewSoc/CPU/Include/CpuRegs.h b/ChvRefCodePkg/CherryViewSoc/CPU/Include/CpuRegs.h new file mode 100644 index 0000000000..41ca96959c --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/CPU/Include/CpuRegs.h @@ -0,0 +1,597 @@ +/** @file + Definitions of CPU registers + + @brief + + Conventions: + + - Prefixes: + Definitions beginning with "MSR_" are MSRs + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + + Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _CPU_REGS_H_ +#define _CPU_REGS_H_ + +// +// Local APIC defines +// +#define APIC_REGISTER_LOCAL_ID_OFFSET 0x00000020 +#define APIC_REGISTER_APIC_VERSION_OFFSET 0x00000030 +#define APIC_REGISTER_SPURIOUS_VECTOR_OFFSET 0x000000F0 +#define APIC_REGISTER_ICR_LOW_OFFSET 0x00000300 +#define APIC_REGISTER_ICR_HIGH_OFFSET 0x00000310 +#define APIC_REGISTER_LINT0_VECTOR_OFFSET 0x00000350 +#define APIC_REGISTER_LINT1_VECTOR_OFFSET 0x00000360 + +#define BROADCAST_MODE_SPECIFY_CPU 0x00 +#define BROADCAST_MODE_ALL_INCLUDING_SELF 0x01 +#define BROADCAST_MODE_ALL_EXCLUDING_SELF 0x02 + +#ifndef DELIVERY_MODE_FIXED +#define DELIVERY_MODE_FIXED 0x0 +#endif +#ifndef DELIVERY_MODE_LOWEST_PRIORITY +#define DELIVERY_MODE_LOWEST_PRIORITY 0x1 +#endif +#ifndef DELIVERY_MODE_SMI +#define DELIVERY_MODE_SMI 0x2 +#endif +#ifndef DELIVERY_MODE_REMOTE_READ +#define DELIVERY_MODE_REMOTE_READ 0x3 +#endif +#ifndef DELIVERY_MODE_NMI +#define DELIVERY_MODE_NMI 0x4 +#endif +#ifndef DELIVERY_MODE_INIT +#define DELIVERY_MODE_INIT 0x5 +#endif +#ifndef DELIVERY_MODE_SIPI +#define DELIVERY_MODE_SIPI 0x6 +#endif +#ifndef DELIVERY_MODE_MAX +#define DELIVERY_MODE_MAX 0x7 +#endif + +#define EFI_CACHE_UNCACHEABLE 0 +#define EFI_CACHE_WRITECOMBINING 1 +#define EFI_CACHE_WRITETHROUGH 4 +#define EFI_CACHE_WRITEPROTECTED 5 +#define EFI_CACHE_WRITEBACK 6 + +// +// CPU Family, Model, Stepping values +// +#define EFI_CPUID_FAMILY_NEHALEM_UARCH 6 +#define EFI_CPUID_MODEL_BLOOMFIELD 0x1A +#define EFI_CPUID_MODEL_GAINESTOWN 0x1A +#define EFI_CPUID_MODEL_PINEVIEW 0x1C +#define EFI_CPUID_MODEL_ATOM 0x1C +#define EFI_CPUID_MODEL_CLARKSFIELD 0x1E +#define EFI_CPUID_MODEL_LYNNFIELD 0x1E +#define EFI_CPUID_MODEL_AUBURNDALE 0x1F +#define EFI_CPUID_MODEL_HAVENDALE 0x1F +#define EFI_CPUID_MODEL_CLARKDALE 0x25 // Havendale 32nm +#define EFI_CPUID_MODEL_NEHALEM_EX 0x2E +#define EFI_CPUID_MODEL_CEDARVIEW 0x36 +#define EFI_CPUID_MODEL_VALLEYVIEW 0x37 +#define EFI_CPUID_MODEL_CHERRYVIEW 0x38 + +#define EFI_CPUID_STEPPING_PINEVIEW_MIN 0x07 +#define EFI_CPUID_STEPPING_PINEVIEW_MAX 0x0F +#define EFI_CPUID_STEPPING_CEDARVIEW_MIN 0x00 +#define EFI_CPUID_STEPPING_CEDARVIEW_MAX 0x0F +#define EFI_CPUID_STEPPING_VALLEYVIEW_MIN 0x00 +#define EFI_CPUID_STEPPING_VALLEYVIEW_MAX 0x0F + +// +// CPUID defines +// +#define EFI_CPUID_SIGNATURE 0x0 + +#define EFI_CPUID_VERSION_INFO 0x1 +#define B_EFI_CPUID_VERSION_INFO_EAX_MASK 0x0FFF0FFF +#define B_EFI_CPUID_VERSION_INFO_EAX_FULL_FAMILY_MODEL_MASK 0x0FFF0FF0 +#define B_EFI_CPUID_VERSION_INFO_EAX_EXT_FAMILY_ID_MASK 0x0FF00000 +#define B_EFI_CPUID_VERSION_INFO_EAX_EXT_MODEL_ID_MASK 0x000F0000 +#define N_EFI_CPUID_VERSION_INFO_EAX_EXT_FAMILY_ID 20 +#define N_EFI_CPUID_VERSION_INFO_EAX_EXT_MODEL_ID 16 +#define N_EFI_CPUID_VERSION_INFO_EAX_TYPE 12 +#define N_EFI_CPUID_VERSION_INFO_EAX_FAMILY_ID 8 +#define N_EFI_CPUID_VERSION_INFO_EAX_MODEL 4 +#define N_EFI_CPUID_VERSION_INFO_EAX_STEPPING_ID 0 +#define B_EFI_CPUID_VERSION_INFO_EBX_DEFAULT_APIC_ID (BIT31 | BIT30 | BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24) +#define B_EFI_CPUID_VERSION_INFO_EBX_LOGICAL_CPU_PER_PACKAGE (BIT23 | BIT22 | BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16) +#define B_EFI_CPUID_VERSION_INFO_EBX_CLFLUSH_CHUNK_COUNT (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) +#define B_EFI_CPUID_VERSION_INFO_ECX_AES BIT25 +#define B_EFI_CPUID_VERSION_INFO_ECX_XAPIC BIT21 +#define B_EFI_CPUID_VERSION_INFO_ECX_SSE4_2 BIT20 +#define B_EFI_CPUID_VERSION_INFO_ECX_SSE4_1 BIT19 +#define B_EFI_CPUID_VERSION_INFO_ECX_DCA BIT18 +#define B_EFI_CPUID_VERSION_INFO_ECX_XTPR_UPDATE BIT14 +#define B_EFI_CPUID_VERSION_INFO_ECX_CMPXCHG16B BIT13 +#define B_EFI_CPUID_VERSION_INFO_ECX_L1_CONTEXT_ID BIT10 +#define B_EFI_CPUID_VERSION_INFO_ECX_SUP_SSE3 BIT9 +#define B_EFI_CPUID_VERSION_INFO_ECX_TM2 BIT8 +#define B_EFI_CPUID_VERSION_INFO_ECX_EIST BIT7 +#define B_EFI_CPUID_VERSION_INFO_ECX_SME BIT6 +#define B_EFI_CPUID_VERSION_INFO_ECX_VME BIT5 +#define B_EFI_CPUID_VERSION_INFO_ECX_QPL BIT4 +#define B_EFI_CPUID_VERSION_INFO_ECX_MWAIT BIT3 +#define B_EFI_CPUID_VERSION_INFO_ECX_SSE3 BIT0 +#define B_EFI_CPUID_VERSION_INFO_EDX_PBE BIT31 +#define B_EFI_CPUID_VERSION_INFO_EDX_THERMAL_CLOCK_CONTROL BIT29 +#define B_EFI_CPUID_VERSION_INFO_EDX_HT BIT28 +#define B_EFI_CPUID_VERSION_INFO_EDX_SELF_SNOOP BIT27 +#define B_EFI_CPUID_VERSION_INFO_EDX_SSE2 BIT26 +#define B_EFI_CPUID_VERSION_INFO_EDX_SSE BIT25 +#define B_EFI_CPUID_VERSION_INFO_EDX_FAST_SAVE_RESTORE BIT24 +#define B_EFI_CPUID_VERSION_INFO_EDX_MMX BIT23 +#define B_EFI_CPUID_VERSION_INFO_EDX_ACPI_SUPPORT BIT22 +#define B_EFI_CPUID_VERSION_INFO_EDX_DEBUG_TRACE_STORE BIT21 +#define B_EFI_CPUID_VERSION_INFO_EDX_XD BIT20 +#define B_EFI_CPUID_VERSION_INFO_EDX_CLFLUSH_INTR BIT19 +#define B_EFI_CPUID_VERSION_INFO_EDX_CPU_SERIAL_NUMBER BIT18 +#define B_EFI_CPUID_VERSION_INFO_EDX_PSE BIT17 +#define B_EFI_CPUID_VERSION_INFO_EDX_PAT BIT16 +#define B_EFI_CPUID_VERSION_INFO_EDX_CON_MOVE_INTR BIT15 +#define B_EFI_CPUID_VERSION_INFO_EDX_MCA BIT14 +#define B_EFI_CPUID_VERSION_INFO_EDX_PGE BIT13 +#define B_EFI_CPUID_VERSION_INFO_EDX_MTRR BIT12 +#define B_EFI_CPUID_VERSION_INFO_EDX_SEP BIT11 +#define B_EFI_CPUID_VERSION_INFO_EDX_ON_CHIP_APIC BIT9 +#define B_EFI_CPUID_VERSION_INFO_EDX_CMPXCHG8 BIT8 +#define B_EFI_CPUID_VERSION_INFO_EDX_MCE BIT7 +#define B_EFI_CPUID_VERSION_INFO_EDX_PAE BIT6 +#define B_EFI_CPUID_VERSION_INFO_EDX_MSR BIT5 +#define B_EFI_CPUID_VERSION_INFO_EDX_TIME_STAMP_COUNTER BIT4 +#define B_EFI_CPUID_VERSION_INFO_EDX_PAGE_SIZE_EXT BIT3 +#define B_EFI_CPUID_VERSION_INFO_EDX_DEBUG_EXT BIT2 +#define B_EFI_CPUID_VERSION_INFO_EDX_VME_8086 BIT1 +#define B_EFI_CPUID_VERSION_INFO_EDX_FP_386 BIT0 + +#define EFI_CPUID_CACHE_INFO 0x2 +#define EFI_CPUID_SERIAL_NUMBER 0x3 + +#define EFI_CPUID_CACHE_PARAMS 0x4 +#define B_EFI_CPUID_CACHE_PARAMS_EAX_MAX_CORES_IN_PACKAGE (BIT31 | BIT30 | BIT29 | BIT28 | BIT27 | BIT26) +#define B_EFI_CPUID_CACHE_PARAMS_EAX_TOTAL_THREADS_SHARE_CACHE (BIT25 | BIT24 | BIT23 | BIT22 | BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16 | BIT15 | BIT14) +#define B_EFI_CPUID_CACHE_PARAMS_EAX_FULLY_ASSOCIATIVE_CACHE BIT9 +#define B_EFI_CPUID_CACHE_PARAMS_EAX_SELF_INITIALIZING BIT8 +#define B_EFI_CPUID_CACHE_PARAMS_EAX_CACHE_LEVEL (BIT7 | BIT6 | BIT5) +#define B_EFI_CPUID_CACHE_PARAMS_EAX_CACHE_TYPE (BIT4 | BIT3 | BIT2 | BIT1 | BIT0) +#define B_EFI_CPUID_CACHE_PARAMS_EBX_WAYS_OF_ASSOCIATIVITY (BIT31 | BIT30 | BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24 | BIT23 | BIT22) +#define B_EFI_CPUID_CACHE_PARAMS_EBX_PHYSICAL_LINE_PARTITIONS (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16 | BIT15 | BIT14 | BIT13 | BIT12) +#define B_EFI_CPUID_CACHE_PARAMS_EBX_SYSTEM_COHERENCY_LINE_SIZE (BIT11 | BIT10 | BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0) +#define B_EFI_CPUID_CACHE_PARAMS_EDX_PREFETCH_STRIDE (BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0) +#define B_EFI_CPUID_CACHE_PARAMS_EDX_CACHE_INCLUSIVE_IN_LOWER_CACHE BIT1 +#define B_EFI_CPUID_CACHE_PARAMS_EDX_WBINVD_INVD_ON_LOWER_CACHE BIT0 +#define V_CPUID_CACHE_TYPE_MASK 0x1F +#define B_CPUID_CACHE_TYPE_DATA 0x1 +#define B_CPUID_CACHE_TYPE_INSTRUCTION 0x2 +#define B_CPUID_CACHE_TYPE_UNIFIED 0x3 +#define V_CPUID_CACHE_LEVEL_MASK 0xE0 +#define B_CPUID_CACHE_LEVEL_SHIFT 5 +#define B_CPUID_CACHE_PARAMS_WAYS_SHIFT 22 +#define B_CPUID_CACHE_PARAMS_PARTITIONS_SHIFT 12 + +#define EFI_CPUID_MONITOR_MWAIT_PARAMS 0x5 +#define B_EFI_CPUID_MONITOR_MWAIT_ECX_INTERRUPTS_BREAK_MWAIT BIT1 +#define B_EFI_CPUID_MONITOR_MWAIT_ECX_MWAIT_SUPPORT BIT0 +#define B_EFI_CPUID_MONITOR_MWAIT_EDX_PARAMS_C7 (BIT31 | BIT30 | BIT29 | BIT28) +#define N_EFI_CPUID_MONITOR_MWAIT_EDX_PARAMS_C7 28 +#define B_EFI_CPUID_MONITOR_MWAIT_EDX_PARAMS_C6 (BIT27 | BIT26 | BIT25 | BIT24) +#define N_EFI_CPUID_MONITOR_MWAIT_EDX_PARAMS_C6 24 +#define B_EFI_CPUID_MONITOR_MWAIT_EDX_PARAMS_C5 (BIT23 | BIT22 | BIT21 | BIT20) +#define N_EFI_CPUID_MONITOR_MWAIT_EDX_PARAMS_C5 20 +#define B_EFI_CPUID_MONITOR_MWAIT_EDX_PARAMS_C4 (BIT19 | BIT18 | BIT17 | BIT16) +#define N_EFI_CPUID_MONITOR_MWAIT_EDX_PARAMS_C4 16 +#define B_EFI_CPUID_MONITOR_MWAIT_EDX_PARAMS_C3 (BIT15 | BIT14 | BIT13 | BIT12) +#define N_EFI_CPUID_MONITOR_MWAIT_EDX_PARAMS_C3 12 +#define B_EFI_CPUID_MONITOR_MWAIT_EDX_PARAMS_C2 (BIT11 | BIT10 | BIT9 | BIT8) +#define N_EFI_CPUID_MONITOR_MWAIT_EDX_PARAMS_C2 8 +#define B_EFI_CPUID_MONITOR_MWAIT_EDX_PARAMS_C1 (BIT7 | BIT6 | BIT5 | BIT4) +#define N_EFI_CPUID_MONITOR_MWAIT_EDX_PARAMS_C1 4 +#define B_EFI_CPUID_MONITOR_MWAIT_EDX_PARAMS_C0 (BIT3 | BIT2 | BIT1 | BIT0) +#define N_EFI_CPUID_MONITOR_MWAIT_EDX_PARAMS_C0 0 + +#define EFI_CPUID_POWER_MANAGEMENT_PARAMS 0x6 +#define EFI_CPUID_POWER_MANAGEMENT_EAX_PECI BIT0 +#define EFI_CPUID_POWER_MANAGEMENT_EBX_NUM_INT_THRESHOLDS (BIT3 | BIT2 | BIT1 | BIT0) +#define EFI_CPUID_POWER_MANAGEMENT_ECX_HW_COORDINATION_FEEDBACK BIT0 + +#define EFI_CPUID_REV7 0x7 +#define EFI_CPUID_REV8 0x8 +#define EFI_CPUID_DCA_PARAMS 0x9 +#define EFI_CPUID_ARCH_PERF_MON 0xA +#define EFI_CPUID_CORE_TOPOLOGY 0xB + +#define EFI_CPUID_EXTENDED_FUNCTION 0x80000000 + +#define EFI_CPUID_EXTENDED_FEATURE_BITS 0x80000001 +#define EFI_CPUID_EXTENDED_FEATURE_BITS_ECX_LAHF_SAHF BIT0 +#define EFI_CPUID_EXTENDED_FEATURE_BITS_EDX_XD BIT20 +#define EFI_CPUID_EXTENDED_FEATURE_BITS_EDX_SYSCALL BIT11 + +// +// This constant defines the maximum length of the CPU brand string. According to the +// IA manual, the brand string is in EAX through EDX (thus 16 bytes) after executing +// the CPUID instructions with EAX as 80000002, 80000003, 80000004. +// +#define MAXIMUM_CPU_BRAND_STRING_LENGTH 48 + +#define EFI_CPUID_BRAND_STRING1 0x80000002 +#define EFI_CPUID_BRAND_STRING2 0x80000003 +#define EFI_CPUID_BRAND_STRING3 0x80000004 + +#define EFI_CPUID_ADVANCED_POWER_MANAGEMENT 0x80000007 +#define EFI_CPUID_ADVANCED_POWER_MANAGEMENT_EDX_TSC_INVARIANCE BIT8 + +#define EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE 0x80000008 +#define B_EFI_CPUID_VIRTUAL_ADDRESS_BITS (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) +#define B_EFI_CPUID_PHYSICAL_ADDRESS_BITS (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0) + +// +// Common MSR +// +//#define EFI_MSR_IA32_PLATFORM_ID 0x00000017 +#define N_EFI_MSR_IA32_PLATFORM_ID_PLATFORM_ID_BITS 50 +#define B_EFI_MSR_IA32_PLATFORM_ID_PLATFORM_ID_BITS_MASK (BIT52 | BIT51 | BIT50) +#define N_EFI_MSR_IA32_PLATFORM_ID_PLATFORM_ID_BITS_MASK_START 50 +#define N_EFI_MSR_IA32_PLATFORM_ID_PLATFORM_ID_BITS_MASK_END 52 + +#ifndef EFI_MSR_IA32_APIC_BASE +#define EFI_MSR_IA32_APIC_BASE 0x0000001B + +#define B_EFI_MSR_IA32_APIC_BASE_APIC_BASE_ADDRESS 0xFFFFFF000 //For Nehalem, base address can be up to 43 bits but not cover here yet +#define B_EFI_MSR_IA32_APIC_BASE_APIC_GLOBAL_ENABLE BIT11 +#define B_EFI_MSR_IA32_APIC_BASE_M_XAPIC BIT10 +#define B_EFI_MSR_IA32_APIC_BASE_BSP BIT8 +#endif // EFI_MSR_IA32_APIC_BASE +// +// Local APIC defines, offset from APIC base address +// +#define APIC_REGISTER_LOCAL_ID_OFFSET 0x00000020 +#define N_APIC_REGISTER_LOCAL_ID_OFFSET_XAPIC_ID_MASK 24 +#define B_APIC_REGISTER_LOCAL_ID_OFFSET_XAPIC_ID_MASK 0xFF000000 + +#define APIC_REGISTER_APIC_VERSION_OFFSET 0x00000030 +#define B_APIC_REGISTER_APIC_VERSION_OFFSET_VERSION_MASK 0xFF + +#define APIC_REGISTER_SPURIOUS_VECTOR_OFFSET 0x000000F0 +#define APIC_REGISTER_ICR_LOW_OFFSET 0x00000300 +#define APIC_REGISTER_ICR_HIGH_OFFSET 0x00000310 +#define APIC_REGISTER_LINT0_VECTOR_OFFSET 0x00000350 +#define APIC_REGISTER_LINT1_VECTOR_OFFSET 0x00000360 + +#define EFI_MSR_IA32_FEATURE_CONTROL 0x0000003A +#define B_EFI_MSR_IA32_FEATURE_CONTROL_SGE BIT15 +#define B_EFI_MSR_IA32_FEATURE_CONTROL_SLFE (BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) +#define B_EFI_MSR_IA32_FEATURE_CONTROL_SMRR BIT3 +#define B_EFI_MSR_IA32_FEATURE_CONTROL_EVT BIT2 +#define B_EFI_MSR_IA32_FEATURE_CONTROL_ELT BIT1 +#define B_EFI_MSR_IA32_FEATURE_CONTROL_LOCK BIT0 +#define B_EFI_MSR_IA32_FEATURE_CONTROL_VT_SECURE 0x0000FF02 + +#ifndef EFI_MSR_IA32_BIOS_UPDT_TRIG +#define EFI_MSR_IA32_BIOS_UPDT_TRIG 0x00000079 +#endif +#ifndef EFI_MSR_IA32_BIOS_SIGN_ID +#define EFI_MSR_IA32_BIOS_SIGN_ID 0x0000008B +#endif + +#define EFI_MSR_PMG_CST_CONFIG 0x000000E2 +#define B_EFI_MSR_PMG_CST_CONFIG_CST_CONTROL_LOCK BIT15 +#define B_EFI_MSR_PMG_CST_CONFIG_IO_MWAIT_REDIRECTION_ENABLE BIT10 +#define B_EFI_MSR_PMG_CST_CONFIG_PACKAGE_C_STATE_LIMIT (BIT2 | BIT1 | BIT0) + +#define EFI_MSR_PMG_IO_CAPTURE_ADDR 0x000000E4 //For Nehalem Spec: EFI_IA32_PMG_IO_CAPTURE_BASE +#define N_EFI_MSR_PMG_IO_CAPTURE_ADDR_CST_RANGE 16 +#define B_EFI_MSR_PMG_IO_CAPTURE_ADDR_LVL_2_BASE_ADDRESS_MASK 0xFFFF + +#define EFI_MSR_IA32_MPERF 0x000000E7 +#define EFI_MSR_IA32_APERF 0x000000E8 + +#define EFI_MSR_IA32_MTRR_CAP 0x000000FE +#define B_EFI_MSR_IA32_MTRR_CAP_EMRR_SUPPORT BIT12 +#define B_EFI_MSR_IA32_MTRR_CAP_SMRR_SUPPORT BIT11 +#define B_EFI_MSR_IA32_MTRR_CAP_WC_SUPPORT BIT10 +#define B_EFI_MSR_IA32_MTRR_CAP_FIXED_SUPPORT BIT8 +#define B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0) + +#define EFI_MSR_IA32_MCG_CAP 0x00000179 +#define EFI_MSR_IA32_MCG_STATUS 0x0000017A + +#define EFI_MSR_CLOCK_FLEX_MAX 0x00000194 +#define B_EFI_MSR_CLOCK_FLEX_MAX_FLEX_EN BIT16 +#define B_EFI_MSR_CLOCK_FLEX_MAX_FLEX_RATIO_MASK 0x1F +#define N_EFI_MSR_CLOCK_FLEX_MAX_FLEX_RATIO 8 + +#define EFI_MSR_IA32_PERF_STS 0x00000198 +#define EFI_MSR_IA32_PERF_CTRL 0x00000199 + +#ifndef EFI_MSR_IA32_THERM_INTERRUPT +#define EFI_MSR_IA32_THERM_INTERRUPT 0x0000019B +#endif + +#define B_EFI_MSR_IA32_THERM_INTERRUPT_VIE BIT4 + +#ifndef EFI_MSR_IA32_THERM_STATUS +#define EFI_MSR_IA32_THERM_STATUS 0x0000019C +#endif + +#ifndef EFI_MSR_IA32_MISC_ENABLE +#define EFI_MSR_IA32_MISC_ENABLE 0x000001A0 +#endif + +#define B_EFI_MSR_IA32_MISC_ENABLE_XD BIT34 +#define B_EFI_MSR_IA32_MISC_ENABLE_CPUID_MAX BIT22 +#define B_EFI_MSR_IA32_MISC_ENABLE_MONITOR BIT18 +#define B_EFI_MSR_IA32_MISC_ENABLE_EIST BIT16 +#define B_EFI_MSR_IA32_MISC_ENABLE_TM1_EN BIT3 + +#define EFI_MSR_SMRR_PHYS_BASE 0x000001F2 //0x000000A0 +#define EFI_MSR_SMRR_PHYS_MASK 0x000001F3 //0x000000A1 +#define EFI_MSR_EMRR_PHYS_BASE 0x000001F4 +#define EFI_MSR_EMRR_PHYS_MASK 0x000001F5 + +#define EFI_MSR_CACHE_VARIABLE_MTRR_BASE 0x00000200 +#define EFI_MSR_CACHE_VARIABLE_MTRR_END 0x0000020F +#define V_EFI_FIXED_MTRR_NUMBER 11 + +#define EFI_MSR_IA32_MTRR_FIX64K_00000 0x00000250 +#define EFI_MSR_IA32_MTRR_FIX16K_80000 0x00000258 +#define EFI_MSR_IA32_MTRR_FIX16K_A0000 0x00000259 +#define EFI_MSR_IA32_MTRR_FIX4K_C0000 0x00000268 +#define EFI_MSR_IA32_MTRR_FIX4K_C8000 0x00000269 +#define EFI_MSR_IA32_MTRR_FIX4K_D0000 0x0000026A +#define EFI_MSR_IA32_MTRR_FIX4K_D8000 0x0000026B +#define EFI_MSR_IA32_MTRR_FIX4K_E0000 0x0000026C +#define EFI_MSR_IA32_MTRR_FIX4K_E8000 0x0000026D +#define EFI_MSR_IA32_MTRR_FIX4K_F0000 0x0000026E +#define EFI_MSR_IA32_MTRR_FIX4K_F8000 0x0000026F +#define EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE 0x000002FF +#define B_EFI_MSR_CACHE_MTRR_VALID BIT11 +#define B_EFI_MSR_GLOBAL_MTRR_ENABLE BIT11 +#define B_EFI_MSR_FIXED_MTRR_ENABLE BIT10 +#define B_EFI_MSR_CACHE_MEMORY_TYPE (BIT2 | BIT1 | BIT0) + +#define EFI_MSR_VALID_MASK 0xFFFFFFFFF +#define EFI_CACHE_VALID_ADDRESS 0xFFFFFF000 +#define EFI_SMRR_CACHE_VALID_ADDRESS 0xFFFFF000 +#define EFI_CACHE_VALID_EXTENDED_ADDRESS 0xFFFFFFFFFF000 + +// Leave one MTRR pairs for OS use +#define EFI_CACHE_NUM_VAR_MTRR_PAIRS_FOR_OS 1 +#define EFI_CACHE_LAST_VARIABLE_MTRR_FOR_BIOS (EFI_MSR_CACHE_VARIABLE_MTRR_END) - \ + (EFI_CACHE_NUM_VAR_MTRR_PAIRS_FOR_OS * 2) + +#define EFI_MSR_IA32_MC0_CTL 0x00000400 +#define EFI_MSR_IA32_MC0_STATUS 0x00000401 +#define EFI_MSR_IA32_MC0_ADDR 0x00000402 +#define EFI_MSR_IA32_MC0_MISC 0x00000403 +#define EFI_MSR_IA32_MC8_CTL (EFI_IA32_MC0_CTL + (8*4)) +#define EFI_MSR_IA32_MC8_STATUS (EFI_IA32_MC0_STATUS + (8*4)) + +// +// MSR specific for Pineview +// +#ifndef EFI_MSR_IA32_PLATFORM_ID +#define EFI_MSR_IA32_PLATFORM_ID 0x00000017 + +#define B_EFI_MSR_IA32_PLATFORM_ID_MOBILE_PROCESSOR BIT28 +#define V_EFI_MSR_IA32_PLATFORM_ID_MOBILE_PROCESSOR BIT28 +#define B_EFI_MSR_IA32_PLATFORM_ID_PRODUCTION BIT27 +#define B_EFI_MSR_IA32_PLATFORM_ID_THERMAL_MONITOR_DISABLED BIT19 +#define B_EFI_MSR_IA32_PLATFORM_ID_EIST_DISABLED BIT17 +#define B_EFI_MSR_IA32_PLATFORM_ID_RATIO_LOCKED BIT15 +#define N_EFI_MSR_IA32_PLATFORM_ID_MAX_BUS_RATIO 8 +#define B_EFI_MSR_IA32_PLATFORM_ID_MAX_BUS_RATIO_MASK (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) +#define B_EFI_MSR_IA32_PLATFORM_ID_MAX_VID_MASK (BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0) +#endif // EFI_MSR_IA32_PLATFORM_ID + +#define EFI_MSR_EBL_CR_POWERON 0x0000002A +#define B_EFI_MSR_EBL_CR_POWERON_EXECUTEBIST BIT9 + +#ifndef EFI_MSR_IA32_FEATURE_CONTROL +#define EFI_MSR_IA32_FEATURE_CONTROL 0x0000003A +#endif +#define B_EFI_MSR_IA32_FEATURE_CONTROL_C_STATE_SMI BIT16 + +#ifndef EFI_MSR_PMG_CST_CONFIG +#define EFI_MSR_PMG_CST_CONFIG 0x000000E2 +#endif +#define B_EFI_MSR_PMG_CST_CONFIG_L2_SHRINK_THRESHOLD_MASK (BIT20 | BIT19 | BIT18 | BIT17 | BIT16) +#define B_EFI_MSR_PMG_CST_CONFIG_EIST_HARWARE_COORDINATION BIT11 + +#define EFI_BBL_CR_CTL3 0x0000011E +#define B_EFI_BBL_CR_CTL3_L2_WAY_SHRINK_MIN (BIT31 | BIT30) +#define B_EFI_BBL_CR_CTL3_L2_WAY_SHRINK_RATE (BIT29 | BIT28) +#define B_EFI_BBL_CR_CTL3_L2_WAY_CHUNK_SIZE (BIT27 | BIT26 | BIT25) +#define B_EFI_BBL_CR_CTL3_L2_REDUCTION_CONF_LOCK BIT24 +#define B_EFI_BBL_CR_CTL3_L2_NOT_PRESENT BIT23 +#define B_EFI_BBL_CR_CTL3_SIZE_OF_WAY (BIT17 | BIT16 | BIT15 | BIT14 | BIT13) +#define B_EFI_BBL_CR_CTL3_L2_ENABLED BIT8 +#define B_EFI_BBL_CR_CTL3_NUMBER_OF_WAYS (BIT4 | BIT3 | BIT2 | BIT1) +#define B_EFI_BBL_CR_CTL3_L2_HW_ENABLED BIT0 + +#ifndef EFI_MSR_IA32_PERF_STS +#define EFI_MSR_IA32_PERF_STS 0x00000198 +#endif + +#define B_EFI_MSR_IA32_PERF_STS_BUS_RATIO_BOOT (BIT60 | BIT59 | BIT58 | BIT57 | BIT56) +#define B_EFI_MSR_IA32_PERF_STS_VID_BOOT (BIT53 | BIT52 | BIT51 | BIT50 | BIT49 | BIT48) +#define B_EFI_MSR_IA32_PERF_STS_BUS_RATIO_MAX (BIT44 | BIT43 | BIT42 | BIT41 | BIT40) +#define B_EFI_MSR_IA32_PERF_STS_VID_MAX (BIT37 | BIT36 | BIT35 | BIT34 | BIT33 | BIT32) +#define N_EFI_MSR_IA32_PERF_STS_BUT_RATIO_MIN 24 +#define B_EFI_MSR_IA32_PERF_STS_BUT_RATIO_MIN_MASK (BIT28 | BIT27 | BIT26 | BIT25 | BIT24) +#define B_EFI_MSR_IA32_PERF_STS_TS BIT21 +#define B_EFI_MSR_IA32_PERF_STS_CMD_SEEK BIT20 +#define B_EFI_MSR_IA32_PERF_STS_THERM_THROT BIT19 +#define B_EFI_MSR_IA32_PERF_STS_TT BIT18 +#define B_EFI_MSR_IA32_PERF_STS_VIP BIT17 +#define B_EFI_MSR_IA32_PERF_STS_FIP BIT16 +#define B_EFI_MSR_IA32_PERF_STS_BUS_RATIO_STS (BIT12 | BIT11 | BIT10 | BIT9 | BIT8) +#define N_EFI_MSR_IA32_PERF_STS_BUS_RATIO_STS 8 +#define B_EFI_MSR_IA32_PERF_STS_VID_STS (BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0) + +#ifndef EFI_MSR_IA32_PERF_CTRL +#define EFI_MSR_IA32_PERF_CTRL 0x00000199 +#endif + +#define B_EFI_MSR_IA32_PERF_CTRL_BUS_RATIO_SEL (BIT12 | BIT11 | BIT10 | BIT9 | BIT8) +#define B_EFI_MSR_IA32_PERF_CTRL_VID_SEL (BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0) + +#define EFI_MSR_THERM2_CTL 0x0000019D +#define B_EFI_MSR_THERM2_CTL_BUS_RATIO_THROT (BIT12 | BIT11 | BIT10 | BIT9 | BIT8) +#define B_EFI_MSR_THERM2_CTL_VID_THROT (BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0) + +#ifndef EFI_MSR_IA32_MISC_ENABLE +#define EFI_MSR_IA32_MISC_ENABLE 0x000001A0 +#endif +#define B_EFI_MSR_IA32_MISC_ENABLE_HARD_C4E_EN BIT33 +#define B_EFI_MSR_IA32_MISC_ENABLE_C4E_EN BIT32 +#define B_EFI_MSR_IA32_MISC_ENABLE_C2E_EN BIT26 +#define B_EFI_MSR_IA32_MISC_ENABLE_FORCEPR_INPUT_EN BIT21 +#define B_EFI_MSR_IA32_MISC_ENABLE_BI_DIRECTIONAL_PROCHOT_EN BIT17 +#define B_EFI_MSR_IA32_MISC_ENABLE_TM2_EN BIT13 + +#ifndef MSR_PLATFORM_INFO +#define MSR_PLATFORM_INFO 0xCE +#endif + +#ifndef MSR_IACORE_RATIOS +#define MSR_PM_CFG_CTRL 0xE2 + #define C0_SUB_STATES_MASK 0x0000000f + #define C1_SUB_STATES_MASK 0x000000f0 + #define C2_SUB_STATES_MASK 0x00000f00 + #define C3_SUB_STATES_MASK 0x0000f000 + #define C4_SUB_STATES_MASK 0x000f0000 + #define C5_SUB_STATES_MASK 0x00f00000 + #define C6_SUB_STATES_MASK 0x0f000000 + #define C7_SUB_STATES_MASK 0xf0000000 + #define CSTATE_LIMIT_MASK 0x7 + #define CSTATE_LIMIT_NO_LIMIT 0x0 + #define CSTATE_LIMIT_C1 0x1 + #define CSTATE_LIMIT_C2 0x2 + #define CSTATE_LIMIT_C3 0x3 + #define CSTATE_LIMIT_C4 0x4 + #define CSTATE_LIMIT_C6 0x6 + #define CSTATE_LIMIT_C7 0x7 + + #define DYNAMIC_L2_ENABLE (1 << 3) + #define CSM_SMI_TRIG_MASK (7 << 4) + #define CSM_SMI_TRIG_AUTO (7 << 4) + #define MWAIT_IO_REDIR (1 << 10) + #define HW_COORD_DIS (1 << 11) + #define SINGLE_PCTL (1 << 11) + #define LEVEL_5_READ_DISABLE (1 << 13) + #define CFG_LOCK (1 << 15) + #define C3_AUTO_DEMOTE_ENABLE (1 << 25) + #define C1_AUTO_DEMOTE_ENABLE (1 << 26) + #define C3_UNDEMOTION_ENABLE (1 << 27) + #define C1_UNDEMOTION_ENABLE (1 << 28) + #define L2_SHRINK_THRESHOLD_MASK (0x3F << 16) + #define L2_SHRINK_THRESHOLD_DISABLE (1 << 16) + #define L2_SHRINK_THRESHOLD_DEFAULT (6 << 16) + #define L2_SHRINK_THRESHOLD_OFFSET (16) + +// +// Turbo +// + #define MSR_IA32_MISC_ENABLE 0x1a0 + #define MSR_TURBO_RATIO_LIMIT 0x1ad + #define MAX_RATIO_LIMIT_4C_OFFSET 24 + #define MAX_RATIO_LIMIT_3C_OFFSET 16 + #define MAX_RATIO_LIMIT_2C_OFFSET 8 + #define MAX_RATIO_LIMIT_1C_OFFSET 0 + #define MAX_RATIO_LIMIT_MASK1 0x000000ff + #define MAX_RATIO_LIMIT_MASK2 0x0000ff00 + #define MAX_RATIO_LIMIT_MASK3 0x00ff0000 + #define MAX_RATIO_LIMIT_MASK4 0xff000000 + #define TURBO_DISABLE_MASK ((UINT64)1 << 38) + #define TURBO_MODE_DISABLE_BIT 38 +// +// P-State +// + +#define MSR_POWER_CTL 0x1fc +#define RATIO_FLEX_CLEAR_MASK 0xFFFFFFFFFFFF00FF // Clear Bits 16:8 +#define RATIO_FLEX_EN_MASK 0x0000000000010000 // Clear all but bit 16 +#define MAX_NON_TURBO_MASK 0x000000000000FF00 +#define MAX_EFFICIENCY_MASK 0x0000FF0000000000 +#define P_STATE_TARGET_OFFSET 8 +#define P_STATE_TARGET_MASK (0x3F7F) + +#define MSR_IACORE_RATIOS 0x66a +#define MSR_IACORE_VIDS 0x66b + +// +// ACPI P-State Coordination Type +// +#define PSD_SW_ALL 0xfc +#define PSD_SW_ANY 0xfd +#define PSD_HW_ALL 0xfe +#endif + +//----------------------------------------------------------------------------- +// Thermal Management Registers +//----------------------------------------------------------------------------- +#define EFI_MSR_IA32_CR_THERM_INTERRUPT 0x19b +#define EFI_MSR_IA32_CR_THERM_STATUS 0x19c + +#pragma pack(1) + +typedef enum { + EnumCpuUarchUnknown = 0, + EnumNehalemUarch, +} EFI_CPU_UARCH; + +typedef enum { + EnumCpuPlatformUnknown = 0, + EnumDesktop, + EnumMobile, + EnumServer, + EnumNetTop +} EFI_CPU_PLATFORM; + +typedef enum { + EnumCpuTypeUnknown = 0, + EnumAtom, + EnumNehalemEx, + EnumBloomfield, + EnumGainestown, + EnumHavendale, + EnumLynnfield, + EnumAuburndale, + EnumClarksfield, + EnumPineview, + EnumCedarview, + EnumValleyview, + EnumClarkdale // Havendale 32nm +} EFI_CPU_TYPE; + +typedef enum { + EnumCpuFamilyUnknown = 0, + EnumFamilyField, + EnumFamilyDale +} EFI_CPU_FAMILY; + +#pragma pack() + +#endif diff --git a/ChvRefCodePkg/CherryViewSoc/CPU/Include/Guid/HtBistHob.h b/ChvRefCodePkg/CherryViewSoc/CPU/Include/Guid/HtBistHob.h new file mode 100644 index 0000000000..930473b4f1 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/CPU/Include/Guid/HtBistHob.h @@ -0,0 +1,21 @@ +/** @file + GUID used for HT BIST Status HOB entries in the HOB list. + + Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _HT_BIST_HOB_GUID_H_ +#define _HT_BIST_HOB_GUID_H_ + +extern EFI_GUID gEfiHtBistHobGuid; + +#endif diff --git a/ChvRefCodePkg/CherryViewSoc/CPU/Include/Guid/PlatformCpuInfo.h b/ChvRefCodePkg/CherryViewSoc/CPU/Include/Guid/PlatformCpuInfo.h new file mode 100644 index 0000000000..933fa23b91 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/CPU/Include/Guid/PlatformCpuInfo.h @@ -0,0 +1,196 @@ +/** @file + GUID used for Platform CPU Info Data entries in the HOB list. + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PLATFORM_CPU_INFO_GUID_H_ +#define _PLATFORM_CPU_INFO_GUID_H_ + +extern EFI_GUID gEfiPlatformCpuInfoGuid; +extern CHAR16 EfiPlatformCpuInfoVariable[]; + +// +// Tri-state for feature capabilities and enable/disable. +// [0] clear=feature isn't capable +// [0] set =feature is capable +// [1] clear=feature is disabled +// [1] set =feature is enabled +// +#define CPU_FEATURES_CAPABLE BIT0 +#define CPU_FEATURES_ENABLE BIT1 + +#define MAX_CACHE_DESCRIPTORS 64 +#define MAXIMUM_CPU_BRAND_STRING_LENGTH 48 + +#pragma pack(1) +/** +add description + +**/ +typedef struct { + UINT32 FullCpuId; // [31:0] & 0x0FFF0FFF + UINT32 FullFamilyModelId; // [31:0] & 0x0FFF0FF0 + UINT8 ExtendedFamilyId; // [27:20] + UINT8 ExtendedModelId; // [19:16] + UINT8 ProcessorType; // [13:11] + UINT8 FamilyId; // [11:8] + UINT8 Model; // [7:4] + UINT8 SteppingId; // [3:0] +} EFI_CPU_VERSION_INFO; // CPUID.1.EAX +/** +add description + +**/ +typedef struct { + UINT32 L1InstructionCacheSize; + UINT32 L1DataCacheSize; + UINT32 L2CacheSize; + UINT32 L3CacheSize; + UINT32 TraceCacheSize; + UINT8 CacheDescriptor[MAX_CACHE_DESCRIPTORS]; +} EFI_CPU_CACHE_INFO; // CPUID.2.EAX +/** +add description + +**/ +typedef struct { + UINT8 PhysicalPackages; + UINT8 LogicalProcessorsPerPhysicalPackage; + UINT8 CoresPerPhysicalPackage; + UINT8 ThreadsPerCore; +} EFI_CPU_PACKAGE_INFO; // CPUID.4.EAX +/** +add description + +**/ +typedef struct { + UINT32 RegEdx; // CPUID.5.EAX + UINT8 MaxCState; + UINT8 C0SubCStatesMwait; // EDX [3:0] + UINT8 C1SubCStatesMwait; // EDX [7:4] + UINT8 C2SubCStatesMwait; // EDX [11:8] + UINT8 C3SubCStatesMwait; // EDX [15:12] + UINT8 C4SubCStatesMwait; // EDX [19:16] + UINT8 C5SubCStatesMwait; // EDX [23:20] + UINT8 C6SubCStatesMwait; // EDX [27:24] + UINT8 C7SubCStatesMwait; // EDX [31:28] + UINT8 MonitorMwaitSupport; // ECX [0] + UINT8 InterruptsBreakMwait; // ECX [1] +} EFI_CPU_CSTATE_INFO; // CPUID.5.EAX +/** +add description + +**/ +typedef struct { + UINT8 Turbo; // EAX [1] + UINT8 PECI; // EAX [0] + UINT8 NumIntThresholds; // EBX [3:0] + UINT8 HwCoordinationFeedback; // ECX [0] +} EFI_CPU_POWER_MANAGEMENT; // CPUID.6.EAX + +// +// IMPORTANT: Each CPU feature enabling entry is assumed a tri-state variable. +// - Keep the respective feature entry variable as default value (0x00) +// if the CPU is not capable for the feature. +// - Use the specially defined programming convention to update the variable +// to indicate capable, enable or disable. +// ie. F_CAPABLE for feature available +// F_ENABLE for feature enable +// F_DISABLE for feature disable +// +/** +add description + +**/ +typedef struct { + EFI_CPUID_REGISTER Regs; // CPUID.1.EAX + UINT8 Xapic; // ECX [21] + UINT8 SSE4_2; // ECX [20] + UINT8 SSE4_1; // ECX [19] + UINT8 Dca; // ECX [18] + UINT8 SupSSE3; // ECX [9] + UINT8 Tm2; // ECX [8] + UINT8 Eist; // ECX [7] + UINT8 Lt; // ECX [6] + UINT8 Vt; // ECX [5] + UINT8 Mwait; // ECX [3] + UINT8 SSE3; // ECX [0] + UINT8 Tcc; // EDX [29] + UINT8 Mt; // EDX [28] + UINT8 SSE2; // EDX [26] + UINT8 SSE; // EDX [25] + UINT8 MMX; // EDX [23] + EFI_CPUID_REGISTER ExtRegs; // CPUID.80000001.EAX + UINT8 ExtLahfSahf64; // ECX [0] + UINT8 ExtIntel64; // EDX [29] + UINT8 ExtXd; // EDX [20] + UINT8 ExtSysCallRet64; // EDX [11] + UINT16 Ht; // CPUID.0B.EAX EBX [15:0] +} EFI_CPU_FEATURES; // CPUID.1.EAX, CPUID.0B.EAX, CPUID.80000001.EAX +/** +add description + +**/ +typedef struct { + UINT8 PhysicalBits; + UINT8 VirtualBits; +} EFI_CPU_ADDRESS_BITS; // CPUID.80000008.EAX +/** +add description + +**/ +typedef struct { + UINT8 PlatformID; // MSR 0x17 [52:50] + UINT32 MicrocodeRevision; // MSR 0x8B [63:32] + UINT8 MaxEfficiencyRatio; // MSR 0xCE [47:40] + UINT8 DdrRatioUnlockCap; // MSR 0xCE [30] + UINT8 TdcTdpLimitsTurbo; // MSR 0xCE [29] + UINT8 RatioLimitsTurbo; // MSR 0xCE [28] + UINT8 PreProduction; // MSR 0xCE [27] + UINT8 DcuModeSelect; // MSR 0xCE [26] + UINT8 MaxNonTurboRatio; // MSR 0xCE [15:8] + UINT8 Emrr; // MSR 0xFE [12] + UINT8 Smrr; // MSR 0xFE [11] + UINT8 VariableMtrrCount; // MSR 0xFE [7:0] + UINT16 PState; // MSR 0x198 [15:0] + UINT8 TccActivationTemperature; // MSR 0x1A2 [23:16] + UINT8 TemperatureControlOffset; // MSR 0x1A2 [15:8] + UINT32 PCIeBar; // MSR 0x300 [39:20] + UINT8 PCIeBarSizeMB; // MSR 0x300 [3:1] +} EFI_MSR_FEATURES; +/** +add description + +**/ +typedef struct { + BOOLEAN IsIntelProcessor; + UINT8 BrandString[MAXIMUM_CPU_BRAND_STRING_LENGTH + 1]; + UINT32 CpuidMaxInputValue; + UINT32 CpuidMaxExtInputValue; + EFI_CPU_UARCH CpuUarch; + EFI_CPU_FAMILY CpuFamily; + EFI_CPU_PLATFORM CpuPlatform; + EFI_CPU_TYPE CpuType; + EFI_CPU_VERSION_INFO CpuVersion; + EFI_CPU_CACHE_INFO CpuCache; + EFI_CPU_FEATURES CpuFeatures; + EFI_CPU_CSTATE_INFO CpuCState; + EFI_CPU_PACKAGE_INFO CpuPackage; + EFI_CPU_POWER_MANAGEMENT CpuPowerManagement; + EFI_CPU_ADDRESS_BITS CpuAddress; + EFI_MSR_FEATURES Msr; +} EFI_PLATFORM_CPU_INFO; + +#pragma pack() + +#endif diff --git a/ChvRefCodePkg/CherryViewSoc/CPU/Include/Guid/PowerManagementAcpiTableStorage.h b/ChvRefCodePkg/CherryViewSoc/CPU/Include/Guid/PowerManagementAcpiTableStorage.h new file mode 100644 index 0000000000..10b0824bfa --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/CPU/Include/Guid/PowerManagementAcpiTableStorage.h @@ -0,0 +1,24 @@ +/** @file + GUID definition for the Power Management ACPI table storage file name + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _POWER_MANAGEMENT_ACPI_TABLE_STORAGE_H_ +#define _POWER_MANAGEMENT_ACPI_TABLE_STORAGE_H_ + +#define POWER_MANAGEMENT_ACPI_TABLE_STORAGE_GUID \ + { 0x161be597, 0xe9c5, 0x49db, 0xae, 0x50, 0xc4, 0x62, 0xab, 0x54, 0xee, 0xda } + +extern EFI_GUID gPowerManagementAcpiTableStorageGuid; + +#endif diff --git a/ChvRefCodePkg/CherryViewSoc/CPU/Include/Library/StallSmmLib.h b/ChvRefCodePkg/CherryViewSoc/CPU/Include/Library/StallSmmLib.h new file mode 100644 index 0000000000..17c97a7f66 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/CPU/Include/Library/StallSmmLib.h @@ -0,0 +1,38 @@ +/** @file + This library provides SMM functions for Stall. + These can be used to save size and simplify code. + All contents must be runtime and SMM safe. + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SMM_STALL_LIB_H_ +#define _SMM_STALL_LIB_H_ +#include "PiDxe.h" +#include "Pi/PiSmmCis.h" + +extern EFI_SMM_SYSTEM_TABLE2 *mSmst; + +/** + Delay for at least the request number of microseconds + + @param[in] Microseconds Number of microseconds to delay. + + @retval None + +**/ +VOID +SmmStall ( + IN UINTN Microseconds + ); + +#endif diff --git a/ChvRefCodePkg/CherryViewSoc/CPU/Include/MchPpmLib.h b/ChvRefCodePkg/CherryViewSoc/CPU/Include/MchPpmLib.h new file mode 100644 index 0000000000..ea44e35465 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/CPU/Include/MchPpmLib.h @@ -0,0 +1,80 @@ +/** @file + Header file for MCH power management functionality + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _MCH_PPM_LIB_H_ +#define _MCH_PPM_LIB_H_ + +// +// Statements that include other files +// +#include +#include + +/** + Initialize the MCH support library. + This must be called once during driver initialization before using + any of the other library services provided. + + @param[in] None + + @retval EFI_SUCCESS The library has been initialized correctly. + +**/ +EFI_STATUS +InitializeMchLib ( + VOID + ); + +/** + Determine the processor core frequency + + @param[in] None + + @retval Processor core frequency multiplied by 3 + +**/ +UINT16 +DetermineiFsbFromMsr ( + VOID + ); + +/** + Determines if MCH is capable of dynamic FSB frequency switching(Bus Geyserville) + + @param[in] None + + @retval FALSE Dynamic FSB frequency switching(Bus Geyserville) is NOT supported. + @retval TRUE Dynamic FSB frequency switching(Bus Geyserville) is supported. + +**/ +BOOLEAN +MchSupportDynamicFsbFrequencySwitching ( + VOID + ); + +/** + Enables dynamic FSB frequency switching(Bus Geyserville) on MCH + + @param[in] None + + @retval EFI_SUCCESS Dynamic FSB frequency switching(Bus Geyserville) enabled + +**/ +EFI_STATUS +EnableMchDynamicFsbFrequencySwitching ( + VOID + ); + +#endif diff --git a/ChvRefCodePkg/CherryViewSoc/CPU/Include/MmioAccess.h b/ChvRefCodePkg/CherryViewSoc/CPU/Include/MmioAccess.h new file mode 100644 index 0000000000..c6aa627737 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/CPU/Include/MmioAccess.h @@ -0,0 +1,84 @@ +/** @file + Macros to simplify and abstract the interface to PCI configuration. + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _MMIOACCESS_H_INCLUDED_ +#define _MMIOACCESS_H_INCLUDED_ + +#define MmioAddress( BaseAddr, Register ) \ + ( (UINTN)BaseAddr + \ + (UINTN)(Register) \ + ) + +// +// UINT32 +// + +#define Mmio32Ptr( BaseAddr, Register ) \ + ( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) ) + +#define Mmio32( BaseAddr, Register ) \ + *Mmio32Ptr( BaseAddr, Register ) + +#define Mmio32Or( BaseAddr, Register, OrData ) \ + Mmio32( BaseAddr, Register ) = \ + (UINT32) ( \ + Mmio32( BaseAddr, Register ) | \ + (UINT32)(OrData) \ + ) + +#define Mmio32And( BaseAddr, Register, AndData ) \ + Mmio32( BaseAddr, Register ) = \ + (UINT32) ( \ + Mmio32( BaseAddr, Register ) & \ + (UINT32)(AndData) \ + ) + +#define Mmio32AndThenOr( BaseAddr, Register, AndData, OrData ) \ + Mmio32( BaseAddr, Register ) = \ + (UINT32) ( \ + ( Mmio32( BaseAddr, Register ) & \ + (UINT32)(AndData) \ + ) | \ + (UINT32)(OrData) \ + ) + +// +// UINT16 +// + +#define Mmio16Ptr( BaseAddr, Register ) \ + ( (volatile UINT16 *)MmioAddress( BaseAddr, Register ) ) + +#define Mmio16( BaseAddr, Register ) \ + *Mmio16Ptr( BaseAddr, Register ) + +#define Mmio16Or( BaseAddr, Register, OrData ) \ + Mmio16( BaseAddr, Register ) = \ + (UINT16) ( \ + Mmio16( BaseAddr, Register ) | \ + (UINT16)(OrData) \ + ) + +// +// UINT8 +// + +#define Mmio8Ptr( BaseAddr, Register ) \ + ( (volatile UINT8 *)MmioAddress( BaseAddr, Register ) ) + +#define Mmio8( BaseAddr, Register ) \ + *Mmio8Ptr( BaseAddr, Register ) + +#endif diff --git a/ChvRefCodePkg/CherryViewSoc/CPU/Include/Ppi/Cache.h b/ChvRefCodePkg/CherryViewSoc/CPU/Include/Ppi/Cache.h new file mode 100644 index 0000000000..3b4de959a2 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/CPU/Include/Ppi/Cache.h @@ -0,0 +1,59 @@ +/** @file + Cache PPI definition. + + Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PEI_CACHE_PPI_H_ +#define _PEI_CACHE_PPI_H_ + +typedef struct _PEI_CACHE_PPI PEI_CACHE_PPI; + +// +// EFI_MEMORY_CACHE_TYPE +// +typedef INT32 EFI_MEMORY_CACHE_TYPE; + +// +// PEI_SET_CACHE_PPI +// +typedef +EFI_STATUS +(EFIAPI *PEI_SET_CACHE_PPI) ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_CACHE_PPI *This, + IN EFI_PHYSICAL_ADDRESS MemoryAddress, + IN UINT64 MemoryLength, + IN EFI_MEMORY_CACHE_TYPE MemoryCacheType + ); + +// +// PEI_RESET_CACHE_PPI +// +typedef +EFI_STATUS +(EFIAPI *PEI_RESET_CACHE_PPI) ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_CACHE_PPI *This + ); + +// +// PEI_CACHE_PPI +// +struct _PEI_CACHE_PPI { + PEI_SET_CACHE_PPI SetCache; + PEI_RESET_CACHE_PPI ResetCache; +}; + +extern EFI_GUID gPeiCachePpiGuid; + +#endif diff --git a/ChvRefCodePkg/CherryViewSoc/CPU/Include/Ppi/CpuPlatformPolicyPpi.h b/ChvRefCodePkg/CherryViewSoc/CPU/Include/Ppi/CpuPlatformPolicyPpi.h new file mode 100644 index 0000000000..5fe04d4aab --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/CPU/Include/Ppi/CpuPlatformPolicyPpi.h @@ -0,0 +1,73 @@ +/** @file + CPU policy PPI produced by a platform driver specifying various + expected CPU settings. This PPI is consumed by CPU PEI modules. + + Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef CPU_PLATFORM_POLICY_PPI_H_ +#define CPU_PLATFORM_POLICY_PPI_H_ + +extern EFI_GUID gPeiCpuPlatformPolicyPpiGuid; + +typedef struct _PEI_CPU_PLATFORM_POLICY_PPI PEI_CPU_PLATFORM_POLICY_PPI; + +#define CPU_FEATURE_ENABLE 1 +#define CPU_FEATURE_DISABLE 0 + +// +// PEI_CPU_PLATFORM_POLICY_PPI revisions +// +#define PEI_CPU_PLATFORM_POLICY_PPI_REVISION_1 1 +#define PEI_CPU_PLATFORM_POLICY_PPI_REVISION_2 2 + +/// +/// Platform Policies for CPU features configration Platform code can enable/disable/configure features through this structure. +/// +typedef struct { + // + // Byte 0, bit definition Generic CPU feature configuration + // + UINT8 ActiveCoreCount : 1; ///< Enable or Disable BIST on Reset; 0: Disable; 1 Enable. + UINT8 Rsvdbyte : 7; ///< Place holder for additonal functionalites expected in future platforms. +} CPU_CONFIG_PPI; + +typedef struct { + /** + Boot performance mode. + - 0: Maximum non-turbo performance + - 1:Maximum battery performance. + **/ + UINT8 BootInLfm; +} POWER_MGMT_CONFIG_PPI; + +/** + The PPI allows the platform code to publish a set of configuration information that the + CPU drivers will use to configure the processor in the PEI phase. + This Platform Policy PPI needs to be initialized for CPU configuration. + @note The PPI has to be published before processor PEIMs are dispatched. +**/ +struct _PEI_CPU_PLATFORM_POLICY_PPI { + /** + This member specifies the revision of the CPU Policy PPI. This field is used to indicate backward + compatible changes to the PPI. Any such changes to this PPI will result in an update in the revision number. + + Revision 1: + - Initial version. +yy + **/ + UINT8 Revision; + CPU_CONFIG_PPI *CpuConfig; ///< Processor Features Configuration. + POWER_MGMT_CONFIG_PPI *PowerMgmtConfig; ///< Processor Power ManagementFeatures Configuration. +}; + +#endif diff --git a/ChvRefCodePkg/CherryViewSoc/CPU/Include/PpmCommon.h b/ChvRefCodePkg/CherryViewSoc/CPU/Include/PpmCommon.h new file mode 100644 index 0000000000..0830eaff40 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/CPU/Include/PpmCommon.h @@ -0,0 +1,114 @@ +/** @file + IST/PPM reference code definitions. + + Acronyms: + PPM Platform Power Management + GV Geyserville + TM Thermal Monitor + IST Intel(R) Speedstep technology + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PPM_COMMON_H_ +#define _PPM_COMMON_H_ + +#include + +// +// Forward Declarations +// +typedef union _FVID_TABLE FVID_TABLE; + +// +// Limit the number of P-states to 16. Up to Windows 7, the OS allocates 1KB buffer for the PSS package. +// So the maximum number of P-state OS can handle is 19. This is not an OS issue. Having too many P-states +// is not good for the system performance. +// +#define FVID_MAX_STATES 32 // ACPI Max P-States = 16 + +#define FVID_MIN_STEP_SIZE 1 + +// +// Structure declarations +// + +typedef struct _FVID_HEADER { + UINT32 Stepping; // Matches value returned by CPUID function 1 + UINT16 MaxVid; // Matches VID_MAX field in PERF_STS_MSR + UINT16 MaxBusRatio; // Matches BUS_RATIO_MAX field in PERF_STS_MSR + UINT16 Gv3States; // Number of states of FVID (N) +} FVID_HEADER; + +typedef struct _FVID_STATE { + UINT32 State; // State Number (0 - N-1) + UINT16 Vid; // VID_SEL value to be written to PERF_CTL + UINT16 BusRatio; // BUS_RATIO_SEL value to be written to PERF_CTL + UINT16 Power; // Typical power consumed by CPU in this state +} FVID_STATE; + +typedef union _FVID_TABLE { + FVID_HEADER FvidHeader; + FVID_STATE FvidState; + UINT64 FvidData; +} FVID_TABLE; + +// +// Processor Power Management Flags Bit Definitions: +// +#define PPM_GV3 (1 << 0) // (EIST) - Enhanced Intel SpeedStep Technology.a.k.a Geyserville 3. +#define PPM_C1 (1 << 1) // C1 enabled, supported. +#define PPM_C1E (1 << 2) // C1E enabled. +#define PPM_C2 (1 << 3) // C2 enabled, supported. +#define PPM_C2E (1 << 4) // C2E enabled. +#define PPM_C3 (1 << 5) // C3 enabled, supported. +#define PPM_C3E (1 << 6) // C3E enabled. +#define PPM_C4 (1 << 7) // C4 enabled, supported. +#define PPM_C4E (1 << 8) // C4E enabled, supported. +#define PPM_DEEP_C4 (1 << 9) // Deep C4 enabled, supported. +#define PPM_HARD_C4E (1 << 10) // Hard C4E enabled. +#define PPM_C6 (1 << 11) // C6 enabled, supported. +#define PPM_C6S (1 << 12) // C6S enabled, supported. +#define PPM_C7 (1 << 13) // C6S enabled, supported. + +#define PPM_TM (1 << 16) // Thermal Monitor 1 & Thermal Monitor 2. +#define PPM_TM1 (1 << 16) // Thermal Monitor 1. +#define PPM_TM2 (1 << 17) // Thermal Monitor 2. + +#define PPM_PROC_HOT (1 << 19) // Bi-directional ProcHot. +#define PPM_TSC (1 << 20) // TSC 64-bit writeable. +#define PPM_MWAIT_EXT (1 << 21) // MONITIOR/MWAIT Extensions supported. +#define PPM_QUAD (1 << 23) // Quad-core processor. + +#define PPM_CMP (1 << 24) // CMP. +#define PPM_TURBO (1 << 25) // Turbo Mode +#define PPM_EMTTM (1 << 26) // Enhanced Multi Threaded Thermal Monitoring +#define PPM_DYNAMIC_FSB (1 << 27) // Dynamic FSB Switching + +#define PPM_TSTATES (1 << 28) // CPU throttling states +#define PPM_BOOT_P_ST_HFM (1 << 29) // Set boot P-state to HFM when EIST is enabled +#define PPM_S0ix (1 << 30) // S0ix is enabled + +// @NOTE: Not available in VLV +#define PPM_FAST_BRK_SNOOP 0x200000 // BTI 21: Fast break Snoop Enable +#define PPM_FAST_BRK_INTERRUPT 0x400000 // BIT 22: Fast break Interrupt Enable + +#define PPM_C_STATES (PPM_C1 + PPM_C4 + PPM_C6 + PPM_C6S + PPM_C7) +#define PPM_ENHANCED_C_STATES (PPM_C1E) + +#define CST_UPDT_TSC (1 << 1) +#define CST_DATA_TBASE 3579545 + +#define PPM_ENABLE 1 +#define PPM_DISABLE 0 + +#endif diff --git a/ChvRefCodePkg/CherryViewSoc/CPU/Include/Pram.h b/ChvRefCodePkg/CherryViewSoc/CPU/Include/Pram.h new file mode 100644 index 0000000000..ddde718d34 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/CPU/Include/Pram.h @@ -0,0 +1,41 @@ +/** @file + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PRAM_H_ +#define _PRAM_H_ + +// +// Statements that include other files +// +#include +#include "Platform.h" +#include + +#define EFI_ACPI_PRAM_BASE_ADDRESS_TABLE_SIGNATURE 0x4D415250 + +#define EFI_ACPI_OEM_PRAM_REVISION 0x00000001 + +#define EFI_ACPI_PRAM_BASE_ADDRESS_TABLE_REVISION 0x01 + +#pragma pack(1) + +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + EFI_PHYSICAL_ADDRESS PramBaseAddress; + UINT32 PramSize; +} EFI_ACPI_PRAM_BASE_ADDRESS_TABLE; + +#pragma pack() + +#endif // diff --git a/ChvRefCodePkg/CherryViewSoc/CPU/Include/Protocol/CpuPlatformPolicyProtocol.h b/ChvRefCodePkg/CherryViewSoc/CPU/Include/Protocol/CpuPlatformPolicyProtocol.h new file mode 100644 index 0000000000..c56dab1179 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/CPU/Include/Protocol/CpuPlatformPolicyProtocol.h @@ -0,0 +1,241 @@ +/** @file + Protocol used for specifying platform related CPU information and policy setting. + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _CPU_PLATFORM_POLICY_PROTOCOL_H_ +#define _CPU_PLATFORM_POLICY_PROTOCOL_H_ + +typedef UINT16 STRING_REF; +#include + +typedef struct _EFI_PLATFORM_CPU_PROTOCOL EFI_PLATFORM_CPU_PROTOCOL; + +// +// Prototypes for the Platform CPU Protocol +// +typedef +EFI_STATUS +(EFIAPI *EFI_PLATFORM_CPU_RETRIEVE_MICROCODE) ( + IN EFI_PLATFORM_CPU_PROTOCOL * This, + OUT UINT8 **MicrocodeData + ); + +typedef +EFI_STATUS +(EFIAPI *EFI_PLATFORM_CPU_GET_TM2_CONTROL_INFO) ( + IN EFI_PLATFORM_CPU_PROTOCOL * This, + OUT UINT8 *Tm2Core2BusRatio, + OUT UINT8 *Tm2Vid + ); +// +// The platform capabilities for enabling must be same as +// disabling. +// +typedef UINT32 EFI_CPU_STATE_CHANGE_CAPABILITIES; + +// +// The platform supports a hardware mechanism to +// enable and disable the processor. +// A CPU that is disabled in HW becomes 'invisible' to +// the software and does not consume any system resources, such as +// RAM or ROM. This CPU does not respond to any bus +// cycles including Inter processor Interrupts +// The processor state is persistent. If the +// hardware underneath does not support persistency, the +// platform CPU driver will simulate that behavior. +// +#define EFI_CPU_HW_EN_DIS_SUPPORTED 0x0001 + +// +// Meaningful if EFI_CPU_HW_ EN_DIS_SUPPORTED is set. +// Set if the platform supports a harware mechanism to +// enable and disable the processor in this boot (without a reset) +// If this flag is clear, all state changes take effect on the +// next boot and the call to EnableDisableCpu ( )results in +// a system reset +// +#define EFI_CPU_HW_EN_DIS_THIS_BOOT 0x0002 + +// +// TBD, capabilities with regards to hot remove/addition of CPUs +// +// +// The minimum granularity of enable/disable operations +// EfiCpuControlThreadGranularity -Can enable/disable one thread at a // time. E.g. if a CPU core has two threads, one can be enabled +// while the other is disabled. +// EfiCpuControlCoreGranularity -Can enable/disable one core at a +// time. E.g. if a CPU package has two cores, one core can be +// enabled while the other is disabled. +// enabling or disabling CPUs. +// EfiCpuControlPackageGranularity -Can enable/disable one package at // a time +// +typedef enum { + EfiCpuControlThreadGranularity, + EfiCpuControlCoreGranularity, + EfiCpuControlDieGranularity, + EfiCpuControlPackageGranularity +} EFI_CPU_STATE_CHANGE_GRANULARITY; + +// +// The state of the CPU +// EfiCpuNotKnown - Only used if the platform plays no role in +// enabling or disabling CPUs. +// EfiCpuAbsent - CPU is physically absent +// EfiCpuPresentDisabled - CPU is physically present, but has been +// disabled by the platform +// +typedef enum { + EfiCpuStateNotKnown, + EfiCpuAbsent, + EfiCpuPresentDisabled, + EfiCpuPresentEnabled +} EFI_CPU_STATE; + +// +// The platform category, Server, Desktop and Mobile +// are defined. +// +typedef enum { + EfiPlatformUnknown = 0, + EfiPlatformDesktop, + EfiPlatformMobile, + EfiPlatformServer, + EfiPlatformMax +} EFI_PLATFORM_CATEGORY; +// +// The reason for changing the state of the processor +// Only applies to Disabling processors. +// In future, we can add add/remove support +// +#define EFI_CPU_CAUSE_NOT_DISABLED 0x0000 +#define EFI_CPU_CAUSE_INTERNAL_ERROR 0x0001 +#define EFI_CPU_CAUSE_THERMAL_ERROR 0x0002 +#define EFI_CPU_CAUSE_SELFTEST_FAILURE 0x0004 +#define EFI_CPU_CAUSE_PREBOOT_TIMEOUT 0x0008 +#define EFI_CPU_CAUSE_FAILED_TO_START 0x0010 +#define EFI_CPU_CAUSE_CONFIG_ERROR 0x0020 +#define EFI_CPU_CAUSE_USER_SELECTION 0x0080 +#define EFI_CPU_CAUSE_BY_ASSOCIATION 0x0100 +#define EFI_CPU_CAUSE_UNSPECIFIED 0x8000 + +typedef UINT32 EFI_CPU_STATE_CHANGE_CAUSE; + +typedef struct { + EFI_CPU_PHYSICAL_LOCATION Location; + EFI_CPU_STATE State; + EFI_CPU_STATE_CHANGE_CAUSE Cause; +} EFI_CPU_STATE_CHANGE_OP_LIST; + +typedef struct { + CHAR8 *SocketDesignation; + UINT16 MaxSpeed; + UINT8 ProcessorUpgrade; + CHAR8 *SerialNumber; + CHAR8 *AssetTag; + CHAR8 *PartNumber; +} PLATFORM_CPU_INFORMATION_FOR_SMBIOS; + +typedef +EFI_STATUS +(EFIAPI *EFI_PLATFORM_CPU_GET_MAX_COUNT) ( + IN EFI_PLATFORM_CPU_PROTOCOL * This, + OUT UINT32 *MaxThreadsPerCore, + OUT UINT32 *MaxCoresPerDie, + OUT UINT32 *MaxDiesPerPackage, + OUT UINT32 *MaxPackages + ); + +typedef +EFI_STATUS +(EFIAPI *EFI_PLATFORM_CPU_GET_CPU_INFO) ( + IN EFI_PLATFORM_CPU_PROTOCOL * This, + IN UINT16 iFsbFrequency, + IN OUT PLATFORM_CPU_INFORMATION_FOR_SMBIOS *PlatformCpuInfoForSmbios + ); + +typedef +EFI_STATUS +(EFIAPI *EFI_PLATFORM_CPU_STALL) ( + IN EFI_PLATFORM_CPU_PROTOCOL *This, + IN UINTN Microseconds + ); + +// +// Interface structure for the Platform CPU Protocol +// +typedef struct _EFI_PLATFORM_CPU_PROTOCOL { + BOOLEAN HtState; + EFI_PLATFORM_CPU_STALL Stall; + EFI_PLATFORM_CPU_RETRIEVE_MICROCODE RetrieveMicrocode; + EFI_PLATFORM_CPU_GET_TM2_CONTROL_INFO GetTm2ControlInfo; + BOOLEAN EnableL3Cache; + BOOLEAN LimitCpuidMaximumValue; + EFI_PLATFORM_CPU_GET_MAX_COUNT GetMaxCount; + EFI_PLATFORM_CPU_GET_CPU_INFO GetCpuInfo; + UINT8 BspSelection; + UINT8 UpBootSelection; + UINT8 ProcessorBistEnable; + UINT8 ProcessorHyperThreadingDisable; + UINT8 ProcessorVmxEnable; + UINT8 EnableCoresInSbsp; + UINT8 EnableCoresInNbsp; + UINT32 DcaPrefetchDelayValue; + UINT32 VirtualWireMode; + BOOLEAN ProcessorMsrLockControl; + BOOLEAN Processor3StrikeControl; + BOOLEAN DcaState; + BOOLEAN CcxEnable; + BOOLEAN C1AutoDemotion; + BOOLEAN C3AutoDemotion; + UINT8 PackageCState; + BOOLEAN C1eEnable; + UINT8 AesEnable; + BOOLEAN Gv3State; + BOOLEAN PsdState; + BOOLEAN CmpState; + BOOLEAN PECIEnable; + BOOLEAN LtEnable; + BOOLEAN L2Enable; + BOOLEAN L2EccEnable; + BOOLEAN FastString; + BOOLEAN MachineCheckEnable; + BOOLEAN MLCSpatialPrefetcherEnable; + BOOLEAN MLCStreamerPrefetcherEnable; + BOOLEAN DCUStreamerPrefetcherEnable; + BOOLEAN DCUIPPrefetcherEnable; + BOOLEAN EchoTprDisable; + BOOLEAN MonitorMwaitEnable; + BOOLEAN TurboModeEnable; + BOOLEAN ExtremeEnable; + BOOLEAN XapicEnable; + BOOLEAN Vr11Enable; + BOOLEAN TdcLimitOverride; + UINT16 TdcLimit; + BOOLEAN TdpLimitOverride; + UINT16 TdpLimit; + UINT8 RatioLimit1C; + UINT8 RatioLimit2C; + UINT8 RatioLimit3C; + UINT8 RatioLimit4C; + UINT64 CpuCommonFeature; + BOOLEAN DCUModeSelection; + BOOLEAN BiDirectionalProchot; + EFI_PLATFORM_CATEGORY PlatformCategory; + UINT8 ActiveProcessorCores; + UINT8 EnableDts; +} EFI_PLATFORM_CPU_PROTOCOL; + +extern EFI_GUID gEfiPlatformCpuProtocolGuid; + +#endif diff --git a/ChvRefCodePkg/CherryViewSoc/CPU/Include/Protocol/PpmPlatformPolicy.h b/ChvRefCodePkg/CherryViewSoc/CPU/Include/Protocol/PpmPlatformPolicy.h new file mode 100644 index 0000000000..4a814ce257 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/CPU/Include/Protocol/PpmPlatformPolicy.h @@ -0,0 +1,125 @@ +/** @file + Interface definition details between PPM and platform drivers during DXE phase. + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PPM_PLATFORM_POLICY_H_ +#define _PPM_PLATFORM_POLICY_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPpmPlatformPolicyProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PPM_PLATFORM_POLICY_PROTOCOL PPM_PLATFORM_POLICY_PROTOCOL; + +// +// Protocol revision number +// Any backwards compatible changes to this protocol will result in an update in the revision number +// Major changes will require publication of a new protocol +// +// Revision 1: Original version +// Revision 2: Added T-states field to the PPM_FUNCTION_ENABLES structure, Renamed unused fields - CxPopUpEnable, CxPopDownEnable, FastC4ExitEnable +// Revision 3: Extended VidCpuid to 32 bits for extended CPUID support (Penryn) +// Revision 4: Added support for extended C6 residency enabling +// +#define PPM_PLATFORM_POLICY_PROTOCOL_REVISION 1 +#define PPM_PLATFORM_POLICY_PROTOCOL_REVISION_2 2 +#define PPM_PLATFORM_POLICY_PROTOCOL_REVISION_3 3 +#define PPM_PLATFORM_POLICY_PROTOCOL_REVISION_4 4 + +// +// Define maximum number of custom VID states supported +// +#ifndef MAX_CUSTOM_VID_TABLE_STATES + #define MAX_CUSTOM_VID_TABLE_STATES 6 +#endif +// +// Custom VID table +// +typedef struct { + UINT8 VidNumber; + UINT32 VidCpuid; + UINT16 VidMaxRatio; + UINT16 VidMaxVid; + UINT16 StateRatio[MAX_CUSTOM_VID_TABLE_STATES]; + UINT16 StateVid[MAX_CUSTOM_VID_TABLE_STATES]; +} PPM_CUSTOM_VID_TABLE; + +// +// PPM functional enables +// +typedef struct { + UINT8 EnableGv :1; // 0: Disabled; 1: Enabled + UINT8 EnableCx :1; + UINT8 EnableCxe :1; + UINT8 EnableC4 :1; + UINT8 EnableC6 :1; + UINT8 EnableC7 :1; + UINT8 EnableTm :1; + UINT8 EnableEmttm :1; + UINT8 EnableDynamicFsb :1; + UINT8 EnableTurboMode :1; + UINT8 PowerLimit2 :1; + UINT8 EnableProcHot :1; + UINT8 HTD :1; + UINT8 EnableCMP :1; + UINT8 TStatesEnable :1; + UINT8 S0ixSupport :1; + UINT8 Reserved2 ; + +} PPM_FUNCTION_ENABLES; + +// +// PPM Turbo settings +// +typedef struct _PPM_TURBO_SETTINGS { + UINT16 PowerLimit1; + UINT32 PowerLimit1Time; + UINT16 PowerLimit2; + UINT8 TurboPowerLimitLock; +} PPM_TURBO_SETTINGS; +// +// SMI functions +// + +// +// Platform Policy +// +typedef struct _PPM_PLATFORM_POLICY_PROTOCOL { + UINT8 Revision; + PPM_FUNCTION_ENABLES FunctionEnables; + PPM_CUSTOM_VID_TABLE CustomVidTable; + PPM_TURBO_SETTINGS TurboSettings; + UINT8 PowerStateSwitchSmiNumber; + UINT8 EnableCStateIoRedirectionSmiNumber; + UINT8 DisableCStateIoRedirectionSmiNumber; + UINT8 EnableSmiCStateCoordinationSmiNumber; + UINT8 DisableSmiCStateCoordinationSmiNumber; + UINT8 EnablePStateHardwareCoordinationSmiNumber; + UINT8 DisablePStateHardwareCoordinationSmiNumber; + UINT8 S3RestoreMsrSwSmiNumber; + UINT8 BootInLfm; + UINT32 FlexRatioVid; + UINT8 EnableEnableC6ResidencySmiNumber; + // + // Primary and Secondary Plane Current Limits + // + UINT16 PrimaryPlaneCurrentLimit; + UINT8 OsPolicy; +} PPM_PLATFORM_POLICY_PROTOCOL; + +#endif diff --git a/ChvRefCodePkg/CherryViewSoc/CPU/Include/Protocol/PpmProcessorSupport2.h b/ChvRefCodePkg/CherryViewSoc/CPU/Include/Protocol/PpmProcessorSupport2.h new file mode 100644 index 0000000000..a74e2e566f --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/CPU/Include/Protocol/PpmProcessorSupport2.h @@ -0,0 +1,561 @@ +/** @file + This protocol provides Platform Power Management support functionality and definitions. + + Acronyms: + PPM Platform Power Management + GV Geyserville + TM Thermal Monitor + IST Intel(R) Speedstep technology + HT Hyper-Threading Technology + CMP Core Multi-Processing + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PPM_PROCESSOR_SUPPORT_PROTOCOL_2_H_ +#define _PPM_PROCESSOR_SUPPORT_PROTOCOL_2_H_ + +#include + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPpmProcessorSupportProtocol2Guid; + +// +// Forward reference for pure ANSI compatability +// +typedef struct _PPM_PROCESSOR_SUPPORT_PROTOCOL_2 PPM_PROCESSOR_SUPPORT_PROTOCOL_2; + +// +// Protocol data definitions +// + +// +// Protocol member function prototypes +// + +/** + Set the PPM flags supported by this processor. + PpmFlags format is defined in the GlobalNvsArea protocol. + + @param[in] + + This Pointer to the protocol instance + + @retval + + EFI_SUCCESS PpmFlags updated with the features supported by the processor + +**/ +typedef +EFI_STATUS +(EFIAPI *SET_PPM_FLAGS) ( + IN OUT PPM_PROCESSOR_SUPPORT_PROTOCOL_2 *This + ); + +/** + Enable C state support as specified by the input flags + + @param[in] + + This Pointer to the protocol instance + C2IoAddress IO address to generate C2 states (PM base + 014 usually) + CsmIoAddress IO trap address for CSM generated Cx requests (see PMG_IO_BASE_ADDR and PMG_CST_CONFIG_CONTROL MSR) + + @retval + + EFI_SUCCESS Processor C state support configured successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *ENABLE_C_STATES) ( + IN OUT PPM_PROCESSOR_SUPPORT_PROTOCOL_2 *This, + IN UINT16 C2IoAddress, + IN UINT16 CsmIoAddress + + ); + +/** + Initialize general thermal management for the processor + + @param[in] + + This Pointer to the protocol instance + + @retval + + EFI_SUCCESS Processor thermal support configured successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *INIT_THERMAL) ( + IN OUT PPM_PROCESSOR_SUPPORT_PROTOCOL_2 *This, + IN OUT PPM_PLATFORM_POLICY_PROTOCOL *PPMPolicy + ); + +/** + Enable TM1 for the processor + + @param[in] + + This Pointer to the protocol instance + + @retval + + EFI_SUCCESS Processor TM1 support configured successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *ENABLE_TM) ( + IN OUT PPM_PROCESSOR_SUPPORT_PROTOCOL_2 *This + ); + +/** + Enable TM2 for the processor + + @param[in] + + This Pointer to the protocol instance + FvidPointer Pointer to a table to be updated + + @retval + + EFI_SUCCESS Processor TM2 support configured successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *ENABLE_TM2) ( + IN OUT PPM_PROCESSOR_SUPPORT_PROTOCOL_2 *This, + IN OUT FVID_TABLE *FvidPointer + ); + +/** + Enable the bi-directional PROCHOT# signal + + @param[in] + + This Pointer to the protocol instance + + @retval + + EFI_SUCCESS Processor PROCHOT# support configured successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *ENABLE_PROC_HOT) ( + IN OUT PPM_PROCESSOR_SUPPORT_PROTOCOL_2 *This + ); + +/** + Initialize the TSC support. + + @param[in] + + This Pointer to the protocol instance + FvidPointer Pointer to a table to be updated + FrequencyCorrectionFactor Applicable frequency correction factor, the processor core frequency. + PpmCstTmrFlags Flag of update TSC MSR if C3 or C4 + PpmTscCorrFactor TSC correction factor + PpmTscCorrFactorRem TSC correction factor remainder + + @retval + + EFI_SUCCESS Processor TSC support configured successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *ENABLE_TSC) ( + IN OUT PPM_PROCESSOR_SUPPORT_PROTOCOL_2 *This, + IN OUT FVID_TABLE *FvidPointer, + IN UINT16 FrequencyCorrectionFactor, + IN OUT UINT8 *PpmCstTmrFlags, + IN OUT UINTN *PpmTscCorrFactor, + IN OUT UINTN *PpmTscCorrFactorRem + ); + +/** + Save processor MSR runtime settings for S3. + + @param[in] + + This Pointer to the protocol instance + + @retval + + EFI_SUCCESS Processor MSR setting is saved. + +**/ +typedef +EFI_STATUS +(EFIAPI *S3_SAVE_MSR) ( + IN OUT PPM_PROCESSOR_SUPPORT_PROTOCOL_2 *This + ); + +/** + Restore processor MSR runtime settings for S3. + + @param[in] + + This Pointer to the protocol instance + + @retval + + EFI_SUCCESS Processor MSR setting is restored. + +**/ +typedef +EFI_STATUS +(EFIAPI *S3_RESTORE_MSR) ( + IN OUT PPM_PROCESSOR_SUPPORT_PROTOCOL_2 *This + ); + +/** + Enable IO redirection C state control. + This should only be enabled if the OS and processor driver support + independent C state control for C2 and higher. + + This will cause the processor to capture LVL_X reads and perform the requested + C state transition. + + This cannot be enabled when SMI based C state coordination is enabled, + so this function will disable SMI based C state coordination. + + @param[in] + + This Pointer to the protocol instance + + @retval + + EFI_SUCCESS Processor IO redirection C state control enabled. + +**/ +typedef +EFI_STATUS +(EFIAPI *ENABLE_C_STATE_IO_REDIRECTION) ( + IN OUT PPM_PROCESSOR_SUPPORT_PROTOCOL_2 *This + ); + +/** + Disable IO redirection C state control. + + @param[in] + + This Pointer to the protocol instance + + @retval + + EFI_SUCCESS Processor IO redirection C state control disabled. + +**/ +typedef +EFI_STATUS +(EFIAPI *DISABLE_C_STATE_IO_REDIRECTION) ( + IN OUT PPM_PROCESSOR_SUPPORT_PROTOCOL_2 *This + ); + +/** + Enable SMI based C state coordination. + This should only be enabled if the OS and processor driver do not support + independent C state control for C2 and higher. + This will cause an SMI to be generated when both processors enter autohalt state. + + This cannot be enabled when IO redirection control is enabled, so this function + will disable IO redirection control. + + @param[in] + + This Pointer to the protocol instance + + @retval + + EFI_SUCCESS Processor SMI based C state coordination enabled. + +**/ +typedef +EFI_STATUS +(EFIAPI *ENABLE_C_STATE_SMI_COORDINATION) ( + IN OUT PPM_PROCESSOR_SUPPORT_PROTOCOL_2 *This + ); + +/** + Disable SMI based C state coordination. + + @param[in] + + This Pointer to the protocol instance + + @retval + + EFI_SUCCESS Processor SMI based C state coordination disabled. + +**/ +typedef +EFI_STATUS +(EFIAPI *DISABLE_C_STATE_SMI_COORDINATION) ( + IN OUT PPM_PROCESSOR_SUPPORT_PROTOCOL_2 *This + ); + +/** + Enable the Geyserville hardware coordination of P-states. + + @param[in] + + This Pointer to the protocol instance + + @retval + + EFI_SUCCESS Hardware coordination enabled. + +**/ +typedef +EFI_STATUS +(EFIAPI *ENABLE_P_STATE_HARDWARE_COORDINATION) ( + IN OUT PPM_PROCESSOR_SUPPORT_PROTOCOL_2 *This + ); + +/** + Disable the Geyserville hardware coordination of P-states. + + @param[in] + + This Pointer to the protocol instance + + @retval + + EFI_SUCCESS Hardware coordination disabled. + +**/ +typedef +EFI_STATUS +(EFIAPI *DISABLE_P_STATE_HARDWARE_COORDINATION) ( + IN OUT PPM_PROCESSOR_SUPPORT_PROTOCOL_2 *This + ); + +/** + This function enables EMTTM support in the processor. + + @param[in] + + This Pointer to the protocol instance + FvidPointer Pointer to a table to be updated + + @retval + + EFI_SUCCESS EMTTM enabled in the processor. + +**/ +typedef +EFI_STATUS +(EFIAPI *ENABLE_EMTTM) ( + IN OUT PPM_PROCESSOR_SUPPORT_PROTOCOL_2 *This, + IN OUT FVID_TABLE *FvidPointer + ); + +/** + This function causes the specified processor to transition to a new P state. + + The function may be provided by either the protocol producer or consumer. + If the protocol producer provides this function, it should take precedence over + a consumer version. + + E.G. If the protocol producer does not provide the function, it will be NULL in + the protocol structure. The consumer would detect this and update the protocol + with a function to provide this service. + If the protocol producer does provide this service, the consumer should not + update the protocol. + + @param[in] + + This Pointer to the protocol instance + FvidPointer Pointer to a table containing P state information + CpuNumber The processor thread to perform the transition on + NextState The desired state (zero based) from the provided FVID table + + @retval + + EFI_SUCCESS The specified processor was transitioned to the requested state. + +**/ +typedef +EFI_STATUS +(EFIAPI *P_STATE_TRANSITION) ( + IN OUT PPM_PROCESSOR_SUPPORT_PROTOCOL_2 *This, + IN FVID_TABLE *FvidPointer, + IN UINTN CpuNumber, + IN UINTN NextState + ); + +/** + Initializes required structures for P-State table creation and enables GV3 + support in the processor. + + @param[in] + + This Pointer to the protocol instance + FvidPointer Pointer to a table to be updated + + @retval + + EFI_SUCCESS + +**/ +typedef +EFI_STATUS +(EFIAPI *INIT_GV3) ( + IN OUT PPM_PROCESSOR_SUPPORT_PROTOCOL_2 *This, + IN OUT FVID_TABLE *FvidPointer, + IN OUT PPM_PLATFORM_POLICY_PROTOCOL * PPMPolicy + ); + +/** + Enable C6 residency under Windows XP SP1 and SP2. + + @param[in] + + This Pointer to the protocol instance + + @retval + + EFI_SUCCESS + +**/ +typedef +EFI_STATUS +(EFIAPI *ENABLE_C6_RESIDENCY) ( + IN OUT PPM_PROCESSOR_SUPPORT_PROTOCOL_2 *This + ); + +/** + Locks various PPM Configurations. + + @param[in] + + PpmPolicy Pointer to PPM Policy structure + + @retval + + EFI_SUCCESS + +-- +typedef +EFI_STATUS +(EFIAPI *PPM_LOCK_SETTINGS) ( + IN OUT PPM_PLATFORM_POLICY_PROTOCOL_2 * PPMPolicy + ); + +*/ +typedef +EFI_STATUS +(EFIAPI *POWER_SOURCE_CHANGE) ( + IN OUT PPM_PROCESSOR_SUPPORT_PROTOCOL_2 *This, + IN BOOLEAN PowerSource + ); + +/** + Set processor P state when Eist is disabled. + + @param[in] + + This Pointer to the protocol instance + + @retval + + EFI_SUCCESS Processor MSR setting is saved. + +**/ +typedef +EFI_STATUS +(EFIAPI *PPM_SET_BOOT_P_STATE) ( + IN OUT PPM_PROCESSOR_SUPPORT_PROTOCOL_2 *This + ); + +/** + - Configures following fields of MSR 0x610 based on user configuration: + - Configures Long duration Turbo Mode (power limit 1) power level and time window + - Configures Short duration turbo mode (power limit 2) + + @param[in] + + This Pointer to the protocol instance + PPMPolicy Pointer to policy protocol instance + + @retval + + None + +**/ +typedef +VOID +(EFIAPI *CONFIGURE_TURBO_POWER_LIMIT) ( + IN OUT PPM_PROCESSOR_SUPPORT_PROTOCOL_2 *This, + IN OUT PPM_PLATFORM_POLICY_PROTOCOL *PPMPolicy + ); + +/** + Perform any processor configuration required on power source change event. + + @param[in] + + This Pointer to the protocol instance + PowerSource Current power source, TRUE = AC power, FALSE = Battery power + + @retval + + EFI_SUCCESS + +**/ + +// +// Protocol data structure definition +// +typedef struct _PPM_PROCESSOR_SUPPORT_PROTOCOL_2 { + UINT32 PpmFlags; + UINT32 PpmFeatureFlags; + + SET_PPM_FLAGS SetPpmFlags; + ENABLE_C_STATES EnableCStates; + INIT_GV3 InitGv3; + CONFIGURE_TURBO_POWER_LIMIT ConfigureTurboPowerLimit; + INIT_THERMAL InitThermal; + ENABLE_TM EnableTm; + ENABLE_PROC_HOT EnableProcHot; + ENABLE_TSC EnableTsc; + ENABLE_EMTTM EnableEmttm; OPTIONAL + + S3_SAVE_MSR S3SaveMsr; + S3_RESTORE_MSR S3RestoreMsr; + PPM_SET_BOOT_P_STATE SetBootPState; + ENABLE_C_STATE_IO_REDIRECTION EnableCStateIoRedirection; OPTIONAL + DISABLE_C_STATE_IO_REDIRECTION DisableCStateIoRedirection; OPTIONAL + + ENABLE_P_STATE_HARDWARE_COORDINATION EnablePStateHardwareCoordination; OPTIONAL + DISABLE_P_STATE_HARDWARE_COORDINATION DisablePStateHardwareCoordination; OPTIONAL + ENABLE_C6_RESIDENCY EnableC6Residency; OPTIONAL + + // + // If this function is not-null, consumers should use the processor specific transition code + // Otherwise, consumer code may update this with a P state transition function + // + P_STATE_TRANSITION PStateTransition; OPTIONAL + + POWER_SOURCE_CHANGE PowerSourceChange; OPTIONAL + +} PPM_PROCESSOR_SUPPORT_PROTOCOL_2; + +#endif -- cgit v1.2.3