From ebeffc42b4ed3b6e74b6cb6a17c47503d6a5d72a Mon Sep 17 00:00:00 2001 From: andrewfish Date: Tue, 18 May 2010 21:04:30 +0000 Subject: Added stub RTC lib, turned on option of building debug agent (GDB STUB) into SEC. Added the platform library template needed to break into GDB stub with ctrl-c. Cleaned up PCDs for selecting serial ports for Console or GDB usage. Filled in GDB Serial Port lib. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10509 6f19259b-4bc3-4df7-8a09-765794883524 --- ArmEbPkg/Library/TimerLib/TimerLib.c | 108 ++++++++++++++++++++++++++++++----- 1 file changed, 94 insertions(+), 14 deletions(-) (limited to 'ArmEbPkg/Library/TimerLib') diff --git a/ArmEbPkg/Library/TimerLib/TimerLib.c b/ArmEbPkg/Library/TimerLib/TimerLib.c index c2a2a90736..c56b77acaa 100755 --- a/ArmEbPkg/Library/TimerLib/TimerLib.c +++ b/ArmEbPkg/Library/TimerLib/TimerLib.c @@ -1,4 +1,22 @@ /** @file + TimerLib for ARM EB. Hardcoded to 100ns period + + This library assume the following initialization, usually done in SEC. + + // configure SP810 to use 1MHz clock and disable + MmioAndThenOr32 (EB_SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK); + // Enable + MmioOr32 (EB_SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER2_EN); + + // configure timer 2 for one shot operation, 32 bits, no prescaler, and interrupt disabled + MmioOr32 (EB_SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ONESHOT | SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1); + + // preload the timer count register + MmioWrite32 (EB_SP804_TIMER2_BASE + SP804_TIMER_LOAD_REG, 1); + + // enable the timer + MmioOr32 (EB_SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE); + Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
@@ -20,7 +38,19 @@ #include #include +#include + + +/** + Stalls the CPU for at least the given number of microseconds. + Stalls the CPU for the number of microseconds specified by MicroSeconds. + + @param MicroSeconds The minimum number of microseconds to delay. + + @return The value of MicroSeconds inputted. + +**/ UINTN EFIAPI MicroSecondDelay ( @@ -41,41 +71,89 @@ MicroSecondDelay ( return MicroSeconds; } +/** + Stalls the CPU for at least the given number of nanoseconds. + + Stalls the CPU for the number of nanoseconds specified by NanoSeconds. + + @param NanoSeconds The minimum number of nanoseconds to delay. + + @return The value of NanoSeconds inputted. + +**/ UINTN EFIAPI NanoSecondDelay ( IN UINTN NanoSeconds ) { - UINT32 Delay; - UINT32 StartTime; - UINT32 CurrentTime; - UINT32 ElapsedTime; + UINT32 TickNumber; - - Delay = (NanoSeconds / PcdGet32(PcdEmbeddedPerformanceCounterPeriodInNanoseconds)) + 1; + if (NanoSeconds == 0) { + return NanoSeconds; + } - StartTime = MmioRead32 (0); - do - { - CurrentTime = 0ULL; - ElapsedTime = CurrentTime - StartTime; - } while (ElapsedTime < Delay); + // Round up to 100ns Tick Number + TickNumber = (UINT32)NanoSeconds / 100; + TickNumber += ((UINT32)NanoSeconds % 100) == 0 ? 0 : 1; - NanoSeconds = ElapsedTime * PcdGet32 (PcdEmbeddedPerformanceCounterPeriodInNanoseconds); + // load the timer count register + MmioWrite32 (EB_SP804_TIMER2_BASE + SP804_TIMER_LOAD_REG, TickNumber); + while (MmioRead32 (EB_SP804_TIMER2_BASE + SP804_TIMER_CURRENT_REG) > 0) { + ; + } + return NanoSeconds; } +/** + Retrieves the current value of a 64-bit free running performance counter. + + The counter can either count up by 1 or count down by 1. If the physical + performance counter counts by a larger increment, then the counter values + must be translated. The properties of the counter can be retrieved from + GetPerformanceCounterProperties(). + + @return The current value of the free running performance counter. + +**/ UINT64 EFIAPI GetPerformanceCounter ( VOID ) { + // Free running 64-bit/32-bit counter is needed here. + // Don't think we need this to boot, just to do performance profile + ASSERT (FALSE); return (UINT64)0ULL; } + +/** + Retrieves the 64-bit frequency in Hz and the range of performance counter + values. + + If StartValue is not NULL, then the value that the performance counter starts + with immediately after is it rolls over is returned in StartValue. If + EndValue is not NULL, then the value that the performance counter end with + immediately before it rolls over is returned in EndValue. The 64-bit + frequency of the performance counter in Hz is always returned. If StartValue + is less than EndValue, then the performance counter counts up. If StartValue + is greater than EndValue, then the performance counter counts down. For + example, a 64-bit free running counter that counts up would have a StartValue + of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter + that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0. + + @param StartValue The value the performance counter starts with when it + rolls over. + @param EndValue The value that the performance counter ends with before + it rolls over. + + @return The frequency in Hz. + +**/ UINT64 EFIAPI GetPerformanceCounterProperties ( @@ -93,5 +171,7 @@ GetPerformanceCounterProperties ( *EndValue = 0xFFFFFFFF; } - return PcdGet64(PcdEmbeddedPerformanceCounterFrequencyInHz); + return 100; } + + -- cgit v1.2.3