From 3402aac7d985bf8a9f9d3c639f3fe93609380513 Mon Sep 17 00:00:00 2001 From: Ronald Cron Date: Tue, 19 Aug 2014 13:29:52 +0000 Subject: ARM Packages: Removed trailing spaces Trailing spaces create issue/warning when generating/applying patches. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron Reviewed-By: Olivier Martin git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15833 6f19259b-4bc3-4df7-8a09-765794883524 --- ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.S | 74 +++++++++++++------------- 1 file changed, 37 insertions(+), 37 deletions(-) (limited to 'ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.S') diff --git a/ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.S b/ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.S index 6a1a15570f..3433b99cd4 100644 --- a/ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.S +++ b/ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.S @@ -1,4 +1,4 @@ -#------------------------------------------------------------------------------ +#------------------------------------------------------------------------------ # # Use ARMv6 instruction to operate on a single stack # @@ -22,7 +22,7 @@ This is the stack constructed by the exception handler (low address to high address) # R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM Reg Offset - === ====== + === ====== R0 0x00 # stmfd SP!,{R0-R12} R1 0x04 R2 0x08 @@ -44,14 +44,14 @@ This is the stack constructed by the exception handler (low address to high addr DFAR 0x48 IFSR 0x4c IFAR 0x50 - + LR 0x54 # SVC Link register (we need to restore it) - - LR 0x58 # pushed by srsfd - CPSR 0x5c + + LR 0x58 # pushed by srsfd + CPSR 0x5c */ - + GCC_ASM_EXPORT(ExceptionHandlersStart) GCC_ASM_EXPORT(ExceptionHandlersEnd) @@ -103,7 +103,7 @@ ASM_PFX(ResetEntry): stmfd SP!,{LR} @ Store the link register for the current mode sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR stmfd SP!,{R0-R12} @ Store the register state - + mov R0,#0 @ ExceptionType ldr R1,ASM_PFX(CommonExceptionEntry) bx R1 @@ -200,53 +200,53 @@ ASM_PFX(CommonExceptionEntry): ASM_PFX(ExceptionHandlersEnd): // -// This code runs from CpuDxe driver loaded address. It is patched into +// This code runs from CpuDxe driver loaded address. It is patched into // CommonExceptionEntry. // ASM_PFX(AsmCommonExceptionEntry): mrc p15, 0, R1, c6, c0, 2 @ Read IFAR - str R1, [SP, #0x50] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR - + str R1, [SP, #0x50] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR + mrc p15, 0, R1, c5, c0, 1 @ Read IFSR str R1, [SP, #0x4c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR - + mrc p15, 0, R1, c6, c0, 0 @ Read DFAR str R1, [SP, #0x48] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR - + mrc p15, 0, R1, c5, c0, 0 @ Read DFSR str R1, [SP, #0x44] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR - - ldr R1, [SP, #0x5c] @ srsdb saved pre-exception CPSR on the stack + + ldr R1, [SP, #0x5c] @ srsdb saved pre-exception CPSR on the stack str R1, [SP, #0x40] @ Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR and R3, R1, #0x1f @ Check CPSR to see if User or System Mode cmp R3, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1f)) - cmpne R3, #0x10 @ + cmpne R3, #0x10 @ stmeqed R2, {lr}^ @ save unbanked lr - @ else + @ else stmneed R2, {lr} @ save SVC lr - ldr R5, [SP, #0x58] @ PC is the LR pushed by srsfd + ldr R5, [SP, #0x58] @ PC is the LR pushed by srsfd @ Check to see if we have to adjust for Thumb entry sub r4, r0, #1 @ if (ExceptionType == 1 || ExceptionType == 2)) { - cmp r4, #1 @ // UND & SVC have differnt LR adjust for Thumb + cmp r4, #1 @ // UND & SVC have differnt LR adjust for Thumb bhi NoAdjustNeeded - - tst r1, #0x20 @ if ((CPSR & T)) == T) { // Thumb Mode on entry + + tst r1, #0x20 @ if ((CPSR & T)) == T) { // Thumb Mode on entry addne R5, R5, #2 @ PC += 2; strne R5,[SP,#0x58] @ Update LR value pushed by srsfd - + NoAdjustNeeded: str R5, [SP, #0x3c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.PC - + add R1, SP, #0x60 @ We pushed 0x60 bytes on the stack str R1, [SP, #0x34] @ Store it in EFI_SYSTEM_CONTEXT_ARM.SP - - @ R0 is ExceptionType - mov R1,SP @ R1 is SystemContext + + @ R0 is ExceptionType + mov R1,SP @ R1 is SystemContext #if (FixedPcdGet32(PcdVFPEnabled)) vpush {d0-d15} @ save vstm registers in case they are used in optimizations @@ -256,7 +256,7 @@ NoAdjustNeeded: tst R4, #4 subne SP, SP, #4 @ Adjust SP if not 8-byte aligned -/* +/* VOID EFIAPI CommonCExceptionHandler ( @@ -264,13 +264,13 @@ CommonCExceptionHandler ( IN OUT EFI_SYSTEM_CONTEXT SystemContext R1 ) -*/ +*/ blx ASM_PFX(CommonCExceptionHandler) @ Call exception handler mov SP, R4 @ Restore SP #if (FixedPcdGet32(PcdVFPEnabled)) - vpop {d0-d15} + vpop {d0-d15} #endif ldr R1, [SP, #0x4c] @ Restore EFI_SYSTEM_CONTEXT_ARM.IFSR @@ -278,26 +278,26 @@ CommonCExceptionHandler ( ldr R1, [SP, #0x44] @ Restore EFI_SYSTEM_CONTEXT_ARM.DFSR mcr p15, 0, R1, c5, c0, 0 @ Write DFSR - + ldr R1,[SP,#0x3c] @ EFI_SYSTEM_CONTEXT_ARM.PC - str R1,[SP,#0x58] @ Store it back to srsfd stack slot so it can be restored + str R1,[SP,#0x58] @ Store it back to srsfd stack slot so it can be restored ldr R1,[SP,#0x40] @ EFI_SYSTEM_CONTEXT_ARM.CPSR - str R1,[SP,#0x5c] @ Store it back to srsfd stack slot so it can be restored - + str R1,[SP,#0x5c] @ Store it back to srsfd stack slot so it can be restored + add R3, SP, #0x54 @ Make R3 point to SVC LR saved on entry add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR and R1, R1, #0x1f @ Check to see if User or System Mode cmp R1, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1f)) - cmpne R1, #0x10 @ + cmpne R1, #0x10 @ ldmeqed R2, {lr}^ @ restore unbanked lr @ else ldmneed R3, {lr} @ restore SVC lr, via ldmfd SP!, {LR} - + ldmfd SP!,{R0-R12} @ Restore general purpose registers @ Exception handler can not change SP - + add SP,SP,#0x20 @ Clear out the remaining stack space ldmfd SP!,{LR} @ restore the link register for this context rfefd SP! @ return from exception via srsfd stack slot - + -- cgit v1.2.3