From 6c128c65b5ec0e5b8b5a0ccb165f3afd29e485f8 Mon Sep 17 00:00:00 2001 From: Guo Mang Date: Wed, 2 Aug 2017 09:54:47 +0800 Subject: Remove core packages since we can get them from edk2 repository Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang --- ArmPkg/Drivers/CpuDxe/AArch64/Exception.c | 154 ---- ArmPkg/Drivers/CpuDxe/AArch64/ExceptionSupport.S | 394 ---------- ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c | 344 --------- ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.S | 191 ----- ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.asm | 152 ---- ArmPkg/Drivers/CpuDxe/ArmV6/Exception.c | 234 ------ ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.S | 303 -------- ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.asm | 301 -------- ArmPkg/Drivers/CpuDxe/ArmV6/Mmu.c | 880 ----------------------- ArmPkg/Drivers/CpuDxe/CpuDxe.c | 280 -------- ArmPkg/Drivers/CpuDxe/CpuDxe.h | 182 ----- ArmPkg/Drivers/CpuDxe/CpuDxe.inf | 93 --- ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c | 282 -------- ArmPkg/Drivers/CpuDxe/CpuMpCore.c | 103 --- 14 files changed, 3893 deletions(-) delete mode 100644 ArmPkg/Drivers/CpuDxe/AArch64/Exception.c delete mode 100644 ArmPkg/Drivers/CpuDxe/AArch64/ExceptionSupport.S delete mode 100644 ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c delete mode 100644 ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.S delete mode 100644 ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.asm delete mode 100644 ArmPkg/Drivers/CpuDxe/ArmV6/Exception.c delete mode 100644 ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.S delete mode 100644 ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.asm delete mode 100644 ArmPkg/Drivers/CpuDxe/ArmV6/Mmu.c delete mode 100644 ArmPkg/Drivers/CpuDxe/CpuDxe.c delete mode 100644 ArmPkg/Drivers/CpuDxe/CpuDxe.h delete mode 100644 ArmPkg/Drivers/CpuDxe/CpuDxe.inf delete mode 100644 ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c delete mode 100644 ArmPkg/Drivers/CpuDxe/CpuMpCore.c (limited to 'ArmPkg/Drivers/CpuDxe') diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/Exception.c b/ArmPkg/Drivers/CpuDxe/AArch64/Exception.c deleted file mode 100644 index ce1c6ce09a..0000000000 --- a/ArmPkg/Drivers/CpuDxe/AArch64/Exception.c +++ /dev/null @@ -1,154 +0,0 @@ -/** @file - - Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
- Portions Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include "CpuDxe.h" - -#include - -VOID -ExceptionHandlersStart ( - VOID - ); - -VOID -ExceptionHandlersEnd ( - VOID - ); - -VOID -CommonExceptionEntry ( - VOID - ); - -VOID -AsmCommonExceptionEntry ( - VOID - ); - - -EFI_EXCEPTION_CALLBACK gExceptionHandlers[MAX_AARCH64_EXCEPTION + 1]; -EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[MAX_AARCH64_EXCEPTION + 1]; - - - -/** - This function registers and enables the handler specified by InterruptHandler for a processor - interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the - handler for the processor interrupt or exception type specified by InterruptType is uninstalled. - The installed handler is called once for each processor interrupt or exception. - - @param InterruptType A pointer to the processor's current interrupt state. Set to TRUE if interrupts - are enabled and FALSE if interrupts are disabled. - @param InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called - when a processor interrupt occurs. If this parameter is NULL, then the handler - will be uninstalled. - - @retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled. - @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was - previously installed. - @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not - previously installed. - @retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported. - -**/ -EFI_STATUS -RegisterInterruptHandler ( - IN EFI_EXCEPTION_TYPE InterruptType, - IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler - ) -{ - if (InterruptType > MAX_AARCH64_EXCEPTION) { - return EFI_UNSUPPORTED; - } - - if ((InterruptHandler != NULL) && (gExceptionHandlers[InterruptType] != NULL)) { - return EFI_ALREADY_STARTED; - } - - gExceptionHandlers[InterruptType] = InterruptHandler; - - return EFI_SUCCESS; -} - - - -VOID -EFIAPI -CommonCExceptionHandler ( - IN EFI_EXCEPTION_TYPE ExceptionType, - IN OUT EFI_SYSTEM_CONTEXT SystemContext - ) -{ - if (ExceptionType <= MAX_AARCH64_EXCEPTION) { - if (gExceptionHandlers[ExceptionType]) { - gExceptionHandlers[ExceptionType] (ExceptionType, SystemContext); - return; - } - } else { - DEBUG ((EFI_D_ERROR, "Unknown exception type %d from %016lx\n", ExceptionType, SystemContext.SystemContextAArch64->ELR)); - ASSERT (FALSE); - } - - DefaultExceptionHandler (ExceptionType, SystemContext); -} - - - -EFI_STATUS -InitializeExceptions ( - IN EFI_CPU_ARCH_PROTOCOL *Cpu - ) -{ - EFI_STATUS Status; - BOOLEAN IrqEnabled; - BOOLEAN FiqEnabled; - - Status = EFI_SUCCESS; - ZeroMem (gExceptionHandlers,sizeof(*gExceptionHandlers)); - - // - // Disable interrupts - // - Cpu->GetInterruptState (Cpu, &IrqEnabled); - Cpu->DisableInterrupt (Cpu); - - // - // EFI does not use the FIQ, but a debugger might so we must disable - // as we take over the exception vectors. - // - FiqEnabled = ArmGetFiqState (); - ArmDisableFiq (); - - // The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure 'Align=4K' - // is defined into your FDF for this module. - ASSERT (((UINTN)ExceptionHandlersStart & ARM_VECTOR_TABLE_ALIGNMENT) == 0); - - // We do not copy the Exception Table at PcdGet32(PcdCpuVectorBaseAddress). We just set Vector - // Base Address to point into CpuDxe code. - ArmWriteVBar ((UINTN)ExceptionHandlersStart); - - if (FiqEnabled) { - ArmEnableFiq (); - } - - if (IrqEnabled) { - // - // Restore interrupt state - // - Status = Cpu->EnableInterrupt (Cpu); - } - - return Status; -} diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/ExceptionSupport.S b/ArmPkg/Drivers/CpuDxe/AArch64/ExceptionSupport.S deleted file mode 100644 index 2682f4fe75..0000000000 --- a/ArmPkg/Drivers/CpuDxe/AArch64/ExceptionSupport.S +++ /dev/null @@ -1,394 +0,0 @@ -// -// Copyright (c) 2011 - 2014 ARM LTD. All rights reserved.
-// Portion of Copyright (c) 2014 NVIDIA Corporation. All rights reserved.
-// -// This program and the accompanying materials -// are licensed and made available under the terms and conditions of the BSD License -// which accompanies this distribution. The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -// -//------------------------------------------------------------------------------ - -#include -#include - -/* - This is the stack constructed by the exception handler (low address to high address). - X0 to FAR makes up the EFI_SYSTEM_CONTEXT for AArch64. - - UINT64 X0; 0x000 - UINT64 X1; 0x008 - UINT64 X2; 0x010 - UINT64 X3; 0x018 - UINT64 X4; 0x020 - UINT64 X5; 0x028 - UINT64 X6; 0x030 - UINT64 X7; 0x038 - UINT64 X8; 0x040 - UINT64 X9; 0x048 - UINT64 X10; 0x050 - UINT64 X11; 0x058 - UINT64 X12; 0x060 - UINT64 X13; 0x068 - UINT64 X14; 0x070 - UINT64 X15; 0x078 - UINT64 X16; 0x080 - UINT64 X17; 0x088 - UINT64 X18; 0x090 - UINT64 X19; 0x098 - UINT64 X20; 0x0a0 - UINT64 X21; 0x0a8 - UINT64 X22; 0x0b0 - UINT64 X23; 0x0b8 - UINT64 X24; 0x0c0 - UINT64 X25; 0x0c8 - UINT64 X26; 0x0d0 - UINT64 X27; 0x0d8 - UINT64 X28; 0x0e0 - UINT64 FP; 0x0e8 // x29 - Frame Pointer - UINT64 LR; 0x0f0 // x30 - Link Register - UINT64 SP; 0x0f8 // x31 - Stack Pointer - - // FP/SIMD Registers. 128bit if used as Q-regs. - UINT64 V0[2]; 0x100 - UINT64 V1[2]; 0x110 - UINT64 V2[2]; 0x120 - UINT64 V3[2]; 0x130 - UINT64 V4[2]; 0x140 - UINT64 V5[2]; 0x150 - UINT64 V6[2]; 0x160 - UINT64 V7[2]; 0x170 - UINT64 V8[2]; 0x180 - UINT64 V9[2]; 0x190 - UINT64 V10[2]; 0x1a0 - UINT64 V11[2]; 0x1b0 - UINT64 V12[2]; 0x1c0 - UINT64 V13[2]; 0x1d0 - UINT64 V14[2]; 0x1e0 - UINT64 V15[2]; 0x1f0 - UINT64 V16[2]; 0x200 - UINT64 V17[2]; 0x210 - UINT64 V18[2]; 0x220 - UINT64 V19[2]; 0x230 - UINT64 V20[2]; 0x240 - UINT64 V21[2]; 0x250 - UINT64 V22[2]; 0x260 - UINT64 V23[2]; 0x270 - UINT64 V24[2]; 0x280 - UINT64 V25[2]; 0x290 - UINT64 V26[2]; 0x2a0 - UINT64 V27[2]; 0x2b0 - UINT64 V28[2]; 0x2c0 - UINT64 V29[2]; 0x2d0 - UINT64 V30[2]; 0x2e0 - UINT64 V31[2]; 0x2f0 - - // System Context - UINT64 ELR; 0x300 // Exception Link Register - UINT64 SPSR; 0x308 // Saved Processor Status Register - UINT64 FPSR; 0x310 // Floating Point Status Register - UINT64 ESR; 0x318 // Exception syndrome register - UINT64 FAR; 0x320 // Fault Address Register - UINT64 Padding;0x328 // Required for stack alignment -*/ - -GCC_ASM_EXPORT(ExceptionHandlersStart) -GCC_ASM_EXPORT(ExceptionHandlersEnd) -GCC_ASM_EXPORT(CommonExceptionEntry) -GCC_ASM_EXPORT(AsmCommonExceptionEntry) -GCC_ASM_EXPORT(CommonCExceptionHandler) - -.text -.align 11 - -#define GP_CONTEXT_SIZE (32 * 8) -#define FP_CONTEXT_SIZE (32 * 16) -#define SYS_CONTEXT_SIZE ( 6 * 8) // 5 SYS regs + Alignment requirement (ie: the stack must be aligned on 0x10) - -// Cannot str x31 directly -#define ALL_GP_REGS \ - REG_PAIR (x0, x1, 0x000, GP_CONTEXT_SIZE); \ - REG_PAIR (x2, x3, 0x010, GP_CONTEXT_SIZE); \ - REG_PAIR (x4, x5, 0x020, GP_CONTEXT_SIZE); \ - REG_PAIR (x6, x7, 0x030, GP_CONTEXT_SIZE); \ - REG_PAIR (x8, x9, 0x040, GP_CONTEXT_SIZE); \ - REG_PAIR (x10, x11, 0x050, GP_CONTEXT_SIZE); \ - REG_PAIR (x12, x13, 0x060, GP_CONTEXT_SIZE); \ - REG_PAIR (x14, x15, 0x070, GP_CONTEXT_SIZE); \ - REG_PAIR (x16, x17, 0x080, GP_CONTEXT_SIZE); \ - REG_PAIR (x18, x19, 0x090, GP_CONTEXT_SIZE); \ - REG_PAIR (x20, x21, 0x0a0, GP_CONTEXT_SIZE); \ - REG_PAIR (x22, x23, 0x0b0, GP_CONTEXT_SIZE); \ - REG_PAIR (x24, x25, 0x0c0, GP_CONTEXT_SIZE); \ - REG_PAIR (x26, x27, 0x0d0, GP_CONTEXT_SIZE); \ - REG_PAIR (x28, x29, 0x0e0, GP_CONTEXT_SIZE); \ - REG_ONE (x30, 0x0f0, GP_CONTEXT_SIZE); - -// In order to save the SP we need to put it somewhere else first. -// STR only works with XZR/WZR directly -#define SAVE_SP \ - add x1, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE); \ - REG_ONE (x1, 0x0f8, GP_CONTEXT_SIZE); - -#define ALL_FP_REGS \ - REG_PAIR (q0, q1, 0x000, FP_CONTEXT_SIZE); \ - REG_PAIR (q2, q3, 0x020, FP_CONTEXT_SIZE); \ - REG_PAIR (q4, q5, 0x040, FP_CONTEXT_SIZE); \ - REG_PAIR (q6, q7, 0x060, FP_CONTEXT_SIZE); \ - REG_PAIR (q8, q9, 0x080, FP_CONTEXT_SIZE); \ - REG_PAIR (q10, q11, 0x0a0, FP_CONTEXT_SIZE); \ - REG_PAIR (q12, q13, 0x0c0, FP_CONTEXT_SIZE); \ - REG_PAIR (q14, q15, 0x0e0, FP_CONTEXT_SIZE); \ - REG_PAIR (q16, q17, 0x100, FP_CONTEXT_SIZE); \ - REG_PAIR (q18, q19, 0x120, FP_CONTEXT_SIZE); \ - REG_PAIR (q20, q21, 0x140, FP_CONTEXT_SIZE); \ - REG_PAIR (q22, q23, 0x160, FP_CONTEXT_SIZE); \ - REG_PAIR (q24, q25, 0x180, FP_CONTEXT_SIZE); \ - REG_PAIR (q26, q27, 0x1a0, FP_CONTEXT_SIZE); \ - REG_PAIR (q28, q29, 0x1c0, FP_CONTEXT_SIZE); \ - REG_PAIR (q30, q31, 0x1e0, FP_CONTEXT_SIZE); - -#define ALL_SYS_REGS \ - REG_PAIR (x1, x2, 0x000, SYS_CONTEXT_SIZE); \ - REG_PAIR (x3, x4, 0x010, SYS_CONTEXT_SIZE); \ - REG_ONE (x5, 0x020, SYS_CONTEXT_SIZE); - -// -// This code gets copied to the ARM vector table -// VectorTableStart - VectorTableEnd gets copied -// -ASM_PFX(ExceptionHandlersStart): - -// -// Current EL with SP0 : 0x0 - 0x180 -// -.align 7 -ASM_PFX(SynchronousExceptionSP0): - b ASM_PFX(SynchronousExceptionEntry) - -.align 7 -ASM_PFX(IrqSP0): - b ASM_PFX(IrqEntry) - -.align 7 -ASM_PFX(FiqSP0): - b ASM_PFX(FiqEntry) - -.align 7 -ASM_PFX(SErrorSP0): - b ASM_PFX(SErrorEntry) - -// -// Current EL with SPx: 0x200 - 0x380 -// -.align 7 -ASM_PFX(SynchronousExceptionSPx): - b ASM_PFX(SynchronousExceptionEntry) - -.align 7 -ASM_PFX(IrqSPx): - b ASM_PFX(IrqEntry) - -.align 7 -ASM_PFX(FiqSPx): - b ASM_PFX(FiqEntry) - -.align 7 -ASM_PFX(SErrorSPx): - b ASM_PFX(SErrorEntry) - -// -// Lower EL using AArch64 : 0x400 - 0x580 -// -.align 7 -ASM_PFX(SynchronousExceptionA64): - b ASM_PFX(SynchronousExceptionEntry) - -.align 7 -ASM_PFX(IrqA64): - b ASM_PFX(IrqEntry) - -.align 7 -ASM_PFX(FiqA64): - b ASM_PFX(FiqEntry) - -.align 7 -ASM_PFX(SErrorA64): - b ASM_PFX(SErrorEntry) - -// -// Lower EL using AArch32 : 0x0 - 0x180 -// -.align 7 -ASM_PFX(SynchronousExceptionA32): - b ASM_PFX(SynchronousExceptionEntry) - -.align 7 -ASM_PFX(IrqA32): - b ASM_PFX(IrqEntry) - -.align 7 -ASM_PFX(FiqA32): - b ASM_PFX(FiqEntry) - -.align 7 -ASM_PFX(SErrorA32): - b ASM_PFX(SErrorEntry) - - -#undef REG_PAIR -#undef REG_ONE -#define REG_PAIR(REG1, REG2, OFFSET, CONTEXT_SIZE) stp REG1, REG2, [sp, #(OFFSET-CONTEXT_SIZE)] -#define REG_ONE(REG1, OFFSET, CONTEXT_SIZE) stur REG1, [sp, #(OFFSET-CONTEXT_SIZE)] - -ASM_PFX(SynchronousExceptionEntry): - // Move the stackpointer so we can reach our structure with the str instruction. - sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE) - - // Save all the General regs before touching x0 and x1. - // This does not save r31(SP) as it is special. We do that later. - ALL_GP_REGS - - // Record the type of exception that occurred. - mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS - - // Jump to our general handler to deal with all the common parts and process the exception. - ldr x1, ASM_PFX(CommonExceptionEntry) - br x1 - -ASM_PFX(IrqEntry): - sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE) - ALL_GP_REGS - mov x0, #EXCEPT_AARCH64_IRQ - ldr x1, ASM_PFX(CommonExceptionEntry) - br x1 - -ASM_PFX(FiqEntry): - sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE) - ALL_GP_REGS - mov x0, #EXCEPT_AARCH64_FIQ - ldr x1, ASM_PFX(CommonExceptionEntry) - br x1 - -ASM_PFX(SErrorEntry): - sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE) - ALL_GP_REGS - mov x0, #EXCEPT_AARCH64_SERROR - ldr x1, ASM_PFX(CommonExceptionEntry) - br x1 - - -// -// This gets patched by the C code that patches in the vector table -// -.align 3 -ASM_PFX(CommonExceptionEntry): - .8byte ASM_PFX(AsmCommonExceptionEntry) - -ASM_PFX(ExceptionHandlersEnd): - - - -// -// This code runs from CpuDxe driver loaded address. It is patched into -// CommonExceptionEntry. -// -ASM_PFX(AsmCommonExceptionEntry): - /* NOTE: - We have to break up the save code because the immediate value to be used - with the SP is too big to do it all in one step so we need to shuffle the SP - along as we go. (we only have 9bits of immediate to work with) */ - - // Save the current Stack pointer before we start modifying it. - SAVE_SP - - // Preserve the stack pointer we came in with before we modify it - EL1_OR_EL2(x1) -1:mrs x1, elr_el1 // Exception Link Register - mrs x2, spsr_el1 // Saved Processor Status Register 32bit - mrs x3, fpsr // Floating point Status Register 32bit - mrs x4, esr_el1 // EL1 Exception syndrome register 32bit - mrs x5, far_el1 // EL1 Fault Address Register - b 3f - -2:mrs x1, elr_el2 // Exception Link Register - mrs x2, spsr_el2 // Saved Processor Status Register 32bit - mrs x3, fpsr // Floating point Status Register 32bit - mrs x4, esr_el2 // EL2 Exception syndrome register 32bit - mrs x5, far_el2 // EL2 Fault Address Register - - // Adjust SP to save next set -3:add sp, sp, #FP_CONTEXT_SIZE - - // Push FP regs to Stack. - ALL_FP_REGS - - // Adjust SP to save next set - add sp, sp, #SYS_CONTEXT_SIZE - - // Save the SYS regs - ALL_SYS_REGS - - // Point to top of struct after all regs saved - sub sp, sp, #(GP_CONTEXT_SIZE + FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE) - - // x0 still holds the exception type. - // Set x1 to point to the top of our struct on the Stack - mov x1, sp - -// CommonCExceptionHandler ( -// IN EFI_EXCEPTION_TYPE ExceptionType, R0 -// IN OUT EFI_SYSTEM_CONTEXT SystemContext R1 -// ) - - // Call the handler as defined above - - // For now we spin in the handler if we received an abort of some kind. - // We do not try to recover. - bl ASM_PFX(CommonCExceptionHandler) // Call exception handler - - -// Defines for popping from stack - -#undef REG_PAIR -#undef REG_ONE -#define REG_PAIR(REG1, REG2, OFFSET, CONTEXT_SIZE) ldp REG1, REG2, [sp, #(OFFSET-CONTEXT_SIZE)] -#define REG_ONE(REG1, OFFSET, CONTEXT_SIZE) ldur REG1, [sp, #(OFFSET-CONTEXT_SIZE)] - - // Adjust SP to pop system registers - add sp, sp, #(GP_CONTEXT_SIZE + FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE) - ALL_SYS_REGS - - EL1_OR_EL2(x6) -1:msr elr_el1, x1 // Exception Link Register - msr spsr_el1,x2 // Saved Processor Status Register 32bit - msr fpsr, x3 // Floating point Status Register 32bit - msr esr_el1, x4 // EL1 Exception syndrome register 32bit - msr far_el1, x5 // EL1 Fault Address Register - b 3f -2:msr elr_el2, x1 // Exception Link Register - msr spsr_el2,x2 // Saved Processor Status Register 32bit - msr fpsr, x3 // Floating point Status Register 32bit - msr esr_el2, x4 // EL2 Exception syndrome register 32bit - msr far_el2, x5 // EL2 Fault Address Register - -3:// pop all regs and return from exception. - sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE) - ALL_GP_REGS - - // Adjust SP to pop next set - add sp, sp, #FP_CONTEXT_SIZE - // Pop FP regs to Stack. - ALL_FP_REGS - - // Adjust SP to be where we started from when we came into the handler. - // The handler can not change the SP. - add sp, sp, #SYS_CONTEXT_SIZE - - eret - -#undef REG_PAIR -#undef REG_ONE diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c deleted file mode 100644 index d8bb419780..0000000000 --- a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c +++ /dev/null @@ -1,344 +0,0 @@ -/*++ - -Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.
-Portions copyright (c) 2010, Apple Inc. All rights reserved.
-Portions copyright (c) 2011-2013, ARM Ltd. All rights reserved.
- -This program and the accompanying materials -are licensed and made available under the terms and conditions of the BSD License -which accompanies this distribution. The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - - ---*/ - -#include -#include "CpuDxe.h" - -#define TT_ATTR_INDX_INVALID ((UINT32)~0) - -STATIC -UINT64 -GetFirstPageAttribute ( - IN UINT64 *FirstLevelTableAddress, - IN UINTN TableLevel - ) -{ - UINT64 FirstEntry; - - // Get the first entry of the table - FirstEntry = *FirstLevelTableAddress; - - if ((TableLevel != 3) && (FirstEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY) { - // Only valid for Levels 0, 1 and 2 - - // Get the attribute of the subsequent table - return GetFirstPageAttribute ((UINT64*)(FirstEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE), TableLevel + 1); - } else if (((FirstEntry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY) || - ((TableLevel == 3) && ((FirstEntry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY_LEVEL3))) - { - return FirstEntry & TT_ATTR_INDX_MASK; - } else { - return TT_ATTR_INDX_INVALID; - } -} - -STATIC -UINT64 -GetNextEntryAttribute ( - IN UINT64 *TableAddress, - IN UINTN EntryCount, - IN UINTN TableLevel, - IN UINT64 BaseAddress, - IN OUT UINT32 *PrevEntryAttribute, - IN OUT UINT64 *StartGcdRegion - ) -{ - UINTN Index; - UINT64 Entry; - UINT32 EntryAttribute; - UINT32 EntryType; - EFI_STATUS Status; - UINTN NumberOfDescriptors; - EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap; - - // Get the memory space map from GCD - MemorySpaceMap = NULL; - Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap); - ASSERT_EFI_ERROR (Status); - - // We cannot get more than 3-level page table - ASSERT (TableLevel <= 3); - - // While the top level table might not contain TT_ENTRY_COUNT entries; - // the subsequent ones should be filled up - for (Index = 0; Index < EntryCount; Index++) { - Entry = TableAddress[Index]; - EntryType = Entry & TT_TYPE_MASK; - EntryAttribute = Entry & TT_ATTR_INDX_MASK; - - // If Entry is a Table Descriptor type entry then go through the sub-level table - if ((EntryType == TT_TYPE_BLOCK_ENTRY) || - ((TableLevel == 3) && (EntryType == TT_TYPE_BLOCK_ENTRY_LEVEL3))) { - if ((*PrevEntryAttribute == TT_ATTR_INDX_INVALID) || (EntryAttribute != *PrevEntryAttribute)) { - if (*PrevEntryAttribute != TT_ATTR_INDX_INVALID) { - // Update GCD with the last region - SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, - *StartGcdRegion, - (BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel))) - *StartGcdRegion, - PageAttributeToGcdAttribute (*PrevEntryAttribute)); - } - - // Start of the new region - *StartGcdRegion = BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel)); - *PrevEntryAttribute = EntryAttribute; - } else { - continue; - } - } else if (EntryType == TT_TYPE_TABLE_ENTRY) { - // Table Entry type is only valid for Level 0, 1, 2 - ASSERT (TableLevel < 3); - - // Increase the level number and scan the sub-level table - GetNextEntryAttribute ((UINT64*)(Entry & TT_ADDRESS_MASK_DESCRIPTION_TABLE), - TT_ENTRY_COUNT, TableLevel + 1, - (BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel))), - PrevEntryAttribute, StartGcdRegion); - } else { - if (*PrevEntryAttribute != TT_ATTR_INDX_INVALID) { - // Update GCD with the last region - SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, - *StartGcdRegion, - (BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel))) - *StartGcdRegion, - PageAttributeToGcdAttribute (*PrevEntryAttribute)); - - // Start of the new region - *StartGcdRegion = BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel)); - *PrevEntryAttribute = TT_ATTR_INDX_INVALID; - } - } - } - - FreePool (MemorySpaceMap); - - return BaseAddress + (EntryCount * TT_ADDRESS_AT_LEVEL(TableLevel)); -} - -EFI_STATUS -SyncCacheConfig ( - IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol - ) -{ - EFI_STATUS Status; - UINT32 PageAttribute = 0; - UINT64 *FirstLevelTableAddress; - UINTN TableLevel; - UINTN TableCount; - UINTN NumberOfDescriptors; - EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap; - UINTN Tcr; - UINTN T0SZ; - UINT64 BaseAddressGcdRegion; - UINT64 EndAddressGcdRegion; - - // This code assumes MMU is enabled and filed with section translations - ASSERT (ArmMmuEnabled ()); - - // - // Get the memory space map from GCD - // - MemorySpaceMap = NULL; - Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap); - ASSERT_EFI_ERROR (Status); - - // The GCD implementation maintains its own copy of the state of memory space attributes. GCD needs - // to know what the initial memory space attributes are. The CPU Arch. Protocol does not provide a - // GetMemoryAttributes function for GCD to get this so we must resort to calling GCD (as if we were - // a client) to update its copy of the attributes. This is bad architecture and should be replaced - // with a way for GCD to query the CPU Arch. driver of the existing memory space attributes instead. - - // Obtain page table base - FirstLevelTableAddress = (UINT64*)(ArmGetTTBR0BaseAddress ()); - - // Get Translation Control Register value - Tcr = ArmGetTCR (); - // Get Address Region Size - T0SZ = Tcr & TCR_T0SZ_MASK; - - // Get the level of the first table for the indicated Address Region Size - GetRootTranslationTableInfo (T0SZ, &TableLevel, &TableCount); - - // First Attribute of the Page Tables - PageAttribute = GetFirstPageAttribute (FirstLevelTableAddress, TableLevel); - - // We scan from the start of the memory map (ie: at the address 0x0) - BaseAddressGcdRegion = 0x0; - EndAddressGcdRegion = GetNextEntryAttribute (FirstLevelTableAddress, - TableCount, TableLevel, - BaseAddressGcdRegion, - &PageAttribute, &BaseAddressGcdRegion); - - // Update GCD with the last region if valid - if (PageAttribute != TT_ATTR_INDX_INVALID) { - SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, - BaseAddressGcdRegion, - EndAddressGcdRegion - BaseAddressGcdRegion, - PageAttributeToGcdAttribute (PageAttribute)); - } - - FreePool (MemorySpaceMap); - - return EFI_SUCCESS; -} - -UINT64 -EfiAttributeToArmAttribute ( - IN UINT64 EfiAttributes - ) -{ - UINT64 ArmAttributes; - - switch (EfiAttributes & EFI_MEMORY_CACHETYPE_MASK) { - case EFI_MEMORY_UC: - ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY; - break; - case EFI_MEMORY_WC: - ArmAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE; - break; - case EFI_MEMORY_WT: - ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH; - break; - case EFI_MEMORY_WB: - ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK; - break; - default: - DEBUG ((EFI_D_ERROR, "EfiAttributeToArmAttribute: 0x%lX attributes is not supported.\n", EfiAttributes)); - ASSERT (0); - ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY; - } - - // Set the access flag to match the block attributes - ArmAttributes |= TT_AF; - - // Determine protection attributes - if (EfiAttributes & EFI_MEMORY_WP) { - ArmAttributes |= TT_AP_RO_RO; - } - - // Process eXecute Never attribute - if (EfiAttributes & EFI_MEMORY_XP) { - ArmAttributes |= TT_PXN_MASK; - } - - return ArmAttributes; -} - -// This function will recursively go down the page table to find the first block address linked to 'BaseAddress'. -// And then the function will identify the size of the region that has the same page table attribute. -EFI_STATUS -GetMemoryRegionRec ( - IN UINT64 *TranslationTable, - IN UINTN TableLevel, - IN UINT64 *LastBlockEntry, - IN OUT UINTN *BaseAddress, - OUT UINTN *RegionLength, - OUT UINTN *RegionAttributes - ) -{ - EFI_STATUS Status; - UINT64 *NextTranslationTable; - UINT64 *BlockEntry; - UINT64 BlockEntryType; - UINT64 EntryType; - - if (TableLevel != 3) { - BlockEntryType = TT_TYPE_BLOCK_ENTRY; - } else { - BlockEntryType = TT_TYPE_BLOCK_ENTRY_LEVEL3; - } - - // Find the block entry linked to the Base Address - BlockEntry = (UINT64*)TT_GET_ENTRY_FOR_ADDRESS (TranslationTable, TableLevel, *BaseAddress); - EntryType = *BlockEntry & TT_TYPE_MASK; - - if ((TableLevel < 3) && (EntryType == TT_TYPE_TABLE_ENTRY)) { - NextTranslationTable = (UINT64*)(*BlockEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE); - - // The entry is a page table, so we go to the next level - Status = GetMemoryRegionRec ( - NextTranslationTable, // Address of the next level page table - TableLevel + 1, // Next Page Table level - (UINTN*)TT_LAST_BLOCK_ADDRESS(NextTranslationTable, TT_ENTRY_COUNT), - BaseAddress, RegionLength, RegionAttributes); - - // In case of 'Success', it means the end of the block region has been found into the upper - // level translation table - if (!EFI_ERROR(Status)) { - return EFI_SUCCESS; - } - - // Now we processed the table move to the next entry - BlockEntry++; - } else if (EntryType == BlockEntryType) { - // We have found the BlockEntry attached to the address. We save its start address (the start - // address might be before the 'BaseAdress') and attributes - *BaseAddress = *BaseAddress & ~(TT_ADDRESS_AT_LEVEL(TableLevel) - 1); - *RegionLength = 0; - *RegionAttributes = *BlockEntry & TT_ATTRIBUTES_MASK; - } else { - // We have an 'Invalid' entry - return EFI_UNSUPPORTED; - } - - while (BlockEntry <= LastBlockEntry) { - if ((*BlockEntry & TT_ATTRIBUTES_MASK) == *RegionAttributes) { - *RegionLength = *RegionLength + TT_BLOCK_ENTRY_SIZE_AT_LEVEL(TableLevel); - } else { - // In case we have found the end of the region we return success - return EFI_SUCCESS; - } - BlockEntry++; - } - - // If we have reached the end of the TranslationTable and we have not found the end of the region then - // we return EFI_NOT_FOUND. - // The caller will continue to look for the memory region at its level - return EFI_NOT_FOUND; -} - -EFI_STATUS -GetMemoryRegion ( - IN OUT UINTN *BaseAddress, - OUT UINTN *RegionLength, - OUT UINTN *RegionAttributes - ) -{ - EFI_STATUS Status; - UINT64 *TranslationTable; - UINTN TableLevel; - UINTN EntryCount; - UINTN T0SZ; - - ASSERT ((BaseAddress != NULL) && (RegionLength != NULL) && (RegionAttributes != NULL)); - - TranslationTable = ArmGetTTBR0BaseAddress (); - - T0SZ = ArmGetTCR () & TCR_T0SZ_MASK; - // Get the Table info from T0SZ - GetRootTranslationTableInfo (T0SZ, &TableLevel, &EntryCount); - - Status = GetMemoryRegionRec (TranslationTable, TableLevel, - (UINTN*)TT_LAST_BLOCK_ADDRESS(TranslationTable, EntryCount), - BaseAddress, RegionLength, RegionAttributes); - - // If the region continues up to the end of the root table then GetMemoryRegionRec() - // will return EFI_NOT_FOUND - if (Status == EFI_NOT_FOUND) { - return EFI_SUCCESS; - } else { - return Status; - } -} diff --git a/ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.S b/ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.S deleted file mode 100644 index c82618aa1b..0000000000 --- a/ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.S +++ /dev/null @@ -1,191 +0,0 @@ -#------------------------------------------------------------------------------ -# -# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
-# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -#------------------------------------------------------------------------------ - -.text -.align 3 - -GCC_ASM_EXPORT(ExceptionHandlersStart) -GCC_ASM_EXPORT(ExceptionHandlersEnd) -GCC_ASM_EXPORT(CommonExceptionEntry) -GCC_ASM_EXPORT(AsmCommonExceptionEntry) -GCC_ASM_EXPORT(CommonCExceptionHandler) - -ASM_PFX(ExceptionHandlersStart): - -ASM_PFX(Reset): - b ASM_PFX(ResetEntry) - -ASM_PFX(UndefinedInstruction): - b ASM_PFX(UndefinedInstructionEntry) - -ASM_PFX(SoftwareInterrupt): - b ASM_PFX(SoftwareInterruptEntry) - -ASM_PFX(PrefetchAbort): - b ASM_PFX(PrefetchAbortEntry) - -ASM_PFX(DataAbort): - b ASM_PFX(DataAbortEntry) - -ASM_PFX(ReservedException): - b ASM_PFX(ReservedExceptionEntry) - -ASM_PFX(Irq): - b ASM_PFX(IrqEntry) - -ASM_PFX(Fiq): - b ASM_PFX(FiqEntry) - -ASM_PFX(ResetEntry): - srsdb #0x13! @ Store return state on SVC stack - stmfd SP!,{LR} @ Store the link register for the current mode - sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR - stmfd SP!,{R0-R12} @ Store the register state - - mov R0,#0 - ldr R1,ASM_PFX(CommonExceptionEntry) - bx R1 - -ASM_PFX(UndefinedInstructionEntry): - srsdb #0x13! @ Store return state on SVC stack - cps #0x13 @ Switch to SVC for common stack - stmfd SP!,{LR} @ Store the link register for the current mode - sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR - stmfd SP!,{R0-R12} @ Store the register state - - mov r0,#1 - ldr r1,ASM_PFX(CommonExceptionEntry) - bx r1 - -ASM_PFX(SoftwareInterruptEntry): - srsdb #0x13! @ Store return state on SVC stack - stmfd SP!,{LR} @ Store the link register for the current mode - sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR - stmfd SP!,{R0-R12} @ Store the register state - - mov r0,#2 - ldr r1,ASM_PFX(CommonExceptionEntry) - bx r1 - -ASM_PFX(PrefetchAbortEntry): - sub LR,LR,#4 - srsdb #0x13! @ Store return state on SVC stack - cps #0x13 @ Switch to SVC for common stack - stmfd SP!,{LR} @ Store the link register for the current mode - sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR - stmfd SP!,{R0-R12} @ Store the register state - - mov r0,#3 - ldr r1,ASM_PFX(CommonExceptionEntry) - bx r1 - -ASM_PFX(DataAbortEntry): - sub LR,LR,#8 - srsdb #0x13! @ Store return state on SVC stack - cps #0x13 @ Switch to SVC for common stack - stmfd SP!,{LR} @ Store the link register for the current mode - sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR - stmfd SP!,{R0-R12} @ Store the register state - - mov r0,#4 - ldr r1,ASM_PFX(CommonExceptionEntry) - bx r1 - -ASM_PFX(ReservedExceptionEntry): - srsdb #0x13! @ Store return state on SVC stack - cps #0x13 @ Switch to SVC for common stack - stmfd SP!,{LR} @ Store the link register for the current mode - sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR - stmfd SP!,{R0-R12} @ Store the register state - - mov r0,#5 - ldr r1,ASM_PFX(CommonExceptionEntry) - bx r1 - -ASM_PFX(IrqEntry): - sub LR,LR,#4 - srsdb #0x13! @ Store return state on SVC stack - cps #0x13 @ Switch to SVC for common stack - stmfd SP!,{LR} @ Store the link register for the current mode - sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR - stmfd SP!,{R0-R12} @ Store the register state - - mov r0,#6 - ldr r1,ASM_PFX(CommonExceptionEntry) - bx r1 - -ASM_PFX(FiqEntry): - sub LR,LR,#4 - srsdb #0x13! @ Store return state on SVC stack - cps #0x13 @ Switch to SVC for common stack - stmfd SP!,{LR} @ Store the link register for the current mode - sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR - stmfd SP!,{R0-R12} @ Store the register state - - mov r0,#7 - ldr r1,ASM_PFX(CommonExceptionEntry) - bx r1 - -ASM_PFX(CommonExceptionEntry): - .byte 0x12 - .byte 0x34 - .byte 0x56 - .byte 0x78 - -ASM_PFX(ExceptionHandlersEnd): - -ASM_PFX(AsmCommonExceptionEntry): - mrc p15, 0, R1, c6, c0, 2 @ Read IFAR - str R1, [SP, #0x50] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR - - mrc p15, 0, R1, c5, c0, 1 @ Read IFSR - str R1, [SP, #0x4c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR - - mrc p15, 0, R1, c6, c0, 0 @ Read DFAR - str R1, [SP, #0x48] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR - - mrc p15, 0, R1, c5, c0, 0 @ Read DFSR - str R1, [SP, #0x44] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR - - ldr R1, [SP, #0x5c] @ srsdb saved pre-exception CPSR on the stack - str R1, [SP, #0x40] @ Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR - and r1, r1, #0x1f @ Check to see if User or System Mode - cmp r1, #0x1f - cmpne r1, #0x10 - add R2, SP, #0x38 @ Store it in EFI_SYSTEM_CONTEXT_ARM.LR - ldmneed r2, {lr}^ @ User or System mode, use unbanked register - ldmneed r2, {lr} @ All other modes used banked register - - ldr R1, [SP, #0x58] @ PC is the LR pushed by srsdb - str R1, [SP, #0x3c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.PC - - sub R1, SP, #0x60 @ We pused 0x60 bytes on the stack - str R1, [SP, #0x34] @ Store it in EFI_SYSTEM_CONTEXT_ARM.SP - - @ R0 is exception type - mov R1,SP @ Prepare System Context pointer as an argument for the exception handler - blx ASM_PFX(CommonCExceptionHandler) @ Call exception handler - - ldr R2,[SP,#0x40] @ EFI_SYSTEM_CONTEXT_ARM.CPSR - str R2,[SP,#0x5c] @ Store it back to srsdb stack slot so it can be restored - - ldr R2,[SP,#0x3c] @ EFI_SYSTEM_CONTEXT_ARM.PC - str R2,[SP,#0x58] @ Store it back to srsdb stack slot so it can be restored - - ldmfd SP!,{R0-R12} @ Restore general purpose registers - @ Exception handler can not change SP or LR as we would blow chunks - - add SP,SP,#0x20 @ Clear out the remaining stack space - ldmfd SP!,{LR} @ restore the link register for this context - rfefd SP! @ return from exception via srsdb stack slot diff --git a/ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.asm b/ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.asm deleted file mode 100644 index 9f09a0bc76..0000000000 --- a/ArmPkg/Drivers/CpuDxe/ArmV4/ExceptionSupport.asm +++ /dev/null @@ -1,152 +0,0 @@ -//------------------------------------------------------------------------------ -// -// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
-// -// This program and the accompanying materials -// are licensed and made available under the terms and conditions of the BSD License -// which accompanies this distribution. The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -// -//------------------------------------------------------------------------------ - - EXPORT ExceptionHandlersStart - EXPORT ExceptionHandlersEnd - EXPORT CommonExceptionEntry - EXPORT AsmCommonExceptionEntry - IMPORT CommonCExceptionHandler - - PRESERVE8 - AREA DxeExceptionHandlers, CODE, READONLY - -ExceptionHandlersStart - -Reset - b ResetEntry - -UndefinedInstruction - b UndefinedInstructionEntry - -SoftwareInterrupt - b SoftwareInterruptEntry - -PrefetchAbort - b PrefetchAbortEntry - -DataAbort - b DataAbortEntry - -ReservedException - b ReservedExceptionEntry - -Irq - b IrqEntry - -Fiq - b FiqEntry - -ResetEntry - stmfd SP!,{R0-R1} - mov R0,#0 - ldr R1,CommonExceptionEntry - bx R1 - -UndefinedInstructionEntry - stmfd SP!,{R0-R1} - mov R0,#1 - ldr R1,CommonExceptionEntry - bx R1 - -SoftwareInterruptEntry - stmfd SP!,{R0-R1} - mov R0,#2 - ldr R1,CommonExceptionEntry - bx R1 - -PrefetchAbortEntry - stmfd SP!,{R0-R1} - mov R0,#3 - SUB LR,LR,#4 - ldr R1,CommonExceptionEntry - bx R1 - -DataAbortEntry - stmfd SP!,{R0-R1} - mov R0,#4 - SUB LR,LR,#8 - ldr R1,CommonExceptionEntry - bx R1 - -ReservedExceptionEntry - stmfd SP!,{R0-R1} - mov R0,#5 - ldr R1,CommonExceptionEntry - bx R1 - -IrqEntry - stmfd SP!,{R0-R1} - mov R0,#6 - SUB LR,LR,#4 - ldr R1,CommonExceptionEntry - bx R1 - -FiqEntry - stmfd SP!,{R0-R1} - mov R0,#7 - SUB LR,LR,#4 - ldr R1,CommonExceptionEntry - bx R1 - -CommonExceptionEntry - dcd 0x12345678 - -ExceptionHandlersEnd - -AsmCommonExceptionEntry - mrc p15, 0, r1, c6, c0, 2 ; Read IFAR - stmfd SP!,{R1} ; Store the IFAR - - mrc p15, 0, r1, c5, c0, 1 ; Read IFSR - stmfd SP!,{R1} ; Store the IFSR - - mrc p15, 0, r1, c6, c0, 0 ; Read DFAR - stmfd SP!,{R1} ; Store the DFAR - - mrc p15, 0, r1, c5, c0, 0 ; Read DFSR - stmfd SP!,{R1} ; Store the DFSR - - mrs R1,SPSR ; Read SPSR (which is the pre-exception CPSR) - stmfd SP!,{R1} ; Store the SPSR - - stmfd SP!,{LR} ; Store the link register (which is the pre-exception PC) - stmfd SP,{SP,LR}^ ; Store user/system mode stack pointer and link register - nop ; Required by ARM architecture - SUB SP,SP,#0x08 ; Adjust stack pointer - stmfd SP!,{R2-R12} ; Store general purpose registers - - ldr R3,[SP,#0x50] ; Read saved R1 from the stack (it was saved by the exception entry routine) - ldr R2,[SP,#0x4C] ; Read saved R0 from the stack (it was saved by the exception entry routine) - stmfd SP!,{R2-R3} ; Store general purpose registers R0 and R1 - - mov R1,SP ; Prepare System Context pointer as an argument for the exception handler - - sub SP,SP,#4 ; Adjust SP to preserve 8-byte alignment - blx CommonCExceptionHandler ; Call exception handler - add SP,SP,#4 ; Adjust SP back to where we were - - ldr R2,[SP,#0x40] ; Load CPSR from context, in case it has changed - MSR SPSR_cxsf,R2 ; Store it back to the SPSR to be restored when exiting this handler - - ldmfd SP!,{R0-R12} ; Restore general purpose registers - ldm SP,{SP,LR}^ ; Restore user/system mode stack pointer and link register - nop ; Required by ARM architecture - add SP,SP,#0x08 ; Adjust stack pointer - ldmfd SP!,{LR} ; Restore the link register (which is the pre-exception PC) - add SP,SP,#0x1C ; Clear out the remaining stack space - movs PC,LR ; Return from exception - - END - - diff --git a/ArmPkg/Drivers/CpuDxe/ArmV6/Exception.c b/ArmPkg/Drivers/CpuDxe/ArmV6/Exception.c deleted file mode 100644 index 4b05199db3..0000000000 --- a/ArmPkg/Drivers/CpuDxe/ArmV6/Exception.c +++ /dev/null @@ -1,234 +0,0 @@ -/** @file - - Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
- Copyright (c) 2014, ARM Limited. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include "CpuDxe.h" - -//FIXME: Will not compile on non-ARMv7 builds -#include - -VOID -ExceptionHandlersStart ( - VOID - ); - -VOID -ExceptionHandlersEnd ( - VOID - ); - -VOID -CommonExceptionEntry ( - VOID - ); - -VOID -AsmCommonExceptionEntry ( - VOID - ); - - -EFI_EXCEPTION_CALLBACK gExceptionHandlers[MAX_ARM_EXCEPTION + 1]; -EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[MAX_ARM_EXCEPTION + 1]; - - - -/** - This function registers and enables the handler specified by InterruptHandler for a processor - interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the - handler for the processor interrupt or exception type specified by InterruptType is uninstalled. - The installed handler is called once for each processor interrupt or exception. - - @param InterruptType A pointer to the processor's current interrupt state. Set to TRUE if interrupts - are enabled and FALSE if interrupts are disabled. - @param InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called - when a processor interrupt occurs. If this parameter is NULL, then the handler - will be uninstalled. - - @retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled. - @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was - previously installed. - @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not - previously installed. - @retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported. - -**/ -EFI_STATUS -RegisterInterruptHandler ( - IN EFI_EXCEPTION_TYPE InterruptType, - IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler - ) -{ - if (InterruptType > MAX_ARM_EXCEPTION) { - return EFI_UNSUPPORTED; - } - - if ((InterruptHandler != NULL) && (gExceptionHandlers[InterruptType] != NULL)) { - return EFI_ALREADY_STARTED; - } - - gExceptionHandlers[InterruptType] = InterruptHandler; - - return EFI_SUCCESS; -} - - - - -VOID -EFIAPI -CommonCExceptionHandler ( - IN EFI_EXCEPTION_TYPE ExceptionType, - IN OUT EFI_SYSTEM_CONTEXT SystemContext - ) -{ - if (ExceptionType <= MAX_ARM_EXCEPTION) { - if (gExceptionHandlers[ExceptionType]) { - gExceptionHandlers[ExceptionType] (ExceptionType, SystemContext); - return; - } - } else { - DEBUG ((EFI_D_ERROR, "Unknown exception type %d from %08x\n", ExceptionType, SystemContext.SystemContextArm->PC)); - ASSERT (FALSE); - } - - if (ExceptionType == EXCEPT_ARM_SOFTWARE_INTERRUPT) { - // - // ARM JTAG debuggers some times use this vector, so it is not an error to get one - // - return; - } - - DefaultExceptionHandler (ExceptionType, SystemContext); -} - - - -EFI_STATUS -InitializeExceptions ( - IN EFI_CPU_ARCH_PROTOCOL *Cpu - ) -{ - EFI_STATUS Status; - UINTN Offset; - UINTN Length; - UINTN Index; - BOOLEAN IrqEnabled; - BOOLEAN FiqEnabled; - EFI_PHYSICAL_ADDRESS Base; - UINT32 *VectorBase; - - Status = EFI_SUCCESS; - ZeroMem (gExceptionHandlers,sizeof(*gExceptionHandlers)); - - // - // Disable interrupts - // - Cpu->GetInterruptState (Cpu, &IrqEnabled); - Cpu->DisableInterrupt (Cpu); - - // - // EFI does not use the FIQ, but a debugger might so we must disable - // as we take over the exception vectors. - // - FiqEnabled = ArmGetFiqState (); - ArmDisableFiq (); - - if (FeaturePcdGet(PcdRelocateVectorTable) == TRUE) { - // - // Copy an implementation of the ARM exception vectors to PcdCpuVectorBaseAddress. - // - Length = (UINTN)ExceptionHandlersEnd - (UINTN)ExceptionHandlersStart; - - // Check if the exception vector is in the low address - if (PcdGet32 (PcdCpuVectorBaseAddress) == 0x0) { - // Set SCTLR.V to 0 to enable VBAR to be used - ArmSetLowVectors (); - } else { - ArmSetHighVectors (); - } - - // - // Reserve space for the exception handlers - // - Base = (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdCpuVectorBaseAddress); - VectorBase = (UINT32 *)(UINTN)Base; - Status = gBS->AllocatePages (AllocateAddress, EfiBootServicesCode, EFI_SIZE_TO_PAGES (Length), &Base); - // If the request was for memory that's not in the memory map (which is often the case for 0x00000000 - // on embedded systems, for example, we don't want to hang up. So we'll check here for a status of - // EFI_NOT_FOUND, and continue in that case. - if (EFI_ERROR(Status) && (Status != EFI_NOT_FOUND)) { - ASSERT_EFI_ERROR (Status); - } - - if (FeaturePcdGet(PcdDebuggerExceptionSupport) == TRUE) { - // Save existing vector table, in case debugger is already hooked in - CopyMem ((VOID *)gDebuggerExceptionHandlers, (VOID *)VectorBase, sizeof (gDebuggerExceptionHandlers)); - } - - // Copy our assembly code into the page that contains the exception vectors. - CopyMem ((VOID *)VectorBase, (VOID *)ExceptionHandlersStart, Length); - - // - // Patch in the common Assembly exception handler - // - Offset = (UINTN)CommonExceptionEntry - (UINTN)ExceptionHandlersStart; - *(UINTN *) ((UINT8 *)(UINTN)PcdGet32 (PcdCpuVectorBaseAddress) + Offset) = (UINTN)AsmCommonExceptionEntry; - - // - // Initialize the C entry points for interrupts - // - for (Index = 0; Index <= MAX_ARM_EXCEPTION; Index++) { - if (!FeaturePcdGet(PcdDebuggerExceptionSupport) || - (gDebuggerExceptionHandlers[Index] == 0) || (gDebuggerExceptionHandlers[Index] == (VOID *)(UINTN)0xEAFFFFFE)) { - // Exception handler contains branch to vector location (jmp $) so no handler - // NOTE: This code assumes vectors are ARM and not Thumb code - Status = RegisterInterruptHandler (Index, NULL); - ASSERT_EFI_ERROR (Status); - } else { - // If the debugger has already hooked put its vector back - VectorBase[Index] = (UINT32)(UINTN)gDebuggerExceptionHandlers[Index]; - } - } - - // Flush Caches since we updated executable stuff - InvalidateInstructionCacheRange ((VOID *)PcdGet32(PcdCpuVectorBaseAddress), Length); - - //Note: On ARM processor with the Security Extension, the Vector Table can be located anywhere in the memory. - // The Vector Base Address Register defines the location - ArmWriteVBar (PcdGet32(PcdCpuVectorBaseAddress)); - } else { - // The Vector table must be 32-byte aligned - if (((UINT32)ExceptionHandlersStart & ARM_VECTOR_TABLE_ALIGNMENT) != 0) { - ASSERT (0); - return EFI_INVALID_PARAMETER; - } - - // We do not copy the Exception Table at PcdGet32(PcdCpuVectorBaseAddress). We just set Vector Base Address to point into CpuDxe code. - ArmWriteVBar ((UINT32)ExceptionHandlersStart); - } - - if (FiqEnabled) { - ArmEnableFiq (); - } - - if (IrqEnabled) { - // - // Restore interrupt state - // - Status = Cpu->EnableInterrupt (Cpu); - } - - return Status; -} diff --git a/ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.S b/ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.S deleted file mode 100644 index 3433b99cd4..0000000000 --- a/ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.S +++ /dev/null @@ -1,303 +0,0 @@ -#------------------------------------------------------------------------------ -# -# Use ARMv6 instruction to operate on a single stack -# -# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
-# Copyright (c) 2014, ARM Limited. All rights reserved.
-# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -#------------------------------------------------------------------------------ - -#include - -/* - -This is the stack constructed by the exception handler (low address to high address) - # R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM - Reg Offset - === ====== - R0 0x00 # stmfd SP!,{R0-R12} - R1 0x04 - R2 0x08 - R3 0x0c - R4 0x10 - R5 0x14 - R6 0x18 - R7 0x1c - R8 0x20 - R9 0x24 - R10 0x28 - R11 0x2c - R12 0x30 - SP 0x34 # reserved via subtraction 0x20 (32) from SP - LR 0x38 - PC 0x3c - CPSR 0x40 - DFSR 0x44 - DFAR 0x48 - IFSR 0x4c - IFAR 0x50 - - LR 0x54 # SVC Link register (we need to restore it) - - LR 0x58 # pushed by srsfd - CPSR 0x5c - - */ - - -GCC_ASM_EXPORT(ExceptionHandlersStart) -GCC_ASM_EXPORT(ExceptionHandlersEnd) -GCC_ASM_EXPORT(CommonExceptionEntry) -GCC_ASM_EXPORT(AsmCommonExceptionEntry) -GCC_ASM_EXPORT(CommonCExceptionHandler) - -.text -#if !defined(__APPLE__) -.fpu neon @ makes vpush/vpop assemble -#endif -.align 5 - - -// -// This code gets copied to the ARM vector table -// ExceptionHandlersStart - ExceptionHandlersEnd gets copied -// -ASM_PFX(ExceptionHandlersStart): - -ASM_PFX(Reset): - b ASM_PFX(ResetEntry) - -ASM_PFX(UndefinedInstruction): - b ASM_PFX(UndefinedInstructionEntry) - -ASM_PFX(SoftwareInterrupt): - b ASM_PFX(SoftwareInterruptEntry) - -ASM_PFX(PrefetchAbort): - b ASM_PFX(PrefetchAbortEntry) - -ASM_PFX(DataAbort): - b ASM_PFX(DataAbortEntry) - -ASM_PFX(ReservedException): - b ASM_PFX(ReservedExceptionEntry) - -ASM_PFX(Irq): - b ASM_PFX(IrqEntry) - -ASM_PFX(Fiq): - b ASM_PFX(FiqEntry) - -ASM_PFX(ResetEntry): - srsdb #0x13! @ Store return state on SVC stack - @ We are already in SVC mode - - stmfd SP!,{LR} @ Store the link register for the current mode - sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR - stmfd SP!,{R0-R12} @ Store the register state - - mov R0,#0 @ ExceptionType - ldr R1,ASM_PFX(CommonExceptionEntry) - bx R1 - -ASM_PFX(UndefinedInstructionEntry): - sub LR, LR, #4 @ Only -2 for Thumb, adjust in CommonExceptionEntry - srsdb #0x13! @ Store return state on SVC stack - cps #0x13 @ Switch to SVC for common stack - stmfd SP!,{LR} @ Store the link register for the current mode - sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR - stmfd SP!,{R0-R12} @ Store the register state - - mov R0,#1 @ ExceptionType - ldr R1,ASM_PFX(CommonExceptionEntry) - bx R1 - -ASM_PFX(SoftwareInterruptEntry): - srsdb #0x13! @ Store return state on SVC stack - @ We are already in SVC mode - stmfd SP!,{LR} @ Store the link register for the current mode - sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR - stmfd SP!,{R0-R12} @ Store the register state - - mov R0,#2 @ ExceptionType - ldr R1,ASM_PFX(CommonExceptionEntry) - bx R1 - -ASM_PFX(PrefetchAbortEntry): - sub LR,LR,#4 - srsdb #0x13! @ Store return state on SVC stack - cps #0x13 @ Switch to SVC for common stack - stmfd SP!,{LR} @ Store the link register for the current mode - sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR - stmfd SP!,{R0-R12} @ Store the register state - - mov R0,#3 @ ExceptionType - ldr R1,ASM_PFX(CommonExceptionEntry) - bx R1 - -ASM_PFX(DataAbortEntry): - sub LR,LR,#8 - srsdb #0x13! @ Store return state on SVC stack - cps #0x13 @ Switch to SVC for common stack - stmfd SP!,{LR} @ Store the link register for the current mode - sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR - stmfd SP!,{R0-R12} @ Store the register state - - mov R0,#4 - ldr R1,ASM_PFX(CommonExceptionEntry) - bx R1 - -ASM_PFX(ReservedExceptionEntry): - srsdb #0x13! @ Store return state on SVC stack - cps #0x13 @ Switch to SVC for common stack - stmfd SP!,{LR} @ Store the link register for the current mode - sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR - stmfd SP!,{R0-R12} @ Store the register state - - mov R0,#5 - ldr R1,ASM_PFX(CommonExceptionEntry) - bx R1 - -ASM_PFX(IrqEntry): - sub LR,LR,#4 - srsdb #0x13! @ Store return state on SVC stack - cps #0x13 @ Switch to SVC for common stack - stmfd SP!,{LR} @ Store the link register for the current mode - sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR - stmfd SP!,{R0-R12} @ Store the register state - - mov R0,#6 @ ExceptionType - ldr R1,ASM_PFX(CommonExceptionEntry) - bx R1 - -ASM_PFX(FiqEntry): - sub LR,LR,#4 - srsdb #0x13! @ Store return state on SVC stack - cps #0x13 @ Switch to SVC for common stack - stmfd SP!,{LR} @ Store the link register for the current mode - sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR - stmfd SP!,{R0-R12} @ Store the register state - @ Since we have already switch to SVC R8_fiq - R12_fiq - @ never get used or saved - mov R0,#7 @ ExceptionType - ldr R1,ASM_PFX(CommonExceptionEntry) - bx R1 - -// -// This gets patched by the C code that patches in the vector table -// -ASM_PFX(CommonExceptionEntry): - .word ASM_PFX(AsmCommonExceptionEntry) - -ASM_PFX(ExceptionHandlersEnd): - -// -// This code runs from CpuDxe driver loaded address. It is patched into -// CommonExceptionEntry. -// -ASM_PFX(AsmCommonExceptionEntry): - mrc p15, 0, R1, c6, c0, 2 @ Read IFAR - str R1, [SP, #0x50] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR - - mrc p15, 0, R1, c5, c0, 1 @ Read IFSR - str R1, [SP, #0x4c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR - - mrc p15, 0, R1, c6, c0, 0 @ Read DFAR - str R1, [SP, #0x48] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR - - mrc p15, 0, R1, c5, c0, 0 @ Read DFSR - str R1, [SP, #0x44] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR - - ldr R1, [SP, #0x5c] @ srsdb saved pre-exception CPSR on the stack - str R1, [SP, #0x40] @ Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR - - add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR - and R3, R1, #0x1f @ Check CPSR to see if User or System Mode - cmp R3, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1f)) - cmpne R3, #0x10 @ - stmeqed R2, {lr}^ @ save unbanked lr - @ else - stmneed R2, {lr} @ save SVC lr - - - ldr R5, [SP, #0x58] @ PC is the LR pushed by srsfd - @ Check to see if we have to adjust for Thumb entry - sub r4, r0, #1 @ if (ExceptionType == 1 || ExceptionType == 2)) { - cmp r4, #1 @ // UND & SVC have differnt LR adjust for Thumb - bhi NoAdjustNeeded - - tst r1, #0x20 @ if ((CPSR & T)) == T) { // Thumb Mode on entry - addne R5, R5, #2 @ PC += 2; - strne R5,[SP,#0x58] @ Update LR value pushed by srsfd - -NoAdjustNeeded: - - str R5, [SP, #0x3c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.PC - - add R1, SP, #0x60 @ We pushed 0x60 bytes on the stack - str R1, [SP, #0x34] @ Store it in EFI_SYSTEM_CONTEXT_ARM.SP - - @ R0 is ExceptionType - mov R1,SP @ R1 is SystemContext - -#if (FixedPcdGet32(PcdVFPEnabled)) - vpush {d0-d15} @ save vstm registers in case they are used in optimizations -#endif - - mov R4, SP @ Save current SP - tst R4, #4 - subne SP, SP, #4 @ Adjust SP if not 8-byte aligned - -/* -VOID -EFIAPI -CommonCExceptionHandler ( - IN EFI_EXCEPTION_TYPE ExceptionType, R0 - IN OUT EFI_SYSTEM_CONTEXT SystemContext R1 - ) - -*/ - blx ASM_PFX(CommonCExceptionHandler) @ Call exception handler - - mov SP, R4 @ Restore SP - -#if (FixedPcdGet32(PcdVFPEnabled)) - vpop {d0-d15} -#endif - - ldr R1, [SP, #0x4c] @ Restore EFI_SYSTEM_CONTEXT_ARM.IFSR - mcr p15, 0, R1, c5, c0, 1 @ Write IFSR - - ldr R1, [SP, #0x44] @ Restore EFI_SYSTEM_CONTEXT_ARM.DFSR - mcr p15, 0, R1, c5, c0, 0 @ Write DFSR - - ldr R1,[SP,#0x3c] @ EFI_SYSTEM_CONTEXT_ARM.PC - str R1,[SP,#0x58] @ Store it back to srsfd stack slot so it can be restored - - ldr R1,[SP,#0x40] @ EFI_SYSTEM_CONTEXT_ARM.CPSR - str R1,[SP,#0x5c] @ Store it back to srsfd stack slot so it can be restored - - add R3, SP, #0x54 @ Make R3 point to SVC LR saved on entry - add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR - and R1, R1, #0x1f @ Check to see if User or System Mode - cmp R1, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1f)) - cmpne R1, #0x10 @ - ldmeqed R2, {lr}^ @ restore unbanked lr - @ else - ldmneed R3, {lr} @ restore SVC lr, via ldmfd SP!, {LR} - - ldmfd SP!,{R0-R12} @ Restore general purpose registers - @ Exception handler can not change SP - - add SP,SP,#0x20 @ Clear out the remaining stack space - ldmfd SP!,{LR} @ restore the link register for this context - rfefd SP! @ return from exception via srsfd stack slot - diff --git a/ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.asm b/ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.asm deleted file mode 100644 index b28ff9f7ee..0000000000 --- a/ArmPkg/Drivers/CpuDxe/ArmV6/ExceptionSupport.asm +++ /dev/null @@ -1,301 +0,0 @@ -//------------------------------------------------------------------------------ -// -// Use ARMv6 instruction to operate on a single stack -// -// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
-// Copyright (c) 2014, ARM Limited. All rights reserved.
-// -// This program and the accompanying materials -// are licensed and made available under the terms and conditions of the BSD License -// which accompanies this distribution. The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -// -//------------------------------------------------------------------------------ - -#include - -/* - -This is the stack constructed by the exception handler (low address to high address) - # R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM - Reg Offset - === ====== - R0 0x00 # stmfd SP!,{R0-R12} - R1 0x04 - R2 0x08 - R3 0x0c - R4 0x10 - R5 0x14 - R6 0x18 - R7 0x1c - R8 0x20 - R9 0x24 - R10 0x28 - R11 0x2c - R12 0x30 - SP 0x34 # reserved via subtraction 0x20 (32) from SP - LR 0x38 - PC 0x3c - CPSR 0x40 - DFSR 0x44 - DFAR 0x48 - IFSR 0x4c - IFAR 0x50 - - LR 0x54 # SVC Link register (we need to restore it) - - LR 0x58 # pushed by srsfd - CPSR 0x5c - - */ - - - EXPORT ExceptionHandlersStart - EXPORT ExceptionHandlersEnd - EXPORT CommonExceptionEntry - EXPORT AsmCommonExceptionEntry - IMPORT CommonCExceptionHandler - - PRESERVE8 - AREA DxeExceptionHandlers, CODE, READONLY, CODEALIGN, ALIGN=5 - -// -// This code gets copied to the ARM vector table -// ExceptionHandlersStart - ExceptionHandlersEnd gets copied -// -ExceptionHandlersStart - -Reset - b ResetEntry - -UndefinedInstruction - b UndefinedInstructionEntry - -SoftwareInterrupt - b SoftwareInterruptEntry - -PrefetchAbort - b PrefetchAbortEntry - -DataAbort - b DataAbortEntry - -ReservedException - b ReservedExceptionEntry - -Irq - b IrqEntry - -Fiq - b FiqEntry - -ResetEntry - srsfd #0x13! ; Store return state on SVC stack - ; We are already in SVC mode - stmfd SP!,{LR} ; Store the link register for the current mode - sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR - stmfd SP!,{R0-R12} ; Store the register state - - mov R0,#0 ; ExceptionType - ldr R1,CommonExceptionEntry - bx R1 - -UndefinedInstructionEntry - sub LR, LR, #4 ; Only -2 for Thumb, adjust in CommonExceptionEntry - srsfd #0x13! ; Store return state on SVC stack - cps #0x13 ; Switch to SVC for common stack - stmfd SP!,{LR} ; Store the link register for the current mode - sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR - stmfd SP!,{R0-R12} ; Store the register state - - mov R0,#1 ; ExceptionType - ldr R1,CommonExceptionEntry; - bx R1 - -SoftwareInterruptEntry - srsfd #0x13! ; Store return state on SVC stack - ; We are already in SVC mode - stmfd SP!,{LR} ; Store the link register for the current mode - sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR - stmfd SP!,{R0-R12} ; Store the register state - - mov R0,#2 ; ExceptionType - ldr R1,CommonExceptionEntry - bx R1 - -PrefetchAbortEntry - sub LR,LR,#4 - srsfd #0x13! ; Store return state on SVC stack - cps #0x13 ; Switch to SVC for common stack - stmfd SP!,{LR} ; Store the link register for the current mode - sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR - stmfd SP!,{R0-R12} ; Store the register state - - mov R0,#3 ; ExceptionType - ldr R1,CommonExceptionEntry - bx R1 - -DataAbortEntry - sub LR,LR,#8 - srsfd #0x13! ; Store return state on SVC stack - cps #0x13 ; Switch to SVC for common stack - stmfd SP!,{LR} ; Store the link register for the current mode - sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR - stmfd SP!,{R0-R12} ; Store the register state - - mov R0,#4 ; ExceptionType - ldr R1,CommonExceptionEntry - bx R1 - -ReservedExceptionEntry - srsfd #0x13! ; Store return state on SVC stack - cps #0x13 ; Switch to SVC for common stack - stmfd SP!,{LR} ; Store the link register for the current mode - sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR - stmfd SP!,{R0-R12} ; Store the register state - - mov R0,#5 ; ExceptionType - ldr R1,CommonExceptionEntry - bx R1 - -IrqEntry - sub LR,LR,#4 - srsfd #0x13! ; Store return state on SVC stack - cps #0x13 ; Switch to SVC for common stack - stmfd SP!,{LR} ; Store the link register for the current mode - sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR - stmfd SP!,{R0-R12} ; Store the register state - - mov R0,#6 ; ExceptionType - ldr R1,CommonExceptionEntry - bx R1 - -FiqEntry - sub LR,LR,#4 - srsfd #0x13! ; Store return state on SVC stack - cps #0x13 ; Switch to SVC for common stack - stmfd SP!,{LR} ; Store the link register for the current mode - sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR - stmfd SP!,{R0-R12} ; Store the register state - ; Since we have already switch to SVC R8_fiq - R12_fiq - ; never get used or saved - mov R0,#7 ; ExceptionType - ldr R1,CommonExceptionEntry - bx R1 - -// -// This gets patched by the C code that patches in the vector table -// -CommonExceptionEntry - dcd AsmCommonExceptionEntry - -ExceptionHandlersEnd - -// -// This code runs from CpuDxe driver loaded address. It is patched into -// CommonExceptionEntry. -// -AsmCommonExceptionEntry - mrc p15, 0, R1, c6, c0, 2 ; Read IFAR - str R1, [SP, #0x50] ; Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR - - mrc p15, 0, R1, c5, c0, 1 ; Read IFSR - str R1, [SP, #0x4c] ; Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR - - mrc p15, 0, R1, c6, c0, 0 ; Read DFAR - str R1, [SP, #0x48] ; Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR - - mrc p15, 0, R1, c5, c0, 0 ; Read DFSR - str R1, [SP, #0x44] ; Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR - - ldr R1, [SP, #0x5c] ; srsfd saved pre-exception CPSR on the stack - str R1, [SP, #0x40] ; Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR - - add R2, SP, #0x38 ; Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR - and R3, R1, #0x1f ; Check CPSR to see if User or System Mode - cmp R3, #0x1f ; if ((CPSR == 0x10) || (CPSR == 0x1f)) - cmpne R3, #0x10 ; - stmeqed R2, {lr}^ ; save unbanked lr - ; else - stmneed R2, {lr} ; save SVC lr - - - ldr R5, [SP, #0x58] ; PC is the LR pushed by srsfd - ; Check to see if we have to adjust for Thumb entry - sub r4, r0, #1 ; if (ExceptionType == 1 || ExceptionType == 2)) { - cmp r4, #1 ; // UND & SVC have differnt LR adjust for Thumb - bhi NoAdjustNeeded - - tst r1, #0x20 ; if ((CPSR & T)) == T) { // Thumb Mode on entry - addne R5, R5, #2 ; PC += 2; - strne R5,[SP,#0x58] ; Update LR value pushed by srsfd - -NoAdjustNeeded - - str R5, [SP, #0x3c] ; Store it in EFI_SYSTEM_CONTEXT_ARM.PC - - add R1, SP, #0x60 ; We pushed 0x60 bytes on the stack - str R1, [SP, #0x34] ; Store it in EFI_SYSTEM_CONTEXT_ARM.SP - - ; R0 is ExceptionType - mov R1,SP ; R1 is SystemContext - -#if (FixedPcdGet32(PcdVFPEnabled)) - vpush {d0-d15} ; save vstm registers in case they are used in optimizations -#endif - - mov R4, SP ; Save current SP - tst R4, #4 - subne SP, SP, #4 ; Adjust SP if not 8-byte aligned - -/* -VOID -EFIAPI -CommonCExceptionHandler ( - IN EFI_EXCEPTION_TYPE ExceptionType, R0 - IN OUT EFI_SYSTEM_CONTEXT SystemContext R1 - ) - -*/ - blx CommonCExceptionHandler ; Call exception handler - - mov SP, R4 ; Restore SP - -#if (FixedPcdGet32(PcdVFPEnabled)) - vpop {d0-d15} -#endif - - ldr R1, [SP, #0x4c] ; Restore EFI_SYSTEM_CONTEXT_ARM.IFSR - mcr p15, 0, R1, c5, c0, 1 ; Write IFSR - - ldr R1, [SP, #0x44] ; Restore EFI_SYSTEM_CONTEXT_ARM.DFSR - mcr p15, 0, R1, c5, c0, 0 ; Write DFSR - - ldr R1,[SP,#0x3c] ; EFI_SYSTEM_CONTEXT_ARM.PC - str R1,[SP,#0x58] ; Store it back to srsfd stack slot so it can be restored - - ldr R1,[SP,#0x40] ; EFI_SYSTEM_CONTEXT_ARM.CPSR - str R1,[SP,#0x5c] ; Store it back to srsfd stack slot so it can be restored - - add R3, SP, #0x54 ; Make R3 point to SVC LR saved on entry - add R2, SP, #0x38 ; Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR - and R1, R1, #0x1f ; Check to see if User or System Mode - cmp R1, #0x1f ; if ((CPSR == 0x10) || (CPSR == 0x1f)) - cmpne R1, #0x10 ; - ldmeqed R2, {lr}^ ; restore unbanked lr - ; else - ldmneed R3, {lr} ; restore SVC lr, via ldmfd SP!, {LR} - - ldmfd SP!,{R0-R12} ; Restore general purpose registers - ; Exception handler can not change SP - - add SP,SP,#0x20 ; Clear out the remaining stack space - ldmfd SP!,{LR} ; restore the link register for this context - rfefd SP! ; return from exception via srsfd stack slot - - END - - diff --git a/ArmPkg/Drivers/CpuDxe/ArmV6/Mmu.c b/ArmPkg/Drivers/CpuDxe/ArmV6/Mmu.c deleted file mode 100644 index 63da8ba8cb..0000000000 --- a/ArmPkg/Drivers/CpuDxe/ArmV6/Mmu.c +++ /dev/null @@ -1,880 +0,0 @@ -/*++ - -Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.
-Portions copyright (c) 2010, Apple Inc. All rights reserved.
-Portions copyright (c) 2013, ARM Ltd. All rights reserved.
- -This program and the accompanying materials -are licensed and made available under the terms and conditions of the BSD License -which accompanies this distribution. The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - - ---*/ - -#include -#include "CpuDxe.h" - -// First Level Descriptors -typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR; - -// Second Level Descriptors -typedef UINT32 ARM_PAGE_TABLE_ENTRY; - -EFI_STATUS -SectionToGcdAttributes ( - IN UINT32 SectionAttributes, - OUT UINT64 *GcdAttributes - ) -{ - *GcdAttributes = 0; - - // determine cacheability attributes - switch(SectionAttributes & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) { - case TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED: - *GcdAttributes |= EFI_MEMORY_UC; - break; - case TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE: - *GcdAttributes |= EFI_MEMORY_UC; - break; - case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC: - *GcdAttributes |= EFI_MEMORY_WT; - break; - case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC: - *GcdAttributes |= EFI_MEMORY_WB; - break; - case TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE: - *GcdAttributes |= EFI_MEMORY_WC; - break; - case TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC: - *GcdAttributes |= EFI_MEMORY_WB; - break; - case TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE: - *GcdAttributes |= EFI_MEMORY_UC; - break; - default: - return EFI_UNSUPPORTED; - } - - // determine protection attributes - switch(SectionAttributes & TT_DESCRIPTOR_SECTION_AP_MASK) { - case TT_DESCRIPTOR_SECTION_AP_NO_NO: // no read, no write - //*GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP; - break; - - case TT_DESCRIPTOR_SECTION_AP_RW_NO: - case TT_DESCRIPTOR_SECTION_AP_RW_RW: - // normal read/write access, do not add additional attributes - break; - - // read only cases map to write-protect - case TT_DESCRIPTOR_SECTION_AP_RO_NO: - case TT_DESCRIPTOR_SECTION_AP_RO_RO: - *GcdAttributes |= EFI_MEMORY_WP; - break; - - default: - return EFI_UNSUPPORTED; - } - - // now process eXectue Never attribute - if ((SectionAttributes & TT_DESCRIPTOR_SECTION_XN_MASK) != 0 ) { - *GcdAttributes |= EFI_MEMORY_XP; - } - - return EFI_SUCCESS; -} - -EFI_STATUS -PageToGcdAttributes ( - IN UINT32 PageAttributes, - OUT UINT64 *GcdAttributes - ) -{ - *GcdAttributes = 0; - - // determine cacheability attributes - switch(PageAttributes & TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK) { - case TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED: - *GcdAttributes |= EFI_MEMORY_UC; - break; - case TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE: - *GcdAttributes |= EFI_MEMORY_UC; - break; - case TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC: - *GcdAttributes |= EFI_MEMORY_WT; - break; - case TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC: - *GcdAttributes |= EFI_MEMORY_WB; - break; - case TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE: - *GcdAttributes |= EFI_MEMORY_WC; - break; - case TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC: - *GcdAttributes |= EFI_MEMORY_WB; - break; - case TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE: - *GcdAttributes |= EFI_MEMORY_UC; - break; - default: - return EFI_UNSUPPORTED; - } - - // determine protection attributes - switch(PageAttributes & TT_DESCRIPTOR_PAGE_AP_MASK) { - case TT_DESCRIPTOR_PAGE_AP_NO_NO: // no read, no write - //*GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP; - break; - - case TT_DESCRIPTOR_PAGE_AP_RW_NO: - case TT_DESCRIPTOR_PAGE_AP_RW_RW: - // normal read/write access, do not add additional attributes - break; - - // read only cases map to write-protect - case TT_DESCRIPTOR_PAGE_AP_RO_NO: - case TT_DESCRIPTOR_PAGE_AP_RO_RO: - *GcdAttributes |= EFI_MEMORY_WP; - break; - - default: - return EFI_UNSUPPORTED; - } - - // now process eXectue Never attribute - if ((PageAttributes & TT_DESCRIPTOR_PAGE_XN_MASK) != 0 ) { - *GcdAttributes |= EFI_MEMORY_XP; - } - - return EFI_SUCCESS; -} - -EFI_STATUS -SyncCacheConfigPage ( - IN UINT32 SectionIndex, - IN UINT32 FirstLevelDescriptor, - IN UINTN NumberOfDescriptors, - IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap, - IN OUT EFI_PHYSICAL_ADDRESS *NextRegionBase, - IN OUT UINT64 *NextRegionLength, - IN OUT UINT32 *NextSectionAttributes - ) -{ - EFI_STATUS Status; - UINT32 i; - volatile ARM_PAGE_TABLE_ENTRY *SecondLevelTable; - UINT32 NextPageAttributes = 0; - UINT32 PageAttributes = 0; - UINT32 BaseAddress; - UINT64 GcdAttributes; - - // Get the Base Address from FirstLevelDescriptor; - BaseAddress = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(SectionIndex << TT_DESCRIPTOR_SECTION_BASE_SHIFT); - - // Convert SectionAttributes into PageAttributes - NextPageAttributes = - TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(*NextSectionAttributes,0) | - TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(*NextSectionAttributes); - - // obtain page table base - SecondLevelTable = (ARM_PAGE_TABLE_ENTRY *)(FirstLevelDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK); - - for (i=0; i < TRANSLATION_TABLE_PAGE_COUNT; i++) { - if ((SecondLevelTable[i] & TT_DESCRIPTOR_PAGE_TYPE_MASK) == TT_DESCRIPTOR_PAGE_TYPE_PAGE) { - // extract attributes (cacheability and permissions) - PageAttributes = SecondLevelTable[i] & (TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK | TT_DESCRIPTOR_PAGE_AP_MASK); - - if (NextPageAttributes == 0) { - // start on a new region - *NextRegionLength = 0; - *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT); - NextPageAttributes = PageAttributes; - } else if (PageAttributes != NextPageAttributes) { - // Convert Section Attributes into GCD Attributes - Status = PageToGcdAttributes (NextPageAttributes, &GcdAttributes); - ASSERT_EFI_ERROR (Status); - - // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK) - SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, *NextRegionBase, *NextRegionLength, GcdAttributes); - - // start on a new region - *NextRegionLength = 0; - *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT); - NextPageAttributes = PageAttributes; - } - } else if (NextPageAttributes != 0) { - // Convert Page Attributes into GCD Attributes - Status = PageToGcdAttributes (NextPageAttributes, &GcdAttributes); - ASSERT_EFI_ERROR (Status); - - // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK) - SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, *NextRegionBase, *NextRegionLength, GcdAttributes); - - *NextRegionLength = 0; - *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT); - NextPageAttributes = 0; - } - *NextRegionLength += TT_DESCRIPTOR_PAGE_SIZE; - } - - // Convert back PageAttributes into SectionAttributes - *NextSectionAttributes = - TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(NextPageAttributes,0) | - TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(NextPageAttributes); - - return EFI_SUCCESS; -} - -EFI_STATUS -SyncCacheConfig ( - IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol - ) -{ - EFI_STATUS Status; - UINT32 i; - EFI_PHYSICAL_ADDRESS NextRegionBase; - UINT64 NextRegionLength; - UINT32 NextSectionAttributes = 0; - UINT32 SectionAttributes = 0; - UINT64 GcdAttributes; - volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable; - UINTN NumberOfDescriptors; - EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap; - - - DEBUG ((EFI_D_PAGE, "SyncCacheConfig()\n")); - - // This code assumes MMU is enabled and filed with section translations - ASSERT (ArmMmuEnabled ()); - - // - // Get the memory space map from GCD - // - MemorySpaceMap = NULL; - Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap); - ASSERT_EFI_ERROR (Status); - - - // The GCD implementation maintains its own copy of the state of memory space attributes. GCD needs - // to know what the initial memory space attributes are. The CPU Arch. Protocol does not provide a - // GetMemoryAttributes function for GCD to get this so we must resort to calling GCD (as if we were - // a client) to update its copy of the attributes. This is bad architecture and should be replaced - // with a way for GCD to query the CPU Arch. driver of the existing memory space attributes instead. - - // obtain page table base - FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)(ArmGetTTBR0BaseAddress ()); - - // Get the first region - NextSectionAttributes = FirstLevelTable[0] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK); - - // iterate through each 1MB descriptor - NextRegionBase = NextRegionLength = 0; - for (i=0; i < TRANSLATION_TABLE_SECTION_COUNT; i++) { - if ((FirstLevelTable[i] & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) { - // extract attributes (cacheability and permissions) - SectionAttributes = FirstLevelTable[i] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK); - - if (NextSectionAttributes == 0) { - // start on a new region - NextRegionLength = 0; - NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT); - NextSectionAttributes = SectionAttributes; - } else if (SectionAttributes != NextSectionAttributes) { - // Convert Section Attributes into GCD Attributes - Status = SectionToGcdAttributes (NextSectionAttributes, &GcdAttributes); - ASSERT_EFI_ERROR (Status); - - // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK) - SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes); - - // start on a new region - NextRegionLength = 0; - NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT); - NextSectionAttributes = SectionAttributes; - } - NextRegionLength += TT_DESCRIPTOR_SECTION_SIZE; - } else if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(FirstLevelTable[i])) { - Status = SyncCacheConfigPage ( - i,FirstLevelTable[i], - NumberOfDescriptors, MemorySpaceMap, - &NextRegionBase,&NextRegionLength,&NextSectionAttributes); - ASSERT_EFI_ERROR (Status); - } else { - // We do not support yet 16MB sections - ASSERT ((FirstLevelTable[i] & TT_DESCRIPTOR_SECTION_TYPE_MASK) != TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION); - - // start on a new region - if (NextSectionAttributes != 0) { - // Convert Section Attributes into GCD Attributes - Status = SectionToGcdAttributes (NextSectionAttributes, &GcdAttributes); - ASSERT_EFI_ERROR (Status); - - // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK) - SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes); - - NextRegionLength = 0; - NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT); - NextSectionAttributes = 0; - } - NextRegionLength += TT_DESCRIPTOR_SECTION_SIZE; - } - } // section entry loop - - if (NextSectionAttributes != 0) { - // Convert Section Attributes into GCD Attributes - Status = SectionToGcdAttributes (NextSectionAttributes, &GcdAttributes); - ASSERT_EFI_ERROR (Status); - - // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK) - SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes); - } - - FreePool (MemorySpaceMap); - - return EFI_SUCCESS; -} - - - -EFI_STATUS -UpdatePageEntries ( - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes, - IN EFI_PHYSICAL_ADDRESS VirtualMask - ) -{ - EFI_STATUS Status; - UINT32 EntryValue; - UINT32 EntryMask; - UINT32 FirstLevelIdx; - UINT32 Offset; - UINT32 NumPageEntries; - UINT32 Descriptor; - UINT32 p; - UINT32 PageTableIndex; - UINT32 PageTableEntry; - UINT32 CurrentPageTableEntry; - VOID *Mva; - - volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable; - volatile ARM_PAGE_TABLE_ENTRY *PageTable; - - Status = EFI_SUCCESS; - - // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone) - // EntryValue: values at bit positions specified by EntryMask - EntryMask = TT_DESCRIPTOR_PAGE_TYPE_MASK; - EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE; - // Although the PI spec is unclear on this the GCD guarantees that only - // one Attribute bit is set at a time, so we can safely use a switch statement - switch (Attributes) { - case EFI_MEMORY_UC: - // modify cacheability attributes - EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; - // map to strongly ordered - EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0 - break; - - case EFI_MEMORY_WC: - // modify cacheability attributes - EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; - // map to normal non-cachable - EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0 - break; - - case EFI_MEMORY_WT: - // modify cacheability attributes - EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; - // write through with no-allocate - EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0 - break; - - case EFI_MEMORY_WB: - // modify cacheability attributes - EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; - // write back (with allocate) - EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1 - break; - - case EFI_MEMORY_WP: - case EFI_MEMORY_XP: - case EFI_MEMORY_UCE: - // cannot be implemented UEFI definition unclear for ARM - // Cause a page fault if these ranges are accessed. - EntryValue = TT_DESCRIPTOR_PAGE_TYPE_FAULT; - DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting page %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes)); - break; - - default: - return EFI_UNSUPPORTED; - } - - // Obtain page table base - FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress (); - - // Calculate number of 4KB page table entries to change - NumPageEntries = Length / TT_DESCRIPTOR_PAGE_SIZE; - - // Iterate for the number of 4KB pages to change - Offset = 0; - for(p = 0; p < NumPageEntries; p++) { - // Calculate index into first level translation table for page table value - - FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress + Offset) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT; - ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT); - - // Read the descriptor from the first level page table - Descriptor = FirstLevelTable[FirstLevelIdx]; - - // Does this descriptor need to be converted from section entry to 4K pages? - if (!TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Descriptor)) { - Status = ConvertSectionToPages (FirstLevelIdx << TT_DESCRIPTOR_SECTION_BASE_SHIFT); - if (EFI_ERROR(Status)) { - // Exit for loop - break; - } - - // Re-read descriptor - Descriptor = FirstLevelTable[FirstLevelIdx]; - } - - // Obtain page table base address - PageTable = (ARM_PAGE_TABLE_ENTRY *)TT_DESCRIPTOR_PAGE_BASE_ADDRESS(Descriptor); - - // Calculate index into the page table - PageTableIndex = ((BaseAddress + Offset) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT; - ASSERT (PageTableIndex < TRANSLATION_TABLE_PAGE_COUNT); - - // Get the entry - CurrentPageTableEntry = PageTable[PageTableIndex]; - - // Mask off appropriate fields - PageTableEntry = CurrentPageTableEntry & ~EntryMask; - - // Mask in new attributes and/or permissions - PageTableEntry |= EntryValue; - - if (VirtualMask != 0) { - // Make this virtual address point at a physical page - PageTableEntry &= ~VirtualMask; - } - - if (CurrentPageTableEntry != PageTableEntry) { - Mva = (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << TT_DESCRIPTOR_SECTION_BASE_SHIFT) + (PageTableIndex << TT_DESCRIPTOR_PAGE_BASE_SHIFT)); - if ((CurrentPageTableEntry & TT_DESCRIPTOR_PAGE_CACHEABLE_MASK) == TT_DESCRIPTOR_PAGE_CACHEABLE_MASK) { - // The current section mapping is cacheable so Clean/Invalidate the MVA of the page - // Note assumes switch(Attributes), not ARMv7 possibilities - WriteBackInvalidateDataCacheRange (Mva, TT_DESCRIPTOR_PAGE_SIZE); - } - - // Only need to update if we are changing the entry - PageTable[PageTableIndex] = PageTableEntry; - ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], Mva); - } - - Status = EFI_SUCCESS; - Offset += TT_DESCRIPTOR_PAGE_SIZE; - - } // End first level translation table loop - - return Status; -} - - - -EFI_STATUS -UpdateSectionEntries ( - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes, - IN EFI_PHYSICAL_ADDRESS VirtualMask - ) -{ - EFI_STATUS Status = EFI_SUCCESS; - UINT32 EntryMask; - UINT32 EntryValue; - UINT32 FirstLevelIdx; - UINT32 NumSections; - UINT32 i; - UINT32 CurrentDescriptor; - UINT32 Descriptor; - VOID *Mva; - volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable; - - // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone) - // EntryValue: values at bit positions specified by EntryMask - - // Make sure we handle a section range that is unmapped - EntryMask = TT_DESCRIPTOR_SECTION_TYPE_MASK; - EntryValue = TT_DESCRIPTOR_SECTION_TYPE_SECTION; - - // Although the PI spec is unclear on this the GCD guarantees that only - // one Attribute bit is set at a time, so we can safely use a switch statement - switch(Attributes) { - case EFI_MEMORY_UC: - // modify cacheability attributes - EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; - // map to strongly ordered - EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0 - break; - - case EFI_MEMORY_WC: - // modify cacheability attributes - EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; - // map to normal non-cachable - EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0 - break; - - case EFI_MEMORY_WT: - // modify cacheability attributes - EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; - // write through with no-allocate - EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0 - break; - - case EFI_MEMORY_WB: - // modify cacheability attributes - EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; - // write back (with allocate) - EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1 - break; - - case EFI_MEMORY_WP: - case EFI_MEMORY_XP: - case EFI_MEMORY_RP: - case EFI_MEMORY_UCE: - // cannot be implemented UEFI definition unclear for ARM - // Cause a page fault if these ranges are accessed. - EntryValue = TT_DESCRIPTOR_SECTION_TYPE_FAULT; - DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting section %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes)); - break; - - - default: - return EFI_UNSUPPORTED; - } - - // obtain page table base - FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress (); - - // calculate index into first level translation table for start of modification - FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT; - ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT); - - // calculate number of 1MB first level entries this applies to - NumSections = Length / TT_DESCRIPTOR_SECTION_SIZE; - - // iterate through each descriptor - for(i=0; i> TT_DESCRIPTOR_SECTION_BASE_SHIFT; - ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT); - - // Get section attributes and convert to page attributes - SectionDescriptor = FirstLevelTable[FirstLevelIdx]; - PageDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttributesToPageAttributes (SectionDescriptor, FALSE); - - // Allocate a page table for the 4KB entries (we use up a full page even though we only need 1KB) - Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, 1, &PageTableAddr); - if (EFI_ERROR(Status)) { - return Status; - } - - PageTable = (volatile ARM_PAGE_TABLE_ENTRY *)(UINTN)PageTableAddr; - - // Write the page table entries out - for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) { - PageTable[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (Index << 12)) | PageDescriptor; - } - - // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks - WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)PageTableAddr, TT_DESCRIPTOR_PAGE_SIZE); - - // Formulate page table entry, Domain=0, NS=0 - PageTableDescriptor = (((UINTN)PageTableAddr) & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE; - - // Write the page table entry out, replacing section entry - FirstLevelTable[FirstLevelIdx] = PageTableDescriptor; - - return EFI_SUCCESS; -} - - - -EFI_STATUS -SetMemoryAttributes ( - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes, - IN EFI_PHYSICAL_ADDRESS VirtualMask - ) -{ - EFI_STATUS Status; - - if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) { - // Is the base and length a multiple of 1 MB? - DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes)); - Status = UpdateSectionEntries (BaseAddress, Length, Attributes, VirtualMask); - } else { - // Base and/or length is not a multiple of 1 MB - DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU page 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes)); - Status = UpdatePageEntries (BaseAddress, Length, Attributes, VirtualMask); - } - - // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks - // flush and invalidate pages - //TODO: Do we really need to invalidate the caches everytime we change the memory attributes ? - ArmCleanInvalidateDataCache (); - - ArmInvalidateInstructionCache (); - - // Invalidate all TLB entries so changes are synced - ArmInvalidateTlb (); - - return Status; -} - -UINT64 -EfiAttributeToArmAttribute ( - IN UINT64 EfiAttributes - ) -{ - UINT64 ArmAttributes; - - switch (EfiAttributes & EFI_MEMORY_CACHETYPE_MASK) { - case EFI_MEMORY_UC: - // Map to strongly ordered - ArmAttributes = TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0 - break; - - case EFI_MEMORY_WC: - // Map to normal non-cachable - ArmAttributes = TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0 - break; - - case EFI_MEMORY_WT: - // Write through with no-allocate - ArmAttributes = TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0 - break; - - case EFI_MEMORY_WB: - // Write back (with allocate) - ArmAttributes = TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1 - break; - - case EFI_MEMORY_WP: - case EFI_MEMORY_XP: - case EFI_MEMORY_RP: - case EFI_MEMORY_UCE: - default: - // Cannot be implemented UEFI definition unclear for ARM - // Cause a page fault if these ranges are accessed. - ArmAttributes = TT_DESCRIPTOR_SECTION_TYPE_FAULT; - DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): Unsupported attribute %x will page fault on access\n", EfiAttributes)); - break; - } - - // Determine protection attributes - if (EfiAttributes & EFI_MEMORY_WP) { - ArmAttributes |= TT_DESCRIPTOR_SECTION_AP_RO_RO; - } else { - ArmAttributes |= TT_DESCRIPTOR_SECTION_AP_RW_RW; - } - - // Determine eXecute Never attribute - if (EfiAttributes & EFI_MEMORY_XP) { - ArmAttributes |= TT_DESCRIPTOR_SECTION_XN_MASK; - } - - return ArmAttributes; -} - -EFI_STATUS -GetMemoryRegionPage ( - IN UINT32 *PageTable, - IN OUT UINTN *BaseAddress, - OUT UINTN *RegionLength, - OUT UINTN *RegionAttributes - ) -{ - UINT32 PageAttributes; - UINT32 TableIndex; - UINT32 PageDescriptor; - - // Convert the section attributes into page attributes - PageAttributes = ConvertSectionAttributesToPageAttributes (*RegionAttributes, 0); - - // Calculate index into first level translation table for start of modification - TableIndex = ((*BaseAddress) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT; - ASSERT (TableIndex < TRANSLATION_TABLE_PAGE_COUNT); - - // Go through the page table to find the end of the section - for (; TableIndex < TRANSLATION_TABLE_PAGE_COUNT; TableIndex++) { - // Get the section at the given index - PageDescriptor = PageTable[TableIndex]; - - if ((PageDescriptor & TT_DESCRIPTOR_PAGE_TYPE_MASK) == TT_DESCRIPTOR_PAGE_TYPE_FAULT) { - // Case: End of the boundary of the region - return EFI_SUCCESS; - } else if ((PageDescriptor & TT_DESCRIPTOR_PAGE_TYPE_PAGE) == TT_DESCRIPTOR_PAGE_TYPE_PAGE) { - if ((PageDescriptor & TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK) == PageAttributes) { - *RegionLength = *RegionLength + TT_DESCRIPTOR_PAGE_SIZE; - } else { - // Case: End of the boundary of the region - return EFI_SUCCESS; - } - } else { - // We do not support Large Page yet. We return EFI_SUCCESS that means end of the region. - ASSERT(0); - return EFI_SUCCESS; - } - } - - return EFI_NOT_FOUND; -} - -EFI_STATUS -GetMemoryRegion ( - IN OUT UINTN *BaseAddress, - OUT UINTN *RegionLength, - OUT UINTN *RegionAttributes - ) -{ - EFI_STATUS Status; - UINT32 TableIndex; - UINT32 PageAttributes; - UINT32 PageTableIndex; - UINT32 SectionDescriptor; - ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable; - UINT32 *PageTable; - - // Initialize the arguments - *RegionLength = 0; - - // Obtain page table base - FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress (); - - // Calculate index into first level translation table for start of modification - TableIndex = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (*BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT; - ASSERT (TableIndex < TRANSLATION_TABLE_SECTION_COUNT); - - // Get the section at the given index - SectionDescriptor = FirstLevelTable[TableIndex]; - - // If 'BaseAddress' belongs to the section then round it to the section boundary - if (((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) || - ((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION)) - { - *BaseAddress = (*BaseAddress) & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK; - *RegionAttributes = SectionDescriptor & TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK; - } else { - // Otherwise, we round it to the page boundary - *BaseAddress = (*BaseAddress) & TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK; - - // Get the attribute at the page table level (Level 2) - PageTable = (UINT32*)(SectionDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK); - - // Calculate index into first level translation table for start of modification - PageTableIndex = ((*BaseAddress) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT; - ASSERT (PageTableIndex < TRANSLATION_TABLE_PAGE_COUNT); - - PageAttributes = PageTable[PageTableIndex] & TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK; - *RegionAttributes = TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY (PageAttributes, 0) | - TT_DESCRIPTOR_CONVERT_TO_SECTION_AP (PageAttributes); - } - - for (;TableIndex < TRANSLATION_TABLE_SECTION_COUNT; TableIndex++) { - // Get the section at the given index - SectionDescriptor = FirstLevelTable[TableIndex]; - - // If the entry is a level-2 page table then we scan it to find the end of the region - if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE (SectionDescriptor)) { - // Extract the page table location from the descriptor - PageTable = (UINT32*)(SectionDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK); - - // Scan the page table to find the end of the region. - Status = GetMemoryRegionPage (PageTable, BaseAddress, RegionLength, RegionAttributes); - - // If we have found the end of the region (Status == EFI_SUCCESS) then we exit the for-loop - if (Status == EFI_SUCCESS) { - break; - } - } else if (((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) || - ((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION)) { - if ((SectionDescriptor & TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK) != *RegionAttributes) { - // If the attributes of the section differ from the one targeted then we exit the loop - break; - } else { - *RegionLength = *RegionLength + TT_DESCRIPTOR_SECTION_SIZE; - } - } else { - // If we are on an invalid section then it means it is the end of our section. - break; - } - } - - return EFI_SUCCESS; -} diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.c b/ArmPkg/Drivers/CpuDxe/CpuDxe.c deleted file mode 100644 index 0c49acb510..0000000000 --- a/ArmPkg/Drivers/CpuDxe/CpuDxe.c +++ /dev/null @@ -1,280 +0,0 @@ -/** @file - - Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
- Copyright (c) 2011, ARM Limited. All rights reserved. - - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include "CpuDxe.h" - -#include - -BOOLEAN mInterruptState = FALSE; - - -/** - This function flushes the range of addresses from Start to Start+Length - from the processor's data cache. If Start is not aligned to a cache line - boundary, then the bytes before Start to the preceding cache line boundary - are also flushed. If Start+Length is not aligned to a cache line boundary, - then the bytes past Start+Length to the end of the next cache line boundary - are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be - supported. If the data cache is fully coherent with all DMA operations, then - this function can just return EFI_SUCCESS. If the processor does not support - flushing a range of the data cache, then the entire data cache can be flushed. - - @param This The EFI_CPU_ARCH_PROTOCOL instance. - @param Start The beginning physical address to flush from the processor's data - cache. - @param Length The number of bytes to flush from the processor's data cache. This - function may flush more bytes than Length specifies depending upon - the granularity of the flush operation that the processor supports. - @param FlushType Specifies the type of flush operation to perform. - - @retval EFI_SUCCESS The address range from Start to Start+Length was flushed from - the processor's data cache. - @retval EFI_UNSUPPORTEDT The processor does not support the cache flush type specified - by FlushType. - @retval EFI_DEVICE_ERROR The address range from Start to Start+Length could not be flushed - from the processor's data cache. - -**/ -EFI_STATUS -EFIAPI -CpuFlushCpuDataCache ( - IN EFI_CPU_ARCH_PROTOCOL *This, - IN EFI_PHYSICAL_ADDRESS Start, - IN UINT64 Length, - IN EFI_CPU_FLUSH_TYPE FlushType - ) -{ - - switch (FlushType) { - case EfiCpuFlushTypeWriteBack: - WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length); - break; - case EfiCpuFlushTypeInvalidate: - InvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length); - break; - case EfiCpuFlushTypeWriteBackInvalidate: - WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length); - break; - default: - return EFI_INVALID_PARAMETER; - } - - return EFI_SUCCESS; -} - - -/** - This function enables interrupt processing by the processor. - - @param This The EFI_CPU_ARCH_PROTOCOL instance. - - @retval EFI_SUCCESS Interrupts are enabled on the processor. - @retval EFI_DEVICE_ERROR Interrupts could not be enabled on the processor. - -**/ -EFI_STATUS -EFIAPI -CpuEnableInterrupt ( - IN EFI_CPU_ARCH_PROTOCOL *This - ) -{ - ArmEnableInterrupts (); - - mInterruptState = TRUE; - return EFI_SUCCESS; -} - - -/** - This function disables interrupt processing by the processor. - - @param This The EFI_CPU_ARCH_PROTOCOL instance. - - @retval EFI_SUCCESS Interrupts are disabled on the processor. - @retval EFI_DEVICE_ERROR Interrupts could not be disabled on the processor. - -**/ -EFI_STATUS -EFIAPI -CpuDisableInterrupt ( - IN EFI_CPU_ARCH_PROTOCOL *This - ) -{ - ArmDisableInterrupts (); - - mInterruptState = FALSE; - return EFI_SUCCESS; -} - - -/** - This function retrieves the processor's current interrupt state a returns it in - State. If interrupts are currently enabled, then TRUE is returned. If interrupts - are currently disabled, then FALSE is returned. - - @param This The EFI_CPU_ARCH_PROTOCOL instance. - @param State A pointer to the processor's current interrupt state. Set to TRUE if - interrupts are enabled and FALSE if interrupts are disabled. - - @retval EFI_SUCCESS The processor's current interrupt state was returned in State. - @retval EFI_INVALID_PARAMETER State is NULL. - -**/ -EFI_STATUS -EFIAPI -CpuGetInterruptState ( - IN EFI_CPU_ARCH_PROTOCOL *This, - OUT BOOLEAN *State - ) -{ - if (State == NULL) { - return EFI_INVALID_PARAMETER; - } - - *State = mInterruptState; - return EFI_SUCCESS; -} - - -/** - This function generates an INIT on the processor. If this function succeeds, then the - processor will be reset, and control will not be returned to the caller. If InitType is - not supported by this processor, or the processor cannot programmatically generate an - INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error - occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned. - - @param This The EFI_CPU_ARCH_PROTOCOL instance. - @param InitType The type of processor INIT to perform. - - @retval EFI_SUCCESS The processor INIT was performed. This return code should never be seen. - @retval EFI_UNSUPPORTED The processor INIT operation specified by InitType is not supported - by this processor. - @retval EFI_DEVICE_ERROR The processor INIT failed. - -**/ -EFI_STATUS -EFIAPI -CpuInit ( - IN EFI_CPU_ARCH_PROTOCOL *This, - IN EFI_CPU_INIT_TYPE InitType - ) -{ - return EFI_UNSUPPORTED; -} - -EFI_STATUS -EFIAPI -CpuRegisterInterruptHandler ( - IN EFI_CPU_ARCH_PROTOCOL *This, - IN EFI_EXCEPTION_TYPE InterruptType, - IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler - ) -{ - return RegisterInterruptHandler (InterruptType, InterruptHandler); -} - -EFI_STATUS -EFIAPI -CpuGetTimerValue ( - IN EFI_CPU_ARCH_PROTOCOL *This, - IN UINT32 TimerIndex, - OUT UINT64 *TimerValue, - OUT UINT64 *TimerPeriod OPTIONAL - ) -{ - return EFI_UNSUPPORTED; -} - -/** - Callback function for idle events. - - @param Event Event whose notification function is being invoked. - @param Context The pointer to the notification function's context, - which is implementation-dependent. - -**/ -VOID -EFIAPI -IdleLoopEventCallback ( - IN EFI_EVENT Event, - IN VOID *Context - ) -{ - CpuSleep (); -} - -// -// Globals used to initialize the protocol -// -EFI_HANDLE mCpuHandle = NULL; -EFI_CPU_ARCH_PROTOCOL mCpu = { - CpuFlushCpuDataCache, - CpuEnableInterrupt, - CpuDisableInterrupt, - CpuGetInterruptState, - CpuInit, - CpuRegisterInterruptHandler, - CpuGetTimerValue, - CpuSetMemoryAttributes, - 0, // NumberOfTimers - 4, // DmaBufferAlignment -}; - -EFI_STATUS -CpuDxeInitialize ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - EFI_EVENT IdleLoopEvent; - - InitializeExceptions (&mCpu); - - Status = gBS->InstallMultipleProtocolInterfaces ( - &mCpuHandle, - &gEfiCpuArchProtocolGuid, &mCpu, - &gVirtualUncachedPagesProtocolGuid, &gVirtualUncachedPages, - NULL - ); - - // - // Make sure GCD and MMU settings match. This API calls gDS->SetMemorySpaceAttributes () - // and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go - // after the protocol is installed - // - SyncCacheConfig (&mCpu); - - // If the platform is a MPCore system then install the Configuration Table describing the - // secondary core states - if (ArmIsMpCore()) { - PublishArmProcessorTable(); - } - - // - // Setup a callback for idle events - // - Status = gBS->CreateEventEx ( - EVT_NOTIFY_SIGNAL, - TPL_NOTIFY, - IdleLoopEventCallback, - NULL, - &gIdleLoopEventGuid, - &IdleLoopEvent - ); - ASSERT_EFI_ERROR (Status); - - return Status; -} diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.h b/ArmPkg/Drivers/CpuDxe/CpuDxe.h deleted file mode 100644 index d16abe400e..0000000000 --- a/ArmPkg/Drivers/CpuDxe/CpuDxe.h +++ /dev/null @@ -1,182 +0,0 @@ -/** @file - - Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
- Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#ifndef __CPU_DXE_ARM_EXCEPTION_H__ -#define __CPU_DXE_ARM_EXCEPTION_H__ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - - -#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | \ - EFI_MEMORY_WC | \ - EFI_MEMORY_WT | \ - EFI_MEMORY_WB | \ - EFI_MEMORY_UCE \ - ) - - -/** - This function registers and enables the handler specified by InterruptHandler for a processor - interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the - handler for the processor interrupt or exception type specified by InterruptType is uninstalled. - The installed handler is called once for each processor interrupt or exception. - - @param InterruptType A pointer to the processor's current interrupt state. Set to TRUE if interrupts - are enabled and FALSE if interrupts are disabled. - @param InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called - when a processor interrupt occurs. If this parameter is NULL, then the handler - will be uninstalled. - - @retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled. - @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was - previously installed. - @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not - previously installed. - @retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported. - -**/ -EFI_STATUS -RegisterInterruptHandler ( - IN EFI_EXCEPTION_TYPE InterruptType, - IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler - ); - - -/** - This function registers and enables the handler specified by InterruptHandler for a processor - interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the - handler for the processor interrupt or exception type specified by InterruptType is uninstalled. - The installed handler is called once for each processor interrupt or exception. - - @param InterruptType A pointer to the processor's current interrupt state. Set to TRUE if interrupts - are enabled and FALSE if interrupts are disabled. - @param InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called - when a processor interrupt occurs. If this parameter is NULL, then the handler - will be uninstalled. - - @retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled. - @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was - previously installed. - @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not - previously installed. - @retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported. - -**/ -EFI_STATUS -RegisterDebuggerInterruptHandler ( - IN EFI_EXCEPTION_TYPE InterruptType, - IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler - ); - - -EFI_STATUS -EFIAPI -CpuSetMemoryAttributes ( - IN EFI_CPU_ARCH_PROTOCOL *This, - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes - ); - -EFI_STATUS -InitializeExceptions ( - IN EFI_CPU_ARCH_PROTOCOL *Cpu - ); - -EFI_STATUS -SyncCacheConfig ( - IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol - ); - -EFI_STATUS -ConvertSectionToPages ( - IN EFI_PHYSICAL_ADDRESS BaseAddress - ); - -/** - * Publish ARM Processor Data table in UEFI SYSTEM Table. - * @param HobStart Pointer to the beginning of the HOB List from PEI. - * - * Description : This function iterates through HOB list and finds ARM processor Table Entry HOB. - * If the ARM processor Table Entry HOB is found, the HOB data is copied to run-time memory - * and a pointer is assigned to it in ARM processor table. Then the ARM processor table is - * installed in EFI configuration table. -**/ -VOID -EFIAPI -PublishArmProcessorTable( - VOID - ); - -EFI_STATUS -SetMemoryAttributes ( - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes, - IN EFI_PHYSICAL_ADDRESS VirtualMask - ); - -// The ARM Attributes might be defined on 64-bit (case of the long format description table) -UINT64 -EfiAttributeToArmAttribute ( - IN UINT64 EfiAttributes - ); - -EFI_STATUS -GetMemoryRegion ( - IN OUT UINTN *BaseAddress, - OUT UINTN *RegionLength, - OUT UINTN *RegionAttributes - ); - -VOID -GetRootTranslationTableInfo ( - IN UINTN T0SZ, - OUT UINTN *TableLevel, - OUT UINTN *TableEntryCount - ); - -EFI_STATUS -SetGcdMemorySpaceAttributes ( - IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap, - IN UINTN NumberOfDescriptors, - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes - ); - -extern VIRTUAL_UNCACHED_PAGES_PROTOCOL gVirtualUncachedPages; - -#endif // __CPU_DXE_ARM_EXCEPTION_H__ diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.inf b/ArmPkg/Drivers/CpuDxe/CpuDxe.inf deleted file mode 100644 index 01f65a3655..0000000000 --- a/ArmPkg/Drivers/CpuDxe/CpuDxe.inf +++ /dev/null @@ -1,93 +0,0 @@ -#/** @file -# -# DXE CPU driver -# -# Copyright (c) 2009, Apple Inc. All rights reserved.
-# Copyright (c) 2011-2013, ARM Limited. All rights reserved. -# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -#**/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = ArmCpuDxe - FILE_GUID = B8D9777E-D72A-451F-9BDB-BAFB52A68415 - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - - ENTRY_POINT = CpuDxeInitialize - -[Sources.Common] - CpuDxe.c - CpuDxe.h - CpuMpCore.c - CpuMmuCommon.c - -# -# Prior to ARMv6 we have multiple stacks, one per mode -# -# ArmV4/ExceptionSupport.asm | RVCT -# ArmV4/ExceptionSupport.S | GCC - -# -# ARMv6 or later uses a single stack via srs/stm instructions -# - -[Sources.ARM] - ArmV6/Mmu.c - ArmV6/Exception.c - ArmV6/ExceptionSupport.asm | RVCT - ArmV6/ExceptionSupport.S | GCC - -[Sources.AARCH64] - AArch64/Mmu.c - AArch64/Exception.c - AArch64/ExceptionSupport.S - -[Packages] - ArmPkg/ArmPkg.dec - EmbeddedPkg/EmbeddedPkg.dec - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - -[LibraryClasses] - ArmLib - BaseMemoryLib - CacheMaintenanceLib - CpuLib - DebugLib - DefaultExceptionHandlerLib - DxeServicesTableLib - HobLib - PeCoffGetEntryPointLib - UefiDriverEntryPoint - UefiLib - -[Protocols] - gEfiCpuArchProtocolGuid - gEfiDebugSupportPeriodicCallbackProtocolGuid - gVirtualUncachedPagesProtocolGuid - -[Guids] - gEfiDebugImageInfoTableGuid - gArmMpCoreInfoGuid - gIdleLoopEventGuid - -[Pcd.common] - gArmTokenSpaceGuid.PcdVFPEnabled - gArmTokenSpaceGuid.PcdCpuVectorBaseAddress - -[FeaturePcd.common] - gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport - gArmTokenSpaceGuid.PcdRelocateVectorTable - gArmTokenSpaceGuid.PcdDebuggerExceptionSupport - -[Depex] - TRUE diff --git a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c deleted file mode 100644 index 723604d1df..0000000000 --- a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c +++ /dev/null @@ -1,282 +0,0 @@ -/** @file -* -* Copyright (c) 2013, ARM Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#include "CpuDxe.h" - -/** - Searches memory descriptors covered by given memory range. - - This function searches into the Gcd Memory Space for descriptors - (from StartIndex to EndIndex) that contains the memory range - specified by BaseAddress and Length. - - @param MemorySpaceMap Gcd Memory Space Map as array. - @param NumberOfDescriptors Number of descriptors in map. - @param BaseAddress BaseAddress for the requested range. - @param Length Length for the requested range. - @param StartIndex Start index into the Gcd Memory Space Map. - @param EndIndex End index into the Gcd Memory Space Map. - - @retval EFI_SUCCESS Search successfully. - @retval EFI_NOT_FOUND The requested descriptors does not exist. - -**/ -EFI_STATUS -SearchGcdMemorySpaces ( - IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap, - IN UINTN NumberOfDescriptors, - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - OUT UINTN *StartIndex, - OUT UINTN *EndIndex - ) -{ - UINTN Index; - - *StartIndex = 0; - *EndIndex = 0; - for (Index = 0; Index < NumberOfDescriptors; Index++) { - if ((BaseAddress >= MemorySpaceMap[Index].BaseAddress) && - (BaseAddress < (MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length))) { - *StartIndex = Index; - } - if (((BaseAddress + Length - 1) >= MemorySpaceMap[Index].BaseAddress) && - ((BaseAddress + Length - 1) < (MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length))) { - *EndIndex = Index; - return EFI_SUCCESS; - } - } - return EFI_NOT_FOUND; -} - - -/** - Sets the attributes for a specified range in Gcd Memory Space Map. - - This function sets the attributes for a specified range in - Gcd Memory Space Map. - - @param MemorySpaceMap Gcd Memory Space Map as array - @param NumberOfDescriptors Number of descriptors in map - @param BaseAddress BaseAddress for the range - @param Length Length for the range - @param Attributes Attributes to set - - @retval EFI_SUCCESS Memory attributes set successfully - @retval EFI_NOT_FOUND The specified range does not exist in Gcd Memory Space - -**/ -EFI_STATUS -SetGcdMemorySpaceAttributes ( - IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap, - IN UINTN NumberOfDescriptors, - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 Attributes - ) -{ - EFI_STATUS Status; - UINTN Index; - UINTN StartIndex; - UINTN EndIndex; - EFI_PHYSICAL_ADDRESS RegionStart; - UINT64 RegionLength; - - DEBUG ((DEBUG_GCD, "SetGcdMemorySpaceAttributes[0x%lX; 0x%lX] = 0x%lX\n", - BaseAddress, BaseAddress + Length, Attributes)); - - // We do not support a smaller granularity than 4KB on ARM Architecture - if ((Length & EFI_PAGE_MASK) != 0) { - DEBUG ((DEBUG_WARN, - "Warning: We do not support smaller granularity than 4KB on ARM Architecture (passed length: 0x%lX).\n", - Length)); - } - - // - // Get all memory descriptors covered by the memory range - // - Status = SearchGcdMemorySpaces ( - MemorySpaceMap, - NumberOfDescriptors, - BaseAddress, - Length, - &StartIndex, - &EndIndex - ); - if (EFI_ERROR (Status)) { - return Status; - } - - // - // Go through all related descriptors and set attributes accordingly - // - for (Index = StartIndex; Index <= EndIndex; Index++) { - if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) { - continue; - } - // - // Calculate the start and end address of the overlapping range - // - if (BaseAddress >= MemorySpaceMap[Index].BaseAddress) { - RegionStart = BaseAddress; - } else { - RegionStart = MemorySpaceMap[Index].BaseAddress; - } - if ((BaseAddress + Length - 1) < (MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length)) { - RegionLength = BaseAddress + Length - RegionStart; - } else { - RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart; - } - // - // Set memory attributes according to MTRR attribute and the original attribute of descriptor - // - gDS->SetMemorySpaceAttributes ( - RegionStart, - RegionLength, - (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes) - ); - } - - return EFI_SUCCESS; -} - -/** - This function modifies the attributes for the memory region specified by BaseAddress and - Length from their current attributes to the attributes specified by Attributes. - - @param This The EFI_CPU_ARCH_PROTOCOL instance. - @param BaseAddress The physical address that is the start address of a memory region. - @param Length The size in bytes of the memory region. - @param Attributes The bit mask of attributes to set for the memory region. - - @retval EFI_SUCCESS The attributes were set for the memory region. - @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by - BaseAddress and Length cannot be modified. - @retval EFI_INVALID_PARAMETER Length is zero. - @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of - the memory resource range. - @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory - resource range specified by BaseAddress and Length. - The bit mask of attributes is not support for the memory resource - range specified by BaseAddress and Length. - -**/ -EFI_STATUS -EFIAPI -CpuSetMemoryAttributes ( - IN EFI_CPU_ARCH_PROTOCOL *This, - IN EFI_PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN UINT64 EfiAttributes - ) -{ - EFI_STATUS Status; - UINTN ArmAttributes; - UINTN RegionBaseAddress; - UINTN RegionLength; - UINTN RegionArmAttributes; - - if ((BaseAddress & (SIZE_4KB - 1)) != 0) { - // Minimum granularity is SIZE_4KB (4KB on ARM) - DEBUG ((EFI_D_PAGE, "CpuSetMemoryAttributes(%lx, %lx, %lx): Minimum ganularity is SIZE_4KB\n", BaseAddress, Length, EfiAttributes)); - return EFI_UNSUPPORTED; - } - - // Convert the 'Attribute' into ARM Attribute - ArmAttributes = EfiAttributeToArmAttribute (EfiAttributes); - - // Get the region starting from 'BaseAddress' and its 'Attribute' - RegionBaseAddress = BaseAddress; - Status = GetMemoryRegion (&RegionBaseAddress, &RegionLength, &RegionArmAttributes); - - // Data & Instruction Caches are flushed when we set new memory attributes. - // So, we only set the attributes if the new region is different. - if (EFI_ERROR (Status) || (RegionArmAttributes != ArmAttributes) || - ((BaseAddress + Length) > (RegionBaseAddress + RegionLength))) - { - return SetMemoryAttributes (BaseAddress, Length, EfiAttributes, 0); - } else { - return EFI_SUCCESS; - } -} - -EFI_STATUS -EFIAPI -CpuConvertPagesToUncachedVirtualAddress ( - IN VIRTUAL_UNCACHED_PAGES_PROTOCOL *This, - IN EFI_PHYSICAL_ADDRESS Address, - IN UINTN Length, - IN EFI_PHYSICAL_ADDRESS VirtualMask, - OUT UINT64 *Attributes OPTIONAL - ) -{ - EFI_STATUS Status; - EFI_GCD_MEMORY_SPACE_DESCRIPTOR GcdDescriptor; - - if (Attributes != NULL) { - Status = gDS->GetMemorySpaceDescriptor (Address, &GcdDescriptor); - if (!EFI_ERROR (Status)) { - *Attributes = GcdDescriptor.Attributes; - } - } - - // - // Make this address range page fault if accessed. If it is a DMA buffer than this would - // be the PCI address. Code should always use the CPU address, and we will or in VirtualMask - // to that address. - // - Status = SetMemoryAttributes (Address, Length, EFI_MEMORY_WP, 0); - if (!EFI_ERROR (Status)) { - Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_UC, VirtualMask); - } - - DEBUG ((DEBUG_INFO | DEBUG_LOAD, "CpuConvertPagesToUncachedVirtualAddress()\n Unmapped 0x%08lx Mapped 0x%08lx 0x%x bytes\n", Address, Address | VirtualMask, Length)); - - return Status; -} - - -EFI_STATUS -EFIAPI -CpuReconvertPages ( - IN VIRTUAL_UNCACHED_PAGES_PROTOCOL *This, - IN EFI_PHYSICAL_ADDRESS Address, - IN UINTN Length, - IN EFI_PHYSICAL_ADDRESS VirtualMask, - IN UINT64 Attributes - ) -{ - EFI_STATUS Status; - - DEBUG ((DEBUG_INFO | DEBUG_LOAD, "CpuReconvertPages(%lx, %x, %lx, %lx)\n", Address, Length, VirtualMask, Attributes)); - - // - // Unmap the aliased Address - // - Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_WP, 0); - if (!EFI_ERROR (Status)) { - // - // Restore atttributes - // - Status = SetMemoryAttributes (Address, Length, Attributes, 0); - } - - return Status; -} - - -VIRTUAL_UNCACHED_PAGES_PROTOCOL gVirtualUncachedPages = { - CpuConvertPagesToUncachedVirtualAddress, - CpuReconvertPages -}; diff --git a/ArmPkg/Drivers/CpuDxe/CpuMpCore.c b/ArmPkg/Drivers/CpuDxe/CpuMpCore.c deleted file mode 100644 index 81d858ea25..0000000000 --- a/ArmPkg/Drivers/CpuDxe/CpuMpCore.c +++ /dev/null @@ -1,103 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2014, ARM Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#include -#include -#include -#include -#include - -#include - -ARM_PROCESSOR_TABLE mArmProcessorTableTemplate = { - { - EFI_ARM_PROCESSOR_TABLE_SIGNATURE, - 0, - EFI_ARM_PROCESSOR_TABLE_REVISION, - EFI_ARM_PROCESSOR_TABLE_OEM_ID, - EFI_ARM_PROCESSOR_TABLE_OEM_TABLE_ID, - EFI_ARM_PROCESSOR_TABLE_OEM_REVISION, - EFI_ARM_PROCESSOR_TABLE_CREATOR_ID, - EFI_ARM_PROCESSOR_TABLE_CREATOR_REVISION, - { 0 }, - 0 - }, //ARM Processor table header - 0, // Number of entries in ARM processor Table - NULL // ARM Processor Table -}; - -/** Publish ARM Processor Data table in UEFI SYSTEM Table. - * @param: HobStart Pointer to the beginning of the HOB List from PEI. - * - * Description : This function iterates through HOB list and finds ARM processor Table Entry HOB. - * If the ARM processor Table Entry HOB is found, the HOB data is copied to run-time memory - * and a pointer is assigned to it in ARM processor table. Then the ARM processor table is - * installed in EFI configuration table. -**/ -VOID -EFIAPI -PublishArmProcessorTable ( - VOID - ) -{ - EFI_PEI_HOB_POINTERS Hob; - - Hob.Raw = GetHobList (); - - // Iterate through the HOBs and find if there is ARM PROCESSOR ENTRY HOB - for (; !END_OF_HOB_LIST(Hob); Hob.Raw = GET_NEXT_HOB(Hob)) { - // Check for Correct HOB type - if ((GET_HOB_TYPE (Hob)) == EFI_HOB_TYPE_GUID_EXTENSION) { - // Check for correct GUID type - if (CompareGuid(&(Hob.Guid->Name), &gArmMpCoreInfoGuid)) { - ARM_PROCESSOR_TABLE *ArmProcessorTable; - EFI_STATUS Status; - - // Allocate Runtime memory for ARM processor table - ArmProcessorTable = (ARM_PROCESSOR_TABLE*)AllocateRuntimePool(sizeof(ARM_PROCESSOR_TABLE)); - - // Check if the memory allocation is succesful or not - ASSERT(NULL != ArmProcessorTable); - - // Set ARM processor table to default values - CopyMem(ArmProcessorTable,&mArmProcessorTableTemplate,sizeof(ARM_PROCESSOR_TABLE)); - - // Fill in Length fields of ARM processor table - ArmProcessorTable->Header.Length = sizeof(ARM_PROCESSOR_TABLE); - ArmProcessorTable->Header.DataLen = GET_GUID_HOB_DATA_SIZE(Hob); - - // Fill in Identifier(ARM processor table GUID) - ArmProcessorTable->Header.Identifier = gArmMpCoreInfoGuid; - - // Set Number of ARM core entries in the Table - ArmProcessorTable->NumberOfEntries = GET_GUID_HOB_DATA_SIZE(Hob)/sizeof(ARM_CORE_INFO); - - // Allocate runtime memory for ARM processor Table entries - ArmProcessorTable->ArmCpus = (ARM_CORE_INFO*)AllocateRuntimePool ( - ArmProcessorTable->NumberOfEntries * sizeof(ARM_CORE_INFO)); - - // Check if the memory allocation is succesful or not - ASSERT(NULL != ArmProcessorTable->ArmCpus); - - // Copy ARM Processor Table data from HOB list to newly allocated memory - CopyMem(ArmProcessorTable->ArmCpus,GET_GUID_HOB_DATA(Hob), ArmProcessorTable->Header.DataLen); - - // Install the ARM Processor table into EFI system configuration table - Status = gBS->InstallConfigurationTable (&gArmMpCoreInfoGuid, ArmProcessorTable); - - ASSERT_EFI_ERROR (Status); - } - } - } -} -- cgit v1.2.3