From 9d59a88be171f74ae08ad63b3e8d1b77a87522e8 Mon Sep 17 00:00:00 2001
From: oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524>
Date: Wed, 2 May 2012 20:14:55 +0000
Subject: ArmPkg/ArmCpuLib: Fixed SMP Cortex-A9 and Cortex-A15

Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13261 6f19259b-4bc3-4df7-8a09-765794883524
---
 ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.c | 11 +++++------
 ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.c   |  5 +++--
 2 files changed, 8 insertions(+), 8 deletions(-)

(limited to 'ArmPkg/Drivers')

diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.c b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.c
index 9b64d662d9..95ab073e18 100644
--- a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.c
+++ b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.c
@@ -20,7 +20,7 @@
 #include <Library/IoLib.h>
 #include <Library/PcdLib.h>
 
-#include <Chipset/ArmV7.h>
+#include <Chipset/ArmCortexA15.h>
 
 VOID
 ArmCpuSetup (
@@ -41,10 +41,11 @@ ArmCpuSetup (
   // if security extensions are implemented.
   ArmArchTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
 
-  /*// If MPCore then Enable the SCU
   if (ArmIsMpCore()) {
-    ArmEnableScu ();
-  }*/
+    // Turn on SMP coherency
+    ArmSetAuxCrBit (A15_FEATURE_SMP);
+  }
+
 }
 
 
@@ -53,8 +54,6 @@ ArmCpuSetupSmpNonSecure (
   IN  UINTN         MpId
   )
 {
-  //ArmSetAuxCrBit (A15_FEATURE_SMP);
-
   /*// Make the SCU accessible in Non Secure world
   if (IS_PRIMARY_CORE(MpId)) {
     ScuBase = ArmGetScuBaseAddress();
diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.c b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.c
index 324ddb5850..8d9530cee2 100644
--- a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.c
+++ b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.c
@@ -48,6 +48,9 @@ ArmCpuSetup (
 
   // If MPCore then Enable the SCU
   if (ArmIsMpCore()) {
+    // Signals the Cortex-A9 processor is taking part in coherency
+    ArmSetAuxCrBit (A9_FEATURE_SMP);
+
     ArmEnableScu ();
   }
 }
@@ -60,8 +63,6 @@ ArmCpuSetupSmpNonSecure (
 {
   INTN          ScuBase;
 
-  ArmSetAuxCrBit (A9_FEATURE_SMP);
-
   // Make the SCU accessible in Non Secure world
   if (IS_PRIMARY_CORE(MpId)) {
     ScuBase = ArmGetScuBaseAddress();
-- 
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