From 6ea34e3a459733d3c27617dfb1cee2d841193ca2 Mon Sep 17 00:00:00 2001
From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Date: Tue, 14 Apr 2015 11:54:40 +0000
Subject: ArmPkg: remove cache maintenance by VA operation range size threshold

This removes the range size threshold for virtual address based cache
maintenance instructions that operate on VA ranges to be 'promoted' to
use set/way instructions.

Doing so is unsafe: set/way operations are fundamentally different
from VA operations, and really only suitable for cleaning or invalidating
a cache when turning it on or off.

To quote the ARM ARM (DDI0487A_d G3.4):
"""
Since the set/way instructions are performed only locally, there is no
guarantee of the atomicity of cache maintenance between different PEs,
even if those different PEs are each performing the same cache maintenance
instructions at the same time. Since any cacheable line can be allocated
into the cache at any time, it is possible for [a] cache line to migrate
from an entry in the cache of one PE to the cache of a different PE in a
manner that the cache line avoids being affected by set/way based cache
maintenance. Therefore, ARM strongly discourages the use of set/way
instructions to manage coherency in coherent systems.
"""

Contributed-under: TianoCore Contribution Agreement 1.0
Reviewed-by: Olivier Martin <Olivier.Martin@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17176 6f19259b-4bc3-4df7-8a09-765794883524
---
 .../ArmCacheMaintenanceLib.c                       | 29 ++++++++--------------
 .../ArmCacheMaintenanceLib.inf                     |  3 ---
 2 files changed, 11 insertions(+), 21 deletions(-)

(limited to 'ArmPkg/Library/ArmCacheMaintenanceLib')

diff --git a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
index 8501e5c613..d8e53df609 100644
--- a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
+++ b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
@@ -20,27 +20,20 @@ VOID
 CacheRangeOperation (
   IN  VOID            *Start,
   IN  UINTN           Length,
-  IN  CACHE_OPERATION CacheOperation,
   IN  LINE_OPERATION  LineOperation
   )
 {
   UINTN ArmCacheLineLength         = ArmDataCacheLineLength();
   UINTN ArmCacheLineAlignmentMask  = ArmCacheLineLength - 1;
-  UINTN ArmCacheOperationThreshold = PcdGet32(PcdArmCacheOperationThreshold);
 
-  if ((CacheOperation != NULL) && (Length >= ArmCacheOperationThreshold)) {
-    ArmDrainWriteBuffer ();
-    CacheOperation ();
-  } else {
-    // Align address (rounding down)
-    UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
-    UINTN EndAddress     = (UINTN)Start + Length;
+  // Align address (rounding down)
+  UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
+  UINTN EndAddress     = (UINTN)Start + Length;
 
-    // Perform the line operation on an address in each cache line
-    while (AlignedAddress < EndAddress) {
-      LineOperation(AlignedAddress);
-      AlignedAddress += ArmCacheLineLength;
-    }
+  // Perform the line operation on an address in each cache line
+  while (AlignedAddress < EndAddress) {
+    LineOperation(AlignedAddress);
+    AlignedAddress += ArmCacheLineLength;
   }
 }
 
@@ -70,7 +63,7 @@ InvalidateInstructionCacheRange (
   IN      UINTN                     Length
   )
 {
-  CacheRangeOperation (Address, Length, ArmCleanDataCacheToPoU, ArmCleanDataCacheEntryByMVA);
+  CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryByMVA);
   ArmInvalidateInstructionCache ();
   return Address;
 }
@@ -91,7 +84,7 @@ WriteBackInvalidateDataCacheRange (
   IN      UINTN                     Length
   )
 {
-  CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCache, ArmCleanInvalidateDataCacheEntryByMVA);
+  CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCacheEntryByMVA);
   return Address;
 }
 
@@ -111,7 +104,7 @@ WriteBackDataCacheRange (
   IN      UINTN                     Length
   )
 {
-  CacheRangeOperation(Address, Length, ArmCleanDataCache, ArmCleanDataCacheEntryByMVA);
+  CacheRangeOperation(Address, Length, ArmCleanDataCacheEntryByMVA);
   return Address;
 }
 
@@ -122,6 +115,6 @@ InvalidateDataCacheRange (
   IN      UINTN                     Length
   )
 {
-  CacheRangeOperation(Address, Length, NULL, ArmInvalidateDataCacheEntryByMVA);
+  CacheRangeOperation(Address, Length, ArmInvalidateDataCacheEntryByMVA);
   return Address;
 }
diff --git a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
index 5910db09d6..d519972942 100644
--- a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+++ b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
@@ -31,6 +31,3 @@
 [LibraryClasses]
   ArmLib
   BaseLib
-
-[FixedPcd]
-  gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
-- 
cgit v1.2.3