From f94522c823610a4b44486835aca195c267bd3953 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Tue, 28 Jul 2015 20:45:10 +0000 Subject: ArmPkg: cache detected revision in ArmGicArchLib Instead of inferring the GIC revision from the CPU id registers and the presence/availability of the system register interface upon each invocation, move the logic to a constructor and cache the result. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Laszlo Ersek Reviewed-by: Leif Lindholm Tested-by: Leif Lindholm git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18100 6f19259b-4bc3-4df7-8a09-765794883524 --- .../Library/ArmGicArchLib/AArch64/ArmGicArchLib.c | 23 ++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) (limited to 'ArmPkg/Library/ArmGicArchLib/AArch64/ArmGicArchLib.c') diff --git a/ArmPkg/Library/ArmGicArchLib/AArch64/ArmGicArchLib.c b/ArmPkg/Library/ArmGicArchLib/AArch64/ArmGicArchLib.c index 0e0fa3b9f3..9853c7ba85 100644 --- a/ArmPkg/Library/ArmGicArchLib/AArch64/ArmGicArchLib.c +++ b/ArmPkg/Library/ArmGicArchLib/AArch64/ArmGicArchLib.c @@ -15,9 +15,11 @@ #include #include -ARM_GIC_ARCH_REVISION +STATIC ARM_GIC_ARCH_REVISION mGicArchRevision; + +RETURN_STATUS EFIAPI -ArmGicGetSupportedArchRevision ( +ArmGicArchLibInitialize ( VOID ) { @@ -43,9 +45,22 @@ ArmGicGetSupportedArchRevision ( IccSre = ArmGicV3GetControlSystemRegisterEnable (); } if (IccSre & ICC_SRE_EL2_SRE) { - return ARM_GIC_ARCH_REVISION_3; + mGicArchRevision = ARM_GIC_ARCH_REVISION_3; + goto Done; } } - return ARM_GIC_ARCH_REVISION_2; + mGicArchRevision = ARM_GIC_ARCH_REVISION_2; + +Done: + return RETURN_SUCCESS; +} + +ARM_GIC_ARCH_REVISION +EFIAPI +ArmGicGetSupportedArchRevision ( + VOID + ) +{ + return mGicArchRevision; } -- cgit v1.2.3