From bb02cb8071e9df25cbcae15a9afa70d6387320cb Mon Sep 17 00:00:00 2001 From: andrewfish Date: Tue, 13 Apr 2010 19:27:03 +0000 Subject: Cleanup MMU code to do book required sync. Update exception handler to clear fault registers. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10366 6f19259b-4bc3-4df7-8a09-765794883524 --- ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.S | 38 +++++++++++++++++++++++++---- 1 file changed, 33 insertions(+), 5 deletions(-) (limited to 'ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.S') diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.S b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.S index cdfd3dc9cf..9932e1462b 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.S +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.S @@ -1,6 +1,6 @@ #------------------------------------------------------------------------------ # -# Copyright (c) 2008-2009 Apple Inc. All rights reserved. +# Copyright (c) 2008-2010 Apple Inc. All rights reserved. # # All rights reserved. This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -12,8 +12,6 @@ # #------------------------------------------------------------------------------ -.text -.align 2 .globl ASM_PFX(Cp15IdCode) .globl ASM_PFX(Cp15CacheInfo) .globl ASM_PFX(ArmEnableInterrupts) @@ -26,11 +24,14 @@ .globl ASM_PFX(ArmSetTranslationTableBaseAddress) .globl ASM_PFX(ArmGetTranslationTableBaseAddress) .globl ASM_PFX(ArmSetDomainAccessControl) +.globl ASM_PFX(ArmUpdateTranslationTableEntry) .globl ASM_PFX(CPSRMaskInsert) .globl ASM_PFX(CPSRRead) .globl ASM_PFX(ReadCCSIDR) .globl ASM_PFX(ReadCLIDR) +.text +.align 2 #------------------------------------------------------------------------------ @@ -67,7 +68,7 @@ ASM_PFX(ArmDisableFiq): ASM_PFX(ArmGetFiqState): mrs R0,CPSR - tst R0,#0x30 @Check if IRQ is enabled. + tst R0,#0x40 @Check if FIQ is enabled. moveq R0,#1 movne R0,#0 bx LR @@ -75,6 +76,8 @@ ASM_PFX(ArmGetFiqState): ASM_PFX(ArmInvalidateTlb): mov r0,#0 mcr p15,0,r0,c8,c7,0 + mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp + dsb isb bx lr @@ -85,6 +88,7 @@ ASM_PFX(ArmSetTranslationTableBaseAddress): ASM_PFX(ArmGetTranslationTableBaseAddress): mrc p15,0,r0,c2,c0,0 + isb bx lr @@ -93,6 +97,21 @@ ASM_PFX(ArmSetDomainAccessControl): isb bx lr +// +//VOID +//ArmUpdateTranslationTableEntry ( +// IN VOID *TranslationTableEntry // R0 +// IN VOID *MVA // R1 +// ); +ASM_PFX(ArmUpdateTranslationTableEntry): + mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA + dsb + mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA + mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp + dsb + isb + bx lr + ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert stmfd sp!, {r4-r12, lr} @ save all the banked registers mov r3, sp @ copy the stack pointer into a non-banked register @@ -101,6 +120,7 @@ ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to in and r1, r1, r0 @ clear bits outside the mask in the input orr r2, r2, r1 @ set field msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch) + isb mov sp, r3 @ restore stack pointer ldmfd sp!, {r4-r12, lr} @ restore registers bx lr @ return (hopefully thumb-safe!) @@ -109,14 +129,22 @@ ASM_PFX(CPSRRead): mrs r0, cpsr bx lr +// UINT32 +// ReadCCSIDR ( +// IN UINT32 CSSELR +// ) ASM_PFX(ReadCCSIDR): mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR) isb mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR) bx lr - +// UINT32 +// ReadCLIDR ( +// IN UINT32 CSSELR +// ) ASM_PFX(ReadCLIDR): mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register + bx lr ASM_FUNCTION_REMOVE_IF_UNREFERENCED -- cgit v1.2.3