From 3402aac7d985bf8a9f9d3c639f3fe93609380513 Mon Sep 17 00:00:00 2001 From: Ronald Cron Date: Tue, 19 Aug 2014 13:29:52 +0000 Subject: ARM Packages: Removed trailing spaces Trailing spaces create issue/warning when generating/applying patches. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron Reviewed-By: Olivier Martin git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15833 6f19259b-4bc3-4df7-8a09-765794883524 --- ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S | 14 +++---- ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm | 14 +++---- ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimer.c | 14 +++---- .../Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.S | 2 +- .../Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.asm | 2 +- ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c | 48 +++++++++++----------- ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.h | 2 +- ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf | 6 +-- ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf | 8 ++-- ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf | 18 ++++---- ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c | 32 +++++++-------- ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S | 42 +++++++++---------- ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm | 46 ++++++++++----------- 13 files changed, 124 insertions(+), 124 deletions(-) (limited to 'ArmPkg/Library/ArmLib/ArmV7') diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S index 5ee8b25675..333827a992 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S @@ -1,4 +1,4 @@ -#------------------------------------------------------------------------------ +#------------------------------------------------------------------------------ # # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
# Copyright (c) 2011-2013, ARM Limited. All rights reserved. @@ -81,21 +81,21 @@ ASM_PFX(ArmDisableInterrupts): cpsid if isb bx LR - -// UINT32 + +// UINT32 // ReadCCSIDR ( // IN UINT32 CSSELR -// ) +// ) ASM_PFX(ReadCCSIDR): mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR) isb mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR) bx lr - -// UINT32 + +// UINT32 // ReadCLIDR ( // IN UINT32 CSSELR -// ) +// ) ASM_PFX(ReadCLIDR): mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register bx lr diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm index 6af662bda5..d60d4ed213 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm @@ -1,4 +1,4 @@ -//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ // // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
// Copyright (c) 2011-2013, ARM Limited. All rights reserved. @@ -80,21 +80,21 @@ ArmDisableInterrupts cpsid if isb bx LR - -// UINT32 + +// UINT32 // ReadCCSIDR ( // IN UINT32 CSSELR -// ) +// ) ReadCCSIDR mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR) isb mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR) bx lr - -// UINT32 + +// UINT32 // ReadCLIDR ( // IN UINT32 CSSELR -// ) +// ) ReadCLIDR mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register bx lr diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimer.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimer.c index fd82ef927b..79083f56b7 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimer.c +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimer.c @@ -1,14 +1,14 @@ /** @file * * Copyright (c) 2011 - 2014, ARM Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php * -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. * **/ diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.S index 531d8fd1e0..ec4ede5250 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.S +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.S @@ -1,4 +1,4 @@ -#------------------------------------------------------------------------------ +#------------------------------------------------------------------------------ # # Copyright (c) 2011, ARM Limited. All rights reserved. # diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.asm index fc0be1966b..514830d28f 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.asm +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.asm @@ -1,4 +1,4 @@ -//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ // // Copyright (c) 2011, ARM Limited. All rights reserved. // diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c index 65709780ed..feb60881bd 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c @@ -2,7 +2,7 @@ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
Copyright (c) 2011 - 2014, ARM Limited. All rights reserved. - + This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -47,7 +47,7 @@ ArmDataCachePresent ( ) { UINT32 CLIDR = ReadCLIDR (); - + if ((CLIDR & 0x2) == 0x2) { // Instruction cache exists return TRUE; @@ -56,10 +56,10 @@ ArmDataCachePresent ( // Unified cache return TRUE; } - + return FALSE; } - + UINTN EFIAPI ArmDataCacheSize ( @@ -70,15 +70,15 @@ ArmDataCacheSize ( UINT32 Associativity; UINT32 LineSize; UINT32 CCSIDR = ReadCCSIDR (0); - + LineSize = (1 << ((CCSIDR & 0x7) + 2)); Associativity = ((CCSIDR >> 3) & 0x3ff) + 1; NumSets = ((CCSIDR >> 13) & 0x7fff) + 1; // LineSize is in words (4 byte chunks) - return NumSets * Associativity * LineSize * 4; + return NumSets * Associativity * LineSize * 4; } - + UINTN EFIAPI ArmDataCacheAssociativity ( @@ -89,14 +89,14 @@ ArmDataCacheAssociativity ( return ((CCSIDR >> 3) & 0x3ff) + 1; } - + UINTN ArmDataCacheSets ( VOID ) { UINT32 CCSIDR = ReadCCSIDR (0); - + return ((CCSIDR >> 13) & 0x7fff) + 1; } @@ -111,7 +111,7 @@ ArmDataCacheLineLength ( // * 4 converts to bytes return (1 << (CCSIDR + 2)) * 4; } - + BOOLEAN EFIAPI ArmInstructionCachePresent ( @@ -119,7 +119,7 @@ ArmInstructionCachePresent ( ) { UINT32 CLIDR = ReadCLIDR (); - + if ((CLIDR & 1) == 1) { // Instruction cache exists return TRUE; @@ -128,10 +128,10 @@ ArmInstructionCachePresent ( // Unified cache return TRUE; } - + return FALSE; } - + UINTN EFIAPI ArmInstructionCacheSize ( @@ -142,15 +142,15 @@ ArmInstructionCacheSize ( UINT32 Associativity; UINT32 LineSize; UINT32 CCSIDR = ReadCCSIDR (1); - + LineSize = (1 << ((CCSIDR & 0x7) + 2)); Associativity = ((CCSIDR >> 3) & 0x3ff) + 1; NumSets = ((CCSIDR >> 13) & 0x7fff) + 1; // LineSize is in words (4 byte chunks) - return NumSets * Associativity * LineSize * 4; + return NumSets * Associativity * LineSize * 4; } - + UINTN EFIAPI ArmInstructionCacheAssociativity ( @@ -162,7 +162,7 @@ ArmInstructionCacheAssociativity ( return ((CCSIDR >> 3) & 0x3ff) + 1; // return 4; } - + UINTN EFIAPI ArmInstructionCacheSets ( @@ -170,7 +170,7 @@ ArmInstructionCacheSets ( ) { UINT32 CCSIDR = ReadCCSIDR (1); - + return ((CCSIDR >> 13) & 0x7fff) + 1; } @@ -198,11 +198,11 @@ ArmV7DataCacheOperation ( SavedInterruptState = ArmGetInterruptState (); ArmDisableInterrupts (); - + ArmV7AllDataCachesOperation (DataCacheOperation); - + ArmDrainWriteBuffer (); - + if (SavedInterruptState) { ArmEnableInterrupts (); } @@ -218,11 +218,11 @@ ArmV7PoUDataCacheOperation ( SavedInterruptState = ArmGetInterruptState (); ArmDisableInterrupts (); - + ArmV7PerformPoUDataCacheOperation (DataCacheOperation); - + ArmDrainWriteBuffer (); - + if (SavedInterruptState) { ArmEnableInterrupts (); } diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.h b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.h index f183a1cca3..1398d75071 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.h +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.h @@ -27,6 +27,6 @@ VOID ArmV7AllDataCachesOperation ( IN ARM_V7_CACHE_OPERATION DataCacheOperation ); - + #endif // __ARM_V7_LIB_H__ diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf index ec2a0bae89..55c0ec661a 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf @@ -28,10 +28,10 @@ ../Common/Arm/ArmLibSupport.S | GCC ../Common/Arm/ArmLibSupport.asm | RVCT ../Common/ArmLib.c - + ArmV7Support.S | GCC ArmV7Support.asm | RVCT - + ArmV7Lib.c ArmV7Mmu.c @@ -45,7 +45,7 @@ [LibraryClasses] MemoryAllocationLib - + [Protocols] gEfiCpuArchProtocolGuid diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf b/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf index be5b8e4930..bc403d5613 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf @@ -28,13 +28,13 @@ ../Common/Arm/ArmLibSupport.S | GCC ../Common/Arm/ArmLibSupport.asm | RVCT ../Common/ArmLib.c - + ArmV7Support.S | GCC ArmV7Support.asm | RVCT - + ArmV7Lib.c ArmV7Mmu.c - + ArmV7ArchTimer.c ArmV7ArchTimerSupport.S | GCC ArmV7ArchTimerSupport.asm | RVCT @@ -45,7 +45,7 @@ [LibraryClasses] PrePiLib - + [Protocols] gEfiCpuArchProtocolGuid diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf b/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf index c1f97bb12d..4081d1a3e5 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf @@ -1,13 +1,13 @@ #/* @file # Copyright (c) 2011, ARM Limited. All rights reserved. -# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php # -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. # #*/ @@ -26,12 +26,12 @@ ../Common/Arm/ArmLibSupport.S | GCC ../Common/Arm/ArmLibSupport.asm | RVCT ../Common/ArmLib.c - + ArmV7Support.S | GCC ArmV7Support.asm | RVCT ArmV7Lib.c - + ArmV7ArchTimer.c ArmV7ArchTimerSupport.S | GCC ArmV7ArchTimerSupport.asm | RVCT diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c index 1a5d982022..d035ff3caa 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c @@ -2,18 +2,18 @@ * File managing the MMU for ARMv7 architecture * * Copyright (c) 2011-2013, ARM Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php * -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. * **/ -#include +#include #include #include #include @@ -145,7 +145,7 @@ FillTranslationTable ( UINT32 Attributes; UINT32 PhysicalBase = MemoryRegion->PhysicalBase; UINT32 RemainLength = MemoryRegion->Length; - + ASSERT(MemoryRegion->Length > 0); switch (MemoryRegion->Attributes) { @@ -177,7 +177,7 @@ FillTranslationTable ( Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0); break; } - + // Get the first section entry for this mapping SectionEntry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase); @@ -231,7 +231,7 @@ ArmConfigureMmu ( if (TranslationTableBase != NULL) { *TranslationTableBase = TranslationTable; } - + if (TranslationTableSize != NULL) { *TranslationTableSize = TRANSLATION_TABLE_SECTION_SIZE; } @@ -251,13 +251,13 @@ ArmConfigureMmu ( } // Translate the Memory Attributes into Translation Table Register Attributes - if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) || + if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) || (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED)) { TTBRAttributes = TTBR_NON_CACHEABLE; - } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) || + } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) || (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) { TTBRAttributes = TTBR_WRITE_BACK_ALLOC; - } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) || + } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) || (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH)) { TTBRAttributes = TTBR_WRITE_THROUGH_NO_ALLOC; } else { @@ -278,7 +278,7 @@ ArmConfigureMmu ( ArmInvalidateInstructionCache (); ArmSetTTBR0 ((VOID *)(UINTN)(((UINTN)TranslationTable & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) | (TTBRAttributes & 0x7F))); - + ArmSetDomainAccessControl (DOMAIN_ACCESS_CONTROL_NONE(15) | DOMAIN_ACCESS_CONTROL_NONE(14) | DOMAIN_ACCESS_CONTROL_NONE(13) | @@ -295,7 +295,7 @@ ArmConfigureMmu ( DOMAIN_ACCESS_CONTROL_NONE( 2) | DOMAIN_ACCESS_CONTROL_NONE( 1) | DOMAIN_ACCESS_CONTROL_MANAGER(0)); - + ArmEnableInstructionCache(); ArmEnableDataCache(); ArmEnableMmu(); diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S index 954762717c..c31d49bcfb 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S @@ -1,4 +1,4 @@ -#------------------------------------------------------------------------------ +#------------------------------------------------------------------------------ # # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved. @@ -63,13 +63,13 @@ GCC_ASM_EXPORT (ArmReadIdPfr1) ASM_PFX(ArmInvalidateDataCacheEntryByMVA): - mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line + mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line dsb isb bx lr ASM_PFX(ArmCleanDataCacheEntryByMVA): - mcr p15, 0, r0, c7, c10, 1 @clean single data cache line + mcr p15, 0, r0, c7, c10, 1 @clean single data cache line dsb isb bx lr @@ -83,21 +83,21 @@ ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA): ASM_PFX(ArmInvalidateDataCacheEntryBySetWay): - mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line + mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line dsb isb bx lr ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay): - mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line + mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line dsb isb bx lr ASM_PFX(ArmCleanDataCacheEntryBySetWay): - mcr p15, 0, r0, c7, c10, 2 @ Clean this line + mcr p15, 0, r0, c7, c10, 2 @ Clean this line dsb isb bx lr @@ -141,7 +141,7 @@ ASM_PFX(ArmDisableCachesAndMmu): ASM_PFX(ArmMmuEnabled): mrc p15,0,R0,c1,c0,0 and R0,R0,#1 - bx LR + bx LR ASM_PFX(ArmEnableDataCache): ldr R1,=DC_ON @@ -151,7 +151,7 @@ ASM_PFX(ArmEnableDataCache): dsb isb bx LR - + ASM_PFX(ArmDisableDataCache): ldr R1,=DC_ON mrc p15,0,R0,c1,c0,0 @Read control register configuration data @@ -169,7 +169,7 @@ ASM_PFX(ArmEnableInstructionCache): dsb isb bx LR - + ASM_PFX(ArmDisableInstructionCache): ldr R1,=IC_ON mrc p15,0,R0,c1,c0,0 @Read control register configuration data @@ -225,14 +225,14 @@ ASM_PFX(ArmV7AllDataCachesOperation): beq L_Finished mov R10, #0 -Loop1: +Loop1: add R2, R10, R10, LSR #1 @ Work out 3xcachelevel mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level and R12, R12, #7 @ get those 3 bits alone cmp R12, #2 blt L_Skip @ no cache or only instruction cache at this level mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction - isb @ isb to sync the change to the CacheSizeID reg + isb @ isb to sync the change to the CacheSizeID reg mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR) and R2, R12, #0x7 @ extract the line length field add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes) @@ -246,10 +246,10 @@ Loop1: sub R7, R7, #1 ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned) -Loop2: +Loop2: mov R9, R4 @ R9 working copy of the max way size (right aligned) -Loop3: +Loop3: orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11 orr R0, R0, R7, LSL R2 @ factor in the index number @@ -259,11 +259,11 @@ Loop3: bge Loop3 subs R7, R7, #1 @ decrement the index bge Loop2 -L_Skip: +L_Skip: add R10, R10, #2 @ increment the cache number cmp R3, R10 bgt Loop1 - + L_Finished: dsb ldmfd SP!, {r4-r12, lr} @@ -285,7 +285,7 @@ Loop4: cmp R12, #2 blt Skip2 @ no cache or only instruction cache at this level mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction - isb @ isb to sync the change to the CacheSizeID reg + isb @ isb to sync the change to the CacheSizeID reg mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR) and R2, R12, #0x7 @ extract the line length field add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes) @@ -312,7 +312,7 @@ Skip2: add R10, R10, #2 @ increment the cache number cmp R3, R10 bgt Loop4 - + Finished2: dsb ldmfd SP!, {r4-r12, lr} @@ -321,12 +321,12 @@ Finished2: ASM_PFX(ArmDataMemoryBarrier): dmb bx LR - + ASM_PFX(ArmDataSyncronizationBarrier): ASM_PFX(ArmDrainWriteBuffer): dsb bx LR - + ASM_PFX(ArmInstructionSynchronizationBarrier): isb bx LR @@ -338,7 +338,7 @@ ASM_PFX(ArmReadVBar): ASM_PFX(ArmWriteVBar): # Set the Address of the Vector Table in the VBAR register - mcr p15, 0, r0, c12, c0, 0 + mcr p15, 0, r0, c12, c0, 0 # Ensure the SCTLR.V bit is clear mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data) bic r0, r0, #0x00002000 @ clear V bit @@ -376,7 +376,7 @@ ASM_PFX(ArmInvalidateInstructionAndDataTlb): ASM_PFX(ArmReadMpidr): mrc p15, 0, r0, c0, c0, 5 @ read MPIDR bx lr - + ASM_PFX(ArmReadTpidrurw): mrc p15, 0, r0, c13, c0, 2 @ read TPIDRURW bx lr diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm index 4808c7ba74..368138933a 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm @@ -1,4 +1,4 @@ -//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ // // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved. @@ -63,13 +63,13 @@ CTRL_I_BIT EQU (1 << 12) ArmInvalidateDataCacheEntryByMVA - mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line + mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line dsb isb bx lr ArmCleanDataCacheEntryByMVA - mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line + mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line dsb isb bx lr @@ -83,21 +83,21 @@ ArmCleanInvalidateDataCacheEntryByMVA ArmInvalidateDataCacheEntryBySetWay - mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line + mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line dsb isb bx lr ArmCleanInvalidateDataCacheEntryBySetWay - mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line + mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line dsb isb bx lr ArmCleanDataCacheEntryBySetWay - mcr p15, 0, r0, c7, c10, 2 ; Clean this line + mcr p15, 0, r0, c7, c10, 2 ; Clean this line dsb isb bx lr @@ -150,7 +150,7 @@ ArmEnableDataCache dsb isb bx LR - + ArmDisableDataCache ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) @@ -168,7 +168,7 @@ ArmEnableInstructionCache dsb isb bx LR - + ArmDisableInstructionCache ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) @@ -223,14 +223,14 @@ ArmV7AllDataCachesOperation beq Finished mov R10, #0 -Loop1 +Loop1 add R2, R10, R10, LSR #1 ; Work out 3xcachelevel mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level and R12, R12, #7 ; get those 3 bits alone cmp R12, #2 blt Skip ; no cache or only instruction cache at this level mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction - isb ; isb to sync the change to the CacheSizeID reg + isb ; isb to sync the change to the CacheSizeID reg mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR) and R2, R12, #&7 ; extract the line length field add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes) @@ -240,10 +240,10 @@ Loop1 ldr R7, =0x00007FFF ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned) -Loop2 +Loop2 mov R9, R4 ; R9 working copy of the max way size (right aligned) -Loop3 +Loop3 orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11 orr R0, R0, R7, LSL R2 ; factor in the index number @@ -253,11 +253,11 @@ Loop3 bge Loop3 subs R7, R7, #1 ; decrement the index bge Loop2 -Skip +Skip add R10, R10, #2 ; increment the cache number cmp R3, R10 bgt Loop1 - + Finished dsb ldmfd SP!, {r4-r12, lr} @@ -272,14 +272,14 @@ ArmV7PerformPoUDataCacheOperation beq Finished2 mov R10, #0 -Loop4 +Loop4 add R2, R10, R10, LSR #1 ; Work out 3xcachelevel mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level and R12, R12, #7 ; get those 3 bits alone cmp R12, #2 blt Skip2 ; no cache or only instruction cache at this level mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction - isb ; isb to sync the change to the CacheSizeID reg + isb ; isb to sync the change to the CacheSizeID reg mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR) and R2, R12, #&7 ; extract the line length field add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes) @@ -289,10 +289,10 @@ Loop4 ldr R7, =0x00007FFF ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned) -Loop5 +Loop5 mov R9, R4 ; R9 working copy of the max way size (right aligned) -Loop6 +Loop6 orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11 orr R0, R0, R7, LSL R2 ; factor in the index number @@ -302,11 +302,11 @@ Loop6 bge Loop6 subs R7, R7, #1 ; decrement the index bge Loop5 -Skip2 +Skip2 add R10, R10, #2 ; increment the cache number cmp R3, R10 bgt Loop4 - + Finished2 dsb ldmfd SP!, {r4-r12, lr} @@ -315,12 +315,12 @@ Finished2 ArmDataMemoryBarrier dmb bx LR - + ArmDataSyncronizationBarrier ArmDrainWriteBuffer dsb bx LR - + ArmInstructionSynchronizationBarrier isb bx LR @@ -332,7 +332,7 @@ ArmReadVBar ArmWriteVBar // Set the Address of the Vector Table in the VBAR register - mcr p15, 0, r0, c12, c0, 0 + mcr p15, 0, r0, c12, c0, 0 // Ensure the SCTLR.V bit is clear mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data) bic r0, r0, #0x00002000 ; clear V bit -- cgit v1.2.3