From 07070ecc76cff00175715f9a9534bc9216599a11 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Wed, 18 Nov 2015 15:59:04 +0000 Subject: ArmPkg/ArmV7Mmu: make cached translation table accesses shareable To align with the way normal cacheable memory is mapped, set the shareable bit for cached accesses performed by the page table walker. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18896 6f19259b-4bc3-4df7-8a09-765794883524 --- ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'ArmPkg/Library') diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c index 8ed763cc82..f03f609d21 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c @@ -265,6 +265,19 @@ ArmConfigureMmu ( return RETURN_UNSUPPORTED; } + if (TTBRAttributes & TTBR_SHAREABLE) { + // + // Unlike the S bit in the short descriptors, which implies inner shareable + // on an implementation that supports two levels, the meaning of the S bit + // in the TTBR depends on the NOS bit, which defaults to Outer Shareable. + // However, we should only set this bit after we have confirmed that the + // implementation supports multiple levels, or else the NOS bit is UNK/SBZP + // + if (((ArmReadIdMmfr0 () >> 12) & 0xf) != 0) { + TTBRAttributes |= TTBR_NOT_OUTER_SHAREABLE; + } + } + ArmCleanInvalidateDataCache (); ArmInvalidateInstructionCache (); -- cgit v1.2.3