From 54d8d4dc971d326b1272095358427cb062b6e410 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Fri, 2 Oct 2015 14:48:21 +0000 Subject: ArmPkg/Mmu: do not configure block translations at level 0 Now that the AArch64 MMU code correctly identifies and handles naturally aligned regions of more than 2 MB in size, it will happily try to use block mappings at level 0 to map huge memory regions, such as the single cacheable 1:1 mapping we use for Xen domU to map the entire PA space. However, block mappings are not supported at level 0 so the resulting translation tables will be incorrect, causing execution to fail as soon as the MMU is enabled. So use level 1 as the minimum level at which to perform block translations. Reported-by: Julien Grall Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Tested-by: Stefano Stabellini Reviewed-by: Leif Lindholm git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18568 6f19259b-4bc3-4df7-8a09-765794883524 --- ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'ArmPkg') diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c index df37154f35..b2ab5aa7bb 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c @@ -295,8 +295,9 @@ GetBlockEntryListFromAddress ( BaseAddressAlignment = LowBitSet64 (RegionStart); } - // Identify the Page Level the RegionStart must belongs to - PageLevel = 3 - ((BaseAddressAlignment - 12) / 9); + // Identify the Page Level the RegionStart must belong to. Note that PageLevel + // should be at least 1 since block translations are not supported at level 0 + PageLevel = MAX (3 - ((BaseAddressAlignment - 12) / 9), 1); // If the required size is smaller than the current block size then we need to go to the page below. // The PageLevel was calculated on the Base Address alignment but did not take in account the alignment -- cgit v1.2.3