From bd6b97994ab6219c74033a7e68a503dbb8d56f9f Mon Sep 17 00:00:00 2001 From: oliviermartin Date: Tue, 27 Sep 2011 16:31:20 +0000 Subject: ArmPkg/ArmLib: Clean ArmV7Lib - Move the non specific ArmV7 functions to ArmLib. - Clean the ARM Platform common components to not depend on ArmV7 if not required git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12453 6f19259b-4bc3-4df7-8a09-765794883524 --- ArmPkg/Drivers/CpuDxe/Mmu.c | 2 - ArmPkg/Include/Chipset/ArmV7.h | 138 +---- ArmPkg/Include/Library/ArmLib.h | 85 ++- ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.S | 193 ------- ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm | 192 ------- ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S | 101 ++++ ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm | 100 ++++ ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c | 10 - ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.h | 160 +++--- ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf | 11 +- ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf | 9 +- ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf | 7 +- ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c | 23 +- ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S | 698 ++++++++++++------------ ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm | 691 ++++++++++++----------- ArmPkg/Library/ArmLib/Common/ArmLib.c | 12 + ArmPkg/Library/ArmLib/Common/ArmLibSupport.S | 272 ++++----- ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm | 282 +++++----- 18 files changed, 1390 insertions(+), 1596 deletions(-) delete mode 100644 ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.S delete mode 100644 ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm create mode 100644 ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S create mode 100644 ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm (limited to 'ArmPkg') diff --git a/ArmPkg/Drivers/CpuDxe/Mmu.c b/ArmPkg/Drivers/CpuDxe/Mmu.c index 74794eb945..6218b5d27f 100644 --- a/ArmPkg/Drivers/CpuDxe/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/Mmu.c @@ -15,8 +15,6 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. --*/ #include "CpuDxe.h" -//FIXME: Remove this ARMv7 specific header -#include // First Level Descriptors typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR; diff --git a/ArmPkg/Include/Chipset/ArmV7.h b/ArmPkg/Include/Chipset/ArmV7.h index 5fab7eddbe..909686ce36 100644 --- a/ArmPkg/Include/Chipset/ArmV7.h +++ b/ArmPkg/Include/Chipset/ArmV7.h @@ -1,6 +1,7 @@ /** @file Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Copyright (c) 2011, ARM Ltd. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License @@ -24,28 +25,6 @@ #define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a))) #define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a))) -// Cortex A9 feature bit definitions -#define A9_FEATURE_PARITY (1<<9) -#define A9_FEATURE_AOW (1<<8) -#define A9_FEATURE_EXCL (1<<7) -#define A9_FEATURE_SMP (1<<6) -#define A9_FEATURE_FOZ (1<<3) -#define A9_FEATURE_DPREF (1<<2) -#define A9_FEATURE_HINT (1<<1) -#define A9_FEATURE_FWD (1<<0) - -// SCU register offsets & masks -#define SCU_CONTROL_OFFSET 0x0 -#define SCU_CONFIG_OFFSET 0x4 -#define SCU_INVALL_OFFSET 0xC -#define SCU_FILT_START_OFFSET 0x40 -#define SCU_FILT_END_OFFSET 0x44 -#define SCU_SACR_OFFSET 0x50 -#define SCU_SSACR_OFFSET 0x54 - -#define SMP_GIC_CPUIF_BASE 0x100 -#define SMP_GIC_DIST_BASE 0x1000 - // CPACR - Coprocessor Access Control Register definitions #define CPACR_CP_DENIED(cp) 0x00 #define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF) @@ -71,121 +50,24 @@ #define SCR_FW (1 << 4) #define SCR_AW (1 << 5) -VOID -EFIAPI -ArmEnableSWPInstruction ( - VOID - ); +// MIDR - Main ID Register definitions +#define ARM_CPU_TYPE_MASK 0xFFF +#define ARM_CPU_TYPE_A15 0xC0F +#define ARM_CPU_TYPE_A9 0xC09 +#define ARM_CPU_TYPE_A5 0xC05 VOID EFIAPI -ArmWriteNsacr ( - IN UINT32 SetWayFormat - ); - -VOID -EFIAPI -ArmWriteScr ( - IN UINT32 SetWayFormat - ); - -VOID -EFIAPI -ArmWriteVMBar ( - IN UINT32 SetWayFormat - ); - -VOID -EFIAPI -ArmWriteVBar ( - IN UINT32 SetWayFormat - ); - -UINT32 -EFIAPI -ArmReadVBar ( - VOID - ); - -VOID -EFIAPI -ArmWriteCPACR ( - IN UINT32 SetWayFormat - ); - -VOID -EFIAPI -ArmEnableVFP ( - VOID - ); - -VOID -EFIAPI -ArmCallWFI ( - VOID - ); - -VOID -EFIAPI -ArmInvalidScu ( - VOID - ); - -UINTN -EFIAPI -ArmGetScuBaseAddress ( - VOID - ); - -UINT32 -EFIAPI -ArmIsScuEnable ( - VOID - ); - -VOID -EFIAPI -ArmWriteAuxCr ( - IN UINT32 Bit - ); - -UINT32 -EFIAPI -ArmReadAuxCr ( +ArmEnableSWPInstruction ( VOID ); -VOID -EFIAPI -ArmSetAuxCrBit ( - IN UINT32 Bits - ); - -VOID -EFIAPI -ArmSetupSmpNonSecure ( - IN UINTN CoreId - ); - UINTN EFIAPI ArmReadCbar ( VOID ); -VOID -EFIAPI -ArmInvalidateInstructionAndDataTlb ( - VOID - ); - - -UINTN -EFIAPI -ArmReadMpidr ( - VOID - ); - UINTN EFIAPI ArmReadTpidrurw ( @@ -198,4 +80,10 @@ ArmWriteTpidrurw ( UINTN Value ); +UINTN +EFIAPI +ArmReadIdPfr1 ( + VOID + ); + #endif // __ARM_V7_H__ diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h index 89d915a8df..e88633e1e9 100644 --- a/ArmPkg/Include/Library/ArmLib.h +++ b/ArmPkg/Include/Library/ArmLib.h @@ -15,6 +15,12 @@ #ifndef __ARM_LIB__ #define __ARM_LIB__ +#ifdef ARM_CPU_ARMv6 +#include +#else +#include +#endif + typedef enum { ARM_CACHE_TYPE_WRITE_BACK, ARM_CACHE_TYPE_UNKNOWN @@ -250,6 +256,12 @@ ArmDisableCachesAndMmu ( VOID ); +VOID +EFIAPI +ArmInvalidateInstructionAndDataTlb ( + VOID + ); + VOID EFIAPI ArmEnableInterrupts ( @@ -384,6 +396,77 @@ EFIAPI ArmInstructionSynchronizationBarrier ( VOID ); - + +VOID +EFIAPI +ArmWriteVBar ( + IN UINT32 VectorBase + ); + +UINT32 +EFIAPI +ArmReadVBar ( + VOID + ); + +VOID +EFIAPI +ArmWriteAuxCr ( + IN UINT32 Bit + ); + +UINT32 +EFIAPI +ArmReadAuxCr ( + VOID + ); + +VOID +EFIAPI +ArmSetAuxCrBit ( + IN UINT32 Bits + ); + +VOID +EFIAPI +ArmCallWFI ( + VOID + ); + +UINTN +EFIAPI +ArmReadMpidr ( + VOID + ); + +VOID +EFIAPI +ArmWriteCPACR ( + IN UINT32 Access + ); + +VOID +EFIAPI +ArmEnableVFP ( + VOID + ); + +VOID +EFIAPI +ArmWriteNsacr ( + IN UINT32 SetWayFormat + ); + +VOID +EFIAPI +ArmWriteScr ( + IN UINT32 SetWayFormat + ); + +VOID +EFIAPI +ArmWriteVMBar ( + IN UINT32 VectorMonitorBase + ); #endif // __ARM_LIB__ diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.S b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.S deleted file mode 100644 index 54f36174bb..0000000000 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.S +++ /dev/null @@ -1,193 +0,0 @@ -#------------------------------------------------------------------------------ -# -# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
-# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -#------------------------------------------------------------------------------ - -#include - -.text -.align 2 - -GCC_ASM_EXPORT(Cp15IdCode) -GCC_ASM_EXPORT(Cp15CacheInfo) -GCC_ASM_EXPORT(ArmIsMPCore) -GCC_ASM_EXPORT(ArmEnableAsynchronousAbort) -GCC_ASM_EXPORT(ArmDisableAsynchronousAbort) -GCC_ASM_EXPORT(ArmEnableIrq) -GCC_ASM_EXPORT(ArmDisableIrq) -GCC_ASM_EXPORT(ArmGetInterruptState) -GCC_ASM_EXPORT(ArmEnableFiq) -GCC_ASM_EXPORT(ArmDisableFiq) -GCC_ASM_EXPORT(ArmEnableInterrupts) -GCC_ASM_EXPORT(ArmDisableInterrupts) -GCC_ASM_EXPORT(ArmGetFiqState) -GCC_ASM_EXPORT(ArmInvalidateTlb) -GCC_ASM_EXPORT(ArmSetTTBR0) -GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress) -GCC_ASM_EXPORT(ArmSetDomainAccessControl) -GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry) -GCC_ASM_EXPORT(CPSRMaskInsert) -GCC_ASM_EXPORT(CPSRRead) -GCC_ASM_EXPORT(ReadCCSIDR) -GCC_ASM_EXPORT(ReadCLIDR) - - - -#------------------------------------------------------------------------------ - -ASM_PFX(Cp15IdCode): - mrc p15,0,R0,c0,c0,0 - bx LR - -ASM_PFX(Cp15CacheInfo): - mrc p15,0,R0,c0,c0,1 - bx LR - -ASM_PFX(ArmIsMPCore): - mrc p15,0,R0,c0,c0,5 - // Get Multiprocessing extension (bit31) & U bit (bit30) - and R0, R0, #0xC0000000 - // if bit30 == 0 then the processor is part of a multiprocessor system) - and R0, R0, #0x80000000 - bx LR - -ASM_PFX(ArmEnableAsynchronousAbort): - cpsie a - isb - bx LR - -ASM_PFX(ArmDisableAsynchronousAbort): - cpsid a - isb - bx LR - -ASM_PFX(ArmEnableIrq): - cpsie i - isb - bx LR - -ASM_PFX(ArmDisableIrq): - cpsid i - isb - bx LR - -ASM_PFX(ArmGetInterruptState): - mrs R0,CPSR - tst R0,#0x80 @Check if IRQ is enabled. - moveq R0,#1 - movne R0,#0 - bx LR - -ASM_PFX(ArmEnableFiq): - cpsie f - isb - bx LR - -ASM_PFX(ArmDisableFiq): - cpsid f - isb - bx LR - -ASM_PFX(ArmEnableInterrupts): - cpsie if - isb - bx LR - -ASM_PFX(ArmDisableInterrupts): - cpsid if - isb - bx LR - -ASM_PFX(ArmGetFiqState): - mrs R0,CPSR - tst R0,#0x40 @Check if FIQ is enabled. - moveq R0,#1 - movne R0,#0 - bx LR - -ASM_PFX(ArmInvalidateTlb): - mov r0,#0 - mcr p15,0,r0,c8,c7,0 - mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp - dsb - isb - bx lr - -ASM_PFX(ArmSetTTBR0): - mcr p15,0,r0,c2,c0,0 - isb - bx lr - -ASM_PFX(ArmGetTTBR0BaseAddress): - mrc p15,0,r0,c2,c0,0 - LoadConstantToReg(0xFFFFC000, r1) - and r0, r0, r1 - isb - bx lr - - -ASM_PFX(ArmSetDomainAccessControl): - mcr p15,0,r0,c3,c0,0 - isb - bx lr - -// -//VOID -//ArmUpdateTranslationTableEntry ( -// IN VOID *TranslationTableEntry // R0 -// IN VOID *MVA // R1 -// ); -ASM_PFX(ArmUpdateTranslationTableEntry): - mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA - dsb - mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA - mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp - dsb - isb - bx lr - -ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert - stmfd sp!, {r4-r12, lr} @ save all the banked registers - mov r3, sp @ copy the stack pointer into a non-banked register - mrs r2, cpsr @ read the cpsr - bic r2, r2, r0 @ clear mask in the cpsr - and r1, r1, r0 @ clear bits outside the mask in the input - orr r2, r2, r1 @ set field - msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch) - isb - mov sp, r3 @ restore stack pointer - ldmfd sp!, {r4-r12, lr} @ restore registers - bx lr @ return (hopefully thumb-safe!) - -ASM_PFX(CPSRRead): - mrs r0, cpsr - bx lr - -// UINT32 -// ReadCCSIDR ( -// IN UINT32 CSSELR -// ) -ASM_PFX(ReadCCSIDR): - mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR) - isb - mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR) - bx lr - -// UINT32 -// ReadCLIDR ( -// IN UINT32 CSSELR -// ) -ASM_PFX(ReadCLIDR): - mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register - bx lr - -ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm deleted file mode 100644 index 19f489f3c0..0000000000 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm +++ /dev/null @@ -1,192 +0,0 @@ -//------------------------------------------------------------------------------ -// -// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
-// -// This program and the accompanying materials -// are licensed and made available under the terms and conditions of the BSD License -// which accompanies this distribution. The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -// -//------------------------------------------------------------------------------ - - - EXPORT Cp15IdCode - EXPORT Cp15CacheInfo - EXPORT ArmIsMPCore - EXPORT ArmEnableAsynchronousAbort - EXPORT ArmDisableAsynchronousAbort - EXPORT ArmEnableIrq - EXPORT ArmDisableIrq - EXPORT ArmGetInterruptState - EXPORT ArmEnableFiq - EXPORT ArmDisableFiq - EXPORT ArmEnableInterrupts - EXPORT ArmDisableInterrupts - EXPORT ArmGetFiqState - EXPORT ArmInvalidateTlb - EXPORT ArmSetTTBR0 - EXPORT ArmGetTTBR0BaseAddress - EXPORT ArmSetDomainAccessControl - EXPORT ArmUpdateTranslationTableEntry - EXPORT CPSRMaskInsert - EXPORT CPSRRead - EXPORT ReadCCSIDR - EXPORT ReadCLIDR - - AREA ArmLibSupport, CODE, READONLY - - -//------------------------------------------------------------------------------ - -Cp15IdCode - mrc p15,0,R0,c0,c0,0 - bx LR - -Cp15CacheInfo - mrc p15,0,R0,c0,c0,1 - bx LR - -ArmIsMPCore - mrc p15,0,R0,c0,c0,5 - // Get Multiprocessing extension (bit31) & U bit (bit30) - and R0, R0, #0xC0000000 - // if bit30 == 0 then the processor is part of a multiprocessor system) - and R0, R0, #0x80000000 - bx LR - -ArmEnableAsynchronousAbort - cpsie a - isb - bx LR - -ArmDisableAsynchronousAbort - cpsid a - isb - bx LR - -ArmEnableIrq - cpsie i - isb - bx LR - -ArmDisableIrq - cpsid i - isb - bx LR - -ArmEnableFiq - cpsie f - isb - bx LR - -ArmDisableFiq - cpsid f - isb - bx LR - -ArmEnableInterrupts - cpsie if - isb - bx LR - -ArmDisableInterrupts - cpsid if - isb - bx LR - -ArmGetInterruptState - mrs R0,CPSR - tst R0,#0x80 ;Check if IRQ is enabled. - moveq R0,#1 - movne R0,#0 - bx LR - -ArmGetFiqState - mrs R0,CPSR - tst R0,#0x40 ;Check if FIQ is enabled. - moveq R0,#1 - movne R0,#0 - bx LR - -ArmInvalidateTlb - mov r0,#0 - mcr p15,0,r0,c8,c7,0 - mcr p15,0,R9,c7,c5,6 ; BPIALL Invalidate Branch predictor array. R9 == NoOp - dsb - isb - bx lr - -ArmSetTTBR0 - mcr p15,0,r0,c2,c0,0 - isb - bx lr - -ArmGetTTBR0BaseAddress - mrc p15,0,r0,c2,c0,0 - ldr r1, = 0xFFFFC000 - and r0, r0, r1 - isb - bx lr - - -ArmSetDomainAccessControl - mcr p15,0,r0,c3,c0,0 - isb - bx lr - -// -//VOID -//ArmUpdateTranslationTableEntry ( -// IN VOID *TranslationTableEntry // R0 -// IN VOID *MVA // R1 -// ); -ArmUpdateTranslationTableEntry - mcr p15,0,R0,c7,c14,1 ; DCCIMVAC Clean data cache by MVA - dsb - mcr p15,0,R1,c8,c7,1 ; TLBIMVA TLB Invalidate MVA - mcr p15,0,R9,c7,c5,6 ; BPIALL Invalidate Branch predictor array. R9 == NoOp - dsb - isb - bx lr - -CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to insert - stmfd sp!, {r4-r12, lr} ; save all the banked registers - mov r3, sp ; copy the stack pointer into a non-banked register - mrs r2, cpsr ; read the cpsr - bic r2, r2, r0 ; clear mask in the cpsr - and r1, r1, r0 ; clear bits outside the mask in the input - orr r2, r2, r1 ; set field - msr cpsr_cxsf, r2 ; write back cpsr (may have caused a mode switch) - isb - mov sp, r3 ; restore stack pointer - ldmfd sp!, {r4-r12, lr} ; restore registers - bx lr ; return (hopefully thumb-safe!) - -CPSRRead - mrs r0, cpsr - bx lr - - -// UINT32 -// ReadCCSIDR ( -// IN UINT32 CSSELR -// ) -ReadCCSIDR - mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR) - isb - mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR) - bx lr - - -// UINT32 -// ReadCLIDR ( -// IN UINT32 CSSELR -// ) -ReadCLIDR - mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register - bx lr - -END diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S new file mode 100644 index 0000000000..9595f224c5 --- /dev/null +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S @@ -0,0 +1,101 @@ +#------------------------------------------------------------------------------ +# +# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+# Copyright (c) 2011, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#------------------------------------------------------------------------------ + +#include + +.text +.align 2 + +GCC_ASM_EXPORT(ArmIsMpCore) +GCC_ASM_EXPORT(ArmEnableAsynchronousAbort) +GCC_ASM_EXPORT(ArmDisableAsynchronousAbort) +GCC_ASM_EXPORT(ArmEnableIrq) +GCC_ASM_EXPORT(ArmDisableIrq) +GCC_ASM_EXPORT(ArmEnableFiq) +GCC_ASM_EXPORT(ArmDisableFiq) +GCC_ASM_EXPORT(ArmEnableInterrupts) +GCC_ASM_EXPORT(ArmDisableInterrupts) +GCC_ASM_EXPORT(ReadCCSIDR) +GCC_ASM_EXPORT(ReadCLIDR) + +#------------------------------------------------------------------------------ + +ASM_PFX(ArmIsMpCore): + mrc p15,0,R0,c0,c0,5 + // Get Multiprocessing extension (bit31) & U bit (bit30) + and R0, R0, #0xC0000000 + // if bit30 == 0 then the processor is part of a multiprocessor system) + and R0, R0, #0x80000000 + bx LR + +ASM_PFX(ArmEnableAsynchronousAbort): + cpsie a + isb + bx LR + +ASM_PFX(ArmDisableAsynchronousAbort): + cpsid a + isb + bx LR + +ASM_PFX(ArmEnableIrq): + cpsie i + isb + bx LR + +ASM_PFX(ArmDisableIrq): + cpsid i + isb + bx LR + +ASM_PFX(ArmEnableFiq): + cpsie f + isb + bx LR + +ASM_PFX(ArmDisableFiq): + cpsid f + isb + bx LR + +ASM_PFX(ArmEnableInterrupts): + cpsie if + isb + bx LR + +ASM_PFX(ArmDisableInterrupts): + cpsid if + isb + bx LR + +// UINT32 +// ReadCCSIDR ( +// IN UINT32 CSSELR +// ) +ASM_PFX(ReadCCSIDR): + mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR) + isb + mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR) + bx lr + +// UINT32 +// ReadCLIDR ( +// IN UINT32 CSSELR +// ) +ASM_PFX(ReadCLIDR): + mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register + bx lr + +ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm new file mode 100644 index 0000000000..39d6c85937 --- /dev/null +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm @@ -0,0 +1,100 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
+// Copyright (c) 2011, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +//------------------------------------------------------------------------------ + + + EXPORT ArmIsMpCore + EXPORT ArmEnableAsynchronousAbort + EXPORT ArmDisableAsynchronousAbort + EXPORT ArmEnableIrq + EXPORT ArmDisableIrq + EXPORT ArmEnableFiq + EXPORT ArmDisableFiq + EXPORT ArmEnableInterrupts + EXPORT ArmDisableInterrupts + EXPORT ReadCCSIDR + EXPORT ReadCLIDR + + AREA ArmLibSupportV7, CODE, READONLY + + +//------------------------------------------------------------------------------ + +ArmIsMpCore + mrc p15,0,R0,c0,c0,5 + // Get Multiprocessing extension (bit31) & U bit (bit30) + and R0, R0, #0xC0000000 + // if bit30 == 0 then the processor is part of a multiprocessor system) + and R0, R0, #0x80000000 + bx LR + +ArmEnableAsynchronousAbort + cpsie a + isb + bx LR + +ArmDisableAsynchronousAbort + cpsid a + isb + bx LR + +ArmEnableIrq + cpsie i + isb + bx LR + +ArmDisableIrq + cpsid i + isb + bx LR + +ArmEnableFiq + cpsie f + isb + bx LR + +ArmDisableFiq + cpsid f + isb + bx LR + +ArmEnableInterrupts + cpsie if + isb + bx LR + +ArmDisableInterrupts + cpsid if + isb + bx LR + +// UINT32 +// ReadCCSIDR ( +// IN UINT32 CSSELR +// ) +ReadCCSIDR + mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR) + isb + mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR) + bx lr + +// UINT32 +// ReadCLIDR ( +// IN UINT32 CSSELR +// ) +ReadCLIDR + mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register + bx lr + +END diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c index 4329bd7239..1ffdb7f83f 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c @@ -235,13 +235,3 @@ ArmCleanDataCache ( ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay); } -VOID -EFIAPI -ArmSetAuxCrBit ( - IN UINT32 Bits - ) -{ - UINT32 val = ArmReadAuxCr(); - val |= Bits; - ArmWriteAuxCr(val); -} diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.h b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.h index 7eaeb15661..b98407cfbc 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.h +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.h @@ -1,80 +1,80 @@ -/** @file - - Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#ifndef __ARM_V7_LIB_H__ -#define __ARM_V7_LIB_H__ - - -VOID -EFIAPI -ArmDrainWriteBuffer ( - VOID - ); - -VOID -EFIAPI -ArmInvalidateDataCacheEntryBySetWay ( - IN UINT32 SetWayFormat - ); - -VOID -EFIAPI -ArmCleanDataCacheEntryBySetWay ( - IN UINT32 SetWayFormat - ); - -VOID -EFIAPI -ArmCleanInvalidateDataCacheEntryBySetWay ( - IN UINT32 SetWayFormat - ); - -VOID -EFIAPI -ArmEnableAsynchronousAbort ( - VOID - ); - -UINTN -EFIAPI -ArmDisableAsynchronousAbort ( - VOID - ); - -VOID -EFIAPI -ArmEnableIrq ( - VOID - ); - -UINTN -EFIAPI -ArmDisableIrq ( - VOID - ); - -VOID -EFIAPI -ArmEnableFiq ( - VOID - ); - -UINTN -EFIAPI -ArmDisableFiq ( - VOID - ); - -#endif // __ARM_V7_LIB_H__ - +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __ARM_V7_LIB_H__ +#define __ARM_V7_LIB_H__ + + +VOID +EFIAPI +ArmDrainWriteBuffer ( + VOID + ); + +VOID +EFIAPI +ArmInvalidateDataCacheEntryBySetWay ( + IN UINT32 SetWayFormat + ); + +VOID +EFIAPI +ArmCleanDataCacheEntryBySetWay ( + IN UINT32 SetWayFormat + ); + +VOID +EFIAPI +ArmCleanInvalidateDataCacheEntryBySetWay ( + IN UINT32 SetWayFormat + ); + +VOID +EFIAPI +ArmEnableAsynchronousAbort ( + VOID + ); + +UINTN +EFIAPI +ArmDisableAsynchronousAbort ( + VOID + ); + +VOID +EFIAPI +ArmEnableIrq ( + VOID + ); + +UINTN +EFIAPI +ArmDisableIrq ( + VOID + ); + +VOID +EFIAPI +ArmEnableFiq ( + VOID + ); + +UINTN +EFIAPI +ArmDisableFiq ( + VOID + ); + +#endif // __ARM_V7_LIB_H__ + diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf index 2452c28734..2f0ade9b8e 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf @@ -1,7 +1,7 @@ #/** @file -# Semihosting serail port lib # # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
+# Copyright (c) 2011, ARM Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -22,13 +22,16 @@ LIBRARY_CLASS = ArmLib [Sources.common] - ArmLibSupport.S | GCC - ArmLibSupport.asm | RVCT + ArmLibSupportV7.S | GCC + ArmLibSupportV7.asm | RVCT + + ../Common/ArmLibSupport.S | GCC + ../Common/ArmLibSupport.asm | RVCT ../Common/ArmLib.c ArmV7Support.S | GCC ArmV7Support.asm | RVCT - + ArmV7Lib.c ArmV7Mmu.c diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf b/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf index f97b5a4cee..6211549742 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf @@ -22,13 +22,16 @@ LIBRARY_CLASS = ArmLib [Sources.common] - ArmLibSupport.S | GCC - ArmLibSupport.asm | RVCT + ArmLibSupportV7.S | GCC + ArmLibSupportV7.asm | RVCT + + ../Common/ArmLibSupport.S | GCC + ../Common/ArmLibSupport.asm | RVCT ../Common/ArmLib.c ArmV7Support.S | GCC ArmV7Support.asm | RVCT - + ArmV7Lib.c ArmV7Mmu.c diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf b/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf index 73bf09a5a3..b7cb450462 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf @@ -20,8 +20,11 @@ LIBRARY_CLASS = ArmLib [Sources.common] - ArmLibSupport.S | GCC - ArmLibSupport.asm | RVCT + ArmLibSupportV7.S | GCC + ArmLibSupportV7.asm | RVCT + + ../Common/ArmLibSupport.S | GCC + ../Common/ArmLibSupport.asm | RVCT ../Common/ArmLib.c ArmV7Support.S | GCC diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c index 3ba66d62bf..f57e48b3a5 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c @@ -29,7 +29,8 @@ PopulateLevel2PageTable ( IN UINT32 PhysicalBase, IN UINT32 RemainLength, IN ARM_MEMORY_REGION_ATTRIBUTES Attributes - ) { + ) +{ UINT32* PageEntry; UINT32 Pages; UINT32 Index; @@ -173,14 +174,14 @@ FillTranslationTable ( PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE; } else { // Case: Physical address aligned on the Section Size (1MB) && the length does not fill a section - PopulateLevel2PageTable(SectionEntry++,PhysicalBase,RemainLength,MemoryRegion->Attributes); + PopulateLevel2PageTable (SectionEntry++, PhysicalBase, RemainLength, MemoryRegion->Attributes); // It must be the last entry break; } } else { // Case: Physical address NOT aligned on the Section Size (1MB) - PopulateLevel2PageTable(SectionEntry++,PhysicalBase,RemainLength,MemoryRegion->Attributes); + PopulateLevel2PageTable (SectionEntry++, PhysicalBase, RemainLength, MemoryRegion->Attributes); // Aligned the address PhysicalBase = (PhysicalBase + TT_DESCRIPTOR_SECTION_SIZE) & ~(TT_DESCRIPTOR_SECTION_SIZE-1); @@ -206,7 +207,7 @@ ArmConfigureMmu ( UINT32 TTBRAttributes; // Allocate pages for translation table. - TranslationTable = (UINTN)AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SECTION_SIZE + TRANSLATION_TABLE_SECTION_ALIGNMENT)); + TranslationTable = (UINTN)AllocatePages (EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SECTION_SIZE + TRANSLATION_TABLE_SECTION_ALIGNMENT)); TranslationTable = ((UINTN)TranslationTable + TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK; if (TranslationTableBase != NULL) { @@ -219,17 +220,17 @@ ArmConfigureMmu ( ZeroMem ((VOID *)TranslationTable, TRANSLATION_TABLE_SECTION_SIZE); - ArmCleanInvalidateDataCache(); - ArmInvalidateInstructionCache(); - ArmInvalidateTlb(); + ArmCleanInvalidateDataCache (); + ArmInvalidateInstructionCache (); + ArmInvalidateTlb (); - ArmDisableDataCache(); + ArmDisableDataCache (); ArmDisableInstructionCache(); - ArmDisableMmu(); + ArmDisableMmu (); // Make sure nothing sneaked into the cache - ArmCleanInvalidateDataCache(); - ArmInvalidateInstructionCache(); + ArmCleanInvalidateDataCache (); + ArmInvalidateInstructionCache (); TranslationTableAttribute = (ARM_MEMORY_REGION_ATTRIBUTES)0; while (MemoryTable->Length != 0) { diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S index 75e1e0b5df..fb1ca2dee2 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S @@ -1,358 +1,340 @@ -#------------------------------------------------------------------------------ -# -# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
-# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -#------------------------------------------------------------------------------ - -.text -.align 2 - -GCC_ASM_EXPORT (ArmInvalidateInstructionCache) -GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA) -GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA) -GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA) -GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay) -GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay) -GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay) -GCC_ASM_EXPORT (ArmDrainWriteBuffer) -GCC_ASM_EXPORT (ArmEnableMmu) -GCC_ASM_EXPORT (ArmDisableMmu) -GCC_ASM_EXPORT (ArmDisableCachesAndMmu) -GCC_ASM_EXPORT (ArmMmuEnabled) -GCC_ASM_EXPORT (ArmEnableDataCache) -GCC_ASM_EXPORT (ArmDisableDataCache) -GCC_ASM_EXPORT (ArmEnableInstructionCache) -GCC_ASM_EXPORT (ArmDisableInstructionCache) -GCC_ASM_EXPORT (ArmEnableSWPInstruction) -GCC_ASM_EXPORT (ArmEnableBranchPrediction) -GCC_ASM_EXPORT (ArmDisableBranchPrediction) -GCC_ASM_EXPORT (ArmSetLowVectors) -GCC_ASM_EXPORT (ArmSetHighVectors) -GCC_ASM_EXPORT (ArmV7AllDataCachesOperation) -GCC_ASM_EXPORT (ArmDataMemoryBarrier) -GCC_ASM_EXPORT (ArmDataSyncronizationBarrier) -GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier) -GCC_ASM_EXPORT (ArmWriteNsacr) -GCC_ASM_EXPORT (ArmWriteScr) -GCC_ASM_EXPORT (ArmWriteVMBar) -GCC_ASM_EXPORT (ArmWriteVBar) -GCC_ASM_EXPORT (ArmWriteCPACR) -GCC_ASM_EXPORT (ArmEnableVFP) -GCC_ASM_EXPORT (ArmCallWFI) -GCC_ASM_EXPORT (ArmWriteAuxCr) -GCC_ASM_EXPORT (ArmReadAuxCr) -GCC_ASM_EXPORT (ArmReadCbar) -GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb) -GCC_ASM_EXPORT (ArmReadMpidr) -GCC_ASM_EXPORT (ArmReadTpidrurw) -GCC_ASM_EXPORT (ArmWriteTpidrurw) - -.set DC_ON, (0x1<<2) -.set IC_ON, (0x1<<12) -.set CTRL_M_BIT, (1 << 0) -.set CTRL_C_BIT, (1 << 2) -.set CTRL_B_BIT, (1 << 7) -.set CTRL_I_BIT, (1 << 12) - - -ASM_PFX(ArmInvalidateDataCacheEntryByMVA): - mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line - dsb - isb - bx lr - -ASM_PFX(ArmCleanDataCacheEntryByMVA): - mcr p15, 0, r0, c7, c10, 1 @clean single data cache line - dsb - isb - bx lr - - -ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA): - mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line - dsb - isb - bx lr - - -ASM_PFX(ArmInvalidateDataCacheEntryBySetWay): - mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line - dsb - isb - bx lr - - -ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay): - mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line - dsb - isb - bx lr - - -ASM_PFX(ArmCleanDataCacheEntryBySetWay): - mcr p15, 0, r0, c7, c10, 2 @ Clean this line - dsb - isb - bx lr - -ASM_PFX(ArmInvalidateInstructionCache): - mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache - dsb - isb - bx LR - -ASM_PFX(ArmEnableMmu): - mrc p15,0,R0,c1,c0,0 - orr R0,R0,#1 - mcr p15,0,R0,c1,c0,0 - dsb - isb - bx LR - - -ASM_PFX(ArmDisableMmu): - mrc p15,0,R0,c1,c0,0 - bic R0,R0,#1 - mcr p15,0,R0,c1,c0,0 @Disable MMU - - mcr p15,0,R0,c8,c7,0 @Invalidate TLB - mcr p15,0,R0,c7,c5,6 @Invalidate Branch predictor array - dsb - isb - bx LR - -ASM_PFX(ArmDisableCachesAndMmu): - mrc p15, 0, r0, c1, c0, 0 @ Get control register - bic r0, r0, #CTRL_M_BIT @ Disable MMU - bic r0, r0, #CTRL_C_BIT @ Disable D Cache - bic r0, r0, #CTRL_I_BIT @ Disable I Cache - mcr p15, 0, r0, c1, c0, 0 @ Write control register - dsb - isb - bx LR - -ASM_PFX(ArmMmuEnabled): - mrc p15,0,R0,c1,c0,0 - and R0,R0,#1 - bx LR - -ASM_PFX(ArmEnableDataCache): - ldr R1,=DC_ON - mrc p15,0,R0,c1,c0,0 @Read control register configuration data - orr R0,R0,R1 @Set C bit - mcr p15,0,r0,c1,c0,0 @Write control register configuration data - dsb - isb - bx LR - -ASM_PFX(ArmDisableDataCache): - ldr R1,=DC_ON - mrc p15,0,R0,c1,c0,0 @Read control register configuration data - bic R0,R0,R1 @Clear C bit - mcr p15,0,r0,c1,c0,0 @Write control register configuration data - dsb - isb - bx LR - -ASM_PFX(ArmEnableInstructionCache): - ldr R1,=IC_ON - mrc p15,0,R0,c1,c0,0 @Read control register configuration data - orr R0,R0,R1 @Set I bit - mcr p15,0,r0,c1,c0,0 @Write control register configuration data - dsb - isb - bx LR - -ASM_PFX(ArmDisableInstructionCache): - ldr R1,=IC_ON - mrc p15,0,R0,c1,c0,0 @Read control register configuration data - bic R0,R0,R1 @Clear I bit. - mcr p15,0,r0,c1,c0,0 @Write control register configuration data - dsb - isb - bx LR - -ASM_PFX(ArmEnableSWPInstruction): - mrc p15, 0, r0, c1, c0, 0 - orr r0, r0, #0x00000400 - mcr p15, 0, r0, c1, c0, 0 - isb - bx LR - -ASM_PFX(ArmEnableBranchPrediction): - mrc p15, 0, r0, c1, c0, 0 - orr r0, r0, #0x00000800 - mcr p15, 0, r0, c1, c0, 0 - dsb - isb - bx LR - -ASM_PFX(ArmDisableBranchPrediction): - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x00000800 - mcr p15, 0, r0, c1, c0, 0 - dsb - isb - bx LR - -ASM_PFX(ArmSetLowVectors): - mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data) - bic r0, r0, #0x00002000 @ clear V bit - mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data) - isb - bx LR - -ASM_PFX(ArmSetHighVectors): - mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data) - orr r0, r0, #0x00002000 @ clear V bit - mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data) - isb - bx LR - -ASM_PFX(ArmV7AllDataCachesOperation): - stmfd SP!,{r4-r12, LR} - mov R1, R0 @ Save Function call in R1 - mrc p15, 1, R6, c0, c0, 1 @ Read CLIDR - ands R3, R6, #0x7000000 @ Mask out all but Level of Coherency (LoC) - mov R3, R3, LSR #23 @ Cache level value (naturally aligned) - beq L_Finished - mov R10, #0 - -Loop1: - add R2, R10, R10, LSR #1 @ Work out 3xcachelevel - mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level - and R12, R12, #7 @ get those 3 bits alone - cmp R12, #2 - blt L_Skip @ no cache or only instruction cache at this level - mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction - isb @ isb to sync the change to the CacheSizeID reg - mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR) - and R2, R12, #0x7 @ extract the line length field - add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes) -@ ldr R4, =0x3FF - mov R4, #0x400 - sub R4, R4, #1 - ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned) - clz R5, R4 @ R5 is the bit position of the way size increment -@ ldr R7, =0x00007FFF - mov R7, #0x00008000 - sub R7, R7, #1 - ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned) - -Loop2: - mov R9, R4 @ R9 working copy of the max way size (right aligned) - -Loop3: - orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11 - orr R0, R0, R7, LSL R2 @ factor in the index number - - blx R1 - - subs R9, R9, #1 @ decrement the way number - bge Loop3 - subs R7, R7, #1 @ decrement the index - bge Loop2 -L_Skip: - add R10, R10, #2 @ increment the cache number - cmp R3, R10 - bgt Loop1 - -L_Finished: - dsb - ldmfd SP!, {r4-r12, lr} - bx LR - -ASM_PFX(ArmDataMemoryBarrier): - dmb - bx LR - -ASM_PFX(ArmDataSyncronizationBarrier): -ASM_PFX(ArmDrainWriteBuffer): - dsb - bx LR - -ASM_PFX(ArmInstructionSynchronizationBarrier): - isb - bx LR - -ASM_PFX(ArmWriteNsacr): - mcr p15, 0, r0, c1, c1, 2 - bx lr - -ASM_PFX(ArmWriteScr): - mcr p15, 0, r0, c1, c1, 0 - bx lr - -ASM_PFX(ArmWriteAuxCr): - mcr p15, 0, r0, c1, c0, 1 - bx lr - -ASM_PFX(ArmReadAuxCr): - mrc p15, 0, r0, c1, c0, 1 - bx lr - -ASM_PFX(ArmWriteVMBar): - mcr p15, 0, r0, c12, c0, 1 - bx lr - -ASM_PFX(ArmWriteVBar): - # Set the Address of the Vector Table in the VBAR register - mcr p15, 0, r0, c12, c0, 0 - # Ensure the SCTLR.V bit is clear - mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data) - bic r0, r0, #0x00002000 @ clear V bit - mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data) - isb - bx lr - -ASM_PFX(ArmWriteCPACR): - mcr p15, 0, r0, c1, c0, 2 - bx lr - -ASM_PFX(ArmEnableVFP): - # Read CPACR (Coprocessor Access Control Register) - mrc p15, 0, r0, c1, c0, 2 - # Enable VPF access (Full Access to CP10, CP11) (V* instructions) - orr r0, r0, #0x00f00000 - # Write back CPACR (Coprocessor Access Control Register) - mcr p15, 0, r0, c1, c0, 2 - # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally. - mov r0, #0x40000000 - mcr p10,#0x7,r0,c8,c0,#0 - bx lr - -ASM_PFX(ArmCallWFI): - wfi - bx lr - -#Note: Return 0 in Uniprocessor implementation -ASM_PFX(ArmReadCbar): - mrc p15, 4, r0, c15, c0, 0 @ Read Configuration Base Address Register - bx lr - -ASM_PFX(ArmInvalidateInstructionAndDataTlb): - mcr p15, 0, r0, c8, c7, 0 @ Invalidate Inst TLB and Data TLB - dsb - bx lr - -ASM_PFX(ArmReadMpidr): - mrc p15, 0, r0, c0, c0, 5 @ read MPIDR - bx lr - -ASM_PFX(ArmReadTpidrurw): - mrc p15, 0, r0, c13, c0, 2 @ read TPIDRURW - bx lr - -ASM_PFX(ArmWriteTpidrurw): - mcr p15, 0, r0, c13, c0, 2 @ write TPIDRURW - bx lr - -ASM_FUNCTION_REMOVE_IF_UNREFERENCED +#------------------------------------------------------------------------------ +# +# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
+# Copyright (c) 2011, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#------------------------------------------------------------------------------ + +.text +.align 2 + +GCC_ASM_EXPORT (ArmInvalidateInstructionCache) +GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA) +GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA) +GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA) +GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay) +GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay) +GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay) +GCC_ASM_EXPORT (ArmDrainWriteBuffer) +GCC_ASM_EXPORT (ArmEnableMmu) +GCC_ASM_EXPORT (ArmDisableMmu) +GCC_ASM_EXPORT (ArmDisableCachesAndMmu) +GCC_ASM_EXPORT (ArmMmuEnabled) +GCC_ASM_EXPORT (ArmEnableDataCache) +GCC_ASM_EXPORT (ArmDisableDataCache) +GCC_ASM_EXPORT (ArmEnableInstructionCache) +GCC_ASM_EXPORT (ArmDisableInstructionCache) +GCC_ASM_EXPORT (ArmEnableSWPInstruction) +GCC_ASM_EXPORT (ArmEnableBranchPrediction) +GCC_ASM_EXPORT (ArmDisableBranchPrediction) +GCC_ASM_EXPORT (ArmSetLowVectors) +GCC_ASM_EXPORT (ArmSetHighVectors) +GCC_ASM_EXPORT (ArmV7AllDataCachesOperation) +GCC_ASM_EXPORT (ArmDataMemoryBarrier) +GCC_ASM_EXPORT (ArmDataSyncronizationBarrier) +GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier) +GCC_ASM_EXPORT (ArmWriteVBar) +GCC_ASM_EXPORT (ArmEnableVFP) +GCC_ASM_EXPORT (ArmCallWFI) +GCC_ASM_EXPORT (ArmReadCbar) +GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb) +GCC_ASM_EXPORT (ArmReadMpidr) +GCC_ASM_EXPORT (ArmReadTpidrurw) +GCC_ASM_EXPORT (ArmWriteTpidrurw) +GCC_ASM_EXPORT (ArmIsArchTimerImplemented) +GCC_ASM_EXPORT (ArmReadIdPfr1) + +.set DC_ON, (0x1<<2) +.set IC_ON, (0x1<<12) +.set CTRL_M_BIT, (1 << 0) +.set CTRL_C_BIT, (1 << 2) +.set CTRL_B_BIT, (1 << 7) +.set CTRL_I_BIT, (1 << 12) + + +ASM_PFX(ArmInvalidateDataCacheEntryByMVA): + mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line + dsb + isb + bx lr + +ASM_PFX(ArmCleanDataCacheEntryByMVA): + mcr p15, 0, r0, c7, c10, 1 @clean single data cache line + dsb + isb + bx lr + + +ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA): + mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line + dsb + isb + bx lr + + +ASM_PFX(ArmInvalidateDataCacheEntryBySetWay): + mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line + dsb + isb + bx lr + + +ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay): + mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line + dsb + isb + bx lr + + +ASM_PFX(ArmCleanDataCacheEntryBySetWay): + mcr p15, 0, r0, c7, c10, 2 @ Clean this line + dsb + isb + bx lr + +ASM_PFX(ArmInvalidateInstructionCache): + mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache + dsb + isb + bx LR + +ASM_PFX(ArmEnableMmu): + mrc p15,0,R0,c1,c0,0 + orr R0,R0,#1 + mcr p15,0,R0,c1,c0,0 + dsb + isb + bx LR + + +ASM_PFX(ArmDisableMmu): + mrc p15,0,R0,c1,c0,0 + bic R0,R0,#1 + mcr p15,0,R0,c1,c0,0 @Disable MMU + + mcr p15,0,R0,c8,c7,0 @Invalidate TLB + mcr p15,0,R0,c7,c5,6 @Invalidate Branch predictor array + dsb + isb + bx LR + +ASM_PFX(ArmDisableCachesAndMmu): + mrc p15, 0, r0, c1, c0, 0 @ Get control register + bic r0, r0, #CTRL_M_BIT @ Disable MMU + bic r0, r0, #CTRL_C_BIT @ Disable D Cache + bic r0, r0, #CTRL_I_BIT @ Disable I Cache + mcr p15, 0, r0, c1, c0, 0 @ Write control register + dsb + isb + bx LR + +ASM_PFX(ArmMmuEnabled): + mrc p15,0,R0,c1,c0,0 + and R0,R0,#1 + bx LR + +ASM_PFX(ArmEnableDataCache): + ldr R1,=DC_ON + mrc p15,0,R0,c1,c0,0 @Read control register configuration data + orr R0,R0,R1 @Set C bit + mcr p15,0,r0,c1,c0,0 @Write control register configuration data + dsb + isb + bx LR + +ASM_PFX(ArmDisableDataCache): + ldr R1,=DC_ON + mrc p15,0,R0,c1,c0,0 @Read control register configuration data + bic R0,R0,R1 @Clear C bit + mcr p15,0,r0,c1,c0,0 @Write control register configuration data + dsb + isb + bx LR + +ASM_PFX(ArmEnableInstructionCache): + ldr R1,=IC_ON + mrc p15,0,R0,c1,c0,0 @Read control register configuration data + orr R0,R0,R1 @Set I bit + mcr p15,0,r0,c1,c0,0 @Write control register configuration data + dsb + isb + bx LR + +ASM_PFX(ArmDisableInstructionCache): + ldr R1,=IC_ON + mrc p15,0,R0,c1,c0,0 @Read control register configuration data + bic R0,R0,R1 @Clear I bit. + mcr p15,0,r0,c1,c0,0 @Write control register configuration data + dsb + isb + bx LR + +ASM_PFX(ArmEnableSWPInstruction): + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #0x00000400 + mcr p15, 0, r0, c1, c0, 0 + isb + bx LR + +ASM_PFX(ArmEnableBranchPrediction): + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #0x00000800 + mcr p15, 0, r0, c1, c0, 0 + dsb + isb + bx LR + +ASM_PFX(ArmDisableBranchPrediction): + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00000800 + mcr p15, 0, r0, c1, c0, 0 + dsb + isb + bx LR + +ASM_PFX(ArmSetLowVectors): + mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data) + bic r0, r0, #0x00002000 @ clear V bit + mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data) + isb + bx LR + +ASM_PFX(ArmSetHighVectors): + mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data) + orr r0, r0, #0x00002000 @ clear V bit + mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data) + isb + bx LR + +ASM_PFX(ArmV7AllDataCachesOperation): + stmfd SP!,{r4-r12, LR} + mov R1, R0 @ Save Function call in R1 + mrc p15, 1, R6, c0, c0, 1 @ Read CLIDR + ands R3, R6, #0x7000000 @ Mask out all but Level of Coherency (LoC) + mov R3, R3, LSR #23 @ Cache level value (naturally aligned) + beq L_Finished + mov R10, #0 + +Loop1: + add R2, R10, R10, LSR #1 @ Work out 3xcachelevel + mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level + and R12, R12, #7 @ get those 3 bits alone + cmp R12, #2 + blt L_Skip @ no cache or only instruction cache at this level + mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction + isb @ isb to sync the change to the CacheSizeID reg + mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR) + and R2, R12, #0x7 @ extract the line length field + add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes) +@ ldr R4, =0x3FF + mov R4, #0x400 + sub R4, R4, #1 + ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned) + clz R5, R4 @ R5 is the bit position of the way size increment +@ ldr R7, =0x00007FFF + mov R7, #0x00008000 + sub R7, R7, #1 + ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned) + +Loop2: + mov R9, R4 @ R9 working copy of the max way size (right aligned) + +Loop3: + orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11 + orr R0, R0, R7, LSL R2 @ factor in the index number + + blx R1 + + subs R9, R9, #1 @ decrement the way number + bge Loop3 + subs R7, R7, #1 @ decrement the index + bge Loop2 +L_Skip: + add R10, R10, #2 @ increment the cache number + cmp R3, R10 + bgt Loop1 + +L_Finished: + dsb + ldmfd SP!, {r4-r12, lr} + bx LR + +ASM_PFX(ArmDataMemoryBarrier): + dmb + bx LR + +ASM_PFX(ArmDataSyncronizationBarrier): +ASM_PFX(ArmDrainWriteBuffer): + dsb + bx LR + +ASM_PFX(ArmInstructionSynchronizationBarrier): + isb + bx LR + +ASM_PFX(ArmWriteVBar): + # Set the Address of the Vector Table in the VBAR register + mcr p15, 0, r0, c12, c0, 0 + # Ensure the SCTLR.V bit is clear + mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data) + bic r0, r0, #0x00002000 @ clear V bit + mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data) + isb + bx lr + +ASM_PFX(ArmEnableVFP): + # Read CPACR (Coprocessor Access Control Register) + mrc p15, 0, r0, c1, c0, 2 + # Enable VPF access (Full Access to CP10, CP11) (V* instructions) + orr r0, r0, #0x00f00000 + # Write back CPACR (Coprocessor Access Control Register) + mcr p15, 0, r0, c1, c0, 2 + # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally. + mov r0, #0x40000000 + mcr p10,#0x7,r0,c8,c0,#0 + bx lr + +ASM_PFX(ArmCallWFI): + wfi + bx lr + +#Note: Return 0 in Uniprocessor implementation +ASM_PFX(ArmReadCbar): + mrc p15, 4, r0, c15, c0, 0 @ Read Configuration Base Address Register + bx lr + +ASM_PFX(ArmInvalidateInstructionAndDataTlb): + mcr p15, 0, r0, c8, c7, 0 @ Invalidate Inst TLB and Data TLB + dsb + bx lr + +ASM_PFX(ArmReadMpidr): + mrc p15, 0, r0, c0, c0, 5 @ read MPIDR + bx lr + +ASM_PFX(ArmReadTpidrurw): + mrc p15, 0, r0, c13, c0, 2 @ read TPIDRURW + bx lr + +ASM_PFX(ArmWriteTpidrurw): + mcr p15, 0, r0, c13, c0, 2 @ write TPIDRURW + bx lr + +ASM_PFX(ArmIsArchTimerImplemented): + mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1 + and r0, r0, #0x000F0000 + bx lr + +ASM_PFX(ArmReadIdPfr1): + mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1 Register + bx lr + +ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm index 62539efd91..fc28b0d922 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm @@ -1,357 +1,334 @@ -//------------------------------------------------------------------------------ -// -// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
-// -// This program and the accompanying materials -// are licensed and made available under the terms and conditions of the BSD License -// which accompanies this distribution. The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -// -//------------------------------------------------------------------------------ - - EXPORT ArmInvalidateInstructionCache - EXPORT ArmInvalidateDataCacheEntryByMVA - EXPORT ArmCleanDataCacheEntryByMVA - EXPORT ArmCleanInvalidateDataCacheEntryByMVA - EXPORT ArmInvalidateDataCacheEntryBySetWay - EXPORT ArmCleanDataCacheEntryBySetWay - EXPORT ArmCleanInvalidateDataCacheEntryBySetWay - EXPORT ArmDrainWriteBuffer - EXPORT ArmEnableMmu - EXPORT ArmDisableMmu - EXPORT ArmDisableCachesAndMmu - EXPORT ArmMmuEnabled - EXPORT ArmEnableDataCache - EXPORT ArmDisableDataCache - EXPORT ArmEnableInstructionCache - EXPORT ArmDisableInstructionCache - EXPORT ArmEnableSWPInstruction - EXPORT ArmEnableBranchPrediction - EXPORT ArmDisableBranchPrediction - EXPORT ArmSetLowVectors - EXPORT ArmSetHighVectors - EXPORT ArmV7AllDataCachesOperation - EXPORT ArmDataMemoryBarrier - EXPORT ArmDataSyncronizationBarrier - EXPORT ArmInstructionSynchronizationBarrier - EXPORT ArmWriteNsacr - EXPORT ArmWriteScr - EXPORT ArmWriteVMBar - EXPORT ArmWriteVBar - EXPORT ArmReadVBar - EXPORT ArmWriteCPACR - EXPORT ArmEnableVFP - EXPORT ArmCallWFI - EXPORT ArmWriteAuxCr - EXPORT ArmReadAuxCr - EXPORT ArmReadCbar - EXPORT ArmInvalidateInstructionAndDataTlb - EXPORT ArmReadMpidr - EXPORT ArmReadTpidrurw - EXPORT ArmWriteTpidrurw - - AREA ArmCacheLib, CODE, READONLY - PRESERVE8 - -DC_ON EQU ( 0x1:SHL:2 ) -IC_ON EQU ( 0x1:SHL:12 ) -CTRL_M_BIT EQU (1 << 0) -CTRL_C_BIT EQU (1 << 2) -CTRL_B_BIT EQU (1 << 7) -CTRL_I_BIT EQU (1 << 12) - - -ArmInvalidateDataCacheEntryByMVA - mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line - dsb - isb - bx lr - - -ArmCleanDataCacheEntryByMVA - mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line - dsb - isb - bx lr - - -ArmCleanInvalidateDataCacheEntryByMVA - mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line - dsb - isb - bx lr - - -ArmInvalidateDataCacheEntryBySetWay - mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line - dsb - isb - bx lr - - -ArmCleanInvalidateDataCacheEntryBySetWay - mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line - dsb - isb - bx lr - - -ArmCleanDataCacheEntryBySetWay - mcr p15, 0, r0, c7, c10, 2 ; Clean this line - dsb - isb - bx lr - - -ArmInvalidateInstructionCache - mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache - isb - bx LR - -ArmEnableMmu - mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) - orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU - mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data) - dsb - isb - bx LR - -ArmMmuEnabled - mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) - and R0,R0,#1 - bx LR - -ArmDisableMmu - mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) - bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU - mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data) - - mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB - mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array - dsb - isb - bx LR - -ArmDisableCachesAndMmu - mrc p15, 0, r0, c1, c0, 0 ; Get control register - bic r0, r0, #CTRL_M_BIT ; Disable MMU - bic r0, r0, #CTRL_C_BIT ; Disable D Cache - bic r0, r0, #CTRL_I_BIT ; Disable I Cache - mcr p15, 0, r0, c1, c0, 0 ; Write control register - dsb - isb - bx LR - -ArmEnableDataCache - ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit - mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) - orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled - mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data) - dsb - isb - bx LR - -ArmDisableDataCache - ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit - mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) - bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled - mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data) - isb - bx LR - -ArmEnableInstructionCache - ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit - mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) - orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled - mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data) - dsb - isb - bx LR - -ArmDisableInstructionCache - ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit - mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) - BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled - mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data) - isb - bx LR - -ArmEnableSWPInstruction - mrc p15, 0, r0, c1, c0, 0 - orr r0, r0, #0x00000400 - mcr p15, 0, r0, c1, c0, 0 - isb - bx LR - -ArmEnableBranchPrediction - mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data) - orr r0, r0, #0x00000800 ; - mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data) - isb - bx LR - -ArmDisableBranchPrediction - mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data) - bic r0, r0, #0x00000800 ; - mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data) - isb - bx LR - -ArmSetLowVectors - mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data) - bic r0, r0, #0x00002000 ; clear V bit - mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data) - isb - bx LR - -ArmSetHighVectors - mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data) - orr r0, r0, #0x00002000 ; clear V bit - mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data) - isb - bx LR - -ArmV7AllDataCachesOperation - stmfd SP!,{r4-r12, LR} - mov R1, R0 ; Save Function call in R1 - mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR - ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC) - mov R3, R3, LSR #23 ; Cache level value (naturally aligned) - beq Finished - mov R10, #0 - -Loop1 - add R2, R10, R10, LSR #1 ; Work out 3xcachelevel - mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level - and R12, R12, #7 ; get those 3 bits alone - cmp R12, #2 - blt Skip ; no cache or only instruction cache at this level - mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction - isb ; isb to sync the change to the CacheSizeID reg - mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR) - and R2, R12, #&7 ; extract the line length field - add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes) - ldr R4, =0x3FF - ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned) - clz R5, R4 ; R5 is the bit position of the way size increment - ldr R7, =0x00007FFF - ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned) - -Loop2 - mov R9, R4 ; R9 working copy of the max way size (right aligned) - -Loop3 - orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11 - orr R0, R0, R7, LSL R2 ; factor in the index number - - blx R1 - - subs R9, R9, #1 ; decrement the way number - bge Loop3 - subs R7, R7, #1 ; decrement the index - bge Loop2 -Skip - add R10, R10, #2 ; increment the cache number - cmp R3, R10 - bgt Loop1 - -Finished - dsb - ldmfd SP!, {r4-r12, lr} - bx LR - - -ArmDataMemoryBarrier - dmb - bx LR - -ArmDataSyncronizationBarrier -ArmDrainWriteBuffer - dsb - bx LR - -ArmInstructionSynchronizationBarrier - isb - bx LR - -ArmWriteNsacr - mcr p15, 0, r0, c1, c1, 2 - bx lr - -ArmWriteScr - mcr p15, 0, r0, c1, c1, 0 - bx lr - -ArmWriteAuxCr - mcr p15, 0, r0, c1, c0, 1 - bx lr - -ArmReadAuxCr - mrc p15, 0, r0, c1, c0, 1 - bx lr - -ArmWriteVMBar - mcr p15, 0, r0, c12, c0, 1 - bx lr - -ArmWriteVBar - // Set the Address of the Vector Table in the VBAR register - mcr p15, 0, r0, c12, c0, 0 - // Ensure the SCTLR.V bit is clear - mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data) - bic r0, r0, #0x00002000 ; clear V bit - mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data) - isb - bx lr - -ArmReadVBar - mrc p15, 0, r0, c12, c0, 0 - bx lr - -ArmWriteCPACR - mcr p15, 0, r0, c1, c0, 2 - bx lr - -ArmEnableVFP - // Read CPACR (Coprocessor Access Control Register) - mrc p15, 0, r0, c1, c0, 2 - // Enable VPF access (Full Access to CP10, CP11) (V* instructions) - orr r0, r0, #0x00f00000 - // Write back CPACR (Coprocessor Access Control Register) - mcr p15, 0, r0, c1, c0, 2 - // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally. - mov r0, #0x40000000 - mcr p10,#0x7,r0,c8,c0,#0 - bx lr - -ArmCallWFI - wfi - bx lr - -//Note: Return 0 in Uniprocessor implementation -ArmReadCbar - mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register - bx lr - -ArmInvalidateInstructionAndDataTlb - mcr p15, 0, r0, c8, c7, 0 ; Invalidate Inst TLB and Data TLB - dsb - bx lr - -ArmReadMpidr - mrc p15, 0, r0, c0, c0, 5 ; read MPIDR - bx lr - -ArmReadTpidrurw - mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW - bx lr - -ArmWriteTpidrurw - mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW - bx lr - - END - +//------------------------------------------------------------------------------ +// +// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
+// Copyright (c) 2011, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +//------------------------------------------------------------------------------ + + EXPORT ArmInvalidateInstructionCache + EXPORT ArmInvalidateDataCacheEntryByMVA + EXPORT ArmCleanDataCacheEntryByMVA + EXPORT ArmCleanInvalidateDataCacheEntryByMVA + EXPORT ArmInvalidateDataCacheEntryBySetWay + EXPORT ArmCleanDataCacheEntryBySetWay + EXPORT ArmCleanInvalidateDataCacheEntryBySetWay + EXPORT ArmDrainWriteBuffer + EXPORT ArmEnableMmu + EXPORT ArmDisableMmu + EXPORT ArmDisableCachesAndMmu + EXPORT ArmMmuEnabled + EXPORT ArmEnableDataCache + EXPORT ArmDisableDataCache + EXPORT ArmEnableInstructionCache + EXPORT ArmDisableInstructionCache + EXPORT ArmEnableSWPInstruction + EXPORT ArmEnableBranchPrediction + EXPORT ArmDisableBranchPrediction + EXPORT ArmSetLowVectors + EXPORT ArmSetHighVectors + EXPORT ArmV7AllDataCachesOperation + EXPORT ArmDataMemoryBarrier + EXPORT ArmDataSyncronizationBarrier + EXPORT ArmInstructionSynchronizationBarrier + EXPORT ArmWriteVBar + EXPORT ArmEnableVFP + EXPORT ArmCallWFI + EXPORT ArmReadCbar + EXPORT ArmInvalidateInstructionAndDataTlb + EXPORT ArmReadMpidr + EXPORT ArmReadTpidrurw + EXPORT ArmWriteTpidrurw + EXPORT ArmIsArchTimerImplemented + EXPORT ArmReadIdPfr1 + + AREA ArmV7Support, CODE, READONLY + PRESERVE8 + +DC_ON EQU ( 0x1:SHL:2 ) +IC_ON EQU ( 0x1:SHL:12 ) +CTRL_M_BIT EQU (1 << 0) +CTRL_C_BIT EQU (1 << 2) +CTRL_B_BIT EQU (1 << 7) +CTRL_I_BIT EQU (1 << 12) + + +ArmInvalidateDataCacheEntryByMVA + mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line + dsb + isb + bx lr + +ArmCleanDataCacheEntryByMVA + mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line + dsb + isb + bx lr + + +ArmCleanInvalidateDataCacheEntryByMVA + mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line + dsb + isb + bx lr + + +ArmInvalidateDataCacheEntryBySetWay + mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line + dsb + isb + bx lr + + +ArmCleanInvalidateDataCacheEntryBySetWay + mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line + dsb + isb + bx lr + + +ArmCleanDataCacheEntryBySetWay + mcr p15, 0, r0, c7, c10, 2 ; Clean this line + dsb + isb + bx lr + + +ArmInvalidateInstructionCache + mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache + isb + bx LR + +ArmEnableMmu + mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) + orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU + mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data) + dsb + isb + bx LR + +ArmDisableMmu + mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) + bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU + mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data) + + mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB + mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array + dsb + isb + bx LR + +ArmDisableCachesAndMmu + mrc p15, 0, r0, c1, c0, 0 ; Get control register + bic r0, r0, #CTRL_M_BIT ; Disable MMU + bic r0, r0, #CTRL_C_BIT ; Disable D Cache + bic r0, r0, #CTRL_I_BIT ; Disable I Cache + mcr p15, 0, r0, c1, c0, 0 ; Write control register + dsb + isb + bx LR + +ArmMmuEnabled + mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) + and R0,R0,#1 + bx LR + +ArmEnableDataCache + ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit + mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) + orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled + mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data) + dsb + isb + bx LR + +ArmDisableDataCache + ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit + mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) + bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled + mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data) + dsb + isb + bx LR + +ArmEnableInstructionCache + ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit + mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) + orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled + mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data) + dsb + isb + bx LR + +ArmDisableInstructionCache + ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit + mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data) + BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled + mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data) + isb + bx LR + +ArmEnableSWPInstruction + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #0x00000400 + mcr p15, 0, r0, c1, c0, 0 + isb + bx LR + +ArmEnableBranchPrediction + mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data) + orr r0, r0, #0x00000800 ; + mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data) + dsb + isb + bx LR + +ArmDisableBranchPrediction + mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data) + bic r0, r0, #0x00000800 ; + mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data) + dsb + isb + bx LR + +ArmSetLowVectors + mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data) + bic r0, r0, #0x00002000 ; clear V bit + mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data) + isb + bx LR + +ArmSetHighVectors + mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data) + orr r0, r0, #0x00002000 ; clear V bit + mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data) + isb + bx LR + +ArmV7AllDataCachesOperation + stmfd SP!,{r4-r12, LR} + mov R1, R0 ; Save Function call in R1 + mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR + ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC) + mov R3, R3, LSR #23 ; Cache level value (naturally aligned) + beq Finished + mov R10, #0 + +Loop1 + add R2, R10, R10, LSR #1 ; Work out 3xcachelevel + mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level + and R12, R12, #7 ; get those 3 bits alone + cmp R12, #2 + blt Skip ; no cache or only instruction cache at this level + mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction + isb ; isb to sync the change to the CacheSizeID reg + mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR) + and R2, R12, #&7 ; extract the line length field + add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes) + ldr R4, =0x3FF + ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned) + clz R5, R4 ; R5 is the bit position of the way size increment + ldr R7, =0x00007FFF + ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned) + +Loop2 + mov R9, R4 ; R9 working copy of the max way size (right aligned) + +Loop3 + orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11 + orr R0, R0, R7, LSL R2 ; factor in the index number + + blx R1 + + subs R9, R9, #1 ; decrement the way number + bge Loop3 + subs R7, R7, #1 ; decrement the index + bge Loop2 +Skip + add R10, R10, #2 ; increment the cache number + cmp R3, R10 + bgt Loop1 + +Finished + dsb + ldmfd SP!, {r4-r12, lr} + bx LR + +ArmDataMemoryBarrier + dmb + bx LR + +ArmDataSyncronizationBarrier +ArmDrainWriteBuffer + dsb + bx LR + +ArmInstructionSynchronizationBarrier + isb + bx LR + +ArmWriteVBar + // Set the Address of the Vector Table in the VBAR register + mcr p15, 0, r0, c12, c0, 0 + // Ensure the SCTLR.V bit is clear + mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data) + bic r0, r0, #0x00002000 ; clear V bit + mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data) + isb + bx lr + +ArmEnableVFP + // Read CPACR (Coprocessor Access Control Register) + mrc p15, 0, r0, c1, c0, 2 + // Enable VPF access (Full Access to CP10, CP11) (V* instructions) + orr r0, r0, #0x00f00000 + // Write back CPACR (Coprocessor Access Control Register) + mcr p15, 0, r0, c1, c0, 2 + // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally. + mov r0, #0x40000000 + mcr p10,#0x7,r0,c8,c0,#0 + bx lr + +ArmCallWFI + wfi + bx lr + +//Note: Return 0 in Uniprocessor implementation +ArmReadCbar + mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register + bx lr + +ArmInvalidateInstructionAndDataTlb + mcr p15, 0, r0, c8, c7, 0 ; Invalidate Inst TLB and Data TLB + dsb + bx lr + +ArmReadMpidr + mrc p15, 0, r0, c0, c0, 5 ; read MPIDR + bx lr + +ArmReadTpidrurw + mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW + bx lr + +ArmWriteTpidrurw + mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW + bx lr + +ArmIsArchTimerImplemented + mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 + and r0, r0, #0x000F0000 + bx lr + +ArmReadIdPfr1 + mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register + bx lr + + END diff --git a/ArmPkg/Library/ArmLib/Common/ArmLib.c b/ArmPkg/Library/ArmLib/Common/ArmLib.c index 2a2c4e86fd..ae1b785608 100644 --- a/ArmPkg/Library/ArmLib/Common/ArmLib.c +++ b/ArmPkg/Library/ArmLib/Common/ArmLib.c @@ -58,3 +58,15 @@ ArmProcessorMode ( { return (ARM_PROCESSOR_MODE)(CPSRRead() & (UINT32)ARM_PROCESSOR_MODE_MASK); } + +VOID +EFIAPI +ArmSetAuxCrBit ( + IN UINT32 Bits + ) +{ + UINT32 val = ArmReadAuxCr(); + val |= Bits; + ArmWriteAuxCr(val); +} + diff --git a/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S index 29ccf6dceb..edd94d2995 100644 --- a/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S +++ b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S @@ -1,124 +1,148 @@ -#------------------------------------------------------------------------------ -# -# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
-# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -#------------------------------------------------------------------------------ - -#include - -.text -.align 2 -GCC_ASM_EXPORT(Cp15IdCode) -GCC_ASM_EXPORT(Cp15CacheInfo) -GCC_ASM_EXPORT(ArmEnableInterrupts) -GCC_ASM_EXPORT(ArmDisableInterrupts) -GCC_ASM_EXPORT(ArmGetInterruptState) -GCC_ASM_EXPORT(ArmEnableFiq) -GCC_ASM_EXPORT(ArmDisableFiq) -GCC_ASM_EXPORT(ArmGetFiqState) -GCC_ASM_EXPORT(ArmInvalidateTlb) -GCC_ASM_EXPORT(ArmSetTTBR0) -GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress) -GCC_ASM_EXPORT(ArmSetDomainAccessControl) -GCC_ASM_EXPORT(CPSRMaskInsert) -GCC_ASM_EXPORT(CPSRRead) - -#------------------------------------------------------------------------------ - -ASM_PFX(Cp15IdCode): - mrc p15,0,R0,c0,c0,0 - bx LR - -ASM_PFX(Cp15CacheInfo): - mrc p15,0,R0,c0,c0,1 - bx LR - -ASM_PFX(ArmEnableInterrupts): - mrs R0,CPSR - bic R0,R0,#0x80 @Enable IRQ interrupts - msr CPSR_c,R0 - bx LR - -ASM_PFX(ArmDisableInterrupts): - mrs R0,CPSR - orr R1,R0,#0x80 @Disable IRQ interrupts - msr CPSR_c,R1 - tst R0,#0x80 - moveq R0,#1 - movne R0,#0 - bx LR - -ASM_PFX(ArmGetInterruptState): - mrs R0,CPSR - tst R0,#0x80 @Check if IRQ is enabled. - moveq R0,#1 - movne R0,#0 - bx LR - -ASM_PFX(ArmEnableFiq): - mrs R0,CPSR - bic R0,R0,#0x40 @Enable FIQ interrupts - msr CPSR_c,R0 - bx LR - -ASM_PFX(ArmDisableFiq): - mrs R0,CPSR - orr R1,R0,#0x40 @Disable FIQ interrupts - msr CPSR_c,R1 - tst R0,#0x80 - moveq R0,#1 - movne R0,#0 - bx LR - -ASM_PFX(ArmGetFiqState): - mrs R0,CPSR - tst R0,#0x80 @Check if FIQ is enabled. - moveq R0,#1 - movne R0,#0 - bx LR - -ASM_PFX(ArmInvalidateTlb): - mov r0,#0 - mcr p15,0,r0,c8,c7,0 - bx lr - -ASM_PFX(ArmSetTTBR0): - mcr p15,0,r0,c2,c0,0 - bx lr - -ASM_PFX(ArmGetTTBR0BaseAddress): - mrc p15,0,r0,c2,c0,0 - LoadConstantToReg(0xFFFFC000, r1) @ and r0, r0, #0xFFFFC000 - and r0, r0, r1 - bx lr - - -ASM_PFX(ArmSetDomainAccessControl): - mcr p15,0,r0,c3,c0,0 - bx lr - -ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert - stmfd sp!, {r4-r12, lr} @ save all the banked registers - mov r3, sp @ copy the stack pointer into a non-banked register - mrs r2, cpsr @ read the cpsr - bic r2, r2, r0 @ clear mask in the cpsr - and r1, r1, r0 @ clear bits outside the mask in the input - orr r2, r2, r1 @ set field - msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch) - mov sp, r3 @ restore stack pointer - ldmfd sp!, {r4-r12, lr} @ restore registers - bx lr @ return (hopefully thumb-safe!) - -ASM_PFX(CPSRRead): - mrs r0, cpsr - bx lr - -ASM_FUNCTION_REMOVE_IF_UNREFERENCED +#------------------------------------------------------------------------------ +# +# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+# Copyright (c) 2011, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#------------------------------------------------------------------------------ + +#include + +#ifdef ARM_CPU_ARMv6 +// No memory barriers for ARMv6 +#define isb +#define dsb +#endif + +.text +.align 2 +GCC_ASM_EXPORT(Cp15IdCode) +GCC_ASM_EXPORT(Cp15CacheInfo) +GCC_ASM_EXPORT(ArmGetInterruptState) +GCC_ASM_EXPORT(ArmGetFiqState) +GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress) +GCC_ASM_EXPORT(ArmSetTTBR0) +GCC_ASM_EXPORT(ArmSetDomainAccessControl) +GCC_ASM_EXPORT(CPSRMaskInsert) +GCC_ASM_EXPORT(CPSRRead) +GCC_ASM_EXPORT(ArmWriteCPACR) +GCC_ASM_EXPORT(ArmWriteAuxCr) +GCC_ASM_EXPORT(ArmReadAuxCr) +GCC_ASM_EXPORT(ArmInvalidateTlb) +GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry) +GCC_ASM_EXPORT(ArmWriteNsacr) +GCC_ASM_EXPORT(ArmWriteScr) +GCC_ASM_EXPORT(ArmWriteVMBar) + +#------------------------------------------------------------------------------ + +ASM_PFX(Cp15IdCode): + mrc p15,0,R0,c0,c0,0 + bx LR + +ASM_PFX(Cp15CacheInfo): + mrc p15,0,R0,c0,c0,1 + bx LR + +ASM_PFX(ArmGetInterruptState): + mrs R0,CPSR + tst R0,#0x80 @Check if IRQ is enabled. + moveq R0,#1 + movne R0,#0 + bx LR + +ASM_PFX(ArmGetFiqState): + mrs R0,CPSR + tst R0,#0x40 @Check if FIQ is enabled. + moveq R0,#1 + movne R0,#0 + bx LR + +ASM_PFX(ArmSetDomainAccessControl): + mcr p15,0,r0,c3,c0,0 + bx lr + +ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert + stmfd sp!, {r4-r12, lr} @ save all the banked registers + mov r3, sp @ copy the stack pointer into a non-banked register + mrs r2, cpsr @ read the cpsr + bic r2, r2, r0 @ clear mask in the cpsr + and r1, r1, r0 @ clear bits outside the mask in the input + orr r2, r2, r1 @ set field + msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch) + isb + mov sp, r3 @ restore stack pointer + ldmfd sp!, {r4-r12, lr} @ restore registers + bx lr @ return (hopefully thumb-safe!) @ return (hopefully thumb-safe!) + +ASM_PFX(CPSRRead): + mrs r0, cpsr + bx lr + +ASM_PFX(ArmWriteCPACR): + mcr p15, 0, r0, c1, c0, 2 + bx lr + +ASM_PFX(ArmWriteAuxCr): + mcr p15, 0, r0, c1, c0, 1 + bx lr + +ASM_PFX(ArmReadAuxCr): + mrc p15, 0, r0, c1, c0, 1 + bx lr + +ASM_PFX(ArmSetTTBR0): + mcr p15,0,r0,c2,c0,0 + isb + bx lr + +ASM_PFX(ArmGetTTBR0BaseAddress): + mrc p15,0,r0,c2,c0,0 + LoadConstantToReg(0xFFFFC000, r1) + and r0, r0, r1 + isb + bx lr + +// +//VOID +//ArmUpdateTranslationTableEntry ( +// IN VOID *TranslationTableEntry // R0 +// IN VOID *MVA // R1 +// ); +ASM_PFX(ArmUpdateTranslationTableEntry): + mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA + dsb + mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA + mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp + dsb + isb + bx lr + +ASM_PFX(ArmInvalidateTlb): + mov r0,#0 + mcr p15,0,r0,c8,c7,0 + mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp + dsb + isb + bx lr + +ASM_PFX(ArmWriteNsacr): + mcr p15, 0, r0, c1, c1, 2 + bx lr + +ASM_PFX(ArmWriteScr): + mcr p15, 0, r0, c1, c1, 0 + bx lr + +ASM_PFX(ArmWriteVMBar): + mcr p15, 0, r0, c12, c0, 1 + bx lr + +ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm index 850bb9691c..3f603873f3 100644 --- a/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm +++ b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm @@ -1,134 +1,148 @@ -//------------------------------------------------------------------------------ -// -// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
-// -// This program and the accompanying materials -// are licensed and made available under the terms and conditions of the BSD License -// which accompanies this distribution. The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -// -//------------------------------------------------------------------------------ - -#include - - INCLUDE AsmMacroIoLib.inc - - EXPORT Cp15IdCode - EXPORT Cp15CacheInfo - EXPORT ArmIsMPCore - EXPORT ArmEnableInterrupts - EXPORT ArmDisableInterrupts - EXPORT ArmGetInterruptState - EXPORT ArmEnableFiq - EXPORT ArmDisableFiq - EXPORT ArmGetFiqState - EXPORT ArmInvalidateTlb - EXPORT ArmSetTTBR0 - EXPORT ArmGetTTBR0BaseAddress - EXPORT ArmSetDomainAccessControl - EXPORT CPSRMaskInsert - EXPORT CPSRRead - - AREA ArmLibSupport, CODE, READONLY - -Cp15IdCode - mrc p15,0,R0,c0,c0,0 - bx LR - -Cp15CacheInfo - mrc p15,0,R0,c0,c0,1 - bx LR - -ArmIsMPCore - mrc p15,0,R0,c0,c0,5 - // Get Multiprocessing extension (bit31) & U bit (bit30) - and R0, R0, #0xC0000000 - // if bit30 == 0 then the processor is part of a multiprocessor system) - and R0, R0, #0x80000000 - bx LR - -ArmEnableInterrupts - mrs R0,CPSR - bic R0,R0,#0x80 ;Enable IRQ interrupts - msr CPSR_c,R0 - bx LR - -ArmDisableInterrupts - mrs R0,CPSR - orr R1,R0,#0x80 ;Disable IRQ interrupts - msr CPSR_c,R1 - tst R0,#0x80 - moveq R0,#1 - movne R0,#0 - bx LR - -ArmGetInterruptState - mrs R0,CPSR - tst R0,#0x80 ;Check if IRQ is enabled. - moveq R0,#1 - movne R0,#0 - bx LR - -ArmEnableFiq - mrs R0,CPSR - bic R0,R0,#0x40 ;Enable IRQ interrupts - msr CPSR_c,R0 - bx LR - -ArmDisableFiq - mrs R0,CPSR - orr R1,R0,#0x40 ;Disable IRQ interrupts - msr CPSR_c,R1 - tst R0,#0x40 - moveq R0,#1 - movne R0,#0 - bx LR - -ArmGetFiqState - mrs R0,CPSR - tst R0,#0x40 ;Check if IRQ is enabled. - moveq R0,#1 - movne R0,#0 - bx LR - -ArmInvalidateTlb - mov r0,#0 - mcr p15,0,r0,c8,c7,0 - bx lr - -ArmSetTTBR0 - mcr p15,0,r0,c2,c0,0 - bx lr - -ArmGetTTBR0BaseAddress - mrc p15,0,r0,c2,c0,0 - LoadConstantToReg(0xFFFFC000,r1) // and r0, r0, #0xFFFFC000 - and r0, r0, r1 - bx lr - -ArmSetDomainAccessControl - mcr p15,0,r0,c3,c0,0 - bx lr - -CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to insert - stmfd sp!, {r4-r12, lr} ; save all the banked registers - mov r3, sp ; copy the stack pointer into a non-banked register - mrs r2, cpsr ; read the cpsr - bic r2, r2, r0 ; clear mask in the cpsr - and r1, r1, r0 ; clear bits outside the mask in the input - orr r2, r2, r1 ; set field - msr cpsr_cxsf, r2 ; write back cpsr (may have caused a mode switch) - mov sp, r3 ; restore stack pointer - ldmfd sp!, {r4-r12, lr} ; restore registers - bx lr ; return (hopefully thumb-safe!) - -CPSRRead - mrs r0, cpsr - bx lr - - END - - +//------------------------------------------------------------------------------ +// +// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+// Copyright (c) 2011, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +//------------------------------------------------------------------------------ + +#include + + INCLUDE AsmMacroIoLib.inc + +#ifdef ARM_CPU_ARMv6 +// No memory barriers for ARMv6 +#define isb +#define dsb +#endif + + EXPORT Cp15IdCode + EXPORT Cp15CacheInfo + EXPORT ArmGetInterruptState + EXPORT ArmGetFiqState + EXPORT ArmGetTTBR0BaseAddress + EXPORT ArmSetTTBR0 + EXPORT ArmSetDomainAccessControl + EXPORT CPSRMaskInsert + EXPORT CPSRRead + EXPORT ArmWriteCPACR + EXPORT ArmWriteAuxCr + EXPORT ArmReadAuxCr + EXPORT ArmInvalidateTlb + EXPORT ArmUpdateTranslationTableEntry + EXPORT ArmWriteNsacr + EXPORT ArmWriteScr + EXPORT ArmWriteVMBar + + AREA ArmLibSupport, CODE, READONLY + +Cp15IdCode + mrc p15,0,R0,c0,c0,0 + bx LR + +Cp15CacheInfo + mrc p15,0,R0,c0,c0,1 + bx LR + +ArmGetInterruptState + mrs R0,CPSR + tst R0,#0x80 // Check if IRQ is enabled. + moveq R0,#1 + movne R0,#0 + bx LR + +ArmGetFiqState + mrs R0,CPSR + tst R0,#0x40 // Check if FIQ is enabled. + moveq R0,#1 + movne R0,#0 + bx LR + +ArmSetDomainAccessControl + mcr p15,0,r0,c3,c0,0 + bx lr + +CPSRMaskInsert // on entry, r0 is the mask and r1 is the field to insert + stmfd sp!, {r4-r12, lr} // save all the banked registers + mov r3, sp // copy the stack pointer into a non-banked register + mrs r2, cpsr // read the cpsr + bic r2, r2, r0 // clear mask in the cpsr + and r1, r1, r0 // clear bits outside the mask in the input + orr r2, r2, r1 // set field + msr cpsr_cxsf, r2 // write back cpsr (may have caused a mode switch) + isb + mov sp, r3 // restore stack pointer + ldmfd sp!, {r4-r12, lr} // restore registers + bx lr // return (hopefully thumb-safe!) // return (hopefully thumb-safe!) + +CPSRRead + mrs r0, cpsr + bx lr + +ArmWriteCPACR + mcr p15, 0, r0, c1, c0, 2 + bx lr + +ArmWriteAuxCr + mcr p15, 0, r0, c1, c0, 1 + bx lr + +ArmReadAuxCr + mrc p15, 0, r0, c1, c0, 1 + bx lr + +ArmSetTTBR0 + mcr p15,0,r0,c2,c0,0 + isb + bx lr + +ArmGetTTBR0BaseAddress + mrc p15,0,r0,c2,c0,0 + LoadConstantToReg(0xFFFFC000, r1) + and r0, r0, r1 + isb + bx lr + +// +//VOID +//ArmUpdateTranslationTableEntry ( +// IN VOID *TranslationTableEntry // R0 +// IN VOID *MVA // R1 +// ); +ArmUpdateTranslationTableEntry + mcr p15,0,R0,c7,c14,1 // DCCIMVAC Clean data cache by MVA + dsb + mcr p15,0,R1,c8,c7,1 // TLBIMVA TLB Invalidate MVA + mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp + dsb + isb + bx lr + +ArmInvalidateTlb + mov r0,#0 + mcr p15,0,r0,c8,c7,0 + mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp + dsb + isb + bx lr + +ArmWriteNsacr + mcr p15, 0, r0, c1, c1, 2 + bx lr + +ArmWriteScr + mcr p15, 0, r0, c1, c1, 0 + bx lr + +ArmWriteVMBar + mcr p15, 0, r0, c12, c0, 1 + bx lr + + END -- cgit v1.2.3