From ce6aec3ea31270d40ceb64739c5558bee8a09b01 Mon Sep 17 00:00:00 2001 From: Eugene Cohen Date: Tue, 1 Dec 2015 18:39:29 +0000 Subject: ArmPkg: Convert whole-cache InvalidateInstructionCache to just ASSERT In SVN 18756 ("disallow whole D-cache maintenance operations") InvalidateInstructionCache was modified to remove the full data cache clean but left the full instruction cache invalidate. The change was made to address issues in the set/way clean methodology but the resulting code could lead someone to a painful debug. If a component called this function, the proper code would not be flushed to the PoU, since the intent of this function is not only to invalidate the I-cache but to provide coherency after code loading / modification. This change simply places an ASSERT(FALSE) in this function to avoid this hazard. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen Reviewed-by: Ard Biesheuvel git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19084 6f19259b-4bc3-4df7-8a09-765794883524 --- ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'ArmPkg') diff --git a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c index 65ba8749e7..feab4497ac 100644 --- a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c +++ b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c @@ -45,7 +45,7 @@ InvalidateInstructionCache ( VOID ) { - ArmInvalidateInstructionCache(); + ASSERT (FALSE); } VOID -- cgit v1.2.3