From 7809daf1046ca96896130038402054a8ace671e7 Mon Sep 17 00:00:00 2001 From: Guo Mang Date: Thu, 22 Dec 2016 18:10:17 +0800 Subject: ArmPlatformPkg: Remove unused Package Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang --- .../ArmJunoPkg/Drivers/ArmJunoDxe/AcpiTables.c | 78 --- .../ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c | 562 ---------------- .../ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf | 95 --- .../Drivers/ArmJunoDxe/ArmJunoDxeInternal.h | 46 -- .../ArmJunoPkg/Drivers/ArmJunoDxe/PciEmulation.c | 596 ----------------- .../ArmJunoPkg/Drivers/ArmJunoDxe/PciEmulation.h | 284 -------- .../Drivers/ArmJunoDxe/PciRootBridgeIo.c | 299 --------- .../Drivers/PciHostBridgeDxe/PciHostBridge.c | 199 ------ .../Drivers/PciHostBridgeDxe/PciHostBridge.h | 324 --------- .../Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf | 76 --- .../PciHostBridgeResourceAllocation.c | 642 ------------------ .../Drivers/PciHostBridgeDxe/PciRootBridge.c | 745 --------------------- .../Drivers/PciHostBridgeDxe/XPressRich3.c | 167 ----- .../Drivers/PciHostBridgeDxe/XPressRich3.h | 111 --- 14 files changed, 4224 deletions(-) delete mode 100644 ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/AcpiTables.c delete mode 100644 ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c delete mode 100644 ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf delete mode 100644 ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxeInternal.h delete mode 100644 ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciEmulation.c delete mode 100644 ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciEmulation.h delete mode 100644 ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciRootBridgeIo.c delete mode 100644 ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridge.c delete mode 100644 ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridge.h delete mode 100644 ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf delete mode 100644 ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridgeResourceAllocation.c delete mode 100644 ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciRootBridge.c delete mode 100644 ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c delete mode 100644 ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.h (limited to 'ArmPlatformPkg/ArmJunoPkg/Drivers') diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/AcpiTables.c b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/AcpiTables.c deleted file mode 100644 index bf08346434..0000000000 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/AcpiTables.c +++ /dev/null @@ -1,78 +0,0 @@ -/** @file - - This file contains support for ACPI Tables that are generated at boot time. - - Copyright (c) 2015, ARM Ltd. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include "ArmPlatform.h" -#include "ArmJunoDxeInternal.h" - -#include - -/* - * Memory Mapped Configuration Space Access Table (MCFG) - */ -typedef struct { - EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header; - EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Entry; -} MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ACCESS_TABLE; - -MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ACCESS_TABLE mAcpiMcfgTable = { - { - ARM_ACPI_HEADER ( - EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, - MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ACCESS_TABLE, - EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION - ), - 0, // Reserved - }, { - FixedPcdGet32 (PcdPciConfigurationSpaceBaseAddress), - 0, // PciSegmentGroupNumber - FixedPcdGet32 (PcdPciBusMin), - FixedPcdGet32 (PcdPciBusMax), - 0 // Reserved; - } -}; - -/** - * Callback called when ACPI Protocol is installed - */ -VOID -AcpiPciNotificationEvent ( - IN EFI_EVENT Event, - IN VOID *Context - ) -{ - EFI_STATUS Status; - EFI_ACPI_TABLE_PROTOCOL *AcpiTableProtocol; - UINTN AcpiTableKey; - - // - // Ensure the ACPI protocol is installed - // - Status = gBS->LocateProtocol ( - &gEfiAcpiTableProtocolGuid, - NULL, - (VOID**)&AcpiTableProtocol - ); - if (EFI_ERROR (Status)) { - return; - } - - // - // Install MCFG Table - // - AcpiTableKey = 0; - Status = AcpiTableProtocol->InstallAcpiTable (AcpiTableProtocol, &mAcpiMcfgTable, sizeof (mAcpiMcfgTable), &AcpiTableKey); - ASSERT_EFI_ERROR (Status); -} diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c deleted file mode 100644 index 756c2751e1..0000000000 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c +++ /dev/null @@ -1,562 +0,0 @@ -/** @file -* -* Copyright (c) 2013-2015, ARM Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#include "ArmJunoDxeInternal.h" -#include - -#include -#include - -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -// -// Size in number of characters of the Linux boot argument -// passing the MAC address to be used by the PCI GigaByte -// Ethernet device : " sky2.mac_address=0x11,0x22,0x33,0x44,0x55,0x66" -// -#define SKY2_MAC_ADDRESS_BOOTARG_LEN 47 - -// -// Hardware platform identifiers -// -typedef enum { - UNKNOWN, - JUNO_R0, - JUNO_R1 -} JUNO_REVISION; - -// -// Function prototypes -// -STATIC EFI_STATUS SetJunoR1DefaultBootEntries ( - VOID - ); - -// This GUID must match the FILE_GUID in ArmPlatformPkg/ArmJunoPkg/AcpiTables/AcpiTables.inf -STATIC CONST EFI_GUID mJunoAcpiTableFile = { 0xa1dd808e, 0x1e95, 0x4399, { 0xab, 0xc0, 0x65, 0x3c, 0x82, 0xe8, 0x53, 0x0c } }; - -typedef struct { - ACPI_HID_DEVICE_PATH AcpiDevicePath; - PCI_DEVICE_PATH PciDevicePath; - EFI_DEVICE_PATH_PROTOCOL EndDevicePath; -} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; - -STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mPciRootComplexDevicePath = { - { - { ACPI_DEVICE_PATH, - ACPI_DP, - { (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), - (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) } - }, - EISA_PNP_ID (0x0A03), - 0 - }, - { - { HARDWARE_DEVICE_PATH, - HW_PCI_DP, - { (UINT8) (sizeof (PCI_DEVICE_PATH)), - (UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) } - }, - 0, - 0 - }, - { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - { END_DEVICE_PATH_LENGTH, 0 } - } -}; - -EFI_EVENT mAcpiRegistration = NULL; - -/** - * Build and Set UEFI Variable Boot#### - * - * @param BootVariableName Name of the UEFI Variable - * @param Attributes 'Attributes' for the Boot#### variable as per UEFI spec - * @param BootDescription Description of the Boot#### variable - * @param DevicePath EFI Device Path of the EFI Application to boot - * @param OptionalData Parameters to pass to the EFI application - * @param OptionalDataSize Size of the parameters to pass to the EFI application - * - * @return EFI_OUT_OF_RESOURCES A memory allocation failed - * @return Return value of RT.SetVariable - */ -STATIC -EFI_STATUS -BootOptionCreate ( - IN CHAR16 BootVariableName[9], - IN UINT32 Attributes, - IN CHAR16* BootDescription, - IN EFI_DEVICE_PATH_PROTOCOL* DevicePath, - IN UINT8* OptionalData, - IN UINTN OptionalDataSize - ) -{ - UINTN VariableSize; - UINT8 *Variable; - UINT8 *VariablePtr; - UINTN FilePathListLength; - UINTN BootDescriptionSize; - - FilePathListLength = GetDevicePathSize (DevicePath); - BootDescriptionSize = StrSize (BootDescription); - - // Each Boot#### variable is built as follow: - // UINT32 Attributes - // UINT16 FilePathListLength - // CHAR16* Description - // EFI_DEVICE_PATH_PROTOCOL FilePathList[] - // UINT8 OptionalData[] - VariableSize = sizeof (UINT32) + sizeof (UINT16) + - BootDescriptionSize + FilePathListLength + OptionalDataSize; - Variable = AllocateZeroPool (VariableSize); - if (Variable == NULL) { - return EFI_OUT_OF_RESOURCES; - } - - // 'Attributes' field - *(UINT32*)Variable = Attributes; - // 'FilePathListLength' field - VariablePtr = Variable + sizeof (UINT32); - *(UINT16*)VariablePtr = FilePathListLength; - // 'Description' field - VariablePtr += sizeof (UINT16); - CopyMem (VariablePtr, BootDescription, BootDescriptionSize); - // 'FilePathList' field - VariablePtr += BootDescriptionSize; - CopyMem (VariablePtr, DevicePath, FilePathListLength); - // 'OptionalData' field - VariablePtr += FilePathListLength; - CopyMem (VariablePtr, OptionalData, OptionalDataSize); - - return gRT->SetVariable ( - BootVariableName, - &gEfiGlobalVariableGuid, - EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, - VariableSize, Variable - ); -} - -/** - Notification function of the event defined as belonging to the - EFI_END_OF_DXE_EVENT_GROUP_GUID event group that was created in - the entry point of the driver. - - This function is called when an event belonging to the - EFI_END_OF_DXE_EVENT_GROUP_GUID event group is signalled. Such an - event is signalled once at the end of the dispatching of all - drivers (end of the so called DXE phase). - - @param[in] Event Event declared in the entry point of the driver whose - notification function is being invoked. - @param[in] Context NULL -**/ -STATIC -VOID -OnEndOfDxe ( - IN EFI_EVENT Event, - IN VOID *Context - ) -{ - EFI_DEVICE_PATH_PROTOCOL* PciRootComplexDevicePath; - EFI_HANDLE Handle; - EFI_STATUS Status; - - // - // PCI Root Complex initialization - // At the end of the DXE phase, we should get all the driver dispatched. - // Force the PCI Root Complex to be initialized. It allows the OS to skip - // this step. - // - PciRootComplexDevicePath = (EFI_DEVICE_PATH_PROTOCOL*) &mPciRootComplexDevicePath; - Status = gBS->LocateDevicePath (&gEfiPciRootBridgeIoProtocolGuid, - &PciRootComplexDevicePath, - &Handle); - - Status = gBS->ConnectController (Handle, NULL, PciRootComplexDevicePath, FALSE); - ASSERT_EFI_ERROR (Status); -} - -STATIC -BOOLEAN -AcpiTableJunoR0Check ( - IN EFI_ACPI_DESCRIPTION_HEADER *AcpiHeader - ) -{ - return TRUE; -} - -STATIC -BOOLEAN -AcpiTableJunoR1Check ( - IN EFI_ACPI_DESCRIPTION_HEADER *AcpiHeader - ) -{ - return TRUE; -} - -EFI_STATUS -EFIAPI -ArmJunoEntryPoint ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - EFI_PHYSICAL_ADDRESS HypBase; - CHAR16 *TextDevicePath; - UINTN TextDevicePathSize; - VOID *Buffer; - UINT32 Midr; - UINT32 CpuType; - UINT32 CpuRev; - JUNO_REVISION JunoRevision; - EFI_EVENT EndOfDxeEvent; - - JunoRevision = UNKNOWN; - Status = PciEmulationEntryPoint (); - if (EFI_ERROR (Status)) { - return Status; - } - - // - // If a hypervisor has been declared then we need to make sure its region is protected at runtime - // - // Note: This code is only a workaround for our dummy hypervisor (ArmPkg/Extra/AArch64ToAArch32Shim/) - // that does not set up (yet) the stage 2 translation table to hide its own memory to EL1. - // - if (FixedPcdGet32 (PcdHypFvSize) != 0) { - // Ensure the hypervisor region is strictly contained into a EFI_PAGE_SIZE-aligned region. - // The memory must be a multiple of EFI_PAGE_SIZE to ensure we do not reserve more memory than the hypervisor itself. - // A UEFI Runtime region size granularity cannot be smaller than EFI_PAGE_SIZE. If the hypervisor size is not rounded - // to this size then there is a risk some non-runtime memory could be visible to the OS view. - if (((FixedPcdGet32 (PcdHypFvSize) & EFI_PAGE_MASK) == 0) && ((FixedPcdGet32 (PcdHypFvBaseAddress) & EFI_PAGE_MASK) == 0)) { - // The memory needs to be declared because the DXE core marked it as reserved and removed it from the memory space - // as it contains the Firmware. - Status = gDS->AddMemorySpace ( - EfiGcdMemoryTypeSystemMemory, - FixedPcdGet32 (PcdHypFvBaseAddress), FixedPcdGet32 (PcdHypFvSize), - EFI_MEMORY_WB | EFI_MEMORY_RUNTIME - ); - if (!EFI_ERROR (Status)) { - // We allocate the memory to ensure it is marked as runtime memory - HypBase = FixedPcdGet32 (PcdHypFvBaseAddress); - Status = gBS->AllocatePages (AllocateAddress, EfiRuntimeServicesCode, - EFI_SIZE_TO_PAGES (FixedPcdGet32 (PcdHypFvSize)), &HypBase); - } - } else { - // The hypervisor must be contained into a EFI_PAGE_SIZE-aligned region and its size must also be aligned - // on a EFI_PAGE_SIZE boundary (ie: 4KB). - Status = EFI_UNSUPPORTED; - ASSERT_EFI_ERROR (Status); - } - - if (EFI_ERROR (Status)) { - return Status; - } - } - - // - // Create an event belonging to the "gEfiEndOfDxeEventGroupGuid" group. - // The "OnEndOfDxe()" function is declared as the call back function. - // It will be called at the end of the DXE phase when an event of the - // same group is signalled to inform about the end of the DXE phase. - // Install the INSTALL_FDT_PROTOCOL protocol. - // - Status = gBS->CreateEventEx ( - EVT_NOTIFY_SIGNAL, - TPL_CALLBACK, - OnEndOfDxe, - NULL, - &gEfiEndOfDxeEventGroupGuid, - &EndOfDxeEvent - ); - - // Install dynamic Shell command to run baremetal binaries. - Status = ShellDynCmdRunAxfInstall (ImageHandle); - if (EFI_ERROR (Status)) { - DEBUG ((EFI_D_ERROR, "ArmJunoDxe: Failed to install ShellDynCmdRunAxf\n")); - } - - // - // We detect whether we are running on a Juno r0 or Juno r1 board at - // runtime by checking the value of the MIDR register. - // - - Midr = ArmReadMidr (); - CpuType = (Midr >> ARM_CPU_TYPE_SHIFT) & ARM_CPU_TYPE_MASK; - CpuRev = Midr & ARM_CPU_REV_MASK; - - switch (CpuType) { - case ARM_CPU_TYPE_A53: - if (CpuRev == ARM_CPU_REV (0, 0)) { - JunoRevision = JUNO_R0; - } else if (CpuRev == ARM_CPU_REV (0, 3)) { - JunoRevision = JUNO_R1; - } - break; - - case ARM_CPU_TYPE_A57: - if (CpuRev == ARM_CPU_REV (0, 0)) { - JunoRevision = JUNO_R0; - } else if (CpuRev == ARM_CPU_REV (1, 1)) { - JunoRevision = JUNO_R1; - } - } - - // - // Try to install the ACPI Tables - // - if (JunoRevision == JUNO_R0) { - Status = LocateAndInstallAcpiFromFvConditional (&mJunoAcpiTableFile, AcpiTableJunoR0Check); - } else if (JunoRevision == JUNO_R1) { - Status = LocateAndInstallAcpiFromFvConditional (&mJunoAcpiTableFile, AcpiTableJunoR1Check); - } - ASSERT_EFI_ERROR (Status); - - - // - // Set the R1 two boot options if not already done. - // - if (JunoRevision == JUNO_R1) { - Status = SetJunoR1DefaultBootEntries (); - if (EFI_ERROR (Status)) { - return Status; - } - - // Enable PCI enumeration - PcdSetBool (PcdPciDisableBusEnumeration, FALSE); - - // Declare the related ACPI Tables - EfiCreateProtocolNotifyEvent ( - &gEfiAcpiTableProtocolGuid, - TPL_CALLBACK, - AcpiPciNotificationEvent, - NULL, - &mAcpiRegistration - ); - } - - // - // Set up the device path to the FDT. - // - switch (JunoRevision) { - case JUNO_R0: - TextDevicePath = (CHAR16*)FixedPcdGetPtr (PcdJunoR0FdtDevicePath); - break; - - case JUNO_R1: - TextDevicePath = (CHAR16*)FixedPcdGetPtr (PcdJunoR1A57x2FdtDevicePath); - break; - - default: - TextDevicePath = NULL; - } - - if (TextDevicePath != NULL) { - TextDevicePathSize = StrSize (TextDevicePath); - Buffer = PcdSetPtr (PcdFdtDevicePaths, &TextDevicePathSize, TextDevicePath); - Status = (Buffer != NULL) ? EFI_SUCCESS : EFI_BUFFER_TOO_SMALL; - } else { - Status = EFI_NOT_FOUND; - } - - if (EFI_ERROR (Status)) { - DEBUG ( - (EFI_D_ERROR, - "ArmJunoDxe: Setting of FDT device path in PcdFdtDevicePaths failed - %r\n", Status) - ); - return Status; - } - - return Status; -} - -/** - * If no boot entry is currently defined, define the two default boot entries - * for Juno R1. - * - * @return EFI_SUCCESS Some boot entries were already defined or - * the default boot entries were set successfully. - * @return EFI_OUT_OF_RESOURCES A memory allocation failed. - * @return EFI_DEVICE_ERROR An UEFI variable could not be saved due to a hardware failure. - * @return EFI_WRITE_PROTECTED An UEFI variable is read-only. - * @return EFI_SECURITY_VIOLATION An UEFI variable could not be written. - */ -STATIC -EFI_STATUS -SetJunoR1DefaultBootEntries ( - VOID - ) -{ - EFI_STATUS Status; - CONST CHAR16* ExtraBootArgument = L" dtb=r1a57a53.dtb"; - UINTN Size; - EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL *EfiDevicePathFromTextProtocol; - EFI_DEVICE_PATH* BootDevicePath; - UINT32 SysPciGbeL; - UINT32 SysPciGbeH; - CHAR16* DefaultBootArgument; - CHAR16* DefaultBootArgument1; - UINTN DefaultBootArgument1Size; - CHAR16* DefaultBootArgument2; - UINTN DefaultBootArgument2Size; - UINT16 BootOrder[2]; - - BootDevicePath = NULL; - DefaultBootArgument1 = NULL; - DefaultBootArgument2 = NULL; - - // - // Because the driver has a dependency on gEfiVariable(Write)ArchProtocolGuid - // (see [Depex] section of the INF file), we know we can safely access the - // UEFI Variable at that stage. - // - Size = 0; - Status = gRT->GetVariable (L"BootOrder", &gEfiGlobalVariableGuid, NULL, &Size, NULL); - if (Status != EFI_NOT_FOUND) { - return EFI_SUCCESS; - } - - Status = gBS->LocateProtocol ( - &gEfiDevicePathFromTextProtocolGuid, - NULL, - (VOID **)&EfiDevicePathFromTextProtocol - ); - if (EFI_ERROR (Status)) { - // - // You must provide an implementation of DevicePathFromTextProtocol - // in your firmware (eg: DevicePathDxe) - // - DEBUG ((EFI_D_ERROR, "Error: Require DevicePathFromTextProtocol\n")); - return Status; - } - // - // We use the same default kernel. - // - BootDevicePath = EfiDevicePathFromTextProtocol->ConvertTextToDevicePath ( - (CHAR16*)PcdGetPtr (PcdDefaultBootDevicePath) - ); - if (BootDevicePath == NULL) { - return EFI_UNSUPPORTED; - } - - DefaultBootArgument = (CHAR16*)PcdGetPtr (PcdDefaultBootArgument); - DefaultBootArgument1Size = StrSize (DefaultBootArgument) + - (SKY2_MAC_ADDRESS_BOOTARG_LEN * sizeof (CHAR16)); - DefaultBootArgument2Size = DefaultBootArgument1Size + StrSize (ExtraBootArgument); - - Status = EFI_OUT_OF_RESOURCES; - DefaultBootArgument1 = AllocatePool (DefaultBootArgument1Size); - if (DefaultBootArgument1 == NULL) { - goto Error; - } - DefaultBootArgument2 = AllocatePool (DefaultBootArgument2Size); - if (DefaultBootArgument2 == NULL) { - goto Error; - } - - SysPciGbeL = MmioRead32 (ARM_JUNO_SYS_PCIGBE_L); - SysPciGbeH = MmioRead32 (ARM_JUNO_SYS_PCIGBE_H); - - UnicodeSPrint ( - DefaultBootArgument1, - DefaultBootArgument1Size, - L"%s sky2.mac_address=0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x", - DefaultBootArgument, - (SysPciGbeH >> 8 ) & 0xFF, (SysPciGbeH ) & 0xFF, - (SysPciGbeL >> 24) & 0xFF, (SysPciGbeL >> 16) & 0xFF, - (SysPciGbeL >> 8 ) & 0xFF, (SysPciGbeL ) & 0xFF - ); - - CopyMem (DefaultBootArgument2, DefaultBootArgument1, DefaultBootArgument1Size); - CopyMem ( - (UINT8*)DefaultBootArgument2 + DefaultBootArgument1Size - sizeof (CHAR16), - ExtraBootArgument, - StrSize (ExtraBootArgument) - ); - - // - // Create Boot0001 environment variable - // - Status = BootOptionCreate ( - L"Boot0001", LOAD_OPTION_ACTIVE | LOAD_OPTION_CATEGORY_BOOT, - L"Linux with A57x2", BootDevicePath, - (UINT8*)DefaultBootArgument1, DefaultBootArgument1Size - ); - if (EFI_ERROR (Status)) { - ASSERT_EFI_ERROR (Status); - goto Error; - } - - // - // Create Boot0002 environment variable - // - Status = BootOptionCreate ( - L"Boot0002", LOAD_OPTION_ACTIVE | LOAD_OPTION_CATEGORY_BOOT, - L"Linux with A57x2_A53x4", BootDevicePath, - (UINT8*)DefaultBootArgument2, DefaultBootArgument2Size - ); - if (EFI_ERROR (Status)) { - ASSERT_EFI_ERROR (Status); - goto Error; - } - - // - // Add the new Boot Index to the list - // - BootOrder[0] = 1; // Boot0001 - BootOrder[1] = 2; // Boot0002 - Status = gRT->SetVariable ( - L"BootOrder", - &gEfiGlobalVariableGuid, - EFI_VARIABLE_NON_VOLATILE | - EFI_VARIABLE_BOOTSERVICE_ACCESS | - EFI_VARIABLE_RUNTIME_ACCESS, - sizeof (BootOrder), - BootOrder - ); - -Error: - if (BootDevicePath != NULL) { - FreePool (BootDevicePath); - } - if (DefaultBootArgument1 != NULL) { - FreePool (DefaultBootArgument1); - } - if (DefaultBootArgument2 != NULL) { - FreePool (DefaultBootArgument2); - } - - if (EFI_ERROR (Status)) { - DEBUG (( - EFI_D_ERROR, - "ArmJunoDxe - The setting of the default boot entries failed - %r\n", - Status - )); - } - - return Status; -} diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf deleted file mode 100644 index 6157f9807f..0000000000 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf +++ /dev/null @@ -1,95 +0,0 @@ -# -# Copyright (c) 2013-2015, ARM Limited. All rights reserved. -# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = ArmJunoDxe - FILE_GUID = 1484ebe8-2681-45f1-a2e5-12ecad893b62 - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - ENTRY_POINT = ArmJunoEntryPoint - -[Sources.common] - AcpiTables.c - ArmJunoDxe.c - PciEmulation.c - PciRootBridgeIo.c - -[Packages] - ArmPkg/ArmPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec - ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec - EmbeddedPkg/EmbeddedPkg.dec - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - -[LibraryClasses] - AcpiLib - ArmLib - ArmShellCmdRunAxfLib - BaseMemoryLib - BdsLib - DebugLib - DmaLib - DxeServicesTableLib - IoLib - PcdLib - PrintLib - SerialPortLib - UefiBootServicesTableLib - UefiRuntimeServicesTableLib - UefiLib - UefiDriverEntryPoint - -[Guids] - gArmGlobalVariableGuid - gEfiEndOfDxeEventGroupGuid - gEfiFileInfoGuid - -[Protocols] - gEfiBlockIoProtocolGuid - gEfiDevicePathFromTextProtocolGuid - gEfiPciIoProtocolGuid - gEfiPciRootBridgeIoProtocolGuid - gEfiSimpleFileSystemProtocolGuid - gEfiAcpiTableProtocolGuid - -[FixedPcd] - gArmTokenSpaceGuid.PcdSystemMemoryBase - gArmTokenSpaceGuid.PcdSystemMemorySize - - gArmTokenSpaceGuid.PcdHypFvBaseAddress - gArmTokenSpaceGuid.PcdHypFvSize - - gArmJunoTokenSpaceGuid.PcdSynopsysUsbEhciBaseAddress - gArmJunoTokenSpaceGuid.PcdSynopsysUsbOhciBaseAddress - - gArmJunoTokenSpaceGuid.PcdJunoR0FdtDevicePath - gArmJunoTokenSpaceGuid.PcdJunoR1A57x2FdtDevicePath - gArmJunoTokenSpaceGuid.PcdJunoR1A57x2A53x4FdtDevicePath - - gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath - gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument - - # PCI Root complex specific PCDs - gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress - gArmPlatformTokenSpaceGuid.PcdPciBusMin - gArmPlatformTokenSpaceGuid.PcdPciBusMax - -[Pcd] - gEmbeddedTokenSpaceGuid.PcdFdtDevicePaths - gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration - -[Depex] - # We depend on these protocols to create the default boot entries - gEfiVariableArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxeInternal.h b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxeInternal.h deleted file mode 100644 index 662c41377f..0000000000 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxeInternal.h +++ /dev/null @@ -1,46 +0,0 @@ -/** @file -* -* Copyright (c) 2013-2015, ARM Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#ifndef __ARM_JUNO_DXE_INTERNAL_H__ -#define __ARM_JUNO_DXE_INTERNAL_H__ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include - -EFI_STATUS -PciEmulationEntryPoint ( - VOID - ); - -/** - * Callback called when ACPI Protocol is installed - */ -VOID -AcpiPciNotificationEvent ( - IN EFI_EVENT Event, - IN VOID *Context - ); - -#endif // __ARM_JUNO_DXE_INTERNAL_H__ diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciEmulation.c b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciEmulation.c deleted file mode 100644 index 2ddebf606e..0000000000 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciEmulation.c +++ /dev/null @@ -1,596 +0,0 @@ -/** @file - - Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
- Copyright (c) 2013 - 2014, ARM Ltd. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include "PciEmulation.h" - -#define HOST_CONTROLLER_OPERATION_REG_SIZE 0x44 - -typedef struct { - ACPI_HID_DEVICE_PATH AcpiDevicePath; - PCI_DEVICE_PATH PciDevicePath; - EFI_DEVICE_PATH_PROTOCOL EndDevicePath; -} EFI_PCI_IO_DEVICE_PATH; - -typedef struct { - UINT32 Signature; - EFI_PCI_IO_DEVICE_PATH DevicePath; - EFI_PCI_IO_PROTOCOL PciIoProtocol; - PCI_TYPE00 *ConfigSpace; - PCI_ROOT_BRIDGE RootBridge; - UINTN Segment; -} EFI_PCI_IO_PRIVATE_DATA; - -#define EFI_PCI_IO_PRIVATE_DATA_SIGNATURE SIGNATURE_32('p', 'c', 'i', 'o') -#define EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(a) CR (a, EFI_PCI_IO_PRIVATE_DATA, PciIoProtocol, EFI_PCI_IO_PRIVATE_DATA_SIGNATURE) - -EFI_PCI_IO_DEVICE_PATH PciIoDevicePathTemplate = -{ - { - { ACPI_DEVICE_PATH, ACPI_DP, { sizeof (ACPI_HID_DEVICE_PATH), 0 } }, - EISA_PNP_ID(0x0A03), // HID - 0 // UID - }, - { - { HARDWARE_DEVICE_PATH, HW_PCI_DP, { sizeof (PCI_DEVICE_PATH), 0 } }, - 0, - 0 - }, - { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0} } -}; - -STATIC -VOID -ConfigureUSBHost ( - VOID - ) -{ -} - - -EFI_STATUS -PciIoPollMem ( - IN EFI_PCI_IO_PROTOCOL *This, - IN EFI_PCI_IO_PROTOCOL_WIDTH Width, - IN UINT8 BarIndex, - IN UINT64 Offset, - IN UINT64 Mask, - IN UINT64 Value, - IN UINT64 Delay, - OUT UINT64 *Result - ) -{ - ASSERT (FALSE); - return EFI_UNSUPPORTED; -} - -EFI_STATUS -PciIoPollIo ( - IN EFI_PCI_IO_PROTOCOL *This, - IN EFI_PCI_IO_PROTOCOL_WIDTH Width, - IN UINT8 BarIndex, - IN UINT64 Offset, - IN UINT64 Mask, - IN UINT64 Value, - IN UINT64 Delay, - OUT UINT64 *Result - ) -{ - ASSERT (FALSE); - return EFI_UNSUPPORTED; -} - -EFI_STATUS -PciIoMemRead ( - IN EFI_PCI_IO_PROTOCOL *This, - IN EFI_PCI_IO_PROTOCOL_WIDTH Width, - IN UINT8 BarIndex, - IN UINT64 Offset, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This); - - return PciRootBridgeIoMemRead (&Private->RootBridge.Io, - (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, - Private->ConfigSpace->Device.Bar[BarIndex] + Offset, //Fix me ConfigSpace - Count, - Buffer - ); -} - -EFI_STATUS -PciIoMemWrite ( - IN EFI_PCI_IO_PROTOCOL *This, - IN EFI_PCI_IO_PROTOCOL_WIDTH Width, - IN UINT8 BarIndex, - IN UINT64 Offset, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This); - - return PciRootBridgeIoMemWrite (&Private->RootBridge.Io, - (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, - Private->ConfigSpace->Device.Bar[BarIndex] + Offset, //Fix me ConfigSpace - Count, - Buffer - ); -} - -EFI_STATUS -PciIoIoRead ( - IN EFI_PCI_IO_PROTOCOL *This, - IN EFI_PCI_IO_PROTOCOL_WIDTH Width, - IN UINT8 BarIndex, - IN UINT64 Offset, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - ASSERT (FALSE); - return EFI_UNSUPPORTED; -} - -EFI_STATUS -PciIoIoWrite ( - IN EFI_PCI_IO_PROTOCOL *This, - IN EFI_PCI_IO_PROTOCOL_WIDTH Width, - IN UINT8 BarIndex, - IN UINT64 Offset, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - ASSERT (FALSE); - return EFI_UNSUPPORTED; -} - -/** - Enable a PCI driver to read PCI controller registers in PCI configuration space. - - @param[in] This A pointer to the EFI_PCI_IO_PROTOCOL instance. - @param[in] Width Signifies the width of the memory operations. - @param[in] Offset The offset within the PCI configuration space for - the PCI controller. - @param[in] Count The number of PCI configuration operations to - perform. Bytes moved is Width size * Count, - starting at Offset. - - @param[in out] Buffer The destination buffer to store the results. - - @retval EFI_SUCCESS The data was read from the PCI controller. - @retval EFI_INVALID_PARAMETER "Width" is invalid. - @retval EFI_INVALID_PARAMETER "Buffer" is NULL. - -**/ -EFI_STATUS -PciIoPciRead ( - IN EFI_PCI_IO_PROTOCOL *This, - IN EFI_PCI_IO_PROTOCOL_WIDTH Width, - IN UINT32 Offset, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This); - EFI_STATUS Status; - - if ((Width < 0) || (Width >= EfiPciIoWidthMaximum) || (Buffer == NULL)) { - return EFI_INVALID_PARAMETER; - } - - Status = PciRootBridgeIoMemRW ( - (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width, - Count, - TRUE, - (PTR)(UINTN)Buffer, - TRUE, - (PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset) //Fix me ConfigSpace - ); - - return Status; -} - -/** - Enable a PCI driver to write PCI controller registers in PCI configuration space. - - @param[in] This A pointer to the EFI_PCI_IO_PROTOCOL instance. - @param[in] Width Signifies the width of the memory operations. - @param[in] Offset The offset within the PCI configuration space for - the PCI controller. - @param[in] Count The number of PCI configuration operations to - perform. Bytes moved is Width size * Count, - starting at Offset. - - @param[in out] Buffer The source buffer to write data from. - - @retval EFI_SUCCESS The data was read from the PCI controller. - @retval EFI_INVALID_PARAMETER "Width" is invalid. - @retval EFI_INVALID_PARAMETER "Buffer" is NULL. - -**/ -EFI_STATUS -PciIoPciWrite ( - IN EFI_PCI_IO_PROTOCOL *This, - IN EFI_PCI_IO_PROTOCOL_WIDTH Width, - IN UINT32 Offset, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This); - - if ((Width < 0) || (Width >= EfiPciIoWidthMaximum) || (Buffer == NULL)) { - return EFI_INVALID_PARAMETER; - } - - return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, - Count, - TRUE, - (PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset), //Fix me ConfigSpace - TRUE, - (PTR)(UINTN)Buffer - ); -} - -EFI_STATUS -PciIoCopyMem ( - IN EFI_PCI_IO_PROTOCOL *This, - IN EFI_PCI_IO_PROTOCOL_WIDTH Width, - IN UINT8 DestBarIndex, - IN UINT64 DestOffset, - IN UINT8 SrcBarIndex, - IN UINT64 SrcOffset, - IN UINTN Count - ) -{ - ASSERT (FALSE); - return EFI_UNSUPPORTED; -} - -EFI_STATUS -PciIoMap ( - IN EFI_PCI_IO_PROTOCOL *This, - IN EFI_PCI_IO_PROTOCOL_OPERATION Operation, - IN VOID *HostAddress, - IN OUT UINTN *NumberOfBytes, - OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, - OUT VOID **Mapping - ) -{ - DMA_MAP_OPERATION DmaOperation; - - if (Operation == EfiPciIoOperationBusMasterRead) { - DmaOperation = MapOperationBusMasterRead; - } else if (Operation == EfiPciIoOperationBusMasterWrite) { - DmaOperation = MapOperationBusMasterWrite; - } else if (Operation == EfiPciIoOperationBusMasterCommonBuffer) { - DmaOperation = MapOperationBusMasterCommonBuffer; - } else { - return EFI_INVALID_PARAMETER; - } - return DmaMap (DmaOperation, HostAddress, NumberOfBytes, DeviceAddress, Mapping); -} - -EFI_STATUS -PciIoUnmap ( - IN EFI_PCI_IO_PROTOCOL *This, - IN VOID *Mapping - ) -{ - return DmaUnmap (Mapping); -} - -/** - Allocate pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer - mapping. - - @param[in] This A pointer to the EFI_PCI_IO_PROTOCOL instance. - @param[in] Type This parameter is not used and must be ignored. - @param[in] MemoryType The type of memory to allocate, EfiBootServicesData or - EfiRuntimeServicesData. - @param[in] Pages The number of pages to allocate. - @param[out] HostAddress A pointer to store the base system memory address of - the allocated range. - @param[in] Attributes The requested bit mask of attributes for the allocated - range. Only the attributes, - EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE and - EFI_PCI_ATTRIBUTE_MEMORY_CACHED may be used with this - function. If any other bits are set, then EFI_UNSUPPORTED - is returned. This function ignores this bit mask. - - @retval EFI_SUCCESS The requested memory pages were allocated. - @retval EFI_INVALID_PARAMETER HostAddress is NULL. - @retval EFI_INVALID_PARAMETER MemoryType is invalid. - @retval EFI_UNSUPPORTED Attributes is unsupported. - @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. - -**/ -EFI_STATUS -PciIoAllocateBuffer ( - IN EFI_PCI_IO_PROTOCOL *This, - IN EFI_ALLOCATE_TYPE Type, - IN EFI_MEMORY_TYPE MemoryType, - IN UINTN Pages, - OUT VOID **HostAddress, - IN UINT64 Attributes - ) -{ - if (Attributes & - (~(EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE | - EFI_PCI_ATTRIBUTE_MEMORY_CACHED ))) { - return EFI_UNSUPPORTED; - } - - return DmaAllocateBuffer (MemoryType, Pages, HostAddress); -} - - -EFI_STATUS -PciIoFreeBuffer ( - IN EFI_PCI_IO_PROTOCOL *This, - IN UINTN Pages, - IN VOID *HostAddress - ) -{ - return DmaFreeBuffer (Pages, HostAddress); -} - - -EFI_STATUS -PciIoFlush ( - IN EFI_PCI_IO_PROTOCOL *This - ) -{ - return EFI_SUCCESS; -} - -/** - Retrieves this PCI controller's current PCI bus number, device number, and function number. - - @param[in] This A pointer to the EFI_PCI_IO_PROTOCOL instance. - @param[out] SegmentNumber The PCI controller's current PCI segment number. - @param[out] BusNumber The PCI controller's current PCI bus number. - @param[out] DeviceNumber The PCI controller's current PCI device number. - @param[out] FunctionNumber The PCI controller’s current PCI function number. - - @retval EFI_SUCCESS The PCI controller location was returned. - @retval EFI_INVALID_PARAMETER At least one out of the four output parameters is - a NULL pointer. -**/ -EFI_STATUS -PciIoGetLocation ( - IN EFI_PCI_IO_PROTOCOL *This, - OUT UINTN *SegmentNumber, - OUT UINTN *BusNumber, - OUT UINTN *DeviceNumber, - OUT UINTN *FunctionNumber - ) -{ - EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This); - - if ((SegmentNumber == NULL) || (BusNumber == NULL) || - (DeviceNumber == NULL) || (FunctionNumber == NULL) ) { - return EFI_INVALID_PARAMETER; - } - - *SegmentNumber = Private->Segment; - *BusNumber = 0xff; - *DeviceNumber = 0; - *FunctionNumber = 0; - - return EFI_SUCCESS; -} - -/** - Performs an operation on the attributes that this PCI controller supports. - - The operations include getting the set of supported attributes, retrieving - the current attributes, setting the current attributes, enabling attributes, - and disabling attributes. - - @param[in] This A pointer to the EFI_PCI_IO_PROTOCOL instance. - @param[in] Operation The operation to perform on the attributes for this - PCI controller. - @param[in] Attributes The mask of attributes that are used for Set, - Enable and Disable operations. - @param[out] Result A pointer to the result mask of attributes that are - returned for the Get and Supported operations. This - is an optional parameter that may be NULL for the - Set, Enable, and Disable operations. - - @retval EFI_SUCCESS The operation on the PCI controller's - attributes was completed. If the operation - was Get or Supported, then the attribute mask - is returned in Result. - @retval EFI_INVALID_PARAMETER Operation is greater than or equal to - EfiPciIoAttributeOperationMaximum. - @retval EFI_INVALID_PARAMETER Operation is Get and Result is NULL. - @retval EFI_INVALID_PARAMETER Operation is Supported and Result is NULL. - -**/ -EFI_STATUS -PciIoAttributes ( - IN EFI_PCI_IO_PROTOCOL *This, - IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation, - IN UINT64 Attributes, - OUT UINT64 *Result OPTIONAL - ) -{ - switch (Operation) { - case EfiPciIoAttributeOperationGet: - case EfiPciIoAttributeOperationSupported: - if (Result == NULL) { - return EFI_INVALID_PARAMETER; - } - // - // We are not a real PCI device so just say things we kind of do - // - *Result = EFI_PCI_DEVICE_ENABLE; - break; - - case EfiPciIoAttributeOperationSet: - case EfiPciIoAttributeOperationEnable: - case EfiPciIoAttributeOperationDisable: - if (Attributes & (~EFI_PCI_DEVICE_ENABLE)) { - return EFI_UNSUPPORTED; - } - // Since we are not a real PCI device no enable/set or disable operations exist. - return EFI_SUCCESS; - - default: - return EFI_INVALID_PARAMETER; - }; - return EFI_SUCCESS; -} - -EFI_STATUS -PciIoGetBarAttributes ( - IN EFI_PCI_IO_PROTOCOL *This, - IN UINT8 BarIndex, - OUT UINT64 *Supports, OPTIONAL - OUT VOID **Resources OPTIONAL - ) -{ - ASSERT (FALSE); - return EFI_UNSUPPORTED; -} - -EFI_STATUS -PciIoSetBarAttributes ( - IN EFI_PCI_IO_PROTOCOL *This, - IN UINT64 Attributes, - IN UINT8 BarIndex, - IN OUT UINT64 *Offset, - IN OUT UINT64 *Length - ) -{ - ASSERT (FALSE); - return EFI_UNSUPPORTED; -} - -EFI_PCI_IO_PROTOCOL PciIoTemplate = -{ - PciIoPollMem, - PciIoPollIo, - { PciIoMemRead, PciIoMemWrite }, - { PciIoIoRead, PciIoIoWrite }, - { PciIoPciRead, PciIoPciWrite }, - PciIoCopyMem, - PciIoMap, - PciIoUnmap, - PciIoAllocateBuffer, - PciIoFreeBuffer, - PciIoFlush, - PciIoGetLocation, - PciIoAttributes, - PciIoGetBarAttributes, - PciIoSetBarAttributes, - 0, - 0 -}; - -EFI_STATUS -PciInstallDevice ( - IN UINTN DeviceId, - IN PHYSICAL_ADDRESS MemoryStart, - IN UINT64 MemorySize, - IN UINTN ClassCode1, - IN UINTN ClassCode2, - IN UINTN ClassCode3 - ) -{ - EFI_STATUS Status; - EFI_HANDLE Handle; - EFI_PCI_IO_PRIVATE_DATA *Private; - - // Configure USB host - ConfigureUSBHost (); - - // Create a private structure - Private = AllocatePool (sizeof (EFI_PCI_IO_PRIVATE_DATA)); - if (Private == NULL) { - Status = EFI_OUT_OF_RESOURCES; - return Status; - } - - Private->Signature = EFI_PCI_IO_PRIVATE_DATA_SIGNATURE; // Fill in signature - Private->RootBridge.Signature = PCI_ROOT_BRIDGE_SIGNATURE; // Fake Root Bridge structure needs a signature too - Private->RootBridge.MemoryStart = MemoryStart; // Get the USB capability register base - Private->Segment = 0; // Default to segment zero - - // Calculate the total size of the USB controller (OHCI + EHCI). - Private->RootBridge.MemorySize = MemorySize; //CapabilityLength + (HOST_CONTROLLER_OPERATION_REG_SIZE + ((4 * PhysicalPorts) - 1)); - - // Create fake PCI config space: OHCI + EHCI - Private->ConfigSpace = AllocateZeroPool (sizeof (PCI_TYPE00)); - if (Private->ConfigSpace == NULL) { - Status = EFI_OUT_OF_RESOURCES; - FreePool (Private); - return Status; - } - - // - // Configure PCI config space: OHCI + EHCI - // - Private->ConfigSpace->Hdr.VendorId = 0xFFFF; // Invalid vendor Id as it is not an actual device. - Private->ConfigSpace->Hdr.DeviceId = 0x0000; // Not relevant as the vendor id is not valid. - Private->ConfigSpace->Hdr.ClassCode[0] = ClassCode1; - Private->ConfigSpace->Hdr.ClassCode[1] = ClassCode2; - Private->ConfigSpace->Hdr.ClassCode[2] = ClassCode3; - Private->ConfigSpace->Device.Bar[0] = MemoryStart; - - Handle = NULL; - - // Unique device path. - CopyMem (&Private->DevicePath, &PciIoDevicePathTemplate, sizeof (PciIoDevicePathTemplate)); - Private->DevicePath.AcpiDevicePath.UID = 1; // Use '1' to differentiate from PLDA root complex - Private->DevicePath.PciDevicePath.Device = DeviceId; - - // Copy protocol structure - CopyMem (&Private->PciIoProtocol, &PciIoTemplate, sizeof (PciIoTemplate)); - - Status = gBS->InstallMultipleProtocolInterfaces (&Handle, - &gEfiPciIoProtocolGuid, &Private->PciIoProtocol, - &gEfiDevicePathProtocolGuid, &Private->DevicePath, - NULL); - if (EFI_ERROR (Status)) { - DEBUG ((EFI_D_ERROR, "PciEmulationEntryPoint InstallMultipleProtocolInterfaces () failed.\n")); - } - - return Status; -} - -EFI_STATUS -PciEmulationEntryPoint ( - VOID - ) -{ - EFI_STATUS Status; - - Status = PciInstallDevice (0, FixedPcdGet32 (PcdSynopsysUsbOhciBaseAddress), SIZE_64KB, PCI_IF_OHCI, PCI_CLASS_SERIAL_USB, PCI_CLASS_SERIAL); - if (EFI_ERROR (Status)) { - DEBUG ((EFI_D_ERROR, "PciEmulation: failed to install OHCI device.\n")); - } - - Status = PciInstallDevice (1, FixedPcdGet32 (PcdSynopsysUsbEhciBaseAddress), SIZE_64KB, PCI_IF_EHCI, PCI_CLASS_SERIAL_USB, PCI_CLASS_SERIAL); - if (EFI_ERROR (Status)) { - DEBUG ((EFI_D_ERROR, "PciEmulation: failed to install EHCI device.\n")); - } - - return Status; -} diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciEmulation.h b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciEmulation.h deleted file mode 100644 index de2855d01d..0000000000 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciEmulation.h +++ /dev/null @@ -1,284 +0,0 @@ -/** @file - - Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
- Copyright (c) 2013 - 2014, ARM Ltd. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#ifndef _PCI_ROOT_BRIDGE_H_ -#define _PCI_ROOT_BRIDGE_H_ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include - -#include "ArmJunoDxeInternal.h" - -#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL -#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL -#define EFI_RESOURCE_SATISFIED 0x0000000000000000ULL - - -typedef struct { - ACPI_HID_DEVICE_PATH AcpiDevicePath; - EFI_DEVICE_PATH_PROTOCOL EndDevicePath; -} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; - - -#define ACPI_CONFIG_IO 0 -#define ACPI_CONFIG_MMIO 1 -#define ACPI_CONFIG_BUS 2 - -typedef struct { - EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR Desc[3]; - EFI_ACPI_END_TAG_DESCRIPTOR EndDesc; -} ACPI_CONFIG_INFO; - - -#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32 ('P', 'c', 'i', 'F') - -typedef struct { - UINT32 Signature; - EFI_HANDLE Handle; - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io; - EFI_PCI_ROOT_BRIDGE_DEVICE_PATH DevicePath; - - UINT8 StartBus; - UINT8 EndBus; - UINT16 Type; - UINT32 MemoryStart; - UINT32 MemorySize; - UINTN IoOffset; - UINT32 IoStart; - UINT32 IoSize; - UINT64 PciAttributes; - - ACPI_CONFIG_INFO *Config; - -} PCI_ROOT_BRIDGE; - - -#define INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) CR (a, PCI_ROOT_BRIDGE, Io, PCI_ROOT_BRIDGE_SIGNATURE) - - -typedef union { - UINT8 volatile *Buffer; - UINT8 volatile *Ui8; - UINT16 volatile *Ui16; - UINT32 volatile *Ui32; - UINT64 volatile *Ui64; - UINTN volatile Ui; -} PTR; - - - -EFI_STATUS -EFIAPI -PciRootBridgeIoPollMem ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINT64 Mask, - IN UINT64 Value, - IN UINT64 Delay, - OUT UINT64 *Result - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoPollIo ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINT64 Mask, - IN UINT64 Value, - IN UINT64 Delay, - OUT UINT64 *Result - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoMemRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoMemWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoIoRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 UserAddress, - IN UINTN Count, - IN OUT VOID *UserBuffer - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoIoWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 UserAddress, - IN UINTN Count, - IN OUT VOID *UserBuffer - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoCopyMem ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 DestAddress, - IN UINT64 SrcAddress, - IN UINTN Count - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoPciRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoPciWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoMap ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation, - IN VOID *HostAddress, - IN OUT UINTN *NumberOfBytes, - OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, - OUT VOID **Mapping - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoUnmap ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN VOID *Mapping - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoAllocateBuffer ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_ALLOCATE_TYPE Type, - IN EFI_MEMORY_TYPE MemoryType, - IN UINTN Pages, - OUT VOID **HostAddress, - IN UINT64 Attributes - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoFreeBuffer ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN UINTN Pages, - OUT VOID *HostAddress - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoFlush ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoGetAttributes ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - OUT UINT64 *Supported, - OUT UINT64 *Attributes - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoSetAttributes ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN UINT64 Attributes, - IN OUT UINT64 *ResourceBase, - IN OUT UINT64 *ResourceLength - ); - -EFI_STATUS -EFIAPI -PciRootBridgeIoConfiguration ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - OUT VOID **Resources - ); - -// -// Private Function Prototypes -// -EFI_STATUS -EFIAPI -PciRootBridgeIoMemRW ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINTN Count, - IN BOOLEAN InStrideFlag, - IN PTR In, - IN BOOLEAN OutStrideFlag, - OUT PTR Out - ); - -BOOLEAN -PciIoMemAddressValid ( - IN EFI_PCI_IO_PROTOCOL *This, - IN UINT64 Address - ); - -EFI_STATUS -EmulatePciIoForEhci ( - INTN MvPciIfMaxIf - ); - -#endif diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciRootBridgeIo.c b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciRootBridgeIo.c deleted file mode 100644 index f1eaceff28..0000000000 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciRootBridgeIo.c +++ /dev/null @@ -1,299 +0,0 @@ -/** @file - - Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#include "PciEmulation.h" - -BOOLEAN -PciRootBridgeMemAddressValid ( - IN PCI_ROOT_BRIDGE *Private, - IN UINT64 Address - ) -{ - if ((Address >= Private->MemoryStart) && (Address < (Private->MemoryStart + Private->MemorySize))) { - return TRUE; - } - - return FALSE; -} - - -EFI_STATUS -PciRootBridgeIoMemRW ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINTN Count, - IN BOOLEAN InStrideFlag, - IN PTR In, - IN BOOLEAN OutStrideFlag, - OUT PTR Out - ) -{ - UINTN Stride; - UINTN InStride; - UINTN OutStride; - - Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03); - Stride = (UINTN)1 << Width; - InStride = InStrideFlag ? Stride : 0; - OutStride = OutStrideFlag ? Stride : 0; - - // - // Loop for each iteration and move the data - // - switch (Width) { - case EfiPciWidthUint8: - for (;Count > 0; Count--, In.Buffer += InStride, Out.Buffer += OutStride) { - *In.Ui8 = *Out.Ui8; - } - break; - case EfiPciWidthUint16: - for (;Count > 0; Count--, In.Buffer += InStride, Out.Buffer += OutStride) { - *In.Ui16 = *Out.Ui16; - } - break; - case EfiPciWidthUint32: - for (;Count > 0; Count--, In.Buffer += InStride, Out.Buffer += OutStride) { - *In.Ui32 = *Out.Ui32; - } - break; - default: - return EFI_INVALID_PARAMETER; - } - - return EFI_SUCCESS; -} - -EFI_STATUS -PciRootBridgeIoPciRW ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN BOOLEAN Write, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 UserAddress, - IN UINTN Count, - IN OUT VOID *UserBuffer - ) -{ - return EFI_SUCCESS; -} - -/** - Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space. - - @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param Width Signifies the width of the memory operations. - @param Address The base address of the memory operations. - @param Count The number of memory operations to perform. - @param Buffer For read operations, the destination buffer to store the results. For write - operations, the source buffer to write data from. - - @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. - @retval EFI_INVALID_PARAMETER One or more parameters are invalid. - -**/ -EFI_STATUS -EFIAPI -PciRootBridgeIoMemRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - PCI_ROOT_BRIDGE *Private; - UINTN AlignMask; - PTR In; - PTR Out; - - if ( Buffer == NULL ) { - return EFI_INVALID_PARAMETER; - } - - Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); - - if (!PciRootBridgeMemAddressValid (Private, Address)) { - return EFI_INVALID_PARAMETER; - } - - AlignMask = (1 << (Width & 0x03)) - 1; - if (Address & AlignMask) { - return EFI_INVALID_PARAMETER; - } - - In.Buffer = Buffer; - Out.Buffer = (VOID *)(UINTN) Address; - - switch (Width) { - case EfiPciWidthUint8: - case EfiPciWidthUint16: - case EfiPciWidthUint32: - case EfiPciWidthUint64: - return PciRootBridgeIoMemRW (Width, Count, TRUE, In, TRUE, Out); - - case EfiPciWidthFifoUint8: - case EfiPciWidthFifoUint16: - case EfiPciWidthFifoUint32: - case EfiPciWidthFifoUint64: - return PciRootBridgeIoMemRW (Width, Count, TRUE, In, FALSE, Out); - - case EfiPciWidthFillUint8: - case EfiPciWidthFillUint16: - case EfiPciWidthFillUint32: - case EfiPciWidthFillUint64: - return PciRootBridgeIoMemRW (Width, Count, FALSE, In, TRUE, Out); - - default: - break; - } - - return EFI_INVALID_PARAMETER; -} - -/** - Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space. - - @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param Width Signifies the width of the memory operations. - @param Address The base address of the memory operations. - @param Count The number of memory operations to perform. - @param Buffer For read operations, the destination buffer to store the results. For write - operations, the source buffer to write data from. - - @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. - @retval EFI_INVALID_PARAMETER One or more parameters are invalid. - -**/ -EFI_STATUS -EFIAPI -PciRootBridgeIoMemWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - PCI_ROOT_BRIDGE *Private; - UINTN AlignMask; - PTR In; - PTR Out; - - if ( Buffer == NULL ) { - return EFI_INVALID_PARAMETER; - } - - Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); - - if (!PciRootBridgeMemAddressValid (Private, Address)) { - return EFI_INVALID_PARAMETER; - } - - AlignMask = (1 << (Width & 0x03)) - 1; - if (Address & AlignMask) { - return EFI_INVALID_PARAMETER; - } - - In.Buffer = (VOID *)(UINTN) Address; - Out.Buffer = Buffer; - - switch (Width) { - case EfiPciWidthUint8: - case EfiPciWidthUint16: - case EfiPciWidthUint32: - case EfiPciWidthUint64: - return PciRootBridgeIoMemRW (Width, Count, TRUE, In, TRUE, Out); - - case EfiPciWidthFifoUint8: - case EfiPciWidthFifoUint16: - case EfiPciWidthFifoUint32: - case EfiPciWidthFifoUint64: - return PciRootBridgeIoMemRW (Width, Count, FALSE, In, TRUE, Out); - - case EfiPciWidthFillUint8: - case EfiPciWidthFillUint16: - case EfiPciWidthFillUint32: - case EfiPciWidthFillUint64: - return PciRootBridgeIoMemRW (Width, Count, TRUE, In, FALSE, Out); - - default: - break; - } - - return EFI_INVALID_PARAMETER; -} - -/** - Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space. - - @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param Width Signifies the width of the memory operations. - @param Address The base address of the memory operations. - @param Count The number of memory operations to perform. - @param Buffer For read operations, the destination buffer to store the results. For write - operations, the source buffer to write data from. - - @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. - @retval EFI_INVALID_PARAMETER One or more parameters are invalid. - -**/ -EFI_STATUS -EFIAPI -PciRootBridgeIoPciRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - if (Buffer == NULL) { - return EFI_INVALID_PARAMETER; - } - - return PciRootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer); -} - -/** - Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space. - - @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param Width Signifies the width of the memory operations. - @param Address The base address of the memory operations. - @param Count The number of memory operations to perform. - @param Buffer For read operations, the destination buffer to store the results. For write - operations, the source buffer to write data from. - - @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. - @retval EFI_INVALID_PARAMETER One or more parameters are invalid. - -**/ -EFI_STATUS -EFIAPI -PciRootBridgeIoPciWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - if (Buffer == NULL) { - return EFI_INVALID_PARAMETER; - } - - return PciRootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer); -} diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridge.c b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridge.c deleted file mode 100644 index e1a6b749e4..0000000000 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridge.c +++ /dev/null @@ -1,199 +0,0 @@ -/** @file -* Pci Host Bridge support for the Xpress-RICH3 PCIe Root Complex -* -* Copyright (c) 2011-2015, ARM Ltd. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#include "PciHostBridge.h" - -#include - -/** - * PCI Root Bridge Description - */ -typedef struct { - UINT32 AcpiUid; - UINT64 MemAllocAttributes; -} PCI_ROOT_BRIDGE_DESC; - -PCI_ROOT_BRIDGE_DESC PciRbDescriptions = { - 0, // AcpiUid - PCI_MEMORY_ALLOCATION_ATTRIBUTES // MemAllocAttributes -}; - -/** - * Template for PCI Host Bridge Instance - **/ -STATIC CONST PCI_HOST_BRIDGE_INSTANCE -gPciHostBridgeInstanceTemplate = { - PCI_HOST_BRIDGE_SIGNATURE, //Signature - NULL, // Handle - NULL, // ImageHandle - NULL, // RootBridge - TRUE, // CanRestarted - NULL, // CpuIo - NULL, // Metronome - { // ResAlloc - PciHbRaNotifyPhase, // ResAlloc.NotifyPhase - PciHbRaGetNextRootBridge, // ResAlloc.GetNextRootBridge - PciHbRaGetAllocAttributes, // ResAlloc.GetAllocAttributes - PciHbRaStartBusEnumeration, // ResAlloc.StartBusEnumeration - PciHbRaSetBusNumbers, // ResAlloc.SetBusNumbers - PciHbRaSubmitResources, // ResAlloc.SubmitResources - PciHbRaGetProposedResources, // ResAlloc.GetProposedResources - PciHbRaPreprocessController // ResAlloc.PreprocessController - } -}; -PCI_HOST_BRIDGE_INSTANCE* gpPciHostBridgeInstance; - -EFI_STATUS -HostBridgeConstructor ( - IN OUT PCI_HOST_BRIDGE_INSTANCE** Instance, - IN EFI_HANDLE ImageHandle - ) -{ - EFI_STATUS Status; - PCI_HOST_BRIDGE_INSTANCE* HostBridge; - - PCI_TRACE ("HostBridgeConstructor()"); - - if (Instance == NULL) { - return EFI_INVALID_PARAMETER; - } - - HostBridge = AllocateCopyPool (sizeof (PCI_HOST_BRIDGE_INSTANCE), &gPciHostBridgeInstanceTemplate); - if (HostBridge == NULL) { - PCI_TRACE ("HostBridgeConstructor(): FAIL to allocate resources"); - return EFI_OUT_OF_RESOURCES; - } - - // It will also create a device handle for the PCI Host Bridge (as HostBridge->Handle == NULL) - Status = gBS->InstallMultipleProtocolInterfaces ( - &HostBridge->Handle, - &gEfiPciHostBridgeResourceAllocationProtocolGuid, &HostBridge->ResAlloc, - NULL - ); - if (EFI_ERROR (Status)) { - PCI_TRACE ("HostBridgeConstructor(): FAIL to install resource allocator"); - FreePool (HostBridge); - return EFI_DEVICE_ERROR; - } else { - PCI_TRACE ("HostBridgeConstructor(): SUCCEED to install resource allocator"); - } - - Status = gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL, (VOID **)(&(HostBridge->CpuIo))); - ASSERT_EFI_ERROR (Status); - - Status = gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL, (VOID **)(&(HostBridge->Metronome))); - ASSERT_EFI_ERROR (Status); - - HostBridge->ImageHandle = ImageHandle; - - *Instance = HostBridge; - return EFI_SUCCESS; -} - -EFI_STATUS -HostBridgeDestructor ( - IN PCI_HOST_BRIDGE_INSTANCE* HostBridge - ) -{ - EFI_STATUS Status; - - Status = gBS->UninstallMultipleProtocolInterfaces ( - HostBridge->Handle, - &gEfiPciHostBridgeResourceAllocationProtocolGuid, &HostBridge->ResAlloc, - NULL - ); - - if (HostBridge->RootBridge) { - PciRbDestructor (HostBridge->RootBridge); - } - - FreePool (HostBridge); - - return Status; -} - -/** - Entry point of this driver - - @param ImageHandle Handle of driver image - @param SystemTable Point to EFI_SYSTEM_TABLE - - @retval EFI_OUT_OF_RESOURCES Can not allocate memory resource - @retval EFI_DEVICE_ERROR Can not install the protocol instance - @retval EFI_SUCCESS Success to initialize the Pci host bridge. -**/ -EFI_STATUS -EFIAPI -PciHostBridgeEntryPoint ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - - PCI_TRACE ("PciHostBridgeEntryPoint()"); - - // Creation of the PCI Host Bridge Instance - Status = HostBridgeConstructor (&gpPciHostBridgeInstance, ImageHandle); - if (EFI_ERROR (Status)) { - PCI_TRACE ("PciHostBridgeEntryPoint(): ERROR: Fail to construct PCI Host Bridge."); - return Status; - } - - // Creation of the PCIe Root Bridge - Status = PciRbConstructor (gpPciHostBridgeInstance, PciRbDescriptions.AcpiUid, PciRbDescriptions.MemAllocAttributes); - if (EFI_ERROR (Status)) { - PCI_TRACE ("PciHostBridgeEntryPoint(): ERROR: Fail to construct PCI Root Bridge."); - return Status; - } - ASSERT (gpPciHostBridgeInstance->RootBridge->Signature == PCI_ROOT_BRIDGE_SIGNATURE); - - // PCI 32bit Memory Space - Status = gDS->AddMemorySpace ( - EfiGcdMemoryTypeMemoryMappedIo, - PCI_MEM32_BASE, - PCI_MEM32_SIZE, - 0 - ); - - // PCI 64bit Memory Space - Status = gDS->AddMemorySpace ( - EfiGcdMemoryTypeMemoryMappedIo, - PCI_MEM64_BASE, - PCI_MEM64_SIZE, - 0 - ); - - return EFI_SUCCESS; -} - -EFI_STATUS -EFIAPI -PciHostBridgeUnload ( - IN EFI_HANDLE ImageHandle - ) -{ - EFI_STATUS Status; - - // Free Reserved memory space in GCD - gDS->RemoveMemorySpace (PCI_MEM32_BASE, PCI_MEM32_SIZE); - gDS->RemoveMemorySpace (PCI_MEM64_BASE, PCI_MEM64_SIZE); - - // Free the allocated memory - Status = HostBridgeDestructor (gpPciHostBridgeInstance); - ASSERT_EFI_ERROR (Status); - - return Status; -} diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridge.h b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridge.h deleted file mode 100644 index e53f4fa3a8..0000000000 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridge.h +++ /dev/null @@ -1,324 +0,0 @@ -/** @file -* Header containing the structure specific to the Xpress-RICH3 PCIe Root Complex -* -* Copyright (c) 2011-2015, ARM Ltd. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#ifndef __PCIHOSTBRIDGE_H -#define __PCIHOSTBRIDGE_H - -#include - -#include "XPressRich3.h" - -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#define PCI_TRACE(txt) DEBUG((EFI_D_VERBOSE, "ARM_PCI: " txt "\n")) - -#define PCIE_ROOTPORT_WRITE32(Add, Val) { UINT32 Value = (UINT32)(Val); CpuIo->Mem.Write (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieRootPortBaseAddress)+(Add)),1,&Value); } -#define PCIE_ROOTPORT_READ32(Add, Val) { CpuIo->Mem.Read (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieRootPortBaseAddress)+(Add)),1,&Val); } - -#define PCIE_CONTROL_WRITE32(Add, Val) { UINT32 Value = (UINT32)(Val); CpuIo->Mem.Write (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieControlBaseAddress)+(Add)),1,&Value); } -#define PCIE_CONTROL_READ32(Add, Val) { CpuIo->Mem.Read (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieControlBaseAddress)+(Add)),1,&Val); } - -/** - * PCI Root Bridge Device Path (ACPI Device Node + End Node) - */ -typedef struct { - ACPI_HID_DEVICE_PATH Acpi; - EFI_DEVICE_PATH_PROTOCOL End; -} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; - -typedef enum { - ResTypeIo = 0, - ResTypeMem32, - ResTypePMem32, - ResTypeMem64, - ResTypePMem64, - ResTypeMax -} PCI_RESOURCE_TYPE; - -#define ACPI_SPECFLAG_PREFETCHABLE 0x06 -#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL -#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL - -typedef struct { - UINT64 Base; - UINT64 Length; - UINT64 Alignment; -} PCI_RESOURCE_ALLOC; - -typedef struct _PCI_HOST_BRIDGE_INSTANCE PCI_HOST_BRIDGE_INSTANCE; - -/** - * PCI Root Bridge Instance structure - **/ -typedef struct { - UINTN Signature; - EFI_HANDLE Handle; - PCI_HOST_BRIDGE_INSTANCE *HostBridge; - // - // Set Type of memory allocation (could be EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM - // and EFI_PCI_HOST_BRIDGE_MEM64_DECODE). - // - UINT64 MemAllocAttributes; - PCI_RESOURCE_ALLOC ResAlloc[ResTypeMax]; - UINTN BusStart; - UINTN BusLength; - UINT64 Supports; - UINT64 Attributes; - EFI_PCI_ROOT_BRIDGE_DEVICE_PATH DevicePath; - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io; -} PCI_ROOT_BRIDGE_INSTANCE; - -/** - * PCI Host Bridge Instance structure - **/ -struct _PCI_HOST_BRIDGE_INSTANCE { - UINTN Signature; - EFI_HANDLE Handle; - EFI_HANDLE ImageHandle; - PCI_ROOT_BRIDGE_INSTANCE *RootBridge; - // - // The enumeration cannot be restarted after the process goes into the non initial - // enumeration phase. - // - BOOLEAN CanRestarted; - EFI_CPU_IO2_PROTOCOL *CpuIo; - EFI_METRONOME_ARCH_PROTOCOL *Metronome; - EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc; -}; - -#define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32 ('e', 'h', 's', 't') -#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32 ('e', '2', 'p', 'b') -#define INSTANCE_FROM_RESOURCE_ALLOCATION_THIS(a) CR (a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE) -#define INSTANCE_FROM_ROOT_BRIDGE_IO_THIS(a) CR (a, PCI_ROOT_BRIDGE_INSTANCE, Io, PCI_ROOT_BRIDGE_SIGNATURE) - -/** - * PCI Host Bridge Resource Allocator Functions - **/ -EFI_STATUS PciHbRaNotifyPhase ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase - ); - -EFI_STATUS PciHbRaGetNextRootBridge ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN OUT EFI_HANDLE *RootBridgeHandle - ); - -EFI_STATUS PciHbRaGetAllocAttributes ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - OUT UINT64 *Attributes - ); - -EFI_STATUS PciHbRaStartBusEnumeration ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - OUT VOID **Configuration - ); - -EFI_STATUS PciHbRaSetBusNumbers ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - IN VOID *Configuration - ); - -EFI_STATUS PciHbRaSubmitResources ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - IN VOID *Configuration - ); - -EFI_STATUS PciHbRaGetProposedResources ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - OUT VOID **Configuration - ); - -EFI_STATUS PciHbRaPreprocessController ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, - IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase - ); - - -/** - * PCI Root Bridge - **/ -EFI_STATUS PciRbPollMem ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINT64 Mask, - IN UINT64 Value, - IN UINT64 Delay, - OUT UINT64 *Result - ); - -EFI_STATUS PciRbPollIo ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINT64 Mask, - IN UINT64 Value, - IN UINT64 Delay, - OUT UINT64 *Result - ); - -EFI_STATUS PciRbMemRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ); - -EFI_STATUS PciRbMemWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ); - -EFI_STATUS PciRbIoRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ); - -EFI_STATUS PciRbIoWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ); - -EFI_STATUS PciRbPciRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ); - -EFI_STATUS PciRbPciWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ); - -EFI_STATUS PciRbCopyMem ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 DestAddress, - IN UINT64 SrcAddress, - IN UINTN Count - ); - -EFI_STATUS PciRbMap ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation, - IN VOID *HostAddress, - IN OUT UINTN *NumberOfBytes, - OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, - OUT VOID **Mapping - ); - -EFI_STATUS PciRbUnMap ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN VOID *Mapping - ); - -EFI_STATUS PciRbAllocateBuffer ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_ALLOCATE_TYPE Type, - IN EFI_MEMORY_TYPE MemoryType, - IN UINTN Pages, - IN OUT VOID **HostAddress, - IN UINT64 Attributes - ); - -EFI_STATUS PciRbFreeBuffer ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN UINTN Pages, - IN VOID *HostAddress - ); - -EFI_STATUS PciRbFlush ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This - ); - -EFI_STATUS PciRbSetAttributes ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN UINT64 Attributes, - IN OUT UINT64 *ResourceBase, - IN OUT UINT64 *ResourceLength - ); - -EFI_STATUS PciRbGetAttributes ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - OUT UINT64 *Supports, - OUT UINT64 *Attributes - ); - -EFI_STATUS PciRbConfiguration ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - OUT VOID **Resources - ); - -/** - * PCI Root Bridge Functions - **/ -EFI_STATUS -PciRbConstructor ( - IN PCI_HOST_BRIDGE_INSTANCE *HostBridge, - IN UINT32 PciAcpiUid, - IN UINT64 MemAllocAttributes - ); - -EFI_STATUS -PciRbDestructor ( - IN PCI_ROOT_BRIDGE_INSTANCE* RootBridge - ); - -EFI_STATUS -HWPciRbInit ( - IN EFI_CPU_IO2_PROTOCOL *CpuIo - ); - -#endif diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf deleted file mode 100644 index 9f526910c4..0000000000 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf +++ /dev/null @@ -1,76 +0,0 @@ -#/** @file -# INF file for the Xpress-RICH3 PCIe Root Complex -# -# Copyright (c) 2011-2015, ARM Ltd. All rights reserved. -# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -#**/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = PciHostBridge - FILE_GUID = C62F4B20-681E-11DF-8F0D-0002A5D5C51B - MODULE_TYPE = DXE_DRIVER - VERSION_STRING = 1.0 - - ENTRY_POINT = PciHostBridgeEntryPoint - UNLOAD_IMAGE = PciHostBridgeUnload - -[Packages] - MdePkg/MdePkg.dec - ArmPkg/ArmPkg.dec - EmbeddedPkg/EmbeddedPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec - -[LibraryClasses] - UefiDriverEntryPoint - UefiBootServicesTableLib - MemoryAllocationLib - DxeServicesTableLib - CacheMaintenanceLib - DmaLib - -[Sources] - PciHostBridge.c - PciHostBridgeResourceAllocation.c - PciRootBridge.c - XPressRich3.c - -[Protocols] - gEfiPciHostBridgeResourceAllocationProtocolGuid # Produced - gEfiPciRootBridgeIoProtocolGuid # Produced - gEfiDevicePathProtocolGuid # Produced - gEfiCpuIo2ProtocolGuid # Consumed - gEfiMetronomeArchProtocolGuid # Consumed - -[FeaturePcd] - gArmJunoTokenSpaceGuid.PcdPciMaxPayloadFixup - -[Pcd.common] - gArmTokenSpaceGuid.PcdSystemMemoryBase - gArmTokenSpaceGuid.PcdSystemMemorySize - - gArmPlatformTokenSpaceGuid.PcdPciBusMin - gArmPlatformTokenSpaceGuid.PcdPciBusMax - gArmPlatformTokenSpaceGuid.PcdPciIoBase - gArmPlatformTokenSpaceGuid.PcdPciIoSize - gArmPlatformTokenSpaceGuid.PcdPciMmio32Base - gArmPlatformTokenSpaceGuid.PcdPciMmio32Size - gArmPlatformTokenSpaceGuid.PcdPciMmio64Base - gArmPlatformTokenSpaceGuid.PcdPciMmio64Size - - gArmJunoTokenSpaceGuid.PcdPcieControlBaseAddress - gArmJunoTokenSpaceGuid.PcdPcieRootPortBaseAddress - gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress - gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceSize - -[Depex] - gEfiCpuIo2ProtocolGuid AND gEfiMetronomeArchProtocolGuid diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridgeResourceAllocation.c b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridgeResourceAllocation.c deleted file mode 100644 index de60db7184..0000000000 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridgeResourceAllocation.c +++ /dev/null @@ -1,642 +0,0 @@ -/** @file -* Implementation of the Pci Host Bridge Resource Allocation for the Xpress-RICH3 PCIe Root Complex -* -* Copyright (c) 2011-2015, ARM Ltd. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#include "PciHostBridge.h" - -EFI_STATUS -PciHbRaNotifyPhase ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase - ) -{ - PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - EFI_STATUS Status; - EFI_PHYSICAL_ADDRESS BaseAddress; - UINT64 AddrLen; - UINTN BitsOfAlignment; - - HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); - - PCI_TRACE ("PciHbRaNotifyPhase()"); - - // Check RootBridge Signature - ASSERT (HostBridgeInstance->RootBridge->Signature == PCI_ROOT_BRIDGE_SIGNATURE); - - // The enumeration cannot be restarted after the process has been further than the first phase - if (Phase == EfiPciHostBridgeBeginEnumeration) { - if (!HostBridgeInstance->CanRestarted) { - return EFI_NOT_READY; - } - } else { - HostBridgeInstance->CanRestarted = FALSE; - } - - switch (Phase) { - case EfiPciHostBridgeBeginEnumeration: - PCI_TRACE ("PciHbRaNotifyPhase(EfiPciHostBridgeBeginEnumeration)"); - // Resets the host bridge PCI apertures and internal data structures - Status = HWPciRbInit (HostBridgeInstance->CpuIo); - if (EFI_ERROR (Status)) { - return Status; - } - break; - - case EfiPciHostBridgeBeginBusAllocation: - PCI_TRACE ("PciHbRaNotifyPhase(EfiPciHostBridgeBeginBusAllocation)"); - // The bus allocation phase is about to begin - break; - - case EfiPciHostBridgeEndBusAllocation: - PCI_TRACE ("PciHbRaNotifyPhase(EfiPciHostBridgeEndBusAllocation)"); - // The bus allocation and bus programming phase is complete. All the PCI-to-PCI bridges have been given and written back - // a bus number range into their configuration - break; - - case EfiPciHostBridgeBeginResourceAllocation: - PCI_TRACE ("PciHbRaNotifyPhase(EfiPciHostBridgeBeginResourceAllocation)"); - // The resource allocation phase is about to begin. - break; - - case EfiPciHostBridgeAllocateResources: - PCI_TRACE ("PciHbRaNotifyPhase(EfiPciHostBridgeAllocateResources)"); - // Allocates resources per previously submitted requests for all the PCI root bridges. The resources have been submitted to - // PciHbRaSubmitResources() before. - - RootBridgeInstance = HostBridgeInstance->RootBridge; - if (RootBridgeInstance->ResAlloc[ResTypeIo].Length != 0) { - BitsOfAlignment = HighBitSet64 (RootBridgeInstance->ResAlloc[ResTypeIo].Alignment) + 1; // Get the number of '1' in Alignment - AddrLen = RootBridgeInstance->ResAlloc[ResTypeIo].Length; - - Status = gDS->AllocateIoSpace ( - EfiGcdAllocateAnySearchBottomUp, - EfiGcdIoTypeIo, - BitsOfAlignment, - AddrLen, - &BaseAddress, - HostBridgeInstance->ImageHandle, - NULL - ); - // If error then ResAlloc[n].Base ==0 - if (!EFI_ERROR (Status)) { - RootBridgeInstance->ResAlloc[ResTypeIo].Base = (UINTN)BaseAddress; - } - } - - if (RootBridgeInstance->ResAlloc[ResTypeMem32].Length != 0) { - BitsOfAlignment = HighBitSet64 (RootBridgeInstance->ResAlloc[ResTypeMem32].Alignment) + 1; // Get the number of '1' in Alignment - AddrLen = RootBridgeInstance->ResAlloc[ResTypeMem32].Length; - - // Top of the 32bit PCI Memory space - BaseAddress = FixedPcdGet64 (PcdPciMmio32Base) + FixedPcdGet64 (PcdPciMmio32Size); - - Status = gDS->AllocateMemorySpace ( - EfiGcdAllocateMaxAddressSearchTopDown, - EfiGcdMemoryTypeMemoryMappedIo, - BitsOfAlignment, - AddrLen, - &BaseAddress, - HostBridgeInstance->ImageHandle, - NULL - ); - - // Ensure the allocation is in the 32bit PCI memory space - if (!EFI_ERROR (Status) && (BaseAddress >= FixedPcdGet64 (PcdPciMmio32Base))) { - RootBridgeInstance->ResAlloc[ResTypeMem32].Base = (UINTN)BaseAddress; - } - } - if (RootBridgeInstance->ResAlloc[ResTypePMem32].Length != 0) { - BitsOfAlignment = HighBitSet64 (RootBridgeInstance->ResAlloc[ResTypePMem32].Alignment) + 1; // Get the number of '1' in Alignment - AddrLen = RootBridgeInstance->ResAlloc[ResTypePMem32].Length; - - // Top of the 32bit PCI Memory space - BaseAddress = FixedPcdGet64 (PcdPciMmio32Base) + FixedPcdGet64 (PcdPciMmio32Size); - - Status = gDS->AllocateMemorySpace ( - EfiGcdAllocateMaxAddressSearchTopDown, - EfiGcdMemoryTypeMemoryMappedIo, - BitsOfAlignment, - AddrLen, - &BaseAddress, - HostBridgeInstance->ImageHandle, - NULL - ); - - // Ensure the allocation is in the 32bit PCI memory space - if (!EFI_ERROR (Status) && (BaseAddress >= FixedPcdGet64 (PcdPciMmio32Base))) { - RootBridgeInstance->ResAlloc[ResTypePMem32].Base = (UINTN)BaseAddress; - } - } - if (RootBridgeInstance->ResAlloc[ResTypeMem64].Length != 0) { - BitsOfAlignment = HighBitSet64 (RootBridgeInstance->ResAlloc[ResTypeMem64].Alignment) + 1; // Get the number of '1' in Alignment - AddrLen = RootBridgeInstance->ResAlloc[ResTypeMem64].Length; - - // Top of the 64bit PCI Memory space - BaseAddress = FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size); - - Status = gDS->AllocateMemorySpace ( - EfiGcdAllocateMaxAddressSearchTopDown, - EfiGcdMemoryTypeMemoryMappedIo, - BitsOfAlignment, - AddrLen, - &BaseAddress, - HostBridgeInstance->ImageHandle, - NULL - ); - - // Ensure the allocation is in the 64bit PCI memory space - if (!EFI_ERROR (Status) && (BaseAddress >= FixedPcdGet64 (PcdPciMmio64Base))) { - RootBridgeInstance->ResAlloc[ResTypeMem64].Base = (UINTN)BaseAddress; - } - } - if (RootBridgeInstance->ResAlloc[ResTypePMem64].Length != 0) { - BitsOfAlignment = HighBitSet64 (RootBridgeInstance->ResAlloc[ResTypePMem64].Alignment) + 1; //Get the number of '1' in Alignment - AddrLen = RootBridgeInstance->ResAlloc[ResTypePMem64].Length; - - // Top of the 64bit PCI Memory space - BaseAddress = FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size); - - Status = gDS->AllocateMemorySpace ( - EfiGcdAllocateMaxAddressSearchTopDown, - EfiGcdMemoryTypeMemoryMappedIo, - BitsOfAlignment, - AddrLen, - &BaseAddress, - HostBridgeInstance->ImageHandle, - NULL - ); - - // Ensure the allocation is in the 64bit PCI memory space - if (!EFI_ERROR (Status) && (BaseAddress >= FixedPcdGet64 (PcdPciMmio64Base))) { - RootBridgeInstance->ResAlloc[ResTypePMem64].Base = (UINTN)BaseAddress; - } - } - - break; - - case EfiPciHostBridgeSetResources: - PCI_TRACE ("PciHbRaNotifyPhase(EfiPciHostBridgeSetResources)"); - // Programs the host bridge hardware to decode previously allocated resources (proposed resources) - // for all the PCI root bridges. The PCI bus driver will now program the resources - break; - - case EfiPciHostBridgeFreeResources: - PCI_TRACE ("PciHbRaNotifyPhase(EfiPciHostBridgeFreeResources)"); - // Deallocates resources that were previously allocated for all the PCI root bridges and resets the - // I/O and memory apertures to their initial state.*/ - break; - - case EfiPciHostBridgeEndResourceAllocation: - PCI_TRACE ("PciHbRaNotifyPhase(EfiPciHostBridgeEndResourceAllocation)"); - break; - - case EfiPciHostBridgeEndEnumeration: - PCI_TRACE ("PciHbRaNotifyPhase(EfiPciHostBridgeEndEnumeration)"); - break; - - default: - DEBUG ((EFI_D_INFO, "PciHbRaNotifyPhase(Phase:%d)\n", Phase)); - ASSERT (0); - } - - return EFI_SUCCESS; -} - -/** - * PciHbRaGetNextRootBridge() returns the next root bridge attached to the 'This' PCI Host Bridge. - * As we have only got one PCI Root Bridge in this PCI interface, we return either this root bridge - * if it the first time we call this function (*RootBridgeHandle == NULL) or we return EFI_NOT_FOUND - **/ -EFI_STATUS -PciHbRaGetNextRootBridge ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN OUT EFI_HANDLE *RootBridgeHandle - ) -{ - PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; - - PCI_TRACE ("PciHbRaGetNextRootBridge()"); - - HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); - ASSERT (HostBridgeInstance->RootBridge != NULL); - - //Check RootBridge Signature - ASSERT (HostBridgeInstance->RootBridge->Signature == PCI_ROOT_BRIDGE_SIGNATURE); - - if (*RootBridgeHandle == NULL) { - *RootBridgeHandle = HostBridgeInstance->RootBridge->Handle; - return EFI_SUCCESS; - } else if (*RootBridgeHandle == HostBridgeInstance->RootBridge->Handle) { - return EFI_NOT_FOUND; - } else { - return EFI_INVALID_PARAMETER; - } -} - -/** PciHbRaGetAllocAttributes() returns the resource allocation attributes supported by this PCI Root Bridge. - * A PCI Root bridge could support these types : - * - EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM : does not support separate windows for nonprefetchable and prefetchable memory. - * - EFI_PCI_HOST_BRIDGE_MEM64_DECODE : supports 64-bit memory windows - **/ -EFI_STATUS -PciHbRaGetAllocAttributes ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - OUT UINT64 *Attributes - ) -{ - PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; - - PCI_TRACE ("PciHbRaGetAllocAttributes()"); - - HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); - - // Check if the RootBridgeHandle is the one managed by this PCI Host Bridge - ASSERT (HostBridgeInstance->RootBridge != NULL); - if (HostBridgeInstance->RootBridge->Handle != RootBridgeHandle) { - return EFI_INVALID_PARAMETER; - } - - *Attributes = HostBridgeInstance->RootBridge->MemAllocAttributes; - return EFI_SUCCESS; -} - -EFI_STATUS -PciHbRaStartBusEnumeration ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - OUT VOID **Configuration - ) -{ - VOID *Buffer; - UINT8 *Ptr; - PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; - - // Fill an ACPI descriptor table with the Bus Number Range. This information will be used by the PCI Bus driver - // to set bus numbers to PCI-to-PCI bridge. - PCI_TRACE ("PciHbRaStartBusEnumeration()"); - - HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); - - Buffer = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)); - if (Buffer == NULL) { - return EFI_OUT_OF_RESOURCES; - } - - Ptr = (UINT8 *)Buffer; - - ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR; // QWORD Address space Descriptor - ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->Len = 0x2B; // Length of this descriptor in bytes not including the first two fields - ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS; // Resource Type Bus Number Range - ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->GenFlag = 0; - ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->SpecificFlag = 0; - ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrSpaceGranularity = 0; - ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrRangeMin = HostBridgeInstance->RootBridge->BusStart; // Bus Start - ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrRangeMax = 0; // Bus Max - ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrTranslationOffset = 0; - ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrLen = FixedPcdGet32 (PcdPciBusMax) - FixedPcdGet32 (PcdPciBusMin) + 1; - - Ptr = Ptr + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR); - ((EFI_ACPI_END_TAG_DESCRIPTOR *)Ptr)->Desc = ACPI_END_TAG_DESCRIPTOR; - ((EFI_ACPI_END_TAG_DESCRIPTOR *)Ptr)->Checksum = 0x0; - - *Configuration = Buffer; - return EFI_SUCCESS; -} - -EFI_STATUS -PciHbRaSetBusNumbers ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - IN VOID *Configuration - ) -{ - PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; - UINT8 *Ptr; - UINTN BusStart; - UINTN BusEnd; - UINTN BusLen; - - PCI_TRACE ("PciHbRaSetBusNumbers()"); - - Ptr = Configuration; - if (*Ptr != ACPI_ADDRESS_SPACE_DESCRIPTOR) { - return EFI_INVALID_PARAMETER; - } - - // Check if the passed ACPI descriptor table define a Bus Number Range - if (((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->ResType != ACPI_ADDRESS_SPACE_TYPE_BUS) { - return EFI_INVALID_PARAMETER; - } - - // Check if the Configuration only passed one ACPI Descriptor (+ End Descriptor) - if (*((UINT8*)(Ptr + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR))) != ACPI_END_TAG_DESCRIPTOR) { - return EFI_INVALID_PARAMETER; - } - - HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); - ASSERT (HostBridgeInstance->RootBridge != NULL); - if (HostBridgeInstance->RootBridge->Handle != RootBridgeHandle) { - return EFI_INVALID_PARAMETER; - } - - BusStart = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrRangeMin; - BusLen = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrLen; - BusEnd = BusStart + BusLen - 1; - - ASSERT (BusStart <= BusEnd); // We should at least have PCI_BUS_ROOT and PCI_SWITCH_BUS - ASSERT ((BusStart >= HostBridgeInstance->RootBridge->BusStart) && (BusLen <= HostBridgeInstance->RootBridge->BusLength)); - - HostBridgeInstance->RootBridge->BusStart = BusStart; - HostBridgeInstance->RootBridge->BusLength = BusLen; - - return EFI_SUCCESS; -} - -/** - * This function is used to submit all the I/O and memory resources that are required by the specified - * PCI root bridge. - **/ -EFI_STATUS -PciHbRaSubmitResources ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - IN VOID *Configuration - ) -{ - PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - UINT8 *Ptr; - EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc; - PCI_RESOURCE_TYPE ResType; - - PCI_TRACE ("PciHbRaSubmitResources()"); - - HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); - - if (Configuration == NULL) { - return EFI_INVALID_PARAMETER; - } - - // Check if the ACPI Descriptor tables is conformed - Ptr = (UINT8 *)Configuration; - while (*Ptr == ACPI_ADDRESS_SPACE_DESCRIPTOR) { // QWORD Address Space descriptor - Ptr += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) ; - } - if (*Ptr != ACPI_END_TAG_DESCRIPTOR) { // End tag - return EFI_INVALID_PARAMETER; - } - - // Check the RootBridgeHandle - RootBridgeInstance = HostBridgeInstance->RootBridge; - ASSERT (RootBridgeInstance != NULL); - if (RootBridgeHandle != HostBridgeInstance->RootBridge->Handle) { - return EFI_INVALID_PARAMETER; - } - - Ptr = (UINT8 *)Configuration; - while ( *Ptr == ACPI_ADDRESS_SPACE_DESCRIPTOR) { // While the entry is an ACPI Descriptor Table - Desc = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr; - - // Check if the description is valid - if (Desc->AddrLen > 0xffffffff) { - return EFI_INVALID_PARAMETER; - } - - if ((Desc->AddrRangeMax >= 0xffffffff) || (Desc->AddrRangeMax != (GetPowerOfTwo64 (Desc->AddrRangeMax + 1) - 1))) { - return EFI_INVALID_PARAMETER; - } - - switch (Desc->ResType) { - case ACPI_ADDRESS_SPACE_TYPE_MEM: - // Check invalid Address Space Granularity - if ((Desc->AddrSpaceGranularity != 32) && (Desc->AddrSpaceGranularity != 64)) { - return EFI_INVALID_PARAMETER; - } - - // check the memory resource request is supported by PCI root bridge - if (RootBridgeInstance->MemAllocAttributes == EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM && Desc->SpecificFlag == 0x06) { - return EFI_INVALID_PARAMETER; - } - - if (Desc->AddrSpaceGranularity == 32) { - if (Desc->SpecificFlag == ACPI_SPECFLAG_PREFETCHABLE) { - ResType = ResTypePMem32; - } else { - ResType = ResTypeMem32; - } - } else { - if (Desc->SpecificFlag == ACPI_SPECFLAG_PREFETCHABLE) { - ResType = ResTypePMem64; - } else { - ResType = ResTypeMem64; - } - } - RootBridgeInstance->ResAlloc[ResType].Length = Desc->AddrLen; - RootBridgeInstance->ResAlloc[ResType].Alignment = Desc->AddrRangeMax; - RootBridgeInstance->ResAlloc[ResType].Base = Desc->AddrRangeMin; - break; - case ACPI_ADDRESS_SPACE_TYPE_IO: - RootBridgeInstance->ResAlloc[ResTypeIo].Length = Desc->AddrLen; - RootBridgeInstance->ResAlloc[ResTypeIo].Alignment = Desc->AddrRangeMax; - RootBridgeInstance->ResAlloc[ResTypeIo].Base = 0; - break; - default: - ASSERT (0); // Could be the case Desc->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS - break; - } - Ptr += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR); - } - - return EFI_SUCCESS; -} - -/** Returns the proposed resource settings for the specified PCI root bridge. The resources have been submitted by - * PciHbRaSubmitResources() before - **/ -EFI_STATUS -PciHbRaGetProposedResources ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - OUT VOID **Configuration - ) -{ - PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - UINT32 i; - UINT32 ResAllocCount; - VOID *Buffer; - UINT8 *Ptr; - EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc; - - PCI_TRACE ("PciHbRaGetProposedResources()"); - - HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); - - // Check the RootBridgeHandle - RootBridgeInstance = HostBridgeInstance->RootBridge; - ASSERT (RootBridgeInstance != NULL); - if (RootBridgeHandle != HostBridgeInstance->RootBridge->Handle) { - return EFI_INVALID_PARAMETER; - } - - // Count the number of Resource Allocated for this Root Bridge - ResAllocCount = 0; - for (i = 0; i < ResTypeMax; i++) { - if (RootBridgeInstance->ResAlloc[i].Length != 0) ResAllocCount++; - } - - if (ResAllocCount == 0) { - return EFI_INVALID_PARAMETER; - } - - Buffer = AllocateZeroPool (ResAllocCount * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)); - if (Buffer == NULL) { - return EFI_OUT_OF_RESOURCES; - } - - Ptr = Buffer; - for (i = 0; i < ResTypeMax; i++) { - if (RootBridgeInstance->ResAlloc[i].Length != 0) { // Base != 0 if the resource has been allocated - Desc = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr; - - Desc->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR; - Desc->Len = 0x2B; - Desc->GenFlag = 0; - Desc->AddrRangeMax = 0; - - switch (i) { - case ResTypeIo: - Desc->ResType = ACPI_ADDRESS_SPACE_TYPE_IO; - Desc->SpecificFlag = 0; - Desc->AddrSpaceGranularity = 0; - break; - case ResTypeMem32: - Desc->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM; - Desc->SpecificFlag = 0; - Desc->AddrSpaceGranularity = 32; - break; - case ResTypePMem32: - Desc->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM; - Desc->SpecificFlag = ACPI_SPECFLAG_PREFETCHABLE; - Desc->AddrSpaceGranularity = 32; - break; - case ResTypeMem64: - Desc->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM; - Desc->SpecificFlag = 0; - Desc->AddrSpaceGranularity = 64; - break; - case ResTypePMem64: - Desc->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM; - Desc->SpecificFlag = ACPI_SPECFLAG_PREFETCHABLE; - Desc->AddrSpaceGranularity = 64; - break; - } - Desc->AddrRangeMin = RootBridgeInstance->ResAlloc[i].Base; - Desc->AddrTranslationOffset = (RootBridgeInstance->ResAlloc[i].Base != 0) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; - Desc->AddrLen = RootBridgeInstance->ResAlloc[i].Length; - Ptr += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR); - } - } - - ((EFI_ACPI_END_TAG_DESCRIPTOR *)Ptr)->Desc = ACPI_END_TAG_DESCRIPTOR; - ((EFI_ACPI_END_TAG_DESCRIPTOR *)Ptr)->Checksum = 0x0; - - *Configuration = Buffer; - return EFI_SUCCESS; -} - -EFI_STATUS -PciHbRaPreprocessController ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, - IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase - ) -{ - PCI_HOST_BRIDGE_INSTANCE* HostBridge; - PCI_ROOT_BRIDGE_INSTANCE* RootBridge; - UINT32 CapabilityPtr; - UINT32 CapabilityEntry; - UINT16 CapabilityID; - UINT32 DeviceCapability; - - PCI_TRACE ("PciHbRaPreprocessController()"); - - if (FeaturePcdGet (PcdPciMaxPayloadFixup)) { - // Do Max payload fixup for every devices - if (Phase == EfiPciBeforeResourceCollection) { - // Get RootBridge Instance from Host Bridge Instance - HostBridge = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); - RootBridge = HostBridge->RootBridge; - - // Get the first PCI Capability - CapabilityPtr = PCI_CAPBILITY_POINTER_OFFSET; - RootBridge->Io.Pci.Read ( - &RootBridge->Io, - EfiPciWidthUint8, - EFI_PCI_ADDRESS (PciAddress.Bus, PciAddress.Device, PciAddress.Function, CapabilityPtr), - 1, - &CapabilityPtr - ); - CapabilityPtr &= 0x1FF; - - // Get Pci Express Capability - while (CapabilityPtr != 0) { - RootBridge->Io.Pci.Read ( - &RootBridge->Io, - EfiPciWidthUint16, - EFI_PCI_ADDRESS (PciAddress.Bus, PciAddress.Device, PciAddress.Function, CapabilityPtr), - 1, - &CapabilityEntry - ); - - CapabilityID = (UINT8)CapabilityEntry; - - // Is PCIe capability ? - if (CapabilityID == EFI_PCI_CAPABILITY_ID_PCIEXP) { - // Get PCIe Device Capabilities - RootBridge->Io.Pci.Read ( - &RootBridge->Io, - EfiPciWidthUint32, - EFI_PCI_ADDRESS (PciAddress.Bus, PciAddress.Device, PciAddress.Function, CapabilityPtr + 0x8), - 1, - &DeviceCapability - ); - - // Force the Max Payload to 128 Bytes (128 Bytes Max Payload Size = 0) - DeviceCapability &= ~ ((UINT32)(0x7 << 5 )); - // Max Read Request Size to 128 Bytes (128 Bytes Max Read Request Size = 0) - DeviceCapability &= ~ ((UINT32)(0x7 << 12)); - // Enable all error reporting - DeviceCapability |= 0xF; - - RootBridge->Io.Pci.Write ( - &RootBridge->Io, - EfiPciWidthUint32, - EFI_PCI_ADDRESS (PciAddress.Bus, PciAddress.Device, PciAddress.Function, CapabilityPtr + 0x8), - 1, - &DeviceCapability - ); - - return EFI_SUCCESS; - } - CapabilityPtr = (CapabilityEntry >> 8) & 0xFF; - } - } - } - - return EFI_SUCCESS; -} diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciRootBridge.c b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciRootBridge.c deleted file mode 100644 index 10a4575c16..0000000000 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciRootBridge.c +++ /dev/null @@ -1,745 +0,0 @@ -/** @file -* Implementation of the PCI Root Bridge Protocol for XPress-RICH3 PCIe Root Complex -* -* Copyright (c) 2011-2015, ARM Ltd. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#include "PciHostBridge.h" - -#include -#include - -#define CPUIO_FROM_ROOT_BRIDGE_INSTANCE(Instance) (Instance->HostBridge->CpuIo) -#define METRONOME_FROM_ROOT_BRIDGE_INSTANCE(Instance) (Instance->HostBridge->Metronome) - -/** - * PCI Root Bridge Instance Templates - */ -STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH gDevicePathTemplate = { - { - { ACPI_DEVICE_PATH, - ACPI_DP, - { (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), - (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) } - }, - EISA_PNP_ID (0x0A03), - 0 - }, - { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - { END_DEVICE_PATH_LENGTH, 0 } - } -}; - -STATIC CONST EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL gIoTemplate = { - 0, - PciRbPollMem, - PciRbPollIo, - { - PciRbMemRead, - PciRbMemWrite - }, - { - PciRbIoRead, - PciRbIoWrite - }, - { - PciRbPciRead, - PciRbPciWrite - }, - PciRbCopyMem, - PciRbMap, - PciRbUnMap, - PciRbAllocateBuffer, - PciRbFreeBuffer, - PciRbFlush, - PciRbGetAttributes, - PciRbSetAttributes, - PciRbConfiguration, - 0 - }; - -typedef struct { - EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR SpaceDesp[ResTypeMax+1]; - EFI_ACPI_END_TAG_DESCRIPTOR EndDesp; -} RESOURCE_CONFIGURATION; - - -RESOURCE_CONFIGURATION Configuration = { - {{ACPI_ADDRESS_SPACE_DESCRIPTOR, 0x2B, ACPI_ADDRESS_SPACE_TYPE_IO , 0, 0, 0, 0, 0, 0, 0}, - {ACPI_ADDRESS_SPACE_DESCRIPTOR, 0x2B, ACPI_ADDRESS_SPACE_TYPE_MEM, 0, 0, 32, 0, 0, 0, 0}, - {ACPI_ADDRESS_SPACE_DESCRIPTOR, 0x2B, ACPI_ADDRESS_SPACE_TYPE_MEM, 0, 6, 32, 0, 0, 0, 0}, - {ACPI_ADDRESS_SPACE_DESCRIPTOR, 0x2B, ACPI_ADDRESS_SPACE_TYPE_MEM, 0, 0, 64, 0, 0, 0, 0}, - {ACPI_ADDRESS_SPACE_DESCRIPTOR, 0x2B, ACPI_ADDRESS_SPACE_TYPE_MEM, 0, 6, 64, 0, 0, 0, 0}, - {ACPI_ADDRESS_SPACE_DESCRIPTOR, 0x2B, ACPI_ADDRESS_SPACE_TYPE_BUS, 0, 0, 0, 0, 255, 0, 255}}, - {ACPI_END_TAG_DESCRIPTOR, 0} -}; - - -EFI_STATUS -PciRbPollMem ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINT64 Mask, - IN UINT64 Value, - IN UINT64 Delay, - OUT UINT64 *Result - ) -{ - EFI_STATUS Status; - UINT64 NumberOfTicks; - UINT32 Remainder; - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - EFI_METRONOME_ARCH_PROTOCOL *Metronome; - - PCI_TRACE ("PciRbPollMem()"); - - RootBridgeInstance = INSTANCE_FROM_ROOT_BRIDGE_IO_THIS (This); - Metronome = METRONOME_FROM_ROOT_BRIDGE_INSTANCE (RootBridgeInstance); - - if (Result == NULL) { - return EFI_INVALID_PARAMETER; - } - - if (Width > EfiPciWidthUint64) { - return EFI_INVALID_PARAMETER; - } - - // No matter what, always do a single poll. - Status = This->Mem.Read (This, Width, Address, 1, Result); - if (EFI_ERROR (Status)) { - return Status; - } - if ((*Result & Mask) == Value) { - return EFI_SUCCESS; - } - - if (Delay == 0) { - return EFI_SUCCESS; - } - - NumberOfTicks = DivU64x32Remainder (Delay, (UINT32) Metronome->TickPeriod, &Remainder); - if (Remainder != 0) { - NumberOfTicks += 1; - } - NumberOfTicks += 1; - - while (NumberOfTicks) { - Metronome->WaitForTick (Metronome, 1); - - Status = This->Mem.Read (This, Width, Address, 1, Result); - if (EFI_ERROR (Status)) { - return Status; - } - - if ((*Result & Mask) == Value) { - return EFI_SUCCESS; - } - - NumberOfTicks -= 1; - } - - return EFI_TIMEOUT; -} - -EFI_STATUS -PciRbPollIo ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINT64 Mask, - IN UINT64 Value, - IN UINT64 Delay, - OUT UINT64 *Result - ) -{ - EFI_STATUS Status; - UINT64 NumberOfTicks; - UINT32 Remainder; - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - EFI_METRONOME_ARCH_PROTOCOL *Metronome; - - PCI_TRACE ("PciRbPollIo()"); - - RootBridgeInstance = INSTANCE_FROM_ROOT_BRIDGE_IO_THIS (This); - Metronome = METRONOME_FROM_ROOT_BRIDGE_INSTANCE (RootBridgeInstance); - - if (Result == NULL) { - return EFI_INVALID_PARAMETER; - } - - if (Width > EfiPciWidthUint64) { - return EFI_INVALID_PARAMETER; - } - - // No matter what, always do a single poll. - Status = This->Io.Read (This, Width, Address, 1, Result); - if (EFI_ERROR (Status)) { - return Status; - } - if ((*Result & Mask) == Value) { - return EFI_SUCCESS; - } - - if (Delay == 0) { - return EFI_SUCCESS; - } - - NumberOfTicks = DivU64x32Remainder (Delay, (UINT32) Metronome->TickPeriod, &Remainder); - if (Remainder != 0) { - NumberOfTicks += 1; - } - NumberOfTicks += 1; - - while (NumberOfTicks) { - Metronome->WaitForTick (Metronome, 1); - - Status = This->Io.Read (This, Width, Address, 1, Result); - if (EFI_ERROR (Status)) { - return Status; - } - - if ((*Result & Mask) == Value) { - return EFI_SUCCESS; - } - - NumberOfTicks -= 1; - } - - return EFI_TIMEOUT; -} - -EFI_STATUS -PciRbMemRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - EFI_CPU_IO2_PROTOCOL *CpuIo; - - PCI_TRACE ("PciRbMemRead()"); - - RootBridgeInstance = INSTANCE_FROM_ROOT_BRIDGE_IO_THIS (This); - CpuIo = CPUIO_FROM_ROOT_BRIDGE_INSTANCE (RootBridgeInstance); - - if (Buffer == NULL) { - return EFI_INVALID_PARAMETER; - } - - if (Width >= EfiPciWidthMaximum) { - return EFI_INVALID_PARAMETER; - } - - if (((Address < PCI_MEM32_BASE) || (Address > (PCI_MEM32_BASE + PCI_MEM32_SIZE))) && - ((Address < PCI_MEM64_BASE) || (Address > (PCI_MEM64_BASE + PCI_MEM64_SIZE)))) { - return EFI_INVALID_PARAMETER; - } - - return CpuIo->Mem.Read (CpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH)Width, Address, Count, Buffer); -} - -EFI_STATUS -PciRbMemWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - EFI_CPU_IO2_PROTOCOL *CpuIo; - - PCI_TRACE ("PciRbMemWrite()"); - - RootBridgeInstance = INSTANCE_FROM_ROOT_BRIDGE_IO_THIS (This); - CpuIo = CPUIO_FROM_ROOT_BRIDGE_INSTANCE (RootBridgeInstance); - - if (Buffer == NULL) { - return EFI_INVALID_PARAMETER; - } - - if (Width >= EfiPciWidthMaximum) { - return EFI_INVALID_PARAMETER; - } - - if (((Address < PCI_MEM32_BASE) || (Address > (PCI_MEM32_BASE + PCI_MEM32_SIZE))) && - ((Address < PCI_MEM64_BASE) || (Address > (PCI_MEM64_BASE + PCI_MEM64_SIZE)))) { - return EFI_INVALID_PARAMETER; - } - - return CpuIo->Mem.Write (CpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH)Width, Address, Count, Buffer); -} - -EFI_STATUS -PciRbIoRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - PCI_TRACE ("PciRbIoRead()"); - - if (Buffer == NULL) { - return EFI_INVALID_PARAMETER; - } - - if (Width >= EfiPciWidthMaximum) { - return EFI_INVALID_PARAMETER; - } - - // IO currently unsupported - return EFI_INVALID_PARAMETER; -} - -EFI_STATUS -PciRbIoWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - PCI_TRACE ("PciRbIoWrite()"); - - if (Buffer == NULL) { - return EFI_INVALID_PARAMETER; - } - - if (Width >= EfiPciWidthMaximum) { - return EFI_INVALID_PARAMETER; - } - - // IO currently unsupported - return EFI_INVALID_PARAMETER; -} - -EFI_STATUS -PciRbPciRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 EfiAddress, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - UINT32 Offset; - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - EFI_CPU_IO2_PROTOCOL *CpuIo; - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *EfiPciAddress; - UINT64 Address; - - EfiPciAddress = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *)&EfiAddress; - RootBridgeInstance = INSTANCE_FROM_ROOT_BRIDGE_IO_THIS (This); - CpuIo = CPUIO_FROM_ROOT_BRIDGE_INSTANCE (RootBridgeInstance); - - if (Buffer == NULL) { - return EFI_INVALID_PARAMETER; - } - - if (Width >= EfiPciWidthMaximum) { - return EFI_INVALID_PARAMETER; - } - - if (EfiPciAddress->ExtendedRegister) { - Offset = EfiPciAddress->ExtendedRegister; - } else { - Offset = EfiPciAddress->Register; - } - - // The UEFI PCI enumerator scans for devices at all possible addresses, - // and ignores some PCI rules - this results in some hardware being - // detected multiple times. We work around this by faking absent - // devices - if ((EfiPciAddress->Bus == 0) && ((EfiPciAddress->Device != 0) || (EfiPciAddress->Function != 0))) { - *((UINT32 *)Buffer) = 0xffffffff; - return EFI_SUCCESS; - } - if ((EfiPciAddress->Bus == 1) && ((EfiPciAddress->Device != 0) || (EfiPciAddress->Function != 0))) { - *((UINT32 *)Buffer) = 0xffffffff; - return EFI_SUCCESS; - } - - // Work around incorrect class ID in the root bridge - if ((EfiPciAddress->Bus == 0) && (EfiPciAddress->Device == 0) && (EfiPciAddress->Function == 0) && (Offset == 8)) { - *((UINT32 *)Buffer) = 0x06040001; - return EFI_SUCCESS; - } - - Address = PCI_ECAM_BASE + ((EfiPciAddress->Bus << 20) | - (EfiPciAddress->Device << 15) | - (EfiPciAddress->Function << 12) | Offset); - - if ((Address < PCI_ECAM_BASE) || (Address > PCI_ECAM_BASE + PCI_ECAM_SIZE)) { - return EFI_INVALID_PARAMETER; - } - - return CpuIo->Mem.Read (CpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH)Width, Address, Count, Buffer); -} - -EFI_STATUS -PciRbPciWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 EfiAddress, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - UINT32 Offset; - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - EFI_CPU_IO2_PROTOCOL *CpuIo; - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *EfiPciAddress; - UINT64 Address; - - EfiPciAddress = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *)&EfiAddress; - RootBridgeInstance = INSTANCE_FROM_ROOT_BRIDGE_IO_THIS (This); - CpuIo = CPUIO_FROM_ROOT_BRIDGE_INSTANCE (RootBridgeInstance); - - if (Buffer == NULL) { - return EFI_INVALID_PARAMETER; - } - - if (Width >= EfiPciWidthMaximum) { - return EFI_INVALID_PARAMETER; - } - - if (EfiPciAddress->ExtendedRegister) - Offset = EfiPciAddress->ExtendedRegister; - else - Offset = EfiPciAddress->Register; - - Address = PCI_ECAM_BASE + ((EfiPciAddress->Bus << 20) | - (EfiPciAddress->Device << 15) | - (EfiPciAddress->Function << 12) | Offset); - - if (Address < PCI_ECAM_BASE || Address > PCI_ECAM_BASE + PCI_ECAM_SIZE) { - return EFI_INVALID_PARAMETER; - } - - return CpuIo->Mem.Write (CpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH)Width, Address, Count, Buffer); -} - -EFI_STATUS -PciRbCopyMem ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 DestAddress, - IN UINT64 SrcAddress, - IN UINTN Count - ) -{ - EFI_STATUS Status; - BOOLEAN Direction; - UINTN Stride; - UINTN Index; - UINT64 Result; - - PCI_TRACE ("PciRbCopyMem()"); - - if (Width > EfiPciWidthUint64) { - return EFI_INVALID_PARAMETER; - } - - if (DestAddress == SrcAddress) { - return EFI_SUCCESS; - } - - Stride = (UINTN)(1 << Width); - - Direction = TRUE; - if ((DestAddress > SrcAddress) && (DestAddress < (SrcAddress + Count * Stride))) { - Direction = FALSE; - SrcAddress = SrcAddress + (Count-1) * Stride; - DestAddress = DestAddress + (Count-1) * Stride; - } - - for (Index = 0; Index < Count; Index++) { - Status = PciRbMemRead ( - This, - Width, - SrcAddress, - 1, - &Result - ); - if (EFI_ERROR (Status)) { - return Status; - } - Status = PciRbMemWrite ( - This, - Width, - DestAddress, - 1, - &Result - ); - if (EFI_ERROR (Status)) { - return Status; - } - if (Direction) { - SrcAddress += Stride; - DestAddress += Stride; - } else { - SrcAddress -= Stride; - DestAddress -= Stride; - } - } - return EFI_SUCCESS; -} - -EFI_STATUS -PciRbMap ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation, - IN VOID *HostAddress, - IN OUT UINTN *NumberOfBytes, - OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, - OUT VOID **Mapping - ) -{ - DMA_MAP_OPERATION DmaOperation; - - PCI_TRACE ("PciRbMap()"); - - if (Operation == EfiPciOperationBusMasterRead) { - DmaOperation = MapOperationBusMasterRead; - } else if (Operation == EfiPciOperationBusMasterWrite) { - DmaOperation = MapOperationBusMasterWrite; - } else if (Operation == EfiPciOperationBusMasterCommonBuffer) { - DmaOperation = MapOperationBusMasterCommonBuffer; - } else { - return EFI_INVALID_PARAMETER; - } - return DmaMap (DmaOperation, HostAddress, NumberOfBytes, DeviceAddress, Mapping); -} - -EFI_STATUS -PciRbUnMap ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN VOID *Mapping - ) -{ - PCI_TRACE ("PciRbUnMap()"); - return DmaUnmap (Mapping); -} - -EFI_STATUS -PciRbAllocateBuffer ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_ALLOCATE_TYPE Type, - IN EFI_MEMORY_TYPE MemoryType, - IN UINTN Pages, - IN OUT VOID **HostAddress, - IN UINT64 Attributes - ) -{ - PCI_TRACE ("PciRbAllocateBuffer()"); - - if (Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) { - return EFI_UNSUPPORTED; - } - - return DmaAllocateBuffer (MemoryType, Pages, HostAddress); -} - -EFI_STATUS -PciRbFreeBuffer ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN UINTN Pages, - IN VOID *HostAddress - ) -{ - PCI_TRACE ("PciRbFreeBuffer()"); - return DmaFreeBuffer (Pages, HostAddress); -} - -EFI_STATUS -PciRbFlush ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This - ) -{ - PCI_TRACE ("PciRbFlush()"); - - //TODO: Not supported yet - - return EFI_SUCCESS; -} - -EFI_STATUS -PciRbSetAttributes ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN UINT64 Attributes, - IN OUT UINT64 *ResourceBase, - IN OUT UINT64 *ResourceLength - ) -{ - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - - PCI_TRACE ("PciRbSetAttributes()"); - - RootBridgeInstance = INSTANCE_FROM_ROOT_BRIDGE_IO_THIS (This); - - if (Attributes) { - if ((Attributes & (~(RootBridgeInstance->Supports))) != 0) { - return EFI_UNSUPPORTED; - } - } - - //TODO: Cannot allowed to change attributes - if (Attributes & ~RootBridgeInstance->Attributes) { - return EFI_UNSUPPORTED; - } - - return EFI_SUCCESS; -} - -EFI_STATUS -PciRbGetAttributes ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - OUT UINT64 *Supported, - OUT UINT64 *Attributes - ) -{ - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - - PCI_TRACE ("PciRbGetAttributes()"); - - RootBridgeInstance = INSTANCE_FROM_ROOT_BRIDGE_IO_THIS (This); - - if (Attributes == NULL && Supported == NULL) { - return EFI_INVALID_PARAMETER; - } - - // Set the return value for Supported and Attributes - if (Supported) { - *Supported = RootBridgeInstance->Supports; - } - - if (Attributes) { - *Attributes = RootBridgeInstance->Attributes; - } - - return EFI_SUCCESS; -} - -EFI_STATUS -PciRbConfiguration ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - OUT VOID **Resources - ) -{ - PCI_ROOT_BRIDGE_INSTANCE *RootBridge; - UINTN Index; - - PCI_TRACE ("PciRbConfiguration()"); - - RootBridge = INSTANCE_FROM_ROOT_BRIDGE_IO_THIS (This); - - for (Index = 0; Index < ResTypeMax; Index++) { - //if (ResAlloc[Index].Length != 0) => Resource allocated - if (RootBridge->ResAlloc[Index].Length != 0) { - Configuration.SpaceDesp[Index].AddrRangeMin = RootBridge->ResAlloc[Index].Base; - Configuration.SpaceDesp[Index].AddrRangeMax = RootBridge->ResAlloc[Index].Base + RootBridge->ResAlloc[Index].Length - 1; - Configuration.SpaceDesp[Index].AddrLen = RootBridge->ResAlloc[Index].Length; - } - } - - // Set up Configuration for the bus - Configuration.SpaceDesp[Index].AddrRangeMin = RootBridge->BusStart; - Configuration.SpaceDesp[Index].AddrLen = RootBridge->BusLength; - - *Resources = &Configuration; - return EFI_SUCCESS; -} - -EFI_STATUS -PciRbConstructor ( - IN PCI_HOST_BRIDGE_INSTANCE *HostBridge, - IN UINT32 PciAcpiUid, - IN UINT64 MemAllocAttributes - ) -{ - PCI_ROOT_BRIDGE_INSTANCE* RootBridge; - EFI_STATUS Status; - - PCI_TRACE ("PciRbConstructor()"); - - // Allocate Memory for the Instance from a Template - RootBridge = AllocateZeroPool (sizeof (PCI_ROOT_BRIDGE_INSTANCE)); - if (RootBridge == NULL) { - PCI_TRACE ("PciRbConstructor(): ERROR: Out of Resources"); - return EFI_OUT_OF_RESOURCES; - } - RootBridge->Signature = PCI_ROOT_BRIDGE_SIGNATURE; - CopyMem (&(RootBridge->DevicePath), &gDevicePathTemplate, sizeof (EFI_PCI_ROOT_BRIDGE_DEVICE_PATH)); - CopyMem (&(RootBridge->Io), &gIoTemplate, sizeof (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL)); - - // Set Parent Handle - RootBridge->Io.ParentHandle = HostBridge->Handle; - - // Attach the Root Bridge to the PCI Host Bridge Instance - RootBridge->HostBridge = HostBridge; - - // Set Device Path for this Root Bridge - RootBridge->DevicePath.Acpi.UID = PciAcpiUid; - - RootBridge->BusStart = FixedPcdGet32 (PcdPciBusMin); - RootBridge->BusLength = FixedPcdGet32 (PcdPciBusMax) - FixedPcdGet32 (PcdPciBusMin) + 1; - - // PCI Attributes - RootBridge->Supports = 0; - RootBridge->Attributes = 0; - - // Install Protocol Instances. It will also generate a device handle for the PCI Root Bridge - Status = gBS->InstallMultipleProtocolInterfaces ( - &RootBridge->Handle, - &gEfiDevicePathProtocolGuid, &RootBridge->DevicePath, - &gEfiPciRootBridgeIoProtocolGuid, &RootBridge->Io, - NULL - ); - ASSERT (RootBridge->Signature == PCI_ROOT_BRIDGE_SIGNATURE); - if (EFI_ERROR (Status)) { - PCI_TRACE ("PciRbConstructor(): ERROR: Fail to install Protocol Interfaces"); - FreePool (RootBridge); - return EFI_DEVICE_ERROR; - } - - HostBridge->RootBridge = RootBridge; - return EFI_SUCCESS; -} - -EFI_STATUS -PciRbDestructor ( - IN PCI_ROOT_BRIDGE_INSTANCE* RootBridge - ) -{ - EFI_STATUS Status; - - Status = gBS->UninstallMultipleProtocolInterfaces ( - RootBridge->Handle, - &gEfiDevicePathProtocolGuid, &RootBridge->DevicePath, - &gEfiPciRootBridgeIoProtocolGuid, &RootBridge->Io, - NULL - ); - - FreePool (RootBridge); - - return Status; -} diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c deleted file mode 100644 index 06de6d5d9a..0000000000 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c +++ /dev/null @@ -1,167 +0,0 @@ -/** @file -* Initialize the XPress-RICH3 PCIe Root complex -* -* Copyright (c) 2011-2015, ARM Ltd. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#include "PciHostBridge.h" - -#include - -#include "ArmPlatform.h" - -EFI_CPU_ARCH_PROTOCOL *mCpu; - -#define PCI_BRIDGE_REVISION_ID 1 -#define CLASS_CODE_REGISTER(Class, SubClass, ProgIf) ((Class << 16) | (SubClass << 8) | ProgIf) -#define PLDA_BRIDGE_CCR CLASS_CODE_REGISTER(PCI_CLASS_BRIDGE, \ - PCI_CLASS_BRIDGE_P2P, \ - PCI_IF_BRIDGE_P2P) - -STATIC -VOID -SetTranslationAddressEntry ( - IN EFI_CPU_IO2_PROTOCOL *CpuIo, - IN UINTN Entry, - IN UINT64 SourceAddress, - IN UINT64 TranslatedAddress, - IN UINT64 TranslationSize, - IN UINT64 TranslationParameter - ) -{ - UINTN Log2Size = HighBitSet64 (TranslationSize); - - // Ensure the size is a power of two. Restriction form the AXI Translation logic - // Othwerwise we increase the translation size - if (TranslationSize != (1ULL << Log2Size)) { - DEBUG ((EFI_D_WARN, "PCI: The size 0x%lX of the region 0x%lx has been increased to " - "be a power of two for the AXI translation table.\n", - TranslationSize, SourceAddress)); - Log2Size++; - } - - PCIE_ROOTPORT_WRITE32 (Entry + PCI_ATR_SRC_ADDR_LOW_SIZE, - (UINT32)SourceAddress | ((Log2Size - 1) << 1) | 0x1); - PCIE_ROOTPORT_WRITE32 (Entry + PCI_ATR_SRC_ADDR_HI, SourceAddress >> 32); - - PCIE_ROOTPORT_WRITE32 (Entry + PCI_ATR_TRSL_ADDR_LOW, (UINT32)TranslatedAddress); - PCIE_ROOTPORT_WRITE32 (Entry + PCI_ATR_TRSL_ADDR_HI, TranslatedAddress >> 32); - - PCIE_ROOTPORT_WRITE32 (Entry + PCI_ATR_TRSL_PARAM, TranslationParameter); -} - -EFI_STATUS -HWPciRbInit ( - IN EFI_CPU_IO2_PROTOCOL *CpuIo - ) -{ - UINT32 Value; - UINT32 Index; - UINTN TranslationTable; - - PCI_TRACE ("VExpressPciRbInit()"); - - PCI_TRACE ("PCIe Setting up Address Translation"); - - PCIE_ROOTPORT_WRITE32 (PCIE_BAR_WIN, PCIE_BAR_WIN_SUPPORT_IO | PCIE_BAR_WIN_SUPPORT_MEM | PCIE_BAR_WIN_SUPPORT_MEM64); - - // Setup the PCI Configuration Registers - // Offset 0a: SubClass 04 PCI-PCI Bridge - // Offset 0b: BaseClass 06 Bridge Device - // The Class Code register is a 24 bit and can be configured by setting up the PCIE_PCI_IDS - // Refer [1] Chapter 13 - PCIE_ROOTPORT_WRITE32 (PCIE_PCI_IDS + PCIE_PCI_IDS_CLASSCODE_OFFSET, ((PLDA_BRIDGE_CCR << 8) | PCI_BRIDGE_REVISION_ID)); - - // - // PCIE Window 0 -> AXI4 Slave 0 Address Translations - // - TranslationTable = VEXPRESS_ATR_PCIE_WIN0; - - // MSI Support - SetTranslationAddressEntry (CpuIo, TranslationTable, ARM_JUNO_GIV2M_MSI_BASE, ARM_JUNO_GIV2M_MSI_BASE, - ARM_JUNO_GIV2M_MSI_SZ, PCI_ATR_TRSLID_AXIDEVICE); - TranslationTable += PCI_ATR_ENTRY_SIZE; - - // System Memory Support - SetTranslationAddressEntry (CpuIo, TranslationTable, PcdGet64 (PcdSystemMemoryBase), PcdGet64 (PcdSystemMemoryBase), - PcdGet64 (PcdSystemMemorySize), PCI_ATR_TRSLID_AXIMEMORY); - TranslationTable += PCI_ATR_ENTRY_SIZE; - SetTranslationAddressEntry (CpuIo, TranslationTable, ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE, ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE, - ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ, PCI_ATR_TRSLID_AXIMEMORY); - - // - // PCIE Window 0 -> AXI4 Slave 0 Address Translations - // - TranslationTable = VEXPRESS_ATR_AXI4_SLV1; - - // PCI ECAM Support - SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_ECAM_BASE, PCI_ECAM_BASE, PCI_ECAM_SIZE, PCI_ATR_TRSLID_PCIE_CONF); - TranslationTable += PCI_ATR_ENTRY_SIZE; - - // PCI IO Support - SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_IO_BASE, PCI_IO_BASE, PCI_IO_SIZE, PCI_ATR_TRSLID_PCIE_IO); - TranslationTable += PCI_ATR_ENTRY_SIZE; - - // PCI MEM32 Support - SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_MEM32_BASE, PCI_MEM32_BASE, PCI_MEM32_SIZE, PCI_ATR_TRSLID_PCIE_MEMORY); - TranslationTable += PCI_ATR_ENTRY_SIZE; - - // PCI MEM64 Support - SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_MEM64_BASE, PCI_MEM64_BASE, PCI_MEM64_SIZE, PCI_ATR_TRSLID_PCIE_MEMORY); - - // Add credits - PCIE_ROOTPORT_WRITE32 (PCIE_VC_CRED, 0x00f0b818); - PCIE_ROOTPORT_WRITE32 (PCIE_VC_CRED + 4, 0x1); - - // Allow ECRC - PCIE_ROOTPORT_WRITE32 (PCIE_PEX_SPC2, 0x6006); - - // Reset controller - PCIE_CONTROL_WRITE32 (PCIE_CONTROL_RST_CTL, PCIE_CONTROL_RST_CTL_RCPHY_REL); - - // Wait for reset - for (Index = 0; Index < 1000; Index++) { - gBS->Stall (1000); - PCIE_CONTROL_READ32 (PCIE_CONTROL_RST_STS, Value); - if ((Value & PCIE_CONTROL_RST_STS_RCPHYPLL_OUT) == PCIE_CONTROL_RST_STS_RCPHYPLL_OUT) { - break; - } - } - - // Check for reset - if (!(Value & PCIE_CONTROL_RST_STS_RCPHYPLL_OUT)) { - DEBUG ((EFI_D_ERROR, "PCIe failed to come out of reset: %x.\n", Value)); - return EFI_NOT_READY; - } - - gBS->Stall (1000); - PCI_TRACE ("Checking link Status..."); - - // Wait for Link Up - for (Index = 0; Index < 1000; Index++) { - gBS->Stall (1000); - PCIE_ROOTPORT_READ32 (VEXPRESS_BASIC_STATUS, Value); - if (Value & LINK_UP) { - break; - } - } - - // Check for link up - if (!(Value & LINK_UP)) { - DEBUG ((EFI_D_ERROR, "PCIe link not up: %x.\n", Value)); - return EFI_NOT_READY; - } - - PCIE_ROOTPORT_WRITE32 (PCIE_IMASK_LOCAL, PCIE_INT_MSI | PCIE_INT_INTx); - - return EFI_SUCCESS; -} diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.h b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.h deleted file mode 100644 index a0c11a7056..0000000000 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.h +++ /dev/null @@ -1,111 +0,0 @@ -/** @file -* Header containing the Xpress-RICH3 PCIe Root Complex specific values -* -* Copyright (c) 2011-2015, ARM Ltd. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#ifndef __XPRESS_RICH3_H__ -#define __XPRESS_RICH3_H__ - -#include -#include - -#define PCI_ECAM_BASE FixedPcdGet64 (PcdPciConfigurationSpaceBaseAddress) -#define PCI_ECAM_SIZE FixedPcdGet64 (PcdPciConfigurationSpaceSize) -#define PCI_IO_BASE FixedPcdGet64 (PcdPciIoBase) -#define PCI_IO_SIZE FixedPcdGet64 (PcdPciIoSize) -#define PCI_MEM32_BASE FixedPcdGet64 (PcdPciMmio32Base) -#define PCI_MEM32_SIZE FixedPcdGet64 (PcdPciMmio32Size) -#define PCI_MEM64_BASE FixedPcdGet64 (PcdPciMmio64Base) -#define PCI_MEM64_SIZE FixedPcdGet64 (PcdPciMmio64Size) - -/* - * Bridge Internal Registers - */ - -// PCIe Available Credit Settings -#define PCIE_VC_CRED 0x090 -// PCIe PCI Standard Configuration Identification Settings registers -#define PCIE_PCI_IDS 0x098 -#define PCIE_PCI_IDS_CLASSCODE_OFFSET 0x4 -// PCIe Specific 2 Capabilities Settings -#define PCIE_PEX_SPC2 0x0d8 -// PCIe Windows Settings register -#define PCIE_BAR_WIN 0x0FC -// Local Processor Interrupt Mask -#define PCIE_IMASK_LOCAL 0x180 - -#define PCIE_BAR_WIN_SUPPORT_IO BIT0 -#define PCIE_BAR_WIN_SUPPORT_IO32 BIT1 -#define PCIE_BAR_WIN_SUPPORT_MEM BIT2 -#define PCIE_BAR_WIN_SUPPORT_MEM64 BIT3 - -#define PCIE_INT_MSI BIT28 -#define PCIE_INT_A BIT24 -#define PCIE_INT_B BIT25 -#define PCIE_INT_C BIT26 -#define PCIE_INT_D BIT27 -#define PCIE_INT_INTx (PCIE_INT_A | PCIE_INT_B |\ - PCIE_INT_C | PCIE_INT_D) - -/* - * PCIe Control Registers - */ -#define PCIE_CONTROL_RST_CTL 0x1004 -#define PCIE_CONTROL_RST_STS 0x1008 - -/* - * PCI Express Address Translation registers - * All are offsets from PcdPcieControlBaseAddress - */ -#define VEXPRESS_ATR_PCIE_WIN0 0x600 -#define VEXPRESS_ATR_AXI4_SLV0 0x800 -#define VEXPRESS_ATR_AXI4_SLV1 0x820 - -#define PCI_ATR_ENTRY_SIZE 0x20 -#define PCI_ATR_SRC_ADDR_LOW_SIZE 0 -#define PCI_ATR_SRC_ADDR_HI 0x4 -#define PCI_ATR_TRSL_ADDR_LOW 0x8 -#define PCI_ATR_TRSL_ADDR_HI 0xc -#define PCI_ATR_TRSL_PARAM 0x10 - -#define PCI_ATR_TRSLID_AXIDEVICE 0x420004 -#define PCI_ATR_TRSLID_AXIMEMORY 0x4e0004 -#define PCI_ATR_TRSLID_PCIE_CONF 0x000001 -#define PCI_ATR_TRSLID_PCIE_IO 0x020000 -#define PCI_ATR_TRSLID_PCIE_MEMORY 0x000000 - -#define PCIE_CONTROL_RST_CTL_RC_REL (1 << 1) -#define PCIE_CONTROL_RST_CTL_PHY_REL (1 << 0) -#define PCIE_CONTROL_RST_CTL_RCPHY_REL (PCIE_CONTROL_RST_CTL_RC_REL | PCIE_CONTROL_RST_CTL_PHY_REL) - -#define PCIE_CONTROL_RST_STS_RC_ST (1 << 2) -#define PCIE_CONTROL_RST_STS_PHY_ST (1 << 1) -#define PCIE_CONTROL_RST_STS_PLL_ST (1 << 0) -#define PCIE_CONTROL_RST_STS_RCPHYPLL_OUT (PCIE_CONTROL_RST_STS_RC_ST | PCIE_CONTROL_RST_STS_PHY_ST | PCIE_CONTROL_RST_STS_PLL_ST) - -#define VEXPRESS_BASIC_STATUS 0x18 -#define LINK_UP 0xff - -/* - * Initialize Versatile Express PCIe Host Bridge - */ -EFI_STATUS -VExpressPciRbInit ( - IN EFI_CPU_IO2_PROTOCOL *CpuIo - ); - -// Does not support neither EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM -// nor EFI_PCI_HOST_BRIDGE_MEM64_DECODE -#define PCI_MEMORY_ALLOCATION_ATTRIBUTES 0 - -#endif -- cgit v1.2.3