From 73ca50096eea3edc64e2c635b6b6d99fbb5572d5 Mon Sep 17 00:00:00 2001 From: Brendan Jackman Date: Thu, 8 May 2014 14:59:04 +0000 Subject: ARM Packages: Use AND instead of BIC instruction with immediate AARCH64 does not have a BIC-with-immediate instruction. GAS assembles it as a AND with the immediate inverted, but Clang's integrated assembler emits an error. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman Reviewed-by: Olivier Martin git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15509 6f19259b-4bc3-4df7-8a09-765794883524 --- .../ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/GicV3.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'ArmPlatformPkg/ArmVExpressPkg/Library') diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/GicV3.S b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/GicV3.S index 7d9c25c769..035e095493 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/GicV3.S +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/GicV3.S @@ -12,6 +12,7 @@ // #include +#include #ifndef __clang__ // Register definitions used by GCC for GICv3 access. @@ -64,6 +65,6 @@ ASM_PFX(InitializeGicV3): // Remove the SCR.NS bit mrs x0, scr_el3 - bic x0, x0, #1 + and x0, x0, #~SCR_NS msr scr_el3, x0 ret -- cgit v1.2.3