From 48edf6be7fd35467b77e6ebf3707094db4da6d6f Mon Sep 17 00:00:00 2001 From: Leif Lindholm Date: Fri, 23 Jan 2015 16:10:00 +0000 Subject: ArmPlatformPkg: detect correct pl011 fifo depth pl011 releases earlier than r1p5 has a fifo depth of 16 bytes, whereas version r1p5 upwards has a fifo depth of 32 bytes. The pl011 driver was hardwired to 32 byte depth, causing dropped characters on some platforms (including default settings on FVP Base and Foundation models). Update driver to select 16 or 32 on port initialization by checking the component revision. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm Reviewed-by: Olivier Martin git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16656 6f19259b-4bc3-4df7-8a09-765794883524 --- ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'ArmPlatformPkg/Drivers/PL011Uart') diff --git a/ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.c b/ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.c index 7e74a05df7..8b256de945 100644 --- a/ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.c +++ b/ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.c @@ -50,12 +50,15 @@ PL011UartInitializePort ( LineControl = 0; - // The PL011 supports a buffer of either 1 or 32 chars. Therefore we can accept + // The PL011 supports a buffer of 1, 16 or 32 chars. Therefore we can accept // 1 char buffer as the minimum fifo size. Because everything can be rounded down, // there is no maximum fifo size. if ((*ReceiveFifoDepth == 0) || (*ReceiveFifoDepth >= 32)) { LineControl |= PL011_UARTLCR_H_FEN; - *ReceiveFifoDepth = 32; + if (PL011_UARTPID2_VER (MmioRead32 (UartBase + UARTPID2)) > PL011_VER_R1P4) + *ReceiveFifoDepth = 32; + else + *ReceiveFifoDepth = 16; } else { ASSERT (*ReceiveFifoDepth < 32); // Nothing else to do. 1 byte fifo is default. -- cgit v1.2.3