From 93b429fc213bd935b5d90c71e8e8b4523253e445 Mon Sep 17 00:00:00 2001 From: oliviermartin Date: Thu, 2 Aug 2012 11:20:37 +0000 Subject: ArmPlatformPkg/PL180MciDxe: Fixed coding style Signed-off-by: Olivier Martin git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13586 6f19259b-4bc3-4df7-8a09-765794883524 --- ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.c | 215 +++++++++++++------------- ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.h | 162 +++++++++++-------- 2 files changed, 208 insertions(+), 169 deletions(-) (limited to 'ArmPlatformPkg/Drivers') diff --git a/ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.c b/ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.c index b79845dccb..313f2af9fd 100644 --- a/ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.c +++ b/ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.c @@ -1,7 +1,7 @@ /** @file This file implement the MMC Host Protocol for the ARM PrimeCell PL180. - Copyright (c) 2011, ARM Limited. All rights reserved. + Copyright (c) 2011-2012, ARM Limited. All rights reserved. This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License @@ -27,12 +27,15 @@ EFI_MMC_HOST_PROTOCOL *gpMmcHost; #define MMCI0_POW2_BLOCKLEN 9 #define MMCI0_TIMEOUT 1000 +#define SYS_MCI_CARDIN BIT0 +#define SYS_MCI_WPROT BIT1 + BOOLEAN MciIsPowerOn ( VOID ) { - return ((MmioRead32(MCI_POWER_CONTROL_REG) & 0x3) == MCI_POWER_ON); + return ((MmioRead32 (MCI_POWER_CONTROL_REG) & MCI_POWER_ON) == MCI_POWER_ON); } EFI_STATUS @@ -40,7 +43,7 @@ MciInitialize ( VOID ) { - MCI_TRACE("MciInitialize()"); + MCI_TRACE ("MciInitialize()"); return EFI_SUCCESS; } @@ -49,7 +52,7 @@ MciIsCardPresent ( IN EFI_MMC_HOST_PROTOCOL *This ) { - return (MmioRead32(FixedPcdGet32(PcdPL180SysMciRegAddress)) & 1); + return (MmioRead32 (FixedPcdGet32 (PcdPL180SysMciRegAddress)) & SYS_MCI_CARDIN); } BOOLEAN @@ -57,7 +60,7 @@ MciIsReadOnly ( IN EFI_MMC_HOST_PROTOCOL *This ) { - return (MmioRead32(FixedPcdGet32(PcdPL180SysMciRegAddress)) & 2); + return (MmioRead32 (FixedPcdGet32 (PcdPL180SysMciRegAddress)) & SYS_MCI_WPROT); } #if 0 @@ -92,13 +95,13 @@ MciPrepareDataPath ( ) { // Set Data Length & Data Timer - MmioWrite32 (MCI_DATA_TIMER_REG,0xFFFFFFF); - MmioWrite32 (MCI_DATA_LENGTH_REG,MMCI0_BLOCKLEN); + MmioWrite32 (MCI_DATA_TIMER_REG, 0xFFFFFFF); + MmioWrite32 (MCI_DATA_LENGTH_REG, MMCI0_BLOCKLEN); #ifndef USE_STREAM - //Note: we are using a hardcoded BlockLen (=512). If we decide to use a variable size, we could - // compute the pow2 of BlockLen with the above function GetPow2BlockLen() - MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_DMA_ENABLE | TransferDirection | (MMCI0_POW2_BLOCKLEN << 4)); + //Note: we are using a hardcoded BlockLen (==512). If we decide to use a variable size, we could + // compute the pow2 of BlockLen with the above function GetPow2BlockLen () + MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_DMA_ENABLE | TransferDirection | (MMCI0_POW2_BLOCKLEN << 4)); #else MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_DMA_ENABLE | TransferDirection | MCI_DATACTL_STREAM_TRANS); #endif @@ -111,21 +114,21 @@ MciSendCommand ( IN UINT32 Argument ) { - UINT32 Status; - UINT32 Cmd; - UINTN RetVal; - UINTN CmdCtrlReg; + UINT32 Status; + UINT32 Cmd; + UINTN RetVal; + UINTN CmdCtrlReg; RetVal = EFI_SUCCESS; if ((MmcCmd == MMC_CMD17) || (MmcCmd == MMC_CMD11)) { - MciPrepareDataPath(MCI_DATACTL_CARD_TO_CONT); + MciPrepareDataPath (MCI_DATACTL_CARD_TO_CONT); } else if ((MmcCmd == MMC_CMD24) || (MmcCmd == MMC_CMD20)) { - MciPrepareDataPath(MCI_DATACTL_CONT_TO_CARD); + MciPrepareDataPath (MCI_DATACTL_CONT_TO_CARD); } // Create Command for PL180 - Cmd = (MMC_GET_INDX(MmcCmd) & INDX_MASK) | MCI_CPSM_ENABLED; + Cmd = (MMC_GET_INDX (MmcCmd) & INDX_MASK) | MCI_CPSM_ENABLE; if (MmcCmd & MMC_CMD_WAIT_RESPONSE) { Cmd |= MCI_CPSM_WAIT_RESPONSE; } @@ -135,29 +138,29 @@ MciSendCommand ( } // Clear Status register static flags - MmioWrite32(MCI_CLEAR_STATUS_REG,0x7FF); + MmioWrite32 (MCI_CLEAR_STATUS_REG, MCI_CLR_ALL_STATUS); - //Write to command argument register - MmioWrite32(MCI_ARGUMENT_REG,Argument); + // Write to command argument register + MmioWrite32 (MCI_ARGUMENT_REG, Argument); - //Write to command register - MmioWrite32(MCI_COMMAND_REG,Cmd); + // Write to command register + MmioWrite32 (MCI_COMMAND_REG, Cmd); if (Cmd & MCI_CPSM_WAIT_RESPONSE) { - Status = MmioRead32(MCI_STATUS_REG); + Status = MmioRead32 (MCI_STATUS_REG); while (!(Status & (MCI_STATUS_CMD_RESPEND | MCI_STATUS_CMD_CMDCRCFAIL | MCI_STATUS_CMD_CMDTIMEOUT | MCI_STATUS_CMD_START_BIT_ERROR))) { Status = MmioRead32(MCI_STATUS_REG); } if ((Status & MCI_STATUS_CMD_START_BIT_ERROR)) { - DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) Start bit Error! Response:0x%X Status:0x%x\n",(Cmd & 0x3F),MmioRead32(MCI_RESPONSE0_REG),Status)); + DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) Start bit Error! Response:0x%X Status:0x%x\n", (Cmd & 0x3F), MmioRead32 (MCI_RESPONSE0_REG), Status)); RetVal = EFI_NO_RESPONSE; goto Exit; } else if ((Status & MCI_STATUS_CMD_CMDTIMEOUT)) { - //DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) TIMEOUT! Response:0x%X Status:0x%x\n",(Cmd & 0x3F),MmioRead32(MCI_RESPONSE0_REG),Status)); + //DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) TIMEOUT! Response:0x%X Status:0x%x\n", (Cmd & 0x3F), MmioRead32 (MCI_RESPONSE0_REG), Status)); RetVal = EFI_TIMEOUT; goto Exit; - } else if ((!(MmcCmd & MMC_CMD_NO_CRC_RESPONSE)) && (Status & MCI_STATUS_CMD_CMDCRCFAIL)) { + } else if ((! (MmcCmd & MMC_CMD_NO_CRC_RESPONSE)) && (Status & MCI_STATUS_CMD_CMDCRCFAIL)) { // The CMD1 and response type R3 do not contain CRC. We should ignore the CRC failed Status. RetVal = EFI_CRC_ERROR; goto Exit; @@ -191,10 +194,10 @@ MciSendCommand ( } Exit: - // Disable Command Path - CmdCtrlReg = MmioRead32(MCI_COMMAND_REG); - MmioWrite32(MCI_COMMAND_REG, (CmdCtrlReg & ~MCI_CPSM_ENABLED)); - return RetVal; + // Disable Command Path + CmdCtrlReg = MmioRead32 (MCI_COMMAND_REG); + MmioWrite32 (MCI_COMMAND_REG, (CmdCtrlReg & ~MCI_CPSM_ENABLE)); + return RetVal; } EFI_STATUS @@ -208,16 +211,18 @@ MciReceiveResponse ( return EFI_INVALID_PARAMETER; } - if ((Type == MMC_RESPONSE_TYPE_R1) || (Type == MMC_RESPONSE_TYPE_R1b) || - (Type == MMC_RESPONSE_TYPE_R3) || (Type == MMC_RESPONSE_TYPE_R6) || - (Type == MMC_RESPONSE_TYPE_R7)) + if ( (Type == MMC_RESPONSE_TYPE_R1) + || (Type == MMC_RESPONSE_TYPE_R1b) + || (Type == MMC_RESPONSE_TYPE_R3) + || (Type == MMC_RESPONSE_TYPE_R6) + || (Type == MMC_RESPONSE_TYPE_R7)) { - Buffer[0] = MmioRead32(MCI_RESPONSE3_REG); + Buffer[0] = MmioRead32 (MCI_RESPONSE3_REG); } else if (Type == MMC_RESPONSE_TYPE_R2) { - Buffer[0] = MmioRead32(MCI_RESPONSE0_REG); - Buffer[1] = MmioRead32(MCI_RESPONSE1_REG); - Buffer[2] = MmioRead32(MCI_RESPONSE2_REG); - Buffer[3] = MmioRead32(MCI_RESPONSE3_REG); + Buffer[0] = MmioRead32 (MCI_RESPONSE0_REG); + Buffer[1] = MmioRead32 (MCI_RESPONSE1_REG); + Buffer[2] = MmioRead32 (MCI_RESPONSE2_REG); + Buffer[3] = MmioRead32 (MCI_RESPONSE3_REG); } return EFI_SUCCESS; @@ -244,7 +249,7 @@ MciReadBlockData ( Finish = MMCI0_BLOCKLEN / 4; do { // Read the Status flags - Status = MmioRead32(MCI_STATUS_REG); + Status = MmioRead32 (MCI_STATUS_REG); // Do eight reads if possible else a single read if (Status & MCI_STATUS_CMD_RXFIFOHALFFULL) { @@ -269,16 +274,16 @@ MciReadBlockData ( Loop++; } else { //Check for error conditions and timeouts - if(Status & MCI_STATUS_CMD_DATATIMEOUT) { - DEBUG ((EFI_D_ERROR, "MciReadBlockData(): TIMEOUT! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status)); + if (Status & MCI_STATUS_CMD_DATATIMEOUT) { + DEBUG ((EFI_D_ERROR, "MciReadBlockData(): TIMEOUT! Response:0x%X Status:0x%x\n", MmioRead32 (MCI_RESPONSE0_REG), Status)); RetVal = EFI_TIMEOUT; break; - } else if(Status & MCI_STATUS_CMD_DATACRCFAIL) { - DEBUG ((EFI_D_ERROR, "MciReadBlockData(): CRC Error! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status)); + } else if (Status & MCI_STATUS_CMD_DATACRCFAIL) { + DEBUG ((EFI_D_ERROR, "MciReadBlockData(): CRC Error! Response:0x%X Status:0x%x\n", MmioRead32 (MCI_RESPONSE0_REG), Status)); RetVal = EFI_CRC_ERROR; break; - } else if(Status & MCI_STATUS_CMD_START_BIT_ERROR) { - DEBUG ((EFI_D_ERROR, "MciReadBlockData(): Start-bit Error! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status)); + } else if (Status & MCI_STATUS_CMD_START_BIT_ERROR) { + DEBUG ((EFI_D_ERROR, "MciReadBlockData(): Start-bit Error! Response:0x%X Status:0x%x\n", MmioRead32 (MCI_RESPONSE0_REG), Status)); RetVal = EFI_NO_RESPONSE; break; } @@ -289,14 +294,14 @@ MciReadBlockData ( } } while ((Loop < Finish)); - //Clear Status flags - MmioWrite32(MCI_CLEAR_STATUS_REG, 0x7FF); + // Clear Status flags + MmioWrite32 (MCI_CLEAR_STATUS_REG, MCI_CLR_ALL_STATUS); - //Disable Data path - DataCtrlReg = MmioRead32(MCI_DATA_CTL_REG); - MmioWrite32(MCI_DATA_CTL_REG, (DataCtrlReg & 0xFE)); + //Disable Data path + DataCtrlReg = MmioRead32 (MCI_DATA_CTL_REG); + MmioWrite32 (MCI_DATA_CTL_REG, (DataCtrlReg & MCI_DATACTL_DISABLE_MASK)); - return RetVal; + return RetVal; } EFI_STATUS @@ -322,7 +327,7 @@ MciWriteBlockData ( Timer = MMCI0_TIMEOUT * 100; do { // Read the Status flags - Status = MmioRead32(MCI_STATUS_REG); + Status = MmioRead32 (MCI_STATUS_REG); // Do eight writes if possible else a single write if (Status & MCI_STATUS_CMD_TXFIFOHALFEMPTY) { @@ -346,16 +351,16 @@ MciWriteBlockData ( MmioWrite32(MCI_FIFO_REG, Buffer[Loop]); Loop++; } else { - //Check for error conditions and timeouts - if(Status & MCI_STATUS_CMD_DATATIMEOUT) { - DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): TIMEOUT! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status)); + // Check for error conditions and timeouts + if (Status & MCI_STATUS_CMD_DATATIMEOUT) { + DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): TIMEOUT! Response:0x%X Status:0x%x\n", MmioRead32 (MCI_RESPONSE0_REG), Status)); RetVal = EFI_TIMEOUT; goto Exit; - } else if(Status & MCI_STATUS_CMD_DATACRCFAIL) { - DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): CRC Error! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status)); + } else if (Status & MCI_STATUS_CMD_DATACRCFAIL) { + DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): CRC Error! Response:0x%X Status:0x%x\n", MmioRead32 (MCI_RESPONSE0_REG), Status)); RetVal = EFI_CRC_ERROR; goto Exit; - } else if(Status & MCI_STATUS_CMD_TX_UNDERRUN) { + } else if (Status & MCI_STATUS_CMD_TX_UNDERRUN) { DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): TX buffer Underrun! Response:0x%X Status:0x%x, Number of bytes written 0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status, Loop)); RetVal = EFI_BUFFER_TOO_SMALL; ASSERT(0); @@ -365,37 +370,37 @@ MciWriteBlockData ( } while (Loop < Finish); // Wait for FIFO to drain - Timer = MMCI0_TIMEOUT * 60; - Status = MmioRead32(MCI_STATUS_REG); + Timer = MMCI0_TIMEOUT * 60; + Status = MmioRead32 (MCI_STATUS_REG); #ifndef USE_STREAM // Single block - while (((Status & MCI_STATUS_CMD_TXDONE) != MCI_STATUS_CMD_TXDONE) && Timer) { + while (((Status & MCI_STATUS_TXDONE) != MCI_STATUS_TXDONE) && Timer) { #else // Stream while (((Status & MCI_STATUS_CMD_DATAEND) != MCI_STATUS_CMD_DATAEND) && Timer) { #endif NanoSecondDelay(10); - Status = MmioRead32(MCI_STATUS_REG); + Status = MmioRead32 (MCI_STATUS_REG); Timer--; } - if(Timer == 0) { + if (Timer == 0) { DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): Data End timeout Number of bytes written 0x%x\n",Loop)); - ASSERT(Timer > 0); + ASSERT (Timer > 0); return EFI_TIMEOUT; } - //Clear Status flags - MmioWrite32(MCI_CLEAR_STATUS_REG, 0x7FF); + // Clear Status flags + MmioWrite32 (MCI_CLEAR_STATUS_REG, MCI_CLR_ALL_STATUS); if (Timer == 0) { RetVal = EFI_TIMEOUT; } Exit: - //Disable Data path - DataCtrlReg = MmioRead32(MCI_DATA_CTL_REG); - MmioWrite32(MCI_DATA_CTL_REG, (DataCtrlReg & 0xFE)); - return RetVal; + // Disable Data path + DataCtrlReg = MmioRead32 (MCI_DATA_CTL_REG); + MmioWrite32 (MCI_DATA_CTL_REG, (DataCtrlReg & MCI_DATACTL_DISABLE_MASK)); + return RetVal; } EFI_STATUS @@ -406,59 +411,59 @@ MciNotifyState ( { UINT32 Data32; - switch(State) { + switch (State) { case MmcInvalidState: - ASSERT(0); + ASSERT (0); break; case MmcHwInitializationState: // If device already turn on then restart it - Data32 = MmioRead32(MCI_POWER_CONTROL_REG); + Data32 = MmioRead32 (MCI_POWER_CONTROL_REG); if ((Data32 & 0x2) == MCI_POWER_UP) { - MCI_TRACE("MciNotifyState(MmcHwInitializationState): TurnOff MCI"); + MCI_TRACE ("MciNotifyState(MmcHwInitializationState): TurnOff MCI"); // Turn off - MmioWrite32(MCI_CLOCK_CONTROL_REG, 0); - MmioWrite32(MCI_POWER_CONTROL_REG, 0); - MicroSecondDelay(100); + MmioWrite32 (MCI_CLOCK_CONTROL_REG, 0); + MmioWrite32 (MCI_POWER_CONTROL_REG, 0); + MicroSecondDelay (100); } - MCI_TRACE("MciNotifyState(MmcHwInitializationState): TurnOn MCI"); + MCI_TRACE ("MciNotifyState(MmcHwInitializationState): TurnOn MCI"); // Setup clock // - 0x1D = 29 => should be the clock divider to be less than 400kHz at MCLK = 24Mhz - MmioWrite32(MCI_CLOCK_CONTROL_REG,0x1D | MCI_CLOCK_ENABLE | MCI_CLOCK_POWERSAVE); + MmioWrite32 (MCI_CLOCK_CONTROL_REG, 0x1D | MCI_CLOCK_ENABLE | MCI_CLOCK_POWERSAVE); //MmioWrite32(MCI_CLOCK_CONTROL_REG,0x1D | MCI_CLOCK_ENABLE); // Set the voltage - MmioWrite32(MCI_POWER_CONTROL_REG,MCI_POWER_OPENDRAIN | (15<<2)); - MmioWrite32(MCI_POWER_CONTROL_REG,MCI_POWER_ROD | MCI_POWER_OPENDRAIN | (15<<2) | MCI_POWER_UP); - MicroSecondDelay(10); - MmioWrite32(MCI_POWER_CONTROL_REG,MCI_POWER_ROD | MCI_POWER_OPENDRAIN | (15<<2) | MCI_POWER_ON); - MicroSecondDelay(100); + MmioWrite32 (MCI_POWER_CONTROL_REG, MCI_POWER_OPENDRAIN | (15<<2)); + MmioWrite32 (MCI_POWER_CONTROL_REG, MCI_POWER_ROD | MCI_POWER_OPENDRAIN | (15<<2) | MCI_POWER_UP); + MicroSecondDelay (10); + MmioWrite32 (MCI_POWER_CONTROL_REG, MCI_POWER_ROD | MCI_POWER_OPENDRAIN | (15<<2) | MCI_POWER_ON); + MicroSecondDelay (100); // Set Data Length & Data Timer - MmioWrite32(MCI_DATA_TIMER_REG,0xFFFFF); - MmioWrite32(MCI_DATA_LENGTH_REG,8); + MmioWrite32 (MCI_DATA_TIMER_REG, 0xFFFFF); + MmioWrite32 (MCI_DATA_LENGTH_REG, 8); - ASSERT((MmioRead32(MCI_POWER_CONTROL_REG) & 0x3) == MCI_POWER_ON); + ASSERT ((MmioRead32 (MCI_POWER_CONTROL_REG) & 0x3) == MCI_POWER_ON); break; case MmcIdleState: - MCI_TRACE("MciNotifyState(MmcIdleState)"); + MCI_TRACE ("MciNotifyState(MmcIdleState)"); break; case MmcReadyState: - MCI_TRACE("MciNotifyState(MmcReadyState)"); + MCI_TRACE ("MciNotifyState(MmcReadyState)"); break; case MmcIdentificationState: - MCI_TRACE("MciNotifyState(MmcIdentificationState)"); + MCI_TRACE ("MciNotifyState (MmcIdentificationState)"); break; case MmcStandByState:{ volatile UINT32 PwrCtrlReg; - MCI_TRACE("MciNotifyState(MmcStandByState)"); + MCI_TRACE ("MciNotifyState (MmcStandByState)"); // Enable MCICMD push-pull drive - PwrCtrlReg = MmioRead32(MCI_POWER_CONTROL_REG); + PwrCtrlReg = MmioRead32 (MCI_POWER_CONTROL_REG); //Disable Open Drain output - PwrCtrlReg &=~(MCI_POWER_OPENDRAIN); - MmioWrite32(MCI_POWER_CONTROL_REG,PwrCtrlReg); + PwrCtrlReg &= ~ (MCI_POWER_OPENDRAIN); + MmioWrite32 (MCI_POWER_CONTROL_REG, PwrCtrlReg); // Set MMCI0 clock to 4MHz (24MHz may be possible with cache enabled) // @@ -471,22 +476,22 @@ MciNotifyState ( break; } case MmcTransferState: - //MCI_TRACE("MciNotifyState(MmcTransferState)"); + //MCI_TRACE ("MciNotifyState(MmcTransferState)"); break; case MmcSendingDataState: - MCI_TRACE("MciNotifyState(MmcSendingDataState)"); + MCI_TRACE ("MciNotifyState(MmcSendingDataState)"); break; case MmcReceiveDataState: - MCI_TRACE("MciNotifyState(MmcReceiveDataState)"); + MCI_TRACE ("MciNotifyState(MmcReceiveDataState)"); break; case MmcProgrammingState: - MCI_TRACE("MciNotifyState(MmcProgrammingState)"); + MCI_TRACE ("MciNotifyState(MmcProgrammingState)"); break; case MmcDisconnectState: - MCI_TRACE("MciNotifyState(MmcDisconnectState)"); + MCI_TRACE ("MciNotifyState(MmcDisconnectState)"); break; default: - ASSERT(0); + ASSERT (0); } return EFI_SUCCESS; } @@ -501,8 +506,8 @@ MciBuildDevicePath ( { EFI_DEVICE_PATH_PROTOCOL *NewDevicePathNode; - NewDevicePathNode = CreateDeviceNode(HARDWARE_DEVICE_PATH,HW_VENDOR_DP,sizeof(VENDOR_DEVICE_PATH)); - CopyGuid(&((VENDOR_DEVICE_PATH*)NewDevicePathNode)->Guid,&mPL180MciDevicePathGuid); + NewDevicePathNode = CreateDeviceNode (HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH)); + CopyGuid (& ((VENDOR_DEVICE_PATH*)NewDevicePathNode)->Guid, &mPL180MciDevicePathGuid); *DevicePath = NewDevicePathNode; return EFI_SUCCESS; @@ -527,9 +532,11 @@ PL180MciDxeInitialize ( ) { EFI_STATUS Status; - EFI_HANDLE Handle = NULL; + EFI_HANDLE Handle; + + Handle = NULL; - MCI_TRACE("PL180MciDxeInitialize()"); + MCI_TRACE ("PL180MciDxeInitialize()"); //Publish Component Name, BlockIO protocol interfaces Status = gBS->InstallMultipleProtocolInterfaces ( diff --git a/ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.h b/ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.h index 43a92bf4d9..63c567d476 100644 --- a/ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.h +++ b/ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.h @@ -1,7 +1,7 @@ /** @file Header for the MMC Host Protocol implementation for the ARM PrimeCell PL180. - Copyright (c) 2011, ARM Limited. All rights reserved. + Copyright (c) 2011-2012, ARM Limited. All rights reserved. This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License @@ -27,76 +27,108 @@ #include #include -#define PL180_MCI_DXE_VERSION 0x10 - -#define MCI_SYSCTL FixedPcdGet32(PcdPL180MciBaseAddress) - -#define MCI_POWER_CONTROL_REG (MCI_SYSCTL+0x000) -#define MCI_CLOCK_CONTROL_REG (MCI_SYSCTL+0x004) -#define MCI_ARGUMENT_REG (MCI_SYSCTL+0x008) -#define MCI_COMMAND_REG (MCI_SYSCTL+0x00C) -#define MCI_RESPCMD_REG (MCI_SYSCTL+0x010) -#define MCI_RESPONSE3_REG (MCI_SYSCTL+0x014) -#define MCI_RESPONSE2_REG (MCI_SYSCTL+0x018) -#define MCI_RESPONSE1_REG (MCI_SYSCTL+0x01C) -#define MCI_RESPONSE0_REG (MCI_SYSCTL+0x020) -#define MCI_DATA_TIMER_REG (MCI_SYSCTL+0x024) -#define MCI_DATA_LENGTH_REG (MCI_SYSCTL+0x028) -#define MCI_DATA_CTL_REG (MCI_SYSCTL+0x02C) -#define MCI_DATA_COUNTER (MCI_SYSCTL+0x030) -#define MCI_STATUS_REG (MCI_SYSCTL+0x034) -#define MCI_CLEAR_STATUS_REG (MCI_SYSCTL+0x038) -#define MCI_INT0_MASK_REG (MCI_SYSCTL+0x03C) -#define MCI_INT1_MASK_REG (MCI_SYSCTL+0x040) -#define MCI_FIFOCOUNT_REG (MCI_SYSCTL+0x048) -#define MCI_FIFO_REG (MCI_SYSCTL+0x080) - -#define MCI_POWER_UP 0x2 -#define MCI_POWER_ON 0x3 -#define MCI_POWER_OPENDRAIN (1 << 6) -#define MCI_POWER_ROD (1 << 7) - -#define MCI_CLOCK_ENABLE 0x100 -#define MCI_CLOCK_POWERSAVE 0x200 -#define MCI_CLOCK_BYPASS 0x400 - -#define MCI_STATUS_CMD_CMDCRCFAIL 0x1 -#define MCI_STATUS_CMD_DATACRCFAIL 0x2 -#define MCI_STATUS_CMD_CMDTIMEOUT 0x4 -#define MCI_STATUS_CMD_DATATIMEOUT 0x8 -#define MCI_STATUS_CMD_TX_UNDERRUN 0x10 -#define MCI_STATUS_CMD_RXOVERRUN 0x20 -#define MCI_STATUS_CMD_RESPEND 0x40 -#define MCI_STATUS_CMD_SENT 0x80 -#define MCI_STATUS_CMD_TXDONE (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND) -#define MCI_STATUS_CMD_DATAEND 0x000100 // Command Status - Data end -#define MCI_STATUS_CMD_START_BIT_ERROR 0x000200 -#define MCI_STATUS_CMD_DATABLOCKEND 0x000400 // Command Status - Data end -#define MCI_STATUS_CMD_ACTIVE 0x800 -#define MCI_STATUS_CMD_RXACTIVE (1 << 13) -#define MCI_STATUS_CMD_RXFIFOHALFFULL 0x008000 -#define MCI_STATUS_CMD_RXFIFOEMPTY 0x080000 -#define MCI_STATUS_CMD_RXDATAAVAILBL (1 << 21) -#define MCI_STATUS_CMD_TXACTIVE (1 << 12) -#define MCI_STATUS_CMD_TXFIFOFULL (1 << 16) -#define MCI_STATUS_CMD_TXFIFOHALFEMPTY (1 << 14) -#define MCI_STATUS_CMD_TXFIFOEMPTY (1 << 18) -#define MCI_STATUS_CMD_TXDATAAVAILBL (1 << 20) - -#define MCI_DATACTL_ENABLE 1 +#define PL180_MCI_DXE_VERSION 0x10 + +#define MCI_SYSCTL FixedPcdGet32 (PcdPL180MciBaseAddress) + +#define MCI_POWER_CONTROL_REG (MCI_SYSCTL + 0x000) +#define MCI_CLOCK_CONTROL_REG (MCI_SYSCTL + 0x004) +#define MCI_ARGUMENT_REG (MCI_SYSCTL + 0x008) +#define MCI_COMMAND_REG (MCI_SYSCTL + 0x00C) +#define MCI_RESPCMD_REG (MCI_SYSCTL + 0x010) +#define MCI_RESPONSE3_REG (MCI_SYSCTL + 0x014) +#define MCI_RESPONSE2_REG (MCI_SYSCTL + 0x018) +#define MCI_RESPONSE1_REG (MCI_SYSCTL + 0x01C) +#define MCI_RESPONSE0_REG (MCI_SYSCTL + 0x020) +#define MCI_DATA_TIMER_REG (MCI_SYSCTL + 0x024) +#define MCI_DATA_LENGTH_REG (MCI_SYSCTL + 0x028) +#define MCI_DATA_CTL_REG (MCI_SYSCTL + 0x02C) +#define MCI_DATA_COUNTER (MCI_SYSCTL + 0x030) +#define MCI_STATUS_REG (MCI_SYSCTL + 0x034) +#define MCI_CLEAR_STATUS_REG (MCI_SYSCTL + 0x038) +#define MCI_INT0_MASK_REG (MCI_SYSCTL + 0x03C) +#define MCI_INT1_MASK_REG (MCI_SYSCTL + 0x040) +#define MCI_SELECT_REG (MCI_SYSCTL + 0x044) +#define MCI_FIFOCOUNT_REG (MCI_SYSCTL + 0x048) +#define MCI_FIFO_REG (MCI_SYSCTL + 0x080) + +#define MCI_POWER_OFF 0 +#define MCI_POWER_UP BIT1 +#define MCI_POWER_ON (BIT1 | BIT0) +#define MCI_POWER_OPENDRAIN BIT6 +#define MCI_POWER_ROD BIT7 + +#define MCI_CLOCK_ENABLE BIT8 +#define MCI_CLOCK_POWERSAVE BIT9 +#define MCI_CLOCK_BYPASS BIT10 +#define MCI_CLOCK_WIDEBUS BIT11 + +#define MCI_STATUS_CMD_CMDCRCFAIL BIT0 +#define MCI_STATUS_CMD_DATACRCFAIL BIT1 +#define MCI_STATUS_CMD_CMDTIMEOUT BIT2 +#define MCI_STATUS_CMD_DATATIMEOUT BIT3 +#define MCI_STATUS_CMD_TX_UNDERRUN BIT4 +#define MCI_STATUS_CMD_RXOVERRUN BIT5 +#define MCI_STATUS_CMD_RESPEND BIT6 +#define MCI_STATUS_CMD_SENT BIT7 +#define MCI_STATUS_CMD_DATAEND BIT8 +#define MCI_STATUS_CMD_START_BIT_ERROR BIT9 +#define MCI_STATUS_CMD_DATABLOCKEND BIT10 +#define MCI_STATUS_CMD_ACTIVE BIT11 +#define MCI_STATUS_CMD_TXACTIVE BIT12 +#define MCI_STATUS_CMD_RXACTIVE BIT13 +#define MCI_STATUS_CMD_TXFIFOHALFEMPTY BIT14 +#define MCI_STATUS_CMD_RXFIFOHALFFULL BIT15 +#define MCI_STATUS_CMD_TXFIFOFULL BIT16 +#define MCI_STATUS_CMD_RXFIFOFULL BIT17 +#define MCI_STATUS_CMD_TXFIFOEMPTY BIT18 +#define MCI_STATUS_CMD_RXFIFOEMPTY BIT19 +#define MCI_STATUS_CMD_TXDATAAVAILBL BIT20 +#define MCI_STATUS_CMD_RXDATAAVAILBL BIT21 + +#define MCI_STATUS_TXDONE (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND) +#define MCI_STATUS_RXDONE (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND) +#define MCI_STATUS_READ_ERROR ( MCI_STATUS_CMD_DATACRCFAIL \ + | MCI_STATUS_CMD_DATATIMEOUT \ + | MCI_STATUS_CMD_RXOVERRUN \ + | MCI_STATUS_CMD_START_BIT_ERROR ) +#define MCI_STATUS_WRITE_ERROR ( MCI_STATUS_CMD_DATACRCFAIL \ + | MCI_STATUS_CMD_DATATIMEOUT \ + | MCI_STATUS_CMD_TX_UNDERRUN ) +#define MCI_STATUS_CMD_ERROR ( MCI_STATUS_CMD_CMDCRCFAIL \ + | MCI_STATUS_CMD_CMDTIMEOUT \ + | MCI_STATUS_CMD_START_BIT_ERROR ) + +#define MCI_CLR_CMD_STATUS ( MCI_STATUS_CMD_RESPEND \ + | MCI_STATUS_CMD_SENT \ + | MCI_STATUS_CMD_ERROR ) + +#define MCI_CLR_READ_STATUS ( MCI_STATUS_RXDONE \ + | MCI_STATUS_READ_ERROR ) + +#define MCI_CLR_WRITE_STATUS ( MCI_STATUS_TXDONE \ + | MCI_STATUS_WRITE_ERROR ) + +#define MCI_CLR_ALL_STATUS (BIT11 - 1) + +#define MCI_DATACTL_DISABLE_MASK 0xFE +#define MCI_DATACTL_ENABLE BIT0 #define MCI_DATACTL_CONT_TO_CARD 0 -#define MCI_DATACTL_CARD_TO_CONT 2 +#define MCI_DATACTL_CARD_TO_CONT BIT1 #define MCI_DATACTL_BLOCK_TRANS 0 -#define MCI_DATACTL_STREAM_TRANS 4 -#define MCI_DATACTL_DMA_ENABLE (1 << 3) +#define MCI_DATACTL_STREAM_TRANS BIT2 +#define MCI_DATACTL_DMA_DISABLED 0 +#define MCI_DATACTL_DMA_ENABLE BIT3 #define INDX_MASK 0x3F -#define MCI_CPSM_ENABLED (1 << 10) -#define MCI_CPSM_WAIT_RESPONSE (1 << 6) -#define MCI_CPSM_LONG_RESPONSE (1 << 7) +#define MCI_CPSM_WAIT_RESPONSE BIT6 +#define MCI_CPSM_LONG_RESPONSE BIT7 +#define MCI_CPSM_LONG_INTERRUPT BIT8 +#define MCI_CPSM_LONG_PENDING BIT9 +#define MCI_CPSM_ENABLE BIT10 -#define MCI_TRACE(txt) DEBUG((EFI_D_BLKIO, "ARM_MCI: " txt "\n")) +#define MCI_TRACE(txt) DEBUG ((EFI_D_BLKIO, "ARM_MCI: " txt "\n")) EFI_STATUS EFIAPI -- cgit v1.2.3