From 1ad14bc86b56eb0134b1c9e504a7392e32c44ddb Mon Sep 17 00:00:00 2001 From: oliviermartin Date: Sat, 11 Jun 2011 12:06:59 +0000 Subject: ArmPlatformPkg: Unify the Secure and Normal FD and FV PCD naming With this change, we now have these following PCDs values to define the location of the Secure and Normal firmwares: - gArmTokenSpaceGuid.PcdSecureFd(BaseAddress|Size) - gArmTokenSpaceGuid.PcdSecureFv(BaseAddress|Size) - gArmTokenSpaceGuid.PcdNormalFd(BaseAddress|Size) - gArmTokenSpaceGuid.PcdNormalFv(BaseAddress|Size) git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11806 6f19259b-4bc3-4df7-8a09-765794883524 --- ArmPlatformPkg/Sec/Sec.c | 14 +++++++------- ArmPlatformPkg/Sec/Sec.inf | 2 +- 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'ArmPlatformPkg/Sec') diff --git a/ArmPlatformPkg/Sec/Sec.c b/ArmPlatformPkg/Sec/Sec.c index b8e5225520..64cf0f0d7e 100644 --- a/ArmPlatformPkg/Sec/Sec.c +++ b/ArmPlatformPkg/Sec/Sec.c @@ -121,18 +121,18 @@ CEntryPoint ( // If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM if (FeaturePcdGet(PcdSkipPeiCore) || !FeaturePcdGet(PcdStandalone)) { // Initialize system memory (DRAM) - ArmPlatformInitializeSystemMemory(); + ArmPlatformInitializeSystemMemory (); } // Some platform can change their physical memory mapping - ArmPlatformBootRemapping(); + ArmPlatformBootRemapping (); } // Test if Trustzone is supported on this platform if (ArmPlatformTrustzoneSupported()) { if (FixedPcdGet32(PcdMPCoreSupport)) { // Setup SMP in Non Secure world - ArmSetupSmpNonSecure(CoreId); + ArmSetupSmpNonSecure (CoreId); } // Enter Monitor Mode @@ -206,7 +206,7 @@ CEntryPoint ( // If ArmVe has not been built as Standalone then we need to patch the DRAM to add an infinite loop at the start address if (FeaturePcdGet(PcdStandalone) == FALSE) { if (CoreId == ARM_PRIMARY_CORE) { - UINTN* StartAddress = (UINTN*)PcdGet32(PcdNormalFdBaseAddress); + UINTN* StartAddress = (UINTN*)PcdGet32(PcdNormalFvBaseAddress); // Patch the DRAM to make an infinite loop at the start address *StartAddress = 0xEAFFFFFE; // opcode for while(1) @@ -215,7 +215,7 @@ CEntryPoint ( SerialPortWrite ((UINT8 *) Buffer, CharCount); // To enter into Non Secure state, we need to make a return from exception - return_from_exception(PcdGet32(PcdNormalFdBaseAddress)); + return_from_exception(PcdGet32(PcdNormalFvBaseAddress)); } else { // When the primary core is stopped by the hardware debugger to copy the firmware // into DRAM. The secondary cores are still running. As soon as the first bytes of @@ -229,7 +229,7 @@ CEntryPoint ( } } else { // To enter into Non Secure state, we need to make a return from exception - return_from_exception(PcdGet32(PcdNormalFdBaseAddress)); + return_from_exception(PcdGet32(PcdNormalFvBaseAddress)); } //-------------------- Non Secure Mode --------------------- @@ -247,7 +247,7 @@ NonSecureWaitForFirmware ( VOID (*secondary_start)(VOID); // The secondary cores will execute the firmware once wake from WFI. - secondary_start = (VOID (*)())PcdGet32(PcdNormalFdBaseAddress); + secondary_start = (VOID (*)())PcdGet32(PcdNormalFvBaseAddress); ArmCallWFI(); diff --git a/ArmPlatformPkg/Sec/Sec.inf b/ArmPlatformPkg/Sec/Sec.inf index 38bd8b9be3..d36fc0c777 100644 --- a/ArmPlatformPkg/Sec/Sec.inf +++ b/ArmPlatformPkg/Sec/Sec.inf @@ -52,7 +52,7 @@ gArmTokenSpaceGuid.PcdVFPEnabled gArmPlatformTokenSpaceGuid.PcdMPCoreSupport - gArmTokenSpaceGuid.PcdNormalFdBaseAddress + gArmTokenSpaceGuid.PcdNormalFvBaseAddress gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize -- cgit v1.2.3