From 73ca50096eea3edc64e2c635b6b6d99fbb5572d5 Mon Sep 17 00:00:00 2001 From: Brendan Jackman Date: Thu, 8 May 2014 14:59:04 +0000 Subject: ARM Packages: Use AND instead of BIC instruction with immediate AARCH64 does not have a BIC-with-immediate instruction. GAS assembles it as a AND with the immediate inverted, but Clang's integrated assembler emits an error. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman Reviewed-by: Olivier Martin git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15509 6f19259b-4bc3-4df7-8a09-765794883524 --- ArmPlatformPkg/Sec/AArch64/Helper.S | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'ArmPlatformPkg/Sec') diff --git a/ArmPlatformPkg/Sec/AArch64/Helper.S b/ArmPlatformPkg/Sec/AArch64/Helper.S index 259aca4856..3b58e12292 100644 --- a/ArmPlatformPkg/Sec/AArch64/Helper.S +++ b/ArmPlatformPkg/Sec/AArch64/Helper.S @@ -1,5 +1,5 @@ #======================================================================================== -# Copyright (c) 2011-2013, ARM Limited. All rights reserved. +# Copyright (c) 2011-2014, ARM Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -31,9 +31,7 @@ ASM_PFX(SwitchToNSExceptionLevel1): orr x0, x0, #(1 << 31) // Set EL1 to be 64bit // Send all interrupts to their respective Exception levels for EL2 - bic x0, x0, #(1 << 3) // Disable virtual FIQ - bic x0, x0, #(1 << 4) // Disable virtual IRQ - bic x0, x0, #(1 << 5) // Disable virtual SError and Abort + and x0, x0, #~(ARM_HCR_FMO | ARM_HCR_IMO | ARM_HCR_AMO) // Disable virtual FIQ, IRQ, SError and Abort msr hcr_el2, x0 // Write back our settings msr cptr_el2, xzr // Disable copro traps to EL2 -- cgit v1.2.3