From 710b8acb569a0dc86e509d8cb6341504eeb0bbbf Mon Sep 17 00:00:00 2001 From: oliviermartin Date: Tue, 1 Nov 2011 23:45:41 +0000 Subject: ArmPlatform/Sec: Ensure all the CPU cores are calling ArmCpuSetup() Only the primary core was calling this function. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12646 6f19259b-4bc3-4df7-8a09-765794883524 --- ArmPlatformPkg/Sec/Sec.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) (limited to 'ArmPlatformPkg') diff --git a/ArmPlatformPkg/Sec/Sec.c b/ArmPlatformPkg/Sec/Sec.c index d9831a5c44..f6b89648f9 100644 --- a/ArmPlatformPkg/Sec/Sec.c +++ b/ArmPlatformPkg/Sec/Sec.c @@ -35,10 +35,20 @@ CEntryPoint ( UINTN CharCount; UINTN JumpAddress; + // Invalidate the data cache. Doesn't have to do the Data cache clean. + ArmInvalidateDataCache(); + + // Invalidate Instruction Cache + ArmInvalidateInstructionCache(); + + // Invalidate I & D TLBs + ArmInvalidateInstructionAndDataTlb(); + + // CPU specific settings + ArmCpuSetup (MpId); + // Primary CPU clears out the SCU tag RAMs, secondaries wait if (IS_PRIMARY_CORE(MpId)) { - ArmCpuSetup (MpId); - if (ArmIsMpCore()) { ArmCpuSynchronizeSignal (ARM_CPU_EVENT_BOOT_MEM_INIT); } @@ -69,15 +79,6 @@ CEntryPoint ( ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase)); } - // Invalidate the data cache. Doesn't have to do the Data cache clean. - ArmInvalidateDataCache(); - - // Invalidate Instruction Cache - ArmInvalidateInstructionCache(); - - // Invalidate I & D TLBs - ArmInvalidateInstructionAndDataTlb(); - // Enable Full Access to CoProcessors ArmWriteCPACR (CPACR_CP_FULL_ACCESS); -- cgit v1.2.3