From f659880bfa42ded20a00d3e371c998b42dcdd0fd Mon Sep 17 00:00:00 2001 From: AJFISH Date: Thu, 14 Jan 2010 03:25:08 +0000 Subject: Added support for L2 (4K) page tables and made the CPU driver change cachability attributes on request. Also got the DebugUncache infrastructure working for the first time. Looks like it works for the simple case. Checking in so we can get more eyes looking at the code. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9734 6f19259b-4bc3-4df7-8a09-765794883524 --- BeagleBoardPkg/Sec/Cache.c | 30 ++++++++++++------------------ 1 file changed, 12 insertions(+), 18 deletions(-) (limited to 'BeagleBoardPkg/Sec/Cache.c') diff --git a/BeagleBoardPkg/Sec/Cache.c b/BeagleBoardPkg/Sec/Cache.c index facc5deae4..d7c906244c 100755 --- a/BeagleBoardPkg/Sec/Cache.c +++ b/BeagleBoardPkg/Sec/Cache.c @@ -58,29 +58,23 @@ InitCache ( MemoryTable[0].Length = MemoryLength; MemoryTable[0].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes; - // Uncached DDR Mirror - MemoryTable[1].PhysicalBase = MemoryBase; - MemoryTable[1].VirtualBase = MemoryBase | UncachedMemoryMask; - MemoryTable[1].Length = MemoryLength; - MemoryTable[1].Attributes = DDR_ATTRIBUTES_UNCACHED; - // SOC Registers. L3 interconnects - MemoryTable[2].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE; - MemoryTable[2].VirtualBase = SOC_REGISTERS_L3_PHYSICAL_BASE; - MemoryTable[2].Length = SOC_REGISTERS_L3_PHYSICAL_LENGTH; - MemoryTable[2].Attributes = SOC_REGISTERS_L3_ATTRIBUTES; + MemoryTable[1].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE; + MemoryTable[1].VirtualBase = SOC_REGISTERS_L3_PHYSICAL_BASE; + MemoryTable[1].Length = SOC_REGISTERS_L3_PHYSICAL_LENGTH; + MemoryTable[1].Attributes = SOC_REGISTERS_L3_ATTRIBUTES; // SOC Registers. L4 interconnects - MemoryTable[3].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE; - MemoryTable[3].VirtualBase = SOC_REGISTERS_L4_PHYSICAL_BASE; - MemoryTable[3].Length = SOC_REGISTERS_L4_PHYSICAL_LENGTH; - MemoryTable[3].Attributes = SOC_REGISTERS_L4_ATTRIBUTES; + MemoryTable[2].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE; + MemoryTable[2].VirtualBase = SOC_REGISTERS_L4_PHYSICAL_BASE; + MemoryTable[2].Length = SOC_REGISTERS_L4_PHYSICAL_LENGTH; + MemoryTable[2].Attributes = SOC_REGISTERS_L4_ATTRIBUTES; // End of Table - MemoryTable[4].PhysicalBase = 0; - MemoryTable[4].VirtualBase = 0; - MemoryTable[4].Length = 0; - MemoryTable[4].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; + MemoryTable[3].PhysicalBase = 0; + MemoryTable[3].VirtualBase = 0; + MemoryTable[3].Length = 0; + MemoryTable[3].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize); -- cgit v1.2.3