From 480c39cdc0478e2e13f546aa8995a2bb59dcdc05 Mon Sep 17 00:00:00 2001 From: Guo Mang Date: Wed, 3 Aug 2016 09:47:12 +0800 Subject: BraswellPlatformPkg: Move AdvancedFeature to Common/Feature Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang Reviewed-by: David Wei --- .../Application/FirmwareUpdate/FirmwareUpdate.c | 932 ++++++++++++ .../Application/FirmwareUpdate/FirmwareUpdate.h | 190 +++ .../Application/FirmwareUpdate/FirmwareUpdate.inf | 75 + .../FirmwareUpdate/FirmwareUpdateStrings.uni | 52 + BraswellPlatformPkg/Common/Feature/Logo/Logo.bmp | Bin 0 -> 94434 bytes .../Common/Feature/PciPlatform/PciPlatform.c | 303 ++++ .../Common/Feature/PciPlatform/PciPlatform.h | 80 ++ .../Common/Feature/PciPlatform/PciPlatform.inf | 58 + .../Common/Feature/SmBiosMiscDxe/CommonHeader.h | 41 + .../SmBiosMiscDxe/MiscBaseBoardManufacturer.uni | 30 + .../SmBiosMiscDxe/MiscBaseBoardManufacturerData.c | 52 + .../MiscBaseBoardManufacturerFunction.c | 313 ++++ .../Feature/SmBiosMiscDxe/MiscBiosVendor.uni | 23 + .../Feature/SmBiosMiscDxe/MiscBiosVendorData.c | 95 ++ .../Feature/SmBiosMiscDxe/MiscBiosVendorFunction.c | 245 ++++ .../SmBiosMiscDxe/MiscBootInformationData.c | 37 + .../SmBiosMiscDxe/MiscBootInformationFunction.c | 69 + .../SmBiosMiscDxe/MiscChassisManufacturer.uni | 25 + .../SmBiosMiscDxe/MiscChassisManufacturerData.c | 50 + .../MiscChassisManufacturerFunction.c | 211 +++ .../Feature/SmBiosMiscDxe/MiscMemoryDevice.uni | 32 + .../Feature/SmBiosMiscDxe/MiscMemoryDeviceData.c | 38 + .../SmBiosMiscDxe/MiscMemoryDeviceFunction.c | 308 ++++ .../MiscNumberOfInstallableLanguagesData.c | 49 + .../MiscNumberOfInstallableLanguagesFunction.c | 91 ++ .../Common/Feature/SmBiosMiscDxe/MiscOemString.uni | 22 + .../Feature/SmBiosMiscDxe/MiscOemStringData.c | 28 + .../Feature/SmBiosMiscDxe/MiscOemStringFunction.c | 84 ++ .../Feature/SmBiosMiscDxe/MiscOemType0x90.uni | 28 + .../Feature/SmBiosMiscDxe/MiscOemType0x90Data.c | 32 + .../SmBiosMiscDxe/MiscOemType0x90Function.c | 436 ++++++ .../Feature/SmBiosMiscDxe/MiscOemType0x94.uni | 39 + .../Feature/SmBiosMiscDxe/MiscOemType0x94Data.c | 47 + .../SmBiosMiscDxe/MiscOemType0x94Function.c | 1036 ++++++++++++++ .../Feature/SmBiosMiscDxe/MiscOnboardDevice.uni | 23 + .../Feature/SmBiosMiscDxe/MiscOnboardDeviceData.c | 57 + .../SmBiosMiscDxe/MiscOnboardDeviceFunction.c | 206 +++ .../Feature/SmBiosMiscDxe/MiscPhysicalArray.uni | 22 + .../Feature/SmBiosMiscDxe/MiscPhysicalArrayData.c | 29 + .../SmBiosMiscDxe/MiscPhysicalArrayFunction.c | 93 ++ .../MiscPortInternalConnectorDesignator.uni | 28 + .../MiscPortInternalConnectorDesignatorData.c | 568 ++++++++ .../MiscPortInternalConnectorDesignatorFunction.c | 261 ++++ .../Feature/SmBiosMiscDxe/MiscProcessorCache.uni | 19 + .../Feature/SmBiosMiscDxe/MiscProcessorCacheData.c | 24 + .../SmBiosMiscDxe/MiscProcessorCacheFunction.c | 43 + .../SmBiosMiscDxe/MiscProcessorInformation.uni | 24 + .../SmBiosMiscDxe/MiscProcessorInformationData.c | 25 + .../MiscProcessorInformationFunction.c | 130 ++ .../SmBiosMiscDxe/MiscResetCapabilitiesData.c | 36 + .../SmBiosMiscDxe/MiscResetCapabilitiesFunction.c | 79 ++ .../Feature/SmBiosMiscDxe/MiscSubclassDriver.h | 216 +++ .../Feature/SmBiosMiscDxe/MiscSubclassDriver.uni | 32 + .../SmBiosMiscDxe/MiscSubclassDriverDataTable.c | 124 ++ .../SmBiosMiscDxe/MiscSubclassDriverEntryPoint.c | 239 ++++ .../SmBiosMiscDxe/MiscSystemLanguageString.uni | 20 + .../SmBiosMiscDxe/MiscSystemLanguageStringData.c | 27 + .../MiscSystemLanguageStringFunction.c | 88 ++ .../SmBiosMiscDxe/MiscSystemManufacturer.uni | 27 + .../SmBiosMiscDxe/MiscSystemManufacturerData.c | 36 + .../SmBiosMiscDxe/MiscSystemManufacturerFunction.c | 341 +++++ .../SmBiosMiscDxe/MiscSystemOptionString.uni | 21 + .../SmBiosMiscDxe/MiscSystemOptionStringData.c | 24 + .../SmBiosMiscDxe/MiscSystemOptionStringFunction.c | 86 ++ .../SmBiosMiscDxe/MiscSystemSlotDesignation.uni | 31 + .../SmBiosMiscDxe/MiscSystemSlotDesignationData.c | 154 ++ .../MiscSystemSlotDesignationFunction.c | 108 ++ .../Common/Feature/SmBiosMiscDxe/SmBiosCpu/Cache.h | 328 +++++ .../Common/Feature/SmBiosMiscDxe/SmBiosCpu/Cpu.h | 289 ++++ .../Feature/SmBiosMiscDxe/SmBiosCpu/CpuConfigLib.h | 685 +++++++++ .../Feature/SmBiosMiscDxe/SmBiosCpu/Processor.h | 60 + .../Feature/SmBiosMiscDxe/SmBiosCpu/SmBiosCpu.c | 1491 ++++++++++++++++++++ .../SmBiosMiscDxe/SmBiosCpu/SocketLga1156Lib.h | 192 +++ .../Feature/SmBiosMiscDxe/SmBiosCpu/Strings.uni | 27 + .../Common/Feature/SmBiosMiscDxe/SmbiosMiscDxe.inf | 172 +++ .../Feature/SmBiosMiscDxe/SmbiosMiscStrings.h | 410 ++++++ 76 files changed, 12046 insertions(+) create mode 100644 BraswellPlatformPkg/Common/Feature/Application/FirmwareUpdate/FirmwareUpdate.c create mode 100644 BraswellPlatformPkg/Common/Feature/Application/FirmwareUpdate/FirmwareUpdate.h create mode 100644 BraswellPlatformPkg/Common/Feature/Application/FirmwareUpdate/FirmwareUpdate.inf create mode 100644 BraswellPlatformPkg/Common/Feature/Application/FirmwareUpdate/FirmwareUpdateStrings.uni create mode 100644 BraswellPlatformPkg/Common/Feature/Logo/Logo.bmp create mode 100644 BraswellPlatformPkg/Common/Feature/PciPlatform/PciPlatform.c create mode 100644 BraswellPlatformPkg/Common/Feature/PciPlatform/PciPlatform.h create mode 100644 BraswellPlatformPkg/Common/Feature/PciPlatform/PciPlatform.inf create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/CommonHeader.h create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBaseBoardManufacturer.uni create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBaseBoardManufacturerData.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBaseBoardManufacturerFunction.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBiosVendor.uni create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBiosVendorData.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBiosVendorFunction.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBootInformationData.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBootInformationFunction.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscChassisManufacturer.uni create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscChassisManufacturerData.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscChassisManufacturerFunction.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscMemoryDevice.uni create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscMemoryDeviceData.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscMemoryDeviceFunction.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscNumberOfInstallableLanguagesData.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscNumberOfInstallableLanguagesFunction.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemString.uni create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemStringData.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemStringFunction.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemType0x90.uni create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemType0x90Data.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemType0x90Function.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemType0x94.uni create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemType0x94Data.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemType0x94Function.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOnboardDevice.uni create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOnboardDeviceData.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOnboardDeviceFunction.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscPhysicalArray.uni create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscPhysicalArrayData.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscPhysicalArrayFunction.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscPortInternalConnectorDesignator.uni create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscPortInternalConnectorDesignatorData.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscPortInternalConnectorDesignatorFunction.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscProcessorCache.uni create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscProcessorCacheData.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscProcessorCacheFunction.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscProcessorInformation.uni create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscProcessorInformationData.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscProcessorInformationFunction.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscResetCapabilitiesData.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscResetCapabilitiesFunction.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSubclassDriver.h create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSubclassDriver.uni create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSubclassDriverDataTable.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSubclassDriverEntryPoint.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemLanguageString.uni create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemLanguageStringData.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemLanguageStringFunction.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemManufacturer.uni create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemManufacturerData.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemManufacturerFunction.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemOptionString.uni create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemOptionStringData.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemOptionStringFunction.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemSlotDesignation.uni create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemSlotDesignationData.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemSlotDesignationFunction.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmBiosCpu/Cache.h create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmBiosCpu/Cpu.h create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmBiosCpu/CpuConfigLib.h create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmBiosCpu/Processor.h create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmBiosCpu/SmBiosCpu.c create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmBiosCpu/SocketLga1156Lib.h create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmBiosCpu/Strings.uni create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmbiosMiscDxe.inf create mode 100644 BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmbiosMiscStrings.h (limited to 'BraswellPlatformPkg/Common') diff --git a/BraswellPlatformPkg/Common/Feature/Application/FirmwareUpdate/FirmwareUpdate.c b/BraswellPlatformPkg/Common/Feature/Application/FirmwareUpdate/FirmwareUpdate.c new file mode 100644 index 0000000000..34b36fe812 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/Application/FirmwareUpdate/FirmwareUpdate.c @@ -0,0 +1,932 @@ +/** @file + Firmware Update driver. + + Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "FirmwareUpdate.h" + +EFI_HII_HANDLE HiiHandle; + +// +// Braswell Platform Flash Layout +// +//Start (hex) End (hex) Length (hex) Area Name +//----------- --------- ------------ --------- +//00000000 007FFFFF 00800000 Flash Image +// +//00000000 00000FFF 00001000 Descriptor Region +//00001000 004FFFFF 004FF000 TXE Region +//00500000 007FFFFF 00300000 BIOS Region +// +FV_REGION_INFO *mRegionInfo; + +UINTN mRegionInfoCount; + +FV_INPUT_DATA mInputData = {0}; + +EFI_SPI_PROTOCOL *mSpiProtocol; + +EFI_STATUS +GetRegionIndex ( + IN EFI_PHYSICAL_ADDRESS Address, + OUT UINTN *RegionIndex + ) +{ + UINTN Index; + + for (Index = 0; Index < mRegionInfoCount; Index++) { + if (Address >= mRegionInfo[Index].Base && + Address < (mRegionInfo[Index].Base + mRegionInfo[Index].Size) + ) { + break; + } + } + + *RegionIndex = Index; + if (Index >= mRegionInfoCount) { + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} + +BOOLEAN +UpdateBlock ( + IN EFI_PHYSICAL_ADDRESS Address + ) +{ + EFI_STATUS Status; + UINTN Index; + + if (mInputData.FullFlashUpdate) { + return TRUE; + } + + Status = GetRegionIndex (Address, &Index); + if ((!EFI_ERROR(Status)) && mRegionInfo[Index].Update) { + return TRUE; + } + + return FALSE; +} + +EFI_STATUS +MarkRegionState ( + IN EFI_PHYSICAL_ADDRESS Address, + IN BOOLEAN Update + ) +{ + EFI_STATUS Status; + UINTN Index; + + Status = GetRegionIndex (Address, &Index); + if (!EFI_ERROR(Status)) { + mRegionInfo[Index].Update = Update; + } + + return Status; +} + +UINTN +InternalPrintToken ( + IN CONST CHAR16 *Format, + IN EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *Console, + IN VA_LIST Marker + ) +{ + EFI_STATUS Status; + UINTN Return; + CHAR16 *Buffer; + UINTN BufferSize; + + ASSERT (Format != NULL); + ASSERT (((UINTN) Format & BIT0) == 0); + ASSERT (Console != NULL); + + BufferSize = (PcdGet32 (PcdUefiLibMaxPrintBufferSize) + 1) * sizeof (CHAR16); + + Buffer = (CHAR16 *) AllocatePool(BufferSize); + ASSERT (Buffer != NULL); + + Return = UnicodeVSPrint (Buffer, BufferSize, Format, Marker); + + if (Console != NULL && Return > 0) { + // + // To be extra safe make sure Console has been initialized. + // + Status = Console->OutputString (Console, Buffer); + if (EFI_ERROR (Status)) { + Return = 0; + } + } + + FreePool (Buffer); + + return Return; +} + +UINTN +EFIAPI +PrintToken ( + IN UINT16 Token, + IN EFI_HII_HANDLE Handle, + ... + ) +{ + VA_LIST Marker; + UINTN Return; + CHAR16 *Format; + + VA_START (Marker, Handle); + + Format = HiiGetString (Handle, Token, NULL); + ASSERT (Format != NULL); + + Return = InternalPrintToken (Format, gST->ConOut, Marker); + + FreePool (Format); + + VA_END (Marker); + + return Return; +} + +EFI_STATUS +ParseCommandLine ( + IN UINTN Argc, + IN CHAR16 **Argv + ) +{ + EFI_STATUS Status; + UINTN Index; + + // + // Check to make sure that the command line has enough arguments for minimal + // operation. The minimum is just the file name. + // + if (Argc < 2 || Argc > 4) { + return EFI_INVALID_PARAMETER; + } + + // + // Loop through command line arguments. + // + for (Index = 1; Index < Argc; Index++) { + // + // Make sure the string is valid. + // + if (StrLen (Argv[Index]) == 0) {; + PrintToken (STRING_TOKEN (STR_FWUPDATE_ZEROLENGTH_ARG), HiiHandle); + return EFI_INVALID_PARAMETER; + } + + // + // Check to see if this is an option or the file name. + // + if ((Argv[Index])[0] == L'-' || (Argv[Index])[0] == L'/') { + // + // Parse the arguments. + // + if ((StrCmp (Argv[Index], L"-h") == 0) || + (StrCmp (Argv[Index], L"--help") == 0) || + (StrCmp (Argv[Index], L"/?") == 0) || + (StrCmp (Argv[Index], L"/h") == 0)) { + // + // Print Help Information. + // + return EFI_INVALID_PARAMETER; + } else if (StrCmp (Argv[Index], L"-m") == 0) { + // + // Parse the MAC address here. + // + Status = ConvertMac(Argv[Index+1]); + if (EFI_ERROR(Status)) { + PrintToken (STRING_TOKEN (STR_FWUPDATE_INVAILD_MAC), HiiHandle); + return Status; + } + + // + // Save the MAC address to mInputData.MacValue. + // + mInputData.UpdateMac= TRUE; + Index++; + } else { + // + // Invalid option was provided. + // + return EFI_INVALID_PARAMETER; + } + } + if ((Index == Argc - 1) && (StrCmp (Argv[Index - 1], L"-m") != 0)) { + // + // The only parameter that is not an option is the firmware image. Check + // to make sure that the file exists. + // + Status = ShellIsFile (Argv[Index]); + if (EFI_ERROR (Status)) { + PrintToken (STRING_TOKEN (STR_FWUPDATE_FILE_NOT_FOUND_ERROR), HiiHandle, Argv[Index]); + return EFI_INVALID_PARAMETER; + } + if (StrLen (Argv[Index]) > INPUT_STRING_LEN) { + PrintToken (STRING_TOKEN (STR_FWUPDATE_PATH_ERROR), HiiHandle, Argv[Index]); + return EFI_INVALID_PARAMETER; + } + StrCpy (mInputData.FileName, Argv[Index]); + mInputData.UpdateFromFile = TRUE; + } + } + + return EFI_SUCCESS; +} + +STATIC +VOID +IntiFvRegion ( + VOID + ) +{ + mRegionInfoCount = 3; + + mRegionInfo = (FV_REGION_INFO *) AllocatePool (mRegionInfoCount * sizeof (FV_REGION_INFO)); + + // + // The mRegionInfo[XXX].Update is FALSE, its region will not be updated by default. It can be updated + // by -f parameter when running firmwareupdate. + // If the region is not listed in the table, it will be updated by default. + // + mRegionInfo[0].Base = PcdGet32 (PcdFlashDescriptorBase); + mRegionInfo[0].Size = PcdGet32 (PcdFlashDescriptorSize); + mRegionInfo[0].Update = TRUE; + + mRegionInfo[1].Base = PcdGet32 (PcdTxeRomBase); + mRegionInfo[1].Size = PcdGet32 (PcdTxeRomSize); + mRegionInfo[1].Update = TRUE; + + mRegionInfo[2].Base = PcdGet32 (PcdBiosRomBase); + mRegionInfo[2].Size = PcdGet32 (PcdBiosRomSize); + mRegionInfo[2].Update = TRUE; +} + +INTN +EFIAPI +ShellAppMain ( + IN UINTN Argc, + IN CHAR16 **Argv + ) +{ + EFI_STATUS Status; + UINTN Index; + UINT32 FileSize; + UINT32 BufferSize; + UINT8 *FileBuffer; + UINT8 *Buffer; + EFI_PHYSICAL_ADDRESS Address; + UINTN CountOfBlocks; + EFI_TPL OldTpl; + BOOLEAN ResetRequired; + BOOLEAN FlashError; + + Index = 0; + FileSize = 0; + BufferSize = 0; + FileBuffer = NULL; + Buffer = NULL; + Address = 0; + CountOfBlocks = 0; + ResetRequired = FALSE; + FlashError = FALSE; + + Status = EFI_SUCCESS; + + mInputData.FullFlashUpdate = TRUE; + + // + // Publish our HII data. + // + HiiHandle = HiiAddPackages ( + &gEfiCallerIdGuid, + NULL, + FirmwareUpdateStrings, + NULL + ); + if (HiiHandle == NULL) { + Status = EFI_OUT_OF_RESOURCES; + goto Done; + } + + // + // Locate the SPI protocol. + // + Status = gBS->LocateProtocol ( + &gEfiSpiProtocolGuid, + NULL, + (VOID **)&mSpiProtocol + ); + if (EFI_ERROR (Status)) { + PrintToken (STRING_TOKEN (STR_SPI_NOT_FOUND), HiiHandle); + return EFI_DEVICE_ERROR; + } + + // + // Parse the command line. + // + Status = ParseCommandLine (Argc, Argv); + if (EFI_ERROR (Status)) { + PrintHelpInfo (); + Status = EFI_SUCCESS; + goto Done; + } + + IntiFvRegion (); + + // + // Display sign-on information. + // + PrintToken (STRING_TOKEN (STR_FWUPDATE_FIRMWARE_VOL_UPDATE), HiiHandle); + PrintToken (STRING_TOKEN (STR_FWUPDATE_VERSION), HiiHandle); + PrintToken (STRING_TOKEN (STR_FWUPDATE_COPYRIGHT), HiiHandle); + + // + // Test to see if the firmware needs to be updated. + // + if (mInputData.UpdateFromFile) { + // + // Get the file to use in the update. + // + PrintToken (STRING_TOKEN (STR_FWUPDATE_READ_FILE), HiiHandle, mInputData.FileName); + Status = ReadFileData (mInputData.FileName, &FileBuffer, &FileSize); + if (EFI_ERROR (Status)) { + PrintToken (STRING_TOKEN (STR_FWUPDATE_READ_FILE_ERROR), HiiHandle, mInputData.FileName); + goto Done; + } + + // + // Check that the file and flash sizes match. + // + if (FileSize != PcdGet32 (PcdFlashChipSize)) { + PrintToken (STRING_TOKEN (STR_FWUPDATE_SIZE), HiiHandle); + Status = EFI_UNSUPPORTED; + goto Done; + } + + // + // Display flash update information. + // + PrintToken (STRING_TOKEN (STR_FWUPDATE_UPDATING_FIRMWARE), HiiHandle); + + // + // Update it. + // + Buffer = FileBuffer; + BufferSize = FileSize; + Address = PcdGet32 (PcdFlashChipBase); + CountOfBlocks = (UINTN) (BufferSize / BLOCK_SIZE); + + // + // Raise TPL to TPL_NOTIFY to block any event handler, + // while still allowing RaiseTPL(TPL_NOTIFY) within + // output driver during Print(). + // + OldTpl = gBS->RaiseTPL (TPL_NOTIFY); + for (Index = 0; Index < CountOfBlocks; Index++) { + // + // Handle block based on address and contents. + // + if (!UpdateBlock (Address)) { + DEBUG((EFI_D_INFO, "Skipping block at 0x%lx\n", Address)); + } else if (!EFI_ERROR (InternalCompareBlock (Address, Buffer))) { + DEBUG((EFI_D_INFO, "Skipping block at 0x%lx (already programmed)\n", Address)); + } else { + // + // Display a dot for each block being updated. + // + Print (L"."); + + // + // Flag that the flash image will be changed and the system must be rebooted + // to use the change. + // + ResetRequired = TRUE; + + // + // Make updating process uninterruptable, + // so that the flash memory area is not accessed by other entities + // which may interfere with the updating process. + // + Status = InternalEraseBlock (Address); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR (Status)) { + gBS->RestoreTPL (OldTpl); + FlashError = TRUE; + goto Done; + } + Status = InternalWriteBlock ( + Address, + Buffer, + (BufferSize > BLOCK_SIZE ? BLOCK_SIZE : BufferSize) + ); + if (EFI_ERROR (Status)) { + gBS->RestoreTPL (OldTpl); + FlashError = TRUE; + goto Done; + } + } + + // + // Move to next block to update. + // + Address += BLOCK_SIZE; + Buffer += BLOCK_SIZE; + if (BufferSize > BLOCK_SIZE) { + BufferSize -= BLOCK_SIZE; + } else { + BufferSize = 0; + } + } + gBS->RestoreTPL (OldTpl); + + // + // Print result of update. + // + if (!FlashError) { + if (ResetRequired) { + Print (L"\n"); + PrintToken (STRING_TOKEN (STR_FWUPDATE_UPDATE_SUCCESS), HiiHandle); + } else { + PrintToken (STRING_TOKEN (STR_FWUPDATE_NO_RESET), HiiHandle); + } + } else { + goto Done; + } + } + + // + // All flash updates are done so see if the system needs to be reset. + // + if (ResetRequired && !FlashError) { + // + // Update successful. + // + for (Index = 5; Index > 0; Index--) { + PrintToken (STRING_TOKEN (STR_FWUPDATE_SHUTDOWN), HiiHandle, Index); + gBS->Stall (1000000); + } + + gRT->ResetSystem (EfiResetShutdown, EFI_SUCCESS, 0, NULL); + PrintToken (STRING_TOKEN (STR_FWUPDATE_MANUAL_RESET), HiiHandle); + CpuDeadLoop (); + } + +Done: + // + // Print flash update failure message if error detected. + // + if (FlashError) { + PrintToken (STRING_TOKEN (STR_FWUPDATE_UPDATE_FAILED), HiiHandle, Index); + } + + // + // Do cleanup. + // + if (HiiHandle != NULL) { + HiiRemovePackages (HiiHandle); + } + if (FileBuffer) { + gBS->FreePool (FileBuffer); + } + + return Status; +} + +/** + Erase the whole block. + + @param[in] BaseAddress Base address of the block to be erased. + + @retval EFI_SUCCESS The command completed successfully. + @retval Other Device error or wirte-locked, operation failed. + +**/ +STATIC +EFI_STATUS +InternalEraseBlock ( + IN EFI_PHYSICAL_ADDRESS BaseAddress + ) +{ + EFI_STATUS Status; + UINTN NumBytes; + + NumBytes = BLOCK_SIZE; + + Status = SpiFlashBlockErase ((UINTN) BaseAddress, &NumBytes); + + return Status; +} + +#if 0 +STATIC +EFI_STATUS +InternalReadBlock ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + OUT VOID *ReadBuffer + ) +{ + EFI_STATUS Status; + UINT32 BlockSize; + + BlockSize = BLOCK_SIZE; + + Status = SpiFlashRead ((UINTN) BaseAddress, &BlockSize, ReadBuffer); + + return Status; +} +#endif + +STATIC +EFI_STATUS +InternalCompareBlock ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT8 *Buffer + ) +{ + EFI_STATUS Status; + VOID *CompareBuffer; + UINT32 NumBytes; + INTN CompareResult; + + NumBytes = BLOCK_SIZE; + CompareBuffer = AllocatePool (NumBytes); + if (CompareBuffer == NULL) { + Status = EFI_OUT_OF_RESOURCES; + goto Done; + } + + Status = SpiFlashRead ((UINTN) BaseAddress, &NumBytes, CompareBuffer); + if (EFI_ERROR (Status)) { + goto Done; + } + CompareResult = CompareMem (CompareBuffer, Buffer, BLOCK_SIZE); + if (CompareResult != 0) { + Status = EFI_VOLUME_CORRUPTED; + } + +Done: + if (CompareBuffer != NULL) { + FreePool (CompareBuffer); + } + + return Status; +} + +/** + Write a block of data. + + @param[in] BaseAddress Base address of the block. + @param[in] Buffer Data buffer. + @param[in] BufferSize Size of the buffer. + + @retval EFI_SUCCESS The command completed successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter, can not proceed. + @retval Other Device error or wirte-locked, operation failed. + +**/ +STATIC +EFI_STATUS +InternalWriteBlock ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT8 *Buffer, + IN UINT32 BufferSize + ) +{ + EFI_STATUS Status; + + Status = SpiFlashWrite ((UINTN) BaseAddress, &BufferSize, Buffer); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR (Status)) { + DEBUG((EFI_D_ERROR, "\nFlash write error.")); + return Status; + } + + WriteBackInvalidateDataCacheRange ((VOID *) (UINTN) BaseAddress, BLOCK_SIZE); + + Status = InternalCompareBlock (BaseAddress, Buffer); + if (EFI_ERROR (Status)) { + DEBUG((EFI_D_ERROR, "\nError when writing to BaseAddress %lx with different at offset %x.", BaseAddress, Status)); + } else { + DEBUG((EFI_D_INFO, "\nVerified data written to Block at %lx is correct.", BaseAddress)); + } + + return Status; +} + +STATIC +EFI_STATUS +ReadFileData ( + IN CHAR16 *FileName, + OUT UINT8 **Buffer, + OUT UINT32 *BufferSize + ) +{ + EFI_STATUS Status; + SHELL_FILE_HANDLE FileHandle; + UINT64 Size; + VOID *NewBuffer; + UINTN ReadSize; + + FileHandle = NULL; + NewBuffer = NULL; + Size = 0; + + Status = ShellOpenFileByName (FileName, &FileHandle, EFI_FILE_MODE_READ, 0); + if (EFI_ERROR (Status)) { + goto Done; + } + + Status = FileHandleIsDirectory (FileHandle); + if (!EFI_ERROR (Status)) { + Status = EFI_NOT_FOUND; + goto Done; + } + + Status = FileHandleGetSize (FileHandle, &Size); + if (EFI_ERROR (Status)) { + goto Done; + } + + NewBuffer = AllocatePool ((UINTN) Size); + + ReadSize = (UINTN) Size; + Status = FileHandleRead (FileHandle, &ReadSize, NewBuffer); + if (EFI_ERROR (Status)) { + goto Done; + } else if (ReadSize != (UINTN) Size) { + Status = EFI_INVALID_PARAMETER; + goto Done; + } + +Done: + if (FileHandle != NULL) { + ShellCloseFile (&FileHandle); + } + + if (EFI_ERROR (Status)) { + if (NewBuffer != NULL) { + FreePool (NewBuffer); + } + } else { + *Buffer = NewBuffer; + *BufferSize = (UINT32) Size; + } + + return Status; +} + +/** + Print out help information. + + @param[in] None. + + @retval None. + +**/ +STATIC +VOID +PrintHelpInfo ( + VOID + ) +{ + PrintToken (STRING_TOKEN (STR_FWUPDATE_FIRMWARE_VOL_UPDATE), HiiHandle); + PrintToken (STRING_TOKEN (STR_FWUPDATE_VERSION), HiiHandle); + PrintToken (STRING_TOKEN (STR_FWUPDATE_COPYRIGHT), HiiHandle); + + Print (L"\n"); + PrintToken (STRING_TOKEN (STR_FWUPDATE_USAGE), HiiHandle); + PrintToken (STRING_TOKEN (STR_FWUPDATE_USAGE_1), HiiHandle); + PrintToken (STRING_TOKEN (STR_FWUPDATE_USAGE_2), HiiHandle); + PrintToken (STRING_TOKEN (STR_FWUPDATE_USAGE_3), HiiHandle); + PrintToken (STRING_TOKEN (STR_FWUPDATE_USAGE_4), HiiHandle); + + Print (L"\n"); +} + +/** + Read NumBytes bytes of data from the address specified by + PAddress into Buffer. + + @param[in] Address The starting physical address of the read. + @param[in,out] NumBytes On input, the number of bytes to read. On output, the number + of bytes actually read. + @param[out] Buffer The destination data buffer for the read. + + @retval EFI_SUCCESS Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashRead ( + IN UINTN Address, + IN OUT UINT32 *NumBytes, + OUT UINT8 *Buffer + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINTN Offset = 0; + + ASSERT ((NumBytes != NULL) && (Buffer != NULL)); + + Offset = Address - (UINTN)PcdGet32 (PcdFlashChipBase); + + Status = mSpiProtocol->Execute ( + mSpiProtocol, + 1, //SPI_READ, + 0, //SPI_WREN, + TRUE, + TRUE, + FALSE, + Offset, + BLOCK_SIZE, + Buffer, + EnumSpiRegionAll + ); + + return Status; +} + +/** + Write NumBytes bytes of data from Buffer to the address specified by + PAddresss. + + @param[in] Address The starting physical address of the write. + @param[in,out] NumBytes On input, the number of bytes to write. On output, + the actual number of bytes written. + @param[in] Buffer The source data buffer for the write. + + @retval EFI_SUCCESS Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashWrite ( + IN UINTN Address, + IN OUT UINT32 *NumBytes, + IN UINT8 *Buffer + ) +{ + EFI_STATUS Status; + UINTN Offset; + UINT32 Length; + UINT32 RemainingBytes; + + ASSERT ((NumBytes != NULL) && (Buffer != NULL)); + ASSERT (Address >= (UINTN)PcdGet32 (PcdFlashChipBase)); + + Offset = Address - (UINTN)PcdGet32 (PcdFlashChipBase); + + ASSERT ((*NumBytes + Offset) <= (UINTN)PcdGet32 (PcdFlashChipSize)); + + Status = EFI_SUCCESS; + RemainingBytes = *NumBytes; + + while (RemainingBytes > 0) { + if (RemainingBytes > SIZE_4KB) { + Length = SIZE_4KB; + } else { + Length = RemainingBytes; + } + Status = mSpiProtocol->Execute ( + mSpiProtocol, + SPI_PROG, + SPI_WREN, + TRUE, + TRUE, + TRUE, + (UINT32) Offset, + Length, + Buffer, + EnumSpiRegionAll + ); + if (EFI_ERROR (Status)) { + break; + } + RemainingBytes -= Length; + Offset += Length; + Buffer += Length; + } + + // + // Actual number of bytes written. + // + *NumBytes -= RemainingBytes; + + return Status; +} + +/** + Erase the block starting at Address. + + @param[in] Address The starting physical address of the block to be erased. + This library assume that caller garantee that the PAddress + is at the starting address of this block. + @param[in] NumBytes On input, the number of bytes of the logical block to be erased. + On output, the actual number of bytes erased. + + @retval EFI_SUCCESS. Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashBlockErase ( + IN UINTN Address, + IN UINTN *NumBytes + ) +{ + EFI_STATUS Status; + UINTN Offset; + UINTN RemainingBytes; + + ASSERT (NumBytes != NULL); + ASSERT (Address >= (UINTN)PcdGet32 (PcdFlashChipBase)); + + Offset = Address - (UINTN)PcdGet32 (PcdFlashChipBase); + + ASSERT ((*NumBytes % SIZE_4KB) == 0); + ASSERT ((*NumBytes + Offset) <= (UINTN)PcdGet32 (PcdFlashChipSize)); + + Status = EFI_SUCCESS; + RemainingBytes = *NumBytes; + + while (RemainingBytes > 0) { + Status = mSpiProtocol->Execute ( + mSpiProtocol, + SPI_SERASE, + SPI_WREN, + FALSE, + TRUE, + FALSE, + (UINT32) Offset, + 0, + NULL, + EnumSpiRegionAll + ); + if (EFI_ERROR (Status)) { + break; + } + RemainingBytes -= SIZE_4KB; + Offset += SIZE_4KB; + } + + // + // Actual number of bytes erased. + // + *NumBytes -= RemainingBytes; + + return Status; +} + +EFI_STATUS +EFIAPI +ConvertMac ( + CHAR16 *Str + ) +{ + UINTN Index; + UINT8 Temp[MAC_ADD_STR_LEN]; + + if (Str == NULL) + return EFI_INVALID_PARAMETER; + + if (StrLen(Str) != MAC_ADD_STR_LEN) + return EFI_INVALID_PARAMETER; + + for (Index = 0; Index < MAC_ADD_STR_LEN; Index++) { + if (Str[Index] >= 0x30 && Str[Index] <= 0x39) { + Temp[Index] = (UINT8)Str[Index] - 0x30; + } else if (Str[Index] >= 0x41 && Str[Index] <= 0x46) { + Temp[Index] = (UINT8)Str[Index] - 0x37; + } else if (Str[Index] >= 0x61 && Str[Index] <= 0x66) { + Temp[Index] = (UINT8)Str[Index] - 0x57; + } else { + return EFI_INVALID_PARAMETER; + } + } + + for (Index = 0; Index < MAC_ADD_BYTE_COUNT; Index++) { + mInputData.MacValue[Index] = (Temp[2 * Index] << 4) + Temp[2 * Index + 1]; + } + + return EFI_SUCCESS; +} + diff --git a/BraswellPlatformPkg/Common/Feature/Application/FirmwareUpdate/FirmwareUpdate.h b/BraswellPlatformPkg/Common/Feature/Application/FirmwareUpdate/FirmwareUpdate.h new file mode 100644 index 0000000000..6d2ac9b02e --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/Application/FirmwareUpdate/FirmwareUpdate.h @@ -0,0 +1,190 @@ +/** @file + The header of Firmware Update driver. + + Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _FIRMWARE_UPDATE_H_ +#define _FIRMWARE_UPDATE_H_ + +#include + +#include + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// +// Function Prototypes. +// +STATIC +EFI_STATUS +ReadFileData ( + IN CHAR16 *FileName, + OUT UINT8 **Buffer, + OUT UINT32 *BufferSize + ); + +STATIC +EFI_STATUS +InternalEraseBlock ( + IN EFI_PHYSICAL_ADDRESS BaseAddress + ); + +#if 0 +STATIC +EFI_STATUS +InternalReadBlock ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + OUT VOID *ReadBuffer + ); +#endif + +STATIC +EFI_STATUS +InternalCompareBlock ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT8 *Buffer + ); + +STATIC +EFI_STATUS +InternalWriteBlock ( + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT8 *Buffer, + IN UINT32 BufferSize + ); + +STATIC +VOID +PrintHelpInfo ( + VOID + ); + +STATIC +EFI_STATUS +EFIAPI +SpiFlashRead ( + IN UINTN Address, + IN OUT UINT32 *NumBytes, + OUT UINT8 *Buffer + ); + +STATIC +EFI_STATUS +EFIAPI +SpiFlashWrite ( + IN UINTN Address, + IN OUT UINT32 *NumBytes, + IN UINT8 *Buffer + ); + +STATIC +EFI_STATUS +EFIAPI +SpiFlashBlockErase ( + IN UINTN Address, + IN UINTN *NumBytes + ); + +STATIC +EFI_STATUS +EFIAPI +ConvertMac ( + CHAR16 *Str + ); + +EFI_STATUS +InitializeFVUPDATE ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +// +// Flash specific definitions. +// - Should we use a PCD for this information? +// +#define BLOCK_SIZE SIZE_4KB + +// +// Flash region layout and update information. +// +typedef struct { + EFI_PHYSICAL_ADDRESS Base; + UINTN Size; + BOOLEAN Update; +} FV_REGION_INFO; + +// +// MAC Address information. +// +#define MAC_ADD_STR_LEN 12 +#define MAC_ADD_STR_SIZE (MAC_ADD_STR_LEN + 1) +#define MAC_ADD_BYTE_COUNT 6 +#define MAC_ADD_TMP_STR_LEN 2 +#define MAC_ADD_TMP_STR_SIZE (MAC_ADD_TMP_STR_LEN + 1) + +// +// Command Line Data. +// +#define INPUT_STRING_LEN 255 +#define INPUT_STRING_SIZE (INPUT_STRING_LEN + 1) +typedef struct { + BOOLEAN UpdateFromFile; + CHAR16 FileName[INPUT_STRING_SIZE]; + BOOLEAN UpdateMac; + UINT8 MacValue[MAC_ADD_BYTE_COUNT]; + BOOLEAN FullFlashUpdate; +} FV_INPUT_DATA; + +// +// Prefix Opcode Index on the host SPI controller. +// +typedef enum { + SPI_WREN, // Prefix Opcode 0: Write Enable. + SPI_EWSR, // Prefix Opcode 1: Enable Write Status Register. +} PREFIX_OPCODE_INDEX; + +// +// Opcode Menu Index on the host SPI controller. +// +typedef enum { + SPI_READ_ID, // Opcode 0: READ ID, Read cycle with address. + SPI_READ, // Opcode 1: READ, Read cycle with address. + SPI_RDSR, // Opcode 2: Read Status Register, No address. + SPI_WRDI_SFDP, // Opcode 3: Write Disable or Discovery Parameters, No address. + SPI_SERASE, // Opcode 4: Sector Erase (4KB), Write cycle with address. + SPI_BERASE, // Opcode 5: Block Erase (32KB), Write cycle with address. + SPI_PROG, // Opcode 6: Byte Program, Write cycle with address. + SPI_WRSR, // Opcode 7: Write Status Register, No address. +} SPI_OPCODE_INDEX; + +#endif diff --git a/BraswellPlatformPkg/Common/Feature/Application/FirmwareUpdate/FirmwareUpdate.inf b/BraswellPlatformPkg/Common/Feature/Application/FirmwareUpdate/FirmwareUpdate.inf new file mode 100644 index 0000000000..f102644916 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/Application/FirmwareUpdate/FirmwareUpdate.inf @@ -0,0 +1,75 @@ +## @file +# Implements a Intel(R) Atom(TM) x5 Processor Series specific flash update program. This will allow +# users to update all regions of the flash as needed in a given update. +# +# Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = FirmwareUpdate + FILE_GUID = 398F95AC-B126-4E13-8847-417021C7A92B + MODULE_TYPE = UEFI_APPLICATION + VERSION_STRING = 1.0 + ENTRY_POINT = ShellCEntryLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = X64 +# + +[Sources] + FirmwareUpdateStrings.uni + FirmwareUpdate.c + FirmwareUpdate.h + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + BraswellPlatformPkg/BraswellPlatformPkg.dec + ChvRefCodePkg/ChvRefCodePkg.dec + ShellPkg/ShellPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + CacheMaintenanceLib + DebugLib + FileHandleLib + MemoryAllocationLib + PcdLib + ShellCEntryLib + ShellLib + UefiApplicationEntryPoint + UefiBootServicesTableLib + UefiLib + UefiRuntimeServicesTableLib + +[Protocols] + gEfiSpiProtocolGuid ## CONSUMES + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdFlashChipBase ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdFlashChipSize ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdFlashDescriptorBase ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdFlashDescriptorSize ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdTxeRomBase ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdTxeRomSize ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdBiosRomBase ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdBiosRomSize ## CONSUMES + +[BuildOptions] + MSFT:*_*_X64_CC_FLAGS = /Od + INTEL:*_*_X64_CC_FLAGS = /Od + diff --git a/BraswellPlatformPkg/Common/Feature/Application/FirmwareUpdate/FirmwareUpdateStrings.uni b/BraswellPlatformPkg/Common/Feature/Application/FirmwareUpdate/FirmwareUpdateStrings.uni new file mode 100644 index 0000000000..e8204aafcb --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/Application/FirmwareUpdate/FirmwareUpdateStrings.uni @@ -0,0 +1,52 @@ +// /** @file +// +// Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// **/ + +#langdef en-US "English" +#langdef fr-FR "Français" + +#string STR_FWUPDATE_FIRMWARE_VOL_UPDATE #language en-US "Intel(R) UDK2014 Firmware Update Utility for the Intel(R) Braswell Platform\n" +#string STR_FWUPDATE_COPYRIGHT #language en-US "Copyright(c) Intel Corporation 2006 - 2014\n" + #language fr-FR "Déposer(c) la Société commerciale de Intel 2006 - 2014\n" +#string STR_FWUPDATE_VERSION #language en-US "Version 0.72\n" + +#string STR_FWUPDATE_ZEROLENGTH_ARG #language en-US "Argument with zero length is not allowed\n" + #language fr-FR "L'argument avec zéro longueur n'est pas permis\n" +#string STR_FWUPDATE_INVAILD_MAC #language en-US "Invalid MAC address.\n" +#string STR_FWUPDATE_READ_FILE #language en-US "\nReading file %s\n" +#string STR_FWUPDATE_READ_FILE_ERROR #language en-US "Unable to read file %s\n" +#string STR_FWUPDATE_SIZE #language en-US "File size should be 16MB\n" + #language fr-FR "Doit être 16 MB\n" +#string STR_FWUPDATE_UPDATE_SUCCESS #language en-US "Update successful\n" + #language fr-FR "Met à jour prospère\n" +#string STR_FWUPDATE_UPDATE_FAILED #language en-US "\nUpdate failed. Please make sure the flash is not write protected.\n" +#string STR_FWUPDATE_RESET #language en-US "\rResetting system in %d seconds ..." + #language fr-FR "\rLe système qui remettre à l'état initial dans %d les secondes ..." +#string STR_FWUPDATE_SHUTDOWN #language en-US "\rShutdown system in %d seconds ..." +#string STR_FWUPDATE_MANUAL_RESET #language en-US "\nPls manually reset system ...\n" + #language fr-FR "\nS'il vous plaît manuellement remet à l'état initial le système ...\n" +#string STR_FWUPDATE_NO_RESET #language en-US "Already up to date\n" +#string STR_MISSING_MAC_ARG #language en-US "Option -m specified without MAC address.\n" +#string STR_INVALID_MAC_ARG #language en-US "Invalid MAC address format used (e.g. -m 0011AA33CC55).\n" +#string STR_FWUPDATE_FILE_NOT_FOUND_ERROR #language en-US "File %s not found.\n" +#string STR_FWUPDATE_PATH_ERROR #language en-US "File path/name too long.\n" +#string STR_FWUPDATE_UPDATING_FIRMWARE #language en-US "\nUpdating Firmware. This may take a few minutes.\n" +#string STR_FWUPDATE_UPDATING_MAC #language en-US "\nUpdating MAC Address.\n" +#string STR_SPI_NOT_FOUND #language en-US "\nSPI Protocol is not found.\n" + +#string STR_FWUPDATE_USAGE #language en-US "Usage: FirmwareUpdate [IMAGEFILE]\n" +#string STR_FWUPDATE_USAGE_1 #language en-US "\n" +#string STR_FWUPDATE_USAGE_2 #language en-US " Programs the 8MB IMAGEFILE for the Braswell Platform.\n" +#string STR_FWUPDATE_USAGE_3 #language en-US " \n" +#string STR_FWUPDATE_USAGE_4 #language en-US " \n" + diff --git a/BraswellPlatformPkg/Common/Feature/Logo/Logo.bmp b/BraswellPlatformPkg/Common/Feature/Logo/Logo.bmp new file mode 100644 index 0000000000..26ac1a81da Binary files /dev/null and b/BraswellPlatformPkg/Common/Feature/Logo/Logo.bmp differ diff --git a/BraswellPlatformPkg/Common/Feature/PciPlatform/PciPlatform.c b/BraswellPlatformPkg/Common/Feature/PciPlatform/PciPlatform.c new file mode 100644 index 0000000000..5455832cf9 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/PciPlatform/PciPlatform.c @@ -0,0 +1,303 @@ +/** @file + The implementation of functions by Pci Platform Driver + + Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "PciPlatform.h" +#include "PchRegs.h" +#include "PchAccess.h" +#include "ChvCommonDefinitions.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern PCI_OPTION_ROM_TABLE mPciOptionRomTable[]; +extern UINTN mSizeOptionRomTable; + +EFI_PCI_PLATFORM_PROTOCOL mPciPlatform = { + PhaseNotify, + PlatformPrepController, + GetPlatformPolicy, + GetPciRom +}; + +EFI_HANDLE mPciPlatformHandle = NULL; + +SYSTEM_CONFIGURATION mSystemConfiguration; + +VOID *mPciRegistration; + +/** + Standard Pci Bus event notification + @param[in] Event the event that is signaled. + @param[in] Context not used here. + +**/ +VOID +EFIAPI +PciBusEvent ( + IN EFI_EVENT Event, + IN VOID* Context + ); + +EFI_STATUS +PciBusDriverHook ( + ) +{ + EFI_STATUS Status; + EFI_EVENT FilterEvent; + + // + // Register for callback to PCI I/O protocol + // + Status = gBS->CreateEvent ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + PciBusEvent, + NULL, + &FilterEvent + ); + ASSERT_EFI_ERROR (Status); + + // + // Register for protocol notifications on this event + // + Status = gBS->RegisterProtocolNotify ( + &gEfiPciIoProtocolGuid, + FilterEvent, + &mPciRegistration + ); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + +VOID +ProgramPciLatency ( + IN EFI_PCI_IO_PROTOCOL *PciIo + ) +{ + EFI_STATUS Status; + + // + // Program Master Latency Timer + // + if (mSystemConfiguration.PciLatency != 0) { + Status = PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint8, + PCI_LATENCY_TIMER_OFFSET, + 1, + &mSystemConfiguration.PciLatency + ); + } + + return; +} + +/** + Standard Pci Bus event notification + @param[in] Event the event that is signaled. + @param[in] Context not used here. + +**/ +VOID +EFIAPI +PciBusEvent ( + IN EFI_EVENT Event, + IN VOID* Context + ) +{ + + EFI_STATUS Status; + UINTN BufferSize; + EFI_HANDLE Handle; + EFI_PCI_IO_PROTOCOL *PciIo; + UINT64 Supports; + UINT8 mCacheLineSize = 0x10; + UINT16 VendorId; + + while (TRUE) { + BufferSize = sizeof (EFI_HANDLE); + Status = gBS->LocateHandle ( + ByRegisterNotify, + NULL, + mPciRegistration, + &BufferSize, + &Handle + ); + if (EFI_ERROR (Status)) { + // + // If no more notification events exist + // + return; + } + + Status = gBS->HandleProtocol ( + Handle, + &gEfiPciIoProtocolGuid, + &PciIo + ); + + PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, 0, 1, &VendorId); + // + // Enable I/O for bridge so port 0x80 codes will come out + // + if (VendorId == V_PCH_INTEL_VENDOR_ID) { + Status = PciIo->Attributes( + PciIo, + EfiPciIoAttributeOperationSupported, + 0, + &Supports + ); + Supports &= EFI_PCI_DEVICE_ENABLE; + Status = PciIo->Attributes ( + PciIo, + EfiPciIoAttributeOperationEnable, + Supports, + NULL + ); + break; + } + + // + // Program PCI Latency Timer + // + ProgramPciLatency(PciIo); + + // + // Program Cache Line Size to 64 bytes (0x10 DWORDs) + // + Status = PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint8, + PCI_CACHELINE_SIZE_OFFSET, + 1, + &mCacheLineSize + ); + } + + return; +} + +EFI_STATUS +EFIAPI +PhaseNotify ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ) +{ + return EFI_UNSUPPORTED; +} + +EFI_STATUS +EFIAPI +PlatformPrepController ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_HANDLE RootBridge, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ) +{ + return EFI_UNSUPPORTED; +} + +EFI_STATUS +EFIAPI +GetPlatformPolicy ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + OUT EFI_PCI_PLATFORM_POLICY *PciPolicy + ) +{ + *PciPolicy = EFI_RESERVE_VGA_IO_ALIAS; + + return EFI_SUCCESS; +} + +/** + GetPciRom from platform specific location for specific PCI device + + @param[in] This Protocol instance + @param[in] PciHandle Identify the specific PCI devic + @param[out] RomImage Returns the ROM Image memory location + @param[out] RomSize Returns Rom Image size + + @retval EFI_SUCCESS + @retval EFI_NOT_FOUND + @retval EFI_OUT_OF_RESOURCES + +**/ +EFI_STATUS +EFIAPI +GetPciRom ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE PciHandle, + OUT VOID **RomImage, + OUT UINTN *RomSize + ) +{ + return EFI_NOT_FOUND; +} + +/** + The Entry Point for Pci Platform driver. + + @param[in] ImageHandle A handle for the image that is initializing this driver + @param[in] SystemTable A pointer to the EFI system table + + @retval EFI_SUCCESS The driver is executed successfully. + @retval Other value Some error occurs when executing this driver. + +**/ +EFI_STATUS +EFIAPI +PciPlatformDriverEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + CopyMem (&mSystemConfiguration, PcdGetPtr (PcdSystemConfiguration), sizeof(SYSTEM_CONFIGURATION)); + + // + // Install on a new handle + // + Status = gBS->InstallProtocolInterface ( + &mPciPlatformHandle, + &gEfiPciPlatformProtocolGuid, + EFI_NATIVE_INTERFACE, + &mPciPlatform + ); + + // + // Install PCI Bus Driver Hook + // + PciBusDriverHook (); + + return Status; +} + diff --git a/BraswellPlatformPkg/Common/Feature/PciPlatform/PciPlatform.h b/BraswellPlatformPkg/Common/Feature/PciPlatform/PciPlatform.h new file mode 100644 index 0000000000..154e47a047 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/PciPlatform/PciPlatform.h @@ -0,0 +1,80 @@ +/** @file + The implementation of functions by Pci Platform Driver. + + Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef PCI_PLATFORM_H_ +#define PCI_PLATFORM_H_ + +#include +#include "Platform.h" + +// +// Produced Protocols +// +#include + +#define IGD_DID_II 0x0BE1 +#define IGD_DID_0BE4 0x0BE4 +#define IGD_DID_VLV_A0 0x0F31 +#define OPROM_DID_OFFSET 0x46 + +typedef struct { + EFI_GUID FileName; + UINTN Segment; + UINTN Bus; + UINTN Device; + UINTN Function; + UINT16 VendorId; + UINT16 DeviceId; + UINT8 Flag; +} PCI_OPTION_ROM_TABLE; + +EFI_STATUS +EFIAPI +PhaseNotify ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ); + +EFI_STATUS +EFIAPI +PlatformPrepController ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_HANDLE RootBridge, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ); + +EFI_STATUS +EFIAPI +GetPlatformPolicy ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + OUT EFI_PCI_PLATFORM_POLICY *PciPolicy + ); + +EFI_STATUS +EFIAPI +GetPciRom ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE PciHandle, + OUT VOID **RomImage, + OUT UINTN *RomSize + ); + +#endif + diff --git a/BraswellPlatformPkg/Common/Feature/PciPlatform/PciPlatform.inf b/BraswellPlatformPkg/Common/Feature/PciPlatform/PciPlatform.inf new file mode 100644 index 0000000000..9f4f88ab83 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/PciPlatform/PciPlatform.inf @@ -0,0 +1,58 @@ +## @file +# Component description file for PciPlatform module +# +# Get Pci Rom from platform specific location for specific PCI device. +# +# Copyright (c) 2003 - 2015, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[defines] + INF_VERSION = 0x00010005 + BASE_NAME = PciPlatform + FILE_GUID = 2BD21AC8-7FF5-456A-BE55-83F9F2DAE6E0 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = PciPlatformDriverEntry + +[sources.common] + PciPlatform.c + PciPlatform.h + +[Protocols] + gEfiPciPlatformProtocolGuid ## PRODUCES + gEfiPciRootBridgeIoProtocolGuid ## CONSUMES + gEfiPciIoProtocolGuid ## CONSUMES + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + BraswellPlatformPkg/BraswellPlatformPkg.dec + ChvRefCodePkg/ChvRefCodePkg.dec + IntelFrameworkPkg/IntelFrameworkPkg.dec + +[LibraryClasses] + HobLib + UefiDriverEntryPoint + BaseLib + BaseMemoryLib + UefiDriverEntryPoint + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + DxeServicesTableLib + +[Pcd] + gEfiEdkIIPlatformTokenSpaceGuid.PcdSystemConfiguration + +[Depex] + gEfiVariableArchProtocolGuid AND + gEfiVariableWriteArchProtocolGuid + diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/CommonHeader.h b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/CommonHeader.h new file mode 100644 index 0000000000..58497fe533 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/CommonHeader.h @@ -0,0 +1,41 @@ +/** @file + Common header file shared by all source files. + This file includes package header files, library classes and protocol, PPI & GUID definitions. + + Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __COMMON_HEADER_H_ +#define __COMMON_HEADER_H_ + +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBaseBoardManufacturer.uni b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBaseBoardManufacturer.uni new file mode 100644 index 0000000000..17e3ec66a3 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBaseBoardManufacturer.uni @@ -0,0 +1,30 @@ +// /** @file +// Base board information. +// +// Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// **/ + + +/=# + +#langdef en-US "English" + +#string STR_MISC_BASE_BOARD_MANUFACTURER #language en-US "Intel Corp." +#string STR_MISC_BASE_BOARD_PRODUCT_NAME #language en-US "Braswell Platform" +#string STR_MISC_BASE_BOARD_PRODUCT_NAME_FFD8 #language en-US "Braswell Platform" +#string STR_MISC_BASE_BOARD_PRODUCT_NAME1 #language en-US "Braswell Platform" +#string STR_MISC_BASE_BOARD_VERSION #language en-US "FAB" +#string STR_MISC_BASE_BOARD_VERSION_FFD8 #language en-US "FAB" +#string STR_MISC_BASE_BOARD_SERIAL_NUMBER #language en-US "1" +#string STR_MISC_BASE_BOARD_ASSET_TAG #language en-US "Base Board Asset Tag" +#string STR_MISC_BASE_BOARD_CHASSIS_LOCATION #language en-US "Part Component" + diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBaseBoardManufacturerData.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBaseBoardManufacturerData.c new file mode 100644 index 0000000000..c9f0aee4d2 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBaseBoardManufacturerData.c @@ -0,0 +1,52 @@ +/** @file + Static data of Base board manufacturer information. + Base board manufacturer information is Misc for subclass type 4, SMBIOS type 2. + + Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" + +#include "MiscSubclassDriver.h" + +// +// Static (possibly build generated) Bios Vendor data. +// +MISC_SMBIOS_TABLE_DATA(EFI_MISC_BASE_BOARD_MANUFACTURER_DATA, MiscBaseBoardManufacturer) += { + STRING_TOKEN(STR_MISC_BASE_BOARD_MANUFACTURER), + STRING_TOKEN(STR_MISC_BASE_BOARD_PRODUCT_NAME), + STRING_TOKEN(STR_MISC_BASE_BOARD_VERSION), + STRING_TOKEN(STR_MISC_BASE_BOARD_SERIAL_NUMBER), + STRING_TOKEN(STR_MISC_BASE_BOARD_ASSET_TAG), + STRING_TOKEN(STR_MISC_BASE_BOARD_CHASSIS_LOCATION), + { // BaseBoardFeatureFlags + 1, // Motherboard + 0, // RequiresDaughterCard + 0, // Removable + 1, // Replaceable, + 0, // HotSwappable + 0, // Reserved + }, + EfiBaseBoardTypeUnknown, // BaseBoardType + { // BaseBoardChassisLink + EFI_MISC_SUBCLASS_GUID, // ProducerName + 1, // Instance + 1, // SubInstance + }, + 0, // BaseBoardNumberLinks + { // LinkN + EFI_MISC_SUBCLASS_GUID, // ProducerName + 1, // Instance + 1, // SubInstance + }, +}; diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBaseBoardManufacturerFunction.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBaseBoardManufacturerFunction.c new file mode 100644 index 0000000000..7c27e4c6a8 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBaseBoardManufacturerFunction.c @@ -0,0 +1,313 @@ +/** @file + BaseBoard manufacturer information boot time changes for SMBIOS type 2. + + Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" +#include "Library/DebugLib.h" +#include +#include + +/** + This function makes boot time changes to the contents of the + MiscBaseBoardManufacturer (Type 2). + + @param RecordData Pointer to copy of RecordData from the Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +MISC_SMBIOS_TABLE_FUNCTION(MiscBaseBoardManufacturer) +{ + CHAR8 *OptionalStrStart; + UINTN ManuStrLen; + UINTN VerStrLen; + UINTN PdNameStrLen; + UINTN SerialNumStrLen; + UINTN AssetTagLen; + EFI_STATUS Status; + CHAR16 Manufacturer[SMBIOS_STRING_MAX_LENGTH]; + CHAR16 ProductName[SMBIOS_STRING_MAX_LENGTH]; + CHAR16 Version[SMBIOS_STRING_MAX_LENGTH]; + CHAR16 SerialNumber[SMBIOS_STRING_MAX_LENGTH]; + CHAR16 AssetTag[SMBIOS_STRING_MAX_LENGTH]; + EFI_STRING ManufacturerPtr; + EFI_STRING ProductNamePtr; + EFI_STRING VersionPtr; + EFI_STRING SerialNumberPtr; + EFI_STRING AssetTagPtr; + STRING_REF TokenToGet; + STRING_REF TokenToUpdate; + EFI_SMBIOS_HANDLE SmbiosHandle; + SMBIOS_TABLE_TYPE2 *SmbiosRecord; + EFI_MISC_BASE_BOARD_MANUFACTURER *ForType2InputData; + UINTN RecordLengthInBytes; + EFI_PLATFORM_INFO_HOB *PlatformInfoHob; + + PlatformInfoHob = PcdGetPtr (PcdPlatformInfo); + + ForType2InputData = (EFI_MISC_BASE_BOARD_MANUFACTURER *)RecordData; + + // + // First check for invalid parameters. + // + if (RecordData == NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // Update strings from PCD for STR_MISC_BASE_BOARD_MANUFACTURER + // + AsciiStrToUnicodeStr ((const CHAR8*)PcdGetPtr(PcdSMBIOSBoardManufacturer), Manufacturer); + if (StrLen (Manufacturer) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_BASE_BOARD_MANUFACTURER); + HiiSetString (mHiiHandle, TokenToUpdate, Manufacturer, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_MANUFACTURER); + ManufacturerPtr = SmbiosMiscGetString (TokenToGet); + ManuStrLen = StrLen(ManufacturerPtr); + if (ManuStrLen > SMBIOS_STRING_MAX_LENGTH) { + DEBUG (( DEBUG_ERROR, "ManuStrLen (0x%08x) > 0x%08x\r\n", ManuStrLen, SMBIOS_STRING_MAX_LENGTH )); + return EFI_UNSUPPORTED; + } + + // + // Get Product name from BoardId + // + switch (PlatformInfoHob->BoardId) { + case 0x00: + StrCpy (ProductName, L"Alpine Valley Board"); + break; + case 0x01: + StrCpy (ProductName, L"Cherry Trail CR"); + break; + case 0x02: + StrCpy (ProductName, L"Cherry Trail COPOP"); + break; + case 0x03: + StrCpy (ProductName, L"Cherry Trail Tablet"); + break; + case 0x04: + StrCpy (ProductName, L"Cherry Trail Sony"); + break; + case 0x05: + StrCpy (ProductName, L"BayLake Board (RVP DDR3L)"); + break; + case 0x07: + StrCpy (ProductName, L"PPV- STHI Board"); + break; + case 0x08: + StrCpy (ProductName, L"Cherry Trail FFD"); + break; + case 0x09: + StrCpy (ProductName, L"Cherry Trail Tablet"); + break; + case 0x0A: + StrCpy (ProductName, L"Cherry Trail FFD"); + break; + case 0x20: + StrCpy (ProductName, L"Bayley Bay Board"); + break; + case 0x30: + StrCpy (ProductName, L"Bakersport Board"); + break; + case 0x44: + StrCpy (ProductName, L"Braswell CRB"); + break; + case 0x55: + StrCpy (ProductName, L"Braswell LC"); + break; + case 0x60: + StrCpy (ProductName, L"Braswell RVP ECC"); + break; + case 0x80: + StrCpy (ProductName, L"Braswell Cherry Hill"); + break; + case 0x82: + StrCpy (ProductName, L"Braswell Cherry Island"); + break; + case 0xEE: + StrCpy (ProductName, L"Bakersport Board"); + break; + case 0xF1: + StrCpy (ProductName, L"BayLake FFRD"); + break; + case 0xF2: + StrCpy (ProductName, L"BayLake RVP"); + break; + case 0xF3: + StrCpy (ProductName, L"CherryTrail ERB"); + break; + case 0xF4: + StrCpy (ProductName, L"CherryTrail CRB"); + break; + case 0xF5: + StrCpy (ProductName, L"Baytrail FFRD8"); + break; + default: + StrCpy (ProductName, L"CherryTrail Platform"); + break; + } + + if (StrLen (ProductName) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_BASE_BOARD_PRODUCT_NAME); + HiiSetString (mHiiHandle, TokenToUpdate, ProductName, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_PRODUCT_NAME); + ProductNamePtr = SmbiosMiscGetString (TokenToGet); + PdNameStrLen = StrLen(ProductNamePtr); + if (PdNameStrLen > SMBIOS_STRING_MAX_LENGTH) { + DEBUG (( DEBUG_ERROR, "PdNameStrLen (0x%08x) > 0x%08x\r\n", PdNameStrLen, SMBIOS_STRING_MAX_LENGTH )); + return EFI_UNSUPPORTED; + } + + // + // Update strings from PCD for STR_MISC_BASE_BOARD_VERSION + // + AsciiStrToUnicodeStr ((const CHAR8*)PcdGetPtr(PcdSMBIOSBoardVersion), Version); + if (StrLen (Version) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_BASE_BOARD_VERSION); + HiiSetString (mHiiHandle, TokenToUpdate, Version, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_VERSION); + VersionPtr = SmbiosMiscGetString (TokenToGet); + VerStrLen = StrLen(VersionPtr); + if (VerStrLen > SMBIOS_STRING_MAX_LENGTH) { + DEBUG (( DEBUG_ERROR, "VerStrLen (0x%08x) > 0x%08x\r\n", VerStrLen, SMBIOS_STRING_MAX_LENGTH )); + return EFI_UNSUPPORTED; + } + + // + // Update strings from PCD for STR_MISC_BASE_BOARD_SERIAL_NUMBER + // + AsciiStrToUnicodeStr ((const CHAR8*)PcdGetPtr(PcdSMBIOSBoardSerialNumber), SerialNumber); + if (StrLen (SerialNumber) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_BASE_BOARD_SERIAL_NUMBER); + HiiSetString (mHiiHandle, TokenToUpdate, SerialNumber, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_SERIAL_NUMBER); + SerialNumberPtr = SmbiosMiscGetString (TokenToGet); + SerialNumStrLen = StrLen(SerialNumberPtr); + if (SerialNumStrLen > SMBIOS_STRING_MAX_LENGTH) { + DEBUG (( DEBUG_ERROR, "SerialNumStrLen (0x%08x) > 0x%08x\r\n", SerialNumStrLen, SMBIOS_STRING_MAX_LENGTH )); + return EFI_UNSUPPORTED; + } + + // + // Update strings from PCD for STR_MISC_BASE_BOARD_ASSET_TAG + // + AsciiStrToUnicodeStr ((const CHAR8*)PcdGetPtr(PcdSMBIOSBoardAssetTag), AssetTag); + if (StrLen (AssetTag) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_BASE_BOARD_ASSET_TAG); + HiiSetString (mHiiHandle, TokenToUpdate, AssetTag, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_ASSET_TAG); + AssetTagPtr = SmbiosMiscGetString (TokenToGet); + AssetTagLen = StrLen(AssetTagPtr); + if (AssetTagLen > SMBIOS_STRING_MAX_LENGTH) { + DEBUG (( DEBUG_ERROR, "AssetTagLen (0x%08x) > 0x%08x\r\n", AssetTagLen, SMBIOS_STRING_MAX_LENGTH )); + return EFI_UNSUPPORTED; + } + + // + // Two zeros following the last string. + // + RecordLengthInBytes = sizeof (SMBIOS_TABLE_TYPE2) + + ManuStrLen + 1 + + PdNameStrLen + 1 + + VerStrLen + 1 + + SerialNumStrLen + 1 + + AssetTagLen + 1 + + 1; + SmbiosRecord = AllocateZeroPool(RecordLengthInBytes); + + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION; + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE2); + + // + // Make handle chosen by smbios protocol.add automatically. + // + SmbiosRecord->Hdr.Handle = 0; + + // + // Manu will be the 1st optional string following the formatted structure. + // + SmbiosRecord->Manufacturer = 1; + + // + // ProductName will be the 2st optional string following the formatted structure. + // + SmbiosRecord->ProductName = 2; + + // + // Version will be the 3rd optional string following the formatted structure. + // + SmbiosRecord->Version = 3; + + // + // SerialNumber will be the 4th optional string following the formatted structure. + // + SmbiosRecord->SerialNumber = 4; + + // + // AssertTag will be the 5th optional string following the formatted structure. + // + SmbiosRecord->AssetTag = 5; + + // + // LocationInChassis will be the 6th optional string following the formatted structure. + // + SmbiosRecord->LocationInChassis = 6; + SmbiosRecord->FeatureFlag = (*(BASE_BOARD_FEATURE_FLAGS*)&(ForType2InputData->BaseBoardFeatureFlags)); + SmbiosRecord->ChassisHandle = 0; + SmbiosRecord->BoardType = (UINT8)ForType2InputData->BaseBoardType; + SmbiosRecord->NumberOfContainedObjectHandles = 0; + + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1); + + // + // Since we fill NumberOfContainedObjectHandles = 0 for simple, just after this filed to fill string + // + UnicodeStrToAsciiStr(ManufacturerPtr, OptionalStrStart); + UnicodeStrToAsciiStr(ProductNamePtr, OptionalStrStart + ManuStrLen + 1); + UnicodeStrToAsciiStr(VersionPtr, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1); + UnicodeStrToAsciiStr(SerialNumberPtr, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1); + UnicodeStrToAsciiStr(AssetTagPtr, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen+ 1); + + // + // Now we have got the full smbios record, call smbios protocol to add this record. + // + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios-> Add( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord + ); + + FreePool(SmbiosRecord); + + // + // Free the memory allocated before + // + FreePool (ManufacturerPtr); + FreePool (ProductNamePtr); + FreePool (VersionPtr); + FreePool (SerialNumberPtr); + FreePool (AssetTagPtr); + + return Status; +} diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBiosVendor.uni b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBiosVendor.uni new file mode 100644 index 0000000000..62e1966ad1 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBiosVendor.uni @@ -0,0 +1,23 @@ +// /** @file +// BIOS vendor information. +// +// Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// **/ + + +/=# + +#langdef en-US "English" + +#string STR_MISC_BIOS_VENDOR #language en-US "Intel Corp." +#string STR_MISC_BIOS_VERSION #language en-US "Cherryview Platform BIOS" +#string STR_MISC_BIOS_RELEASE_DATE #language en-US "12/01/2015" diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBiosVendorData.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBiosVendorData.c new file mode 100644 index 0000000000..9b3947c647 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBiosVendorData.c @@ -0,0 +1,95 @@ +/** @file + Static data of BIOS vendor information. + BIOS vendor information is Misc for subclass type 2, SMBIOS type 0. + + Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" + +#include "MiscSubclassDriver.h" + +// +// Static (possibly build generated) Bios Vendor data. +// +MISC_SMBIOS_TABLE_DATA(EFI_MISC_BIOS_VENDOR_DATA, MiscBiosVendor) += { + STRING_TOKEN(STR_MISC_BIOS_VENDOR), // BiosVendor + STRING_TOKEN(STR_MISC_BIOS_VERSION), // BiosVersion + STRING_TOKEN(STR_MISC_BIOS_RELEASE_DATE), // BiosReleaseDate + 0xF000, // BiosStartingAddress + { // BiosPhysicalDeviceSize + 1, // Value + 21 , // Exponent + }, + { // BiosCharacteristics1 + 0, // Reserved1 :2 + 0, // Unknown :1 + 0, // BiosCharacteristicsNotSupported :1 + 0, // IsaIsSupported :1 + 0, // McaIsSupported :1 + 0, // EisaIsSupported :1 + 1, // PciIsSupported :1 + 0, // PcmciaIsSupported :1 + 0, // PlugAndPlayIsSupported :1 + 0, // ApmIsSupported :1 + 1, // BiosIsUpgradable :1 + 1, // BiosShadowingAllowed :1 + 0, // VlVesaIsSupported :1 + 0, // EscdSupportIsAvailable :1 + 1, // BootFromCdIsSupported :1 + 1, // SelectableBootIsSupported :1 + 0, // RomBiosIsSocketed :1 + 0, // BootFromPcmciaIsSupported :1 + 1, // EDDSpecificationIsSupported :1 + 0, // JapaneseNecFloppyIsSupported :1 + 0, // JapaneseToshibaFloppyIsSupported :1 + 0, // Floppy525_360IsSupported :1 + 0, // Floppy525_12IsSupported :1 + 0, // Floppy35_720IsSupported :1 + 0, // Floppy35_288IsSupported :1 + 0, // PrintScreenIsSupported :1 + 1, // Keyboard8042IsSupported :1 + 1, // SerialIsSupported :1 + 1, // PrinterIsSupported :1 + 1, // CgaMonoIsSupported :1 + 0, // NecPc98 :1 + +// +//BIOS Characteristics Extension Byte 1 +// + 1, // AcpiIsSupported :1 + 1, // UsbLegacyIsSupported :1 + 0, // AgpIsSupported :1 + 0, // I20BootIsSupported :1 + 0, // Ls120BootIsSupported :1 + 1, // AtapiZipDriveBootIsSupported :1 + 0, // Boot1394IsSupported :1 + 0, // SmartBatteryIsSupported :1 + +// +//BIOS Characteristics Extension Byte 2 +// + 1, // BiosBootSpecIsSupported :1 + 1, // FunctionKeyNetworkBootIsSupported :1 + 0x1 // Reserved :19 Bit 2 is SMBiosIsTargContDistEnabled + }, + { // BiosCharacteristics2 + 0x0001,// BiosReserved :16 Bit 0 is BIOS Splash Screen + 0, // SystemReserved :16 + 0 // Reserved :32 + }, + 0xFF, // BiosMajorRelease; + 0xFF, // BiosMinorRelease; + 0xFF, // BiosEmbeddedFirmwareMajorRelease; + 0xFF, // BiosEmbeddedFirmwareMinorRelease; +}; diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBiosVendorFunction.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBiosVendorFunction.c new file mode 100644 index 0000000000..33c542fc65 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBiosVendorFunction.c @@ -0,0 +1,245 @@ +/** @file + BIOS vendor information boot time changes for Misc subclass type 2, SMBIOS type 0. + + Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" + +#include "MiscSubclassDriver.h" + +/** + This function returns the value & exponent to Base2 for a given + Hex value. This is used to calculate the BiosPhysicalDeviceSize. + + @param[in, out] Value The hex value which is to be converted into value-exponent form + @param[out] Exponent The exponent out of the conversion + + @retval EFI_SUCCESS All parameters were valid and *Value & *Exponent have been set. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +EFI_STATUS +GetValueExponentBase2( + IN OUT UINTN *Value, + OUT UINTN *Exponent + ) +{ + if ((Value == NULL) || (Exponent == NULL)) { + return EFI_INVALID_PARAMETER; + } + + while ((*Value % 2) == 0) { + *Value=*Value/2; + (*Exponent)++; + } + + return EFI_SUCCESS; +} + +/** + Field Filling Function. Transform an EFI_EXP_BASE2_DATA to a byte, with '64k' + as the unit. + + @param[in] Base2Data Pointer to Base2_Data + + @retval EFI_SUCCESS Transform successfully. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +UINT16 +Base2ToByteWith64KUnit ( + IN EFI_EXP_BASE2_DATA *Base2Data + ) +{ + UINT16 Value; + UINT16 Exponent; + + Value = Base2Data->Value; + Exponent = Base2Data->Exponent; + Exponent -= 16; + Value <<= Exponent; + + return Value; +} + +/** + This function makes boot time changes to the contents of the + MiscBiosVendor (Type 0). + + @param RecordData Pointer to copy of RecordData from the Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +MISC_SMBIOS_TABLE_FUNCTION(MiscBiosVendor) +{ + CHAR8 *OptionalStrStart; + UINTN VendorStrLen; + UINTN VerStrLen; + UINTN DateStrLen; + UINTN BiosPhysicalSizeHexValue; + UINTN BiosPhysicalSizeExponent; + CHAR16 Version[SMBIOS_STRING_MAX_LENGTH]; + CHAR16 Vendor[SMBIOS_STRING_MAX_LENGTH]; + CHAR16 ReleaseDate[SMBIOS_STRING_MAX_LENGTH]; + EFI_STRING VersionPtr; + EFI_STRING VendorPtr; + EFI_STRING ReleaseDatePtr; + EFI_STATUS Status; + STRING_REF TokenToGet; + STRING_REF TokenToUpdate; + SMBIOS_TABLE_TYPE0 *SmbiosRecord; + EFI_SMBIOS_HANDLE SmbiosHandle; + EFI_MISC_BIOS_VENDOR *ForType0InputData; + UINT32 BiosVersion; + + BiosPhysicalSizeHexValue = 0x0; + BiosPhysicalSizeExponent = 0x0; + ForType0InputData = (EFI_MISC_BIOS_VENDOR *)RecordData; + + // + // First check for invalid parameters. + // + if (RecordData == NULL) { + return EFI_INVALID_PARAMETER; + } + // + // Now update the BiosPhysicalSize + // + BiosPhysicalSizeHexValue = PcdGet32 (PcdFlashAreaSize); + Status= GetValueExponentBase2 ( + &BiosPhysicalSizeHexValue, + &BiosPhysicalSizeExponent + ); + if(Status == EFI_SUCCESS){ + ForType0InputData->BiosPhysicalDeviceSize.Value = (UINT16)BiosPhysicalSizeHexValue; + ForType0InputData->BiosPhysicalDeviceSize.Exponent = (UINT16)BiosPhysicalSizeExponent; + } + // + // Update BIOS Vendor from PCD + // + AsciiStrToUnicodeStr ((const CHAR8 *)PcdGetPtr (PcdFirmwareVendor), Vendor); + if (StrLen (Vendor) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_VENDOR); + HiiSetString (mHiiHandle, TokenToUpdate, Vendor, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_BIOS_VENDOR); + VendorPtr = SmbiosMiscGetString (TokenToGet); + + VendorStrLen = StrLen(VendorPtr); + if (VendorStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + // + // Update BIOS Version from PCD + // + BiosVersion = PcdGet32 (PcdFirmwareRevision); + UnicodeSPrint (Version, sizeof (Version), L"%d", BiosVersion); + if (StrLen (Version) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_VERSION); + HiiSetString (mHiiHandle, TokenToUpdate, Version, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_BIOS_VERSION); + VersionPtr = SmbiosMiscGetString (TokenToGet); + VerStrLen = StrLen(VersionPtr); + if (VerStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + // + // Update BIOS Releason Date from PCD + // + AsciiStrToUnicodeStr ((const CHAR8 *)PcdGetPtr (PcdSMBIOSBiosReleaseDate), ReleaseDate); + if (StrLen (ReleaseDate) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_RELEASE_DATE); + HiiSetString (mHiiHandle, TokenToUpdate, ReleaseDate, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_BIOS_RELEASE_DATE); + ReleaseDatePtr = SmbiosMiscGetString (TokenToGet); + DateStrLen = StrLen(ReleaseDatePtr); + if (DateStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + + // + // Two zeros following the last string. + // + SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE0) + VendorStrLen + 1 + VerStrLen + 1 + DateStrLen + 1 + 1); + + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_BIOS_INFORMATION; + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE0); + + // + // Make handle chosen by smbios protocol.add automatically. + // + SmbiosRecord->Hdr.Handle = 0; + + // + // Vendor will be the 1st optional string following the formatted structure. + // + SmbiosRecord->Vendor = 1; + + // + // Version will be the 2nd optional string following the formatted structure. + // + SmbiosRecord->BiosVersion = 2; + SmbiosRecord->BiosSegment = PcdGet16 (PcdSMBIOSBiosStartAddress); + + // + // ReleaseDate will be the 3rd optional string following the formatted structure. + // + SmbiosRecord->BiosReleaseDate = 3; + SmbiosRecord->BiosSize = (UINT8)(Base2ToByteWith64KUnit(&ForType0InputData->BiosPhysicalDeviceSize) - 1); + *(UINT64 *)&SmbiosRecord->BiosCharacteristics = PcdGet64 (PcdSMBIOSBiosChar); + // + // CharacterExtensionBytes also store in ForType0InputData->BiosCharacteristics1 later two bytes to save size. + // + SmbiosRecord->BIOSCharacteristicsExtensionBytes[0] = PcdGet8 (PcdSMBIOSBiosCharEx1); + SmbiosRecord->BIOSCharacteristicsExtensionBytes[1] = PcdGet8 (PcdSMBIOSBiosCharEx2); + + SmbiosRecord->SystemBiosMajorRelease = ForType0InputData->BiosMajorRelease; + SmbiosRecord->SystemBiosMinorRelease = ForType0InputData->BiosMinorRelease; + SmbiosRecord->EmbeddedControllerFirmwareMajorRelease = ForType0InputData->BiosEmbeddedFirmwareMajorRelease; + SmbiosRecord->EmbeddedControllerFirmwareMinorRelease = ForType0InputData->BiosEmbeddedFirmwareMinorRelease; + + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1); + UnicodeStrToAsciiStr(VendorPtr, OptionalStrStart); + UnicodeStrToAsciiStr(VersionPtr, OptionalStrStart + VendorStrLen + 1); + UnicodeStrToAsciiStr(ReleaseDatePtr, OptionalStrStart + VendorStrLen + 1 + VerStrLen + 1); + + // + // Now we have got the full smbios record, call smbios protocol to add this record. + // + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios-> Add( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord + ); + + FreePool(SmbiosRecord); + + // + // Free the memory allocated before + // + FreePool (VersionPtr); + FreePool (VendorPtr); + FreePool (ReleaseDatePtr); + + return Status; +} diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBootInformationData.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBootInformationData.c new file mode 100644 index 0000000000..a1d6fb8019 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBootInformationData.c @@ -0,0 +1,37 @@ +/** @file + Static data of Boot information. Boot information is Misc for subclass type 26, SMBIOS type 32. + + Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" + +// +// Static (possibly build generated) Bios Vendor data. SMBIOS TYPE 32 +// +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE32, MiscBootInfoStatus) = { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE32), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + { // Reserved[6] + 0, + 0, + 0, + 0, + 0, + 0 + }, + BootInformationStatusNoError ///< BootStatus +}; diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBootInformationFunction.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBootInformationFunction.c new file mode 100644 index 0000000000..368489aac9 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscBootInformationFunction.c @@ -0,0 +1,69 @@ +/** @file + Boot information boot time changes for SMBIOS type 32. + + Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" + +/** + This function makes boot time changes to the contents of the + MiscBootInformation (Type 32). + + @param RecordData Pointer to copy of RecordData from the Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ + +MISC_SMBIOS_TABLE_FUNCTION(MiscBootInfoStatus) +{ + EFI_STATUS Status; + EFI_SMBIOS_HANDLE SmbiosHandle; + SMBIOS_TABLE_TYPE32 *SmbiosRecord; + + // + // First check for invalid parameters. + // + if (RecordData == NULL) { + return EFI_INVALID_PARAMETER; + } + + DEBUG ((EFI_D_INFO, "(MiscBootInfoStatus) Entry.\n")); + // + // Two zeros following the last string. + // + SmbiosRecord = AllocatePool(sizeof(SMBIOS_TABLE_TYPE32) + 1 + 1); + if (SmbiosRecord == NULL) { + DEBUG((EFI_D_ERROR, "(Type32) SmbiosRecord is NULL\n")); + return EFI_OUT_OF_RESOURCES; + } + ZeroMem(SmbiosRecord, sizeof(SMBIOS_TABLE_TYPE32) + 1 + 1); + CopyMem(SmbiosRecord, RecordData, sizeof(SMBIOS_TABLE_TYPE32)); + + // + // Now we have got the full smbios record, call smbios protocol to add this record. + // + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios->Add ( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord + ); + FreePool(SmbiosRecord); + + return Status; +} diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscChassisManufacturer.uni b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscChassisManufacturer.uni new file mode 100644 index 0000000000..979d22d986 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscChassisManufacturer.uni @@ -0,0 +1,25 @@ +// /** @file +// Chassis information. +// +// Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// **/ + + +/=# + +#langdef en-US "English" + +#string STR_MISC_CHASSIS_MANUFACTURER #language en-US "Intel Corporation" +#string STR_MISC_CHASSIS_VERSION #language en-US "0.1" +#string STR_MISC_CHASSIS_SERIAL_NUMBER #language en-US "serial#" +#string STR_MISC_CHASSIS_ASSET_TAG #language en-US "Asset Tag" +#string STR_MISC_CHASSIS_SKU_NUMBER #language en-US "Asset Tag" diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscChassisManufacturerData.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscChassisManufacturerData.c new file mode 100644 index 0000000000..da335827f6 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscChassisManufacturerData.c @@ -0,0 +1,50 @@ +/** @file + Static data is Chassis Manufacturer information. + Chassis Manufacturer information is Misc for subclass type 5, SMBIOS type 3. + + Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" + +// +// Static (possibly build generated) Chassis Manufacturer data. +// +MISC_SMBIOS_TABLE_DATA(EFI_MISC_CHASSIS_MANUFACTURER_DATA, MiscChassisManufacturer) += { + STRING_TOKEN(STR_MISC_CHASSIS_MANUFACTURER), // ChassisManufactrurer + STRING_TOKEN(STR_MISC_CHASSIS_VERSION), // ChassisVersion + STRING_TOKEN(STR_MISC_CHASSIS_SERIAL_NUMBER), // ChassisSerialNumber + STRING_TOKEN(STR_MISC_CHASSIS_ASSET_TAG), // ChassisAssetTag + { // ChassisTypeStatus + EfiMiscChassisTypeHandHeld, // ChassisType + 0, // ChassisLockPresent + 0 // Reserved + }, + EfiChassisStateSafe, // ChassisBootupState + EfiChassisStateSafe, // ChassisPowerSupplyState + EfiChassisStateOther, // ChassisThermalState + EfiChassisSecurityStatusOther, // ChassisSecurityState + 0, // ChassisOemDefined + 0, // ChassisHeight + 0, // ChassisNumberPowerCords + 0, // ChassisElementCount + 0, // ChassisElementRecordLength + { // ChassisElements + {0, 0, 0}, // ChassisElementType + 0, // ChassisElementStructure + EfiBaseBoardTypeUnknown, // ChassisBaseBoard + 0, // ChassisElementMinimum + 0 // ChassisElementMaximum + }, +}; diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscChassisManufacturerFunction.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscChassisManufacturerFunction.c new file mode 100644 index 0000000000..60d7270b50 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscChassisManufacturerFunction.c @@ -0,0 +1,211 @@ +/** @file + Chassis manufacturer information boot time changes for SMBIOS type 3. + + Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" +#include + +/** + Get the chassis type through the PlatformInfoProtocol. + + @retval UINT8 The chassis type. + +**/ +UINT8 +GetChassisType ( + VOID + ) +{ + EFI_PLATFORM_INFO_HOB *PlatformInfoHob; + + PlatformInfoHob = PcdGetPtr (PcdPlatformInfo); + + if ( NULL != PlatformInfoHob) { + if (PlatformInfoHob->PlatformFlavor == FlavorMobile) { + return MiscChassisTypeLapTop; + } else if (PlatformInfoHob->PlatformFlavor == FlavorDesktop) { + return MiscChassisTypeDeskTop; + } else if (PlatformInfoHob->PlatformFlavor == FlavorTablet) { + return MiscChassisTypeHandHeld; + } + } + + return MiscChassisTypeLapTop; +} + +/** + This function makes boot time changes to the contents of the + MiscChassisManufacturer (Type 3). + + @param RecordData Pointer to copy of RecordData from the Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +MISC_SMBIOS_TABLE_FUNCTION(MiscChassisManufacturer) +{ + CHAR8 *OptionalStrStart; + UINTN ManuStrLen; + UINTN VerStrLen; + UINTN AssertTagStrLen; + UINTN SerialNumStrLen; + EFI_STATUS Status; + CHAR16 Manufacturer[SMBIOS_STRING_MAX_LENGTH]; + CHAR16 Version[SMBIOS_STRING_MAX_LENGTH]; + CHAR16 SerialNumber[SMBIOS_STRING_MAX_LENGTH]; + CHAR16 AssertTag[SMBIOS_STRING_MAX_LENGTH]; + EFI_STRING ManufacturerPtr; + EFI_STRING VersionPtr; + EFI_STRING SerialNumberPtr; + EFI_STRING AssertTagPtr; + STRING_REF TokenToGet; + STRING_REF TokenToUpdate; + EFI_SMBIOS_HANDLE SmbiosHandle; + SMBIOS_TABLE_TYPE3 *SmbiosRecord; + EFI_MISC_CHASSIS_MANUFACTURER *ForType3InputData; + + ForType3InputData = (EFI_MISC_CHASSIS_MANUFACTURER *)RecordData; + + // + // First check for invalid parameters. + // + if (RecordData == NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // Update strings from PCD + // + AsciiStrToUnicodeStr ((const CHAR8 *)PcdGetPtr(PcdSMBIOSChassisManufacturer), Manufacturer); + if (StrLen (Manufacturer) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_CHASSIS_MANUFACTURER); + HiiSetString (mHiiHandle, TokenToUpdate, Manufacturer, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_MANUFACTURER); + ManufacturerPtr = SmbiosMiscGetString (TokenToGet); + ManuStrLen = StrLen(ManufacturerPtr); + if (ManuStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + AsciiStrToUnicodeStr ((const CHAR8 *)PcdGetPtr(PcdSMBIOSChassisVersion), Version); + if (StrLen (Version) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_CHASSIS_VERSION); + HiiSetString (mHiiHandle, TokenToUpdate, Version, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_VERSION); + VersionPtr = SmbiosMiscGetString (TokenToGet); + VerStrLen = StrLen(VersionPtr); + if (VerStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + AsciiStrToUnicodeStr ((const CHAR8 *)PcdGetPtr(PcdSMBIOSChassisSerialNumber), SerialNumber); + if (StrLen (SerialNumber) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_CHASSIS_SERIAL_NUMBER); + HiiSetString (mHiiHandle, TokenToUpdate, SerialNumber, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_SERIAL_NUMBER); + SerialNumberPtr = SmbiosMiscGetString (TokenToGet); + SerialNumStrLen = StrLen(SerialNumberPtr); + if (SerialNumStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + AsciiStrToUnicodeStr ((const CHAR8 *)PcdGetPtr(PcdSMBIOSChassisAssetTag), AssertTag); + if (StrLen (AssertTag) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_CHASSIS_ASSET_TAG); + HiiSetString (mHiiHandle, TokenToUpdate, AssertTag, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_ASSET_TAG); + AssertTagPtr = SmbiosMiscGetString (TokenToGet); + AssertTagStrLen = StrLen(AssertTagPtr); + if (AssertTagStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + // + // Two zeros following the last string. + // + SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE3) + ManuStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + AssertTagStrLen + 1 + 1); + + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE; + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE3); + + // + // Make handle chosen by smbios protocol.add automatically. + // + SmbiosRecord->Hdr.Handle = 0; + + // + // Manu will be the 1st optional string following the formatted structure. + // + SmbiosRecord->Manufacturer = 1; + SmbiosRecord->Type = GetChassisType (); + + // + // Version will be the 2nd optional string following the formatted structure. + // + SmbiosRecord->Version = 2; + + // + // SerialNumber will be the 3rd optional string following the formatted structure. + // + SmbiosRecord->SerialNumber = 3; + + // + // AssertTag will be the 4th optional string following the formatted structure. + // + SmbiosRecord->AssetTag = 4; + SmbiosRecord->BootupState = PcdGet8 (PcdSMBIOSChassisBootupState); + SmbiosRecord->PowerSupplyState = PcdGet8 (PcdSMBIOSChassisPowerSupplyState); + SmbiosRecord->ThermalState = (UINT8)ForType3InputData->ChassisThermalState; + SmbiosRecord->SecurityStatus = PcdGet8 (PcdSMBIOSChassisSecurityState); + *(UINT32 *)&SmbiosRecord->OemDefined = PcdGet32 (PcdSMBIOSChassisOemDefined); + SmbiosRecord->Height = PcdGet8 (PcdSMBIOSChassisHeight); + SmbiosRecord->NumberofPowerCords = PcdGet8 (PcdSMBIOSChassisNumberPowerCords); + SmbiosRecord->ContainedElementCount = PcdGet8 (PcdSMBIOSChassisElementCount); + SmbiosRecord->ContainedElementRecordLength = PcdGet8 (PcdSMBIOSChassisElementRecordLength); + + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1); + UnicodeStrToAsciiStr(ManufacturerPtr, OptionalStrStart); + UnicodeStrToAsciiStr(VersionPtr, OptionalStrStart + ManuStrLen + 1); + UnicodeStrToAsciiStr(SerialNumberPtr, OptionalStrStart + ManuStrLen + 1 + VerStrLen + 1); + UnicodeStrToAsciiStr(AssertTagPtr, OptionalStrStart + ManuStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1); + + // + // Now we have got the full smbios record, call smbios protocol to add this record. + // + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios-> Add( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord + ); + + FreePool(SmbiosRecord); + // + // Free the memory allocated before + // + FreePool (ManufacturerPtr); + FreePool (VersionPtr); + FreePool (SerialNumberPtr); + FreePool (AssertTagPtr); + + return Status; +} diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscMemoryDevice.uni b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscMemoryDevice.uni new file mode 100644 index 0000000000..c46a096e06 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscMemoryDevice.uni @@ -0,0 +1,32 @@ +// /** @file +// Memory Device +// Misc. subclass type 17. +// SMBIOS type 17. +// +// Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// **/ + + +/=# + +#langdef en-US "English" + +#string STR_MISC_MEM_DEV_LOCATOR_0 #language en-US "MODULE 0" +#string STR_MISC_MEM_DEV_LOCATOR_1 #language en-US "MODULE 1" +#string STR_MISC_MEM_DEV_LOCATOR0 #language en-US "DIMM 0" +#string STR_MISC_MEM_DEV_LOCATOR1 #language en-US "DIMM 1" +#string STR_MISC_MEM_BANK_LOCATOR0 #language en-US "BANK 0" +#string STR_MISC_MEM_BANK_LOCATOR1 #language en-US "BANK 1" +#string STR_MISC_MEM_MANUFACTURER #language en-US "Macronix" +#string STR_MISC_MEM_SERIAL_NO #language en-US " " +#string STR_MISC_MEM_ASSET_TAG #language en-US " " +#string STR_MISC_MEM_PART_NUMBER #language en-US " " diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscMemoryDeviceData.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscMemoryDeviceData.c new file mode 100644 index 0000000000..21d5148bbd --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscMemoryDeviceData.c @@ -0,0 +1,38 @@ +/** @file + Memory Device is Misc for subclass type 17, SMBIOS type 17. + + Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" + +MISC_SMBIOS_TABLE_DATA(EFI_MEMORY_ARRAY_LINK_DATA, MiscMemoryDevice) = { + STRING_TOKEN (STR_MISC_MEM_DEV_LOCATOR0), // Memory Device locator + STRING_TOKEN (STR_MISC_MEM_BANK_LOCATOR0), // Memory Bank Locator + STRING_TOKEN (STR_MISC_MEM_MANUFACTURER), // Memory manufacturer + STRING_TOKEN (STR_MISC_MEM_SERIAL_NO), // Memory serial Number + STRING_TOKEN (STR_MISC_MEM_ASSET_TAG), // Memory Asset Tag + STRING_TOKEN (STR_MISC_MEM_PART_NUMBER), // Memory Part Number + 0, // Memory Array Link + 0, // Memory SubArray link + 0, // UINT16 MemoryTotalWidth + 0, // UINT16 MemoryDatawidth + 0, // Memory Device Size + EfiMemoryFormFactorDip, // Memory Form Factor + 2, // UINT8 Memory Device type + EfiMemoryTypeDram, // Memory Type + 0, // Memory Type Detail + 0, // Memory Speed + 0 // Memory State + +}; diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscMemoryDeviceFunction.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscMemoryDeviceFunction.c new file mode 100644 index 0000000000..f0784d2a5c --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscMemoryDeviceFunction.c @@ -0,0 +1,308 @@ +/** @file + Memory Device is Misc for subclass type 17, SMBIOS type 17. + + Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" +#include +#include + +#define FREQ_800 0x00 +#define FREQ_1066 0x01 +#define FREQ_1333 0x02 +#define FREQ_1600 0x03 + +#define MAX_SOCKETS 2 +#define EfiMemoryTypeDdr3 0x18 + +enum { + DDRType_DDR3 = 0, + DDRType_DDR3L = 1, + DDRType_DDR3U = 2, + DDRType_DDR3All = 3, + DDRType_LPDDR2 = 4, + DDRType_LPDDR3 = 5, + DDRType_DDR4 = 6 +}; + +typedef struct { + EFI_PHYSICAL_ADDRESS MemoryArrayStartAddress; + EFI_PHYSICAL_ADDRESS MemoryArrayEndAddress; + EFI_INTER_LINK_DATA PhysicalMemoryArrayLink; + UINT16 MemoryArrayPartitionWidth; +} EFI_MEMORY_ARRAY_START_ADDRESS; + +/** + This function makes boot time changes to the contents of the + MiscBiosVendor (Type 0). + + @param RecordData Pointer to copy of RecordData from the Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +VOID +GetType16Hndl ( + IN EFI_SMBIOS_PROTOCOL *Smbios, + OUT EFI_SMBIOS_HANDLE *Handle + ) +{ + EFI_STATUS Status; + EFI_SMBIOS_TYPE RecordType; + EFI_SMBIOS_TABLE_HEADER *Buffer; + + *Handle = 0; + RecordType = EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY; + + Status = Smbios->GetNext ( + Smbios, + Handle, + &RecordType, + &Buffer, + NULL + ); + if (!EFI_ERROR (Status)) { + return; + } + *Handle = 0xFFFF; +} + +MISC_SMBIOS_TABLE_FUNCTION( MiscMemoryDevice ) +{ + CHAR8 *OptionalStrStart; + UINTN MemDeviceStrLen; + UINTN MemBankLocatorStrLen; + UINTN MemManufacturerStrLen; + UINTN MemSerialNumberStrLen; + UINTN MemAssetTagStrLen; + UINTN MemPartNumberStrLen; + CHAR16 *MemDevice; + CHAR16 *MemBankLocator; + CHAR16 *MemManufacturer; + CHAR16 *MemSerialNumber; + CHAR16 *MemAssetTag; + CHAR16 *MemPartNumber; + EFI_STATUS Status; + STRING_REF TokenToGet; + SMBIOS_TABLE_TYPE17 *SmbiosRecord; + EFI_SMBIOS_HANDLE SmbiosHandle; + EFI_MEMORY_ARRAY_LINK_DATA *ForType17InputData; + UINT16 DdrFreq=0; + UINT16 Type16Handle=0; + MEM_INFO_PROTOCOL *MemInfoHob; + UINT8 MemoryType; + UINT8 Dimm; + UINT8 NumSlots; + STRING_REF DevLocator[] = { + STRING_TOKEN(STR_MISC_MEM_DEV_LOCATOR0), STRING_TOKEN(STR_MISC_MEM_DEV_LOCATOR1) + }; + STRING_REF BankLocator[] = { + STRING_TOKEN(STR_MISC_MEM_BANK_LOCATOR0), STRING_TOKEN(STR_MISC_MEM_BANK_LOCATOR1) + }; + + // + // First check for invalid parameters. + // + if (RecordData == NULL) { + return EFI_INVALID_PARAMETER; + } + ForType17InputData = (EFI_MEMORY_ARRAY_LINK_DATA *)RecordData; + + // + // Get Memory size parameters for each rank from the chipset registers + // + Status = gBS->LocateProtocol ( + &gMemInfoProtocolGuid, + NULL, + (void **) &MemInfoHob + ); + ASSERT_EFI_ERROR (Status); + + NumSlots = (UINT8)(MAX_SOCKETS); + + // + // Memory Freq + // + switch (MemInfoHob->MemInfoData.ddrFreq) { + case FREQ_800: + DdrFreq = 800; + break; + case FREQ_1066: + DdrFreq = 1066; + break; + case FREQ_1333: + DdrFreq = 1333; + break; + case FREQ_1600: + DdrFreq = 1600; + break; + default: + DdrFreq = 0; + break; + } + + // + // Memory Type + // + switch (MemInfoHob->MemInfoData.ddrType) { + case DDRType_LPDDR2: + MemoryType = EfiMemoryTypeDdr2; + break; + case DDRType_DDR3: + case DDRType_DDR3L: + case DDRType_DDR3U: + case DDRType_LPDDR3: + MemoryType = EfiMemoryTypeDdr3; + break; + default: + MemoryType = EfiMemoryTypeUnknown; + break; + } + + for (Dimm = 0; Dimm < NumSlots; Dimm++) { + // + // Memory Device Locator + // + TokenToGet = DevLocator[Dimm]; + MemDevice = SmbiosMiscGetString (TokenToGet); + MemDeviceStrLen = StrLen(MemDevice); + if (MemDeviceStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + TokenToGet = DevLocator[Dimm]; + MemDevice = SmbiosMiscGetString (TokenToGet); + MemDeviceStrLen = StrLen(MemDevice); + if (MemDeviceStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + // + // Memory Bank Locator + // + TokenToGet = BankLocator[Dimm]; + MemBankLocator = SmbiosMiscGetString (TokenToGet); + MemBankLocatorStrLen = StrLen(MemBankLocator); + if (MemBankLocatorStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + // + // Memory Manufacturer + // + TokenToGet = STRING_TOKEN (STR_MISC_MEM_MANUFACTURER); + MemManufacturer = SmbiosMiscGetString (TokenToGet); + MemManufacturerStrLen = StrLen(MemManufacturer); + if (MemManufacturerStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + // + // Memory Serial Number + // + TokenToGet = STRING_TOKEN (STR_MISC_MEM_SERIAL_NO); + MemSerialNumber = SmbiosMiscGetString (TokenToGet); + MemSerialNumberStrLen = StrLen(MemSerialNumber); + if (MemSerialNumberStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + // + // Memory Asset Tag Number + // + TokenToGet = STRING_TOKEN (STR_MISC_MEM_ASSET_TAG); + MemAssetTag = SmbiosMiscGetString (TokenToGet); + MemAssetTagStrLen = StrLen(MemAssetTag); + if (MemAssetTagStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + // + // Memory Part Number + // + TokenToGet = STRING_TOKEN (STR_MISC_MEM_PART_NUMBER); + MemPartNumber = SmbiosMiscGetString (TokenToGet); + MemPartNumberStrLen = StrLen(MemPartNumber); + if (MemPartNumberStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + // + // Two zeros following the last string. + // + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE17) + MemDeviceStrLen + 1 + MemBankLocatorStrLen + 1 + MemManufacturerStrLen + 1 + MemSerialNumberStrLen + 1 + MemAssetTagStrLen+1 + MemPartNumberStrLen + 1 + 1); + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE17) + MemDeviceStrLen + 1 + MemBankLocatorStrLen + 1 + MemManufacturerStrLen + 1 + MemSerialNumberStrLen + 1 + MemAssetTagStrLen+1 + MemPartNumberStrLen + 1 + 1); + + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_MEMORY_DEVICE; + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE17); + + // + // Make handle chosen by smbios protocol.add automatically. + // + SmbiosRecord->Hdr.Handle = 0; + + // + // Memory Array Handle will be the 3rd optional string following the formatted structure. + // + GetType16Hndl( Smbios, &Type16Handle); + SmbiosRecord->MemoryArrayHandle = Type16Handle; + + // + // Memory Size + // + if ((MemInfoHob->MemInfoData.dimmSize[Dimm])!=0) { + SmbiosRecord->TotalWidth = 32; + SmbiosRecord->DataWidth = 32; + SmbiosRecord->Size = MemInfoHob->MemInfoData.dimmSize[Dimm]; + SmbiosRecord->Speed = DdrFreq; + SmbiosRecord->ConfiguredMemoryClockSpeed = DdrFreq; + SmbiosRecord->FormFactor = EfiMemoryFormFactorDimm; + } + + SmbiosRecord->DeviceSet =(UINT8) ForType17InputData->MemoryDeviceSet; + SmbiosRecord->DeviceLocator= 1; + SmbiosRecord->BankLocator = 2; + + SmbiosRecord->Manufacturer = 3; + SmbiosRecord->SerialNumber= 4; + SmbiosRecord->AssetTag= 5; + SmbiosRecord->PartNumber= 6; + SmbiosRecord->Attributes = (UINT8) ForType17InputData->MemoryState; + SmbiosRecord->MemoryType = MemoryType; + + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1); + UnicodeStrToAsciiStr(MemDevice, OptionalStrStart); + UnicodeStrToAsciiStr(MemBankLocator, OptionalStrStart + MemDeviceStrLen + 1); + UnicodeStrToAsciiStr(MemManufacturer, OptionalStrStart + MemDeviceStrLen + 1 + MemBankLocatorStrLen + 1); + UnicodeStrToAsciiStr(MemSerialNumber, OptionalStrStart + MemDeviceStrLen + 1 + MemBankLocatorStrLen + 1 + MemManufacturerStrLen + 1); + UnicodeStrToAsciiStr(MemAssetTag, OptionalStrStart + MemDeviceStrLen + 1 + MemBankLocatorStrLen + 1 + MemManufacturerStrLen + 1 + MemSerialNumberStrLen + 1); + UnicodeStrToAsciiStr(MemPartNumber, OptionalStrStart + MemDeviceStrLen + 1 + MemBankLocatorStrLen + 1 + MemManufacturerStrLen + 1 + MemSerialNumberStrLen + 1+ MemAssetTagStrLen+1 ); + + // + // Now we have got the full smbios record, call smbios protocol to add this record. + // + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios->Add ( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord + ); + FreePool(SmbiosRecord); + } + + return Status; +} diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscNumberOfInstallableLanguagesData.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscNumberOfInstallableLanguagesData.c new file mode 100644 index 0000000000..bac400cf82 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscNumberOfInstallableLanguagesData.c @@ -0,0 +1,49 @@ +/** @file + Static data of the Number of installable languages information. + Number of installable languages information is Misc for subclass type 11, SMBIOS type 13. + + Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" + +// +// Static (possibly build generated) Bios Vendor data. +// +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE13, NumberOfInstallableLanguages) = { + { // Hdr + EFI_SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE13), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + 1, // NumberOfInstallableLanguages + 1, // LanguageFlags + { // Reserve[15] + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0 + }, + SMBIOS_MISC_STRING_1, // CurrentLanguage +}; diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscNumberOfInstallableLanguagesFunction.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscNumberOfInstallableLanguagesFunction.c new file mode 100644 index 0000000000..e49f214b96 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscNumberOfInstallableLanguagesFunction.c @@ -0,0 +1,91 @@ +/** @file + This driver parses the mSmbiosMiscDataTable structure and reports + any generated data. + + Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" + +/** + This function makes boot time changes to the contents of the + MiscNumberOfInstallableLanguages (Type 13). + + @param RecordData Pointer to copy of RecordData from the Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +MISC_SMBIOS_TABLE_FUNCTION(NumberOfInstallableLanguages) +{ + CHAR8 *OptionalStrStart; + UINTN StringNumber; + UINTN StringLength; + EFI_STATUS Status; + EFI_SMBIOS_HANDLE SmbiosHandle; + SMBIOS_TABLE_TYPE13 *SmbiosRecord; + SMBIOS_TABLE_TYPE13_STRINGS SmbiosTableType13Strings; + CHAR16 *StrBufferStart; + CHAR16 *StrBufferPtr; + + // + // First check for invalid parameters. + // + if (RecordData == NULL) { + return EFI_INVALID_PARAMETER; + } + + DEBUG ((EFI_D_INFO, "(NumberOfInstallableLanguages) Entry.\n")); + ZeroMem (&SmbiosTableType13Strings, sizeof(SMBIOS_TABLE_TYPE13_STRINGS)); + StringNumber = 0; + StringLength = 0; + StrBufferStart = AllocateZeroPool (1 * SMBIOS_STRING_MAX_LENGTH * sizeof(CHAR16)); + StrBufferPtr = StrBufferStart; + + // + // Initialize SMBIOS Tables Type13 strings + // + SmbiosStrInit ((CHAR16 **) &SmbiosTableType13Strings.CurrentLanguages, SMBIOS_MISC_INSTALLED_LANGUAGE_ENGLISH, &StrBufferPtr, &StringNumber, &StringLength); + + // + // Two zeros following the last string. + // + SmbiosRecord = AllocatePool (sizeof(SMBIOS_TABLE_TYPE13) + StringLength + StringNumber + 1); + if (SmbiosRecord == NULL) { + return EFI_OUT_OF_RESOURCES; + } + ZeroMem (SmbiosRecord, sizeof(SMBIOS_TABLE_TYPE13) + StringLength + StringNumber + 1); + CopyMem(SmbiosRecord, RecordData, sizeof(SMBIOS_TABLE_TYPE13)); + + // + // Update SMBIOS Tables Type13 strings + // + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1); + SmbiosStringsUpdate ((CHAR16 **) &SmbiosTableType13Strings, OptionalStrStart, StringNumber); + + // + // Now we have got the full smbios record, call smbios protocol to add this record. + // + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios->Add ( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord + ); + FreePool(SmbiosRecord); + FreePool(StrBufferStart); + return Status; +} diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemString.uni b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemString.uni new file mode 100644 index 0000000000..19a72cf35e --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemString.uni @@ -0,0 +1,22 @@ +// /** @file +// Language Information. +// +// Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// **/ + + +/=# + +#langdef en-US "English" +#string STR_INTEL_ETK_VER #language en-US "ETK_VER_02.01" +#string STR_INTEL_ETK_VER_FOR_ROEM #language en-US "ETK_VER_02.00" +#string STR_MISC_OEM_EN_US #language en-US "English (US)" diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemStringData.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemStringData.c new file mode 100644 index 0000000000..0cc6893b33 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemStringData.c @@ -0,0 +1,28 @@ +/** @file + Static data of OEM String information. + OEM String information is Misc for subclass type 9, SMBIOS type 11. + + Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" + +// +// Static (possibly build generated) Bios Vendor data. +// +MISC_SMBIOS_TABLE_DATA(EFI_MISC_OEM_STRING, MiscOemString) = { + STRING_TOKEN(STR_INTEL_ETK_VER) +}; +MISC_SMBIOS_TABLE_DATA(EFI_MISC_OEM_STRING_DATA, OemString) = { + STRING_TOKEN(STR_MISC_OEM_EN_US) +}; diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemStringFunction.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemStringFunction.c new file mode 100644 index 0000000000..7f365455d6 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemStringFunction.c @@ -0,0 +1,84 @@ +/** @file + Boot information boot time changes for SMBIOS type 11. + + Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" + +/** + This function makes boot time changes to the contents of the + MiscOemString (Type 11). + + @param RecordData Pointer to copy of RecordData from the Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +MISC_SMBIOS_TABLE_FUNCTION(OemString) +{ + UINTN OemStrLen; + CHAR8 *OptionalStrStart; + EFI_STATUS Status; + EFI_STRING OemStr; + STRING_REF TokenToGet; + EFI_SMBIOS_HANDLE SmbiosHandle; + SMBIOS_TABLE_TYPE11 *SmbiosRecord; + + // + // First check for invalid parameters. + // + if (RecordData == NULL) { + return EFI_INVALID_PARAMETER; + } + + TokenToGet = STRING_TOKEN (STR_MISC_OEM_EN_US); + OemStr = SmbiosMiscGetString (TokenToGet); + OemStrLen = StrLen(OemStr); + if (OemStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + // + // Two zeros following the last string. + // + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE11) + OemStrLen + 1 + 1); + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE11) + OemStrLen + 1 + 1); + + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_OEM_STRINGS; + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE11); + + // + // Make handle chosen by smbios protocol.add automatically. + // + SmbiosRecord->Hdr.Handle = 0; + SmbiosRecord->StringCount = 1; + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1); + UnicodeStrToAsciiStr(OemStr, OptionalStrStart); + + // + // Now we have got the full smbios record, call smbios protocol to add this record. + // + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios->Add ( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord + ); + FreePool(SmbiosRecord); + + return Status; +} diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemType0x90.uni b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemType0x90.uni new file mode 100644 index 0000000000..ab2f1472bb --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemType0x90.uni @@ -0,0 +1,28 @@ +// /** @file +// Firmware Version Information +// SMBIOS type 0x90. +// +// Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// **/ + + +/=# +#langdef en-US "English" + +#string STR_MISC_SEC_VERSION #language en-US "NA" +#string STR_MISC_UCODE_VERSION #language en-US "NA" +#string STR_MISC_GOP_VERSION #language en-US "NA" +#string STR_MISC_PROCESSOR_STEPPING #language en-US "NA" + + + + diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemType0x90Data.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemType0x90Data.c new file mode 100644 index 0000000000..9792efb2eb --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemType0x90Data.c @@ -0,0 +1,32 @@ +/** @file + This file contains the Misc Oem Data (SMBIOS data type 0x90) + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" + +// +// Static (possibly build generated) Oem data. +// +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE90, MiscOemType0x90) = { + { // Hdr + EFI_SMBIOS_TYPE_FIRMWARE_VERSION_INFO, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE90), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_STRING_1, // SECVersion + SMBIOS_MISC_STRING_2, // uCodeVersion + SMBIOS_MISC_STRING_3, // GOPVersion + SMBIOS_MISC_STRING_4 // CpuStepping +}; diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemType0x90Function.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemType0x90Function.c new file mode 100644 index 0000000000..aa050dd046 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemType0x90Function.c @@ -0,0 +1,436 @@ +/** @file + The function that processes the Smbios data type 0x88 before they are submitted to Data Hub. + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" +#include +#include +#include + +VOID +GetCPUStepping ( + CHAR16 *Stepping +) +{ + CHAR16 Buffer[40]; + + UINT16 FamilyId; + UINT8 Model; + UINT8 SteppingId; + UINT8 ProcessorType; + + + EfiCpuVersion (&FamilyId, &Model, &SteppingId, &ProcessorType); + //we need raw Model data + Model = Model & 0xf; + // + //Family/Model/Step + UnicodeSPrint (Buffer, sizeof (Buffer), L"%d/%d/%d", FamilyId, Model, SteppingId); + StrCpy (Stepping, Buffer); + return; +} + +EFI_STATUS +SearchChildHandle ( + EFI_HANDLE Father, + EFI_HANDLE *Child + ) +{ + EFI_STATUS Status; + UINTN HandleIndex; + EFI_GUID **ProtocolGuidArray = NULL; + UINTN ArrayCount; + UINTN ProtocolIndex; + UINTN OpenInfoCount; + UINTN OpenInfoIndex; + EFI_OPEN_PROTOCOL_INFORMATION_ENTRY *OpenInfo = NULL; + UINTN mHandleCount; + EFI_HANDLE *mHandleBuffer= NULL; + + // + // Retrieve the list of all handles from the handle database + // + Status = gBS->LocateHandleBuffer ( + AllHandles, + NULL, + NULL, + &mHandleCount, + &mHandleBuffer + ); + + for (HandleIndex = 0; HandleIndex < mHandleCount; HandleIndex++) { + // + // Retrieve the list of all the protocols on each handle + // + Status = gBS->ProtocolsPerHandle ( + mHandleBuffer[HandleIndex], + &ProtocolGuidArray, + &ArrayCount + ); + if (!EFI_ERROR (Status)) { + for (ProtocolIndex = 0; ProtocolIndex < ArrayCount; ProtocolIndex++) { + Status = gBS->OpenProtocolInformation ( + mHandleBuffer[HandleIndex], + ProtocolGuidArray[ProtocolIndex], + &OpenInfo, + &OpenInfoCount + ); + + if (!EFI_ERROR (Status)) { + for (OpenInfoIndex = 0; OpenInfoIndex < OpenInfoCount; OpenInfoIndex++) { + if (OpenInfo[OpenInfoIndex].AgentHandle == Father) { + if ((OpenInfo[OpenInfoIndex].Attributes & EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) == EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) { + *Child = mHandleBuffer[HandleIndex]; + Status = EFI_SUCCESS; + goto TryReturn; + } + } + } + Status = EFI_NOT_FOUND; + } + } + if (OpenInfo != NULL) { + FreePool(OpenInfo); + OpenInfo = NULL; + } + } + if (ProtocolGuidArray != NULL) { + FreePool (ProtocolGuidArray); + ProtocolGuidArray = NULL; + } + } +TryReturn: + if (OpenInfo != NULL) { + FreePool (OpenInfo); + OpenInfo = NULL; + } + if (ProtocolGuidArray != NULL) { + FreePool(ProtocolGuidArray); + ProtocolGuidArray = NULL; + } + if (mHandleBuffer != NULL) { + FreePool (mHandleBuffer); + mHandleBuffer = NULL; + } + + return Status; +} + +EFI_STATUS +JudgeHandleIsPCIDevice ( + EFI_HANDLE Handle, + UINT8 Device, + UINT8 Funs + ) +{ + EFI_STATUS Status; + EFI_DEVICE_PATH *DPath; + EFI_DEVICE_PATH *DevicePath; + + Status = gBS->HandleProtocol ( + Handle, + &gEfiDevicePathProtocolGuid, + (VOID **) &DPath + ); + if (!EFI_ERROR (Status)) { + DevicePath = DPath; + while (!IsDevicePathEnd(DPath)) { + if ((DPath->Type == HARDWARE_DEVICE_PATH) && (DPath->SubType == HW_PCI_DP)) { + PCI_DEVICE_PATH *PCIPath; + PCIPath = (PCI_DEVICE_PATH*) DPath; + DPath = NextDevicePathNode(DPath); + + if (IsDevicePathEnd(DPath) && (PCIPath->Device == Device) && (PCIPath->Function == Funs)) { + return EFI_SUCCESS; + } + } else { + DPath = NextDevicePathNode(DPath); + } + } + } + + return EFI_UNSUPPORTED; +} + +VOID +GetDriverName( + EFI_HANDLE Handle, + CHAR16* GOPVer +) +{ + EFI_DRIVER_BINDING_PROTOCOL *BindHandle = NULL; + EFI_STATUS Status; + UINT32 Version; + UINT16 *Ptr; + CHAR16 Buffer[40]; + Status = gBS->OpenProtocol( + Handle, + &gEfiDriverBindingProtocolGuid, + (VOID**)&BindHandle, + NULL, + NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL + ); + + if (EFI_ERROR(Status)) + { + StrCpy (GOPVer, L"NA"); + return; + } + + Version = BindHandle->Version; + Ptr = (UINT16*)&Version; + UnicodeSPrint(Buffer, sizeof (Buffer), L"8.0.%04d", *(Ptr)); + StrCpy (GOPVer, Buffer); + + return; +} + +VOID +GetGOPDriverName( + CHAR16* GOPVer +) +{ + UINTN HandleCount; + EFI_HANDLE *Handles= NULL; + UINTN Index; + EFI_STATUS Status; + EFI_HANDLE Child = 0; + + Status = gBS->LocateHandleBuffer( + ByProtocol, + &gEfiDriverBindingProtocolGuid, + NULL, + &HandleCount, + &Handles + ); + + for (Index = 0; Index < HandleCount ; Index++) + { + Status = SearchChildHandle(Handles[Index], &Child); + if(!EFI_ERROR(Status)) + { + Status = JudgeHandleIsPCIDevice(Child, 0x02, 0x00); + if(!EFI_ERROR(Status)) + { + // DEBUG ((EFI_D_ERROR, "JudgeHandleIsPCIDevice ok \n")); + GetDriverName(Handles[Index], GOPVer); + return; + } + } + } + StrCpy (GOPVer, L"NA"); + return; +} + +VOID +GetUcodeVersion( + CHAR16 *uCodeVer +) +{ + UINT32 MicroCodeVersion; + CHAR16 Buffer[40]; + // + // Microcode Revision + // + EfiWriteMsr (EFI_MSR_IA32_BIOS_SIGN_ID, 0); + EfiCpuid (EFI_CPUID_VERSION_INFO, NULL); + MicroCodeVersion = (UINT32) RShiftU64 (EfiReadMsr (EFI_MSR_IA32_BIOS_SIGN_ID), 32); + UnicodeSPrint (Buffer, sizeof (Buffer), L"%x", MicroCodeVersion); + StrCpy (uCodeVer, Buffer); + return; +} + +VOID +GetSeCVersion( + CHAR16 *SECVer +) +{ + StrCpy (SECVer, L"NA"); + return; +} + +EFI_STATUS +EFIAPI +AddSmbiosT0x90Callback ( + IN EFI_EVENT Event, + IN VOID *Context + ) + /*++ + +Routine Description: + + Publish the smbios OEM type 0x90. + +Arguments: + + Event - Event whose notification function is being invoked (gEfiDxeSmmReadyToLockProtocolGuid). + Context - Pointer to the notification functions context, which is implementation dependent. + +Returns: + + None + +--*/ +{ + EFI_STATUS Status; + SMBIOS_TABLE_TYPE90 *SmbiosRecord; + EFI_SMBIOS_HANDLE SmbiosHandle; + SMBIOS_TABLE_TYPE90_STRINGS SmbiosTableType90Strings; + CHAR16 *SECVer; + CHAR16 *uCodeVer; + CHAR16 *GOPVer; + CHAR16 *Stepping; + CHAR8 *OptionalStrStart; + UINTN StringNumber; + UINTN StringLength; + CHAR16 *StrBufferStart; + CHAR16 *StrBufferPtr; + EFI_SMBIOS_PROTOCOL *SmbiosProtocol; + + DEBUG ((EFI_D_INFO, "Executing SMBIOS T0x90 callback.\n")); + + gBS->CloseEvent (Event); // Unload this event. + + // + // First check for invalid parameters. + // + if (Context == NULL) { + return EFI_INVALID_PARAMETER; + } + + ZeroMem (&SmbiosTableType90Strings, sizeof(SMBIOS_TABLE_TYPE90_STRINGS)); + StringNumber = 0; + StringLength = 0; + SECVer = AllocateZeroPool (0x20); + uCodeVer = AllocateZeroPool (0x10); + GOPVer = AllocateZeroPool (0x18); + Stepping = AllocateZeroPool (0x18); + ASSERT(SECVer != NULL); + ASSERT(uCodeVer != NULL); + ASSERT(GOPVer != NULL); + ASSERT(Stepping != NULL); + + StrBufferStart = AllocateZeroPool (4 * SMBIOS_STRING_MAX_LENGTH * sizeof(CHAR16)); + StrBufferPtr = StrBufferStart; + + Status = gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, NULL, (VOID *) &SmbiosProtocol); + ASSERT_EFI_ERROR (Status); + + GetSeCVersion (SECVer); + GetUcodeVersion (uCodeVer); + GetGOPDriverName (GOPVer); + GetCPUStepping (Stepping); + + DEBUG((EFI_D_INFO, "SECVerStr = %s, uCodeVerStr = %s, GOPStr = %s, SteppingStr = %s\n", SECVer, uCodeVer, GOPVer, Stepping)); + + SmbiosStrInit (&SmbiosTableType90Strings.SECVersion, SECVer, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType90Strings.uCodeVersion, uCodeVer, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType90Strings.GOPVersion, GOPVer, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType90Strings.CpuStepping, Stepping, &StrBufferPtr, &StringNumber, &StringLength); + + // + // Two zeros following the last string. + // + SmbiosRecord = AllocatePool (sizeof(SMBIOS_TABLE_TYPE90) + StringLength + StringNumber + 1); + if (SmbiosRecord == NULL) { + FreePool(SECVer); + FreePool(uCodeVer); + FreePool(GOPVer); + FreePool(Stepping); + FreePool(StrBufferStart); + return EFI_OUT_OF_RESOURCES; + } + ZeroMem(SmbiosRecord, sizeof(SMBIOS_TABLE_TYPE90) + StringLength + StringNumber + 1); + CopyMem(SmbiosRecord, Context, sizeof(SMBIOS_TABLE_TYPE90)); + + // + // Update SMBIOS Tables type90 strings + // + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1); + SmbiosStringsUpdate ((CHAR16 **) &SmbiosTableType90Strings, OptionalStrStart, StringNumber); + + // + // Now we have got the full smbios record, call smbios protocol to add this record. + // + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = SmbiosProtocol->Add ( + SmbiosProtocol, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord + ); + + FreePool(SECVer); + FreePool(uCodeVer); + FreePool(GOPVer); + FreePool(Stepping); + FreePool(SmbiosRecord); + FreePool(StrBufferStart); + return Status; +} + +/** + This function makes boot time changes to the contents of the + MiscOemType0x90 (Type 0x90). + + @param RecordData Pointer to copy of RecordData from the Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +MISC_SMBIOS_TABLE_FUNCTION(MiscOemType0x90) +{ + EFI_STATUS Status; + static BOOLEAN CallbackIsInstalledT0x90 = FALSE; + VOID *AddSmbiosT0x90CallbackNotifyReg; + EFI_EVENT AddSmbiosT0x90CallbackEvent; + + // + // This callback will create a OEM Type 0x90 record. + // + if (CallbackIsInstalledT0x90 == FALSE) { + CallbackIsInstalledT0x90 = TRUE; // Prevent more than 1 callback. + DEBUG ((EFI_D_INFO, "Create Smbios T0x90 callback.\n")); + + // + // gEfiDxeSmmReadyToLockProtocolGuid is ready + // + Status = gBS->CreateEvent ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + AddSmbiosT0x90Callback, + RecordData, + &AddSmbiosT0x90CallbackEvent + ); + + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return Status; + } + + Status = gBS->RegisterProtocolNotify ( + &gEfiDxeSmmReadyToLockProtocolGuid, + AddSmbiosT0x90CallbackEvent, + &AddSmbiosT0x90CallbackNotifyReg + ); + + return Status; + } + + return EFI_SUCCESS; +} diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemType0x94.uni b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemType0x94.uni new file mode 100644 index 0000000000..aa1f304a3f --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemType0x94.uni @@ -0,0 +1,39 @@ +// /** @file +// Firmware Version Information. +// SMBIOS type 0x94. +// +// Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// **/ + + +/=# +#langdef en-US "English" + +#string STR_MISC_PMIC_VERSION #language en-US "NA" +#string STR_MISC_TOUCH_VERSION #language en-US "NA" +#string STR_MISC_PROCESSOR_MICROCODE_VALUE #language en-US "NA" +#string STR_MISC_ULPMC_FW_VALUE #language en-US "NA" +#string STR_MISC_PUNIT_FW_VALUE #language en-US "NA" +#string STR_MISC_PMC_FW_VALUE #language en-US "NA" +#string STR_MISC_SOC_VALUE #language en-US "NA" +#string STR_MISC_MRC_VERSION_VALUE #language en-US "NA" +#string STR_MISC_BOARD_ID_VALUE #language en-US "NA" +#string STR_MISC_FAB_ID_VALUE #language en-US "NA" +#string STR_MISC_CPU_FLAVOR_VALUE #language en-US "NA" +#string STR_MISC_SECURE_BOOT #language en-US "NA" +#string STR_MISC_BOOT_MODE #language en-US "NA" +#string STR_MISC_SPEED_STEP #language en-US "NA" +#string STR_MISC_CPU_TURBO #language en-US "NA" +#string STR_MISC_CSTATE #language en-US "NA" +#string STR_MISC_GFX_TURBO #language en-US "NA" +#string STR_MISC_S0IX_VALUE #language en-US "NA" +#string STR_MISC_RC6_VALUE #language en-US "NA" diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemType0x94Data.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemType0x94Data.c new file mode 100644 index 0000000000..1bf2ff4b00 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemType0x94Data.c @@ -0,0 +1,47 @@ +/** @file + This file contains the Misc version Data (SMBIOS data type 0x94) + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" + +// +// Static (possibly build generated) Oem data. +// +MISC_SMBIOS_TABLE_DATA(EFI_MISC_OEM_TYPE_0x94, MiscOemType0x94) = { + +STRING_TOKEN (STR_MISC_GOP_VERSION), +STRING_TOKEN (STR_MISC_SEC_VERSION), +STRING_TOKEN (STR_MISC_MRC_VERSION_VALUE), +STRING_TOKEN (STR_MISC_UCODE_VERSION), +STRING_TOKEN (STR_MISC_PUNIT_FW_VALUE), +STRING_TOKEN (STR_MISC_PMC_FW_VALUE), +STRING_TOKEN (STR_MISC_ULPMC_FW_VALUE), +STRING_TOKEN (STR_MISC_SOC_VALUE), +STRING_TOKEN (STR_MISC_BOARD_ID_VALUE), +STRING_TOKEN (STR_MISC_FAB_ID_VALUE), +STRING_TOKEN (STR_MISC_CPU_FLAVOR_VALUE), +STRING_TOKEN (STR_MISC_BIOS_VERSION), +STRING_TOKEN (STR_MISC_PMIC_VERSION), +STRING_TOKEN (STR_MISC_TOUCH_VERSION), +STRING_TOKEN (STR_MISC_SECURE_BOOT), +STRING_TOKEN (STR_MISC_BOOT_MODE), +STRING_TOKEN (STR_MISC_SPEED_STEP), +STRING_TOKEN (STR_MISC_CPU_TURBO), +STRING_TOKEN (STR_MISC_CSTATE), +STRING_TOKEN (STR_MISC_GFX_TURBO), +STRING_TOKEN (STR_MISC_S0IX_VALUE), +STRING_TOKEN (STR_MISC_RC6_VALUE), + +}; diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemType0x94Function.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemType0x94Function.c new file mode 100644 index 0000000000..ddc57bdb19 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOemType0x94Function.c @@ -0,0 +1,1036 @@ +/** @file + The function that processes the Smbios data type 0x94. + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "Valleyview.h" +#include "VlvAccess.h" +#include "PchAccess.h" +#include "PchCommonDefinitions.h" +#include + +typedef struct { + UINT8 RevId; + CHAR8 String[16]; +} SB_REV; + +SB_REV SBRevisionTable[] = { + {V_PCH_LPC_RID_A0, "(A0 Stepping)"}, + {V_PCH_LPC_RID_A1, "(A1 Stepping)"}, + {V_PCH_LPC_RID_A2, "(A2 Stepping)"}, + {V_PCH_LPC_RID_A3, "(A3 Stepping)"}, + {V_PCH_LPC_RID_A4, "(A4 Stepping)"}, + {V_PCH_LPC_RID_A5, "(A5 Stepping)"}, + {V_PCH_LPC_RID_A6, "(A6 Stepping)"}, + {V_PCH_LPC_RID_A7, "(A7 Stepping)"}, + {V_PCH_LPC_RID_B0, "(B0 Stepping)"}, + {V_PCH_LPC_RID_B1, "(B1 Stepping)"}, + {V_PCH_LPC_RID_B2, "(B2 Stepping)"}, + {V_PCH_LPC_RID_B3, "(B3 Stepping)"}, + {V_PCH_LPC_RID_B4, "(B4 Stepping)"}, + {V_PCH_LPC_RID_B5, "(B5 Stepping)"}, + {V_PCH_LPC_RID_B6, "(B6 Stepping)"}, + {V_PCH_LPC_RID_B7, "(B7 Stepping)"}, + {V_PCH_LPC_RID_C0, "(C0 Stepping)"}, + {V_PCH_LPC_RID_C1, "(C1 Stepping)"}, + {V_PCH_LPC_RID_C2, "(C2 Stepping)"}, + {V_PCH_LPC_RID_C3, "(C3 Stepping)"}, + {V_PCH_LPC_RID_C4, "(C4 Stepping)"}, + {V_PCH_LPC_RID_C5, "(C5 Stepping)"}, + {V_PCH_LPC_RID_C6, "(C6 Stepping)"}, + {V_PCH_LPC_RID_C7, "(C7 Stepping)"}, + {V_PCH_LPC_RID_D0, "(D0 Stepping)"}, + {V_PCH_LPC_RID_D1, "(D1 Stepping)"}, + {V_PCH_LPC_RID_D2, "(D2 Stepping)"}, + {V_PCH_LPC_RID_D3, "(D3 Stepping)"}, + {V_PCH_LPC_RID_D4, "(D4 Stepping)"}, + {V_PCH_LPC_RID_D5, "(D5 Stepping)"}, + {V_PCH_LPC_RID_D6, "(D6 Stepping)"}, + {V_PCH_LPC_RID_D7, "(D7 Stepping)"} +}; + +#define LEFT_JUSTIFY 0x01 +#define PREFIX_SIGN 0x02 +#define PREFIX_BLANK 0x04 +#define COMMA_TYPE 0x08 +#define LONG_TYPE 0x10 +#define PREFIX_ZERO 0x20 + +#define ICH_REG_REV 0x08 +#define MSR_IA32_PLATFORM_ID 0x17 +#define CHARACTER_NUMBER_FOR_VALUE 30 + +UINT8 ReadBuffer[20]; //Version report length +UINT8 WriteBuffer[22] = {0x40,0x01,0x14,0x00,0x06,0x51,0x02,0x07,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; //Version request + +UINTN +EfiValueToString ( + IN OUT CHAR16 *Buffer, + IN INT64 Value, + IN UINTN Flags, + IN UINTN Width + ) +/*++ + +Routine Description: + + VSPrint worker function that prints a Value as a decimal number in Buffer + +Arguments: + + Buffer - Location to place ascii decimal number string of Value. + + Value - Decimal value to convert to a string in Buffer. + + Flags - Flags to use in printing decimal string, see file header for details. + + Width - Width of hex value. + +Returns: + + Number of characters printed. + +--*/ +{ + CHAR16 TempBuffer[CHARACTER_NUMBER_FOR_VALUE]; + CHAR16 *TempStr; + CHAR16 *BufferPtr; + UINTN Count; + UINTN ValueCharNum; + UINTN Remainder; + CHAR16 Prefix; + UINTN Index; + BOOLEAN ValueIsNegative; + UINT64 TempValue; + + TempStr = TempBuffer; + BufferPtr = Buffer; + Count = 0; + ValueCharNum = 0; + ValueIsNegative = FALSE; + + if (Width > CHARACTER_NUMBER_FOR_VALUE - 1) { + Width = CHARACTER_NUMBER_FOR_VALUE - 1; + } + + if (Value < 0) { + Value = -Value; + ValueIsNegative = TRUE; + } + + do { + TempValue = Value; + Value = (INT64)DivU64x32 ((UINT64)Value, 10); + Remainder = (UINTN)((UINT64)TempValue - 10 * Value); + *(TempStr++) = (CHAR16)(Remainder + '0'); + ValueCharNum++; + Count++; + if ((Flags & COMMA_TYPE) == COMMA_TYPE) { + if (ValueCharNum % 3 == 0 && Value != 0) { + *(TempStr++) = ','; + Count++; + } + } + } while (Value != 0); + + if (ValueIsNegative) { + *(TempStr++) = '-'; + Count++; + } + + if ((Flags & PREFIX_ZERO) && !ValueIsNegative) { + Prefix = '0'; + } else { + Prefix = ' '; + } + + Index = Count; + if (!(Flags & LEFT_JUSTIFY)) { + for (; Index < Width; Index++) { + *(TempStr++) = Prefix; + } + } + + // + // Reverse temp string into Buffer. + // + if (Width > 0 && (UINTN) (TempStr - TempBuffer) > Width) { + TempStr = TempBuffer + Width; + } + Index = 0; + while (TempStr != TempBuffer) { + *(BufferPtr++) = *(--TempStr); + Index++; + } + + *BufferPtr = 0; + + return Index; +} + +static CHAR16 mHexStr[] = { L'0', L'1', L'2', L'3', L'4', L'5', L'6', L'7', + L'8', L'9', L'A', L'B', L'C', L'D', L'E', L'F' }; + +UINTN +EfiValueToHexStr ( + IN OUT CHAR16 *Buffer, + IN UINT64 Value, + IN UINTN Flags, + IN UINTN Width + ) +/*++ + +Routine Description: + + VSPrint worker function that prints a Value as a hex number in Buffer + +Arguments: + + Buffer - Location to place ascii hex string of Value. + + Value - Hex value to convert to a string in Buffer. + + Flags - Flags to use in printing Hex string, see file header for details. + + Width - Width of hex value. + +Returns: + + Number of characters printed. + +--*/ +{ + CHAR16 TempBuffer[CHARACTER_NUMBER_FOR_VALUE]; + CHAR16 *TempStr; + CHAR16 Prefix; + CHAR16 *BufferPtr; + UINTN Count; + UINTN Index; + + TempStr = TempBuffer; + BufferPtr = Buffer; + + // + // Count starts at one since we will null terminate. Each iteration of the + // loop picks off one nibble. Oh yea TempStr ends up backwards + // + Count = 0; + + if (Width > CHARACTER_NUMBER_FOR_VALUE - 1) { + Width = CHARACTER_NUMBER_FOR_VALUE - 1; + } + + do { + Index = ((UINTN)Value & 0xf); + *(TempStr++) = mHexStr[Index]; + Value = RShiftU64 (Value, 4); + Count++; + } while (Value != 0); + + if (Flags & PREFIX_ZERO) { + Prefix = '0'; + } else { + Prefix = ' '; + } + + Index = Count; + if (!(Flags & LEFT_JUSTIFY)) { + for (; Index < Width; Index++) { + *(TempStr++) = Prefix; + } + } + + // + // Reverse temp string into Buffer. + // + if (Width > 0 && (UINTN) (TempStr - TempBuffer) > Width) { + TempStr = TempBuffer + Width; + } + Index = 0; + while (TempStr != TempBuffer) { + *(BufferPtr++) = *(--TempStr); + Index++; + } + + *BufferPtr = 0; + return Index; +} + +CHAR16 * +StrMacToString ( + OUT CHAR16 *String, + IN EFI_MAC_ADDRESS *MacAddr, + IN UINT32 AddrSize + ) +/*++ + +Routine Description: + Converts MAC address to Unicode string. + The value is 64-bit and the resulting string will be 12 + digit hex number in pairs of digits separated by dashes. + +Arguments: + String - string that will contain the value + Val - value to convert + +--*/ +// GC_TODO: function comment is missing 'Returns:' +// GC_TODO: MacAddr - add argument and description to function comment +// GC_TODO: AddrSize - add argument and description to function comment +{ + UINT32 i; + + for (i = 0; i < AddrSize; i++) { + + EfiValueToHexStr ( + &String[2 * i], + MacAddr->Addr[i] & 0xFF, + PREFIX_ZERO, + 2 + ); + } + + // + // Terminate the string. + // + String[2 * AddrSize] = L'\0'; + + return String; +} + +EFI_STATUS +TJudgeHandleIsPCIDevice ( + EFI_HANDLE Handle, + UINT8 Device, + UINT8 Funs +) +{ + EFI_STATUS Status; + EFI_DEVICE_PATH *DPath; + EFI_DEVICE_PATH *DevicePath; + + Status = gBS->HandleProtocol ( + Handle, + &gEfiDevicePathProtocolGuid, + (VOID **) &DPath + ); + if (!EFI_ERROR (Status)) { + DevicePath = DPath; + while (!IsDevicePathEnd (DPath)) { + if ((DPath->Type == HARDWARE_DEVICE_PATH) && (DPath->SubType == HW_PCI_DP)) { + PCI_DEVICE_PATH *PCIPath; + PCIPath = (PCI_DEVICE_PATH*) DPath; + DPath = NextDevicePathNode(DPath); + if (IsDevicePathEnd(DPath) && (PCIPath->Device == Device) && (PCIPath->Function == Funs)) { + return EFI_SUCCESS; + } + } + else { + DPath = NextDevicePathNode(DPath); + } + } + } + + return EFI_UNSUPPORTED; +} + +EFI_STATUS +TSearchChildHandle ( + EFI_HANDLE Father, + EFI_HANDLE *Child + ) +{ + EFI_STATUS Status; + UINTN HandleIndex; + EFI_GUID **ProtocolGuidArray = NULL; + UINTN ArrayCount; + UINTN ProtocolIndex; + UINTN OpenInfoCount; + UINTN OpenInfoIndex; + EFI_OPEN_PROTOCOL_INFORMATION_ENTRY *OpenInfo = NULL; + UINTN mHandleCount; + EFI_HANDLE *mHandleBuffer= NULL; + + // + // Retrieve the list of all handles from the handle database + // + Status = gBS->LocateHandleBuffer ( + AllHandles, + NULL, + NULL, + &mHandleCount, + &mHandleBuffer + ); + + for (HandleIndex = 0; HandleIndex < mHandleCount; HandleIndex++) { + // + // Retrieve the list of all the protocols on each handle + // + Status = gBS->ProtocolsPerHandle ( + mHandleBuffer[HandleIndex], + &ProtocolGuidArray, + &ArrayCount + ); + if (!EFI_ERROR (Status)) { + for (ProtocolIndex = 0; ProtocolIndex < ArrayCount; ProtocolIndex++) { + Status = gBS->OpenProtocolInformation ( + mHandleBuffer[HandleIndex], + ProtocolGuidArray[ProtocolIndex], + &OpenInfo, + &OpenInfoCount + ); + if (!EFI_ERROR (Status)) { + for (OpenInfoIndex = 0; OpenInfoIndex < OpenInfoCount; OpenInfoIndex++) { + if (OpenInfo[OpenInfoIndex].AgentHandle == Father) { + if ((OpenInfo[OpenInfoIndex].Attributes & EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) == EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) { + *Child = mHandleBuffer[HandleIndex]; + Status = EFI_SUCCESS; + goto TryReturn; + } + } + } + Status = EFI_NOT_FOUND; + } + } + if (OpenInfo != NULL) { + FreePool(OpenInfo); + OpenInfo = NULL; + } + } + FreePool (ProtocolGuidArray); + ProtocolGuidArray = NULL; + } +TryReturn: + if (OpenInfo != NULL) { + FreePool (OpenInfo); + OpenInfo = NULL; + } + if (ProtocolGuidArray != NULL) { + FreePool(ProtocolGuidArray); + ProtocolGuidArray = NULL; + } + if (mHandleBuffer != NULL) { + FreePool (mHandleBuffer); + mHandleBuffer = NULL; + } + + return Status; +} + +EFI_STATUS +TGetDriverName ( + EFI_HANDLE Handle, + CHAR16 *Name +) +{ + EFI_DRIVER_BINDING_PROTOCOL *BindHandle = NULL; + EFI_STATUS Status; + UINT32 Version; + UINT16 *Ptr; + Status = gBS->OpenProtocol ( + Handle, + &gEfiDriverBindingProtocolGuid, + (VOID **) &BindHandle, + NULL, + NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL + ); + + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + Version = BindHandle->Version; + Ptr = (UINT16*)&Version; + UnicodeSPrint(Name, 40, L"%d.%d.%d", Version >> 24 , (Version >>16)& 0x0f ,*(Ptr)); + + return EFI_SUCCESS; +} + +EFI_STATUS +TGetGOPDriverName ( + CHAR16 *Name +) +{ + UINTN HandleCount; + EFI_HANDLE *Handles= NULL; + UINTN Index; + EFI_STATUS Status; + EFI_HANDLE Child = 0; + + Status = gBS->LocateHandleBuffer( + ByProtocol, + &gEfiDriverBindingProtocolGuid, + NULL, + &HandleCount, + &Handles + ); + for (Index = 0; Index < HandleCount ; Index++) { + Status = TSearchChildHandle(Handles[Index], &Child); + if (!EFI_ERROR (Status)) { + Status = TJudgeHandleIsPCIDevice(Child, 0x02, 0x00); + if (!EFI_ERROR (Status)) { + return TGetDriverName(Handles[Index], Name); + } + } + } + + return EFI_UNSUPPORTED; +} + +EFI_STATUS +TGetTouchFirmwareVersion( + CHAR16 *TouchVerString +) +{ + CHAR16 Buffer[40]; + + UnicodeSPrint (Buffer, sizeof (Buffer), L"NA"); + StrCpy (TouchVerString, Buffer); + + return EFI_SUCCESS; +} + +EFI_STATUS +UpdatePlatformInformation ( + CHAR16 *SECVer, CHAR16 *uCodeVer, CHAR16 *GOPVer, CHAR16 *MrcVer, + CHAR16 *PmcVer, CHAR16 *UlpmcVer, CHAR16 *PunitVer, CHAR16 *SocVer, + CHAR16 *BoardVer, CHAR16 *FabVer, CHAR16 *CpuFlavorString, CHAR16 *BiosVer, + CHAR16 *PmicVer, CHAR16 *TouchVer, CHAR16 *SecureBootMode, CHAR16 *BootModeString, + CHAR16 *SpeedStepMode, CHAR16 *MaxCState, CHAR16 *CpuTurbo, CHAR16 *GfxTurbo, + CHAR16 *S0ix, CHAR16 *RC6 +) +{ + UINT32 MicroCodeVersion; + CHAR16 Buffer[SMBIOS_STRING_MAX_LENGTH + 2]; + EFI_STATUS Status; + UINT8 CpuFlavor=0; + EFI_PEI_HOB_POINTERS GuidHob; + EFI_PLATFORM_INFO_HOB *mPlatformInfo=NULL; + UINTN NumHandles; + EFI_HANDLE *HandleBuffer; + UINTN Index; + DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy; + UINTN PciD31F0RegBase; + UINT8 count; + UINT8 Data8; + UINT8 Data8_1; + + CHAR16 Name[40]; + UINT32 MrcVersion; + CHAR16 *Version; + SYSTEM_CONFIGURATION SystemConfiguration; + EFI_BOOT_MODE BootMode; + UINTN VarSize; + EFI_PLATFORM_INFO_HOB *mPlatformInfo; + + Version = AllocateZeroPool (SMBIOS_STRING_MAX_LENGTH + 2); + + // + // Get the System configuration + // + CopyMem (&SystemConfiguration, PcdGetPtr (PcdSystemConfiguration), sizeof(SYSTEM_CONFIGURATION)); + + // + // Get the HOB list. If it is not present, then ASSERT. + // + mPlatformInfo = PcdGetPtr (PcdPlatformInfo); + + GetSeCVersion (SECVer); + Status = GetBiosVersionDateTime (Version, NULL, NULL); + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", Version); + FreePool(Version); + StrCpy (BiosVer, Buffer); + + Status = TGetGOPDriverName(Name); + + if(!EFI_ERROR(Status)) + { + StrCpy (GOPVer, Name); + } + + // + //CpuFlavor + // + //CHV + //CHV-DC Tablet 000 + //CHV-QC Notebook 001 + //CHV-QC Desktop 010 + + //CPU flavor + CpuFlavor = RShiftU64 (EfiReadMsr (MSR_IA32_PLATFORM_ID), 50) & 0x07; + + switch(CpuFlavor){ + case 0x0: + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s (%01x)", L"CHV-DC Tablet", CpuFlavor); + StrCpy (CpuFlavorString, Buffer); + break; + case 0x01: +#if (TABLET_PF_ENABLE == 1) + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s (%01x)", L"CHV-QC Tablet", CpuFlavor); +#else + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s (%01x)", L"CHV-QC Notebook", CpuFlavor); +#endif + StrCpy (CpuFlavorString, Buffer); + break; + case 0x02: + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s (%01x)", L"CHV-QC Desktop", CpuFlavor); + StrCpy (CpuFlavorString, Buffer); + break; + case 0x03: + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s (%01x)", L"CHV-QC Notebook", CpuFlavor); + StrCpy (CpuFlavorString, Buffer); + break; + default: + UnicodeSPrint (Buffer, sizeof (Buffer), L"%s (%01x)", L"Unknown CPU", CpuFlavor); + StrCpy (CpuFlavorString, Buffer); + break; + } + + if ( NULL != mPlatformInfo) { + // + // Board Id + // + UnicodeSPrint (Buffer, sizeof (Buffer), L"%x", mPlatformInfo->BoardId); + StrCpy (BoardVer, Buffer); + + // + // FAB ID + // + UnicodeSPrint (Buffer, sizeof (Buffer), L"%x", mPlatformInfo->FABID); + StrCpy (FabVer, Buffer); + } + + // + //Update MRC Version + // + MrcVersion = MmioRead32 (MmPciAddress (0, 0, 0, 0, 0xF0)); + MrcVersion &= 0xffff; + Index = EfiValueToString (Buffer, MrcVersion/100, PREFIX_ZERO, 0); + StrCat (Buffer, L"."); + EfiValueToString (Buffer + Index + 1, (MrcVersion%100)/10, PREFIX_ZERO, 0); + EfiValueToString (Buffer + Index + 2, (MrcVersion%100)%10, PREFIX_ZERO, 0); + StrCpy (MrcVer, Buffer); + + // + //Update Soc Version + // + + // + // Retrieve all instances of PCH Platform Policy protocol + // + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gDxePchPlatformPolicyProtocolGuid, + NULL, + &NumHandles, + &HandleBuffer + ); + if (!EFI_ERROR (Status)) { + // + // Find the matching PCH Policy protocol + // + for (Index = 0; Index < NumHandles; Index++) { + Status = gBS->HandleProtocol ( + HandleBuffer[Index], + &gDxePchPlatformPolicyProtocolGuid, + &PchPlatformPolicy + ); + if (!EFI_ERROR (Status)) { + PciD31F0RegBase = MmPciAddress ( + 0, + PchPlatformPolicy->BusNumber, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC, + 0 + ); + + Data8 = MmioRead8 (PciD31F0RegBase + R_PCH_LPC_RID_CC) & B_PCH_LPC_RID_STEPPING_MASK; + count = sizeof (SBRevisionTable) / sizeof (SBRevisionTable[0]); + for (Index = 0; Index < count; Index++) { + if(Data8 == SBRevisionTable[Index].RevId) { + UnicodeSPrint (Buffer, sizeof (Buffer), L"%02x %a", Data8, SBRevisionTable[Index].String); + StrCpy (SocVer, Buffer); + break; + } + } + break; + } + } + } + + // + // Microcode Revision + // + EfiWriteMsr (EFI_MSR_IA32_BIOS_SIGN_ID, 0); + EfiCpuid (EFI_CPUID_VERSION_INFO, NULL); + MicroCodeVersion = (UINT32) RShiftU64 (EfiReadMsr (EFI_MSR_IA32_BIOS_SIGN_ID), 32); + UnicodeSPrint (Buffer, sizeof (Buffer), L"%x", MicroCodeVersion); + StrCpy (uCodeVer, Buffer); + + // + //Secure boot + // + Data8 = SystemConfiguration.SecureBoot; + UnicodeSPrint (Buffer, sizeof(Buffer), L"%x", Data8); + StrCpy (SecureBootMode, Buffer); + + // + //Bootmode + // + BootMode = GetBootModeHob(); + UnicodeSPrint (Buffer, sizeof(Buffer), L"%x", BootMode); + StrCpy (BootModeString, Buffer); + + // + //SpeedStep + // + Data8 = SystemConfiguration.EnableGv; + UnicodeSPrint (Buffer, sizeof(Buffer), L"%x", Data8); + StrCpy (SpeedStepMode, Buffer); + + // + //CPU Turbo + // + Data8 = SystemConfiguration.TurboModeEnable; + UnicodeSPrint (Buffer, sizeof(Buffer), L"%x", Data8); + StrCpy (CpuTurbo, Buffer); + + // + //CState + // + Data8 = SystemConfiguration.MaxCState; + UnicodeSPrint (Buffer, sizeof(Buffer), L"%x", Data8); + StrCpy (MaxCState, Buffer); + + // + //GFX Turbo + // + Data8 = SystemConfiguration.IgdTurboEnabled; + UnicodeSPrint (Buffer, sizeof(Buffer), L"%x", Data8); + StrCpy (GfxTurbo, Buffer); + + // + //S0ix + // + Data8 = SystemConfiguration.S0ix; + UnicodeSPrint (Buffer, sizeof(Buffer), L"%x", Data8); + StrCpy (S0ix, Buffer); + + // + //RC6 + // + Data8 = SystemConfiguration.EnableRenderStandby; + UnicodeSPrint (Buffer, sizeof(Buffer), L"%x", Data8); + StrCpy (RC6, Buffer); + + // + // Punit Version + // + Data8 = (UINT8) EfiReadMsr (0x667); + UnicodeSPrint (Buffer, sizeof (Buffer), L"0x%x", Data8); + StrCpy (PunitVer, Buffer); + + // + // PMC Version + // + Data8 = (UINT8)((MmioRead32 (PMC_BASE_ADDRESS + R_PCH_PMC_PRSTS)>>16)&0x00FF); + Data8_1 = (UINT8)((MmioRead32 (PMC_BASE_ADDRESS + R_PCH_PMC_PRSTS)>>24)&0x00FF); + UnicodeSPrint (Buffer, sizeof (Buffer), L"0x%X_%X", Data8_1, Data8); + StrCpy (PmcVer, Buffer); + + TGetTouchFirmwareVersion(TouchVer); + + return EFI_SUCCESS; +} + + +EFI_STATUS +EFIAPI +AddSmbiosT0x94Callback ( + IN EFI_EVENT Event, + IN VOID *Context + ) + /*++ + +Routine Description: + + Smbios OEM type 0x94 callback. + +Arguments: + + Event - Event whose notification function is being invoked. + Context - Pointer to the notification functions context, which is implementation dependent. + +Returns: + + None + +--*/ +{ + EFI_STATUS Status; + SMBIOS_TABLE_TYPE94 *SmbiosRecord; + EFI_SMBIOS_HANDLE SmbiosHandle; + SMBIOS_TABLE_TYPE94_STRINGS SmbiosTableType94Strings; + CHAR16 *SECVer; + CHAR16 *uCodeVer; + CHAR16 *GOPVer; + CHAR16 *MrcVer; + CHAR16 *PmcVer; + CHAR16 *UlpmcVer; + CHAR16 *PunitVer; + CHAR16 *SocVer; + CHAR16 *BoardVer; + CHAR16 *FabVer; + CHAR16 *CpuFlavor; + CHAR16 *BiosVer; + CHAR16 *PmicVer; + CHAR16 *TouchVer; + CHAR16 *SecureBootMode; + CHAR16 *BootMode; + CHAR16 *SpeedStepMode; + CHAR16 *MaxCState; + CHAR16 *CpuTurbo; + CHAR16 *GfxTurbo; + CHAR16 *S0ix; + CHAR16 *RC6; + + CHAR8 *OptionalStrStart; + UINTN StringNumber; + UINTN StringLength; + CHAR16 *StrBufferStart; + CHAR16 *StrBufferPtr; + EFI_SMBIOS_PROTOCOL *SmbiosProtocol; + + DEBUG ((EFI_D_INFO, "Executing SMBIOS T0x94 callback.\n")); + + gBS->CloseEvent (Event); // Unload this event. + + // + // First check for invalid parameters. + // + if (Context == NULL) { + return EFI_INVALID_PARAMETER; + } + + ZeroMem (&SmbiosTableType94Strings, sizeof(SMBIOS_TABLE_TYPE94_STRINGS)); + StringNumber = 0; + StringLength = 0; + + SECVer = AllocateZeroPool (SMBIOS_STRING_MAX_LENGTH); + uCodeVer = AllocateZeroPool (SMBIOS_STRING_MAX_LENGTH); + GOPVer = AllocateZeroPool (SMBIOS_STRING_MAX_LENGTH); + MrcVer = AllocateZeroPool (SMBIOS_STRING_MAX_LENGTH); + PmcVer = AllocateZeroPool (0x10); + UlpmcVer = AllocateZeroPool (0x10); + PunitVer = AllocateZeroPool (0x10); + SocVer = AllocateZeroPool (SMBIOS_STRING_MAX_LENGTH); + BoardVer = AllocateZeroPool (0x10); + FabVer = AllocateZeroPool (0x10); + CpuFlavor = AllocateZeroPool (SMBIOS_STRING_MAX_LENGTH); + BiosVer = AllocateZeroPool (SMBIOS_STRING_MAX_LENGTH + 2); + PmicVer = AllocateZeroPool (0x10); + TouchVer = AllocateZeroPool (0x10); + SecureBootMode = AllocateZeroPool (0x10); + BootMode = AllocateZeroPool (0x10); + SpeedStepMode = AllocateZeroPool (0x10); + MaxCState = AllocateZeroPool (0x10); + CpuTurbo = AllocateZeroPool (0x10); + GfxTurbo = AllocateZeroPool (0x10); + S0ix = AllocateZeroPool (0x10); + RC6 = AllocateZeroPool (0x10); + + ASSERT(SECVer != NULL); + ASSERT(uCodeVer != NULL); + ASSERT(GOPVer != NULL); + ASSERT(MrcVer != NULL); + ASSERT(PmcVer != NULL); + ASSERT(UlpmcVer != NULL); + ASSERT(PunitVer != NULL); + ASSERT(SocVer != NULL); + ASSERT(BoardVer != NULL); + ASSERT(FabVer != NULL); + ASSERT(CpuFlavor != NULL); + ASSERT(BiosVer != NULL); + ASSERT(SecureBootMode != NULL); + ASSERT(BootMode != NULL); + ASSERT(SpeedStepMode != NULL); + ASSERT(MaxCState != NULL); + ASSERT(CpuTurbo != NULL); + ASSERT(GfxTurbo != NULL); + ASSERT(S0ix != NULL); + ASSERT(RC6 != NULL); + + StrBufferStart = AllocateZeroPool (22 * SMBIOS_STRING_MAX_LENGTH * sizeof(CHAR16)); + StrBufferPtr = StrBufferStart; + + Status = gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, NULL, (VOID *) &SmbiosProtocol); + ASSERT_EFI_ERROR (Status); + + UpdatePlatformInformation ( + SECVer, uCodeVer, GOPVer, MrcVer, + PmcVer, UlpmcVer, PunitVer, SocVer, + BoardVer, FabVer, CpuFlavor, BiosVer, + PmicVer, TouchVer, SecureBootMode, BootMode, + SpeedStepMode, MaxCState, CpuTurbo, GfxTurbo, + S0ix, RC6 + ); + + SmbiosStrInit (&SmbiosTableType94Strings.SECVersion, SECVer, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType94Strings.uCodeVersion, uCodeVer, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType94Strings.GopVersion, GOPVer, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType94Strings.MRCVersion, MrcVer, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType94Strings.PMCVersion, PmcVer, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType94Strings.ULPMCVersion, UlpmcVer, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType94Strings.PUnitVersion, PunitVer, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType94Strings.SoCVersion, SocVer, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType94Strings.BoardVersion, BoardVer, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType94Strings.FabVersion, FabVer, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType94Strings.CPUFlavor, CpuFlavor, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType94Strings.BiosVersion, BiosVer, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType94Strings.PmicVersion, PmicVer, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType94Strings.TouchVersion, TouchVer, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType94Strings.SecureBoot, SecureBootMode, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType94Strings.BootMode, BootMode, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType94Strings.SpeedStepMode, SpeedStepMode, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType94Strings.MaxCState, MaxCState, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType94Strings.CPUTurboMode, CpuTurbo, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType94Strings.GfxTurbo, GfxTurbo, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType94Strings.S0ix, S0ix, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType94Strings.RC6, RC6, &StrBufferPtr, &StringNumber, &StringLength); + + // + // Two zeros following the last string. + // + SmbiosRecord = AllocatePool (sizeof(SMBIOS_TABLE_TYPE94) + StringLength + StringNumber + 1); + if (SmbiosRecord == NULL) { + FreePool(SECVer); + FreePool(uCodeVer); + FreePool(GOPVer); + FreePool(MrcVer); + FreePool(PmcVer); + FreePool(UlpmcVer); + FreePool(PunitVer); + FreePool(SocVer); + FreePool(BoardVer); + FreePool(FabVer); + FreePool(CpuFlavor); + FreePool(BiosVer); + FreePool(PmicVer); + FreePool(TouchVer); + FreePool(SecureBootMode); + FreePool(BootMode); + FreePool(SpeedStepMode); + FreePool(MaxCState); + FreePool(CpuTurbo); + FreePool(GfxTurbo); + FreePool(S0ix); + FreePool(RC6); + FreePool(SmbiosRecord); + FreePool(StrBufferStart); + return EFI_OUT_OF_RESOURCES; + } + ZeroMem(SmbiosRecord, sizeof(SMBIOS_TABLE_TYPE94) + StringLength + StringNumber + 1); + CopyMem(SmbiosRecord, Context, sizeof(SMBIOS_TABLE_TYPE94)); + + // + // Update SMBIOS Tables type94 strings + // + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1); + SmbiosStringsUpdate ((CHAR16 **) &SmbiosTableType94Strings, OptionalStrStart, StringNumber); + + // + // Now we have got the full smbios record, call smbios protocol to add this record. + // + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = SmbiosProtocol-> Add( + SmbiosProtocol, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord + ); + FreePool(SECVer); + FreePool(uCodeVer); + FreePool(GOPVer); + FreePool(MrcVer); + FreePool(PmcVer); + FreePool(UlpmcVer); + FreePool(PunitVer); + FreePool(SocVer); + FreePool(BoardVer); + FreePool(FabVer); + FreePool(CpuFlavor); + FreePool(BiosVer); + FreePool(PmicVer); + FreePool(TouchVer); + FreePool(SecureBootMode); + FreePool(BootMode); + FreePool(SpeedStepMode); + FreePool(MaxCState); + FreePool(CpuTurbo); + FreePool(GfxTurbo); + FreePool(S0ix); + FreePool(RC6); + FreePool(SmbiosRecord); + FreePool(StrBufferStart); + return EFI_SUCCESS; +} + +/** + This function makes boot time changes to the contents of the + MiscOemType0x94 (Type 0x94). + + @param RecordData Pointer to copy of RecordData from the Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +MISC_SMBIOS_TABLE_FUNCTION(MiscOemType0x94) +{ + EFI_STATUS Status; + EFI_EVENT AddSmbiosT0x94CallbackEvent; + + Status = EfiCreateEventReadyToBootEx ( + TPL_CALLBACK, + AddSmbiosT0x94Callback, + RecordData, + &AddSmbiosT0x94CallbackEvent + ); + + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOnboardDevice.uni b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOnboardDevice.uni new file mode 100644 index 0000000000..94b83244be --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOnboardDevice.uni @@ -0,0 +1,23 @@ +// /** @file +// Onboard device information. +// +// Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// **/ + + +/=# + +#langdef en-US "English" + +#string STR_MISC_ONBOARD_DEVICE_VIDEO #language en-US "Intel(R) ValleyView2 HD Graphics" +#string STR_MISC_ONBOARD_DEVICE_AUDIO #language en-US "Intel(R) HD Audio Device" +#string STR_MISC_ONBOARD_DEVICE_NETWORK #language en-US "" diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOnboardDeviceData.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOnboardDeviceData.c new file mode 100644 index 0000000000..21f76bedc1 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOnboardDeviceData.c @@ -0,0 +1,57 @@ +/** @file + Static data of Onboard device information . + The onboard device information is Misc for subclass type 8, SMBIOS type 10. + + Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" + +// +// Static (possibly build generated) Bios Vendor data. +// +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE10, MiscOnBoardDeviceVideo) = { + { // Hdr + EFI_SMBIOS_TYPE_ONBOARD_DEVICE_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE10), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + { // Device + OnBoardDeviceTypeVideo, ///< DeviceType + SMBIOS_MISC_STRING_1 ///< DescriptionString + } +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE10, MiscOnBoardDeviceEthernet) = { + { // Hdr + EFI_SMBIOS_TYPE_ONBOARD_DEVICE_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE10), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + { // Device + OnBoardDeviceTypeEthernet, ///< DeviceType + SMBIOS_MISC_STRING_1 ///< DescriptionString + } +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE10, MiscOnBoardDeviceSound) = { + { // Hdr + EFI_SMBIOS_TYPE_ONBOARD_DEVICE_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE10), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + { // Device + OnBoardDeviceTypeSound, ///< DeviceType + SMBIOS_MISC_STRING_1 ///< DescriptionString + } +}; diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOnboardDeviceFunction.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOnboardDeviceFunction.c new file mode 100644 index 0000000000..af16fe7617 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscOnboardDeviceFunction.c @@ -0,0 +1,206 @@ +/** @file + Create the device path for the Onboard device. + The Onboard device information is Misc for subclass type 8, SMBIOS type 10. + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" +#include +#include + +EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *gPciRootBridgeIo; + +/** + Get the enabling/disabling setting through PciBridgeIo and return that. + + @param[out] OnBoardDeviceType + +**/ +VOID +GetOnBoardDeviceType ( + UINT8 *OnBoardDeviceType +) +{ + EFI_STATUS Status; + UINT8 Value8; + UINT32 Value32; + UINT64 PciAddress; + + Value8 = 0; + Value32 = 0; + PciAddress = 0; + + Status = gBS->LocateProtocol ( + &gEfiPciRootBridgeIoProtocolGuid, + NULL, + &gPciRootBridgeIo + ); + if (EFI_ERROR(Status)) { + // + // Can't access PciRootBridgeIoProtocol, don't change the default setting. + // + DEBUG ((EFI_D_ERROR, "(SMBIOS TABLE Type10) Don't change the default setting for the OnBoardDeviceType.\n")); + return; + } + + // + // Read PCI registers to set enabling/disabling onboard device + // + switch (*OnBoardDeviceType) { + case OnBoardDeviceTypeVideo: + // + // Read command reg of device 0, function 0, reg 0x52 for onboard device enabled + // + PciAddress = EFI_PCI_ADDRESS (0, 0, 0, 0x52); + gPciRootBridgeIo->Pci.Read ( + gPciRootBridgeIo, + EfiPciWidthUint8, + PciAddress, + 1, + &Value8 + ); + if (Value8 & 0x02) { + *OnBoardDeviceType &= 0x7F; + DEBUG ((EFI_D_ERROR, "(SMBIOS TABLE Type10) OnBoardDevice Video is enabled.\n")); + } else { + *OnBoardDeviceType |= 0x80; + } + break; + + case OnBoardDeviceTypeEthernet: + *OnBoardDeviceType &= 0x7F; + break; + + case OnBoardDeviceTypeSound: + // + // Read command reg of HD Audio, reg 0x04 onboard device enabled + // + PciAddress = EFI_PCI_ADDRESS ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_AZALIA, + PCI_FUNCTION_NUMBER_PCH_AZALIA, + PCI_COMMAND_OFFSET + ); + gPciRootBridgeIo->Pci.Read ( + gPciRootBridgeIo, + EfiPciWidthUint32, + PciAddress, + 1, + &Value32 + ); + if (Value32 != 0xffffffff) { + if ((Value32 & 0x02) || (Value32 & 0x01)) { + *OnBoardDeviceType |= 0x80; + DEBUG ((EFI_D_ERROR, "(SMBIOS TABLE Type10) OnBoardDevice Sound is enabled.\n")); + } else { + *OnBoardDeviceType &= 0x7F; + } + } + break; + } + +} +/** + This function makes boot time changes to the contents of the + MiscOnboardDevice (Type 10). + + @param RecordData Pointer to copy of RecordData from the Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +MISC_SMBIOS_TABLE_FUNCTION(MiscOnBoardDevice) +{ + CHAR8 *OptionalStrStart; + UINTN StringNumber; + UINTN StringLength; + EFI_STATUS Status; + EFI_SMBIOS_HANDLE SmbiosHandle; + SMBIOS_TABLE_TYPE10 *SmbiosRecord; + SMBIOS_TABLE_TYPE10 *ForType10InputData; + SMBIOS_TABLE_TYPE10_STRINGS SmbiosTableType10Strings; + CHAR16 *StrBufferStart; + CHAR16 *StrBufferPtr; + + // + // First check for invalid parameters. + // + if (RecordData == NULL) { + return EFI_INVALID_PARAMETER; + } + + DEBUG ((EFI_D_INFO, "(MiscOnBoardDevice) Entry.\n")); + ZeroMem (&SmbiosTableType10Strings, sizeof(SMBIOS_TABLE_TYPE10_STRINGS)); + StringNumber = 0; + StringLength = 0; + ForType10InputData = (SMBIOS_TABLE_TYPE10 *) RecordData; + StrBufferStart = AllocateZeroPool (1 * SMBIOS_STRING_MAX_LENGTH * sizeof(CHAR16)); + StrBufferPtr = StrBufferStart; + + // + // Initialize SMBIOS Tables Type10 strings + // + switch (ForType10InputData->Device[0].DeviceType & 0x7F) { + case OnBoardDeviceTypeVideo: + SmbiosStrInit (&SmbiosTableType10Strings.DescriptionString, SMBIOS_MISC_ONBOARD_DEVICE_VIDEO, &StrBufferPtr, &StringNumber, &StringLength); + break; + case OnBoardDeviceTypeEthernet: + SmbiosStrInit (&SmbiosTableType10Strings.DescriptionString, SMBIOS_MISC_ONBOARD_DEVICE_ETHERNET, &StrBufferPtr, &StringNumber, &StringLength); + break; + case OnBoardDeviceTypeSound: + SmbiosStrInit (&SmbiosTableType10Strings.DescriptionString, SMBIOS_MISC_ONBOARD_DEVICE_SOUND, &StrBufferPtr, &StringNumber, &StringLength); + break; + default: + break; + } + + // + // Two zeros following the last string. + // + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE10) + StringLength + StringNumber + 1); + if (SmbiosRecord == NULL) { + return EFI_OUT_OF_RESOURCES; + } + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE10) + StringLength + StringNumber + 1); + CopyMem(SmbiosRecord, RecordData, sizeof(SMBIOS_TABLE_TYPE10)); + DEBUG((EFI_D_ERROR, "(Type10) SmbiosRecord->Hdr.Type is %d \n", SmbiosRecord->Hdr.Type)); + DEBUG((EFI_D_ERROR, "(Type10) SmbiosRecord->Hdr.Length is %d \n", SmbiosRecord->Hdr.Length)); + + // + // Get device status + // + GetOnBoardDeviceType (&SmbiosRecord->Device[0].DeviceType); + + // + // Update SMBIOS Tables Type10 strings + // + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1); + SmbiosStringsUpdate ((CHAR16 **) &SmbiosTableType10Strings, OptionalStrStart, StringNumber); + + // + // Now we have got the full smbios record, call smbios protocol to add this record. + // + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios->Add ( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord + ); + FreePool(SmbiosRecord); + FreePool(StrBufferStart); + return Status; +} diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscPhysicalArray.uni b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscPhysicalArray.uni new file mode 100644 index 0000000000..fb947a1d31 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscPhysicalArray.uni @@ -0,0 +1,22 @@ +// /** @file +// BIOS Physical Memory +// SMBIOS type 16. +// +// Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// **/ + + +/=# +#langdef en-US "English" + + + diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscPhysicalArrayData.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscPhysicalArrayData.c new file mode 100644 index 0000000000..b9e05de04d --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscPhysicalArrayData.c @@ -0,0 +1,29 @@ +/** @file + BIOS Physical Array static data for SMBIOS type 16. + + Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" + +// +// Static (possibly build generated) Physical Memory Array Dat. +// +MISC_SMBIOS_TABLE_DATA(EFI_MEMORY_ARRAY_LOCATION_DATA, MiscPhysicalMemoryArray) = +{ + EfiMemoryArrayLocationSystemBoard, // Memory location + EfiMemoryArrayUseSystemMemory, // Memory array use + EfiMemoryErrorCorrectionNone, // Memory error correction + 0, // Maximum Memory Capacity + 0x01 // Number of Devices +}; diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscPhysicalArrayFunction.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscPhysicalArrayFunction.c new file mode 100644 index 0000000000..2c799ea75a --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscPhysicalArrayFunction.c @@ -0,0 +1,93 @@ +/** @file + BIOS system Physical Array boot time changes for SMBIOS type 16. + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" + +/** + This function makes boot time changes to the contents of the + MiscPhysicalArrayFunction (Type 16). + + @param RecordData Pointer to copy of RecordData from the Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ + +MISC_SMBIOS_TABLE_FUNCTION(MiscPhysicalMemoryArray) +{ + EFI_STATUS Status; + EFI_SMBIOS_HANDLE SmbiosHandle; + SMBIOS_TABLE_TYPE16 *SmbiosRecord; + EFI_MEMORY_ARRAY_LOCATION_DATA *ForType16InputData; + UINT32 TopOfMemory = 8 * 1024 * 1024; + + // + // First check for invalid parameters. + // + if (RecordData == NULL) { + return EFI_INVALID_PARAMETER; + } + + ForType16InputData = (EFI_MEMORY_ARRAY_LOCATION_DATA *)RecordData; + + // + // Two zeros following the last string. + // + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE16) + 1); + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE16) + 1); + + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY; + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE16); + + // + // Make handle chosen by smbios protocol.add automatically. + // + SmbiosRecord->Hdr.Handle = 0; + + // + // ReleaseDate will be the 3rd optional string following the formatted structure. + // + SmbiosRecord->Location = *(UINT8 *) &ForType16InputData ->MemoryArrayLocation; + SmbiosRecord->Use = *(UINT8 *) &ForType16InputData ->MemoryArrayUse; + SmbiosRecord->MemoryErrorCorrection = *(UINT8 *) &ForType16InputData->MemoryErrorCorrection; + + // + // System does not provide the error information structure + // + SmbiosRecord->MemoryErrorInformationHandle = 0xFFFE; + + // + // Maximum memory capacity + // + SmbiosRecord-> MaximumCapacity = TopOfMemory; + SmbiosRecord-> NumberOfMemoryDevices= 0x02; + + // + // Now we have got the full smbios record, call smbios protocol to add this record. + // + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios->Add ( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord + ); + FreePool(SmbiosRecord); + + return Status; +} diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscPortInternalConnectorDesignator.uni b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscPortInternalConnectorDesignator.uni new file mode 100644 index 0000000000..668992c4ac --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscPortInternalConnectorDesignator.uni @@ -0,0 +1,28 @@ +// /** @file +// Port internal connector information. +// +// Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// **/ + + +/=# + +#langdef en-US "English" + +#string STR_MISC_PORT_INTERNAL_IDE1 #language en-US "J4J1" +#string STR_MISC_PORT_EXTERNAL_IDE1 #language en-US "SATA_CON1" +#string STR_MISC_PORT_INTERNAL_IDE2 #language en-US "J4E3" +#string STR_MISC_PORT_EXTERNAL_IDE2 #language en-US "SATA_CON2" +#string STR_MISC_PORT_INTERNAL_ATX_POWER #language en-US "J3J1" +#string STR_MISC_PORT_EXTERNAL_ATX_POWER #language en-US "ATX_PWR" +#string STR_MISC_PORT_INTERNAL_BTX_POWER #language en-US "BTX_PWR" +#string STR_MISC_PORT_EXTERNAL_BTX_POWER #language en-US "" diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscPortInternalConnectorDesignatorData.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscPortInternalConnectorDesignatorData.c new file mode 100644 index 0000000000..356485d662 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscPortInternalConnectorDesignatorData.c @@ -0,0 +1,568 @@ +/** @file + Static data of Port internal connector designator information. + Port internal connector designator information is Misc for subclass type 6, SMBIOS type 8. + + Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" + +// +// Static (possibly build generated) Bios Vendor data. +// +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortKeyboard) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_KEYBOARD, ///< InternalConnectorDesignator + PortConnectorTypeNone, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypePS2, ///< ExternalConnectorType + PortTypeKeyboard ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortMouse) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_MOUSE, ///< InternalConnectorDesignator + PortConnectorTypeNone, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypePS2, ///< ExternalConnectorType + PortTypeMouse ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortCom1) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_COM1, ///< InternalConnectorDesignator + PortConnectorTypeOther, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeNone, ///< ExternalConnectorType + PortTypeSerial16550ACompatible ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortVideo) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_VIDEO, ///< InternalConnectorDesignator + PortConnectorTypeOther, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeDB15Female, ///< ExternalConnectorType + PortTypeVideoPort ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortHDMI) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_HDMI, ///< InternalConnectorDesignator + PortConnectorTypeOther, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeNone, ///< ExternalConnectorType + PortTypeVideoPort ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortUsb1) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_USB1, ///< InternalConnectorDesignator + PortConnectorTypeNone, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeUsb, ///< ExternalConnectorType + PortTypeUsb ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortUsb2) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_USB2, ///< InternalConnectorDesignator + PortConnectorTypeNone, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeUsb, ///< ExternalConnectorType + PortTypeUsb ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortUsb3) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_USB3, ///< InternalConnectorDesignator + PortConnectorTypeNone, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeUsb, ///< ExternalConnectorType + PortTypeUsb ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortUsb4) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_USB4, ///< InternalConnectorDesignator + PortConnectorTypeNone, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeUsb, ///< ExternalConnectorType + PortTypeUsb ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortUsb5) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_USB5, ///< InternalConnectorDesignator + PortConnectorTypeNone, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeUsb, ///< ExternalConnectorType + PortTypeUsb ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortUsb201) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_USB201, ///< InternalConnectorDesignator + PortConnectorTypeNone, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeUsb, ///< ExternalConnectorType + PortTypeUsb ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortUsb202) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_USB202, ///< InternalConnectorDesignator + PortConnectorTypeNone, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeUsb, ///< ExternalConnectorType + PortTypeUsb ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortNetwork) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_NETWORK, ///< InternalConnectorDesignator + PortConnectorTypeNone, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeRJ45, ///< ExternalConnectorType + PortTypeNetworkPort ///< PortType +}; + + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortIde1) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_IDE1, ///< InternalConnectorDesignator + PortConnectorTypeOnboardIde, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeNone, ///< ExternalConnectorType + PortTypeOther ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortSata0) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_SATA0, ///< InternalConnectorDesignator + PortConnectorTypeNone, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeSasSata, ///< ExternalConnectorType + PortTypeSata ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPorteSata4) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_ESATA4, ///< InternalConnectorDesignator + PortConnectorTypeNone, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeSasSata, ///< ExternalConnectorType + PortTypeSata ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPorteSata3) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_ESATA3, ///< InternalConnectorDesignator + PortConnectorTypeNone, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeSasSata, ///< ExternalConnectorType + PortTypeSata ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortSata2) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_SATA2, ///< InternalConnectorDesignator + PortConnectorTypeSasSata, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeNone, ///< ExternalConnectorType + PortTypeSata ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortSata1) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_SATA1, ///< InternalConnectorDesignator + PortConnectorTypeSasSata, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeNone, ///< ExternalConnectorType + PortTypeSata ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortACIN) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_ACIN, ///< InternalConnectorDesignator + PortConnectorTypeNone, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeOther, ///< ExternalConnectorType + PortTypeOther ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortPCHJTAG) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_PCHJTAG, ///< InternalConnectorDesignator + PortConnectorTypeOther, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeNone, ///< ExternalConnectorType + PortTypeOther ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortPORT80) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_PORT80, ///< InternalConnectorDesignator + PortConnectorTypeOther, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeNone, ///< ExternalConnectorType + PortTypeOther ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPort2X8HEADER) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_2X8HEADER, ///< InternalConnectorDesignator + PortConnectorTypeOther, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeNone, ///< ExternalConnectorType + PortTypeOther ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPort8PINHEADER) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_8PINHEADER, ///< InternalConnectorDesignator + PortConnectorTypeOther, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeNone, ///< ExternalConnectorType + PortTypeOther, ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortHDAHDMI) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_HDAHDMI, ///< InternalConnectorDesignator + PortConnectorTypeOther, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeNone, ///< ExternalConnectorType + PortTypeOther ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortMKEYBOARD) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_MKEYBOARD, ///< InternalConnectorDesignator + PortConnectorTypeOther, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeNone, ///< ExternalConnectorType + PortTypeOther ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortSPI) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_SPI, ///< InternalConnectorDesignator + PortConnectorTypeOther, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeNone, ///< ExternalConnectorType + PortTypeOther ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortLPCDOCKING) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_LPCDOCKING, ///< InternalConnectorDesignator + PortConnectorTypeOther, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeNone, ///< ExternalConnectorType + PortTypeOther ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortSIDEBAND) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_SIDEBAND, ///< InternalConnectorDesignator + PortConnectorTypeOther, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeNone, ///< ExternalConnectorType + PortTypeOther ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortLPCSLOT) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_LPCSLOT, ///< InternalConnectorDesignator + PortConnectorTypeOther, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeNone, ///< ExternalConnectorType + PortTypeOther ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortPCHXDP) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_PCHXDP, ///< InternalConnectorDesignator + PortConnectorTypeOther, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeNone, ///< ExternalConnectorType + PortTypeOther ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortSATAPOWER) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_SATAPOWER, ///< InternalConnectorDesignator + PortConnectorTypeOther, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeNone, ///< ExternalConnectorType + PortTypeOther ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortFPHEADER) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_FPHEADER, ///< InternalConnectorDesignator + PortConnectorTypeOther, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeNone, ///< ExternalConnectorType + PortTypeOther ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortATXPOWER) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_ATXPOWER, ///< InternalConnectorDesignator + PortConnectorTypeOther, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeNone, ///< ExternalConnectorType + PortTypeOther ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortAVMC) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_AVMC, ///< InternalConnectorDesignator + PortConnectorTypeOther, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeNone, ///< ExternalConnectorType + PortTypeOther ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortBATTB) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_BATTB, ///< InternalConnectorDesignator + PortConnectorTypeOther, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeNone, ///< ExternalConnectorType + PortTypeOther ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortBATTA) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_BATTA, ///< InternalConnectorDesignator + PortConnectorTypeOther, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeNone, ///< ExternalConnectorType + PortTypeOther ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortCPUFAN) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_CPUFAN, ///< InternalConnectorDesignator + PortConnectorTypeOther, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeNone, ///< ExternalConnectorType + PortTypeOther ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortXDP) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_XDP, ///< InternalConnectorDesignator + PortConnectorTypeOther, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeNone, ///< ExternalConnectorType + PortTypeOther ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortMEMORY1) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_MEMORY1, ///< InternalConnectorDesignator + PortConnectorTypeOther, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeNone, ///< ExternalConnectorType + PortTypeOther ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortMEMORY2) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_MEMORY2, ///< InternalConnectorDesignator + PortConnectorTypeOther, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeNone, ///< ExternalConnectorType + PortTypeOther ///< PortType +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE8, MiscPortFANPWR) = { + { // Hdr + EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_PORT_TOKEN_FANPWR, ///< InternalConnectorDesignator + PortConnectorTypeOther, ///< InternalConnectorType + SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator + PortConnectorTypeNone, ///< ExternalConnectorType + PortTypeOther ///< PortType +}; diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscPortInternalConnectorDesignatorFunction.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscPortInternalConnectorDesignatorFunction.c new file mode 100644 index 0000000000..77c83fb9a6 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscPortInternalConnectorDesignatorFunction.c @@ -0,0 +1,261 @@ +/** @file + Create the device path for the Port internal connector designator. + Port internal connector designator information is Misc for subclass type 6, SMBIOS type 8. + + Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" + +/** + This function makes boot time changes to the contents of the + MiscPortConnectorInformation (Type 8). + + @param RecordData Pointer to copy of RecordData from the Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +MISC_SMBIOS_TABLE_FUNCTION(MiscPortInternalConnectorDesignator) +{ + CHAR8 *OptionalStrStart; + UINTN StringNumber; + UINTN StringLength; + EFI_STATUS Status; + SMBIOS_TABLE_TYPE8 *SmbiosRecord; + EFI_SMBIOS_HANDLE SmbiosHandle; + SMBIOS_TABLE_TYPE8 *ForType8InputData; + SMBIOS_TABLE_TYPE8_STRINGS SmbiosTableType8Strings; + CHAR16 *StrBufferStart; + CHAR16 *StrBufferPtr; + + // + // First check for invalid parameters. + // + if (RecordData == NULL) { + return EFI_INVALID_PARAMETER; + } + + DEBUG ((EFI_D_INFO, "(MiscPortInternalConnectorDesignator) Entry.\n")); + ZeroMem (&SmbiosTableType8Strings, sizeof(SMBIOS_TABLE_TYPE8_STRINGS)); + StringNumber = 0; + StringLength = 0; + ForType8InputData = (SMBIOS_TABLE_TYPE8 *)RecordData; + StrBufferStart = AllocateZeroPool (2 * SMBIOS_STRING_MAX_LENGTH * sizeof(CHAR16)); + StrBufferPtr = StrBufferStart; + + // + // Initialize SMBIOS Tables Type8 strings + // + switch (ForType8InputData->InternalReferenceDesignator) { + case SMBIOS_MISC_PORT_TOKEN_KEYBOARD: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_KEYBOARD, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_KEYBOARD, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_MOUSE: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_MOUSE, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_MOUSE, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_COM1: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_COM1, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_COM1, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_VIDEO: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_VIDEO, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_VIDEO, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_HDMI: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_HDMI, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_HDMI, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_USB1: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_USB1, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_USB1, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_USB2: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_USB2, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_USB2, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_USB3: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_USB3, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_USB3, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_USB4: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_USB4, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_USB4, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_USB5: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_USB5, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_USB5, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_USB201: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_USB201, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_USB201, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_USB202: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_USB202, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_USB202, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_NETWORK: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_NETWORK, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_NETWORK, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_SATA0: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_SATA0, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_SATA0, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_ESATA4: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_ESATA4, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_ESATA4, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_ESATA3: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_ESATA3, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_ESATA3, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_SATA2: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_SATA2, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_SATA2, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_SATA1: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_SATA1, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_SATA1, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_ACIN: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_ACIN, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_ACIN, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_PCHJTAG: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_PCHJTAG, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_PCHJTAG, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_PORT80: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_PORT80, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_PORT80, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_2X8HEADER: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_2X8HEADER, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_2X8HEADER, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_8PINHEADER: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_8PINHEADER, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_8PINHEADER, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_HDAHDMI: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_HDAHDMI, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_HDAHDMI, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_MKEYBOARD: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_MKEYBOARD, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_MKEYBOARD, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_SPI: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_SPI, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_SPI, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_LPCDOCKING: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_LPCDOCKING, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_LPCDOCKING, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_SIDEBAND: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_SIDEBAND, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_SIDEBAND, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_LPCSLOT: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_LPCSLOT, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_LPCSLOT, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_PCHXDP: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_PCHXDP, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_PCHXDP, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_SATAPOWER: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_SATAPOWER, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_SATAPOWER, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_FPHEADER: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_FPHEADER, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_FPHEADER, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_ATXPOWER: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_ATXPOWER, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_ATXPOWER, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_AVMC: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_AVMC, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_AVMC, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_BATTB: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_BATTB, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_BATTB, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_BATTA: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_BATTA, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_BATTA, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_CPUFAN: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_CPUFAN, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_CPUFAN, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_XDP: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_XDP, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_XDP, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_MEMORY1: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_MEMORY1, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_MEMORY1, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_MEMORY2: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_MEMORY2, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_MEMORY2, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_PORT_TOKEN_FANPWR: + SmbiosStrInit (&SmbiosTableType8Strings.InternalReferenceDesignator, SMBIOS_MISC_PORT_INTERNAL_FANPWR, &StrBufferPtr, &StringNumber, &StringLength); + SmbiosStrInit (&SmbiosTableType8Strings.ExternalReferenceDesignator, SMBIOS_MISC_PORT_EXTERNAL_FANPWR, &StrBufferPtr, &StringNumber, &StringLength); + break; + default: + break; + } + ForType8InputData->InternalReferenceDesignator = SMBIOS_MISC_STRING_1; + + // + // Two zeros following the last string. + // + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE8) + StringLength + StringNumber + 1); + if (SmbiosRecord == NULL) { + return EFI_OUT_OF_RESOURCES; + } + ZeroMem(SmbiosRecord, sizeof(SMBIOS_TABLE_TYPE8) + StringLength + StringNumber + 1); + CopyMem(SmbiosRecord, RecordData, sizeof(SMBIOS_TABLE_TYPE8)); + + // + // Update SMBIOS Tables Type8 strings + // + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1); + SmbiosStringsUpdate ((CHAR16 **) &SmbiosTableType8Strings, OptionalStrStart, StringNumber); + + // + // Now we have got the full smbios record, call smbios protocol to add this record. + // + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios->Add ( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord + ); + FreePool(SmbiosRecord); + FreePool(StrBufferStart); + return Status; +} diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscProcessorCache.uni b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscProcessorCache.uni new file mode 100644 index 0000000000..f417fe3a25 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscProcessorCache.uni @@ -0,0 +1,19 @@ +// /** @file +// +// Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// **/ + + +/=# +#langdef en-US "English" + +#string STR_SOCKET_DESIGNATION #language en-US "0x01" diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscProcessorCacheData.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscProcessorCacheData.c new file mode 100644 index 0000000000..9a1e917e80 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscProcessorCacheData.c @@ -0,0 +1,24 @@ +/** @file + Processor cache static data is Misc for subclass type 7, SMBIOS type 7. + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" + +// +// Static (possibly build generated) Processor cache data. +// +MISC_SMBIOS_TABLE_DATA(EFI_CACHE_VARIABLE_RECORD, MiscProcessorCache) = { +0 +}; diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscProcessorCacheFunction.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscProcessorCacheFunction.c new file mode 100644 index 0000000000..dc32fbf55b --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscProcessorCacheFunction.c @@ -0,0 +1,43 @@ +/** @file + BIOS processor cache details is Misc for subclass type 7, SMBIOS type 7. + + Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" +#include + +extern SMBIOS_TABLE_TYPE7 *SmbiosRecordL1; +extern SMBIOS_TABLE_TYPE7 *SmbiosRecordL2; +extern SMBIOS_TABLE_TYPE7 *SmbiosRecordL3; + +UINT32 +ConvertBase2ToRaw ( + IN EFI_EXP_BASE2_DATA *Data) +{ + UINTN Index; + UINT32 RawData; + + RawData = Data->Value; + for (Index = 0; Index < (UINTN) Data->Exponent; Index++) { + RawData <<= 1; + } + + return RawData; +} + +MISC_SMBIOS_TABLE_FUNCTION(MiscProcessorCache) +{ + + return EFI_SUCCESS; +} diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscProcessorInformation.uni b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscProcessorInformation.uni new file mode 100644 index 0000000000..627d01072b --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscProcessorInformation.uni @@ -0,0 +1,24 @@ +// /** @file +// +// Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// **/ + + +/=# +#langdef en-US "English" + +#string STR_MISC_SOCKET_NAME #language en-US "VLV" +#string STR_MISC_PROCESSOR_MAUFACTURER #language en-US "Intel" +#string STR_MISC_PROCESSOR_VERSION #language en-US "Baytrail A0" +#string STR_MISC_PROCESSOR_SERIAL_NUMBER #language en-US " " +#string STR_MISC_ASSERT_TAG_DATA #language en-US " " +#string STR_MISC_PART_NUMBER #language en-US " " diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscProcessorInformationData.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscProcessorInformationData.c new file mode 100644 index 0000000000..4246fd57ff --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscProcessorInformationData.c @@ -0,0 +1,25 @@ +/** @file + This driver parses the mMiscSubclassDataTable structure and reports any generated data to smbios. + + Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" + + +// Static (possibly build generated) Bios Vendor data. +// +MISC_SMBIOS_TABLE_DATA(EFI_CPU_DATA_RECORD, MiscProcessorInformation) = { +0, +}; + diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscProcessorInformationFunction.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscProcessorInformationFunction.c new file mode 100644 index 0000000000..b0a6272708 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscProcessorInformationFunction.c @@ -0,0 +1,130 @@ +/** @file + Onboard processor information boot time changes for SMBIOS type 4. + + Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" +#include +#include +#include + +#define EfiProcessorFamilyIntelAtomProcessor 0x2B + +EFI_GUID mProcessorProducerGuid; + +/** + Get cache SMBIOS record handle. + + @param[in] Smbios Pointer to SMBIOS protocol instance. + @param[in] CacheLevel Level of cache, starting from one. + @param[out] Handle Returned record handle. + +**/ +VOID +GetCacheHandle ( + IN EFI_SMBIOS_PROTOCOL *Smbios, + IN UINT8 CacheLevel, + OUT EFI_SMBIOS_HANDLE *Handle + ) +{ + UINT16 CacheConfig; + EFI_STATUS Status; + EFI_SMBIOS_TYPE RecordType; + EFI_SMBIOS_TABLE_HEADER *Buffer; + + *Handle = 0; + RecordType = EFI_SMBIOS_TYPE_CACHE_INFORMATION; + + do { + Status = Smbios->GetNext ( + Smbios, + Handle, + &RecordType, + &Buffer, + NULL + ); + if (!EFI_ERROR (Status)) { + CacheConfig = *(UINT16*)((UINT8*)Buffer + 5); + if ((CacheConfig & 0x7) == (CacheLevel -1)) { + return; + } + } + } while (!EFI_ERROR(Status)); + + *Handle = 0xFFFF; +} + +/** + This function makes boot time changes to the contents of the + MiscProcessorInformation (Type 4). + + @param[in] RecordData Pointer to copy of RecordData from the Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +UINT32 +ConvertBase10ToRaw ( + IN EFI_EXP_BASE10_DATA *Data) +{ + UINTN Index; + UINT32 RawData; + + RawData = Data->Value; + for (Index = 0; Index < (UINTN) Data->Exponent; Index++) { + RawData *= 10; + } + + return RawData; +} + +#define BSEL_CR_OVERCLOCK_CONTROL 0xCD +#define FUSE_BSEL_MASK 0x03 + +UINT16 miFSBFrequencyTable[4] = { + 83, // 83.3MHz + 100, // 100MHz + 133, // 133MHz + 117 // 116.7MHz +}; + +/** + Determine the processor core frequency + + @param None + + @retval Processor core frequency multiplied by 3 + +**/ +UINT16 +DetermineiFsbFromMsr ( + VOID + ) +{ + // + // Determine the processor core frequency + // + UINT64 Temp; + Temp = (EfiReadMsr (BSEL_CR_OVERCLOCK_CONTROL)) & FUSE_BSEL_MASK; + + return miFSBFrequencyTable[(UINT32)(Temp)]; +} + +MISC_SMBIOS_TABLE_FUNCTION (MiscProcessorInformation) +{ + return EFI_SUCCESS; +} + diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscResetCapabilitiesData.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscResetCapabilitiesData.c new file mode 100644 index 0000000000..9c5971e2b6 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscResetCapabilitiesData.c @@ -0,0 +1,36 @@ +/** @file + Static data of Reset Capabilities information. + Reset Capabilities information is Misc for subclass type 17, SMBIOS type 23. + + Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" + +// +// Static (possibly build generated) Bios Vendor data. +// +MISC_SMBIOS_TABLE_DATA(EFI_MISC_RESET_CAPABILITIES, MiscResetCapabilities) += { + { // ResetCapabilities + 0, // Status + 0, // BootOption + 0, // BootOptionOnLimit + 0, // WatchdogTimerPresent + 0 // Reserved + }, + 0xFFFF, // ResetCount + 0xFFFF, // ResetLimit + 0xFFFF, // ResetTimerInterval + 0xFFFF // ResetTimeout +}; diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscResetCapabilitiesFunction.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscResetCapabilitiesFunction.c new file mode 100644 index 0000000000..18070852e2 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscResetCapabilitiesFunction.c @@ -0,0 +1,79 @@ +/** @file + Reset Capabilities for SMBIOS type 23. + + Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" + +/** + This function makes boot time changes to the contents of the + MiscOemString (Type 11). + + @param RecordData Pointer to copy of RecordData from the Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +MISC_SMBIOS_TABLE_FUNCTION(MiscResetCapabilities) +{ + EFI_STATUS Status; + EFI_SMBIOS_HANDLE SmbiosHandle; + SMBIOS_TABLE_TYPE23 *SmbiosRecord; + EFI_MISC_RESET_CAPABILITIES *ForType23InputData; + + ForType23InputData = (EFI_MISC_RESET_CAPABILITIES *)RecordData; + + // + // First check for invalid parameters. + // + if (RecordData == NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // Two zeros following the last string. + // + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE23) + 1 + 1); + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE23) + 1 + 1); + + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_SYSTEM_RESET; + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE23); + + // + // Make handle chosen by smbios protocol.add automatically. + // + SmbiosRecord->Hdr.Handle = 0; + SmbiosRecord->Capabilities = *(UINT8*)&(ForType23InputData->ResetCapabilities); + SmbiosRecord->ResetCount = (UINT16)ForType23InputData->ResetCount; + SmbiosRecord->ResetLimit = (UINT16)ForType23InputData->ResetLimit; + SmbiosRecord->TimerInterval = (UINT16)ForType23InputData->ResetTimerInterval; + SmbiosRecord->Timeout = (UINT16)ForType23InputData->ResetTimeout; + + // + // Now we have got the full smbios record, call smbios protocol to add this record. + // + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios->Add ( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord + ); + FreePool(SmbiosRecord); + + return Status; +} + diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSubclassDriver.h b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSubclassDriver.h new file mode 100644 index 0000000000..2aa49a27b8 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSubclassDriver.h @@ -0,0 +1,216 @@ +/** @file + Header file for MiscSubclass Driver. + + Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _MISC_SUBCLASS_DRIVER_H +#define _MISC_SUBCLASS_DRIVER_H + +#include "CommonHeader.h" +#include "SmbiosMiscStrings.h" +extern UINT8 MiscSubclassStrings[]; + +#define T14_FVI_STRING "Driver/firmware version" +#define EFI_SMBIOS_TYPE_FIRMWARE_VERSION_INFO 0x90 +#define EFI_SMBIOS_TYPE_MISC_VERSION_INFO 0x94 +#define TOUCH_ACPI_ID "I2C05\\SFFFF\\400K" +#define TOUCH_RESET_GPIO_MMIO 0xFED0C508 +#define EFI_SMBIOS_TYPE_SEC_INFO 0x83 +#define IntelIdentifer 0x6F725076 + +typedef enum { + PortTypeSata = 0x20, +} EFI_MISC_PORT_TYPE; +// +// Data table entry update function. +// +typedef EFI_STATUS (EFIAPI EFI_MISC_SMBIOS_DATA_FUNCTION) ( + IN VOID *RecordData, + IN EFI_SMBIOS_PROTOCOL *Smbios + ); + +// +// Data table entry definition. +// +typedef struct { + // + // intermediat input data for SMBIOS record + // + VOID *RecordData; + EFI_MISC_SMBIOS_DATA_FUNCTION *Function; +} EFI_MISC_SMBIOS_DATA_TABLE; + +// +// Data Table extern definitions. +// +#define MISC_SMBIOS_TABLE_EXTERNS(NAME1, NAME2, NAME3) \ +extern NAME1 NAME2 ## Data; \ +extern EFI_MISC_SMBIOS_DATA_FUNCTION NAME3 ## Function + +// +// Data Table entries +// +#define MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(NAME1, NAME2) \ +{ \ + & NAME1 ## Data, \ + & NAME2 ## Function \ +} + +// +// Global definition macros. +// +#define MISC_SMBIOS_TABLE_DATA(NAME1, NAME2) \ + NAME1 NAME2 ## Data + +#define MISC_SMBIOS_TABLE_FUNCTION(NAME2) \ + EFI_STATUS EFIAPI NAME2 ## Function( \ + IN VOID *RecordData, \ + IN EFI_SMBIOS_PROTOCOL *Smbios \ + ) + +#pragma pack(1) + +// +// This is definition for SMBIOS Oem data type 0x90 +// +typedef struct { + STRING_REF SECVersion; + STRING_REF uCodeVersion; + STRING_REF GOPVersion; + STRING_REF CpuStepping; +} EFI_MISC_OEM_TYPE_0x90; + +// +// This is definition for SMBIOS Oem data type 0x90 +// +typedef struct { + SMBIOS_STRUCTURE Hdr; + SMBIOS_TABLE_STRING SECVersion; + SMBIOS_TABLE_STRING uCodeVersion; + SMBIOS_TABLE_STRING GOPVersion; + SMBIOS_TABLE_STRING CpuStepping; +} SMBIOS_TABLE_TYPE90; + +typedef struct { + STRING_REF GopVersion; + STRING_REF UCodeVersion; + STRING_REF MRCVersion; + STRING_REF SECVersion; + STRING_REF ULPMCVersion; + STRING_REF PMCVersion; + STRING_REF PUnitVersion; + STRING_REF SoCVersion; + STRING_REF BoardVersion; + STRING_REF FabVersion; + STRING_REF CPUFlavor; + STRING_REF BiosVersion; + STRING_REF PmicVersion; + STRING_REF TouchVersion; + STRING_REF SecureBoot; + STRING_REF BootMode; + STRING_REF SpeedStepMode; + STRING_REF CPUTurboMode; + STRING_REF MaxCState; + STRING_REF GfxTurbo; + STRING_REF IdleReserve; + STRING_REF RC6; +}EFI_MISC_OEM_TYPE_0x94; + +typedef struct { + SMBIOS_STRUCTURE Hdr; + SMBIOS_TABLE_STRING GopVersion; + SMBIOS_TABLE_STRING uCodeVersion; + SMBIOS_TABLE_STRING MRCVersion; + SMBIOS_TABLE_STRING SECVersion; + SMBIOS_TABLE_STRING ULPMCVersion; + SMBIOS_TABLE_STRING PMCVersion; + SMBIOS_TABLE_STRING PUnitVersion; + SMBIOS_TABLE_STRING SoCVersion; + SMBIOS_TABLE_STRING BoardVersion; + SMBIOS_TABLE_STRING FabVersion; + SMBIOS_TABLE_STRING CPUFlavor; + SMBIOS_TABLE_STRING BiosVersion; + SMBIOS_TABLE_STRING PmicVersion; + SMBIOS_TABLE_STRING TouchVersion; + SMBIOS_TABLE_STRING SecureBoot; + SMBIOS_TABLE_STRING BootMode; + SMBIOS_TABLE_STRING SpeedStepMode; + SMBIOS_TABLE_STRING CPUTurboMode; + SMBIOS_TABLE_STRING MaxCState; + SMBIOS_TABLE_STRING GfxTurbo; + SMBIOS_TABLE_STRING IdleReserve; + SMBIOS_TABLE_STRING RC6; +}SMBIOS_TABLE_TYPE94; + +#pragma pack() +// +// Data Table Array +// +extern EFI_MISC_SMBIOS_DATA_TABLE mMiscSubclassDataTable[]; + +// +// Data Table Array Entries +// +extern UINTN mMiscSubclassDataTableEntries; +extern EFI_HII_HANDLE mHiiHandle; + +// +// Prototypes +// +EFI_STATUS +EFIAPI +MiscSubclassDriverEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +EFI_STRING +EFIAPI +SmbiosMiscGetString ( + IN EFI_STRING_ID StringId + ); +/** + Initialize SMBIOS table strings. + + @param[out] **Destination The pointer for the destination. + @param[in] *Source The pointer for the source date. + @param[out] **StrBuffer The pointer for string buffer. + @param[out] *Count The accumulated number of strings. + @param[out] *SizeOfStrings The accumulated number of strings length. + + @retval EFI_SUCCESS Successful. + @retval EFI_INVALID_PARAMETER Distination pointer is not NULL. + +**/ +EFI_STATUS +SmbiosStrInit ( + OUT CHAR16 **Destination, + IN CHAR16 CONST *Source, + OUT CHAR16 **StrBuffer, + OUT UINTN *Count, + OUT UINTN *SizeOfStrings + ); +/** + Update SMBIOS strings. + + @param[in] **StringArray The strings to be updated. + @param[in] *StarAddr The pointer of strat location. + @param[in] NumOfStrings The number of strings. +**/ +VOID +SmbiosStringsUpdate ( + CHAR16 **StringArray, + UINT8 *StartAddr, + UINTN NumOfStrings + ); +#endif diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSubclassDriver.uni b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSubclassDriver.uni new file mode 100644 index 0000000000..d87cc6ac94 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSubclassDriver.uni @@ -0,0 +1,32 @@ +// /** @file +// Misc Subclass information. +// +// Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// **/ + +/=# + +#langdef en-US "English" + +#string STR_MISC_SUBCLASS_DRIVER_TITLE #language en-US "Not used" + +#include "MiscBaseBoardManufacturer.uni" +#include "MiscBiosVendor.uni" +#include "MiscChassisManufacturer.uni" +#include "MiscOemString.uni" +#include "MiscOnboardDevice.uni" +#include "MiscPortInternalConnectorDesignator.uni" +#include "MiscSystemLanguageString.uni" +#include "MiscSystemManufacturer.uni" +#include "MiscSystemOptionString.uni" +#include "MiscSystemSlotDesignation.uni" + diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSubclassDriverDataTable.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSubclassDriverDataTable.c new file mode 100644 index 0000000000..f929be1426 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSubclassDriverDataTable.c @@ -0,0 +1,124 @@ +/** @file + Create the mMiscSubclassDataTable structure, and it is used to report any generate data to the DataHub. + + Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" + +// +// External definitions referenced by Data Table entries. +// +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_BIOS_VENDOR_DATA, MiscBiosVendor, MiscBiosVendor); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_MANUFACTURER_DATA, MiscSystemManufacturer, MiscSystemManufacturer); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_BASE_BOARD_MANUFACTURER_DATA, MiscBaseBoardManufacturer, MiscBaseBoardManufacturer); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_CHASSIS_MANUFACTURER_DATA, MiscChassisManufacturer, MiscChassisManufacturer); +MISC_SMBIOS_TABLE_EXTERNS(EFI_CACHE_VARIABLE_RECORD, MiscProcessorCache, MiscProcessorCache); //type 7 +MISC_SMBIOS_TABLE_EXTERNS(EFI_CPU_DATA_RECORD, MiscProcessorInformation, MiscProcessorInformation); //type 4 +MISC_SMBIOS_TABLE_EXTERNS(EFI_MEMORY_ARRAY_LOCATION_DATA, MiscPhysicalMemoryArray,MiscPhysicalMemoryArray); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MEMORY_ARRAY_LINK_DATA, MiscMemoryDevice, MiscMemoryDevice); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE8, MiscPortKeyboard, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE8, MiscPortMouse, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE8, MiscPortCom1, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE8, MiscPortVideo, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE8, MiscPortHDMI, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE8, MiscPortUsb201, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE8, MiscPortUsb202, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE8, MiscPortNetwork, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE8, MiscPortSata0, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE8, MiscPortSata1, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE8, MiscPortACIN, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE8, MiscPortPORT80, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE8, MiscPort2X8HEADER, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE8, MiscPort8PINHEADER, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE8, MiscPortHDAHDMI, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE8, MiscPortMKEYBOARD, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE8, MiscPortSPI, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE8, MiscPortLPCDOCKING, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE8, MiscPortSIDEBAND, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE8, MiscPortLPCSLOT, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE8, MiscPortSATAPOWER, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE8, MiscPortFPHEADER, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE8, MiscPortATXPOWER, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE8, MiscPortBATTB, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE8, MiscPortBATTA, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE8, MiscPortCPUFAN, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE8, MiscPortXDP, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE8, MiscPortMEMORY1, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE8, MiscPortMEMORY2, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE8, MiscPortFANPWR, MiscPortInternalConnectorDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE9, MiscSystemSlotPcie0, MiscSystemSlotDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE9, MiscSystemSlotPcie1, MiscSystemSlotDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE9, MiscSystemSlotPcie2, MiscSystemSlotDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE9, MiscSystemSlotPcie3, MiscSystemSlotDesignator); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE10, MiscOnBoardDeviceVideo, MiscOnBoardDevice); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE10, MiscOnBoardDeviceEthernet, MiscOnBoardDevice); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE10, MiscOnBoardDeviceSound, MiscOnBoardDevice); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_NUMBER_OF_INSTALLABLE_LANGUAGES_DATA, NumberOfInstallableLanguages, NumberOfInstallableLanguages); +MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_LANGUAGE_STRING_DATA, SystemLanguageString, SystemLanguageString); +MISC_SMBIOS_TABLE_EXTERNS(SMBIOS_TABLE_TYPE32, MiscBootInfoStatus, MiscBootInfoStatus); + +// +// Data Table. +// +EFI_MISC_SMBIOS_DATA_TABLE mMiscSubclassDataTable[] = { + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscBiosVendor, MiscBiosVendor), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemManufacturer, MiscSystemManufacturer), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscBaseBoardManufacturer, MiscBaseBoardManufacturer), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscChassisManufacturer, MiscChassisManufacturer), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortKeyboard, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortMouse, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortCom1, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortVideo, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortHDMI, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortUsb201, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortUsb202, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortNetwork, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortSata0, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortSata1, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortACIN, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortPORT80, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPort2X8HEADER, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPort8PINHEADER, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortHDAHDMI, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortMKEYBOARD, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortSPI, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortLPCDOCKING, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortSIDEBAND, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortLPCSLOT, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortSATAPOWER, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortFPHEADER, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortATXPOWER, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortBATTB, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortBATTA, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortCPUFAN, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortXDP, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortMEMORY1, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortMEMORY2, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortFANPWR, MiscPortInternalConnectorDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlotPcie0, MiscSystemSlotDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlotPcie1, MiscSystemSlotDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlotPcie2, MiscSystemSlotDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlotPcie3, MiscSystemSlotDesignator), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscOnBoardDeviceEthernet, MiscOnBoardDevice), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscOnBoardDeviceSound, MiscOnBoardDevice), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscOnBoardDeviceVideo, MiscOnBoardDevice), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(SystemLanguageString, SystemLanguageString), + MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscBootInfoStatus, MiscBootInfoStatus), +}; + +// +// Number of Data Table entries. +// +UINTN mMiscSubclassDataTableEntries = + (sizeof mMiscSubclassDataTable) / sizeof(EFI_MISC_SMBIOS_DATA_TABLE); diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSubclassDriverEntryPoint.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSubclassDriverEntryPoint.c new file mode 100644 index 0000000000..3d99d4a78a --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSubclassDriverEntryPoint.c @@ -0,0 +1,239 @@ +/** @file + This driver parses the mMiscSubclassDataTable structure and reports any generated data to the DataHub. + + Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" +#include + +EFI_HII_HANDLE mHiiHandle; +EFI_HII_STRING_PROTOCOL *mHiiString; + +EFI_STATUS +GetSmbiosCpuInformation ( EFI_SMBIOS_PROTOCOL *Smbios + ); + +EFI_STRING +EFIAPI +SmbiosMiscGetString ( + IN EFI_STRING_ID StringId + ) +{ + EFI_STATUS Status; + UINTN StringSize; + CHAR16 TempString; + EFI_STRING String; + String = NULL; + + // + // Retrieve the size of the string in the string package for the BestLanguage + // + StringSize = 0; + Status = mHiiString->GetString ( + mHiiString, + "en-US", + mHiiHandle, + StringId, + &TempString, + &StringSize, + NULL + ); + // + // If GetString() returns EFI_SUCCESS for a zero size, + // then there are no supported languages registered for HiiHandle. If GetString() + // returns an error other than EFI_BUFFER_TOO_SMALL, then HiiHandle is not present + // in the HII Database + // + if (Status != EFI_BUFFER_TOO_SMALL) { + goto Error; + } + + // + // Allocate a buffer for the return string + // + String = AllocateZeroPool (StringSize); + if (String == NULL) { + goto Error; + } + + // + // Retrieve the string from the string package + // + Status = mHiiString->GetString ( + mHiiString, + "en-US", + mHiiHandle, + StringId, + String, + &StringSize, + NULL + ); + if (EFI_ERROR (Status)) { + // + // Free the buffer and return NULL if the supported languages can not be retrieved. + // + FreePool (String); + String = NULL; + } +Error: + + return String; +} +/** + Initialize SMBIOS table strings. + + @param[out] **Destination The pointer for the destination. + @param[in] *Source The pointer for the source date. + @param[out] **StrBuffer The pointer for string buffer. + @param[out] *Count The accumulated number of strings. + @param[out] *SizeOfStrings The accumulated number of strings length. + + @retval EFI_SUCCESS Successful. + @retval EFI_INVALID_PARAMETER Distination pointer is not NULL. + +**/ +EFI_STATUS +SmbiosStrInit ( + OUT CHAR16 **Destination, + IN CHAR16 CONST *Source, + OUT CHAR16 **StrBuffer, + OUT UINTN *Count, + OUT UINTN *SizeOfStrings + ) +{ + UINTN StrSize; + + if ((*Destination != NULL) || (*StrBuffer == NULL)) { + return EFI_INVALID_PARAMETER; + } + + DEBUG ((EFI_D_ERROR, "(SmbiosStrInit) Entry.\n")); + if (StrLen(Source) > SMBIOS_STRING_MAX_LENGTH) { + StrSize = SMBIOS_STRING_MAX_LENGTH; + } else { + StrSize = StrLen(Source); + } + + DEBUG ((EFI_D_ERROR, "(SmbiosStrInit) Source string: %S\n", Source)); + StrCpy (*StrBuffer, Source); + *Destination = *StrBuffer; + *StrBuffer += (StrSize + 1); + + *SizeOfStrings += StrSize; + *Count += 1; + + return EFI_SUCCESS; +} +/** + Update SMBIOS strings. + + @param[in] **StringArray The strings to be updated. + @param[in] *StarAddr The pointer of strat location. + @param[in] NumOfStrings The number of strings. +**/ +VOID +SmbiosStringsUpdate ( + CHAR16 **StringArray, + UINT8 *StartAddr, + UINTN NumOfStrings + ) +{ + UINTN LenStr; + UINTN IdxStr; + + LenStr = 0; + IdxStr = 0; + + for (IdxStr = 0; IdxStr < NumOfStrings; IdxStr++) { + UnicodeStrToAsciiStr (StringArray[IdxStr], StartAddr + LenStr + IdxStr); + LenStr += StrLen(StringArray[IdxStr]); + } +} + +/** + Standard EFI driver point. This driver parses the mMiscSubclassDataTable + structure and reports any generated data to the DataHub. + + @param[in] ImageHandle Handle for the image of this driver + @param[in] SystemTable Pointer to the EFI System Table + + @retval EFI_SUCCESS The data was successfully reported to the Data Hub. + @retval EFI_DEVICE_ERROR Can not locate any protocols + +**/ +EFI_STATUS +EFIAPI +MiscSubclassDriverEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + UINTN Index; + EFI_STATUS EfiStatus; + EFI_SMBIOS_PROTOCOL *Smbios; + + // + // Retrieve the pointer to the UEFI HII String Protocol + // + EfiStatus = gBS->LocateProtocol ( + &gEfiHiiStringProtocolGuid, + NULL, + (VOID **) &mHiiString + ); + ASSERT_EFI_ERROR (EfiStatus); + + EfiStatus = gBS->LocateProtocol( + &gEfiSmbiosProtocolGuid, + NULL, + (VOID**)&Smbios + ); + + if (EFI_ERROR (EfiStatus)) { + DEBUG((EFI_D_ERROR, "Could not locate SMBIOS protocol. %r\n", EfiStatus)); + return EfiStatus; + } + + mHiiHandle = HiiAddPackages ( + &gEfiCallerIdGuid, + NULL, + MiscSubclassStrings, + NULL + ); + ASSERT (mHiiHandle != NULL); + + for (Index = 0; Index < mMiscSubclassDataTableEntries; ++Index) { + // + // If the entry have a function pointer, just log the data. + // + if (mMiscSubclassDataTable[Index].Function != NULL) { + EfiStatus = (*mMiscSubclassDataTable[Index].Function)( + mMiscSubclassDataTable[Index].RecordData, + Smbios + ); + + if (EFI_ERROR (EfiStatus)) { + DEBUG((EFI_D_ERROR, "Misc smbios store error. Index=%d, ReturnStatus=%r\n", Index, EfiStatus)); + return EfiStatus; + } + } + } + + // + // SMBIOS Type4/Type7 + // + GetSmbiosCpuInformation(Smbios); + + return EfiStatus; +} + diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemLanguageString.uni b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemLanguageString.uni new file mode 100644 index 0000000000..f8632bb1ac --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemLanguageString.uni @@ -0,0 +1,20 @@ +// /** @file +// System language information +// Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// **/ + + +/=# + +#langdef en-US "English" + +#string STR_MISC_SYSTEM_LANGUAGE_EN_US #language en-US "enUS" diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemLanguageStringData.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemLanguageStringData.c new file mode 100644 index 0000000000..31266b474d --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemLanguageStringData.c @@ -0,0 +1,27 @@ +/** @file + Static data of System language string information. + System language string information is Misc for subclass type 12, SMBIOS type 13. + + Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" + +// +// Static (possibly build generated) Bios Vendor data. +// +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_LANGUAGE_STRING_DATA, SystemLanguageString) += { + 0, + STRING_TOKEN(STR_MISC_SYSTEM_LANGUAGE_EN_US) +}; diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemLanguageStringFunction.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemLanguageStringFunction.c new file mode 100644 index 0000000000..02d7be5801 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemLanguageStringFunction.c @@ -0,0 +1,88 @@ +/** @file + Misc string for SMBIOS type 11. + + Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" + +/** + This function makes boot time changes to the contents of the + MiscOemString (Type 11). + + @param RecordData Pointer to copy of RecordData from the Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ + +MISC_SMBIOS_TABLE_FUNCTION(SystemLanguageString) +{ + EFI_STATUS Status; + EFI_SMBIOS_HANDLE SmbiosHandle; + SMBIOS_TABLE_TYPE13 *SmbiosRecord; + UINTN StrLeng; + CHAR8 *OptionalStrStart; + EFI_STRING Str; + STRING_REF TokenToGet; + + // + // First check for invalid parameters. + // + if (RecordData == NULL) { + return EFI_INVALID_PARAMETER; + } + + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_LANGUAGE_EN_US); + Str = SmbiosMiscGetString (TokenToGet); + StrLeng = StrLen(Str); + if (StrLeng > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + // + // Two zeros following the last string. + // + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE13) + StrLeng + 1 + 1); + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE13) + StrLeng + 1 + 1); + + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION; + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE13); + + // + // Make handle chosen by smbios protocol.add automatically. + // + SmbiosRecord->Hdr.Handle = 0; + SmbiosRecord->InstallableLanguages = 1; + SmbiosRecord->Flags = 1; + SmbiosRecord->CurrentLanguages = 1; + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1); + UnicodeStrToAsciiStr(Str, OptionalStrStart); + + // + // Now we have got the full smbios record, call smbios protocol to add this record. + // + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios->Add ( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord + ); + FreePool(SmbiosRecord); + + return Status; +} + diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemManufacturer.uni b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemManufacturer.uni new file mode 100644 index 0000000000..ff151bf8e2 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemManufacturer.uni @@ -0,0 +1,27 @@ +// /** @file +// System manufacturer information. +// +// Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// **/ + + +/=# + +#langdef en-US "English" + +#string STR_MISC_SYSTEM_MANUFACTURER #language en-US "Intel Corporation" +#string STR_MISC_SYSTEM_PRODUCT_NAME #language en-US "CHERRYVIEW Platform" +#string STR_MISC_SYSTEM_VERSION #language en-US "0.1" +#string STR_MISC_SYSTEM_SERIAL_NUMBER #language en-US "112233445566" +#string STR_MISC_SYSTEM_SKU_NUMBER #language en-US "System SKUNumber" +#string STR_MISC_SYSTEM_FAMILY_NAME #language en-US "Cherryview System" +#string STR_MISC_SYSTEM_FAMILY_NAME1 #language en-US "Cherryview System" diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemManufacturerData.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemManufacturerData.c new file mode 100644 index 0000000000..942d5c0e02 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemManufacturerData.c @@ -0,0 +1,36 @@ +/** @file + Static data of System manufacturer information. + System manufacturer information is Misc for subclass type 3, SMBIOS type 1. + + Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" + +// +// Static (possibly build generated) System Manufacturer data. +// +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_MANUFACTURER_DATA, MiscSystemManufacturer) += { + STRING_TOKEN(STR_MISC_SYSTEM_MANUFACTURER), // SystemManufactrurer + STRING_TOKEN(STR_MISC_SYSTEM_PRODUCT_NAME), // SystemProductName + STRING_TOKEN(STR_MISC_SYSTEM_VERSION), // SystemVersion + STRING_TOKEN(STR_MISC_SYSTEM_SERIAL_NUMBER), // SystemSerialNumber + { // SystemUuid + // + // TODO Hard code here for WHCT test. + 0xa5000288, 0x6462, 0x4524, 0x98, 0x6a, 0x9b, 0x77, 0x37, 0xe3, 0x15, 0xcf + // + }, + EfiSystemWakeupTypePowerSwitch // SystemWakeupType +}; diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemManufacturerFunction.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemManufacturerFunction.c new file mode 100644 index 0000000000..3ce9fff0ce --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemManufacturerFunction.c @@ -0,0 +1,341 @@ +/** @file + This driver parses the mMiscSubclassDataTable structure and reports any generated data. + + Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" +#include +#include +#include "Library/DebugLib.h" +#include +#include + +/** + This function makes boot time changes to the contents of the + MiscSystemManufacturer (Type 1). + + @param RecordData Pointer to copy of RecordData from the Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +MISC_SMBIOS_TABLE_FUNCTION(MiscSystemManufacturer) +{ + CHAR8 *OptionalStrStart; + UINTN ManuStrLen; + UINTN VerStrLen; + UINTN PdNameStrLen; + UINTN SerialNumStrLen; + UINTN SKUNumStrLen; + UINTN FamilyStrLen; + EFI_STATUS Status; + CHAR16 Manufacturer[SMBIOS_STRING_MAX_LENGTH]; + CHAR16 ProductName[SMBIOS_STRING_MAX_LENGTH]; + CHAR16 Version[SMBIOS_STRING_MAX_LENGTH]; + CHAR16 SerialNumber[SMBIOS_STRING_MAX_LENGTH]; + CHAR16 SKUNumber[SMBIOS_STRING_MAX_LENGTH]; + CHAR16 Family[SMBIOS_STRING_MAX_LENGTH]; + EFI_STRING ManufacturerPtr; + EFI_STRING ProductNamePtr; + EFI_STRING VersionPtr; + EFI_STRING SerialNumberPtr; + EFI_STRING SKUNumberPtr; + EFI_STRING FamilyPtr; + STRING_REF TokenToGet; + STRING_REF TokenToUpdate; + EFI_SMBIOS_HANDLE SmbiosHandle; + SMBIOS_TABLE_TYPE1 *SmbiosRecord; + EFI_MISC_SYSTEM_MANUFACTURER *ForType1InputData; + + ForType1InputData = (EFI_MISC_SYSTEM_MANUFACTURER*)RecordData; + + // + // First check for invalid parameters. + // + if (RecordData == NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // Update strings from PCD + // + AsciiStrToUnicodeStr ((const CHAR8 *)PcdGetPtr(PcdSMBIOSSystemManufacturer), Manufacturer); + if (StrLen (Manufacturer) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_MANUFACTURER); + HiiSetString (mHiiHandle, TokenToUpdate, Manufacturer, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_MANUFACTURER); + ManufacturerPtr = SmbiosMiscGetString (TokenToGet); + ManuStrLen = StrLen(ManufacturerPtr); + if (ManuStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + // + // Update strings from PCD + // + // + // SoC Steppings + // + switch (SocStepping()) { + case SocA0: + StrCpy (ProductName, L"CHERRYVIEW A0 PLATFORM"); + break; + case SocA1: + StrCpy (ProductName, L"CHERRYVIEW A1 PLATFORM"); + break; + case SocA2: + StrCpy (ProductName, L"CHERRYVIEW A2 PLATFORM"); + break; + case SocA3: + StrCpy (ProductName, L"CHERRYVIEW A3 PLATFORM"); + break; + case SocA4: + StrCpy (ProductName, L"CHERRYVIEW A4 PLATFORM"); + break; + case SocA5: + StrCpy (ProductName, L"CHERRYVIEW A5 PLATFORM"); + break; + case SocA6: + StrCpy (ProductName, L"CHERRYVIEW A6 PLATFORM"); + break; + case SocA7: + StrCpy (ProductName, L"CHERRYVIEW A7 PLATFORM"); + break; + case SocB0: + StrCpy (ProductName, L"CHERRYVIEW B0 PLATFORM"); + break; + case SocB1: + StrCpy (ProductName, L"CHERRYVIEW B1 PLATFORM"); + break; + case SocB2: + StrCpy (ProductName, L"CHERRYVIEW B2 PLATFORM"); + break; + case SocB3: + StrCpy (ProductName, L"CHERRYVIEW B3 PLATFORM"); + break; + case SocB4: + StrCpy (ProductName, L"CHERRYVIEW B4 PLATFORM"); + break; + case SocB5: + StrCpy (ProductName, L"CHERRYVIEW B5 PLATFORM"); + break; + case SocB6: + StrCpy (ProductName, L"CHERRYVIEW B6 PLATFORM"); + break; + case SocB7: + StrCpy (ProductName, L"CHERRYVIEW B7 PLATFORM"); + break; + case SocC0: + StrCpy (ProductName, L"CHERRYVIEW C0 PLATFORM"); + break; + case SocC1: + StrCpy (ProductName, L"CHERRYVIEW C1 PLATFORM"); + break; + case SocC2: + StrCpy (ProductName, L"CHERRYVIEW C2 PLATFORM"); + break; + case SocC3: + StrCpy (ProductName, L"CHERRYVIEW C3 PLATFORM"); + break; + case SocC4: + StrCpy (ProductName, L"CHERRYVIEW C4 PLATFORM"); + break; + case SocC5: + StrCpy (ProductName, L"CHERRYVIEW C5 PLATFORM"); + break; + case SocC6: + StrCpy (ProductName, L"CHERRYVIEW C6 PLATFORM"); + break; + case SocC7: + StrCpy (ProductName, L"CHERRYVIEW C7 PLATFORM"); + break; + case SocD0: + StrCpy (ProductName, L"CHERRYVIEW D0 PLATFORM"); + break; + case SocD1: + StrCpy (ProductName, L"CHERRYVIEW D1 PLATFORM"); + break; + case SocD2: + StrCpy (ProductName, L"CHERRYVIEW D2 PLATFORM"); + break; + case SocD3: + StrCpy (ProductName, L"CHERRYVIEW D3 PLATFORM"); + break; + case SocD4: + StrCpy (ProductName, L"CHERRYVIEW D4 PLATFORM"); + break; + case SocD5: + StrCpy (ProductName, L"CHERRYVIEW D5 PLATFORM"); + break; + case SocD6: + StrCpy (ProductName, L"CHERRYVIEW D6 PLATFORM"); + break; + case SocD7: + StrCpy (ProductName, L"CHERRYVIEW D7 PLATFORM"); + break; + default: + StrCpy (ProductName, SMBIOS_MISC_TYPE01_PRODUCT_NAME); + DEBUG ((EFI_D_ERROR, "Unknown Stepping Detected\n")); + break; + } + + if (StrLen (ProductName) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_PRODUCT_NAME); + HiiSetString (mHiiHandle, TokenToUpdate, ProductName, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_PRODUCT_NAME); + ProductNamePtr = SmbiosMiscGetString (TokenToGet); + PdNameStrLen = StrLen(ProductNamePtr); + if (PdNameStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + // + // Update strings from PCD + // + AsciiStrToUnicodeStr ((const CHAR8 *)PcdGetPtr(PcdSMBIOSSystemVersion), Version); + if (StrLen (Version) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_VERSION); + HiiSetString (mHiiHandle, TokenToUpdate, Version, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_VERSION); + VersionPtr = SmbiosMiscGetString (TokenToGet); + VerStrLen = StrLen(VersionPtr); + if (VerStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + // + // Update strings from PCD + // + AsciiStrToUnicodeStr ((const CHAR8 *)PcdGetPtr(PcdSMBIOSSystemSerialNumber), SerialNumber); + if (StrLen (SerialNumber) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_SERIAL_NUMBER); + HiiSetString (mHiiHandle, TokenToUpdate, SerialNumber, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SERIAL_NUMBER); + SerialNumberPtr = SmbiosMiscGetString (TokenToGet); + SerialNumStrLen = StrLen(SerialNumberPtr); + if (SerialNumStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + // + // Update strings from PCD + // + AsciiStrToUnicodeStr ((const CHAR8 *)PcdGetPtr(PcdSMBIOSSystemSKUNumber), SKUNumber); + if (StrLen (SKUNumber) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_SKU_NUMBER); + HiiSetString (mHiiHandle, TokenToUpdate, SKUNumber, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SKU_NUMBER); + SKUNumberPtr = SmbiosMiscGetString (TokenToGet); + SKUNumStrLen = StrLen(SKUNumberPtr); + if (SKUNumStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + // + // Update strings from PCD + // + AsciiStrToUnicodeStr ((const CHAR8 *)PcdGetPtr(PcdSMBIOSSystemFamily), Family); + if (StrLen (Family) > 0) { + TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_FAMILY_NAME); + HiiSetString (mHiiHandle, TokenToUpdate, Family, NULL); + } + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_FAMILY_NAME); + FamilyPtr = SmbiosMiscGetString (TokenToGet); + FamilyStrLen = StrLen(FamilyPtr); + if (FamilyStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + // + // Two zeros following the last string. + // + SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE1) + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + SKUNumStrLen + 1 + FamilyStrLen + 1 + 1); + + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_SYSTEM_INFORMATION; + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE1); + + // + // Make handle chosen by smbios protocol.add automatically. + // + SmbiosRecord->Hdr.Handle = 0; + + // + // Manu will be the 1st optional string following the formatted structure. + // + SmbiosRecord->Manufacturer = 1; + + // + // ProductName will be the 2nd optional string following the formatted structure. + // + SmbiosRecord->ProductName = 2; + + // + // Version will be the 3rd optional string following the formatted structure. + // + SmbiosRecord->Version = 3; + + // + // Version will be the 4th optional string following the formatted structure. + // + SmbiosRecord->SerialNumber = 4; + + SmbiosRecord->SKUNumber= 5; + SmbiosRecord->Family= 6; + + // + // Unique UUID + // + CopyMem ((UINT8 *) (&SmbiosRecord->Uuid), (UINT8 *)PcdGetPtr(PcdSMBIOSSystemUuid),16); + + SmbiosRecord->WakeUpType = (UINT8)ForType1InputData->SystemWakeupType; + + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1); + UnicodeStrToAsciiStr(ManufacturerPtr, OptionalStrStart); + UnicodeStrToAsciiStr(ProductNamePtr, OptionalStrStart + ManuStrLen + 1); + UnicodeStrToAsciiStr(VersionPtr, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1); + UnicodeStrToAsciiStr(SerialNumberPtr, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1); + UnicodeStrToAsciiStr(SKUNumberPtr, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen+ 1); + UnicodeStrToAsciiStr(FamilyPtr, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + SKUNumStrLen+ 1); + + // + // Now we have got the full smbios record, call smbios protocol to add this record. + // + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios-> Add( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord + ); + FreePool(SmbiosRecord); + + // + // Free the memory allocated before + // + FreePool (ManufacturerPtr); + FreePool (ProductNamePtr); + FreePool (VersionPtr); + FreePool (SerialNumberPtr); + FreePool (SKUNumberPtr); + FreePool (FamilyPtr); + + return Status; +} diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemOptionString.uni b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemOptionString.uni new file mode 100644 index 0000000000..e0729fff46 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemOptionString.uni @@ -0,0 +1,21 @@ +// /** @file +// System option language. +// +// Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// **/ + + +/=# + +#langdef en-US "English" + +#string STR_MISC_SYSTEM_OPTION_EN_US #language en-US "English (US)" diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemOptionStringData.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemOptionStringData.c new file mode 100644 index 0000000000..5a3eca525a --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemOptionStringData.c @@ -0,0 +1,24 @@ +/** @file + Static data of System option string. + System option string is Miscellaneous for subclass type 10, SMBIOS type 13. + + Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" + +// +// Static (possibly build generated) Bios Vendor data. +// +MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_OPTION_STRING_DATA, SystemOptionString) += { STRING_TOKEN(STR_MISC_SYSTEM_OPTION_EN_US) }; diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemOptionStringFunction.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemOptionStringFunction.c new file mode 100644 index 0000000000..5832fd5eb7 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemOptionStringFunction.c @@ -0,0 +1,86 @@ +/** @file + BIOS system option string boot time changes for SMBIOS type 12. + + Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" + +/** + This function makes boot time changes to the contents of the + MiscSystemOptionString (Type 12). + + @param RecordData Pointer to copy of RecordData from the Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +MISC_SMBIOS_TABLE_FUNCTION(SystemOptionString) +{ + CHAR8 *OptionalStrStart; + UINTN OptStrLen; + EFI_STRING OptionString; + EFI_STATUS Status; + STRING_REF TokenToGet; + EFI_SMBIOS_HANDLE SmbiosHandle; + SMBIOS_TABLE_TYPE12 *SmbiosRecord; + + // + // First check for invalid parameters. + // + if (RecordData == NULL) { + return EFI_INVALID_PARAMETER; + } + + TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_OPTION_EN_US); + OptionString = SmbiosMiscGetString (TokenToGet); + OptStrLen = StrLen(OptionString); + if (OptStrLen > SMBIOS_STRING_MAX_LENGTH) { + return EFI_UNSUPPORTED; + } + + // + // Two zeros following the last string. + // + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE12) + OptStrLen + 1 + 1); + ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE12) + OptStrLen + 1 + 1); + + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_SYSTEM_CONFIGURATION_OPTIONS; + SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE12); + + // + // Make handle chosen by smbios protocol.add automatically. + // + SmbiosRecord->Hdr.Handle = 0; + + SmbiosRecord->StringCount = 1; + OptionalStrStart = (CHAR8*) (SmbiosRecord + 1); + UnicodeStrToAsciiStr(OptionString, OptionalStrStart); + + // + // Now we have got the full smbios record, call smbios protocol to add this record. + // + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios->Add ( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord + ); + + FreePool(SmbiosRecord); + + return Status; +} diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemSlotDesignation.uni b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemSlotDesignation.uni new file mode 100644 index 0000000000..ab89aa4bb9 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemSlotDesignation.uni @@ -0,0 +1,31 @@ +// /** @file +// System slot information. +// +// Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// **/ + + +/=# + +#langdef en-US "English" +#string STR_MISC_SYSTEM_SLOT_PCIEX16 #language en-US "PCIE X16 SLOT" +#string STR_MISC_SYSTEM_SLOT_PCIEX16_1 #language en-US "PCIE X16 SLOT 1" +#string STR_MISC_SYSTEM_SLOT_PCIEX16_2 #language en-US "PCIE X16 SLOT 2" +#string STR_MISC_SYSTEM_SLOT_PCIEX4 #language en-US "PCIE X4 SLOT" +#string STR_MISC_SYSTEM_SLOT_PCIEX1_1 #language en-US "PCIE X1 SLOT 1" +#string STR_MISC_SYSTEM_SLOT_PCIEX1_2 #language en-US "PCIE X1 SLOT 2" +#string STR_MISC_SYSTEM_SLOT_PCIEX1_3 #language en-US "PCIE X1 SLOT 3" +#string STR_MISC_SYSTEM_SLOT_PCI1 #language en-US "PCI SLOT 1" +#string STR_MISC_SYSTEM_SLOT_PCI2 #language en-US "PCI SLOT 2" +#string STR_MISC_SYSTEM_SLOT_PCI3 #language en-US "PCI SLOT 3" + + diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemSlotDesignationData.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemSlotDesignationData.c new file mode 100644 index 0000000000..cfeb219065 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemSlotDesignationData.c @@ -0,0 +1,154 @@ +/** @file + Static data of System Slot Designation. + System Slot Designation is Misc for subclass type 7, SMBIOS type 9. + + Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CommonHeader.h" +#include "MiscSubclassDriver.h" + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE9, MiscSystemSlotPcie0) = { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE9), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_SYSTEM_SLOT_TOKEN_PCIE0, ///< SlotDesignation + SlotTypePciExpressX16, ///< SlotType + SlotDataBusWidth16X, ///< SlotDataBusWidth + SlotUsageAvailable, ///< SlotUsage + SlotLengthLong, ///< SlotLength + 0, ///< SlotId + { // SlotCharacteristics1 + 0, ///< Bit0 CharacteristicsUnknown :1 + 0, ///< Bit1 Provides50Volts :1 + 1, ///< Bit2 Provides33Volts :1 + 0, ///< Bit3 SharedSlot :1 + 0, ///< Bit4 PcCard16Supported :1 + 0, ///< Bit5 CardBusSupported :1 + 0, ///< Bit6 ZoomVideoSupported :1 + 0, ///< Bit7 ModemRingResumeSupported :1 + }, + { // SlotCharacteristics2 + 1, ///< Bit0 PmeSignalSupported :1 + 0, ///< Bit1 HotPlugDevicesSupported :1 + 1, ///< Bit2 SmbusSignalSupported :1 + 0 ///< Bit3-7 Reserved :5 + }, + 0, ///< SegmentGroupNum + PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, ///< BusNum + PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1 ///< DevFuncNum +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE9, MiscSystemSlotPcie1) = { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE9), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_SYSTEM_SLOT_TOKEN_PCIE1, ///< SlotDesignation + SlotTypePciExpress, ///< SlotType + SlotDataBusWidth1X, ///< SlotDataBusWidth + SlotUsageAvailable, ///< SlotUsage + SlotLengthLong, ///< SlotLength + 1, ///< SlotId + { // SlotCharacteristics1 + 0, ///< Bit0 CharacteristicsUnknown :1 + 0, ///< Bit1 Provides50Volts :1 + 1, ///< Bit2 Provides33Volts :1 + 0, ///< Bit3 SharedSlot :1 + 0, ///< Bit4 PcCard16Supported :1 + 0, ///< Bit5 CardBusSupported :1 + 0, ///< Bit6 ZoomVideoSupported :1 + 0, ///< Bit7 ModemRingResumeSupported :1 + }, + { // SlotCharacteristics2 + 1, ///< Bit0 PmeSignalSupported :1 + 0, ///< Bit1 HotPlugDevicesSupported :1 + 1, ///< Bit2 SmbusSignalSupported :1 + 0 ///< Bit3-7 Reserved :5 + }, + 0, ///< SegmentGroupNum + PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, ///< BusNum + PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2 ///< DevFuncNum +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE9, MiscSystemSlotPcie2) = { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE9), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_SYSTEM_SLOT_TOKEN_PCIE2, ///< SlotDesignation + SlotTypePciExpress, ///< SlotType + SlotDataBusWidth1X, ///< SlotDataBusWidth + SlotUsageAvailable, ///< SlotUsage + SlotLengthLong, ///< SlotLength + 2, ///< SlotId + { // SlotCharacteristics1 + 0, ///< Bit0 CharacteristicsUnknown :1 + 0, ///< Bit1 Provides50Volts :1 + 1, ///< Bit2 Provides33Volts :1 + 0, ///< Bit3 SharedSlot :1 + 0, ///< Bit4 PcCard16Supported :1 + 0, ///< Bit5 CardBusSupported :1 + 0, ///< Bit6 ZoomVideoSupported :1 + 0, ///< Bit7 ModemRingResumeSupported :1 + }, + { // SlotCharacteristics2 + 1, ///< Bit0 PmeSignalSupported :1 + 0, ///< Bit1 HotPlugDevicesSupported :1 + 1, ///< Bit2 SmbusSignalSupported :1 + 0 ///< Bit3-7 Reserved :5 + }, + 0, ///< SegmentGroupNum + PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, ///< BusNum + PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3 ///< DevFuncNum +}; + +MISC_SMBIOS_TABLE_DATA(SMBIOS_TABLE_TYPE9, MiscSystemSlotPcie3) = { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, ///< Hdr.Type + sizeof(SMBIOS_TABLE_TYPE9), ///< Hdr.Length + 0 ///< Hdr.Handle + }, + SMBIOS_MISC_SYSTEM_SLOT_TOKEN_PCIE3, ///< SlotDesignation + SlotTypePciExpress, ///< SlotType + SlotDataBusWidth1X, ///< SlotDataBusWidth + SlotUsageAvailable, ///< SlotUsage + SlotLengthLong, ///< SlotLength + 3, ///< SlotId + { // SlotCharacteristics1 + 0, ///< Bit0 CharacteristicsUnknown :1 + 0, ///< Bit1 Provides50Volts :1 + 1, ///< Bit2 Provides33Volts :1 + 0, ///< Bit3 SharedSlot :1 + 0, ///< Bit4 PcCard16Supported :1 + 0, ///< Bit5 CardBusSupported :1 + 0, ///< Bit6 ZoomVideoSupported :1 + 0, ///< Bit7 ModemRingResumeSupported :1 + }, + { // SlotCharacteristics2 + 1, ///< Bit0 PmeSignalSupported :1 + 0, ///< Bit1 HotPlugDevicesSupported :1 + 1, ///< Bit2 SmbusSignalSupported :1 + 0 ///< Bit3-7 Reserved :5 + }, + 0, ///< SegmentGroupNum + PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, ///< BusNum + PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4 ///< DevFuncNum +}; + +// +// PCIESC:RestrictedEnd +// diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemSlotDesignationFunction.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemSlotDesignationFunction.c new file mode 100644 index 0000000000..9ee55df89d --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/MiscSystemSlotDesignationFunction.c @@ -0,0 +1,108 @@ +/** @file + BIOS system slot designator information boot time changes for SMBIOS type 9. + + Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "MiscSubclassDriver.h" + +/** + This function makes boot time changes to the contents of the + MiscSystemSlotDesignator structure (Type 9). + + @param RecordData Pointer to copy of RecordData from the Data Table. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_UNSUPPORTED Unexpected RecordType value. + @retval EFI_INVALID_PARAMETER Invalid parameter was found. + +**/ +MISC_SMBIOS_TABLE_FUNCTION(MiscSystemSlotDesignator) +{ + CHAR8 *OptionalStrStart; + UINTN StringNumber; + UINTN StringLength; + EFI_STATUS Status; + SMBIOS_TABLE_TYPE9 *SmbiosRecord; + EFI_SMBIOS_HANDLE SmbiosHandle; + SMBIOS_TABLE_TYPE9 *ForType9InputData; + SMBIOS_TABLE_TYPE9_STRINGS SmbiosTableType9Strings; + CHAR16 *StrBufferStart; + CHAR16 *StrBufferPtr; + + // + // First check for invalid parameters. + // + if (RecordData == NULL) { + return EFI_INVALID_PARAMETER; + } + + DEBUG ((EFI_D_INFO, "(MiscSystemSlotDesignator) Entry.\n")); + ZeroMem (&SmbiosTableType9Strings, sizeof(SMBIOS_TABLE_TYPE9_STRINGS)); + StringNumber = 0; + StringLength = 0; + ForType9InputData = (SMBIOS_TABLE_TYPE9 *) RecordData; + StrBufferStart = AllocateZeroPool (1 * SMBIOS_STRING_MAX_LENGTH * sizeof(CHAR16)); + StrBufferPtr = StrBufferStart; + + // + // Initialize SMBIOS Tables Type9 strings + // + switch (ForType9InputData->SlotDesignation) { + case SMBIOS_MISC_SYSTEM_SLOT_TOKEN_PCIE0: + SmbiosStrInit (&SmbiosTableType9Strings.SlotDesignation, SMBIOS_MISC_SYSTEM_SLOT_PCIE0, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_SYSTEM_SLOT_TOKEN_PCIE1: + SmbiosStrInit (&SmbiosTableType9Strings.SlotDesignation, SMBIOS_MISC_SYSTEM_SLOT_PCIE1, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_SYSTEM_SLOT_TOKEN_PCIE2: + SmbiosStrInit (&SmbiosTableType9Strings.SlotDesignation, SMBIOS_MISC_SYSTEM_SLOT_PCIE2, &StrBufferPtr, &StringNumber, &StringLength); + break; + case SMBIOS_MISC_SYSTEM_SLOT_TOKEN_PCIE3: + SmbiosStrInit (&SmbiosTableType9Strings.SlotDesignation, SMBIOS_MISC_SYSTEM_SLOT_PCIE3, &StrBufferPtr, &StringNumber, &StringLength); + break; + default: + break; + } + ForType9InputData->SlotDesignation = SMBIOS_MISC_STRING_1; + + // + // Two zeros following the last string. + // + SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE9) + StringLength + StringNumber + 1); + if (SmbiosRecord == NULL) { + return EFI_OUT_OF_RESOURCES; + } + ZeroMem(SmbiosRecord, sizeof(SMBIOS_TABLE_TYPE9) + StringLength + StringNumber + 1); + CopyMem(SmbiosRecord, RecordData, sizeof(SMBIOS_TABLE_TYPE9)); + + // + // Update SMBIOS Tables Type9 strings + // + OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1); + SmbiosStringsUpdate ((CHAR16 **) &SmbiosTableType9Strings, OptionalStrStart, StringNumber); + + // + // Now we have got the full smbios record, call smbios protocol to add this record. + // + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios-> Add( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord + ); + + FreePool(SmbiosRecord); + FreePool(StrBufferStart); + return Status; +} diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmBiosCpu/Cache.h b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmBiosCpu/Cache.h new file mode 100644 index 0000000000..ba25d385ed --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmBiosCpu/Cache.h @@ -0,0 +1,328 @@ +/** @file + Include file for record cache subclass data with Smbios protocol. + + Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _CACHE_H_ +#define _CACHE_H_ + +#include +// +// Bit field definitions for return registers of CPUID EAX = 4 +// +// EAX +#define CPU_CACHE_TYPE_MASK 0x1F +#define CPU_CACHE_LEVEL_MASK 0xE0 +#define CPU_CACHE_LEVEL_SHIFT 5 +// EBX +#define CPU_CACHE_LINESIZE_MASK 0xFFF +#define CPU_CACHE_PARTITIONS_MASK 0x3FF000 +#define CPU_CACHE_PARTITIONS_SHIFT 12 +#define CPU_CACHE_WAYS_MASK 0xFFC00000 +#define CPU_CACHE_WAYS_SHIFT 22 + +#define CPU_CACHE_L1 1 +#define CPU_CACHE_L2 2 +#define CPU_CACHE_L3 3 +#define CPU_CACHE_L4 4 +#define CPU_CACHE_LMAX CPU_CACHE_L4 + + + +typedef struct { + UINT8 CacheLevel; + UINT8 CacheDescriptor; + UINT16 CacheSizeinKB; + CACHE_ASSOCIATIVITY_DATA Associativity; + CACHE_TYPE_DATA SystemCacheType; +} CPU_CACHE_CONVERTER; + + +typedef struct { + UINT16 CacheSizeinKB; + CACHE_ASSOCIATIVITY_DATA Associativity; + CACHE_TYPE_DATA SystemCacheType; + // + // Can extend the structure here. + // +} CPU_CACHE_DATA; + +// +// It is defined for SMBIOS_TABLE_TYPE7.CacheConfiguration. +// +typedef struct { + UINT16 Level :3; + UINT16 Socketed :1; + UINT16 Reserved2 :1; + UINT16 Location :2; + UINT16 Enable :1; + UINT16 OperationalMode :2; + UINT16 Reserved1 :6; +} CPU_CACHE_CONFIGURATION_DATA; + +CPU_CACHE_CONVERTER mCacheConverter[] = { + { + 1, + 0x06, + 8, + CacheAssociativity4Way, + CacheTypeInstruction + }, + { + 1, + 0x08, + 16, + CacheAssociativity4Way, + CacheTypeInstruction + }, + { + 1, + 0x0A, + 8, + CacheAssociativity2Way, + CacheTypeData + }, + { + 1, + 0x0C, + 16, + CacheAssociativity4Way, + CacheTypeData + }, + { + 3, + 0x22, + 512, + CacheAssociativity4Way, + CacheTypeUnified + }, + { + 3, + 0x23, + 1024, + CacheAssociativity8Way, + CacheTypeUnified + }, + { + 3, + 0x25, + 2048, + CacheAssociativity8Way, + CacheTypeUnified + }, + { + 3, + 0x29, + 4096, + CacheAssociativity8Way, + CacheTypeUnified + }, + { + 1, + 0x2C, + 32, + CacheAssociativity8Way, + CacheTypeData + }, + { + 1, + 0x30, + 32, + CacheAssociativity8Way, + CacheTypeInstruction + }, + { + 2, + 0x39, + 128, + CacheAssociativity4Way, + CacheTypeUnified + }, + { + 2, + 0x3B, + 128, + CacheAssociativity2Way, + CacheTypeUnified + }, + { + 2, + 0x3C, + 256, + CacheAssociativity4Way, + CacheTypeUnified + }, + { + 2, + 0x41, + 128, + CacheAssociativity4Way, + CacheTypeUnified + }, + { + 2, + 0x42, + 256, + CacheAssociativity4Way, + CacheTypeUnified + }, + { + 2, + 0x43, + 512, + CacheAssociativity4Way, + CacheTypeUnified + }, + { + 2, + 0x44, + 1024, + CacheAssociativity4Way, + CacheTypeUnified + }, + { + 2, + 0x45, + 2048, + CacheAssociativity4Way, + CacheTypeUnified + }, + { + 2, + 0x49, + 4096, + CacheAssociativity16Way, + CacheTypeUnified + }, + { + 1, + 0x60, + 16, + CacheAssociativity8Way, + CacheTypeData + }, + { + 1, + 0x66, + 8, + CacheAssociativity4Way, + CacheTypeData + }, + { + 1, + 0x67, + 16, + CacheAssociativity4Way, + CacheTypeData + }, + { + 1, + 0x68, + 32, + CacheAssociativity4Way, + CacheTypeData + }, + { + 2, + 0x78, + 1024, + CacheAssociativity4Way, + CacheTypeUnified + }, + { + 2, + 0x79, + 128, + CacheAssociativity8Way, + CacheTypeUnified + }, + { + 2, + 0x7A, + 256, + CacheAssociativity8Way, + CacheTypeUnified + }, + { + 2, + 0x7B, + 512, + CacheAssociativity8Way, + CacheTypeUnified + }, + { + 2, + 0x7C, + 1024, + CacheAssociativity8Way, + CacheTypeUnified + }, + { + 2, + 0x7D, + 2048, + CacheAssociativity8Way, + CacheTypeUnified + }, + { + 2, + 0x7F, + 512, + CacheAssociativity2Way, + CacheTypeUnified + }, + { + 2, + 0x82, + 256, + CacheAssociativity8Way, + CacheTypeUnified + }, + { + 2, + 0x83, + 512, + CacheAssociativity8Way, + CacheTypeUnified + }, + { + 2, + 0x84, + 1024, + CacheAssociativity8Way, + CacheTypeUnified + }, + { + 2, + 0x85, + 2048, + CacheAssociativity8Way, + CacheTypeUnified + }, + { + 2, + 0x86, + 512, + CacheAssociativity4Way, + CacheTypeUnified + }, + { + 2, + 0x87, + 1024, + CacheAssociativity8Way, + CacheTypeUnified + } +}; +#endif + diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmBiosCpu/Cpu.h b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmBiosCpu/Cpu.h new file mode 100644 index 0000000000..872492f4c3 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmBiosCpu/Cpu.h @@ -0,0 +1,289 @@ +/** @file + Include file for CPU DXE Module + + Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _CPU_DXE_H_ +#define _CPU_DXE_H_ + + +#define PLATFORM_DESKTOP 0 +#define PLATFORM_MOBILE 1 +#define PLATFORM_SERVER 2 + + +// +// The definitions below follow the naming rules. +// Definitions beginning with "B_" are bits within registers +// Definitions beginning with "N_" are the bit position +// Definitions with "_CPUID_" are CPUID bit fields +// Definitions with "_MSR_" are MSR bit fields +// Definitions with "N_*_START" are the bit start position +// Definitions with "N_*_STOP" are the bit stop position +// Definitions with "B_*_MASK" are the bit mask for the register values +// + +// +// Bit definitions for CPUID EAX = 1 +// +// ECX +#define N_CPUID_MONITOR_MWAIT_SUPPORT 3 +#define N_CPUID_VMX_SUPPORT 5 +#define N_CPUID_SMX_SUPPORT 6 +#define N_CPUID_EIST_SUPPORT 7 +#define N_CPUID_TM2_SUPPORT 8 +#define N_CPUID_DCA_SUPPORT 18 +#define N_CPUID_X2APIC_SUPPORT 21 +#define N_CPUID_AESNI_SUPPORT 25 +// EDX +#define N_CPUID_MCE_SUPPORT 7 +#define N_CPUID_MCA_SUPPORT 14 +#define N_CPUID_TM_SUPPORT 29 +#define N_CPUID_PBE_SUPPORT 31 + +// +// Bit definitions for CPUID EAX = 6 +// +// EAX +#define N_CPUID_TURBO_MODE_AVAILABLE 1 + +// +// Bit definitions for CPUID EAX = 80000001h +// +// EDX +#define N_CPUID_XD_BIT_AVAILABLE 20 + +// +// Bit definitions for MSR_IA32_APIC_BASE (ECX = 1Bh) +// +#define N_MSR_BSP_FLAG 8 +#define B_MSR_ENABLE_X2APIC_MODE BIT10 +#define N_MSR_ENABLE_X2APIC_MODE 10 +#define N_MSR_APIC_GLOBAL_ENABLE 11 + +// +// Bit definitions for MSR_EBC_SOFT_POWERON (ECX = 2Bh) +// +#define N_MSR_INITIATOR_MCERR_DISABLE 4 +#define N_MSR_INTERNAL_MCERR_DISABLE 5 +#define N_MSR_BINIT_DRIVER_DISABLE 6 + +// +// Bit definitions for MSR_EBC_FREQUENCY_ID (ECX = 2Ch) +// +#define N_MSR_SCALABLE_BUS_SPEED_START 16 +#define N_MSR_SCALABLE_BUS_SPEED_STOP 18 + +// +// Bit definitions for MSR_PIC_MSG_CONTROL (ECX = 2Eh) +// +#define N_MSR_APIC_TPR_UPD_MSG_DISABLE 10 + +// +// Bit definitions for MSR_IA32_FEATURE_CONTROL (ECX = 3Ah) +// +#define N_MSR_FEATURE_CONTROL_LOCK 0 +#define N_MSR_ENABLE_VMX_INSIDE_SMX 1 +#define N_MSR_ENABLE_VMX_OUTSIDE_SMX 2 +#define N_MSR_SENTER_LOCAL_FUNC_ENABLE_START 8 +#define N_MSR_SENTER_LOCAL_FUNC_ENABLE_STOP 14 +#define N_MSR_SENTER_GLOBAL_ENABLE 15 + +// +// Bit definitions for MSR_VLW_CONTROL (ECX = 4Bh) +// +#define N_MSR_A20M_DISABLE 1 + +// +// Bit definitions for MSR_PLATFORM_INFO (ECX = 0CEh) +// +#define N_MSR_MAX_NON_TURBO_RATIO_START 8 +#define N_MSR_MAX_NON_TURBO_RATIO_STOP 15 +#define B_MSR_PROGRAMMABLE_RATIO_LIMIT_TURBO_MODE BIT28 +#define B_MSR_PROGRAMMABLE_TDP_LIMIT_TURBO_MODE BIT29 +#define B_MSR_PROGRAMMABLE_TCC_ACTIVATION_OFFSET BIT30 +#define N_MSR_MAX_EFFICIENCY_RATIO_START 40 +#define N_MSR_MAX_EFFICIENCY_RATIO_STOP 47 +#define B_MSR_NO_OF_CONFIG_TDP_LEVELS (BIT34 | BIT33) + +// +// Bit definitions for MSR_PKG_CST_CONFIG_CONTROL (ECX = 0E2h) +// +#define B_MSR_PACKAGE_C_STATE_LIMIT_MASK 0x7 +#define B_MSR_IO_MWAIT_REDIRECTION_ENABLE BIT10 +#define N_MSR_EIST_HARDWARE_COORDINATION_DISABLE 11 +#define B_MSR_C3_STATE_AUTO_DEMOTION_ENABLE BIT25 +#define B_MSR_C1_STATE_AUTO_DEMOTION_ENABLE BIT26 + +// +// Bit definitions for MSR_FEATURE_CONFIG (ECX = 13Ch) +// +#define N_MSR_FEATURE_CONFIG_LOCK 0 +#define B_MSR_FEATURE_CONFIG_LOCK BIT0 +#define N_MSR_AESNI_DISABLE 1 + +// +// Bit definitions for MSR_IA32_MCG_CAP (ECX = 179h) +// +#define N_MSR_MCG_COUNT_START 0 +#define N_MSR_MCG_COUNT_STOP 7 +#define N_MSR_MCG_CTL_P 8 + +// +// Bit definitions for MSR_IA32_CLOCK_MODULATION (ECX = 19Ah) +// +#define N_MSR_CLOCK_MODULATION_DUTY_CYCLE_START 0 +#define N_MSR_CLOCK_MODULATION_DUTY_CYCLE_STOP 3 +#define B_MSR_CLOCK_MODULATION_DUTY_CYCLE_MASK 0xF +#define N_MSR_CLOCK_MODULATION_ENABLE 4 + +// +// Bit definitions for MSR_IA32_MISC_ENABLE (ECX = 1A0h) +// +#define N_MSR_FAST_STRINGS_ENABLE 0 +#define N_MSR_AUTOMATIC_TCC_ENABLE 3 +#define N_MSR_HW_PREFETCHER_DISABLE 9 +#define N_MSR_FERR_MULTIPLEXING_ENABLE 10 +#define N_MSR_TM2_ENABLE 13 +#define N_MSR_EIST_ENABLE 16 +#define N_MSR_ENABLE_MONITOR_FSM 18 +#define N_MSR_ADJACENT_CACHE_LINE_PREFETCH_DISABLE 19 +#define N_MSR_EIST_SELECT_LOCK 20 +#define N_MSR_LIMIT_CPUID_MAXVAL 22 +#define N_MSR_XD_BIT_DISABLE 34 +#define N_MSR_DCU_PREFETCHER_DISABLE 37 +#define N_MSR_TURBO_MODE_DISABLE 38 +#define N_MSR_IP_PREFETCHER_DISABLE 39 + +// +// Bit definitions for MSR_TEMPERATURE_TARGET (ECX = 1A2h) +// +#define N_MSR_TCC_ACTIVATION_OFFSET_START 24 +#define N_MSR_TCC_ACTIVATION_OFFSET_STOP 27 + +// +// Bit definitions for MSR_MISC_FEATURE_CONTROL (ECX = 1A4h) +// +#define N_MSR_MLC_STREAMER_PREFETCHER_DISABLE 0 +#define N_MSR_MLC_SPATIAL_PREFETCHER_DISABLE 1 +#define N_MSR_DCU_STREAMER_PREFETCHER_DISABLE 2 +#define N_MSR_DCU_IP_PREFETCHER_DISABLE 3 +#define N_MSR_THREE_STRIKE_COUNTER_DISABLE 11 + +// +// Bit definitions for MSR_MISC_PWR_MGMT (ECX = 1AAh) +// +#define N_MSR_EIST_HW_COORDINATION_DISABLE 0 +#define N_MSR_LOCK_TM_INTERRUPT 22 + +// +// Bit definitions for MSR_TURBO_POWER_CURRENT_LIMIT (ECX = 1ACh) +// +#define N_MSR_TDP_LIMIT_START 0 +#define N_MSR_TDP_LIMIT_STOP 14 +#define N_MSR_TDC_LIMIT_START 16 +#define N_MSR_TDC_LIMIT_STOP 30 + +// +// Bit definitions for MSR_TURBO_RATIO_LIMIT (ECX = 1ADh) +// +#define N_MSR_MAX_RATIO_LIMIT_1C_START 0 +#define N_MSR_MAX_RATIO_LIMIT_1C_STOP 7 + +// +// Bit definitions for MSR_IA32_ENERGY_PERFORMANCE_BIAS (ECX = 1B0h) +// +#define N_MSR_POWER_POLICY_PREFERENCE_START 0 +#define N_MSR_POWER_POLICY_PREFERENCE_STOP 3 + +// +// Bit definitions for MSR_IA32_PLATFORM_DCA_CAP (ECX = 1F8h) +// +#define N_MSR_DCA_TYPE0_ENABLE 0 + +// +// Bit definitions for MSR_IA32_CPU_DCA_CAP (ECX = 1F9h) +// +#define B_MSR_DCA_TYPE0_SUPPORTED BIT0 + +// +// Bit definitions for MSR_IA32_DCA_0_CAP (ECX = 1FAh) +// +#define N_MSR_SW_BLOCK 24 + +// +// Bit definitions for MSR_POWER_CTL (ECX = 1FCh) +// +#define N_MSR_BI_DIRECTIONAL_PROCHOT_ENABLE 0 +#define N_MSR_C1E_ENABLE 1 +#define N_MSR_IA32_ENERGY_PERF_BIAS_ACCESS_ENABLE 18 + +// +// Bit definitions for MSR_PACKAGE_POWER_SKU_UNIT (ECX = 606h) +// +#define N_MSR_POWER_UNIT_START 0 +#define N_MSR_POWER_UNIT_STOP 3 + +// +// Bit definitions for MSR_PACKAGE_POWER_LIMIT (ECX = 610h) +// +#define N_MSR_POWER_LIMIT_1_START 0 +#define N_MSR_POWER_LIMIT_1_STOP 14 + +// +// Bit definitions for MSR_IACORE_RATIOS (ECX = 66Ah) +// +#define N_MSR_LFM_RATIO_START 8 +#define N_MSR_LFM_RATIO_STOP 13 +#define N_MSR_GUAR_RATIO_START 16 +#define N_MSR_GUAR_RATIO_STOP 21 + +// +// Bit definitions for MSR_IACORE_VIDS (ECX = 66Bh) +// +#define N_MSR_LFM_VID_START 8 +#define N_MSR_LFM_VID_STOP 14 +#define N_MSR_GUAR_VID_START 16 +#define N_MSR_GUAR_VID_STOP 22 + +// +// Bit definitions for MSR_IACORE_TURBO_RATIOS (ECX = 66Ch) +// +#define M_MSR_MAX_RATIO_1C_MASK 0x3F + +// +// Bit definitions for MSR_IACORE_TURBO_VIDS (ECX = 66Dh) +// +#define B_MSR_MAX_VID_1C_MASK 0x7F + +// +// Bit definitions for Config TDP related MSRs +// +#define MSR_CONFIG_TDP_LVL1 0x649 +#define MSR_CONFIG_TDP_LVL2 0x64A +#define N_CONFIG_TDP_PKG_MIN_PWR 47 +#define B_CONFIG_TDP_PKG_MIN_PWR 0xFFFF // bits 62:47 +#define N_CONFIG_TDP_PKG_MAX_PWR 32 +#define B_CONFIG_TDP_PKG_MAX_PWR 0x7FFF // bits 46:32 +#define N_CONFIG_TDP_LVL_RATIO 16 +#define B_CONFIG_TDP_LVL_RATIO 0xFF +#define B_CONFIG_TDP_LVL_PKG_TDP 0x7FFF + +#define MSR_CONFIG_TDP_CONTROL 0x64B +#define B_CONFIG_TDP_CONTROL_LOCK (1 << 31) +#define B_CONFIG_TDP_CONTROL_LVL 0x3 +#define V_CONFIG_TDP_NOMINAL 0 +#define V_CONFIG_TDP_LEVEL1 1 +#define V_CONFIG_TDP_LEVEL2 2 + +#endif diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmBiosCpu/CpuConfigLib.h b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmBiosCpu/CpuConfigLib.h new file mode 100644 index 0000000000..99d6807bb9 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmBiosCpu/CpuConfigLib.h @@ -0,0 +1,685 @@ +/** @file + Public include file for the CPU Configuration Library + + Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _CPU_CONFIG_LIB_H_ +#define _CPU_CONFIG_LIB_H_ + +#include + +// +// Bits definition of PcdProcessorFeatureUserConfiguration, +// PcdProcessorFeatureCapability, and PcdProcessorFeatureSetting +// +#define PCD_CPU_HT_BIT 0x00000001 +#define PCD_CPU_CMP_BIT 0x00000002 +#define PCD_CPU_L2_CACHE_BIT 0x00000004 +#define PCD_CPU_L2_ECC_BIT 0x00000008 +#define PCD_CPU_VT_BIT 0x00000010 +#define PCD_CPU_LT_BIT 0x00000020 +#define PCD_CPU_EXECUTE_DISABLE_BIT 0x00000040 +#define PCD_CPU_L3_CACHE_BIT 0x00000080 +#define PCD_CPU_MAX_CPUID_VALUE_LIMIT_BIT 0x00000100 +#define PCD_CPU_FAST_STRING_BIT 0x00000200 +#define PCD_CPU_FERR_SIGNAL_BREAK_BIT 0x00000400 +#define PCD_CPU_PECI_BIT 0x00000800 +#define PCD_CPU_HARDWARE_PREFETCHER_BIT 0x00001000 +#define PCD_CPU_ADJACENT_CACHE_LINE_PREFETCH_BIT 0x00002000 +#define PCD_CPU_DCU_PREFETCHER_BIT 0x00004000 +#define PCD_CPU_IP_PREFETCHER_BIT 0x00008000 +#define PCD_CPU_MACHINE_CHECK_BIT 0x00010000 +#define PCD_CPU_THERMAL_MANAGEMENT_BIT 0x00040000 +#define PCD_CPU_EIST_BIT 0x00080000 +#define PCD_CPU_C1E_BIT 0x00200000 +#define PCD_CPU_C2E_BIT 0x00400000 +#define PCD_CPU_C3E_BIT 0x00800000 +#define PCD_CPU_C4E_BIT 0x01000000 +#define PCD_CPU_HARD_C4E_BIT 0x02000000 +#define PCD_CPU_DEEP_C4_BIT 0x04000000 +#define PCD_CPU_A20M_DISABLE_BIT 0x08000000 +#define PCD_CPU_MONITOR_MWAIT_BIT 0x10000000 +#define PCD_CPU_TSTATE_BIT 0x20000000 +#define PCD_CPU_TURBO_MODE_BIT 0x80000000 + +// +// Bits definition of PcdProcessorFeatureUserConfigurationEx1, +// PcdProcessorFeatureCapabilityEx1, and PcdProcessorFeatureSettingEx1 +// +#define PCD_CPU_C_STATE_BIT 0x00000001 +#define PCD_CPU_C1_AUTO_DEMOTION_BIT 0x00000002 +#define PCD_CPU_C3_AUTO_DEMOTION_BIT 0x00000004 +#define PCD_CPU_MLC_STREAMER_PREFETCHER_BIT 0x00000008 +#define PCD_CPU_MLC_SPATIAL_PREFETCHER_BIT 0x00000010 +#define PCD_CPU_THREE_STRIKE_COUNTER_BIT 0x00000020 +#define PCD_CPU_ENERGY_PERFORMANCE_BIAS_BIT 0x00000040 +#define PCD_CPU_DCA_BIT 0x00000080 +#define PCD_CPU_X2APIC_BIT 0x00000100 +#define PCD_CPU_AES_BIT 0x00000200 +#define PCD_CPU_APIC_TPR_UPDATE_MESSAGE_BIT 0x00000400 +#define PCD_CPU_SOCKET_ID_REASSIGNMENT_BIT 0x00000800 +#define PCD_CPU_PECI_DOWNSTREAM_WRITE_BIT 0x00001000 + +// +// Value definition for PcdCpuCallbackSignal +// +#define CPU_BYPASS_SIGNAL 0x00000000 +#define CPU_DATA_COLLECTION_SIGNAL 0x00000001 +#define CPU_PROCESSOR_FEATURE_LIST_CONFIG_SIGNAL 0x00000002 +#define CPU_REGISTER_TABLE_TRANSLATION_SIGNAL 0x00000003 +#define CPU_PROCESSOR_SETTING_SIGNAL 0x00000004 +#define CPU_PROCESSOR_SETTING_END_SIGNAL 0x00000005 + +typedef struct { + UINT32 RegEax; + UINT32 RegEbx; + UINT32 RegEcx; + UINT32 RegEdx; +} EFI_CPUID_REGISTER; + +// +// Enumeration of processor features +// +typedef enum { + Ht, + Cmp, + Vt, + ExecuteDisableBit, + L3Cache, + MaxCpuidValueLimit, + FastString, + FerrSignalBreak, + Peci, + HardwarePrefetcher, + AdjacentCacheLinePrefetch, + DcuPrefetcher, + IpPrefetcher, + ThermalManagement, + Eist, + BiDirectionalProchot, + Forcepr, + C1e, + C2e, + C3e, + C4e, + HardC4e, + DeepC4, + Microcode, + Microcode2, + MachineCheck, + GateA20MDisable, + MonitorMwait, + TState, + TurboMode, + CState, + C1AutoDemotion, + C3AutoDemotion, + MlcStreamerPrefetcher, + MlcSpatialPrefetcher, + ThreeStrikeCounter, + EnergyPerformanceBias, + Dca, + X2Apic, + Aes, + ApicTprUpdateMessage, + TccActivation, + PeciDownstreamWrite, + CpuFeatureMaximum +} CPU_FEATURE_ID; + +// +// Structure for collected processor feature capability, +// and feature-specific attribute. +// +typedef struct { + BOOLEAN Capability; + VOID *Attribute; +} CPU_FEATURE_DATA; + +// +// Structure for collected CPUID data. +// +typedef struct { + EFI_CPUID_REGISTER *CpuIdLeaf; + UINTN NumberOfBasicCpuidLeafs; + UINTN NumberOfExtendedCpuidLeafs; + UINTN NumberOfCacheAndTlbCpuidLeafs; + UINTN NumberOfDeterministicCacheParametersCpuidLeafs; + UINTN NumberOfExtendedTopologyEnumerationLeafs; +} CPU_CPUID_DATA; + +typedef struct { + UINTN Ratio; + UINTN Vid; + UINTN Power; + UINTN TransitionLatency; + UINTN BusMasterLatency; +} FVID_ENTRY; + +// +// Miscellaneous processor data +// +typedef struct { + // + // Local Apic Data + // + UINT32 InitialApicID; ///< Initial APIC ID + UINT32 ApicID; ///< Current APIC ID + EFI_PHYSICAL_ADDRESS ApicBase; + UINT32 ApicVersion; + // + // Frequency data + // + UINTN IntendedFsbFrequency; + UINTN ActualFsbFrequency; + BOOLEAN FrequencyLocked; + UINTN MaxCoreToBusRatio; + UINTN MinCoreToBusRatio; + UINTN MaxTurboRatio; + UINTN MaxVid; + UINTN MinVid; + UINTN PackageTdp; + UINTN CoreTdp; + UINTN NumberOfPStates; + FVID_ENTRY *FvidTable; + // + // Config TDP data + // + UINTN PkgMinPwrLvl1; + UINTN PkgMaxPwrLvl1; + UINTN ConfigTDPLvl1Ratio; + UINTN PkgTDPLvl1; + UINTN PkgMinPwrLvl2; + UINTN PkgMaxPwrLvl2; + UINTN ConfigTDPLvl2Ratio; + UINTN PkgTDPLvl2; + + // + // Other data + // + UINT32 PlatformRequirement; + UINT64 HealthData; + UINT32 MicrocodeRevision; +} CPU_MISC_DATA; + +// +// Structure for all collected processor data +// +typedef struct { + CPU_CPUID_DATA CpuidData; + EFI_CPU_PHYSICAL_LOCATION ProcessorLocation; + CPU_MISC_DATA CpuMiscData; + CPU_FEATURE_DATA FeatureData[CpuFeatureMaximum]; + UINT8 PackageIdBitOffset; + BOOLEAN PackageBsp; +} CPU_COLLECTED_DATA; + +#define GET_CPU_MISC_DATA(ProcessorNumber, Item) \ + ((mCpuConfigConextBuffer.CollectedDataBuffer[ProcessorNumber]).CpuMiscData.Item) + +// +// Signature for feature list entry +// +#define EFI_CPU_FEATURE_ENTRY_SIGNATURE SIGNATURE_32 ('C', 'f', 't', 'r') + +// +// Node of processor feature list +// +typedef struct { + UINT32 Signature; + CPU_FEATURE_ID FeatureID; + VOID *Attribute; + LIST_ENTRY Link; +} CPU_FEATURE_ENTRY; + +#define CPU_FEATURE_ENTRY_FROM_LINK(link) CR (link, CPU_FEATURE_ENTRY, Link, EFI_CPU_FEATURE_ENTRY_SIGNATURE) + +// +// Register types in register table +// +typedef enum _REGISTER_TYPE { + Msr, + ControlRegister, + MemoryMapped, + CacheControl +} REGISTER_TYPE; + +// +// Element of register table entry +// +typedef struct { + REGISTER_TYPE RegisterType; + UINT32 Index; + UINT8 ValidBitStart; + UINT8 ValidBitLength; + UINT64 Value; +} CPU_REGISTER_TABLE_ENTRY; + +// +// Register table definition, including current table length, +// allocated size of this table, and pointer to the list of table entries. +// +typedef struct { + UINT32 TableLength; + UINT32 NumberBeforeReset; + UINT32 AllocatedSize; + UINT32 InitialApicId; + CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry; +} CPU_REGISTER_TABLE; + +// +// Definition of Processor Configuration Context Buffer +// +typedef struct { + UINTN NumberOfProcessors; + UINTN BspNumber; + CPU_COLLECTED_DATA *CollectedDataBuffer; + LIST_ENTRY *FeatureLinkListEntry; + CPU_REGISTER_TABLE *PreSmmInitRegisterTable; + CPU_REGISTER_TABLE *RegisterTable; + UINTN *SettingSequence; +} CPU_CONFIG_CONTEXT_BUFFER; + +// +// Structure conveying socket ID configuration information. +// +typedef struct { + UINT8 DefaultSocketId; + UINT8 NewSocketId; +} CPU_SOCKET_ID_INFO; + + +/** + Set feature capability and related attribute. + + This function sets the feature capability and its attribute. + + @param ProcessorNumber Handle number of specified logical processor + @param FeatureID The ID of the feature. + @param Attribute Feature-specific data. + +**/ +VOID +EFIAPI +SetProcessorFeatureCapability ( + IN UINTN ProcessorNumber, + IN CPU_FEATURE_ID FeatureID, + IN VOID *Attribute + ); + +/** + Clears feature capability and related attribute. + + This function clears the feature capability and its attribute. + + @param ProcessorNumber Handle number of specified logical processor + @param FeatureID The ID of the feature. + +**/ +VOID +EFIAPI +ClearProcessorFeatureCapability ( + IN UINTN ProcessorNumber, + IN CPU_FEATURE_ID FeatureID + ); + +/** + Get feature capability and related attribute. + + This function gets the feature capability and its attribute. + + @param ProcessorNumber Handle number of specified logical processor + @param FeatureID The ID of the feature. + @param Attribute Pointer to the output feature-specific data. + + @retval TRUE The feature is supported by the processor + @retval FALSE The feature is not supported by the processor + +**/ +BOOLEAN +EFIAPI +GetProcessorFeatureCapability ( + IN UINTN ProcessorNumber, + IN CPU_FEATURE_ID FeatureID, + OUT VOID **Attribute OPTIONAL + ); + +typedef enum { + BasicCpuidLeaf, + ExtendedCpuidLeaf, + CacheAndTlbCpuidLeafs, + DeterministicCacheParametersCpuidLeafs, + ExtendedTopologyEnumerationCpuidLeafs +} CPUID_TYPE; + +/** + Get the number of CPUID leafs of various types. + + This function get the number of CPUID leafs of various types. + + @param ProcessorNumber Handle number of specified logical processor + @param CpuidType The type of the CPU id. + + @return Maximal index of CPUID instruction for basic leafs. + +**/ +UINTN +EFIAPI +GetNumberOfCpuidLeafs ( + IN UINTN ProcessorNumber, + IN CPUID_TYPE CpuidType + ); + +/** + Get the pointer to specified CPUID leaf. + + This function gets the pointer to specified CPUID leaf. + + @param ProcessorNumber Handle number of specified logical processor + @param Index Index of the CPUID leaf. + + @return Pointer to specified CPUID leaf + +**/ +EFI_CPUID_REGISTER* +EFIAPI +GetProcessorCpuid ( + IN UINTN ProcessorNumber, + IN UINTN Index + ); + +/** + Get the pointer to specified CPUID leaf of cache and TLB parameters. + + This function gets the pointer to specified CPUID leaf of cache and TLB parameters. + + @param ProcessorNumber Handle number of specified logical processor + @param Index Index of the CPUID leaf. + + @return Pointer to specified CPUID leaf. + +**/ +EFI_CPUID_REGISTER* +EFIAPI +GetCacheAndTlbCpuidLeaf ( + IN UINTN ProcessorNumber, + IN UINTN Index + ); + +/** + Get the pointer to specified CPUID leaf of deterministic cache parameters. + + This function gets the pointer to specified CPUID leaf of deterministic cache parameters. + + @param ProcessorNumber Handle number of specified logical processor + @param Index Index of the CPUID leaf. + + @return Pointer to specified CPUID leaf. + +**/ +EFI_CPUID_REGISTER* +EFIAPI +GetDeterministicCacheParametersCpuidLeaf ( + IN UINTN ProcessorNumber, + IN UINTN Index + ); + +/** + Get the pointer to specified CPUID leaf of Extended Topology Enumeration. + + This function gets the pointer to specified CPUID leaf of Extended Topology Enumeration. + + @param ProcessorNumber Handle number of specified logical processor. + @param Index Index of the CPUID leaf. + + @return Pointer to specified CPUID leaf. + +**/ +EFI_CPUID_REGISTER* +EFIAPI +GetExtendedTopologyEnumerationCpuidLeafs ( + IN UINTN ProcessorNumber, + IN UINTN Index + ); + +/** + Get the version information of specified logical processor. + + This function gets the version information of specified logical processor, + including family ID, model ID, stepping ID and processor type. + + @param ProcessorNumber Handle number of specified logical processor + @param DisplayedFamily Pointer to family ID for output + @param DisplayedModel Pointer to model ID for output + @param SteppingId Pointer to stepping ID for output + @param ProcessorType Pointer to processor type for output + +**/ +VOID +EFIAPI +GetProcessorVersionInfo ( + IN UINTN ProcessorNumber, + OUT UINT32 *DisplayedFamily OPTIONAL, + OUT UINT32 *DisplayedModel OPTIONAL, + OUT UINT32 *SteppingId OPTIONAL, + OUT UINT32 *ProcessorType OPTIONAL + ); + +/** + Get initial local APIC ID of specified logical processor + + This function gets initial local APIC ID of specified logical processor. + + @param ProcessorNumber Handle number of specified logical processor + + @return Initial local APIC ID of specified logical processor + +**/ +UINT32 +EFIAPI +GetInitialLocalApicId ( + UINTN ProcessorNumber + ); + +/** + Get the location of specified processor. + + This function gets the location of specified processor, including + package number, core number within package, thread number within core. + + @param ProcessorNumber Handle number of specified logical processor. + @param PackageNumber Pointer to the output package number. + @param CoreNumber Pointer to the output core number. + @param ThreadNumber Pointer to the output thread number. + +**/ +VOID +EFIAPI +GetProcessorLocation ( + IN UINTN ProcessorNumber, + OUT UINT32 *PackageNumber OPTIONAL, + OUT UINT32 *CoreNumber OPTIONAL, + OUT UINT32 *ThreadNumber OPTIONAL + ); + +/** + Get the Feature entry at specified position in a feature list. + + This function gets the Feature entry at specified position in a feature list. + + @param ProcessorNumber Handle number of specified logical processor + @param FeatureIndex The index of the node in feature list. + @param Attribute Pointer to output feature-specific attribute + + @return Feature ID of specified feature. CpuFeatureMaximum means not found + +**/ +CPU_FEATURE_ID +EFIAPI +GetProcessorFeatureEntry ( + IN UINTN ProcessorNumber, + IN UINTN FeatureIndex, + OUT VOID **Attribute OPTIONAL + ); + +/** + Append a feature entry at the end of a feature list. + + This function appends a feature entry at the end of a feature list. + + @param ProcessorNumber Handle number of specified logical processor + @param FeatureID ID of the specified feature. + @param Attribute Feature-specific attribute. + + @retval EFI_SUCCESS This function always return EFI_SUCCESS + +**/ +EFI_STATUS +EFIAPI +AppendProcessorFeatureIntoList ( + IN UINTN ProcessorNumber, + IN CPU_FEATURE_ID FeatureID, + IN VOID *Attribute + ); + +/** + Delete a feature entry in a feature list. + + This function deletes a feature entry in a feature list. + + @param ProcessorNumber Handle number of specified logical processor + @param FeatureIndex The index of the node in feature list. + + @retval EFI_SUCCESS The feature node successfully removed. + @retval EFI_INVALID_PARAMETER Index surpasses the length of list. + +**/ +EFI_STATUS +EFIAPI +DeleteProcessorFeatureFromList ( + IN UINTN ProcessorNumber, + IN UINTN FeatureIndex + ); + +/** + Insert a feature entry into a feature list. + + This function insert a feature entry into a feature list before a node specified by FeatureIndex. + + @param ProcessorNumber Handle number of specified logical processor + @param FeatureIndex The index of the new node in feature list. + @param FeatureID ID of the specified feature. + @param Attribute Feature-specific attribute. + + @retval EFI_SUCCESS The feature node successfully inserted. + @retval EFI_INVALID_PARAMETER Index surpasses the length of list. + +**/ +EFI_STATUS +EFIAPI +InsertProcessorFeatureIntoList ( + IN UINTN ProcessorNumber, + IN UINTN FeatureIndex, + IN CPU_FEATURE_ID FeatureID, + IN VOID *Attribute + ); + +/** + Add an entry in the post-SMM-init register table. + + This function adds an entry in the post-SMM-init register table, with given register type, + register index, bit section and value. + + @param ProcessorNumber Handle number of specified logical processor + @param RegisterType Type of the register to program + @param Index Index of the register to program + @param ValidBitStart Start of the bit section + @param ValidBitLength Length of the bit section + @param Value Value to write + +**/ +VOID +EFIAPI +WriteRegisterTable ( + IN UINTN ProcessorNumber, + IN REGISTER_TYPE RegisterType, + IN UINT32 Index, + IN UINT8 ValidBitStart, + IN UINT8 ValidBitLength, + IN UINT64 Value + ); + +/** + Add an entry in the pre-SMM-init register table. + + This function adds an entry in the pre-SMM-init register table, with given register type, + register index, bit section and value. + + @param ProcessorNumber Handle number of specified logical processor + @param RegisterType Type of the register to program + @param Index Index of the register to program + @param ValidBitStart Start of the bit section + @param ValidBitLength Length of the bit section + @param Value Value to write + +**/ +VOID +EFIAPI +WritePreSmmInitRegisterTable ( + IN UINTN ProcessorNumber, + IN REGISTER_TYPE RegisterType, + IN UINT32 Index, + IN UINT8 ValidBitStart, + IN UINT8 ValidBitLength, + IN UINT64 Value + ); + +/** + Set the sequence of processor setting. + + This function sets the a processor setting at the position in + setting sequence specified by Index. + + @param Index The zero-based index in the sequence. + @param ProcessorNumber Handle number of the processor to set. + + @retval EFI_SUCCESS The sequence successfully modified. + @retval EFI_INVALID_PARAMETER Index surpasses the boundary of sequence. + @retval EFI_NOT_FOUND Processor specified by ProcessorNumber does not exist. + +**/ +EFI_STATUS +SetSettingSequence ( + IN UINTN Index, + IN UINTN ProcessorNumber + ); + +/** + Set PcdCpuCallbackSignal, and then read the value back. + + This function sets PCD entry PcdCpuCallbackSignal. If there is callback + function registered on it, the callback function will be triggered, and + it may change the value of PcdCpuCallbackSignal. This function then reads + the value of PcdCpuCallbackSignal back, the check whether it has been changed. + + @param Value The value to set to PcdCpuCallbackSignal. + + @return The value of PcdCpuCallbackSignal read back. + +**/ +UINT8 +SetAndReadCpuCallbackSignal ( + IN UINT8 Value + ); + +#endif diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmBiosCpu/Processor.h b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmBiosCpu/Processor.h new file mode 100644 index 0000000000..d4a41d5b38 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmBiosCpu/Processor.h @@ -0,0 +1,60 @@ +/** @file + Include file for record processor subclass data with Smbios protocol. + + Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PROCESSOR_H_ +#define _PROCESSOR_H_ + +// +// This is the string tool generated data representing our strings. +// +extern EFI_SMBIOS_PROTOCOL *mSmbios; + +extern UINT32 mPopulatedSocketCount; + +// +// This constant defines the maximum length of the CPU brand string. According to the +// IA manual, the brand string is in EAX through EDX (thus 16 bytes) after executing +// the CPUID instructions with EAX as 80000002, 80000003, 80000004. +// +#define MAXIMUM_CPU_BRAND_STRING_LENGTH 48 + +typedef struct { + BOOLEAN StringValid; + CHAR16 BrandString[MAXIMUM_CPU_BRAND_STRING_LENGTH + 1]; + EFI_STRING_ID StringRef; +} CPU_PROCESSOR_VERSION_INFORMATION; + +// +// It is defined for SMBIOS_TABLE_TYPE4.Status. +// +typedef struct { + UINT8 CpuStatus :3; // Indicates the status of the processor. + UINT8 Reserved1 :3; // Reserved for future use. Should be set to zero. + UINT8 SocketPopulated :1; // Indicates if the processor socket is populated or not. + UINT8 Reserved2 :1; // Reserved for future use. Should be set to zero. +} CPU_PROCESSOR_STATUS_DATA; + +// +// It is defined for SMBIOS_TABLE_TYPE4.ProcessorCharacteristics. +// +typedef struct { + UINT16 Reserved :1; + UINT16 Unknown :1; + UINT16 Capable64Bit :1; + UINT16 Reserved2 :13; +} CPU_PROCESSOR_CHARACTERISTICS_DATA; + +#endif + diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmBiosCpu/SmBiosCpu.c b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmBiosCpu/SmBiosCpu.c new file mode 100644 index 0000000000..c67bcf9785 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmBiosCpu/SmBiosCpu.c @@ -0,0 +1,1491 @@ +/** @file + This driver will determine memory configuration information from the chipset + and memory and create SMBIOS memory structures appropriately. + + @par Revision Reference: + SMBIOS Specification version 2.8.0 from DMTF: http://www.dmtf.org/standards/smbios + Intel Framework Specifications, all available at: http://www.intel.com/technology/framework/spec.htm + - Data Hub Specification + - SMBUS Host Controller Protocol Specification + - Human Interface Infrastructure Specification + Unified Extensible Firmware Interface (UEFI) Specifications: http://www.uefi.org/specs/ + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "CpuConfigLib.h" +#include "Cache.h" +#include "Processor.h" +#include +#include +#include "Cpu.h" +#include "SocketLga1156Lib.h" +#include +#include +#include "MiscSubclassDriver.h" + +#define PLATFORM_DESKTOP 0 +#define PLATFORM_MOBILE 1 +#define PLATFORM_SERVER 2 + +UINTN mCpuSocketStrNumber = 1; +UINTN mCpuAssetTagStrNumber = 4; +extern UINT8 MiscSubclassStrings[]; +UINT8 mPlatformType = PLATFORM_MOBILE; +UINT32 mPopulatedSocketCount; +CPU_CONFIG_CONTEXT_BUFFER mCpuConfigConextBuffer; + +EFI_STRING_ID +GetProcessorManufacturer ( + IN UINTN ProcessorNumber + ); + +BOOLEAN +IsIntelProcessor ( + IN UINTN ProcessorNumber + ); + +/*********************************************************************************************************************** + *********************************************************************************************************************** + *************************************** The following functions are from CpuConfig.c ********************************** + *********************************************************************************************************************** + ***********************************************************************************************************************/ +/** + Get the location of specified processor. + + This function gets the location of specified processor, including + package number, core number within package, thread number within core. + + @param ProcessorNumber Handle number of specified logical processor. + @param PackageNumber Pointer to the output package number. + @param CoreNumber Pointer to the output core number. + @param ThreadNumber Pointer to the output thread number. + +**/ +VOID +EFIAPI +GetProcessorLocation ( + IN UINTN ProcessorNumber, + OUT UINT32 *PackageNumber OPTIONAL, + OUT UINT32 *CoreNumber OPTIONAL, + OUT UINT32 *ThreadNumber OPTIONAL +) +{ + CPU_COLLECTED_DATA *CpuCollectedData; + + CpuCollectedData = &mCpuConfigConextBuffer.CollectedDataBuffer[ProcessorNumber]; + + // + // If PackageNumber is not NULL, set the package number of the specified processor to it. + // + if (PackageNumber != NULL) { + *PackageNumber = CpuCollectedData->ProcessorLocation.Package; + } + + // + // If CoreNumber is not NULL, set the core number within package to it. + // + if (CoreNumber != NULL) { + *CoreNumber = CpuCollectedData->ProcessorLocation.Core; + } + + // + // If ThreadNumber is not NULL, set the thread number within core to it. + // + if (ThreadNumber != NULL) { + *ThreadNumber = CpuCollectedData->ProcessorLocation.Thread; + } +} + +/** + Get the pointer to specified CPUID leaf of Extended Topology Enumeration. + + This function gets the pointer to specified CPUID leaf of Extended Topology Enumeration. + + @param ProcessorNumber Handle number of specified logical processor. + @param Index Index of the CPUID leaf. + + @return Pointer to specified CPUID leaf. + +**/ +EFI_CPUID_REGISTER* +EFIAPI +GetExtendedTopologyEnumerationCpuidLeafs ( + IN UINTN ProcessorNumber, + IN UINTN Index + ) +{ + UINTN StartIndex; + CPU_CPUID_DATA *CpuidData; + + CpuidData = &(mCpuConfigConextBuffer.CollectedDataBuffer[ProcessorNumber].CpuidData); + + // + // Calculate the start index of Extended Topology Enumeration CPUID leafs. + // + StartIndex = CpuidData->NumberOfBasicCpuidLeafs; + StartIndex += CpuidData->NumberOfExtendedCpuidLeafs; + StartIndex += CpuidData->NumberOfCacheAndTlbCpuidLeafs - 1; + StartIndex += CpuidData->NumberOfDeterministicCacheParametersCpuidLeafs; + + return (&CpuidData->CpuIdLeaf[Index + StartIndex]); +} +/** + Get the pointer to specified CPUID leaf of deterministic cache parameters. + + This function gets the pointer to specified CPUID leaf of deterministic cache parameters. + + @param ProcessorNumber Handle number of specified logical processor + @param Index Index of the CPUID leaf. + + @return Pointer to specified CPUID leaf. + +**/ +EFI_CPUID_REGISTER* +EFIAPI +GetDeterministicCacheParametersCpuidLeaf ( + IN UINTN ProcessorNumber, + IN UINTN Index +) +{ + UINTN StartIndex; + CPU_CPUID_DATA *CpuidData; + + CpuidData = &(mCpuConfigConextBuffer.CollectedDataBuffer[ProcessorNumber].CpuidData); + + // + // Calculate the start index of deterministic cache CPUID leafs. + // + StartIndex = CpuidData->NumberOfBasicCpuidLeafs; + StartIndex += CpuidData->NumberOfExtendedCpuidLeafs; + StartIndex += CpuidData->NumberOfCacheAndTlbCpuidLeafs - 1; + + return (&CpuidData->CpuIdLeaf[Index + StartIndex]); +} + +/*********************************************************************************************************************** + *********************************************************************************************************************** + *************************************** The following functions are from ProcessorData.c ****************************** + *********************************************************************************************************************** + ***********************************************************************************************************************/ +/** + Returns the procesor version string token installed in the system. + + @param ProcessorNumber Processor number of specified processor. + @param Version Pointer to the output processor version. + +**/ +VOID +GetProcessorVersion ( + IN UINTN ProcessorNumber, + OUT CPU_PROCESSOR_VERSION_INFORMATION *Version + ) +{ + CHAR16 BrandIdString[MAXIMUM_CPU_BRAND_STRING_LENGTH + 1]; + EFI_CPUID_REGISTER *CpuBrandString; + UINT8 Index; + + // + // Create the string using Brand ID String. + // + Version->StringValid = FALSE; + + if (IsIntelProcessor (ProcessorNumber)) { + Version->StringRef = STRING_TOKEN (STR_INTEL_GENUINE_PROCESSOR); + + CpuBrandString = GetProcessorCpuid (ProcessorNumber, EFI_CPUID_BRAND_STRING1); + ASSERT (CpuBrandString != NULL); + + // + // Check if Brand ID String is supported or filled up + // + if (CpuBrandString->RegEax != 0) { + AsciiStrToUnicodeStr ((CHAR8 *) CpuBrandString, (CHAR16 *) &BrandIdString[0]); + + CpuBrandString = GetProcessorCpuid (ProcessorNumber, EFI_CPUID_BRAND_STRING2); + ASSERT (CpuBrandString != NULL); + AsciiStrToUnicodeStr ((CHAR8 *) CpuBrandString, (CHAR16 *) &BrandIdString[16]); + + CpuBrandString = GetProcessorCpuid (ProcessorNumber, EFI_CPUID_BRAND_STRING3); + ASSERT (CpuBrandString != NULL); + AsciiStrToUnicodeStr ((CHAR8 *) CpuBrandString, (CHAR16 *) &BrandIdString[32]); + + // + // Remove preceeding spaces + // + Index = 0; + while (((Index < MAXIMUM_CPU_BRAND_STRING_LENGTH) && (BrandIdString[Index] == 0x20)) != 0) { + Index++; + } + + ASSERT (Index <= MAXIMUM_CPU_BRAND_STRING_LENGTH); + CopyMem ( + Version->BrandString, + &BrandIdString[Index], + (MAXIMUM_CPU_BRAND_STRING_LENGTH - Index) * sizeof (CHAR16) + ); + Version->BrandString[MAXIMUM_CPU_BRAND_STRING_LENGTH - Index] = 0; + Version->StringValid = TRUE; + } + } else { + Version->StringRef = STRING_TOKEN (STR_UNKNOWN); + } +} + +/** + Returns the procesor manufaturer string token installed in the system. + + @param ProcessorNumber Processor number of specified processor. + + @return Processor Manufacturer string token. + +**/ +EFI_STRING_ID +GetProcessorManufacturer ( + IN UINTN ProcessorNumber + ) +{ + if (IsIntelProcessor (ProcessorNumber)) { + return STRING_TOKEN (STR_INTEL_CORPORATION); + } else { + return STRING_TOKEN (STR_UNKNOWN); + } +} + +/** + Checks if processor is Intel or not. + + @param ProcessorNumber Processor number of specified processor. + + @return TRUE Intel Processor. + @return FALSE Not Intel Processor. + +**/ +BOOLEAN +IsIntelProcessor ( + IN UINTN ProcessorNumber + ) +{ + EFI_CPUID_REGISTER *Reg; + + Reg = GetProcessorCpuid (ProcessorNumber, EFI_CPUID_SIGNATURE); + ASSERT (Reg != NULL); + + // + // After CPUID(0), check if EBX contians 'uneG', ECX contains 'letn', and EDX contains 'Ieni' + // + if ((Reg->RegEbx != 0x756e6547) || (Reg->RegEcx != 0x6c65746e) || (Reg->RegEdx != 0x49656e69)) { + return FALSE; + } else { + return TRUE; + } +} + +/** + Returns the processor family of the processor installed in the system. + + @param ProcessorNumber Processor number of specified processor. + + @return Processor Family + +**/ +PROCESSOR_FAMILY_DATA +GetProcessorFamily ( + IN UINTN ProcessorNumber + ) +{ + UINT32 FamilyId; + UINT32 ModelId; + + if (IsIntelProcessor (ProcessorNumber)) { + + GetProcessorVersionInfo (ProcessorNumber, &FamilyId, &ModelId, NULL, NULL); + + // + // If Merom or Conroe processor family + // + if (FamilyId == 0x06 && (ModelId == 0x0F || ModelId == 0x16)) { + switch (mPlatformType) { + case PLATFORM_DESKTOP: + return ProcessorFamilyIntelPentiumD; + + case PLATFORM_MOBILE: + return ProcessorFamilyIntelPentiumM; + + case PLATFORM_SERVER: + return ProcessorFamilyIntelXeon; + + default: + return ProcessorFamilyUnknown; + } + } + + // If Quark SoC X1000 family (Family=0x05 Model=0x09) + if (FamilyId == 0x05 && ModelId == 0x09) { + return ProcessorFamilyOther; + } + + return ProcessorFamilyPentium4; + } + + return ProcessorFamilyUnknown; +} +/** + Returns the processor voltage of the processor installed in the system. + + @param ProcessorNumber Processor number of specified processor. + + @return Processor Voltage in mV + +**/ +UINT16 +GetProcessorVoltage ( + IN UINTN ProcessorNumber + ) +{ + UINT16 VoltageInmV; + EFI_CPUID_REGISTER *Reg; + + Reg = GetProcessorCpuid (ProcessorNumber, EFI_CPUID_VERSION_INFO); + ASSERT (Reg != NULL); + + if ((Reg->RegEax >> 8 & 0x3F) == 0xF) { + VoltageInmV = 3000; + } else { + VoltageInmV = 1600; + } + + return VoltageInmV; +} + +/*********************************************************************************************************************** + *********************************************************************************************************************** + *************************************** The following functions are from CacheSubClass.c ****************************** + *********************************************************************************************************************** + ***********************************************************************************************************************/ +/** + Get cache data from CPUID EAX = 2. + + @param[in] ProcessorNumber Processor number of specified processor. + @param[out] CacheData Pointer to the cache data gotten from CPUID EAX = 2. + +**/ +VOID +GetCacheDataFromCpuid2 ( + IN UINTN ProcessorNumber, + OUT CPU_CACHE_DATA *CacheData + ) +{ + UINT8 CacheLevel; + EFI_CPUID_REGISTER *CacheInformation; + UINTN CacheDescriptorNum; + UINT32 RegPointer[4]; + UINT8 RegIndex; + UINT32 RegValue; + UINT8 ByteIndex; + UINT8 Descriptor; + UINTN DescriptorIndex; + + DEBUG ((EFI_D_INFO, "Get cache data from CPUID EAX = 2\n")); + + CacheDescriptorNum = (UINTN) (sizeof (mCacheConverter) / sizeof (mCacheConverter[0])); + CacheInformation = GetProcessorCpuid (ProcessorNumber, EFI_CPUID_CACHE_INFO); + ASSERT (CacheInformation != NULL); + + CopyMem (RegPointer, CacheInformation, sizeof (EFI_CPUID_REGISTER)); + RegPointer[0] &= 0xFFFFFF00; + + for (RegIndex = 0; RegIndex < 4; RegIndex++) { + RegValue = RegPointer[RegIndex]; + // + // The most significant bit (bit 31) of each register indicates whether the register + // contains valid information (set to 0) or is reserved (set to 1). + // + if ((RegValue & BIT31) != 0) { + continue; + } + + for (ByteIndex = 0; ByteIndex < 4; ByteIndex++) { + Descriptor = (UINT8) ((RegValue >> (ByteIndex * 8)) & 0xFF); + for (DescriptorIndex = 0; DescriptorIndex < CacheDescriptorNum; DescriptorIndex++) { + if (mCacheConverter[DescriptorIndex].CacheDescriptor == Descriptor) { + CacheLevel = mCacheConverter[DescriptorIndex].CacheLevel; // 1 based + ASSERT (CacheLevel >= 1 && CacheLevel <= CPU_CACHE_LMAX); + CacheData[CacheLevel - 1].CacheSizeinKB = (UINT16) (CacheData[CacheLevel - 1].CacheSizeinKB + mCacheConverter[DescriptorIndex].CacheSizeinKB); + CacheData[CacheLevel - 1].SystemCacheType = mCacheConverter[DescriptorIndex].SystemCacheType; + CacheData[CacheLevel - 1].Associativity = mCacheConverter[DescriptorIndex].Associativity; + } + } + } + } +} + +/** + Get cache data from CPUID EAX = 4. + + CPUID EAX = 4 is Deterministic Cache Parameters Leaf. + + @param[in] ProcessorNumber Processor number of specified processor. + @param[out] CacheData Pointer to the cache data gotten from CPUID EAX = 4. + +**/ +VOID +GetCacheDataFromCpuid4 ( + IN UINTN ProcessorNumber, + OUT CPU_CACHE_DATA *CacheData + ) +{ + EFI_CPUID_REGISTER *CpuidRegisters; + UINT8 Index; + UINT8 NumberOfDeterministicCacheParameters; + UINT32 Ways; + UINT32 Partitions; + UINT32 LineSize; + UINT32 Sets; + CACHE_TYPE_DATA SystemCacheType; + CACHE_ASSOCIATIVITY_DATA Associativity; + UINT8 CacheLevel; + UINT32 FamilyId; + UINT32 ModelId; + + DEBUG ((EFI_D_INFO, "Get cache data from CPUID EAX = 4\n")); + + // + // If Quark SoC X1000 chip, then force Cache record creation because CPUID Leaf 2 and 4 report 0. + // Quark SoC X1000 contains a 4-way set associative 16KB cache with a 16 byte cache line and 256 lines per tag. + // Quark SoC X1000 CPUID.(EAX=1):EAX = 0x00000590 (Family=0x05 Model = 0x09) + // + GetProcessorVersionInfo (ProcessorNumber, &FamilyId, &ModelId, NULL, NULL); + if (FamilyId == 0x05 && ModelId == 0x09) { + CacheLevel = 1; + ASSERT (CacheLevel >= 1 && CacheLevel <= CPU_CACHE_LMAX); + CacheData[CacheLevel - 1].CacheSizeinKB = 16; + CacheData[CacheLevel - 1].SystemCacheType = CacheTypeUnified; + CacheData[CacheLevel - 1].Associativity = CacheAssociativity4Way; + return; + } + + NumberOfDeterministicCacheParameters = (UINT8) GetNumberOfCpuidLeafs (ProcessorNumber, DeterministicCacheParametersCpuidLeafs); + + for (Index = 0; Index < NumberOfDeterministicCacheParameters; Index++) { + CpuidRegisters = GetDeterministicCacheParametersCpuidLeaf (ProcessorNumber, Index); + + if ((CpuidRegisters->RegEax & CPU_CACHE_TYPE_MASK) == 0) { + //break; + continue; + } + + switch (CpuidRegisters->RegEax & CPU_CACHE_TYPE_MASK) { + case 1: + SystemCacheType = CacheTypeData; + break; + case 2: + SystemCacheType = CacheTypeInstruction; + break; + case 3: + SystemCacheType = CacheTypeUnified; + break; + default: + SystemCacheType = CacheTypeUnknown; + } + + Ways = ((CpuidRegisters->RegEbx & CPU_CACHE_WAYS_MASK) >> CPU_CACHE_WAYS_SHIFT) + 1; + Partitions = ((CpuidRegisters->RegEbx & CPU_CACHE_PARTITIONS_MASK) >> CPU_CACHE_PARTITIONS_SHIFT) + 1; + LineSize = (CpuidRegisters->RegEbx & CPU_CACHE_LINESIZE_MASK) + 1; + Sets = CpuidRegisters->RegEcx + 1; + + switch (Ways) { + case 2: + Associativity = CacheAssociativity2Way; + break; + case 4: + Associativity = CacheAssociativity4Way; + break; + case 8: + Associativity = CacheAssociativity8Way; + break; + case 12: + Associativity = CacheAssociativity12Way; + break; + case 16: + Associativity = CacheAssociativity16Way; + break; + case 24: + Associativity = CacheAssociativity24Way; + break; + case 32: + Associativity = CacheAssociativity32Way; + break; + case 48: + Associativity = CacheAssociativity48Way; + break; + case 64: + Associativity = CacheAssociativity64Way; + break; + default: + Associativity = CacheAssociativityFully; + break; + } + + CacheLevel = (UINT8) ((CpuidRegisters->RegEax & CPU_CACHE_LEVEL_MASK) >> CPU_CACHE_LEVEL_SHIFT); // 1 based + ASSERT (CacheLevel >= 1 && CacheLevel <= CPU_CACHE_LMAX); + CacheData[CacheLevel - 1].CacheSizeinKB = (UINT16) (CacheData[CacheLevel - 1].CacheSizeinKB + (Ways * Partitions * LineSize * Sets) / 1024); + CacheData[CacheLevel - 1].SystemCacheType = SystemCacheType; + CacheData[CacheLevel - 1].Associativity = Associativity; + } + +} + +/*********************************************************************************************************************** + *********************************************************************************************************************** + *************************************** The following functions are from CpuConfig.c ********************************** + *********************************************************************************************************************** + ***********************************************************************************************************************/ +/** + Get the number of CPUID leafs of various types. + + This function get the number of CPUID leafs of various types. + + @param ProcessorNumber Handle number of specified logical processor + @param CpuidType The type of the cpu id. + + @return Maximal index of CPUID instruction for basic leafs. + +**/ +UINTN +EFIAPI +GetNumberOfCpuidLeafs ( + IN UINTN ProcessorNumber, + IN CPUID_TYPE CpuidType + ) +{ + UINTN NumberOfLeafs; + CPU_CPUID_DATA *CpuidData; + + CpuidData = &(mCpuConfigConextBuffer.CollectedDataBuffer[ProcessorNumber].CpuidData); + + switch (CpuidType) { + case BasicCpuidLeaf: + NumberOfLeafs = CpuidData->NumberOfBasicCpuidLeafs; + break; + case ExtendedCpuidLeaf: + NumberOfLeafs = CpuidData->NumberOfExtendedCpuidLeafs; + break; + case CacheAndTlbCpuidLeafs: + NumberOfLeafs = CpuidData->NumberOfCacheAndTlbCpuidLeafs; + break; + case DeterministicCacheParametersCpuidLeafs: + NumberOfLeafs = CpuidData->NumberOfDeterministicCacheParametersCpuidLeafs; + break; + case ExtendedTopologyEnumerationCpuidLeafs: + NumberOfLeafs = CpuidData->NumberOfExtendedTopologyEnumerationLeafs; + break; + default: + NumberOfLeafs = 0; + break; + } + + return NumberOfLeafs; +} + +/*********************************************************************************************************************** + *********************************************************************************************************************** + *************************************** The following functions are from DataCollection.c ***************************** + *********************************************************************************************************************** + ***********************************************************************************************************************/ +/** + Collects all CPUID leafs the processor. + + This function collects all CPUID leafs the processor. + + @param ProcessorNumber Handle number of specified logical processor + +**/ +VOID +CollectCpuidLeafs ( + UINTN ProcessorNumber + ) +{ + CPU_COLLECTED_DATA *CpuCollectedData; + EFI_CPUID_REGISTER *CpuidRegisters; + UINT32 Index; + + CpuCollectedData = &mCpuConfigConextBuffer.CollectedDataBuffer[ProcessorNumber]; + // + // Collect basic CPUID information. + // + CpuidRegisters = CpuCollectedData->CpuidData.CpuIdLeaf; + for (Index = 0; Index < GetNumberOfCpuidLeafs (ProcessorNumber, BasicCpuidLeaf); Index++) { + AsmCpuid ( + Index, + &CpuidRegisters->RegEax, + &CpuidRegisters->RegEbx, + &CpuidRegisters->RegEcx, + &CpuidRegisters->RegEdx + ); + CpuidRegisters++; + } + + // + // Collect extended function CPUID information. + // + for (Index = 0; Index < GetNumberOfCpuidLeafs (ProcessorNumber, ExtendedCpuidLeaf); Index++) { + AsmCpuid ( + Index + 0x80000000, + &CpuidRegisters->RegEax, + &CpuidRegisters->RegEbx, + &CpuidRegisters->RegEcx, + &CpuidRegisters->RegEdx + ); + CpuidRegisters++; + } + + // + // Collect additional Cache & TLB information, if exists. + // + for (Index = 1; Index < GetNumberOfCpuidLeafs (ProcessorNumber, CacheAndTlbCpuidLeafs); Index++) { + AsmCpuid ( + 2, + &CpuidRegisters->RegEax, + &CpuidRegisters->RegEbx, + &CpuidRegisters->RegEcx, + &CpuidRegisters->RegEdx + ); + CpuidRegisters++; + } + + // + // Collect Deterministic Cache Parameters Leaf. + // + for (Index = 0; Index < GetNumberOfCpuidLeafs (ProcessorNumber, DeterministicCacheParametersCpuidLeafs); Index++) { + AsmCpuidEx ( + 4, + Index, + &CpuidRegisters->RegEax, + &CpuidRegisters->RegEbx, + &CpuidRegisters->RegEcx, + &CpuidRegisters->RegEdx + ); + CpuidRegisters++; + } + + // + // Collect Extended Topology Enumeration Leaf. + // + for (Index = 0; Index < GetNumberOfCpuidLeafs (ProcessorNumber, ExtendedTopologyEnumerationCpuidLeafs); Index++) { + AsmCpuidEx ( + EFI_CPUID_CORE_TOPOLOGY, + Index, + &CpuidRegisters->RegEax, + &CpuidRegisters->RegEbx, + &CpuidRegisters->RegEcx, + &CpuidRegisters->RegEdx + ); + CpuidRegisters++; + } +} +/** + Checks the number of CPUID leafs need by a processor. + + This function check the number of CPUID leafs need by a processor. + + @param ProcessorNumber Handle number of specified logical processor. + +**/ +VOID +CountNumberOfCpuidLeafs ( + IN UINTN ProcessorNumber + ) +{ + UINT32 MaxCpuidIndex; + UINT32 MaxExtendedCpuidIndex; + UINT32 NumberOfCacheAndTlbRecords; + UINT32 NumberOfDeterministicCacheParametersLeafs; + UINT32 NumberOfExtendedTopologyEnumerationLeafs; + UINT32 RegValue; + CPU_COLLECTED_DATA *CpuCollectedData; + + CpuCollectedData = &mCpuConfigConextBuffer.CollectedDataBuffer[ProcessorNumber]; + + // + // Get the max index of basic CPUID + // + AsmCpuid (0, &MaxCpuidIndex, NULL, NULL, NULL); + // + // Get the max index of extended CPUID + // + AsmCpuid (0x80000000, &MaxExtendedCpuidIndex, NULL, NULL, NULL); + // + // Get the number of cache and TLB CPUID leafs + // + AsmCpuid (2, &NumberOfCacheAndTlbRecords, NULL, NULL, NULL); + NumberOfCacheAndTlbRecords = NumberOfCacheAndTlbRecords & 0xff; + + // + // Get the number of deterministic cache parameter CPUID leafs + // + NumberOfDeterministicCacheParametersLeafs = 0; + do { + AsmCpuidEx (4, NumberOfDeterministicCacheParametersLeafs++, &RegValue, NULL, NULL, NULL); + } while ((RegValue & 0x0f) != 0); + + // + // Get the number of Extended Topology Enumeration CPUID leafs + // + NumberOfExtendedTopologyEnumerationLeafs = 0; + if (MaxCpuidIndex >= EFI_CPUID_CORE_TOPOLOGY) { + do { + AsmCpuidEx (EFI_CPUID_CORE_TOPOLOGY, NumberOfExtendedTopologyEnumerationLeafs++, NULL, &RegValue, NULL, NULL); + } while ((RegValue & 0x0FFFF) != 0); + } + + // + // Save collected data in Processor Configuration Context Buffer + // + CpuCollectedData->CpuidData.NumberOfBasicCpuidLeafs = MaxCpuidIndex + 1; + CpuCollectedData->CpuidData.NumberOfExtendedCpuidLeafs = (MaxExtendedCpuidIndex - 0x80000000) + 1; + CpuCollectedData->CpuidData.NumberOfCacheAndTlbCpuidLeafs = NumberOfCacheAndTlbRecords; + CpuCollectedData->CpuidData.NumberOfDeterministicCacheParametersCpuidLeafs = NumberOfDeterministicCacheParametersLeafs; + CpuCollectedData->CpuidData.NumberOfExtendedTopologyEnumerationLeafs = NumberOfExtendedTopologyEnumerationLeafs; +} +/** + Checks the number of CPUID leafs of all logical processors, and allocate memory for them. + + This function checks the number of CPUID leafs of all logical processors, and allocates memory for them. + +**/ +VOID +AllocateMemoryForCpuidLeafs ( + VOID + ) +{ + CPU_COLLECTED_DATA *CpuCollectedData; + UINTN ProcessorNumber; + UINTN NumberOfLeafs; + + + // + // Allocate memory for CPUID leafs of all processors + // + for (ProcessorNumber = 0; ProcessorNumber < mCpuConfigConextBuffer.NumberOfProcessors; ProcessorNumber++) { + CpuCollectedData = &mCpuConfigConextBuffer.CollectedDataBuffer[ProcessorNumber]; + + // + // Get the number of basic CPUID leafs. + // + NumberOfLeafs = CpuCollectedData->CpuidData.NumberOfBasicCpuidLeafs; + // + // Get the number of extended CPUID leafs. + // + NumberOfLeafs += CpuCollectedData->CpuidData.NumberOfExtendedCpuidLeafs; + // + // Get the number of cache and TLB CPUID leafs. + // + NumberOfLeafs += CpuCollectedData->CpuidData.NumberOfCacheAndTlbCpuidLeafs - 1; + // + // Get the number of deterministic cache parameters CPUID leafs. + // + NumberOfLeafs += CpuCollectedData->CpuidData.NumberOfDeterministicCacheParametersCpuidLeafs; + // + // Get the number of Extended Topology Enumeration CPUID leafs + // + NumberOfLeafs += CpuCollectedData->CpuidData.NumberOfExtendedTopologyEnumerationLeafs; + + CpuCollectedData->CpuidData.CpuIdLeaf = AllocateZeroPool (sizeof (EFI_CPUID_REGISTER) * NumberOfLeafs); + } +} + +/** + Collects intended FSB frequency and core to bus ratio. + + This function collects intended FSB frequency and core to bus ratio. + + @param ProcessorNumber Handle number of specified logical processor + +**/ +VOID +CollectFrequencyData ( + UINTN ProcessorNumber + ) +{ + CPU_MISC_DATA *CpuMiscData; + UINT64 QWord; + UINT32 FamilyId; + UINT32 ModelId; + UINT32 SteppingId; + + CpuMiscData = &mCpuConfigConextBuffer.CollectedDataBuffer[ProcessorNumber].CpuMiscData; + CpuMiscData->FrequencyLocked = FALSE; + GetProcessorVersionInfo (ProcessorNumber, &FamilyId, &ModelId, &SteppingId, NULL); + + switch (FamilyId) { + case 0x06: + switch (ModelId) { + case 0x4C: + QWord = AsmReadMsr64 (0x66A); + CpuMiscData->MinCoreToBusRatio = (UINTN) BitFieldRead64 (QWord, 8, 15); + CpuMiscData->MaxCoreToBusRatio = (UINTN) BitFieldRead64 (QWord, 16, 23); + + // + // Collect VID + // + QWord = AsmReadMsr64 (0x66B); + CpuMiscData->MinVid = (UINTN) BitFieldRead64 (QWord, 8, 15); + CpuMiscData->MaxVid = (UINTN) BitFieldRead64 (QWord, 16, 23); + QWord = AsmReadMsr64 (0x66C); + CpuMiscData->MaxTurboRatio = (UINTN) BitFieldRead64 (QWord, 0, 7); + + default: + break; + } + break; + default: + break; + } + + // + // Collect intended FSB frequency + // + CpuMiscData->IntendedFsbFrequency = 80; + + // + // Default number of P-states is 1 + // + CpuMiscData->NumberOfPStates = 1; +} + +/*********************************************************************************************************************** + *********************************************************************************************************************** + *************************************** The following functions are from CacheSubClass.c ****************************** + *********************************************************************************************************************** + ***********************************************************************************************************************/ +/** + Add Type 7 SMBIOS Record for Cache Information. + + @param[in] ProcessorNumber Processor number of specified processor. + @param[out] L1CacheHandle Pointer to the handle of the L1 Cache SMBIOS record. + @param[out] L2CacheHandle Pointer to the handle of the L2 Cache SMBIOS record. + @param[out] L3CacheHandle Pointer to the handle of the L3 Cache SMBIOS record. + +**/ +VOID +AddSmbiosCacheTypeTable ( + IN EFI_SMBIOS_PROTOCOL *Smbios, + IN UINTN ProcessorNumber, + OUT EFI_SMBIOS_HANDLE *L1CacheHandle, + OUT EFI_SMBIOS_HANDLE *L2CacheHandle, + OUT EFI_SMBIOS_HANDLE *L3CacheHandle + ) +{ + EFI_STATUS Status; + SMBIOS_TABLE_TYPE7 *SmbiosRecord; + EFI_SMBIOS_HANDLE SmbiosHandle; + UINT8 CacheLevel; + CPU_CACHE_DATA CacheData[CPU_CACHE_LMAX]; + CHAR8 *OptionalStrStart; + UINTN StringBufferSize; + UINTN CacheSocketStrLen; + EFI_STRING CacheSocketStr; + CACHE_SRAM_TYPE_DATA CacheSramType; + CPU_CACHE_CONFIGURATION_DATA CacheConfig; + + ZeroMem (CacheData, CPU_CACHE_LMAX * sizeof (CPU_CACHE_DATA)); + // + // Check whether the CPU supports CPUID EAX = 4, if yes, get cache data from CPUID EAX = 4, + // or no, get cache data from CPUID EAX = 2 to be compatible with the earlier CPU. + // + if (GetNumberOfCpuidLeafs (ProcessorNumber, BasicCpuidLeaf) > 4 ) { + GetCacheDataFromCpuid4 (ProcessorNumber, CacheData); + } else { + GetCacheDataFromCpuid2 (ProcessorNumber, CacheData); + } + + // + // Now cache data has been ready. + // + for (CacheLevel = 0; CacheLevel < CPU_CACHE_LMAX; CacheLevel++) { + // + // NO smbios record for zero-sized cache. + // + if (CacheData[CacheLevel].CacheSizeinKB == 0) { + continue; + } + + DEBUG (( + EFI_D_INFO, + "CacheData: CacheLevel = 0x%x CacheSizeinKB = 0x%xKB SystemCacheType = 0x%x Associativity = 0x%x\n", + CacheLevel + 1, + CacheData[CacheLevel].CacheSizeinKB, + CacheData[CacheLevel].SystemCacheType, + CacheData[CacheLevel].Associativity + )); + + + StringBufferSize = sizeof (CHAR16) * SMBIOS_STRING_MAX_LENGTH; + CacheSocketStr = AllocateZeroPool (StringBufferSize); + ASSERT (CacheSocketStr != NULL); + CacheSocketStrLen = UnicodeSPrint (CacheSocketStr, StringBufferSize, L"L%x-Cache", CacheLevel + 1); + ASSERT (CacheSocketStrLen <= SMBIOS_STRING_MAX_LENGTH); + + // + // Report Cache Information to Type 7 SMBIOS Record. + // + + SmbiosRecord = AllocatePool (sizeof (SMBIOS_TABLE_TYPE7) + CacheSocketStrLen + 1 + 1); + ASSERT (SmbiosRecord != NULL); + ZeroMem (SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE7) + CacheSocketStrLen + 1 + 1); + + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_CACHE_INFORMATION; + SmbiosRecord->Hdr.Length = (UINT8) sizeof (SMBIOS_TABLE_TYPE7); + // + // Make handle chosen by smbios protocol.add automatically. + // + SmbiosRecord->Hdr.Handle = 0; + // + // Socket will be the 1st optional string following the formatted structure. + // + SmbiosRecord->SocketDesignation = 1; + + // + // Cache Level - 1 through 8, e.g. an L1 cache would use value 000b and an L3 cache would use 010b. + // + CacheConfig.Level = CacheLevel; + CacheConfig.Socketed = 0; // Not Socketed + CacheConfig.Reserved2 = 0; + CacheConfig.Location = 0; // Internal Cache + CacheConfig.Enable = 1; // Cache enabled + CacheConfig.OperationalMode = 1; // Write Back + CacheConfig.Reserved1 = 0; + CopyMem (&SmbiosRecord->CacheConfiguration, &CacheConfig, 2); + // + // Only 1K granularity assumed here. + // + SmbiosRecord->MaximumCacheSize = CacheData[CacheLevel].CacheSizeinKB; + SmbiosRecord->InstalledSize = CacheData[CacheLevel].CacheSizeinKB; + + ZeroMem (&CacheSramType, sizeof (CACHE_SRAM_TYPE_DATA)); + CacheSramType.Synchronous = 1; + CopyMem (&SmbiosRecord->SupportedSRAMType, &CacheSramType, 2); + CopyMem (&SmbiosRecord->CurrentSRAMType, &CacheSramType, 2); + + SmbiosRecord->CacheSpeed = 0; + SmbiosRecord->ErrorCorrectionType = CacheErrorSingleBit; + SmbiosRecord->SystemCacheType = (UINT8) CacheData[CacheLevel].SystemCacheType; + SmbiosRecord->Associativity = (UINT8) CacheData[CacheLevel].Associativity; + + OptionalStrStart = (CHAR8 *) (SmbiosRecord + 1); + UnicodeStrToAsciiStr (CacheSocketStr, OptionalStrStart); + + // + // Now we have got the full smbios record, call smbios protocol to add this record. + // + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios->Add ( Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER*) SmbiosRecord + ); + + // + // Record L1/L2/L3 Cache Smbios Handle, Type 4 SMBIOS Record needs it. + // + if (CacheLevel + 1 == CPU_CACHE_L1) { + *L1CacheHandle = SmbiosHandle; + } else if (CacheLevel + 1 == CPU_CACHE_L2) { + *L2CacheHandle = SmbiosHandle; + } else if (CacheLevel + 1 == CPU_CACHE_L3) { + *L3CacheHandle = SmbiosHandle; + } + FreePool (SmbiosRecord); + FreePool (CacheSocketStr); + ASSERT_EFI_ERROR (Status); + } +} + +/*********************************************************************************************************************** + *********************************************************************************************************************** + *************************************** The following functions are from CpuConfig.c ********************************** + *********************************************************************************************************************** + ***********************************************************************************************************************/ +/** + Get the pointer to specified CPUID leaf. + + This function gets the pointer to specified CPUID leaf. + + @param ProcessorNumber Handle number of specified logical processor + @param Index Index of the CPUID leaf. + + @return Pointer to specified CPUID leaf + +**/ +EFI_CPUID_REGISTER* +EFIAPI +GetProcessorCpuid ( + IN UINTN ProcessorNumber, + IN UINTN Index +) +{ + CPU_CPUID_DATA *CpuidData; + + CpuidData = &(mCpuConfigConextBuffer.CollectedDataBuffer[ProcessorNumber].CpuidData); + + // + // If Index specifies basic CPUID leafs, then locate basic leaf to return. + // + if (Index < CpuidData->NumberOfBasicCpuidLeafs) { + return (&CpuidData->CpuIdLeaf[Index]); + } + + // + // If Index specifies extended CPUID leafs, then locate extended leaf to return. + // + if (Index >= 0x80000000 && Index < 0x80000000 + CpuidData->NumberOfExtendedCpuidLeafs) { + return (&CpuidData->CpuIdLeaf[Index - 0x80000000 + CpuidData->NumberOfBasicCpuidLeafs]); + } + + // + // If Index specifies invalid CPUID index, then return NULL. + // + return NULL; +} + +/** + Get the version information of specified logical processor. + + This function gets the version information of specified logical processor, + including family ID, model ID, stepping ID and processor type. + + @param ProcessorNumber Handle number of specified logical processor + @param DisplayedFamily Pointer to family ID for output + @param DisplayedModel Pointer to model ID for output + @param SteppingId Pointer to stepping ID for output + @param ProcessorType Pointer to processor type for output + +**/ +VOID +EFIAPI +GetProcessorVersionInfo ( + IN UINTN ProcessorNumber, + OUT UINT32 *DisplayedFamily OPTIONAL, + OUT UINT32 *DisplayedModel OPTIONAL, + OUT UINT32 *SteppingId OPTIONAL, + OUT UINT32 *ProcessorType OPTIONAL + ) +{ + EFI_CPUID_REGISTER *VersionInfo; + UINT32 RegEax; + UINT32 FamilyId; + UINT32 ExtendedFamilyId; + UINT32 ExtendedModelId; + + // + // Get CPUID(1).EAX + // + VersionInfo = GetProcessorCpuid (ProcessorNumber, EFI_CPUID_VERSION_INFO); + ASSERT (VersionInfo != NULL); + RegEax = VersionInfo->RegEax; + + // + // Processor Type is CPUID(1).EAX[12:13] + // + if (ProcessorType != NULL) { + *ProcessorType = BitFieldRead32 (RegEax, 12, 13); + } + + // + // Stepping ID is CPUID(1).EAX[0:3] + // + if (SteppingId != NULL) { + *SteppingId = BitFieldRead32 (RegEax, 0, 3); + } + + // + // The Extended Family ID needs to be examined only when the Family ID is 0FH. + // If Family ID is 0FH, Displayed Family ID = Family ID + Extended Family ID. + // Otherwise, Displayed Family ID is Family ID + // + FamilyId = BitFieldRead32 (RegEax, 8, 11); + if (DisplayedFamily != NULL) { + *DisplayedFamily = FamilyId; + if (FamilyId == 0x0f) { + ExtendedFamilyId = BitFieldRead32 (RegEax, 20, 27); + *DisplayedFamily += ExtendedFamilyId; + } + } + + // + // The Extended Model ID needs to be examined only when the Family ID is 06H or 0FH. + // If Family ID is 06H or 0FH, Displayed Model ID = Model ID + (Extended Model ID << 4). + // Otherwise, Displayed Model ID is Model ID. + // + if (DisplayedModel != NULL) { + *DisplayedModel = BitFieldRead32 (RegEax, 4, 7); + if (FamilyId == 0x06 || FamilyId == 0x0f) { + ExtendedModelId = BitFieldRead32 (RegEax, 16, 19); + *DisplayedModel += (ExtendedModelId << 4); + } + } +} + +/*********************************************************************************************************************** + *********************************************************************************************************************** + *************************************** The following functions are from ProcessorSubClass.c ************************* + *********************************************************************************************************************** + ***********************************************************************************************************************/ +/** + Add Processor Information to Type 4 SMBIOS Record for Socket Populated. + + @param[in] ProcessorNumber Processor number of specified processor. + @param[in] L1CacheHandle The handle of the L1 Cache SMBIOS record. + @param[in] L2CacheHandle The handle of the L2 Cache SMBIOS record. + @param[in] L3CacheHandle The handle of the L3 Cache SMBIOS record. + +**/ +VOID +AddSmbiosProcessorTypeTable ( + IN EFI_SMBIOS_PROTOCOL *Smbios, + IN UINTN ProcessorNumber, + IN EFI_SMBIOS_HANDLE L1CacheHandle, + IN EFI_SMBIOS_HANDLE L2CacheHandle, + IN EFI_SMBIOS_HANDLE L3CacheHandle + ) +{ + EFI_STATUS Status; + EFI_SMBIOS_HANDLE SmbiosHandle; + UINTN TotalSize; + EFI_STRING_ID Token; + CHAR8 *OptionalStrStart; + EFI_STRING CpuManuStr; + EFI_STRING CpuVerStr; + EFI_STRING CpuSocketStr; + EFI_STRING CpuAssetTagStr; + UINTN CpuManuStrLen; + UINTN CpuVerStrLen; + UINTN CpuSocketStrLen; + UINTN CpuAssetTagStrLen; + SMBIOS_TABLE_TYPE4 *SmbiosRecord; + EFI_CPUID_REGISTER *CpuidRegister; + UINT16 ProcessorVoltage; + CPU_PROCESSOR_VERSION_INFORMATION Version; + CPU_PROCESSOR_STATUS_DATA ProcessorStatus; + CPU_PROCESSOR_CHARACTERISTICS_DATA ProcessorCharacteristics; + UINT16 PackageThreadCount; + UINT16 CoreThreadCount; + UINT16 CoreCount; + UINT32 FamilyId; + UINT32 ModelId; + + CoreCount = 0; + PackageThreadCount = 0; + + GetProcessorVersionInfo (ProcessorNumber, &FamilyId, &ModelId, NULL, NULL); + + // + // Get CPU Socket string, it will be updated when PcdPlatformCpuSocketNames is set. + // + Token = STRING_TOKEN (STR_UNKNOWN); + CpuSocketStr = HiiGetPackageString (&gEfiCallerIdGuid, Token ,NULL); + ASSERT (CpuSocketStr != NULL); + CpuSocketStrLen = StrLen (CpuSocketStr); + ASSERT (CpuSocketStrLen <= SMBIOS_STRING_MAX_LENGTH); + + // + // Get CPU Manufacturer string. + // + Token = GetProcessorManufacturer (ProcessorNumber); + CpuManuStr = HiiGetPackageString (&gEfiCallerIdGuid, Token, NULL); + ASSERT (CpuManuStr != NULL); + CpuManuStrLen = StrLen (CpuManuStr); + ASSERT (CpuManuStrLen <= SMBIOS_STRING_MAX_LENGTH); + + // + // Get CPU Version string. + // + GetProcessorVersion (ProcessorNumber, &Version); + if (Version.StringValid) { + Token = HiiSetString (mHiiHandle, 0, Version.BrandString, NULL); + if (Token == 0) { + Token = Version.StringRef; + } + } else { + Token = Version.StringRef; + } + CpuVerStr = HiiGetPackageString (&gEfiCallerIdGuid, Token, NULL); + ASSERT (CpuVerStr != NULL); + CpuVerStrLen = StrLen (CpuVerStr); + ASSERT (CpuVerStrLen <= SMBIOS_STRING_MAX_LENGTH); + + // + // Get CPU Asset Tag string, it will be updated when PcdPlatformCpuAssetTags is set. + // + Token = STRING_TOKEN (STR_UNKNOWN); + CpuAssetTagStr = HiiGetPackageString (&gEfiCallerIdGuid, Token ,NULL); + ASSERT (CpuAssetTagStr != NULL); + CpuAssetTagStrLen = StrLen (CpuAssetTagStr); + ASSERT (CpuAssetTagStrLen <= SMBIOS_STRING_MAX_LENGTH); + + // + // Get CPU core count. + // + if (GetNumberOfCpuidLeafs (ProcessorNumber, BasicCpuidLeaf) > EFI_CPUID_CORE_TOPOLOGY) { + CpuidRegister = GetExtendedTopologyEnumerationCpuidLeafs (ProcessorNumber, 1); + PackageThreadCount = (UINT16) (CpuidRegister->RegEbx); + CpuidRegister = GetExtendedTopologyEnumerationCpuidLeafs (ProcessorNumber, 0); + CoreThreadCount = (UINT16) (CpuidRegister->RegEbx); + CoreCount = PackageThreadCount / CoreThreadCount; + } else { + // + // Quark SoC X1000 CPUID.(EAX=1):EAX = 0x00000590 (Family=0x05 Model = 0x09) + // + if (FamilyId == 0x05 && ModelId == 0x09) { + PackageThreadCount = 1; + CoreThreadCount = 1; + CoreCount = PackageThreadCount / CoreThreadCount; + } + } + + // + // Report Processor Information to Type 4 SMBIOS Record. + // + + TotalSize = sizeof (SMBIOS_TABLE_TYPE4) + CpuSocketStrLen + 1 + CpuManuStrLen + 1 + CpuVerStrLen + 1 + CpuAssetTagStrLen + 1 + 1; + SmbiosRecord = AllocatePool (TotalSize); + ASSERT (SmbiosRecord != NULL); + ZeroMem (SmbiosRecord, TotalSize); + + SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION; + SmbiosRecord->Hdr.Length = (UINT8) sizeof (SMBIOS_TABLE_TYPE4); + // + // Make handle chosen by smbios protocol.add automatically. + // + SmbiosRecord->Hdr.Handle = 0; + // + // Socket will be the 1st optional string following the formatted structure. + // + SmbiosRecord->Socket = (UINT8) mCpuSocketStrNumber; + SmbiosRecord->ProcessorType = CentralProcessor; + SmbiosRecord->ProcessorFamily = (UINT8) GetProcessorFamily (ProcessorNumber); + // + // Manu will be the 2nd optional string following the formatted structure. + // + SmbiosRecord->ProcessorManufacture = 2; + + CpuidRegister = GetProcessorCpuid (ProcessorNumber, EFI_CPUID_VERSION_INFO); + ASSERT (CpuidRegister != NULL); + *(UINT32 *) &SmbiosRecord->ProcessorId.Signature = CpuidRegister->RegEax; + *(UINT32 *) &SmbiosRecord->ProcessorId.FeatureFlags = CpuidRegister->RegEdx; + + // + // Version will be the 3rd optional string following the formatted structure. + // + SmbiosRecord->ProcessorVersion = 3; + + ProcessorVoltage = GetProcessorVoltage (ProcessorNumber); // mV unit + ProcessorVoltage = (UINT16) ((ProcessorVoltage * 10) / 1000); + *(UINT8 *) &SmbiosRecord->Voltage = (UINT8) ProcessorVoltage; + SmbiosRecord->Voltage.ProcessorVoltageIndicateLegacy = 1; + + SmbiosRecord->ExternalClock = (UINT16) (GET_CPU_MISC_DATA (ProcessorNumber, IntendedFsbFrequency)); + SmbiosRecord->CurrentSpeed = (UINT16) (GET_CPU_MISC_DATA (ProcessorNumber, IntendedFsbFrequency) * GET_CPU_MISC_DATA (ProcessorNumber, MaxCoreToBusRatio)); + + ProcessorStatus.CpuStatus = 1; // CPU Enabled + ProcessorStatus.Reserved1 = 0; + ProcessorStatus.SocketPopulated = 1; // CPU Socket Populated + ProcessorStatus.Reserved2 = 0; + CopyMem (&SmbiosRecord->Status, &ProcessorStatus, 1); + + // + // Quark SoC X1000 CPUID.(EAX=1):EAX = 0x00000590 (Family=0x05 Model = 0x09) + // + if (FamilyId == 0x05 && ModelId == 0x09) { + SmbiosRecord->ProcessorUpgrade = ProcessorUpgradeNone; + } else { + SmbiosRecord->ProcessorUpgrade = ProcessorUpgradeSocketLGA775; + } + + SmbiosRecord->L1CacheHandle = L1CacheHandle; + SmbiosRecord->L2CacheHandle = L2CacheHandle; + SmbiosRecord->L3CacheHandle = L3CacheHandle; + + // + // AssetTag will be the 4th optional string following the formatted structure. + // + SmbiosRecord->AssetTag = (UINT8) mCpuAssetTagStrNumber; + + CoreCount = (CoreCount > 255) ? 0 : CoreCount; + PackageThreadCount = (PackageThreadCount > 255) ? 0 : PackageThreadCount; + SmbiosRecord->CoreCount = (UINT8) CoreCount; + SmbiosRecord->EnabledCoreCount = (UINT8) CoreCount; + SmbiosRecord->ThreadCount = (UINT8) PackageThreadCount; + + ProcessorCharacteristics.Reserved = 0; + ProcessorCharacteristics.Unknown = 0; + ProcessorCharacteristics.Reserved2 = 0; + // + // Quark SoC X1000 CPUID.(EAX=1):EAX = 0x00000590 (Family=0x05 Model = 0x09) + // + if (FamilyId == 0x05 && ModelId == 0x09) { + ProcessorCharacteristics.Capable64Bit = 0; + } else { + ProcessorCharacteristics.Capable64Bit = 1; + } + CopyMem (&SmbiosRecord->ProcessorCharacteristics, &ProcessorCharacteristics, 2); + + OptionalStrStart = (CHAR8 *) (SmbiosRecord + 1); + UnicodeStrToAsciiStr (CpuSocketStr, OptionalStrStart); + UnicodeStrToAsciiStr (CpuManuStr, OptionalStrStart + CpuSocketStrLen + 1); + UnicodeStrToAsciiStr (CpuVerStr, OptionalStrStart + CpuSocketStrLen + 1 + CpuManuStrLen + 1); + UnicodeStrToAsciiStr (CpuAssetTagStr, OptionalStrStart + CpuSocketStrLen + 1 + CpuManuStrLen + 1 + CpuVerStrLen + 1); + // + // Now we have got the full smbios record, call smbios protocol to add this record. + // + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios->Add ( Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER*) SmbiosRecord + ); + FreePool (SmbiosRecord); + FreePool (CpuSocketStr); + FreePool (CpuManuStr); + FreePool (CpuVerStr); + FreePool (CpuAssetTagStr); + ASSERT_EFI_ERROR (Status); +} + +EFI_STATUS +GetSmbiosCpuInformation ( EFI_SMBIOS_PROTOCOL *Smbios + ) +/*++ + + Routine Description: + + This function will get the CPU information to fill SMBIOS type4/type7. + + + Arguments: + + None + + Returns: + + EFI_SUCCESS if the data is successfully reported + EFI_NOT_FOUND if the HOB list could not be located. + +--*/ +{ + EFI_STATUS Status = EFI_SUCCESS; + EFI_MP_SERVICES_PROTOCOL *MpService; + UINTN MaximumNumberOfCPUs; + UINTN NumberOfEnabledCPUs; + UINT32 PreviousPackageNumber; + UINTN ProcessorIndex; + EFI_SMBIOS_HANDLE L1CacheHandle; + EFI_SMBIOS_HANDLE L2CacheHandle; + EFI_SMBIOS_HANDLE L3CacheHandle; + EFI_PROCESSOR_INFORMATION ProcessorInfoBuffer; + UINTN *SocketProcessorNumberTable; + UINT32 SocketIndex; + UINTN Index; + L1CacheHandle = 0xFFFF; + L2CacheHandle = 0xFFFF; + L3CacheHandle = 0xFFFF; + + Status = gBS->LocateProtocol ( + &gEfiMpServiceProtocolGuid, + NULL, + &MpService + ); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Determine the number of processors + // + MpService->GetNumberOfProcessors ( + MpService, + &MaximumNumberOfCPUs, + &NumberOfEnabledCPUs + ); + + SocketProcessorNumberTable = AllocateZeroPool (MaximumNumberOfCPUs * sizeof (UINTN)); + SocketProcessorNumberTable[0] = 0; + ASSERT (SocketProcessorNumberTable != NULL); + + // + // Initialize data for CPU configuration context buffer + // + mCpuConfigConextBuffer.BspNumber = 0; + mCpuConfigConextBuffer.NumberOfProcessors = NumberOfEnabledCPUs; + mCpuConfigConextBuffer.CollectedDataBuffer = AllocateZeroPool (sizeof (CPU_COLLECTED_DATA) * NumberOfEnabledCPUs); + + mCpuConfigConextBuffer.SettingSequence = (UINTN *) (((UINTN) mCpuConfigConextBuffer.RegisterTable) + (sizeof (CPU_REGISTER_TABLE) * NumberOfEnabledCPUs)); + + for (Index = 0; Index < NumberOfEnabledCPUs; Index++) { + mCpuConfigConextBuffer.SettingSequence[Index] = Index; + CountNumberOfCpuidLeafs (Index); + } + + // + // Check the number of CPUID leafs of all logical processors, and allocate memory for them. + // + AllocateMemoryForCpuidLeafs (); + for (Index = 0; Index < NumberOfEnabledCPUs; Index++) { + CollectCpuidLeafs (Index); + CollectFrequencyData(Index); + } + // + // System has 1 populated socket at least, initialize mPopulatedSocketCount to 1 and record ProcessorNumber 0 for it. + // + mPopulatedSocketCount = 1; + GetProcessorLocation (0, &PreviousPackageNumber, NULL, NULL); + // + // Scan and compare the processors' PackageNumber to find the populated sockets. + // + for (ProcessorIndex = 1; ProcessorIndex < NumberOfEnabledCPUs; ProcessorIndex++) { + Status = MpService->GetProcessorInfo ( + MpService, + ProcessorIndex, + &ProcessorInfoBuffer + ); + if (ProcessorInfoBuffer.Location.Package != PreviousPackageNumber) { + // + // Found a new populated socket. + // + PreviousPackageNumber = ProcessorInfoBuffer.Location.Package; + mPopulatedSocketCount++; + SocketProcessorNumberTable[mPopulatedSocketCount - 1] = ProcessorIndex; + } + } + + // + // Add SMBIOS tables for populated sockets. + // + for (SocketIndex = 0; SocketIndex < mPopulatedSocketCount; SocketIndex++) { + AddSmbiosCacheTypeTable (Smbios, SocketProcessorNumberTable[SocketIndex], &L1CacheHandle, &L2CacheHandle, &L3CacheHandle); + AddSmbiosProcessorTypeTable (Smbios, SocketProcessorNumberTable[SocketIndex], L1CacheHandle, L2CacheHandle, L3CacheHandle); + } + FreePool (SocketProcessorNumberTable); + FreePool (mCpuConfigConextBuffer.CollectedDataBuffer); + + return Status; +} diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmBiosCpu/SocketLga1156Lib.h b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmBiosCpu/SocketLga1156Lib.h new file mode 100644 index 0000000000..239485e85c --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmBiosCpu/SocketLga1156Lib.h @@ -0,0 +1,192 @@ +/** @file + Public include file for CPU definitions and CPU library functions that + apply to CPUs that fit into an LGA1156 spocket. + + Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SOCKET_LGA_1156_H_ +#define _SOCKET_LGA_1156_H_ + +#define EFI_CPUID_MONITOR_MWAIT_PARAMS 0x5 + +// +// Processor Family and Model information. +// +#define NEHALEM_FAMILY_ID 0x06 +#define BLOOMFIELD_MODEL_ID 0x1A +#define LYNNFIELD_MODEL_ID 0x1E +#define CLARKDALE_MODEL_ID 0x25 +#define TUNNELCREEK_MODEL_ID 0x26 +#define NEHALEM_EX_MODEL_ID 0x2E +#define WESTMERE_EX_MODEL_ID 0x2F + +#define SANDYBRIDGE_CLIENT_MODEL_ID 0x2A +#define SANDYBRIDGE_SERVER_MODEL_ID 0x2D + +#define VALLEYVIEW_MODEL_ID 0x37 +#define AVOTON_MODEL_ID 0x4D + +#define IVYBRIDGE_CLIENT_MODEL_ID 0x3A +#define IVYBRIDGE_SERVER_MODEL_ID 0x3E + +#define HASWELL_CLIENT_MODEL_ID 0x3C +#define HASWELL_SERVER_MODEL_ID 0x3F + +#define IS_NEHALEM_PROC(FamilyId, ModelId) \ + (FamilyId == NEHALEM_FAMILY_ID && \ + ( \ + ModelId == BLOOMFIELD_MODEL_ID || \ + ModelId == LYNNFIELD_MODEL_ID || \ + ModelId == CLARKDALE_MODEL_ID \ + ) \ + ) + +#define IS_NEHALEM_SERVER_PROC(FamilyId, ModelId) \ + (FamilyId == NEHALEM_FAMILY_ID && \ + ( \ + ModelId == NEHALEM_EX_MODEL_ID || \ + ModelId == WESTMERE_EX_MODEL_ID \ + ) \ + ) + +#define IS_TUNNELCREEK_PROC(FamilyId, ModelId) \ + (FamilyId == NEHALEM_FAMILY_ID && \ + ( \ + ModelId == TUNNELCREEK_MODEL_ID \ + ) \ + ) + +#define IS_SANDYBRIDGE_PROC(FamilyId, ModelId) \ + (FamilyId == NEHALEM_FAMILY_ID && \ + ( \ + ModelId == SANDYBRIDGE_CLIENT_MODEL_ID || \ + ModelId == SANDYBRIDGE_SERVER_MODEL_ID \ + ) \ + ) + +#define IS_SANDYBRIDGE_SERVER_PROC(FamilyId, ModelId) \ + (FamilyId == NEHALEM_FAMILY_ID && \ + ( \ + ModelId == SANDYBRIDGE_SERVER_MODEL_ID \ + ) \ + ) + + #define IS_SILVERMONT_PROC(FamilyId, ModelId) \ + (FamilyId == NEHALEM_FAMILY_ID && \ + ( \ + ModelId == VALLEYVIEW_MODEL_ID || \ + ModelId == AVOTON_MODEL_ID \ + ) \ + ) + + #define IS_VALLEYVIEW_PROC(FamilyId, ModelId) \ + (FamilyId == NEHALEM_FAMILY_ID && \ + ( \ + ModelId == VALLEYVIEW_MODEL_ID \ + ) \ + ) + + #define IS_AVOTON_PROC(FamilyId, ModelId) \ + (FamilyId == NEHALEM_FAMILY_ID && \ + ( \ + ModelId == AVOTON_MODEL_ID \ + ) \ + ) + +#define IS_IVYBRIDGE_PROC(FamilyId, ModelId) \ + (FamilyId == NEHALEM_FAMILY_ID && \ + ( \ + ModelId == IVYBRIDGE_CLIENT_MODEL_ID || \ + ModelId == IVYBRIDGE_SERVER_MODEL_ID \ + ) \ + ) + +#define IS_IVYBRIDGE_SERVER_PROC(FamilyId, ModelId) \ + (FamilyId == NEHALEM_FAMILY_ID && \ + ( \ + ModelId == IVYBRIDGE_SERVER_MODEL_ID \ + ) \ + ) + +#define IS_HASWELL_PROC(FamilyId, ModelId) \ + (FamilyId == NEHALEM_FAMILY_ID && \ + ( \ + ModelId == HASWELL_CLIENT_MODEL_ID || \ + ModelId == HASWELL_SERVER_MODEL_ID \ + ) \ + ) + +#define IS_HASWELL_SERVER_PROC(FamilyId, ModelId) \ + (FamilyId == NEHALEM_FAMILY_ID && \ + ( \ + ModelId == HASWELL_SERVER_MODEL_ID \ + ) \ + ) + +// +// Socket LGA1156 and LGA1366 based MSR definitions. +// +#define MSR_MONITOR_FILTER_SIZE 0x06 +#define MSR_CHL_CONTROLS 0x2D +#define MSR_PIC_MSG_CONTROL 0x2E +#define MSR_DCU_MODE 0x31 +#define MSR_CORE_THREAD_COUNT 0x35 +#define MSR_SOCKET_ID 0x39 +#define MSR_VLW_CONTROL 0x4B +#define MSR_QUIESCE_CONTROL 0x50 +#define MSR_PLATFORM_INFO 0xCE +#define MSR_PMG_CST_CONFIG_CONTROL 0xE2 +#define MSR_PMG_IO_CAPTURE_BASE 0xE4 +#define MSR_CPUID1_FEATURE_MASK 0x130 +#define MSR_CPUID80000001_FEATURE_MASK 0x131 +#define MSR_FEATURE_CONFIG 0x13C +#define MSR_PCID_ENABLE_FEATURE 0x13D +#define MSR_MCG_CONTAIN 0x178 +#define MSR_FLEX_RATIO 0x194 +#define MSR_IA32_CLOCK_MODULATION 0x19A +#define MSR_TEMPERATURE_TARGET 0x1A2 +#define MSR_MISC_FEATURE_CONTROL 0x1A4 +#define MSR_MISC_PWR_MGMT 0x1AA +#define MSR_TURBO_POWER_CURRENT_LIMIT 0x1AC + +#define MSR_IA32_ENERGY_PERFORMANCE_BIAS 0x1B0 +#define MSR_VLW_CAPABILITY 0x1F0 +#define MSR_FERR_CAPABILITY 0x1F1 +#define MSR_SMRR_PHYSBASE 0x1F2 +#define MSR_SMRR_PHYSMASK 0x1F3 +#define MSR_EMRR_PHYSBASE 0x1F4 +#define MSR_EMRR_PHYSMASK 0x1F5 +#define MSR_IA32_PLATFORM_DCA_CAP 0x1F8 +#define MSR_IA32_CPU_DCA_CAP 0x1F9 +#define MSR_IA32_DCA_0_CAP 0x1FA +#define MSR_NO_EVICT_MODE 0x2E0 +#define MSR_UNCORE_CR_MEMLOCK_COMMANDS 0x2E2 +#define MSR_UNCORE_CR_UNCORE_MC_CFG_CONTROL 0x2E3 +#define MSR_PCIEXBAR_MSR 0x300 +#define MSR_PKG_C3_RESIDENCY 0x3F8 +#define MSR_PKG_C6_RESIDENCY 0x3F9 +#define MSR_PKG_C7_RESIDENCY 0x3FA +#define MSR_CORE_C3_RESIDENCY 0x3FC +#define MSR_CORE_C6_RESIDENCY 0x3FD +#define MSR_CORE_C7_RESIDENCY 0x3FE + +#define MSR_PACKAGE_POWER_LIMIT 0x610 +#define MSR_PACKAGE_POWER_SKU_UNIT 0x606 +#define MSR_IACORE_TURBO_RATIOS 0x66C +#define MSR_IACORE_TURBO_VIDS 0x66D + +#define EFI_MSR_EBC_FREQUENCY_ID 0x2C +#define EFI_MSR_PSB_CLOCK_STATUS 0xCD +#define EFI_MSR_GV_THERM 0x19D + +#endif diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmBiosCpu/Strings.uni b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmBiosCpu/Strings.uni new file mode 100644 index 0000000000..ee3e2c7c7c --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmBiosCpu/Strings.uni @@ -0,0 +1,27 @@ +// /** @file +// String definition for Processor/Cache Subclass +// +// Copyright (c) 2015, Intel Corporation. All rights reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// **/ + + +/=# + +#langdef en-US "English" +#string STR_INTEL_GENUINE_PROCESSOR #language en-US "Intel(R) Genuine processor Test" +#string STR_UNKNOWN #language en-US "Unknown" +#string STR_INTEL_CORPORATION #language en-US "Intel(R) Corporation" + + + + + diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmbiosMiscDxe.inf b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmbiosMiscDxe.inf new file mode 100644 index 0000000000..277a196690 --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmbiosMiscDxe.inf @@ -0,0 +1,172 @@ +## @file +# Miscellaneous SMBIOS Strucure Module +# +# Provides SMBIOS information for some miscellaneous SMBIOS structures. These +# structures include type 0, 1, 3, 8, 9, 10, 11, 12, 13 and 32. Specific information +# for each of these structures can be located at DMTF.org. +# +# Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = MiscSubclass + FILE_GUID = BFD000AF-6485-4699-8446-DA527E7B483D + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = MiscSubclassDriverEntryPoint + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[Sources] + MiscBaseBoardManufacturer.uni + MiscBaseBoardManufacturerData.c + MiscBaseBoardManufacturerFunction.c + MiscBiosVendor.uni + MiscBiosVendorData.c + MiscBiosVendorFunction.c + MiscBootInformationData.c + MiscBootInformationFunction.c + MiscChassisManufacturer.uni + MiscChassisManufacturerData.c + MiscChassisManufacturerFunction.c + MiscNumberOfInstallableLanguagesData.c + MiscNumberOfInstallableLanguagesFunction.c + MiscOemString.uni + MiscOemStringData.c + MiscOemStringFunction.c + MiscOnboardDevice.uni + MiscOnboardDeviceData.c + MiscOnboardDeviceFunction.c + MiscPortInternalConnectorDesignator.uni + MiscPortInternalConnectorDesignatorData.c + MiscPortInternalConnectorDesignatorFunction.c + MiscResetCapabilitiesData.c + MiscResetCapabilitiesFunction.c + MiscSystemLanguageString.uni + MiscSystemLanguageStringData.c + MiscSystemLanguageStringFunction.c + MiscSystemManufacturer.uni + MiscSystemManufacturerData.c + MiscSystemManufacturerFunction.c + MiscSystemOptionString.uni + MiscSystemOptionStringData.c + MiscSystemOptionStringFunction.c + MiscSystemSlotDesignation.uni + MiscSystemSlotDesignationData.c + MiscSystemSlotDesignationFunction.c + MiscSubclassDriver.h + MiscSubclassDriver.uni + MiscSubclassDriverDataTable.c + MiscSubclassDriverEntryPoint.c + CommonHeader.h + MiscOemType0x90Function.c + MiscOemType0x90Data.c + MiscOemType0x90.uni + SmBiosCpu/SmBiosCpu.c + SmBiosCpu/Strings.uni + +[Packages] + MdeModulePkg/MdeModulePkg.dec + BraswellPlatformPkg/BraswellPlatformPkg.dec + MdePkg/MdePkg.dec + IntelFrameworkPkg/IntelFrameworkPkg.dec + ChvRefCodePkg/ChvRefCodePkg.dec + +[LibraryClasses] + HiiLib + DevicePathLib + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + UefiDriverEntryPoint + BaseMemoryLib + DebugLib + BaseLib + MemoryAllocationLib + PcdLib + UefiLib + PrintLib + CpuIA32Lib + PchPlatformLib + I2cLib + MemoryAllocationLib + +[Guids] + ## SOMETIMES_CONSUMES ## GUID + gEfiProcessorSubClassGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiCacheSubClassGuid + + +[Protocols] + ## CONSUMES + gEfiSmbiosProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDxeSmmReadyToLockProtocolGuid + + ## CONSUMES + gEfiPciRootBridgeIoProtocolGuid + ## CONSUMES + gEfiMpServiceProtocolGuid + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLang ## CONSUMES + + gEfiEdkIIPlatformTokenSpaceGuid.PcdPlatformInfo + gPlatformModuleTokenSpaceGuid.PcdSMBIOSBiosVersion ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdSMBIOSBiosReleaseDate ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdSMBIOSBiosStartAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize + gPlatformModuleTokenSpaceGuid.PcdSMBIOSBiosChar ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdSMBIOSBiosCharEx1 ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdSMBIOSBiosCharEx2 ## CONSUMES + + gPlatformModuleTokenSpaceGuid.PcdSMBIOSSystemManufacturer ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdSMBIOSSystemVersion ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdSMBIOSSystemSerialNumber ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdSMBIOSSystemUuid ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdSMBIOSSystemSKUNumber ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdSMBIOSSystemFamily ## CONSUMES + + gPlatformModuleTokenSpaceGuid.PcdSMBIOSBoardManufacturer ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdSMBIOSBoardVersion ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdSMBIOSBoardSerialNumber ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdSMBIOSBoardAssetTag ## CONSUMES + + gPlatformModuleTokenSpaceGuid.PcdSMBIOSChassisManufacturer ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdSMBIOSChassisVersion ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdSMBIOSChassisSerialNumber ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdSMBIOSChassisAssetTag ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdSMBIOSChassisBootupState ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdSMBIOSChassisPowerSupplyState ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdSMBIOSChassisSecurityState ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdSMBIOSChassisOemDefined ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdSMBIOSChassisHeight ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdSMBIOSChassisNumberPowerCords ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdSMBIOSChassisElementCount ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdSMBIOSChassisElementRecordLength ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision ## CONSUMES + +[PcdEx] + ## CONSUMES + gEfiEdkIIPlatformTokenSpaceGuid.PcdSystemConfiguration + +[Depex] + gEfiSmbiosProtocolGuid AND gEfiMpServiceProtocolGuid + diff --git a/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmbiosMiscStrings.h b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmbiosMiscStrings.h new file mode 100644 index 0000000000..e0f02f7e1e --- /dev/null +++ b/BraswellPlatformPkg/Common/Feature/SmBiosMiscDxe/SmbiosMiscStrings.h @@ -0,0 +1,410 @@ +/** @file + This driver will determine the default string settting for SMBIOS tables. + + @par Revision Reference: + SMBIOS Specification version 2.8.0 from DMTF: http://www.dmtf.org/standards/smbios + Intel Framework Specifications, all available at: http://www.intel.com/technology/framework/spec.htm + - Data Hub Specification + - SMBUS Host Controller Protocol Specification + - Human Interface Infrastructure Specification + Unified Extensible Firmware Interface (UEFI) Specifications: http://www.uefi.org/specs/ + + Copyright (c) 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SMBIOS_MISC_STRINGS_H_ +#define _SMBIOS_MISC_STRINGS_H_ +/// +/// String references in SMBIOS tables. This eliminates the need for pointers. +/// See the DMTF SMBIOS Specification v2.7.1, section 6.1.3. +/// +#define SMBIOS_MISC_STRING_NULL 0 +#define SMBIOS_MISC_STRING_1 1 +#define SMBIOS_MISC_STRING_2 2 +#define SMBIOS_MISC_STRING_3 3 +#define SMBIOS_MISC_STRING_4 4 +#define SMBIOS_MISC_STRING_5 5 +#define SMBIOS_MISC_STRING_6 6 +#define SMBIOS_MISC_STRING_7 7 +#define SMBIOS_MISC_STRING_8 8 +#define SMBIOS_MISC_STRING_9 9 +#define SMBIOS_MISC_STRING_10 10 +#define SMBIOS_MISC_STRING_11 11 +#define SMBIOS_MISC_STRING_12 12 +#define SMBIOS_MISC_STRING_13 13 +#define SMBIOS_MISC_STRING_14 14 +#define SMBIOS_MISC_STRING_15 15 +#define SMBIOS_MISC_STRING_16 16 +#define SMBIOS_MISC_STRING_17 17 +#define SMBIOS_MISC_STRING_18 18 +#define SMBIOS_MISC_STRING_19 19 +#define SMBIOS_MISC_STRING_20 20 +#define SMBIOS_MISC_STRING_21 21 +#define SMBIOS_MISC_STRING_22 22 + +/// +/// Non-static SMBIOS table data to be filled later with a dynamically generated value +/// +#define TO_BE_FILLED 0 +#define TO_BE_FILLED_STRING " " ///< Initial value should not be NULL +#define TO_BE_FILLED_BY_OEM_STR L"To Be Filled by O.E.M." + +/// +/// SMBIOS_TABLE_TYPE00 Default Strings +/// +/// +#define SMBIOS_MISC_TYPE00_VENDOR L"Intel Corporation" +#define SMBIOS_MISC_TYPE00_BIOS_VERSION L"Cherryview Platform BIOS" +#define SMBIOS_MISC_TYPE00_BIOS_RELEASE_DATE L"12/01/2015" + +typedef struct { + CHAR16 *Vendor; + CHAR16 *BiosVersion; + CHAR16 *BiosReleaseDate; +} SMBIOS_TABLE_TYPE00_STRINGS; + +/// +/// SMBIOS_TABLE_TYPE01 Default Strings +/// +#define SMBIOS_MISC_TYPE01_MANUFACTURER L"Intel Corporation" +#define SMBIOS_MISC_TYPE01_PRODUCT_NAME L"CHERRYVIEW Platform" +#define SMBIOS_MISC_TYPE01_VERSION L"0.1" +#define SMBIOS_MISC_TYPE01_SERIAL_NUMBER L"112233445566" +#define SMBIOS_MISC_TYPE01_SKU_NUMBER L"System SKUNumber" +#define SMBIOS_MISC_TYPE01_FAMILY L"Cherryview System" + +typedef struct { + CHAR16 *Manufacturer; + CHAR16 *ProductName; + CHAR16 *Version; + CHAR16 *SerialNumber; + CHAR16 *SkuNumber; + CHAR16 *Family; +} SMBIOS_TABLE_TYPE01_STRINGS; + +/// +/// SMBIOS_TABLE_TYPE02 Default Strings +/// +#define SMBIOS_MISC_TYPE02_BOARD_MANUFACTURER L"Intel Corp." +#define SMBIOS_MISC_TYPE02_BOARD_PRODUCT_NAME L"Braswell RVP" +#define SMBIOS_MISC_TYPE02_BOARD_VERSION L"FAB" +#define SMBIOS_MISC_TYPE02_BOARD_SERIAL_NUMBER L"1" +#define SMBIOS_MISC_TYPE02_BOARD_ASSET_TAG L"Base Board Asset Tag" +#define SMBIOS_MISC_TYPE02_BOARD_CHASSIS_LOCATION L"Part Component" + +typedef struct { + CHAR16 *Manufacturer; + CHAR16 *ProductName; + CHAR16 *Version; + CHAR16 *SerialNumber; + CHAR16 *AssetTag; + CHAR16 *LocationInChassis; +} SMBIOS_TABLE_TYPE02_STRINGS; + +/// +/// SMBIOS_TABLE_TYPE03 Default Strings +/// +#define SMBIOS_MISC_CHASSIS_MANUFACTURER L"Intel Corporation" +#define SMBIOS_MISC_CHASSIS_VERSION L"0.1" +#define SMBIOS_MISC_CHASSIS_SERIAL_NUMBER L"serial#" +#define SMBIOS_MISC_CHASSIS_ASSET_TAG L"Asset Tag" + +typedef struct { + CHAR16 *Manufacturer; + CHAR16 *Version; + CHAR16 *SerialNumber; + CHAR16 *AssetTag; +} SMBIOS_TABLE_TYPE03_STRINGS; + +/// +/// SMBIOS_TABLE_TYPE08 Default Strings +/// +#define SMBIOS_MISC_PORT_TOKEN_KEYBOARD 0x01 +#define SMBIOS_MISC_PORT_INTERNAL_KEYBOARD L"None" +#define SMBIOS_MISC_PORT_EXTERNAL_KEYBOARD L"Keyboard" +#define SMBIOS_MISC_PORT_TOKEN_MOUSE 0x02 +#define SMBIOS_MISC_PORT_INTERNAL_MOUSE L"None" +#define SMBIOS_MISC_PORT_EXTERNAL_MOUSE L"Mouse" +#define SMBIOS_MISC_PORT_TOKEN_COM1 0x03 +#define SMBIOS_MISC_PORT_INTERNAL_COM1 L"None" +#define SMBIOS_MISC_PORT_EXTERNAL_COM1 L"COM 1" +#define SMBIOS_MISC_PORT_TOKEN_VIDEO 0x04 +#define SMBIOS_MISC_PORT_INTERNAL_VIDEO L"J1A2B" +#define SMBIOS_MISC_PORT_EXTERNAL_VIDEO L"Video" +#define SMBIOS_MISC_PORT_TOKEN_HDMI 0x05 +#define SMBIOS_MISC_PORT_INTERNAL_HDMI L"J3A2" +#define SMBIOS_MISC_PORT_EXTERNAL_HDMI L"HDMI" +#define SMBIOS_MISC_PORT_TOKEN_USB1 0x06 +#define SMBIOS_MISC_PORT_INTERNAL_USB1 L"None" +#define SMBIOS_MISC_PORT_EXTERNAL_USB1 L"USB1.1 - 1#" +#define SMBIOS_MISC_PORT_TOKEN_USB2 0x07 +#define SMBIOS_MISC_PORT_INTERNAL_USB2 L"None" +#define SMBIOS_MISC_PORT_EXTERNAL_USB2 L"USB1.1 - 2#" +#define SMBIOS_MISC_PORT_TOKEN_USB3 0x08 +#define SMBIOS_MISC_PORT_INTERNAL_USB3 L"None" +#define SMBIOS_MISC_PORT_EXTERNAL_USB3 L"USB1.1 - 3#" +#define SMBIOS_MISC_PORT_TOKEN_USB4 0x09 +#define SMBIOS_MISC_PORT_INTERNAL_USB4 L"None" +#define SMBIOS_MISC_PORT_EXTERNAL_USB4 L"USB1.1 - 4#" +#define SMBIOS_MISC_PORT_TOKEN_USB5 0x0A +#define SMBIOS_MISC_PORT_INTERNAL_USB5 L"None" +#define SMBIOS_MISC_PORT_EXTERNAL_USB5 L"USB1.1 - 5#" +#define SMBIOS_MISC_PORT_TOKEN_USB201 0x0B +#define SMBIOS_MISC_PORT_INTERNAL_USB201 L"None" +#define SMBIOS_MISC_PORT_EXTERNAL_USB201 L"USB2.0 - 1#" +#define SMBIOS_MISC_PORT_TOKEN_USB202 0x0C +#define SMBIOS_MISC_PORT_INTERNAL_USB202 L"None" +#define SMBIOS_MISC_PORT_EXTERNAL_USB202 L"USB2.0 - 2#" +#define SMBIOS_MISC_PORT_TOKEN_NETWORK 0x0D +#define SMBIOS_MISC_PORT_INTERNAL_NETWORK L"None" +#define SMBIOS_MISC_PORT_EXTERNAL_NETWORK L"Ethernet" +#define SMBIOS_MISC_PORT_TOKEN_IDE1 0x0E +#define SMBIOS_MISC_PORT_INTERNAL_IDE1 L"None" +#define SMBIOS_MISC_PORT_EXTERNAL_IDE1 L"PATA" +#define SMBIOS_MISC_PORT_TOKEN_SATA0 0x0F +#define SMBIOS_MISC_PORT_INTERNAL_SATA0 L"J8J1" +#define SMBIOS_MISC_PORT_EXTERNAL_SATA0 L"SATA Port 0 Direct Connect" +#define SMBIOS_MISC_PORT_TOKEN_ESATA4 0x10 +#define SMBIOS_MISC_PORT_INTERNAL_ESATA4 L"J7J1" +#define SMBIOS_MISC_PORT_EXTERNAL_ESATA4 L"eSATA Port 4" +#define SMBIOS_MISC_PORT_TOKEN_ESATA3 0x11 +#define SMBIOS_MISC_PORT_INTERNAL_ESATA3 L"J6J1" +#define SMBIOS_MISC_PORT_EXTERNAL_ESATA3 L"eSATA Port 3" +#define SMBIOS_MISC_PORT_TOKEN_ACIN 0x12 +#define SMBIOS_MISC_PORT_INTERNAL_ACIN L"J1F2" +#define SMBIOS_MISC_PORT_EXTERNAL_ACIN L"AC IN" +#define SMBIOS_MISC_PORT_TOKEN_PCHJTAG 0x13 +#define SMBIOS_MISC_PORT_INTERNAL_PCHJTAG L"J5B1 - PCH JTAG" +#define SMBIOS_MISC_PORT_EXTERNAL_PCHJTAG L"None" +#define SMBIOS_MISC_PORT_TOKEN_PORT80 0x14 +#define SMBIOS_MISC_PORT_INTERNAL_PORT80 L"J9A1 - TPM/PORT 80" +#define SMBIOS_MISC_PORT_EXTERNAL_PORT80 L"None" +#define SMBIOS_MISC_PORT_TOKEN_2X8HEADER 0x15 +#define SMBIOS_MISC_PORT_INTERNAL_2X8HEADER L"J9E4 - HDA 2X8 Header" +#define SMBIOS_MISC_PORT_EXTERNAL_2X8HEADER L"None" +#define SMBIOS_MISC_PORT_TOKEN_8PINHEADER 0x16 +#define SMBIOS_MISC_PORT_INTERNAL_8PINHEADER L"J9E7 - HDA 8Pin Header" +#define SMBIOS_MISC_PORT_EXTERNAL_8PINHEADER L"None" +#define SMBIOS_MISC_PORT_TOKEN_HDAHDMI 0x17 +#define SMBIOS_MISC_PORT_INTERNAL_HDAHDMI L"J8F1 - HDA HDMI" +#define SMBIOS_MISC_PORT_EXTERNAL_HDAHDMI L"None" +#define SMBIOS_MISC_PORT_TOKEN_MKEYBOARD 0x18 +#define SMBIOS_MISC_PORT_INTERNAL_MKEYBOARD L"J9E3 - Scan Matrix Keyboard" +#define SMBIOS_MISC_PORT_EXTERNAL_MKEYBOARD L"None" +#define SMBIOS_MISC_PORT_TOKEN_SPI 0x19 +#define SMBIOS_MISC_PORT_INTERNAL_SPI L"J8E1 - SPI Program" +#define SMBIOS_MISC_PORT_EXTERNAL_SPI L"None" +#define SMBIOS_MISC_PORT_TOKEN_LPCDOCKING 0x1A +#define SMBIOS_MISC_PORT_INTERNAL_LPCDOCKING L"J9E5 - LPC Hot Docking" +#define SMBIOS_MISC_PORT_EXTERNAL_LPCDOCKING L"None" +#define SMBIOS_MISC_PORT_TOKEN_SIDEBAND 0x1B +#define SMBIOS_MISC_PORT_INTERNAL_SIDEBAND L"J9G2 - LPC SIDE BAND" +#define SMBIOS_MISC_PORT_EXTERNAL_SIDEBAND L"None" +#define SMBIOS_MISC_PORT_TOKEN_LPCSLOT 0x1C +#define SMBIOS_MISC_PORT_INTERNAL_LPCSLOT L"J8F2 - LPC Slot" +#define SMBIOS_MISC_PORT_EXTERNAL_LPCSLOT L"None" +#define SMBIOS_MISC_PORT_TOKEN_PCHXDP 0x1D +#define SMBIOS_MISC_PORT_INTERNAL_PCHXDP L"J8H3 - PCH XDP" +#define SMBIOS_MISC_PORT_EXTERNAL_PCHXDP L"None" +#define SMBIOS_MISC_PORT_TOKEN_INFRARED 0x1E +#define SMBIOS_MISC_PORT_INTERNAL_INFRARED L"None" +#define SMBIOS_MISC_PORT_EXTERNAL_INFRARED L"Infrared" +#define SMBIOS_MISC_PORT_TOKEN_SDVO 0x1F +#define SMBIOS_MISC_PORT_INTERNAL_SDVO L"None" +#define SMBIOS_MISC_PORT_EXTERNAL_SDVO L"Serial-Digital-Video-Out" +#define SMBIOS_MISC_PORT_TOKEN_LINEIN 0x20 +#define SMBIOS_MISC_PORT_INTERNAL_LINEIN L"None" +#define SMBIOS_MISC_PORT_EXTERNAL_LINEIN L"Audio Line In" +#define SMBIOS_MISC_PORT_TOKEN_LINEOUT 0x21 +#define SMBIOS_MISC_PORT_INTERNAL_LINEOUT L"None" +#define SMBIOS_MISC_PORT_EXTERNAL_LINEOUT L"Audio Line Out" +#define SMBIOS_MISC_PORT_TOKEN_SATA2 0x22 +#define SMBIOS_MISC_PORT_INTERNAL_SATA2 L"J7G1 - SATA Port 2" +#define SMBIOS_MISC_PORT_EXTERNAL_SATA2 L"None" +#define SMBIOS_MISC_PORT_TOKEN_SATA1 0x23 +#define SMBIOS_MISC_PORT_INTERNAL_SATA1 L"J7G2 - SATA Port 1" +#define SMBIOS_MISC_PORT_EXTERNAL_SATA1 L"None" +#define SMBIOS_MISC_PORT_TOKEN_SATAPOWER 0x24 +#define SMBIOS_MISC_PORT_INTERNAL_SATAPOWER L"J6H1 - SATA Power" +#define SMBIOS_MISC_PORT_EXTERNAL_SATAPOWER L"None" +#define SMBIOS_MISC_PORT_TOKEN_FPHEADER 0x25 +#define SMBIOS_MISC_PORT_INTERNAL_FPHEADER L"J5J1 - FP Header" +#define SMBIOS_MISC_PORT_EXTERNAL_FPHEADER L"None" +#define SMBIOS_MISC_PORT_TOKEN_ATXPOWER 0x26 +#define SMBIOS_MISC_PORT_INTERNAL_ATXPOWER L"J4H1 - ATX Power" +#define SMBIOS_MISC_PORT_EXTERNAL_ATXPOWER L"None" +#define SMBIOS_MISC_PORT_TOKEN_AVMC 0x27 +#define SMBIOS_MISC_PORT_INTERNAL_AVMC L"J1J3 - AVMC" +#define SMBIOS_MISC_PORT_EXTERNAL_AVMC L"None" +#define SMBIOS_MISC_PORT_TOKEN_BATTB 0x28 +#define SMBIOS_MISC_PORT_INTERNAL_BATTB L"J1H1 - BATT B" +#define SMBIOS_MISC_PORT_EXTERNAL_BATTB L"None" +#define SMBIOS_MISC_PORT_TOKEN_BATTA 0x29 +#define SMBIOS_MISC_PORT_INTERNAL_BATTA L"J1H2 - BATT A" +#define SMBIOS_MISC_PORT_EXTERNAL_BATTA L"None" +#define SMBIOS_MISC_PORT_TOKEN_CPUFAN 0x2A +#define SMBIOS_MISC_PORT_INTERNAL_CPUFAN L"J2G1 - CPU Fan" +#define SMBIOS_MISC_PORT_EXTERNAL_CPUFAN L"None" +#define SMBIOS_MISC_PORT_TOKEN_XDP 0x2B +#define SMBIOS_MISC_PORT_INTERNAL_XDP L"J1D3 - XDP" +#define SMBIOS_MISC_PORT_EXTERNAL_XDP L"None" +#define SMBIOS_MISC_PORT_TOKEN_MEMORY1 0x2C +#define SMBIOS_MISC_PORT_INTERNAL_MEMORY1 L"J4V1 - Memory Slot 1" +#define SMBIOS_MISC_PORT_EXTERNAL_MEMORY1 L"None" +#define SMBIOS_MISC_PORT_TOKEN_MEMORY2 0x2D +#define SMBIOS_MISC_PORT_INTERNAL_MEMORY2 L"J4V2 - Memory Slot 2" +#define SMBIOS_MISC_PORT_EXTERNAL_MEMORY2 L"None" +#define SMBIOS_MISC_PORT_TOKEN_FANPWR 0x2E +#define SMBIOS_MISC_PORT_INTERNAL_FANPWR L"J4C1 - FAN PWR" +#define SMBIOS_MISC_PORT_EXTERNAL_FANPWR L"None" + +typedef struct { + CHAR16 *InternalReferenceDesignator; + CHAR16 *ExternalReferenceDesignator; +} SMBIOS_TABLE_TYPE8_STRINGS; + +/// +/// SMBIOS_TABLE_TYPE9 Default Strings +/// +#define SMBIOS_MISC_SYSTEM_SLOT_TOKEN_PCIE0 0x43 +#define SMBIOS_MISC_SYSTEM_SLOT_PCIE0 L"PCI-Express 0" +#define SMBIOS_MISC_SYSTEM_SLOT_TOKEN_PCIE1 0x44 +#define SMBIOS_MISC_SYSTEM_SLOT_PCIE1 L"PCI-Express 1" +#define SMBIOS_MISC_SYSTEM_SLOT_TOKEN_PCIE2 0x45 +#define SMBIOS_MISC_SYSTEM_SLOT_PCIE2 L"PCI-Express 2" +#define SMBIOS_MISC_SYSTEM_SLOT_TOKEN_PCIE3 0x46 +#define SMBIOS_MISC_SYSTEM_SLOT_PCIE3 L"PCI-Express 3" + +typedef struct { + CHAR16 *SlotDesignation; +} SMBIOS_TABLE_TYPE9_STRINGS; + +/// +/// SMBIOS_TABLE_TYPE10 Default Strings +/// +#define SMBIOS_MISC_ONBOARD_DEVICE_VIDEO L"To Be Filled by O.E.M." +#define SMBIOS_MISC_ONBOARD_DEVICE_ETHERNET L"To Be Filled by O.E.M." +#define SMBIOS_MISC_ONBOARD_DEVICE_SOUND L"To Be Filled by O.E.M." + +typedef struct { + CHAR16 *DescriptionString; +} SMBIOS_TABLE_TYPE10_STRINGS; + +/// +/// SMBIOS_TABLE_TYPE12 Default Strings +/// +#define SMBIOS_MISC_SYSTEM_OPTION_STRING L"J6H1:1-X CMOS CLEAR(default); J8H1:1-X BIOS RECOVERY" + +typedef struct { + CHAR16 *StringCount; +} SMBIOS_TABLE_TYPE12_STRINGS; + +/// +/// SMBIOS_TABLE_TYPE13 Default Strings +/// +#define SMBIOS_MISC_INSTALLED_LANGUAGE_ENGLISH L"English" + +typedef struct { + CHAR16 *CurrentLanguages; +} SMBIOS_TABLE_TYPE13_STRINGS; + +/// +/// SMBIOS_TABLE_TYPE22 Default Strings +/// +#define SMBIOS_MISC_PROTABLE_BATTERY_TOKEN_VIRTUAL 0x60 +#define SMBIOS_MISC_PORTABLE_BATTERY_VIRTUAL_LOCATION L"Virtual" +#define SMBIOS_MISC_PORTABLE_BATTERY_VIRTUAL_MANUFACTURER L"-Virtual Battery 0-" +#define SMBIOS_MISC_PORTABLE_BATTERY_VIRTUAL_MANUFACTURER_DATE L"01/01/2013" +#define SMBIOS_MISC_PORTABLE_BATTERY_VIRTUAL_SERIAL_NUMBER L"Battery 0" +#define SMBIOS_MISC_PORTABLE_BATTERY_VIRTUAL_DEVICE_NAME L"CRB Battery 0" +#define SMBIOS_MISC_PROTABLE_BATTERY_TOKEN_REAL1 0x61 +#define SMBIOS_MISC_PORTABLE_BATTERY_REAL1_LOCATION L"Real 1" +#define SMBIOS_MISC_PORTABLE_BATTERY_REAL1_MANUFACTURER L"E-One Moli Energy" +#define SMBIOS_MISC_PORTABLE_BATTERY_REAL1_MANUFACTURER_DATE L"01/01/2013" +#define SMBIOS_MISC_PORTABLE_BATTERY_REAL1_SERIAL_NUMBER L"FSPK50074" +#define SMBIOS_MISC_PORTABLE_BATTERY_REAL1_DEVICE_NAME L"MOLICEL" +#define SMBIOS_MISC_PROTABLE_BATTERY_TOKEN_REAL2 0x62 +#define SMBIOS_MISC_PORTABLE_BATTERY_REAL2_LOCATION L"Real 2" +#define SMBIOS_MISC_PORTABLE_BATTERY_REAL2_MANUFACTURER L"E-One Moli Energy" +#define SMBIOS_MISC_PORTABLE_BATTERY_REAL2_MANUFACTURER_DATE L"01/01/2013" +#define SMBIOS_MISC_PORTABLE_BATTERY_REAL2_SERIAL_NUMBER L"FSPK50074" +#define SMBIOS_MISC_PORTABLE_BATTERY_REAL2_DEVICE_NAME L"MOLICEL" + +typedef struct { + CHAR16 *Location; + CHAR16 *Manufacturer; + CHAR16 *ManufacturerDate; + CHAR16 *SerialNumber; + CHAR16 *DeviceName; +} SMBIOS_TABLE_TYPE22_STRINGS; + +/// +/// SMBIOS_TABLE_TYPE27 Default Strings +/// +#define SMBIOS_MISC_COOLING_DEVICE_DESCRIPTION L" " + +typedef struct { + CHAR16 *Description; +} SMBIOS_TABLE_TYPE27_STRINGS; + +/// +/// SMBIOS_TABLE_TYPE39 Default Strings +/// +typedef struct { + CHAR16 *Location; + CHAR16 *DeviceName; + CHAR16 *Manufacturer; + CHAR16 *SerialNumber; + CHAR16 *AssetTagNumber; + CHAR16 *ModelPartNumber; + CHAR16 *RevisionLevel; +} SMBIOS_TABLE_TYPE39_STRINGS; + +/// +/// SMBIOS_TABLE_TYPE90 Default Strings +/// +typedef struct { + CHAR16 *SECVersion; + CHAR16 *uCodeVersion; + CHAR16 *GOPVersion; + CHAR16 *CpuStepping; +} SMBIOS_TABLE_TYPE90_STRINGS; + +/// +/// SMBIOS_TABLE_TYPE94 Default Strings +/// +typedef struct { + CHAR16 *GopVersion; + CHAR16 *uCodeVersion; + CHAR16 *MRCVersion; + CHAR16 *SECVersion; + CHAR16 *ULPMCVersion; + CHAR16 *PMCVersion; + CHAR16 *PUnitVersion; + CHAR16 *SoCVersion; + CHAR16 *BoardVersion; + CHAR16 *FabVersion; + CHAR16 *CPUFlavor; + CHAR16 *BiosVersion; + CHAR16 *PmicVersion; + CHAR16 *TouchVersion; + CHAR16 *SecureBoot; + CHAR16 *BootMode; + CHAR16 *SpeedStepMode; + CHAR16 *CPUTurboMode; + CHAR16 *MaxCState; + CHAR16 *GfxTurbo; + CHAR16 *S0ix; + CHAR16 *RC6; +} SMBIOS_TABLE_TYPE94_STRINGS; + +#endif -- cgit v1.2.3