From 04d72518eeeeae2ed1f6b061455deac0c3d7a701 Mon Sep 17 00:00:00 2001 From: Guo Mang Date: Thu, 2 Jun 2016 14:01:46 +0800 Subject: ChvRefCodePkg: Add SampleCode. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang --- .../SampleCode/Include/Guid/SmbusArpMap.h | 26 ++++++ .../SampleCode/Include/Ppi/SmbusPolicy.h | 35 ++++++++ .../SampleCode/Include/Ppi/SmmControl.h | 94 ++++++++++++++++++++++ .../SampleCode/Include/Ppi/UsbController.h | 92 +++++++++++++++++++++ .../SampleCode/Include/Protocol/SmmSmbus.h | 40 +++++++++ .../SouthCluster/SampleCode/SampleCode.dec | 35 ++++++++ 6 files changed, 322 insertions(+) create mode 100644 ChvRefCodePkg/CherryViewSoc/SouthCluster/SampleCode/Include/Guid/SmbusArpMap.h create mode 100644 ChvRefCodePkg/CherryViewSoc/SouthCluster/SampleCode/Include/Ppi/SmbusPolicy.h create mode 100644 ChvRefCodePkg/CherryViewSoc/SouthCluster/SampleCode/Include/Ppi/SmmControl.h create mode 100644 ChvRefCodePkg/CherryViewSoc/SouthCluster/SampleCode/Include/Ppi/UsbController.h create mode 100644 ChvRefCodePkg/CherryViewSoc/SouthCluster/SampleCode/Include/Protocol/SmmSmbus.h create mode 100644 ChvRefCodePkg/CherryViewSoc/SouthCluster/SampleCode/SampleCode.dec (limited to 'ChvRefCodePkg/CherryViewSoc') diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/SampleCode/Include/Guid/SmbusArpMap.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/SampleCode/Include/Guid/SmbusArpMap.h new file mode 100644 index 0000000000..f4e992c64d --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/SampleCode/Include/Guid/SmbusArpMap.h @@ -0,0 +1,26 @@ +/** @file + GUID for use in describing SMBus devices that were ARPed during PEI. + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _EFI_SMBUS_ARP_MAP_GUID_H_ +#define _EFI_SMBUS_ARP_MAP_GUID_H_ + +#define EFI_SMBUS_ARP_MAP_GUID \ + { \ + 0x707be83e, 0x0bf6, 0x40a5, 0xbe, 0x64, 0x34, 0xc0, 0x3a, 0xa0, 0xb8, 0xe2 \ + } + +extern EFI_GUID gEfiSmbusArpMapGuid; + +#endif diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/SampleCode/Include/Ppi/SmbusPolicy.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/SampleCode/Include/Ppi/SmbusPolicy.h new file mode 100644 index 0000000000..07d8cbf175 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/SampleCode/Include/Ppi/SmbusPolicy.h @@ -0,0 +1,35 @@ +/** @file + Smbus Policy PPI as defined in EFI 2.0 + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PEI_SMBUS_POLICY_PPI_H +#define _PEI_SMBUS_POLICY_PPI_H + +#define PEI_SMBUS_POLICY_PPI_GUID \ + { \ + 0x63b6e435, 0x32bc, 0x49c6, 0x81, 0xbd, 0xb7, 0xa1, 0xa0, 0xfe, 0x1a, 0x6c \ + } + +typedef struct _PEI_SMBUS_POLICY_PPI PEI_SMBUS_POLICY_PPI; + +struct _PEI_SMBUS_POLICY_PPI { + UINTN BaseAddress; + UINT32 PciAddress; + UINT8 NumRsvdAddress; + UINT8 *RsvdAddress; +}; + +extern EFI_GUID gPeiSmbusPolicyPpiGuid; + +#endif diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/SampleCode/Include/Ppi/SmmControl.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/SampleCode/Include/Ppi/SmmControl.h new file mode 100644 index 0000000000..3408ab888f --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/SampleCode/Include/Ppi/SmmControl.h @@ -0,0 +1,94 @@ +/** @file + EFI SMM Control PPI definition. + + This PPI is used to initiate SMI/PMI activations. This protocol could be published by either: + - A processor driver to abstract the SMI/PMI IPI + - The driver that abstracts the ASIC that is supporting the APM port, such as the ICH in an + Intel chipset + Because of the possibility of performing SMI or PMI IPI transactions, the ability to generate this + event from a platform chipset agent is an optional capability for both IA-32 and Itanium-based + systems. + + Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SMM_CONTROL_PPI_H_ +#define _SMM_CONTROL_PPI_H_ + +#define PEI_SMM_CONTROL_PPI_GUID \ + { 0x61c68702, 0x4d7e, 0x4f43, 0x8d, 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0xc5 } + +typedef struct _PEI_SMM_CONTROL_PPI PEI_SMM_CONTROL_PPI; + +/** + Invokes SMI activation from either the preboot or runtime environment. + + @param[in] PeiServices General purpose services available to every PEIM. + @param[in] This The PEI_SMM_CONTROL_PPI instance. + @param[in] ArgumentBuffer The optional sized data to pass into the protocol activation. + @param[in] ArgumentBufferSize The optional size of the data. + @param[in] Periodic An optional mechanism to periodically repeat activation. + @param[in] ActivationInterval An optional parameter to repeat at this period one + time or, if the Periodic Boolean is set, periodically. + + @retval EFI_SUCCESS The SMI/PMI has been engendered. + @retval EFI_DEVICE_ERROR The timing is unsupported. + @retval EFI_INVALID_PARAMETER The activation period is unsupported. + @retval EFI_NOT_STARTED The SMM base service has not been initialized. + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_SMM_ACTIVATE) ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_CONTROL_PPI * This, + IN OUT INT8 *ArgumentBuffer OPTIONAL, + IN OUT UINTN *ArgumentBufferSize OPTIONAL, + IN BOOLEAN Periodic OPTIONAL, + IN UINTN ActivationInterval OPTIONAL + ); + +/** + Clears any system state that was created in response to the Active call. + + @param[in] PeiServices General purpose services available to every PEIM. + @param[in] This The PEI_SMM_CONTROL_PPI instance. + @param[in] Periodic Optional parameter to repeat at this period one + time or, if the Periodic Boolean is set, periodically. + + @retval EFI_SUCCESS The SMI/PMI has been engendered. + @retval EFI_DEVICE_ERROR The source could not be cleared. + @retval EFI_INVALID_PARAMETER The service did not support the Periodic input argument. + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_SMM_DEACTIVATE) ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_CONTROL_PPI * This, + IN BOOLEAN Periodic OPTIONAL + ); + +/// +/// PEI SMM Control PPI is used to initiate SMI/PMI activations. This protocol could be published by either: +/// - A processor driver to abstract the SMI/PMI IPI +/// - The driver that abstracts the ASIC that is supporting the APM port, such as the ICH in an +/// Intel chipset +/// +struct _PEI_SMM_CONTROL_PPI { + PEI_SMM_ACTIVATE Trigger; + PEI_SMM_DEACTIVATE Clear; +}; + +extern EFI_GUID gPeiSmmControlPpiGuid; + +#endif diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/SampleCode/Include/Ppi/UsbController.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/SampleCode/Include/Ppi/UsbController.h new file mode 100644 index 0000000000..89e1b49db1 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/SampleCode/Include/Ppi/UsbController.h @@ -0,0 +1,92 @@ +/** @file + Define APIs to retrieve USB Host Controller Info such as controller type and + I/O Port Base Address. + + Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PEI_USB_CONTROLLER_PPI_H_ +#define _PEI_USB_CONTROLLER_PPI_H_ + +/// +/// Global ID for the PEI_USB_CONTROLLER_PPI. +/// +#define PEI_USB_CONTROLLER_PPI_GUID \ + { \ + 0x3bc1f6de, 0x693e, 0x4547,{ 0xa3, 0x0, 0x21, 0x82, 0x3c, 0xa4, 0x20, 0xb2} \ + } + +/// +/// Forward declaration for the PEI_USB_CONTROLLER_PPI. +/// +typedef struct _PEI_USB_CONTROLLER_PPI PEI_USB_CONTROLLER_PPI; + +/// +/// This bit is used in the ControllerType return parameter of GetUsbController() +/// to identify the USB Host Controller type as UHCI +/// +#define PEI_UHCI_CONTROLLER 0x01 + +/// +/// This bit is used in the ControllerType return parameter of GetUsbController() +/// to identify the USB Host Controller type as OHCI +/// +#define PEI_OHCI_CONTROLLER 0x02 + +/// +/// This bit is used in the ControllerType return parameter of GetUsbController() +/// to identify the USB Host Controller type as EHCI +/// +#define PEI_EHCI_CONTROLLER 0x03 + +/// +/// This bit is used in the ControllerType return parameter of GetUsbController() +/// to identify the USB Host Controller type as XHCI +/// +#define PEI_XHCI_CONTROLLER 0x04 + +/** + Retrieve USB Host Controller Info such as controller type and I/O Base Address. + + @param[in] PeiServices The pointer to the PEI Services Table. + @param[in] This The pointer to this instance of the PEI_USB_CONTROLLER_PPI. + @param[in] ControllerId The ID of the USB controller. + @param[out] ControllerType On output, returns the type of the USB controller. + @param[out] BaseAddress On output, returns the base address of XHCI's MMIO + if XHCI is enabled. + + @retval EFI_SUCCESS USB controller attributes were returned successfully. + @retval EFI_INVALID_PARAMETER ControllerId is greater than the maximum number + of USB controller supported by this platform. + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_GET_USB_CONTROLLER) ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_USB_CONTROLLER_PPI *This, + IN UINT8 UsbControllerId, + OUT UINTN *ControllerType, + OUT UINTN *BaseAddress + ); + +/// +/// This PPI contains a single service to retrieve the USB Host Controller type +/// and the base address of the I/O ports used to access the USB Host Controller. +/// +typedef struct _PEI_USB_CONTROLLER_PPI { + PEI_GET_USB_CONTROLLER GetUsbController; +} PEI_USB_CONTROLLER_PPI; + +extern EFI_GUID gPeiUsbControllerPpiGuid; + +#endif diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/SampleCode/Include/Protocol/SmmSmbus.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/SampleCode/Include/Protocol/SmmSmbus.h new file mode 100644 index 0000000000..3e427a2f29 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/SampleCode/Include/Protocol/SmmSmbus.h @@ -0,0 +1,40 @@ +/** @file + SmmSmbus Protocol + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __EFI_SMM_SMBUS_PROTOCOL_H__ +#define __EFI_SMM_SMBUS_PROTOCOL_H__ + +// +// GUID for the SmmSmbus Protocol +// +// EDK and EDKII have different GUID formats +// + +#define EFI_SMM_SMBUS_PROTOCOL_GUID \ + { \ + 0x72e40094, 0x2ee1, 0x497a, \ + { \ + 0x8f, 0x33, 0x4c, 0x93, 0x4a, 0x9e, 0x9c, 0xc \ + } \ + } + +// +// Resuse the DXE definition, and use another GUID. +// +typedef EFI_SMBUS_HC_PROTOCOL SMM_SMBUS_HC_PROTOCOL; + +extern EFI_GUID gEfiSmmSmbusProtocolGuid; + +#endif diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/SampleCode/SampleCode.dec b/ChvRefCodePkg/CherryViewSoc/SouthCluster/SampleCode/SampleCode.dec new file mode 100644 index 0000000000..220bd297aa --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/SampleCode/SampleCode.dec @@ -0,0 +1,35 @@ +## @file +# +# Copyright (c) 2015, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + DEC_SPECIFICATION = 0x00010005 + PACKAGE_NAME = SampleCode + PACKAGE_GUID = 7200a805-b9f9-4d37-8bb6-7ea74c9c7f8d + PACKAGE_VERSION = 0.1 + +[Includes] + Include + +[Protocols] + ## Include\Protocol\SmmSmbus.h + gEfiSmmSmbusProtocolGuid = { 0x72e40094, 0x2ee1, 0x497a, { 0x8f, 0x33, 0x4c, 0x93, 0x4a, 0x9e, 0x9c, 0xc }} +[Ppis] + ## Include\Ppi\SmbusPolicy.h + gPeiSmbusPolicyPpiGuid = { 0x63b6e435, 0x32bc, 0x49c6, {0x81, 0xbd, 0xb7, 0xa1, 0xa0, 0xfe, 0x1a, 0x6c }} + ## Include\Ppi\UsbController.h + gPeiUsbControllerPpiGuid = {0x3bc1f6de, 0x693e, 0x4547, {0xa3, 0x0, 0x21, 0x82, 0x3c, 0xa4, 0x20, 0xb2}} + +[Guids] + ## Include\Guid\SmbusArpMap.h + gEfiSmbusArpMapGuid = { 0x707be83e, 0x0bf6, 0x40a5, {0xbe, 0x64, 0x34, 0xc0, 0x3a, 0xa0, 0xb8, 0xe2 }} -- cgit v1.2.3