From 254189fe9b9205536b76294b2e5019c4363a3123 Mon Sep 17 00:00:00 2001 From: Guo Mang Date: Thu, 2 Jun 2016 14:07:09 +0800 Subject: ChvRefCodePkg: Add Usb driver. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang --- .../CherryViewSoc/SouthCluster/Usb/Pei/PchUsb.c | 40 +++++ .../CherryViewSoc/SouthCluster/Usb/Pei/PchUsb.h | 42 +++++ .../CherryViewSoc/SouthCluster/Usb/Pei/PchUsb.inf | 57 ++++++ .../CherryViewSoc/SouthCluster/Usb/Pei/PchXhci.c | 198 +++++++++++++++++++++ .../CherryViewSoc/SouthCluster/Usb/Pei/PchXhci.h | 63 +++++++ 5 files changed, 400 insertions(+) create mode 100644 ChvRefCodePkg/CherryViewSoc/SouthCluster/Usb/Pei/PchUsb.c create mode 100644 ChvRefCodePkg/CherryViewSoc/SouthCluster/Usb/Pei/PchUsb.h create mode 100644 ChvRefCodePkg/CherryViewSoc/SouthCluster/Usb/Pei/PchUsb.inf create mode 100644 ChvRefCodePkg/CherryViewSoc/SouthCluster/Usb/Pei/PchXhci.c create mode 100644 ChvRefCodePkg/CherryViewSoc/SouthCluster/Usb/Pei/PchXhci.h (limited to 'ChvRefCodePkg/CherryViewSoc') diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Usb/Pei/PchUsb.c b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Usb/Pei/PchUsb.c new file mode 100644 index 0000000000..4126d21ca1 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Usb/Pei/PchUsb.c @@ -0,0 +1,40 @@ +/** @file + USB PEI Init + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "PchUsb.h" + +/** + Initialize PCH USB PEIM + + @param[in] FfsHeader Not used. + @param[in] PeiServices General purpose services available to every PEIM. + + @retval EFI_SUCCESS The PCH USB PEIM is initialized successfully + @retval Others All other error conditions encountered result in an ASSERT. +**/ +EFI_STATUS +InitializePchUsb ( + IN EFI_PEI_FILE_HANDLE FfsHeader, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + DEBUG ((EFI_D_INFO, "InitializePchUsb() Start\n")); + + InitForXHCI (PeiServices, PcdGet32(PcdPeiPchXhciControllerMemoryBaseAddress)); + + DEBUG ((EFI_D_INFO, "InitializePchUsb() End\n")); + + return EFI_SUCCESS; +} diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Usb/Pei/PchUsb.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Usb/Pei/PchUsb.h new file mode 100644 index 0000000000..239cb1cd07 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Usb/Pei/PchUsb.h @@ -0,0 +1,42 @@ +/** @file + Header file for the USB PEIM + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_USB_H_ +#define _PCH_USB_H_ + +#include "PchAccess.h" +#include +#include +#include + +/** + Initialize PCH XHCI PEIM + + @param[in] PeiServices General purpose services available to every PEIM. + @param[in] UsbPolicyPpi PCH Usb Policy PPI + + @retval EFI_SUCCESS The PCH XHCI PEIM is initialized successfully + @retval EFI_INVALID_PARAMETER UsbControllerId is out of range + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database + @retval Others All other error conditions encountered result in an ASSERT. + +**/ +EFI_STATUS +InitForXHCI ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN UINTN XhciMemBaseAddr + ); + +#endif diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Usb/Pei/PchUsb.inf b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Usb/Pei/PchUsb.inf new file mode 100644 index 0000000000..083239135f --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Usb/Pei/PchUsb.inf @@ -0,0 +1,57 @@ +## @file +# Component description file for PCH USB PEIM +# +# Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[defines] + INF_VERSION = 0x00010005 + BASE_NAME = PchUsb + FILE_GUID = A7815878-5BDA-4A04-84CC-987A1723AFDE + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = InitializePchUsb + +[sources.common] + PchXhci.c + PchUsb.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelFrameworkPkg/IntelFrameworkPkg.dec + ChvRefCodePkg/ChvRefCodePkg.dec + IntelFspWrapperPkg/IntelFspWrapperPkg.dec + +[LibraryClasses] + PeimEntryPoint + IoLib + DebugLib + MemoryAllocationLib + PchPlatformLib + PciLib + BaseMemoryLib + +[Guids] + +[Ppis] + # PRODUCES + gPeiUsbControllerPpiGuid + +[Pcd.common] + # CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + # CONSUMES + gEfiPchTokenSpaceGuid.PcdPeiPchXhciControllerMemoryBaseAddress + +[Depex] + gEfiPeiMasterBootModePpiGuid AND gFspInitDonePpiGuid diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Usb/Pei/PchXhci.c b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Usb/Pei/PchXhci.c new file mode 100644 index 0000000000..507443c917 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Usb/Pei/PchXhci.c @@ -0,0 +1,198 @@ +/** @file + Pch Xhci PPI Init + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "PchXhci.h" + +/// +/// PPI interface function +/// +STATIC +EFI_STATUS +EFIAPI +GetXhciController ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_USB_CONTROLLER_PPI *This, + IN UINT8 UsbControllerId, + OUT UINTN *ControllerType, + OUT UINTN *BaseAddress + ); + +/// +/// Globals +/// +STATIC PEI_USB_CONTROLLER_PPI mXhciControllerPpi = { GetXhciController }; + +STATIC EFI_PEI_PPI_DESCRIPTOR mPpiList = { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gPeiUsbControllerPpiGuid, + NULL +}; + +/// +/// Helper function +/// +STATIC +EFI_STATUS +EnableXhciController ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN PCH_XHCI_DEVICE *PeiPchXhciDev + ); + + +/** + + Initialize PCH XHCI PEIM + + @param[in] PeiServices General purpose services available to every PEIM. + @param[in] UsbPolicyPpi PCH Usb Policy PPI + + @retval EFI_SUCCESS The PCH XHCI PEIM is initialized successfully + @retval EFI_INVALID_PARAMETER UsbControllerId is out of range + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database + @retval Others All other error conditions encountered result in an ASSERT. + +**/ + +EFI_STATUS +InitForXHCI ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN UINTN XhciMemBaseAddr + ) +{ + EFI_STATUS Status; + PCH_XHCI_DEVICE *PeiPchXhciDev; + EFI_BOOT_MODE BootMode; + + DEBUG ((EFI_D_INFO, "InitForXHCI() Start\n")); + + Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode); + + /// + /// We do not export this in S3 boot path, because it is only for recovery. + /// + if (BootMode == BOOT_ON_S3_RESUME) { + return EFI_SUCCESS; + } + + PeiPchXhciDev = (PCH_XHCI_DEVICE *) AllocatePool (sizeof (PCH_XHCI_DEVICE)); + if (PeiPchXhciDev == NULL) { + DEBUG ((EFI_D_ERROR, "Failed to allocate memory for PeiPchXhciDev! \n")); + return EFI_OUT_OF_RESOURCES; + } + + PeiPchXhciDev->Signature = PEI_PCH_XHCI_SIGNATURE; + PeiPchXhciDev->XhciControllerPpi = mXhciControllerPpi; + PeiPchXhciDev->PpiList = mPpiList; + PeiPchXhciDev->PpiList.Ppi = &PeiPchXhciDev->XhciControllerPpi; + + /// + /// Assign resources and enable XHCI controllers + /// + PeiPchXhciDev->MemBase = XhciMemBaseAddr; + Status = EnableXhciController (PeiServices, PeiPchXhciDev); + ASSERT_EFI_ERROR (Status); + /// + /// Install USB Controller PPI + /// + Status = PeiServicesInstallPpi (&PeiPchXhciDev->PpiList); + ASSERT_EFI_ERROR (Status); + + DEBUG ((EFI_D_INFO, "InitForXHCI() End\n")); + + return Status; + +} +/// +/// PPI interface implementation +/// + +/** + + Get XHCI controller information + + @param[in] PeiServices General PEI services + @param[in] This Pointer to the PEI_XHCI_CONTROLLER_PPI + @param[in] UsbControllerId The USB controller number + @param[in] ControllerType Output: USB controller type + @param[in] BaseAddress Output: XHCI controller memory base address + + @retval EFI_INVALID_PARAMETER UsbControllerId is out of range + @retval EFI_SUCCESS Function completes successfully + +**/ +STATIC +EFI_STATUS +EFIAPI +GetXhciController ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_USB_CONTROLLER_PPI *This, + IN UINT8 UsbControllerId, + OUT UINTN *ControllerType, + OUT UINTN *BaseAddress + ) +{ + PCH_XHCI_DEVICE *PeiPchXhciDev; + + PeiPchXhciDev = PCH_XHCI_DEVICE_FROM_THIS (This); + + if (UsbControllerId >= PchXhciControllerMax) { + return EFI_INVALID_PARAMETER; + } + + *ControllerType = PEI_XHCI_CONTROLLER; + + *BaseAddress = PeiPchXhciDev->MemBase; + + return EFI_SUCCESS; +} + + +/** + + Enable the XHCI controller + + @param[in] PeiServices The general PEI services + @param[in] PeiPchXhciDev The XHCI device + + @retval EFI_INVALID_PARAMETER UsbControllerId is out of range + @retval EFI_SUCCESS The function completes successfully + +**/ +STATIC +EFI_STATUS +EnableXhciController ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN PCH_XHCI_DEVICE *PeiPchXhciDev + ) +{ + UINTN BaseAddress; + + BaseAddress = PeiPchXhciDev->MemBase; + + /// + /// Assign base address register + /// + MmioWrite32 ((PCH_PCIE_XHCI_BUS_DEV_FUNC + R_PCH_XHCI_MEM_BASE), BaseAddress); + + /// + /// Enable XHCI register + /// + MmioOr16 ( + (PCH_PCIE_XHCI_BUS_DEV_FUNC + R_PCH_XHCI_COMMAND_REGISTER), + (UINT16) (B_PCH_XHCI_COMMAND_BME | B_PCH_XHCI_COMMAND_MSE) + ); + + return EFI_SUCCESS; +} diff --git a/ChvRefCodePkg/CherryViewSoc/SouthCluster/Usb/Pei/PchXhci.h b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Usb/Pei/PchXhci.h new file mode 100644 index 0000000000..8d3efe44c7 --- /dev/null +++ b/ChvRefCodePkg/CherryViewSoc/SouthCluster/Usb/Pei/PchXhci.h @@ -0,0 +1,63 @@ +/** @file + Header file for the PCH XHCI PPI + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PEI_PCH_XHCI_H +#define _PEI_PCH_XHCI_H + +/// +/// External include files do NOT need to be explicitly specified in real EDKII +/// environment +/// + +/// +/// Driver Produced PPI Prototypes +/// +#include +#include +#include +#include +#include +#include +#include + +#include "PchAccess.h" +#include "PchUsb.h" + +/// +/// The following define is not in framework code yet +/// Add XHCI define as 0x04 +/// +#define PEI_XHCI_CONTROLLER 0x04 + +#define PCH_PCIE_XHCI_BUS_DEV_FUNC MmPciAddress ( \ + 0, \ + DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_XHCI, \ + PCI_FUNCTION_NUMBER_PCH_XHCI, \ + 0 \ + ) + +#define PEI_PCH_XHCI_SIGNATURE SIGNATURE_32 ('X', 'H', 'C', 'I') + +typedef struct { + UINTN Signature; + PEI_USB_CONTROLLER_PPI XhciControllerPpi; + EFI_PEI_PPI_DESCRIPTOR PpiList; + UINTN MemBase; +} PCH_XHCI_DEVICE; + +#define PCH_XHCI_DEVICE_FROM_THIS(a) CR (a, PCH_XHCI_DEVICE, XhciControllerPpi, PEI_PCH_XHCI_SIGNATURE) + +#endif -- cgit v1.2.3