From b4ff1d4d2cec557ae3e4bb3a3cbc12812ffd2084 Mon Sep 17 00:00:00 2001 From: Guo Mang Date: Thu, 2 Jun 2016 11:38:41 +0800 Subject: ChvRefCodePkg: Add AcpiTablesPCAT. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang --- ChvRefCodePkg/AcpiTablesPCAT/AcpiTablePlatform.h | 64 + ChvRefCodePkg/AcpiTablesPCAT/AcpiTables.inf | 44 + ChvRefCodePkg/AcpiTablesPCAT/Cpu/Cpu.asl | 47 + ChvRefCodePkg/AcpiTablesPCAT/Csrt.aslc | 223 ++++ ChvRefCodePkg/AcpiTablesPCAT/Csrt.h | 86 ++ ChvRefCodePkg/AcpiTablesPCAT/DBG2/DBG2.aslc | 172 +++ ChvRefCodePkg/AcpiTablesPCAT/Dsdt.asl | 155 +++ ChvRefCodePkg/AcpiTablesPCAT/Facp/Facp.aslc | 182 +++ ChvRefCodePkg/AcpiTablesPCAT/Facs/Facs.aslc | 77 ++ ChvRefCodePkg/AcpiTablesPCAT/GlobalNvs.asl | 392 ++++++ ChvRefCodePkg/AcpiTablesPCAT/Hpet/Hpet.aslc | 59 + ChvRefCodePkg/AcpiTablesPCAT/Hpet/Hpet.h | 38 + ChvRefCodePkg/AcpiTablesPCAT/Madt/Madt.h | 187 +++ ChvRefCodePkg/AcpiTablesPCAT/Madt/Madt30.aslc | 216 +++ ChvRefCodePkg/AcpiTablesPCAT/Mcfg/Mcfg.aslc | 83 ++ ChvRefCodePkg/AcpiTablesPCAT/Mcfg/Mcfg.h | 64 + ChvRefCodePkg/AcpiTablesPCAT/Mcfg/McfgTable.h | 61 + ChvRefCodePkg/AcpiTablesPCAT/Pch/98Link.asl | 615 +++++++++ ChvRefCodePkg/AcpiTablesPCAT/Pch/LpcB.asl | 144 ++ ChvRefCodePkg/AcpiTablesPCAT/Pch/LpcDev.asl | 173 +++ ChvRefCodePkg/AcpiTablesPCAT/Pch/Pch.asl | 654 ++++++++++ ChvRefCodePkg/AcpiTablesPCAT/Pch/PchAudio.asl | 36 + ChvRefCodePkg/AcpiTablesPCAT/Pch/PchLpss.asl | 953 ++++++++++++++ ChvRefCodePkg/AcpiTablesPCAT/Pch/PchPcie.asl | 88 ++ ChvRefCodePkg/AcpiTablesPCAT/Pch/PchScc.asl | 309 +++++ ChvRefCodePkg/AcpiTablesPCAT/Pch/PchSmb.asl | 592 +++++++++ ChvRefCodePkg/AcpiTablesPCAT/Pch/PchXhci.asl | 443 +++++++ ChvRefCodePkg/AcpiTablesPCAT/Pch/PciTree.asl | 254 ++++ .../Pch/SampleDevice/Audio/Audio.asl | 60 + .../Pch/SampleDevice/Audio/Realtek.asl | 68 + .../Pch/SampleDevice/Bluetooth/Broadcom.asl | 90 ++ .../Pch/SampleDevice/Camera/Camera.asl | 270 ++++ .../Pch/SampleDevice/Camera/Camera2.asl | 815 ++++++++++++ .../Pch/SampleDevice/FingerPrint/AuthenTec.asl | 47 + .../Pch/SampleDevice/Gps/Broadcom.asl | 136 ++ .../AcpiTablesPCAT/Pch/SampleDevice/Nfc/Nxp1.asl | 55 + .../AcpiTablesPCAT/Pch/SampleDevice/Nfc/Nxp2.asl | 33 + .../Pch/SampleDevice/Rfid/Impinj.asl | 88 ++ .../SampleDevice/SensorHub/STMicroelectronics.asl | 87 ++ .../Pch/SampleDevice/TouchPad/Atmel.asl | 160 +++ .../Pch/SampleDevice/TouchPad/Synaptics.asl | 60 + .../Pch/SampleDevice/TouchPad/Synaptics2.asl | 60 + .../Pch/SampleDevice/Wifi/Broadcom.asl | 164 +++ ChvRefCodePkg/AcpiTablesPCAT/Platform/Bat0Virt.asl | 331 +++++ ChvRefCodePkg/AcpiTablesPCAT/Platform/Bat1Real.asl | 197 +++ ChvRefCodePkg/AcpiTablesPCAT/Platform/Ec.asl | 1369 ++++++++++++++++++++ ChvRefCodePkg/AcpiTablesPCAT/Platform/Gpe.asl | 229 ++++ ChvRefCodePkg/AcpiTablesPCAT/Platform/PciDrc.asl | 105 ++ ChvRefCodePkg/AcpiTablesPCAT/Platform/Platform.asl | 1086 ++++++++++++++++ ChvRefCodePkg/AcpiTablesPCAT/Platform/Thermal.asl | 218 ++++ .../SampleCode/Include/SamplePlatformDefinition.h | 35 + .../AcpiTablesPCAT/SampleCode/Madt/Madt.h | 188 +++ .../AcpiTablesPCAT/SampleCode/Madt/Madt30.aslc | 215 +++ .../AcpiTablesPCAT/SampleCode/Mcfg/Mcfg.aslc | 83 ++ .../AcpiTablesPCAT/SampleCode/Mcfg/Mcfg.h | 64 + .../AcpiTablesPCAT/SampleCode/Mcfg/McfgTable.h | 61 + ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/Als.asl | 60 + ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/Chv.asl | 56 + .../AcpiTablesPCAT/SystemAgent/HostBus.asl | 412 ++++++ .../AcpiTablesPCAT/SystemAgent/IgdOpGbda.asl | 153 +++ .../AcpiTablesPCAT/SystemAgent/IgdOpMobf.asl | 483 +++++++ .../AcpiTablesPCAT/SystemAgent/IgdOpRn.ASL | 298 +++++ .../AcpiTablesPCAT/SystemAgent/IgdOpSbcb.asl | 287 ++++ .../AcpiTablesPCAT/SystemAgent/IntelGraphics.asl | 1009 +++++++++++++++ .../AcpiTablesPCAT/SystemAgent/IntelIspDev2.asl | 66 + ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/Video.asl | 32 + ChvRefCodePkg/AcpiTablesPCAT/token.asl | 62 + 67 files changed, 15703 insertions(+) create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/AcpiTablePlatform.h create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/AcpiTables.inf create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Cpu/Cpu.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Csrt.aslc create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Csrt.h create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/DBG2/DBG2.aslc create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Dsdt.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Facp/Facp.aslc create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Facs/Facs.aslc create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/GlobalNvs.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Hpet/Hpet.aslc create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Hpet/Hpet.h create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Madt/Madt.h create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Madt/Madt30.aslc create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Mcfg/Mcfg.aslc create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Mcfg/Mcfg.h create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Mcfg/McfgTable.h create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Pch/98Link.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Pch/LpcB.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Pch/LpcDev.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Pch/Pch.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Pch/PchAudio.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Pch/PchLpss.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Pch/PchPcie.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Pch/PchScc.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Pch/PchSmb.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Pch/PchXhci.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Pch/PciTree.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Audio/Audio.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Audio/Realtek.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Bluetooth/Broadcom.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Camera/Camera.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Camera/Camera2.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/FingerPrint/AuthenTec.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Gps/Broadcom.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Nfc/Nxp1.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Nfc/Nxp2.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Rfid/Impinj.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/SensorHub/STMicroelectronics.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/TouchPad/Atmel.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/TouchPad/Synaptics.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/TouchPad/Synaptics2.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Wifi/Broadcom.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Platform/Bat0Virt.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Platform/Bat1Real.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Platform/Ec.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Platform/Gpe.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Platform/PciDrc.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Platform/Platform.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/Platform/Thermal.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/SampleCode/Include/SamplePlatformDefinition.h create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/SampleCode/Madt/Madt.h create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/SampleCode/Madt/Madt30.aslc create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/SampleCode/Mcfg/Mcfg.aslc create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/SampleCode/Mcfg/Mcfg.h create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/SampleCode/Mcfg/McfgTable.h create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/Als.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/Chv.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/HostBus.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/IgdOpGbda.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/IgdOpMobf.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/IgdOpRn.ASL create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/IgdOpSbcb.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/IntelGraphics.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/IntelIspDev2.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/Video.asl create mode 100644 ChvRefCodePkg/AcpiTablesPCAT/token.asl (limited to 'ChvRefCodePkg') diff --git a/ChvRefCodePkg/AcpiTablesPCAT/AcpiTablePlatform.h b/ChvRefCodePkg/AcpiTablesPCAT/AcpiTablePlatform.h new file mode 100644 index 0000000000..10a7f52134 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/AcpiTablePlatform.h @@ -0,0 +1,64 @@ +/** @file + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _Platform_h_INCLUDED_ +#define _Platform_h_INCLUDED_ + +#include +// +// ACPI table information used to initialize tables. +// +#define EFI_ACPI_OEM_ID 'I','N','T','E','L',' ' // OEMID 6 bytes long +#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('L','A','N','F','O','R','D','C') // OEM table id 8 bytes long +#define EFI_ACPI_OEM_REVISION 0x00000005 +#define EFI_ACPI_CREATOR_ID SIGNATURE_32('M','S','F','T') +#define EFI_ACPI_CREATOR_REVISION 0x0100000D +#define INT_MODEL 0x01 +#define PM_PROFILE EFI_ACPI_4_0_PM_PROFILE_MOBILE +#define SCI_INT_VECTOR 0x0009 +#define SMI_CMD_IO_PORT 0x000000B2 +#define ACPI_ENABLE 0x0A0 +#define ACPI_DISABLE 0x0A1 +#define S4BIOS_REQ 0x00 +#define PSTATE_CNT 0x00 +#define PM1a_EVT_BLK 0x00000400 +#define PM1b_EVT_BLK 0x00000000 +#define PM1a_CNT_BLK 0x00000404 +#define PM1b_CNT_BLK 0x00000000 +#define PM2_CNT_BLK 0x00000450 +#define PM_TMR_BLK 0x00000408 +#define GPE0_BLK 0x00000420 +#define GPE1_BLK 0x00000000 +#define PM1_EVT_LEN 0x04 +#define PM1_CNT_LEN 0x02 +#define PM2_CNT_LEN 0x01 +#define PM_TM_LEN 0x04 +#define GPE0_BLK_LEN 0x10 +#define GPE1_BLK_LEN 0x00 +#define GPE1_BASE 0x00 +#define CST_CNT 0x00 +#define P_LVL2_LAT 0x0065 +#define P_LVL3_LAT 0x03E9 +#define FLUSH_SIZE 0x0400 +#define FLUSH_STRIDE 0x0010 +#define DUTY_OFFSET 0x01 +#define DUTY_WIDTH 0x03 +#define DAY_ALRM 0x0D +#define MON_ALRM 0x00 +#define CENTURY 0x32 +#define FLAG ( EFI_ACPI_5_0_WBINVD | EFI_ACPI_5_0_SLP_BUTTON | EFI_ACPI_5_0_RESET_REG_SUP | EFI_ACPI_5_0_USE_PLATFORM_CLOCK | EFI_ACPI_5_0_RTC_S4 ) +#define IAPC_BOOT_ARCH ( EFI_ACPI_5_0_8042 | EFI_ACPI_5_0_LEGACY_DEVICES ) +#define RESERVED 0x00 + +#endif diff --git a/ChvRefCodePkg/AcpiTablesPCAT/AcpiTables.inf b/ChvRefCodePkg/AcpiTablesPCAT/AcpiTables.inf new file mode 100644 index 0000000000..da0c094d42 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/AcpiTables.inf @@ -0,0 +1,44 @@ +## @file +# Platform Acpi Table Module +# +# This module contains the ACPI tables that can be published for use by an +# ACPI aware OS. This module only contains the data and must be manipulated by +# a separate driver to be functional. +# +# Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[defines] + INF_VERSION = 0x00010005 + BASE_NAME = AcpiTables + FILE_GUID = 594C5339-3DE5-4ccc-8886-9C627DD9F62B + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + EDK_RELEASE_VERSION = 0x00020000 + EFI_SPECIFICATION_VERSION = 0x00020000 + +[sources.common] + Csrt.aslc + Dsdt.asl + Facs/Facs.aslc + Facp/Facp.aslc + SampleCode/Madt/Madt30.aslc + SampleCode/Mcfg/Mcfg.aslc + #Hpet/Hpet.aslc + +[Packages] + MdePkg/MdePkg.dec + ChvRefCodePkg/ChvRefCodePkg.dec + +[Guids] + gEfiAcpiTableStorageGuid ## PRODUCES ## FV + diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Cpu/Cpu.asl b/ChvRefCodePkg/AcpiTablesPCAT/Cpu/Cpu.asl new file mode 100644 index 0000000000..ededd4e801 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Cpu/Cpu.asl @@ -0,0 +1,47 @@ +/** @file + ACPI DSDT table + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + // NOTE: The _PDC Implementation is out of the scope of this + // reference code. Please see the latest Hyper-Threading Technology + // Reference Code for complete implementation details. + + Scope(\_PR) + { + Processor(CPU0, // Unique name for Processor 0. + 1, // Unique ID for Processor 0. + 0x00, // CPU0 ACPI P_BLK address = ACPIBASE + 10h. + 0) // CPU0 ICH7M P_BLK length = 6 bytes. + {} + + Processor(CPU1, // Unique name for Processor 1. + 2, // Unique ID for Processor 1. + 0x00, + 0) // CPU1 P_BLK length = 6 bytes. + {} + + Processor(CPU2, // Unique name for Processor 2. + 3, // Unique ID for Processor 2. + 0x00, + 0) // CPU2 P_BLK length = 6 bytes. + {} + + Processor(CPU3, // Unique name for Processor 3. + 4, // Unique ID for Processor 3. + 0x00, + 0) // CPU3 P_BLK length = 6 bytes. + {} + } // End _PR + + diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Csrt.aslc b/ChvRefCodePkg/AcpiTablesPCAT/Csrt.aslc new file mode 100644 index 0000000000..7ab4e36ebf --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Csrt.aslc @@ -0,0 +1,223 @@ +/** @file + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "AcpiTablePlatform.h" +#include "Csrt.h" + +// +// Debug Port Table +// +EFI_ACPI_CSRT_TABLE Csrt = +{ + { //EFI_ACPI_DESCRIPTION_HEADER Start + EFI_ACPI_5_0_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE, + sizeof(EFI_ACPI_CSRT_TABLE), + EFI_ACPI_CSRT_TABLE_REVISION, + 0, // to make sum of entire table == 0 + EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field + EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long) + EFI_ACPI_OEM_REVISION, // OEM revision + EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID + EFI_ACPI_CREATOR_REVISION // ASL compiler revision number + }, //EFI_ACPI_DESCRIPTION_HEADER End + { + // + // LPIO1 DMA RESOURCE_GROUP_INFO1 + // + { //RESOURCE_GROUP_HEADER Start + sizeof(RESOURCE_GROUP_INFO1),// sizeof(RESOURCE_GROUP_INFO) + 0x4C544E49, + 0x00000000, + 0x9C60, + 0x0000, + 0x0002, + 0x0000, + sizeof(SHARED_INFO_SECTION), + { + // Shared Info Section + 0x0001, // Major Version 1 + 0x0000, // Minor Version 0 + 0x55AA55AA, // MMIO Base - Low Part + 0x00000000, // MMIO Base - High Part + 0x0000002A, // Interrupt GSI 42 + 0x02, // Interrupt Polarity + 0x00, // Interrupt Mode + 0x06, // Number of Channels + 0x20, // DMA Address Width + 0x0000, // Base Request Line + 0x0010, // Number of Handshake Signals + 0x0001000 // Maximum Block Transfer Size + }, + }, // End of Resource Group header + { + { + // Controller 0 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0001, // Resource Type + 0x20495053 // UID - SPI + }, + { + // Channel 0 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0000, // Resource Type + 0x30414843 // UID - CHA0 + }, + { + // Channel 1 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0000, // Resource Type + 0x31414843 // UID - CHA1 + }, + { + // Channel 2 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0000, // Resource Type + 0x32414843 // UID - CHA2 + }, + { + // Channel 3 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0000, // Resource Type + 0x33414843 // UID - CHA3 + }, + { + // Channel 4 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0000, // Resource Type + 0x34414843 // UID - CHA4 + }, + { + // Channel 5 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0000, // Resource Type + 0x35414843 // UID - CHA5 + } + } + }, + { + // + // LPIO2 DMA RESOURCE_GROUP_INFO2 + // + { //RESOURCE_GROUP_HEADER Start + sizeof(RESOURCE_GROUP_INFO2),// sizeof(RESOURCE_GROUP_INFO) + 0x4C544E49, + 0x00000000, + 0x9C60, + 0x0000, + 0x0003, + 0x0000, + sizeof(SHARED_INFO_SECTION), + { + // Shared Info Section + 0x0001, // Major Version 1 + 0x0000, // Minor Version 0 + 0x55AA55AA, // MMIO Base - Low Part + 0x00000000, // MMIO Base - High Part + 0x0000002B, // Interrupt GSI 43 + 0x02, // Interrupt Polarity + 0x00, // Interrupt Mode + 0x08, // Number of Channels + 0x20, // DMA Address Width + 0x0010, // Base Request Line + 0x0010, // Number of Handshake Signals + 0x0001000 // Maximum Block Transfer Size + }, + }, // End of Resource Group header + { + { + // Controller 0 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0001, // Resource Type + 0x20433249 // UID - I2C + }, + { + // Channel 0 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0000, // Resource Type + 0x30414843 // UID - CHA0 + }, + { + // Channel 1 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0000, // Resource Type + 0x31414843 // UID - CHA1 + }, + { + // Channel 2 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0000, // Resource Type + 0x32414843 // UID - CHA2 + }, + { + // Channel 3 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0000, // Resource Type + 0x33414843 // UID - CHA3 + }, + { + // Channel 4 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0000, // Resource Type + 0x34414843 // UID - CHA4 + }, + { + // Channel 5 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0000, // Resource Type + 0x35414843 // UID - CHA5 + }, + { + // Channel 6 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0000, // Resource Type + 0x36414843 // UID - CHA6 + }, + { + // Channel 7 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0000, // Resource Type + 0x37414843 // UID - CHA7 + } + } + }//LPIO2 DMA RESOURCE_GROUP_INFO2 End +}; + +// +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from + // removing the data structure from the executable + // + return (VOID*)&Csrt; +} diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Csrt.h b/ChvRefCodePkg/AcpiTablesPCAT/Csrt.h new file mode 100644 index 0000000000..e8095e60e0 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Csrt.h @@ -0,0 +1,86 @@ +/** @file + + Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// +// CSRT Definitions +// + +#define EFI_ACPI_CSRT_TABLE_REVISION 0x00000000 + +#define NUMBER_RESOURCE_GROUP_INFO 1 //2 + +#define MAX_NO_CHANNEL1_SUPPORTED 7 +#define MAX_NO_CHANNEL2_SUPPORTED 9 + +#define NAMESPACE_STRING_MAX_LENGTH 16 + +// +// Ensure proper structure formats +// +#pragma pack (1) + +typedef struct _SHARED_INFO_SECTION { + UINT16 MajVersion; + UINT16 MinVersion; + UINT32 MMIOLowPart; + UINT32 MMIOHighPart; + UINT32 IntGSI; + UINT8 IntPol; + UINT8 IntMode; + UINT8 NoOfCh; + UINT8 DMAAddressWidth; + UINT16 BaseReqLine; + UINT16 NoOfHandSig; + UINT32 MaxBlockTransferSize; + } SHARED_INFO_SECTION; + +typedef struct _RESOURCE_GROUP_HEADER { + UINT32 Length; + UINT32 VendorId; + UINT32 SubVendorId; + UINT16 DeviceId; + UINT16 SubDeviceId; + UINT16 Revision; + UINT16 Reserved; + UINT32 SharedInfoLength; + SHARED_INFO_SECTION SharedInfoSection; +} RESOURCE_GROUP_HEADER; + +typedef struct _RESOURCE_DESCRIPTOR { + UINT32 Length; + UINT16 ResourceType; + UINT16 ResourceSubType; + UINT32 UUID; + } RESOURCE_DESCRIPTOR; + +typedef struct { + RESOURCE_GROUP_HEADER ResourceGroupHeaderInfo; + RESOURCE_DESCRIPTOR ResourceDescriptorInfo[MAX_NO_CHANNEL1_SUPPORTED]; + } RESOURCE_GROUP_INFO1; + +typedef struct { + RESOURCE_GROUP_HEADER ResourceGroupHeaderInfo; + RESOURCE_DESCRIPTOR ResourceDescriptorInfo[MAX_NO_CHANNEL2_SUPPORTED]; + } RESOURCE_GROUP_INFO2; + +// +// DBGP structure +// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + RESOURCE_GROUP_INFO1 ResourceGroupsInfo1; + RESOURCE_GROUP_INFO2 ResourceGroupsInfo2; +} EFI_ACPI_CSRT_TABLE; + +#pragma pack () diff --git a/ChvRefCodePkg/AcpiTablesPCAT/DBG2/DBG2.aslc b/ChvRefCodePkg/AcpiTablesPCAT/DBG2/DBG2.aslc new file mode 100644 index 0000000000..e223a4c954 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/DBG2/DBG2.aslc @@ -0,0 +1,172 @@ +/** @file + The Debug Port Table 2. + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include "AcpiTablePlatform.h" + +// +// ACPI table information used to initialize tables. +// +#define EFI_ACPI_OEM_ID 'I','N','T','E','L',' ' // OEMID 6 bytes long +#define EFI_ACPI_OEM_REVISION 0x00000003 +#define EFI_ACPI_CREATOR_REVISION 0x0100000D +#define EFI_ACPI_CREATOR_ID SIGNATURE_32 ('V', 'L', 'V', '2') + +// +// DBG2 Definitions +// +#define EFI_ACPI_OEM_DBG2_TABLE_REVISION 0x00000000 +//#define NUMBER_DBG_DEVICE_INFO 2 +#define NUMBER_DBG_DEVICE_INFO 1 +#define DEBUG_DEVICE_INFORMATION_REVISION 0x00 +#define NAMESPACE_STRING_MAX_LENGTH 16 +#define EFI_ACPI_OEM_TABLE_ID_2 SIGNATURE_64('I','N','T','L','D','B','G','2') //Oem table Id for Dbg2 +// +// Ensure proper structure formats +// +#pragma pack (1) + +typedef struct _DEBUG_DEVICE_INFORMATION { + UINT8 Revision; + UINT16 Length; + UINT8 NumberOfGenericAddressRegisters; + UINT16 NameSpaceStringLength; + UINT16 NameSpaceStringOffset; + UINT16 OemDataLength; + UINT16 OemDataOffset; + UINT16 PortType; + UINT16 PortSubtype; + UINT16 Reserved; + UINT16 BaseAddressRegisterOffset; + UINT16 AddressSizeOffset; + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister[1]; + UINT32 AddressSize[1]; + CHAR8 NamespaceString[NAMESPACE_STRING_MAX_LENGTH]; + // UINT8 OemData[OemDataLength]; +} DEBUG_DEVICE_INFORMATION; + + +// +// DBGP structure +// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 OffsetDbgDeviceInfo; + UINT32 NumberDbgDeviceInfo; + DEBUG_DEVICE_INFORMATION DbgDeviceInfo[NUMBER_DBG_DEVICE_INFO]; +} EFI_ACPI_DEBUG_PORT_2_TABLE; + +#pragma pack () + +// +// Debug Port Table +// +EFI_ACPI_DEBUG_PORT_2_TABLE Dbg2 = { + { + EFI_ACPI_5_0_DEBUG_PORT_2_TABLE_SIGNATURE, + sizeof(EFI_ACPI_DEBUG_PORT_2_TABLE), + EFI_ACPI_OEM_DBG2_TABLE_REVISION, + 0, // to make sum of entire table == 0 + EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field + EFI_ACPI_OEM_TABLE_ID_2, // OEM table identification(8 bytes long) + EFI_ACPI_OEM_REVISION, // OEM revision + EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID + EFI_ACPI_CREATOR_REVISION // ASL compiler revision number + }, + OFFSET_OF (EFI_ACPI_DEBUG_PORT_2_TABLE, DbgDeviceInfo), + NUMBER_DBG_DEVICE_INFO, + { + // + // COM1 + // + { + DEBUG_DEVICE_INFORMATION_REVISION, + sizeof(DEBUG_DEVICE_INFORMATION), + 1, // NumberOfGenericAddressRegisters + NAMESPACE_STRING_MAX_LENGTH, + OFFSET_OF (DEBUG_DEVICE_INFORMATION, NamespaceString), + 0, // OemDataLength + 0, // OemDataOffset + 0x08000, // PortType - Serial + 0x0000, // PortSubtype - 16550 compatible + 0, // Reserved + OFFSET_OF (DEBUG_DEVICE_INFORMATION, BaseAddressRegister), + OFFSET_OF (DEBUG_DEVICE_INFORMATION, AddressSize), + { + 0x01, // Address_Space_ID = 0 System Memory, 1 System IO + 0x08, // Register_Bit_Width = 8 bits + 0x00, // Register_Bit_offset + 0x00, // Reserved + 0x3F8 // Base addresse of COM1 + }, + { + sizeof (EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE) + }, + "\\_SB.PCI0.LPCB.IUR3", + // OemData + }, + + +/* + // + // USB OTG information + // + { + DEBUG_DEVICE_INFORMATION_REVISION, + sizeof(DEBUG_DEVICE_INFORMATION), + 1, // NumberOfGenericAddressRegisters + NAMESPACE_STRING_MAX_LENGTH, + OFFSET_OF (DEBUG_DEVICE_INFORMATION, NamespaceString), + 0, // OemDataLength + 0, // OemDataOffset + 0x08002, // PortType - USB + 0x0005, // PortSubtype - Chipidea USB OTG + 0, // Reserved + OFFSET_OF (DEBUG_DEVICE_INFORMATION, BaseAddressRegister), + OFFSET_OF (DEBUG_DEVICE_INFORMATION, AddressSize), + { + 0x00, // Address_Space_ID = System Memory + 0x20, // Register_Bit_Width = 32 bits + 0x00, // Register_Bit_offset + 0x00, // Reserved + 0xFFA60000 // Base addresse of SPI port 0 + }, + { + sizeof (EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE) + }, + "\\_SB.OTG0", + // OemData + } + +*/ + + + + } + +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from + // removing the data structure from the executable + // + return (VOID*)&Dbg2; +} diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Dsdt.asl b/ChvRefCodePkg/AcpiTablesPCAT/Dsdt.asl new file mode 100644 index 0000000000..dbc8588776 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Dsdt.asl @@ -0,0 +1,155 @@ +/** @file + Intel Corporation - ACPI Reference Code for the Cherryview + Family of Customer Reference Boards. + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + +DefinitionBlock ( + "DSDT.aml", + "DSDT", + 0x02, // DSDT revision. + // A Revision field value greater than or equal to 2 signifies that integers + // declared within the Definition Block are to be evaluated as 64-bit values + "INTEL", // OEM ID (6 byte string) + "CHV-SOC", // OEM table ID (8 byte string) + 0x0 // OEM version of DSDT table (4 byte Integer) + ) + +// BEGIN OF ASL SCOPE +{ + External(MDBG, MethodObj) + + Method(ADBG, 1, Serialized) + { + + Return(0) + } + +// Miscellaneous services enabled in Project + include ("token.asl") + include ("GlobalNvs.asl") + include ("Pch/PciTree.asl") + include ("Pch/Pch.asl") + include ("SystemAgent/Chv.asl") + include ("Cpu/Cpu.asl") + include ("Platform/Platform.asl") + +Scope(\_SB) + { + Device(PTID) + { + Name(_HID, EISAID("INT340E")) + Name(_CID, EISAID("PNP0C02")) + Name(IVER, 0x00030000) // Version 3 + Name(_STA, 0x00) + + Name(TSDL, Package() + { //DeviceClass type Name of Temperature Value + 0x00000000, "CPU Core 0 DTS", //not from ec + 0x00000000, "CPU Core 1 DTS", //not from ec + 0x00000003, "AmbientTempLocal", + 0x00000003, "AmbientTempRemote1", + 0x00000003, "AmbientTempRemote2", + 0x00000003, "CpuTempLocal", + 0x00000003, "CpuTempRemote", + 0x00000003, "DDRTempLocal", + 0x00000003, "DDRTempRemote", + 0x00000003, "EC Critical temp", + 0x00000003, "OS Critical trip point", // not from EC + 0x00000003, "OS Hot trip point", // not from EC + 0x00000003, "OS Passive trip point", // not from EC + 0x00000003, "OS Active 0 trip point", // not from EC + 0x0000000E, "TZ01 _TMP" // not from EC + }) + + Method(TSDD, 0, Serialized) + { + Name (TSDX, Package() { + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0x80000000, 0x80000000, 0x80000000 + }) + Store(Add(Multiply(\DTS1, 10), 2732), Index(TSDX, 0)) + Store(Add(Multiply(\DTS2, 10), 2732), Index(TSDX, 1)) + Store(Add(Multiply(\_SB.PCI0.LPCB.H_EC.ALT1, 10), 2732), Index(TSDX, 2)) + Store(Add(Multiply(\_SB.PCI0.LPCB.H_EC.ART1, 10), 2732), Index(TSDX, 3)) + Store(Add(Multiply(\_SB.PCI0.LPCB.H_EC.ART2, 10), 2732), Index(TSDX, 4)) + Store(Add(Multiply(\_SB.PCI0.LPCB.H_EC.LTMP, 10), 2732), Index(TSDX, 5)) + Store(Add(Multiply(\_SB.PCI0.LPCB.H_EC.TMPR, 10), 2732), Index(TSDX, 6)) + Store(Add(Multiply(\_SB.PCI0.LPCB.H_EC.D0TL, 10), 2732), Index(TSDX, 7)) + Store(Add(Multiply(\_SB.PCI0.LPCB.H_EC.DM0T, 10), 2732), Index(TSDX, 8)) + Store(Add(Multiply(\_SB.PCI0.LPCB.H_EC.CTMP, 10), 2732), Index(TSDX, 9)) + Store(\_TZ.TZ01._CRT, Index(TSDX, 10)) + Store(\_TZ.TZ01._HOT, Index(TSDX, 11)) + Store(\_TZ.TZ01._PSV, Index(TSDX, 12)) + Store(\_TZ.TZ01._AC0, Index(TSDX, 13)) + Store(\_TZ.TZ01._TMP, Index(TSDX, 14)) + Return(TSDX) + } + + Name(PSDL, Package() + {// DeviceClass type Name of Power Value + 0x00000000, "CPU Power" + }) + + Method(PSDD, 0, Serialized) + { + Name (PSDX, Package() {0x80000000}) + Store(100, Index(PSDX, 0)) + Return(PSDX) + } + + Name(OSDL, Package() + { // DeviceClass type Descriptive Name Unit + 0x00000004, "CPU Fan Duty Cycle", "RAW", + 0x00000004, "CPU Fan #1 Speed", "RPM" + }) + + Method(OSDD, 0, Serialized) + { + Name (OSDX, Package () {0x80000000, 0x80000000}) + Store(\_SB.PCI0.LPCB.H_EC.FDCY, Index(OSDX, 0)) + Store(\_SB.PCI0.LPCB.H_EC.CFSP, Index(OSDX, 1)) + Return(OSDX) + } + + Method (SDSP) + { + Return(10) // Sampling period + } + }//end of Device(PTID) + } // end \_SB scope + + include ("Platform/Thermal.asl") + include ("Platform/PciDrc.asl") + include ("SystemAgent/Video.asl") + include ("Platform/Gpe.asl") + +// Sleep states supported by Chipset/Board. +//---------------------------------------------------------------------- +// SSx - BIOS setup controlled enabled _Sx Sleep state status + Name(\_S0, Package(4){0x0,0x0,0,0}) // mandatory System state + Name(\_S3, Package(4){0x5,0x0,0,0}) +// Name(\_S4, Package(4){0x6,0x0,0,0}) + Name(\_S5, Package(4){0x7,0x0,0,0}) // mandatory System state + + Method(PTS, 1) { // METHOD CALLED FROM _PTS PRIOR TO ENTER ANY SLEEP STATE + If(Arg0) // entering any sleep state + { + } + } + Method(WAK, 1) { // METHOD CALLED FROM _WAK RIGHT AFTER WAKE UP + } +}// End of ASL File diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Facp/Facp.aslc b/ChvRefCodePkg/AcpiTablesPCAT/Facp/Facp.aslc new file mode 100644 index 0000000000..e7eb0f0cef --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Facp/Facp.aslc @@ -0,0 +1,182 @@ +/** @file + The fixed ACPI description Table (FADT) Structure + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include "AcpiTablePlatform.h" + +EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = { + { + EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + sizeof (EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE), + EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION, + 0, // to make sum of entire table == 0 + EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field + EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long) + EFI_ACPI_OEM_REVISION, // OEM revision number + EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID + EFI_ACPI_CREATOR_REVISION // ASL compiler revision number + }, + 0, // Physical addesss of FACS + 0, // Physical address of DSDT + INT_MODEL, // System Interrupt Model (ignored in 2k and later, must be 0 for 98) + PM_PROFILE, // Preferred PM Profile + SCI_INT_VECTOR, // System vector of SCI interrupt + SMI_CMD_IO_PORT, // Port address of SMI command port + ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI + ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI + S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state + PSTATE_CNT, // PState control + PM1a_EVT_BLK, // Port address of Power Mgt 1a Event Reg Blk + PM1b_EVT_BLK, // Port address of Power Mgt 1b Event Reg Blk + PM1a_CNT_BLK, // Port address of Power Mgt 1a Ctrl Reg Blk + PM1b_CNT_BLK, // Port address of Power Mgt 1b Ctrl Reg Blk + PM2_CNT_BLK, // Port address of Power Mgt 2 Ctrl Reg Blk + PM_TMR_BLK, // Port address of Power Mgt Timer Ctrl Reg Blk + GPE0_BLK, // Port addr of General Purpose Event 0 Reg Blk + GPE1_BLK, // Port addr of General Purpose Event 1 Reg Blk + PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk + PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk + PM2_CNT_LEN, // Byte Length of ports at pm2_cnt_blk + PM_TM_LEN, // Byte Length of ports at pm_tm_blk + GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk + GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk + GPE1_BASE, // offset in gpe model where gpe1 events start + CST_CNT, // _CST support + P_LVL2_LAT, // worst case HW latency to enter/exit C2 state + P_LVL3_LAT, // worst case HW latency to enter/exit C3 state + FLUSH_SIZE, // Size of area read to flush caches + FLUSH_STRIDE, // Stride used in flushing caches + DUTY_OFFSET, // bit location of duty cycle field in p_cnt reg + DUTY_WIDTH, // bit width of duty cycle field in p_cnt reg + DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM + MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM + CENTURY, // index to century in RTC CMOS RAM + IAPC_BOOT_ARCH, // IA-PCI Boot Architecture Flag + RESERVED, // reserved + FLAG, + { + EFI_ACPI_5_0_SYSTEM_IO, + 8, + 0, + 0, + 0xCF9 + }, + 0x06, // Hardware reset value + 0, 0, 0, // Reserved + 0, // XFirmwareCtrl + 0, // XDsdt + // + // X_PM1a Event Register Block + // + EFI_ACPI_5_0_SYSTEM_IO, + 0x20, + 0x00, + EFI_ACPI_3_0_DWORD, + PM1a_EVT_BLK, + + // + // X_PM1b Event Register Block + // + EFI_ACPI_5_0_SYSTEM_IO, + 0x00, + 0x00, + EFI_ACPI_RESERVED_BYTE, + PM1b_EVT_BLK, + + // + // X_PM1a Control Register Block + // + EFI_ACPI_5_0_SYSTEM_IO, + 0x10, + 0x00, + EFI_ACPI_3_0_WORD, + PM1a_CNT_BLK, + + // + // X_PM1b Control Register Block + // + EFI_ACPI_5_0_SYSTEM_IO, + 0x00, + 0x00, + EFI_ACPI_RESERVED_BYTE, + PM1b_CNT_BLK, + + // + // X_PM2 Control Register Block + // + EFI_ACPI_5_0_SYSTEM_IO, + 0x08, + 0x00, + EFI_ACPI_3_0_BYTE, + PM2_CNT_BLK, + + // + // X_PM Timer Control Register Block + // + EFI_ACPI_5_0_SYSTEM_IO, + 0x20, + 0x00, + EFI_ACPI_3_0_DWORD, + PM_TMR_BLK, + + // + // X_General Purpose Event 0 Register Block + // + EFI_ACPI_5_0_SYSTEM_IO, + 0x80, + 0x00, + EFI_ACPI_RESERVED_BYTE, + GPE0_BLK, + + // + // X_General Purpose Event 1 Register Block + // + EFI_ACPI_5_0_SYSTEM_IO, + 0x00, + 0x00, + EFI_ACPI_RESERVED_BYTE, + GPE1_BLK, + + // + // Sleep Control Register Block + // + EFI_ACPI_5_0_SYSTEM_IO, + 0x08, + 0x00, + EFI_ACPI_RESERVED_BYTE, + 0, + + // + // Sleep Status Register Block + // + EFI_ACPI_5_0_SYSTEM_IO, + 0x08, + 0x00, + EFI_ACPI_RESERVED_BYTE, + 0, +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from + // removing the data structure from the executable + // + return (VOID*)&FACP; +} diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Facs/Facs.aslc b/ChvRefCodePkg/AcpiTablesPCAT/Facs/Facs.aslc new file mode 100644 index 0000000000..dbea7be3a3 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Facs/Facs.aslc @@ -0,0 +1,77 @@ +/** @file + The firmware ACPI Control Structure + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// +// Statements that include other files +// + +#include +#include +#include "AcpiTablePlatform.h" + +EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE FACS = { + EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, + sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE), + + // + // Hardware Signature will be updated at runtime + // + 0x00000000, //HardwareSignature + 0x00000000, //FirmwareWakingVector + 0x00000000, //GlobalLock + 0x00000000, //Flags + 0x0000000000000000, //XFirmwareWakingVector + EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, + EFI_ACPI_RESERVED_BYTE, //Reserved0[3] + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + 0x00000000, //OspmFlags + EFI_ACPI_RESERVED_BYTE, //Reserved1[24] + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from + // removing the data structure from the executable + // + return (VOID*)&FACS; +} diff --git a/ChvRefCodePkg/AcpiTablesPCAT/GlobalNvs.asl b/ChvRefCodePkg/AcpiTablesPCAT/GlobalNvs.asl new file mode 100644 index 0000000000..196a5e6f69 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/GlobalNvs.asl @@ -0,0 +1,392 @@ +/** @file + ACPI DSDT table + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + // + // Define a Global region of ACPI NVS Region that may be used for any + // type of implementation. The starting offset and size will be fixed + // up by the System BIOS during POST. Note that the Size must be a word + // in size to be fixed up correctly. + // + + OperationRegion(GNVS,SystemMemory,0xFFFF0000,0xAA55) + Field(GNVS,AnyAcc,Lock,Preserve) + { + Offset(0), // Miscellaneous Dynamic Registers: + OSYS, 16, // (00) Operating System + SMIF, 8, // (02) SMI Function Call (ASL to SMI via I/O Trap) + P80D, 32, // (03) Port 80 Debug Port Value + REVS, 8, // (07) Revision of the structure EFI_GLOBAL_NVS_AREA + OSID, 8, // (08) OS identification. + ADED, 8, // (09) Enable Or Disable Acpi Device Nodes + BDID, 8, // (10) Board ID + FBID, 8, // (11) FAB ID + ECSP, 8, // (12) EC Support + FNSP, 8, // (13) Fan Support + BTSP, 8, // (14) Battery Support +// Reserved51[9]; // Reserved for Platform Policies + +// +// Processor Configuration Values +// + Offset(24), + APIC, 8, // (24) APIC Enabled by SBIOS (APIC Enabled = 1) + MPEN, 8, // (25) Number of Logical Processors if MP Enabled != 0 + PPMF, 32, // (26) PPM configuration Flags (Same as CFGD) + PWRS, 8, // (30) Power State (AC Mode = 1) +// Reserved52[10]; // Reserved for CPU Policies + +// +// System Agent Policies +// + Offset(41), // Internal Graphics Registers: + IGDS, 8, // (41) IGD State (Primary Display = 1) + TLST, 8, // (42) Display Toggle List Selection + CADL, 8, // (43) Current Attached Device List + PADL, 8, // (44) Previous Attached Device List + CSTE, 16, // (45) Current Display State + NSTE, 16, // (47) Next Display State + NDID, 8, // (49) Number of Valid Device IDs + DID1, 32, // (50) Device ID 1 + DID2, 32, // (54) Device ID 2 + DID3, 32, // (58) Device ID 3 + DID4, 32, // (62) Device ID 4 + DID5, 32, // (66) Device ID 5 + DID6, 32, // (70) Device ID 6 + DID7, 32, // (74) Device ID 7 + DID8, 32, // (78) Device ID 8 + ASLB, 32, // (82) IGD OpRegion base address + IBTT, 8, // (86) IGD Boot Display Device + IPAT, 8, // (87) IGD Panel Type CMOs option + ITVF, 8, // (88) IGD TV Format CMOS option + ITVM, 8, // (89) IGD TV Minor Format CMOS option + IPSC, 8, // (90) IGD Panel Scaling + IBLC, 8, // (91) IGD BLC Configuration + IBIA, 8, // (92) IGD BIA Configuration + ISSC, 8, // (93) IGD SSC Configuration + IDMM, 8, // (94) IGD Power Conservation Feature Flag + IDMS, 8, // (95) IGD DVMT Memory Size + IF1E, 8, // (96) IGD Function 1 Enable + GSMI, 8, // (97) GMCH SMI/SCI mode (0=SCI) + PAVP, 8, // (98) IGD PAVP data + PVDR, 8, // (99) MIPI Display Panel Vendor + BLCS, 8, // (100) Backlight Control Registers: + BRTL, 8, // (101) Brightness Level Percentage +// Offset(102), // Ambient Light Sensor Registers: + ALSE, 8, // (102) ALS Enable + ALAF, 8, // (103) Ambient Light Adjusment Factor + LLOW, 8, // (104) LUX Low Value + LHIH, 8, // (105) LUX High Value + ISPA, 32, // (106) ISP Base Address + ISPD, 8, // (110) ISP Device Selection 0: Disabled; 1: PCI Device 2; 2: PCI Device 3 + RCAM, 8, // (111) Camera selection 0 - Cynthiana_A, 1 - Cynthiana_2B + ECAM, 8, // (112) COMBO AIC 0 - Disable, 1 - Enable + NVGA, 32, // (113) NVIG opregion address + NVHA, 32, // (117) NVHM opregion address + AMDA, 32, // (121) AMDA opregion address + HGMD, 8, // (125) HG Mode (0=Disabled, 1=HG Muxed, 2=HG Muxless, 3=DGPU Only) + GBAS, 32, // (126) GPIO Base Address + XBAS, 32, // (130) Any Device's PCIe Config Space Base Address + HGGP, 8, // (134) HG GPIO Support + DLPW, 16, // (135) Delay after Power Enable + DLHR, 16, // (137) Delay after Hold Reset + HRCO, 32, // (139) dGPU HLD RST GPIO Community Offset + HRPO, 32, // (143) dGPU HLD RST GPIO Pin Offset + HRAI, 8, // (147) dGPU HLD RST GPIO Active Information + PECO, 32, // (148) dGPU PWR Enable GPIO Community Offset + PEPO, 32, // (152) dGPU PWR Enable GPIO Pin Offset + PEAI, 8, // (156) dGPU PWR Enable GPIO Active Information + CPSP, 32, // (157) PEG Endpoint Capability Structure Presence (Bit 0: Virtual Channel Capability) + EECP, 8, // (161) PEG Endpoint PCIe Capability Structure Offset + EVCP, 16, // (162) PEG Endpoint Virtual Channel Capability Structure Offset + RPBA, 32, // (164) dGPU Root Port Base Address + DIDX, 32, // (168) Device ID for eDP device + EDPV, 8, // (172) Check for eDP display device + +// Reserved53[9]; // (173 : 181) Reserved for North Cluster policies + +// +// Security Policies +// + Offset(182), // + , 8, // (182) + , 8, // (183) + , 32, // (184) + , 32, // (188) + , 8, // (192) + , 8, // (193) + , 32, // (194) + , 8, // (198) + , 8, // (199) + I0D3, 8, // (200) I2C 1 Runtime D3 Support + I1D3, 8, // (201) I2C 2 Runtime D3 Support + I2D3, 8, // (202) I2C 3 Runtime D3 Support + I3D3, 8, // (203) I2C 4 Runtime D3 Support + I4D3, 8, // (204) I2C 5 Runtime D3 Support + I5D3, 8, // (205) I2C 6 Runtime D3 Support + I6D3, 8, // (206) I2C 7 Runtime D3 Support +// Reserved54[3]; // (207: 209) Reserved for Security policies + +// +// PCH policies +// + Offset(210), + LPES, 8, // (210) LPE Audio Setup Control 0: Disabled 1:Enabled +//Reserved [9] + + Offset(220), + OTG0, 32, // (220) USB OTG BAR0 + OTG1, 32, // (224) USB OTG BAR1 + OTGM, 8, // (228) OTG mode + LPE0, 32, // (229) LPE Bar0 + LPE1, 32, // (233) LPE Bar1 + LPE2, 32, // (237) LPE Bar2 + PFLV, 8, // (241) Platform Flavor 0:unknown 1: Mobile; 2: desktop + XHCI, 8, // (242) xHCI controller mode + PMEN, 8, // (243) PMIC enable/disable + USEL, 8, // (244) UART Interface Selection + BTHS, 8, // (245) BlueTooth selection 0 - Other than PR0, 1 - PR0 which swap the GPIO + EMVR, 8, // (246) eMMC controller version + GOAE, 8, // (247) GPIO ACPI Devices Enabled +// Offset(248), // LPSS Controllers + D10A, 32, // (248) DMA1 BAR0 + D10L, 32, // (252) DMA1 BAR0 Length + D11A, 32, // (256) DMA1 BAR1 + D11L, 32, // (260) DMA1 BAR1 Length + P10A, 32, // (264) PWM1 BAR0 + P10L, 32, // (268) PWM1 BAR0 Length + P11A, 32, // (272) PWM1 BAR1 + P11L, 32, // (276) PWM1 BAR1 Length + P20A, 32, // (280) PWM2 BAR0 + P20L, 32, // (284) PWM2 BAR0 Length + P21A, 32, // (288) PWM2 BAR1 + P21L, 32, // (292) PWM2 BAR1 Length + U10A, 32, // (296) HSUART BAR0 + U10L, 32, // (300) HSUART BAR0 Length + U11A, 32, // (304) HSUART BAR1 + U11L, 32, // (308) HSUART BAR1 Length + U20A, 32, // (312) HSUART2 BAR0 + U20L, 32, // (316) HSUART2 BAR0 Length + U21A, 32, // (320) HSUART2 BAR1 + U21L, 32, // (324) HSUART2 BAR1 Length + SP0A, 32, // (328) SPI BAR0 + SP0L, 32, // (332) SPI BAR0 Length + SP1A, 32, // (336) SPI BAR1 + SP1L, 32, // (340) SPI BAR1 Length + S20A, 32, // (344) SPI2 BAR0 + S20L, 32, // (348) SPI2 BAR0 Length + S21A, 32, // (352) SPI2 BAR1 + S21L, 32, // (356) SPI2 BAR1 Length + S30A, 32, // (360) SPI3 BAR0 + S30L, 32, // (364) SPI3 BAR0 Length + S31A, 32, // (368) SPI3 BAR1 + S31L, 32, // (372) SPI3 BAR1 Length + D20A, 32, // (376) DMA2 BAR0 + D20L, 32, // (380) DMA2 BAR0 Length + D21A, 32, // (384) DMA2 BAR1 + D21L, 32, // (388) DMA2 BAR1 Length + I10A, 32, // (392) I2C1 BAR0 + I10L, 32, // (396) I2C1 BAR0 Length + I11A, 32, // (400) I2C1 BAR1 + I11L, 32, // (404) I2C1 BAR1 Length + I20A, 32, // (408) I2C2 BAR0 + I20L, 32, // (412) I2C2 BAR0 Length + I21A, 32, // (416) I2C2 BAR1 + I21L, 32, // (420) I2C2 BAR1 Length + I30A, 32, // (424) I2C3 BAR0 + I30L, 32, // (428) I2C3 BAR0 Length + I31A, 32, // (432) I2C3 BAR1 + I31L, 32, // (436) I2C3 BAR1 Length + I40A, 32, // (440) I2C4 BAR0 + I40L, 32, // (444) I2C4 BAR0 Length + I41A, 32, // (448) I2C4 BAR1 + I41L, 32, // (452) I2C4 BAR1 Length + I50A, 32, // (456) I2C5 BAR0 + I50L, 32, // (460) I2C5 BAR0 Length + I51A, 32, // (464)I2C5 BAR1 + I51L, 32, // (468) I2C5 BAR1 Length + I60A, 32, // (472) I2C6 BAR0 + I60L, 32, // (476) I2C6 BAR0 Length + I61A, 32, // (480) I2C6 BAR1 + I61L, 32, // (484) I2C6 BAR1 Length + I70A, 32, // (488) I2C7 BAR0 + I70L, 32, // (492) I2C7 BAR0 Length + I71A, 32, // (496) I2C7 BAR1 + I71L, 32, // (500) I2C7 BAR1 Length +// Offset(504), // SCC Controllers + eM0A, 32, // (504) eMMC BAR0 + eM0L, 32, // (508) eMMC BAR0 Length + eM1A, 32, // (512) eMMC BAR1 + eM1L, 32, // (516) eMMC BAR1 Length + SI0A, 32, // (520) SDIO BAR0 + SI0L, 32, // (524) SDIO BAR0 Length + SI1A, 32, // (528) SDIO BAR1 + SI1L, 32, // (532) SDIO BAR1 Length + SD0A, 32, // (536) SDCard BAR0 + SD0L, 32, // (540) SDCard BAR0 Length + SD1A, 32, // (544) SDCard BAR1 + SD1L, 32, // (548) SDCard BAR1 Length + ISH0, 32, // (552) ISH BAR0 + ISH1, 32, // (556) ISH BAR1 + VS18, 16, // (560) SD Card 1.8v Switching Delay (ms) + VD33, 16, // (562) SD Card 3.3v Discahrge Delay (ms) + , 16, // (564) + , 16, // (566) + ITSA, 8, // (568) I2C Touch Screen Address + S0IX, 8, // (569) S0ix status + SDMD, 8, // (570) SDIO Mode + ELLN, 8, // (571) EllensBurg Support 1 - Enable, 0 - Disable + AUCD, 8, // (572) Audio Codec Support 5645 - EB, 5640/5672 - RVP + BTMS, 8, // (573) BT Module Select: BCRM or STP + PMCT, 8, // (574) Pmic Type + PSSD, 8, // (575) Pre-Sillicon Work Arounds for ASL. 1-PSSD, 0-Normal +// Reserved55[9]; // (576: 584) Reserved for PCH policies + +// +// Platform policies +// + Offset(585), + OSCC, 8, // (585) PCIE OSC Control + NEXP, 8, // (586) Native PCIE Setup Value + GPIC, 8, // (587) Global IOAPIC/8259 Interrupt Mode Flag. + L01C, 8, // (588) Global L01 Counter. + MODS, 8, // (589) Modem Selection + PB1E, 8, // (590) Virtual Power Button Support + // Bit0: Enable/Disable Virtual Button (0 - Disable; 1- Enable) + // Bit1: Internal Flag + // Bit2: Rotation Lock flag, 0:unlock, 1:lock + // Bit3: Slate/Laptop Mode Flag, 0: Slate, 1: Laptop / CalmShell + // Bit4: Undock / Dock Flag, 0: Undock, 1: Dock + // Bit5, 6: reserved for future use. + // Bit7: EC 10sec PB Override state for S3/S4 wake up. + PSDE, 8, // (591) PSS Device Selection + ISCT, 8, // (592) Reserved + LIDS, 8, // (593) Lid State (Lid Open = 1) + DSEN, 8, // (594) _DOS Display Support Flag. + ECON, 8, // (595) Embedded Controller Availability Flag. + +// Offset(596), // Thermal Policy Registers: + ACT1, 8, // (596) Active Trip Point 1 + ACTT, 8, // (597) Active Trip Point + PSVT, 8, // (598) Passive Trip Point + TC1V, 8, // (599) Passive Trip Point TC1 Value + TC2V, 8, // (600) Passive Trip Point TC2 Value + TSPV, 8, // (601) Passive Trip Point TSP Value + CRTT, 8, // (602) Critical Trip Point + DTSE, 8, // (603) Digital Thermal Sensor Enable + DTS1, 8, // (604) Digital Thermal Sensor 1 Reading Temperature of BSP + DTS2, 8, // (605) Digital Thermal Sensor 2 Reading Temperature of AP + DTSF, 8, // (606) DTS SMI Function Call via DTS IO Trap + CTYP, 8, // (607) Global Cooling Type Flag. + VFN0, 8, // (608) Virtual Fan0 Status. + STTV, 16, // (609) 10 - Minimum 500 - Maximum + +// Offset(611), // Battery Support Registers: + BNUM, 8, // (611) Battery Number Present + B0SC, 8, // (612) Battery 0 Stored Capacity + B1SC, 8, // (613) Battery 1 Stored Capacity + B0SS, 8, // (614) Battery 0 Stored Status + B1SS, 8, // (615) Battery 1 Stored Status + BCSL, 8, // (616) Battery charging solution 0-CLV 1-ULPMC + DBAT, 8, // (617) Disable Battery MSFT PAC Requirement + NATP, 8, // (618) Dock SIO Present + CMCP, 8, // (619) NPCE COM Port + CIRP, 8, // (620) Onboard COM CIR Port + W381, 8, // (621) W8374L + +// Offset(622), // DPTF + DPTE, 8, // (622) DPTF Enable + THM0, 8, // (623) System Thermal Sensor 0 + THM1, 8, // (624) System Thermal Sensor 1 + THM2, 8, // (625) System Thermal Sensor 2 + THM3, 8, // (626) System Thermal Sensor 3 + THM4, 8, // (627) System Thermal Sensor 4 + CHGR, 8, // (628) DPTF Changer Device + DDSP, 8, // (629) DPTF Display Device + DSOC, 8, // (630) DPTF SoC device + DPSR, 8, // (631) DPTF Processor device + DPCT, 32, // (632) DPTF Processor participant critical temperature + DPPT, 32, // (636) DPTF Processor participant passive temperature + DGC0, 32, // (640) DPTF Generic sensor0 participant critical temperature + DGP0, 32, // (644) DPTF Generic sensor0 participant passive temperature + DGC1, 32, // (648) DPTF Generic sensor1 participant critical temperature + DGP1, 32, // (652) DPTF Generic sensor1 participant passive temperature + DGC2, 32, // (656) DPTF Generic sensor2 participant critical temperature + DGP2, 32, // (660) DPTF Generic sensor2 participant passive temperature + DGC3, 32, // (664) DPTF Generic sensor3 participant critical temperature + DGP3, 32, // (668) DPTF Generic sensor3 participant passive temperature + DGC4, 32, // (672) DPTF Generic sensor4 participant critical temperature + DGP4, 32, // (676) DPTF Generic sensor4 participant passive temperature + DLPM, 8, // (680) DPTF Current low power mode setting + DSC0, 32, // (681) DPTF Critical threshold0 for SCU + DSC1, 32, // (685) DPTF Critical threshold1 for SCU + DSC2, 32, // (689) DPTF Critical threshold2 for SCU + DSC3, 32, // (693) DPTF Critical threshold3 for SCU + DSC4, 32, // (697) DPTF Critical threshold4 for SCU + DDBG, 8, // (701) DPTF Super Debug option. 0 - Disabled, 1 - Enabled + LPOE, 32, // (702) DPTF LPO Enable + LPPS, 32, // (706) P-State start index + LPST, 32, // (710) Step size + LPPC, 32, // (714) Power control setting + LPPF, 32, // (718) Performance control setting + DPME, 8, // (722) DPTF DPPM enable/disable + WWEN, 8, // (723) WWAN Enable + WWCR, 32, // (724) WWAN CRT + WWPS, 32, // (728) WWAN PSV + RSVD, 8, // (732) DPTF Memory Participant + ABS0, 8, // (733) Sign for ABC0 + ABS1, 8, // (734) Sign for ABC1 + ABS2, 8, // (735) Sign for ABC2 + ABS3, 8, // (736) Sign for ABC3 + ABS4, 8, // (737) Sign for ABC4 + ABS5, 8, // (738) Sign for ABC5 + AMTE, 8, // (739) Ambient Trip point change + ABC0, 8, // (740) Ambient Participant Constants + ABC1, 8, // (741) + ABC2, 8, // (742) + ABC3, 8, // (743) + ABC4, 8, // (744) + ABC5, 8, // (745) + DPHL, 8, // (746) + DPLL, 8, // (747) + + NFCS, 8, // (748) NFCx Connect 1: NFC1 to I2C7 2:NFC2 to SEC + BMBD, 32, // (749) BM Bound + FSAS, 8, // (753) FSA Status + + WIFD, 8, // (754) WIFI device selection (0:STP 1:BCM) + DPPP, 8, // (755) EnablePassivePolicy + DPCP, 8, // (756) EnableCriticalPolicy + DPAP, 8, // (757) EnableActivePolicy + DGA0, 32, // (758) DPTF Generic sensor0 participant Active temperature + DGS0, 32, // (762) DPTF Generic sensor0 participant CR3 temperature + DGH0, 32, // (766) DPTF Generic sensor0 participant HOT temperature + DGA1, 32, // (770) DPTF Generic sensor1 participant Active temperature + DGS1, 32, // (774) DPTF Generic sensor1 participant CR3 temperature + DGH1, 32, // (778) DPTF Generic sensor1 participant HOT temperature + DGA2, 32, // (782) DPTF Generic sensor2 participant Active temperature + DGS2, 32, // (786) DPTF Generic sensor2 participant CR3 temperature + DGH2, 32, // (790) DPTF Generic sensor2 participant HOT temperature + SAAT, 32, // (794) DPTF Processor participant active temperature + SACT, 32, // (798) DPTF Processor participant critical temperature + SAST, 32, // (802) DPTF Processor participant CR3 temperature + SAHT, 32, // (806) DPTF Processor participant Hot temperature + SAPT, 32, // (810) DPTF Processor participant passive temperature + SCDD, 8, // (814) Toggle Self Clock Disabling feature in ASL, 0-Disable 1-Enable + ISPE, 8, // (815) ISP Device Enable/Disable + PAVB, 32, // (816) PAVP Memory Base + PAVL, 32, // (820) PAVP Memory Length + DRMB, 64, // (824) DRM DMA Allocated Buffer Address + } + diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Hpet/Hpet.aslc b/ChvRefCodePkg/AcpiTablesPCAT/Hpet/Hpet.aslc new file mode 100644 index 0000000000..7c0ef9918c --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Hpet/Hpet.aslc @@ -0,0 +1,59 @@ +/** @file + The High Precision Event Timer Table + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// +// Statements that include other files +// + +#include +#include "AcpiTablePlatform.h" + +// Hpet Table +EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER HPET = { + { + EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE, + sizeof (EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER), + EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_REVISION, + 0, // to make sum of entire table == 0 + EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field + EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long) + EFI_ACPI_OEM_REVISION, // OEM revision + EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID + EFI_ACPI_CREATOR_REVISION // ASL compiler revision number + }, + 0x0, // EventTimerBlockId + { + 0x00, // Address_Space_ID = System Memory + 0x40, // Register_Bit_Width = 32 bits, mentioned about write failures when in 64bit in SCU HAS + 0x00, // Register_Bit_offset + 0x00, // Dword access + HPET_BASE_ADDRESS, // Base addresse of HPET + }, + 0x0, // Only HPET's _UID in Namespace + MAIN_COUNTER_MIN_PERIODIC_CLOCK_TICKS, + 0x0 +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from + // removing the data structure from the executable + // + return (VOID*)&HPET; +} diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Hpet/Hpet.h b/ChvRefCodePkg/AcpiTablesPCAT/Hpet/Hpet.h new file mode 100644 index 0000000000..d0e9e4a949 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Hpet/Hpet.h @@ -0,0 +1,38 @@ +/** @file + This file describes the contents of the ACPI HPET Table. + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _HPET_H +#define _HPET_H + +// +// Statements that include other files +// + +#include +#include +#include +#include + +// +// HPET Definitions +// + +#define EFI_ACPI_HPET_TABLE_REVISION 0x1 +#define MAIN_COUNTER_MIN_PERIODIC_CLOCK_TICKS 0x80 //approx 1ms + +#define HPET_BASE_ADDRESS 0xFED00000 +#define EFI_ACPI_EVENT_TIMER_BLOCK_ID 0x8086A001 + +#endif diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Madt/Madt.h b/ChvRefCodePkg/AcpiTablesPCAT/Madt/Madt.h new file mode 100644 index 0000000000..31e248c2d6 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Madt/Madt.h @@ -0,0 +1,187 @@ +/** @file + This file describes the contents of the ACPI Multiple APIC Description + Table (MADT). Some additional ACPI values are defined in Acpi1_0.h and + Acpi2_0.h. + To make changes to the MADT, it is necessary to update the count for the + APIC structure being updated, and to modify table found in Madt.c. + + Copyright (c) 1996 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _MADT_H +#define _MADT_H + +// +// Statements that include other files +// +#include "AcpiTablePlatform.h" +#include +#include +#include +#include "Platform.h" + +// +// MADT Definitions +// +#define EFI_ACPI_OEM_MADT_REVISION 0x00000000 +// +// Multiple APIC Flags are defined in AcpiX.0.h +// +#define EFI_ACPI_1_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_1_0_PCAT_COMPAT) +#define EFI_ACPI_2_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_2_0_PCAT_COMPAT) +#define EFI_ACPI_3_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_3_0_PCAT_COMPAT) +#define EFI_ACPI_4_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_4_0_PCAT_COMPAT) + +// +// Define the number of each table type. +// This is where the table layout is modified. +// +#define EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT MAX_CPU_NUM +#define EFI_ACPI_LOCAL_APIC_NMI_COUNT MAX_CPU_NUM +#define EFI_ACPI_IO_APIC_COUNT 1 +#define EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT 2 +#define EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT 0 +#define EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT 0 +#define EFI_ACPI_IO_SAPIC_COUNT 0 +#define EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT 0 +#define EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT 0 + +// +// MADT structure +// +// +// Ensure proper structure formats +// +#pragma pack(1) +// +// ACPI 1.0 Table structure +// +typedef struct { + EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + +#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0 + EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT]; +#endif + +#if EFI_ACPI_IO_APIC_COUNT > 0 + EFI_ACPI_1_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT]; +#endif + +#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0 + EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT]; +#endif + +#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0 + EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT]; +#endif + +#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0 + EFI_ACPI_1_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT]; +#endif + +#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0 + EFI_ACPI_1_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT]; +#endif + +} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + +// +// ACPI 2.0 Table structure +// +typedef struct { + EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + +#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0 + EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT]; +#endif + +#if EFI_ACPI_IO_APIC_COUNT > 0 + EFI_ACPI_2_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT]; +#endif + +#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0 + EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT]; +#endif + +#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0 + EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT]; +#endif + +#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0 + EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT]; +#endif + +#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0 + EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT]; +#endif + +#if EFI_ACPI_IO_SAPIC_COUNT > 0 + EFI_ACPI_2_0_IO_SAPIC_STRUCTURE IoSapic[EFI_ACPI_IO_SAPIC_COUNT]; +#endif + +#if EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT > 0 + EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE LocalSapic[EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT]; +#endif + +#if EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT > 0 + EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE PlatformInterruptSources[EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT]; +#endif + +} EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + +// +// ACPI 3.0 Table structure +// +typedef struct { + EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + +#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0 // Type 0x00 + EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT]; +#endif + +#if EFI_ACPI_IO_APIC_COUNT > 0 // Type 0x01 + EFI_ACPI_3_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT]; +#endif + +#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0 // Type 0x02 + EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT]; +#endif + +#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0 // Type 0x03 + EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT]; +#endif + +#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0 // Type 0x04 + EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT]; +#endif + +#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0 // Type 0x05 + EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT]; +#endif + +#if EFI_ACPI_IO_SAPIC_COUNT > 0 // Type 0x06 + EFI_ACPI_3_0_IO_SAPIC_STRUCTURE IoSapic[EFI_ACPI_IO_SAPIC_COUNT]; +#endif + +#if EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT > 0 // Type 0x07 : This table changes in madt 2.0 + EFI_ACPI_3_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE LocalSapic[EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT]; +#endif + +#if EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT > 0 // Type 0x08 + EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE PlatformInterruptSources[EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT]; +#endif + +} EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + +#pragma pack() + +#endif diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Madt/Madt30.aslc b/ChvRefCodePkg/AcpiTablesPCAT/Madt/Madt30.aslc new file mode 100644 index 0000000000..9f1251a85e --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Madt/Madt30.aslc @@ -0,0 +1,216 @@ +/** @file + This file contains a structure definition for the ACPI 2.0 Multiple APIC + Description Table (MADT). Any changes to the MADT table require updating the + respective structure count in Madt.h and then adding the structure to the + MADT defined in this file. The table layout is defined in Madt.h and the + table contents are defined in Acpi3_0.h and Madt.h. + + Copyright (c) 1996 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// +// Statements that include other files +// +#include "Madt.h" +#include + +// +// Multiple APIC Description Table +// +// http://www.microsoft.com/whdc/system/cec/acpi-mp.mspx +// +EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { + EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, // **Signatures are the same 1.0-3.0 because it says "APIC". + sizeof (EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE), // **Length + EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION, + // + // EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION, // **Table Revision must be 2.0 for ACPI 3.0 + // Checksum will be updated at runtime + // + 0x00, // **Check sum + // + // It is expected that these values will be programmed at runtime + // + ' ', // OEMID + ' ', // Creative way to + ' ', // make six bytes + ' ', // of space in + ' ', // a table for + ' ', // **OEMID + 0, // **OEM Table ID + EFI_ACPI_OEM_MADT_REVISION, // **OEM Revision + 0, // **Creator ID + 0, // **Creator Revision + // + // MADT specific fields + // + LOCAL_APIC_ADDRESS, // **Local APIC Address + EFI_ACPI_4_0_MULTIPLE_APIC_FLAGS, // **Flags + // + // Processor Local APIC Structure + // Correct processor order, Primary threads first then Hyper threads + // And correct APIC-ids + // This text below is included as a reference until Thurley is 100%: + // According to EDS the Local APIC ID is determined based of a bit structure + // Bit 24: Core ID Bit 25: Core Pair ID Bit 26-27: Reserved Bit 28-30: Socket ID Bit 31: Reserved + // 4 Sockets and 4 Cores per Socket. + // So possible LAPIC IDs 00, 01, 02, 03, 10, 11, 12, 13, 20, 21, 22, 23, 30, 31, 32, 33 + // Static Entries 00, 10, 20, 30, 01, 11, 21, 31, 02, 12, 22, 32, 03, 13, 23, 33 + // BSP needs to be first entry in table. Check before boot. If BSP non zero need to rotate the entries. + // Suppore BSP is LAPIC ID xy. Rotate the table by using formula [x + (y * 4)] + // So if BSP LAPIC ID is 21 then table rotated 6 times. + // End of Reference Text. + // Thurley is supposed to be 2 sockets, 4 cores, and hyperthreading available per each core. + // 2 (sockets) x 4 (cores) = 8 (processors non-HT), 8 (processors non-HT) x 2 (HT/proc) = 16 (HT procs) + // Rhyme & reason of the ordering below. This is a best guess ordering for now, + // Thurley EPS may give better info on LAPIC numbers. + // Ordering was established to help dissipate heat across two sockets evenly. + // Since logical processor number only has to be unique, I followed + // a similar approach to high end servers and have the first digit of the LAPIC + // id the socket number. + // + EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC, // Type 0x00 + sizeof (EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x01, // Processor ID + 0x00, // Local APIC ID + 0x00000001, // Flags - Disabled (until initialized by platform driver) + EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC, // Type + sizeof (EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x02, // Processor ID + 0x02, // Local APIC ID //Todo: Temp change APIC ID order for fixing VLV X0 not enable 2 CPU in Windows. + 0x00000001, // Flags - Disabled (until initialized by platform driver) + EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC, // Type + sizeof (EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x03, // Processor ID + 0x04, // Local APIC ID + 0x00000001, // Flags - Disabled (until initialized by platform driver) + EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC, // Type + sizeof (EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x04, // Processor ID + 0x06, // Local APIC ID + 0x00000001, // Flags - Disabled (until initialized by platform driver) + // + // *************** IO APIC Structure ****************** + // + // + // + // ************************** I/O APIC (ICH) ************** + // + EFI_ACPI_3_0_IO_APIC, // Type 0x01 + sizeof (EFI_ACPI_3_0_IO_APIC_STRUCTURE), // Length + ICH_IOAPIC_ID, // IO APIC ID + EFI_ACPI_RESERVED_BYTE, // Reserved EFI_ACPI_RESERVED_BYTE + IO_APIC_ADDRESS, // IO APIC Address (physical) 0xFEC00000 + 0x18 * 0, // Global System Interrupt Base + + // + // Interrupt Source Override Structure: Sample + // + // EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE, // Type 0x02 + // sizeof (EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE),// Length + // 0x00, // Bus + // 0x00, // Source + // 0x00000000, // Global System Interrupt + // 0x0000, // Flags + // + // IRQ0=>IRQ2 Interrupt Source Override Structure + // + EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE, // Type 0x02 + sizeof (EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE), // Length + 0x00, // Bus - ISA + 0x00, // Source - IRQ0 + 0x00000002, // Global System Interrupt - IRQ2 + 0x0000, // Flags - Conforms to specifications of the bus + // + // ISO (SCI Active High) Interrupt Source Override Structure + // + EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE, // Type 0x02 + sizeof (EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE), // Length + 0x00, // Bus - ISA + 0x09, // Source - IRQ0 + 0x00000009, // Global System Interrupt - IRQ2 + 0x000D, // Flags - Level-tiggered, Active High + + // + // Non-Maskable Interrupt (NMIs) Source Structure: Sample + // + // EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE, // Type 0x03 + // sizeof (EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE), // Length + // 0x0000, // Flags + // 0x00000000, // Global System Interrupt + // + // Local APIC NMI Structure: Sample + // + // EFI_ACPI_2_0_LOCAL_APIC_NMI, // Type 0x04 + // sizeof (EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE), // Length + // 0x00, // ACPI Processor ID + // 0x0000, // Flags + // 0x00, // Local APIC LINT# + // >>> CORE_m008 Add Local APIC NMI tables for 2nd, 3rd and 4th physical processors. + // + // Assuming here that only need to entries for two sockets. + // +#if 1 + EFI_ACPI_3_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x01, // ACPI Processor ID + 0x000D, // Flags - Level-tiggered, Active High + 0x01, // Local APIC LINT# + EFI_ACPI_3_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x02, // ACPI Processor ID + 0x000D, // Flags - Level-tiggered, Active High + 0x01, // Local APIC LINT# + EFI_ACPI_3_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x03, // ACPI Processor ID + 0x000D, // Flags - Level-tiggered, Active High + 0x01, // Local APIC LINT# + EFI_ACPI_3_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x04, // ACPI Processor ID + 0x000D, // Flags - Level-tiggered, Active High + 0x01, // Local APIC LINT# +#endif + // + // Local APIC Address Override Structure: Sample + // + // EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE, // Type 0x5 + // sizeof (EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE), // Length + // EFI_ACPI_RESERVED_WORD, // Reserved + // 0x0000000000000000, // Local APIC Address + // + // Sample Platform Interrupt Sources Structure + // + // EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES, // Type 0x8 + // sizeof (EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE), // Length + // 0x0000, // Flags + // 0x00, // Interrupt Type + // 0x00, // Processor ID + // 0x00, // Processor EID + // 0x00, // IO SAPIC Vector + // 0x00000000, // Global System Interrupt + // EFI_ACPI_RESERVED_DWORD, // Reserved + // +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from + // removing the data structure from the executable + // + return (VOID*)&Madt; +} diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Mcfg/Mcfg.aslc b/ChvRefCodePkg/AcpiTablesPCAT/Mcfg/Mcfg.aslc new file mode 100644 index 0000000000..aec2d72b97 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Mcfg/Mcfg.aslc @@ -0,0 +1,83 @@ +/** @file + This file contains a structure definition for the ACPI Memory mapped + configuration space base address Description Table (MCFG). Any changes + to the MCFG table require updating the respective structure count in + Mcfg.h and then adding the structure to the MCFG defined in this file. + The table layout is defined in Mcfg.h and the table contents are defined + in McfgTable.h and Mcfg.h. + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// +// Statements that include other files +// +#include + +// +// MCFG Table definition +// +EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE MCFG = { + EFI_ACPI_3_0_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_SIGNATURE, + sizeof (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE), + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_REVISION, + // + // Checksum will be updated at runtime + // + 0x00, + // + // It is expected that these values will be programmed at runtime + // + ' ', + ' ', + ' ', + ' ', + ' ', + ' ', + + 0, + EFI_ACPI_OEM_MCFG_REVISION, + 0, + 0, + // + // Beginning of MCFG specific fields + // + EFI_ACPI_RESERVED_QWORD, + // + // Sample Memory Mapped Configuration Space Base Address Structure + // + // 0x0, // Base Address + // 0x0, // PCI Segment Group Number + // 0x0, // Start Bus Number + // 0x0, // End Bus Number + // EFI_ACPI_RESERVED_DWORD, // Reserved + // + // Memory Mapped Configuration Space Base Address Structure for BNB + // + 0x0, // Base Address, will be updated by AcpiPlatform + 0x0, // PCI Segment Group Number + 0x0, // Start Bus Number + PLATFORM_MAX_BUS_NUM, // End Bus Number + EFI_ACPI_RESERVED_DWORD, // Reserved +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from + // removing the data structure from the executable + // + return (VOID*)&MCFG; +} diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Mcfg/Mcfg.h b/ChvRefCodePkg/AcpiTablesPCAT/Mcfg/Mcfg.h new file mode 100644 index 0000000000..a88ecc1c7e --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Mcfg/Mcfg.h @@ -0,0 +1,64 @@ +/** @file + ACPI Memory mapped configuration space base address Description Table + implementation, based on PCI Firmware Specification Revision 3.0 final draft, + downloadable at http://www.pcisig.com/home + + Copyright (c) 1996 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _MCFG_H_ +#define _MCFG_H_ + +// +// Statements that include other files +// +#include +#include "McfgTable.h" +#include "Platform.h" +// +// "MCFG" Static Resource Affinity Table +// +#define EFI_ACPI_3_0_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_SIGNATURE 0x4746434D + +// +// MCFG Definitions, see specification for details. +// +#define EFI_ACPI_OEM_MCFG_REVISION 0x00000001 + +// +// Define the number of each table type. +// This is where the table layout is modified. +// +#define EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE_COUNT 1 + +// +// MCFG Table definition. The table must be defined in a platform +// specific manner. +// +// +// Ensure proper structure formats +// +#pragma pack(1) + +typedef struct { + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header; + +#if EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE_COUNT > 0 + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE Segment[ + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE_COUNT]; +#endif + +} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE; + +#pragma pack() + +#endif // _MCFG_H_ diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Mcfg/McfgTable.h b/ChvRefCodePkg/AcpiTablesPCAT/Mcfg/McfgTable.h new file mode 100644 index 0000000000..433119ca04 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Mcfg/McfgTable.h @@ -0,0 +1,61 @@ +/** @file + ACPI Memory mapped configuration space base address Description Table + definition, based on PCI Firmware Specification Revision 3.0 final draft, + downloadable at http://www.pcisig.com/home + + Copyright (c) 1996 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _MCFG_TABLE_H_ +#define _MCFG_TABLE_H_ + +// +// Include files +// +#include + +// +// Ensure proper structure formats +// +#pragma pack(1) +// +// MCFG Revision (defined in spec) +// +#define EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_REVISION 0x01 + +// +// MCFG Structure Definitions +// +// +// Memory Mapped Enhanced Configuration Base Address Allocation +// Structure Definition +// +typedef struct { + UINT64 BaseAddress; + UINT16 PciSegmentGroupNumber; + UINT8 StartBusNumber; + UINT8 EndBusNumber; + UINT32 Reserved; +} EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE; + +// +// MCFG Table header definition. The rest of the table +// must be defined in a platform specific manner. +// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 Reserved; +} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER; + +#pragma pack() + +#endif // _MCFG_TABLE_H diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Pch/98Link.asl b/ChvRefCodePkg/AcpiTablesPCAT/Pch/98Link.asl new file mode 100644 index 0000000000..fe177e6cf6 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Pch/98Link.asl @@ -0,0 +1,615 @@ +/** @file + ACPI DSDT table + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// Use this information when determining the Possible IRQs that can be +// used in a given system. +// +// The following IRQs are always in use by legacy devices: +// 0 = System Timer +// 2 = 8259 PIC +// 8 = RTC +// 9 = SCI Interrupt (It may be used, we choose not to) +// 13 = Co-processor Error +// +// The following may be in use by legacy devices: +// 1 = If using PS/2 Keyboard +// 3 = If COMx Port Enabled and IRQ = 3 +// 4 = If COMx Port Enabled and IRQ = 4 +// 5 = If LPT Port Enabled and IRQ = 5 +// 6 = If FDC Enabled +// 7 = If LPT Port Enabled and IRQ = 7 +// 12 = If using PS/2 Mouse +// 14 = Primary IDE (If populated and in Compatibility Mode) +// 15 = Secondary IDE (If populated and in Compatibility Mode) +// +// The following will never be in use by legacy devices: +// 10 = Assign to PARC, PCRC, PERC, PGRC +// 11 = Assign to PBRC, PDRC, PFRC, PHRC + +Device(LNKA) // PARC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) // PCI Interrupt Link Device + + Name(_UID,1) // Unique to other Link Devices + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PARC,0x80,PARC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSA) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLA,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLA,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PARC,0x0F),IRQ0) + + Return(RTLA) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PARC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PARC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKB) // PBRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,2) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PBRC,0x80,PBRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSB) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLB,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLB,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PBRC,0x0F),IRQ0) + + Return(RTLB) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PBRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PBRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKC) // PCRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,3) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PCRC,0x80,PCRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSC) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLC,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLC,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PCRC,0x0F),IRQ0) + + Return(RTLC) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PCRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PCRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKD) // PDRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,4) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PDRC,0x80,PDRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSD) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLD,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLD,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PDRC,0x0F),IRQ0) + + Return(RTLD) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PDRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PDRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKE) // PERC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,5) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PERC,0x80,PERC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSE) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLE,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLE,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PERC,0x0F),IRQ0) + + Return(RTLE) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PERC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PERC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKF) // PFRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,6) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PFRC,0x80,PFRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSF) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLF,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLF,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PFRC,0x0F),IRQ0) + + Return(RTLF) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PFRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PFRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKG) // PGRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,7) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PGRC,0x80,PGRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSG) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLG,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLG,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PGRC,0x0F),IRQ0) + + Return(RTLG) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PGRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PGRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKH) // PHRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,8) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PHRC,0x80,PHRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSH) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLH,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLH,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PHRC,0x0F),IRQ0) + + Return(RTLH) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PHRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PHRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Pch/LpcB.asl b/ChvRefCodePkg/AcpiTablesPCAT/Pch/LpcB.asl new file mode 100644 index 0000000000..7f807be51e --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Pch/LpcB.asl @@ -0,0 +1,144 @@ +/** @file + ACPI DSDT table + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// LPC Bridge - Device 31, Function 0 +// Define the needed LPC registers used by ASL. + +scope(\_SB) { + OperationRegion(ILBR, SystemMemory, \IBAS, 0x8C) + Field(ILBR, AnyAcc, NoLock, Preserve) { + Offset(0x08), // 0x08 + PARC, 8, + PBRC, 8, + PCRC, 8, + PDRC, 8, + PERC, 8, + PFRC, 8, + PGRC, 8, + PHRC, 8, + Offset(0x14), + ULKM, 8, // R_SB_ILB_ULKMC Trap enable + Offset(0x88), // 0x88 + , 4, + UI4E, 1 + } + + Include ("Pch/98Link.asl") +} + + OperationRegion(LPC0, PCI_Config, 0x00, 0xC0) + Field(LPC0, AnyAcc, NoLock, Preserve) + { + Offset(0x08), // 0x08 + SRID, 8, // Revision ID + Offset(0x080), // 0x80 + C1EN, 1, // COM1 Enable + , 31 + } + + Include ("Platform/Ec.asl") + Include ("Pch/LpcDev.asl") + + // Define the KBC_COMMAND_REG-64, KBC_DATA_REG-60 Registers as an ACPI Operating + // Region. These registers will be used to skip kbd mouse + // resource settings if not present. + + OperationRegion(PKBS, SystemIO, 0x60, 0x05) + Field(PKBS, ByteAcc, Lock, Preserve) + { + PKBD, 8, + , 8, + , 8, + , 8, + PKBC, 8 + } + +Device(PS2K) // PS2 Keyboard +{ + Name(_HID,"MSFT0001") + Name(_CID,EISAID("PNP0303")) + + Method(_STA) + { + + + //If Port 60/64 trap is enabled, always return device present + If (And(ULKM, 0x0F)) { + Return(0x000F) + } + + // Only report resources to the OS if the Keyboard is present + + If(And(LEqual(PKBD,0xFF), LEqual(PKBC, 0xFF))) + { + Return(0x0000) + } + + Return(0x000F) + } + + Name(_CRS,ResourceTemplate() + { + IO(Decode16,0x60,0x60,0x01,0x01) + IO(Decode16,0x64,0x64,0x01,0x01) + IRQ(Edge,ActiveHigh,Exclusive){0x01} + }) + + Name(_PRS, ResourceTemplate() { + StartDependentFn(0, 0) { + FixedIO(0x60,0x01) + FixedIO(0x64,0x01) + IRQNoFlags(){1} + } + EndDependentFn() + }) + +} + +Device(PS2M) // PS/2 Mouse +{ + Name(_HID,"MSFT0003") + Name(_CID,EISAID("PNP0F13")) + + Method(_STA) + { + + //If Port 60/64 trap is enabled, always return device present + If (And(ULKM, 0x0F)) { + Return(0x000F) + } + + // Only report resources to the OS if the Mouse is present + + If(And(LEqual(PKBD,0xFF), LEqual(PKBC, 0xFF))) + { + Return(0x0000) + } + + Return(0x000F) + } + + Name(_CRS,ResourceTemplate() + { + IRQ(Edge,ActiveHigh,Exclusive){0x0C} + }) + + Name(_PRS, ResourceTemplate() { + StartDependentFn(0, 0) { + IRQNoFlags(){12} + } + EndDependentFn() + }) +} diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Pch/LpcDev.asl b/ChvRefCodePkg/AcpiTablesPCAT/Pch/LpcDev.asl new file mode 100644 index 0000000000..de06258033 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Pch/LpcDev.asl @@ -0,0 +1,173 @@ +/** @file + ACPI DSDT table + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Device(FWHD) // Firmware Hub Device +{ + Name(_HID,EISAID("INT0800")) + + Name(_CRS,ResourceTemplate() + { + Memory32Fixed(ReadOnly,0xFF000000,0x1000000) + }) +} + +scope (\_SB) { + + Device(RTC) // RTC + { + Name(_HID,EISAID("PNP0B00")) + + Name(_CRS,ResourceTemplate() + { + IO(Decode16,0x70,0x70,0x01,0x08) + }) + } + +/* Device(HPET) // High Performance Event Timer + { + Name (_HID, EisaId ("PNP0103")) + Name (_UID, 0x00) + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Method (_CRS, 0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) + { + 0x00000008, //0xB HPET-2 + } + }) + Return (RBUF) + } + } // HPET */ +} + +Device(IPIC) // 8259 PIC +{ + Name(_HID,EISAID("PNP0000")) + + Name(_CRS,ResourceTemplate() + { + IO(Decode16,0x20,0x20,0x01,0x02) + IO(Decode16,0x24,0x24,0x01,0x02) + IO(Decode16,0x28,0x28,0x01,0x02) + IO(Decode16,0x2C,0x2C,0x01,0x02) + IO(Decode16,0x30,0x30,0x01,0x02) + IO(Decode16,0x34,0x34,0x01,0x02) + IO(Decode16,0x38,0x38,0x01,0x02) + IO(Decode16,0x3C,0x3C,0x01,0x02) + IO(Decode16,0xA0,0xA0,0x01,0x02) + IO(Decode16,0xA4,0xA4,0x01,0x02) + IO(Decode16,0xA8,0xA8,0x01,0x02) + IO(Decode16,0xAC,0xAC,0x01,0x02) + IO(Decode16,0xB0,0xB0,0x01,0x02) + IO(Decode16,0xB4,0xB4,0x01,0x02) + IO(Decode16,0xB8,0xB8,0x01,0x02) + IO(Decode16,0xBC,0xBC,0x01,0x02) + IO(Decode16,0x4D0,0x4D0,0x01,0x02) + IRQNoFlags() {2} + }) +} + +Device(LDRC) // LPC Device Resource Consumption +{ + Name(_HID,EISAID("PNP0C02")) + + Name(_UID,2) + + Name(_CRS,ResourceTemplate() + { + IO(Decode16,0x4E,0x4E,0x1,0x02) // LPC Slot Access. + IO(Decode16,0x61,0x61,0x1,0x1) // NMI Status. + IO(Decode16,0x63,0x63,0x1,0x1) // Processor I/F. + IO(Decode16,0x65,0x65,0x1,0x1) // Processor I/F. + IO(Decode16,0x67,0x67,0x1,0x1) // Processor I/F. + IO(Decode16,0x70,0x70,0x1,0x1) // NMI Enable. + IO(Decode16,0x80,0x80,0x1,0x10) // Postcode. + IO(Decode16,0x92,0x92,0x1,0x1) // Processor I/F. + IO(Decode16,0xB2,0xB2,0x01,0x02) // Software SMI. + IO(Decode16,0x680,0x680,0x1,0x20) // 32 Byte I/O. + IO(Decode16,0x400,0x400,0x1,0x80) // ACPI Base. + IO(Decode16,0x500,0x500,0x1,0xFF) // GPIO Base. + }) +} + +Device(TIMR) // 8254 Timer +{ + Name(_HID,EISAID("PNP0100")) + + Name(_CRS,ResourceTemplate() + { + IO(Decode16,0x40,0x40,0x01,0x04) + IO(Decode16,0x50,0x50,0x10,0x04) + IRQNoFlags() {0} + }) +} + +Device(IURT) // Internal UART +{ + Name(_HID, EISAID("PNP0501")) + + Name(_UID,1) + + // Status Method for internal UART. + + Method(_STA,0,Serialized) + { + // Only report resources to the OS if internal UART is + // not set to Disabled in BIOS Setup. + + If(LEqual(USEL,0)) + { + Store(1,UI4E) // Enable IRQ4 for internal UART. + Store(1,C1EN) // Enable internal UART. + Return(0x000F) + } + + Return(0x0000) + } + + // Disable Method for internal UART. + + Method(_DIS,0,Serialized) + { + Store(0,UI4E) + Store(0,C1EN) + } + + // Current Resource Setting Method for internal UART. + + Method(_CRS,0,Serialized) + { + // Create the Buffer that stores the Resources to + // be returned. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x03F8,0x03F8,0x01,0x08) + IRQNoFlags(){4} + }) + + Return(BUF0) + } +} diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Pch/Pch.asl b/ChvRefCodePkg/AcpiTablesPCAT/Pch/Pch.asl new file mode 100644 index 0000000000..b00090c01e --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Pch/Pch.asl @@ -0,0 +1,654 @@ +/** @file + ACPI DSDT table + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(\) +{ + // + // Define ABASE I/O as an ACPI operating region. The base address + // can be found in Device 31, Registers 40-43h. + // + OperationRegion(PMIO, SystemIo, \PMBS, 0x46) + Field(PMIO, ByteAcc, NoLock, Preserve) { + , 8, + PWBS, 1, // Power Button Status + Offset(0x20), + , 13, + PMEB, 1, // PME_B0_STS + Offset(0x42), // General Purpose Control + , 1, + GPEC, 1 + } + Field(PMIO, ByteAcc, NoLock, WriteAsZeros) { + Offset(0x20), // GPE0 Status + , 4, + PSCI, 1, // PUNIT SCI Status + SCIS, 1, // GUNIT SCI Status + , 17, + GP23, 1 + } + + // + // Define a Memory Region that will allow access to the PMC + // Register Block. Note that in the Intel Reference Solution, the PMC + // will get fixed up dynamically during POST. + // + OperationRegion(PMCR, SystemMemory, \PMCB, 0x100) // PMC Space + Field(PMCR,DWordAcc,Lock,Preserve) { + Offset(0x34), // Function Disable Register + L10D, 1, // (00) LPIO1 DMA Disable + L11D, 1, // (01) LPIO1 PWM #1 Disable + L12D, 1, // (02) LPIO1 PWM #2 Disable + L13D, 1, // (03) LPIO1 HS-UART #1 Disable + L14D, 1, // (04) LPIO1 HS-UART #2 Disable + L15D, 1, // (05) LPIO1 SPI Disable + L16D, 1, // (06) LPIO1 SPI2 Disable + L17D, 1, // (07) LPIO1 SPI3 Disable + SD1D, 1, // (08) SCC SDIO #1 Disable + SD2D, 1, // (09) SCC SDIO #2 Disable + SD3D, 1, // (10) SCC SDIO #3 Disable + , 1, // (11) + , 1, // (12) Azalia Disable + LPED, 1, // (13) LPE Disable + OTGD, 1, // (14) USB OTG Disable + , 1, // (15) + , 1, // (16) + , 1, // (17) SATA Disable + , 1, // (18) USH Disable + , 1, // (19) SEC Disable + RP1D, 1, // (20) Root Port 0 Disable + RP2D, 1, // (21) Root Port 1 Disable + RP3D, 1, // (22) Root Port 2 Disable + RP4D, 1, // (23) Root Port 3 Disable + L20D, 1, // (24) LPIO2 DMA Disable + L21D, 1, // (25) LPIO2 I2C #1 Disable + L22D, 1, // (26) LPIO2 I2C #2 Disable + L23D, 1, // (27) LPIO2 I2C #3 Disable + L24D, 1, // (28) LPIO2 I2C #4 Disable + L25D, 1, // (29) LPIO2 I2C #5 Disable + L26D, 1, // (30) LPIO2 I2C #6 Disable + L27D, 1, // (31) LPIO2 I2C #7 Disable + Offset(0x38), // Function Disable Register 2 + , 1, // (00) SMBus Disable + , 1, // (01) + , 1, // (02) + , 1, // (03) + ISHD, 1, // (04) ISH Disable + , 27, + Offset(0x60), // PLT_CLK_CTL_0 + CKC0, 2, + CKF0, 1, + , 29, + Offset(0x64), // PLT_CLK_CTL_1 + CKC1, 2, + CKF1, 1, + , 29, + Offset(0x68), // PLT_CLK_CTL_2 + CKC2, 2, + CKF2, 1, + , 29, + Offset(0x6C), // PLT_CLK_CTL_3 + CKC3, 2, + CKF3, 1, + , 29, + Offset(0x70), // PLT_CLK_CTL_4 + CKC4, 2, + CKF4, 1, + , 29, + Offset(0x74), // PLT_CLK_CTL_5 + CKC5, 2, + CKF5, 1, + , 29, + Offset(0xA0), // D3 Status 0 + PMCD, 32, + Offset(0xC0), // xHCI PME Status + , 14, + XPME, 1, + Offset(0xEC), // BIOS_COMM Register + PMCC, 32 + } + + // + // Support S0, S3, S4, and S5. The proper bits to be set when + // entering a given sleep state are found in the Power Management + // 1 Control ( PM1_CNT ) register, located at PMC Base + 0xA0 + // + OperationRegion(PPSC, SystemMemory, Add(\PMCB, 0xA0), 0x08) // PMC Base + 0xA0 + Field(PPSC,DWordAcc,Lock,Preserve) { + DM1P, 1, //BIT0 + PW1P, 1, //BIT1 + PW2P, 1, //2 + UR1P, 1, //3 + UR2P, 1, //4 + SP1P, 1, //5 + SP2P, 1, //6 + SP3P, 1, //7 + EMMP, 1, //8 + SDI1, 1, //9 + SDI2, 1, //10 + , 2, //11-mipi, 12-HDA + LPEP, 1, //13 + , 1, //14 -USB SIP Bridge + , 1, //15 + , 1, //16 + SATP, 1, //17, SATA Power State Current + USBP, 1, //18 + SECP, 1, //19, SEC Power State Current + PRP1, 1, //20 + PRP2, 1, //21 + PRP3, 1, //22 + PRP4, 1, //23, PCIE Rootports 1-4 + DM2P, 1, //24, LPIO2 DMA + IC1P, 1, //25 + IC2P, 1, //26 + IC3P, 1, //27 + IC4P, 1, //28 + IC5P, 1, //29 + IC6P, 1, //30 + IC7P, 1, //31 + Offset(0x4), //reg_D3_STS_1_type + , 2, //0-SMBus + ISHP, 1, //2 + , 29 + } +} //end Scope(\) + +scope (\_SB.PCI0) { + + + // + // Serial ATA Host Controller - Device 19, Function 0 + // + + Device(SATA) { + Name(_ADR,0x00130000) + // + // SATA Methods pulled in via SSDT. + // + + OperationRegion(SATR, PCI_Config, 0x74,0x4) + Field(SATR,WordAcc,NoLock,Preserve) { + Offset(0x00), // 0x74, PMCR + , 8, + PMEE, 1, //PME_EN + , 6, + PMES, 1 //PME_STS + } + Method(_DSW, 3) + { + } // End _DSW + } + + + include("Pch/PchXhci.asl") + + include ("Pch/PchScc.asl") + include ("Pch/PchLpss.asl") + + // + // High Definition Audio Controller - Device 27, Function 0 + // + Device(HDEF) { + Name(_ADR, 0x001B0000) + include("Pch/PchAudio.asl") + Name(_PRW, Package() {0x0D, 4}) + + Method(_DSW, 3) + { + } // End _DSW + } // end "High Definition Audio Controller" + + + // + // PCIE Root Port #1 + // + Device(RP01) { + Name(_ADR, 0x001C0000) + include("Pch/PchPcie.asl") + Name(_PRW, Package() {0x09, 4}) + + Method(_PRT,0) { + If(PICM) { Return(AR04) }// APIC mode + Return (PR04) // PIC Mode + } // end _PRT + } // end "PCIE Root Port #1" + + // + // PCIE Root Port #2 + // + Device(RP02) { + Name(_ADR, 0x001C0001) + include("Pch/PchPcie.asl") + Name(_PRW, Package() {0x09, 4}) + + Method(_PRT,0) { + If(PICM) { Return(AR05) }// APIC mode + Return (PR05) // PIC Mode + } // end _PRT + + } // end "PCIE Root Port #2" + + // + // PCIE Root Port #3 + // + Device(RP03) { + Name(_ADR, 0x001C0002) + include("Pch/PchPcie.asl") + Name(_PRW, Package() {0x09, 4}) + + Method(_PRT,0) { + If(PICM) { Return(AR06) }// APIC mode + Return (PR06) // PIC Mode + } // end _PRT + + } // end "PCIE Root Port #3" + + // + // PCIE Root Port #4 + // + Device(RP04) { + Name(_ADR, 0x001C0003) + include("Pch/PchPcie.asl") + Name(_PRW, Package() {0x09, 4}) + + Method(_PRT,0) { + If(PICM) { Return(AR07) }// APIC mode + Return (PR07) // PIC Mode + } // end _PRT + + } // end "PCIE Root Port #4" + + // + // SMBus Controller - Device 31, Function 3 + // + Device(SBUS) { + Name(_ADR,0x001F0003) + Include("Pch/PchSmb.asl") + } + + // + // Low Power Engine Audio - Device 21, Function 0 + // + Device(LPEA) { + Name (_HID, "808622A8") + Name (_CID, "808622A8") + Name (_DDN, "Intel(R) Low Power Audio Controller - 808622A8") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00200000, BAR0) // MMIO 1 - LPE MMIO + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR1) // MMIO 2 - Shadowed PCI Config Space + Memory32Fixed (ReadWrite, 0x00000000, 0x00200000, BAR2) // MMIO 3 - LPE Reserved Memory + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {24} // LPE IRQ + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {25} // LPE IRQ + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {26} // LPE IRQ + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {27} // LPE IRQ + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {28} // LPE IRQ + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {29} // LPE IRQ + GpioInt(Edge, ActiveBoth, ExclusiveAndWake, PullNone, 0,"\\_SB.GPO3") {77} // Audio jack interrupt + }) + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + Store(LPE0, B0BA) + CreateDwordField(^RBUF, ^BAR1._BAS, B1BA) + Store(LPE1, B1BA) + CreateDwordField(^RBUF, ^BAR2._BAS, B2BA) + Store(LPE2, B2BA) + Return (RBUF) + } + Method (_STA, 0x0, NotSerialized) + { + If (LAnd(LNotEqual(LPE0, 0), LEqual(LPED, 0))) + { + Return (0xF) // Enabled 1111 + } + Return (0x0) // Disabled 0000 + } + Method (_DIS, 0x0, NotSerialized) + { + // Add a dummy disable function + } + Method (_PS3, 0, NotSerialized) + { + OR(PSAT, 0x00000003, PSAT) + OR(PSAT, 0x00000000, PSAT) + } + + Method (_PS0, 0, NotSerialized) + { + And(PSAT, 0xFFFFFFFC, PSAT) + OR(PSAT, 0x00000000, PSAT) + } + OperationRegion (KEYS, SystemMemory, LPE1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + // + // For Andriod +++<< + // + Device (ADMA) + { + Name (_HID, "ADMA22A8") // _HID: Hardware ID + Name (_CID, "ADMA22A8") // _CID: Compatible ID + Name (_DDN, "Intel(R) Audio DMA0 - DMA0F28") // _DDN: DOS Device Name + Name (_UID, One) // _UID: Unique ID + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00200000, BAR0) // MMIO 1 - LPE MMIO + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, ,, ) {24} + }) + + Method (_CRS, 0x0, NotSerialized) { + CreateDwordField(^RBUF, ^BAR0._BAS, B3BA) + Store(LPE0, B3BA) + Return (RBUF) + } + + Method(_STA, 0x0, NotSerialized) { + If (Lor(LEqual(OSID,2), LEqual(OSID,3))) { + Return(0xF) + } + Return(0x0) + } + } // End of Device (ADMA) + } // End "Low Power Engine Audio" + + Device (HAD0) + { + Name (_HID, "HAD022A8") + Name (_CID, "HAD022A8") + Name (_DDN, "Intel(R) HDMI Audio Driver - HAD") + Name (_UID, One) + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, // HDMI Audio register offset + 0x00065800, // Address Base + 0x00000140, // Address Length + ) + }) + Return (RBUF) + } + Method(_STA, 0x0, NotSerialized) { + If (LEqual(ADED,1)){ + If (Lor(LEqual(OSID,2), LEqual(OSID,3))) { + Return(0xF) + } + } + Return(0x0) + } + } ///HAD0 end + + // + // USB3 OTG - Device 22, Function 0 + // + Device(UOTG) { + Name (_HID, "808622B7") + Name (_CID, "808622B7") + Name (_DDN, "Intel(R) USB On-The-Go Controller - 808622B7") + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00200000, BAR0) // MMIO 1 - OTG MMIO + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR1) // MMIO 2 - Shadowed PCI Config Space + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {30} // OTG IRQ + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {31} // OTG IRQ + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + Store(OTG0, B0BA) + CreateDwordField(^RBUF, ^BAR1._BAS, B1BA) + Store(OTG1, B1BA) + If (LNotEqual(OTG0, 0)) + { + Return (RBUF) + } + } + + Method (_STA, 0x0, NotSerialized) + { + If (LOr(LEqual(OTGD, 1), LOr(LEqual(OTGM, 1), LEqual(OTG0, 0)))) + { + Return (0x0) // Disabled 0000 + } + Return (0xF) // Enabled 1111 + } + Method (_DIS, 0x0, NotSerialized) + { + // Add a dummy disable function + } + Method (_PS3, 0, NotSerialized) + { + OR(PSAT, 0x00000003, PSAT) + OR(PSAT, 0x00000000, PSAT) + } + Method (_PS0, 0, NotSerialized) + { + And(PSAT, 0xFFFFFFFC, PSAT) + OR(PSAT, 0x00000000, PSAT) + } + OperationRegion (KEYS, SystemMemory, OTG1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + } // End "USB3 OTG" + + // + // Shadowed PCI Config Space Resource Consumption + // + Device(SPRC) { + Name(_HID,EISAID("PNP0C02")) + Name(_UID,3) + + Name(RBUF,ResourceTemplate() + { + // + // BIOS specific change. + // Provide shadowed PCI config base addresses + // for all the devices that support ACPI mode. + // BIOS to update AddressBase field dynamically after PCI enumeration. + // + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, SCB1) // SCC eMMC BAR1 + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, SCB2) // SCC SDIO BAR1 + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, SCB3) // SCC SDCard BAR1 + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, L10B) // LPSS 1 DMA BAR1 + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, L11B) // LPSS 1 PWM #1 BAR1 + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, L12B) // LPSS 1 PWM #2 BAR1 + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, L13B) // LPSS 1 HSUART #1 BAR1 + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, L14B) // LPSS 1 HSUART #2 BAR1 + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, L15B) // LPSS 1 SPI #1 BAR1 + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, L16B) // LPSS 1 SPI #2 BAR1 + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, L17B) // LPSS 1 SPI #3 BAR1 + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, L20B) // LPSS 2 DMA BAR1 + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, L21B) // LPSS 2 I2C #1 BAR1 + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, L22B) // LPSS 2 I2C #2 BAR1 + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, L23B) // LPSS 2 I2C #3 BAR1 + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, L24B) // LPSS 2 I2C #4 BAR1 + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, L25B) // LPSS 2 I2C #5 BAR1 + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, L26B) // LPSS 2 I2C #6 BAR1 + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, L27B) // LPSS 2 I2C #7 BAR1 + }) + + Method (_CRS, 0x0, NotSerialized) + { + // + // Populate BAR Lengths if the BAR addresses are non-zero + // + CreateDWordField(^RBUF, ^SCB1._BAS, BR01) + Store(eM1A, BR01) + If(LAnd(LNotEqual(BR01, 0), LNotEqual(BR01, 0xFFFFF000))) + { + CreateDWordField(^RBUF, ^SCB1._LEN, LN01) + Store(eM1L, LN01) + } + + CreateDWordField(^RBUF, ^SCB2._BAS, BR02) + Store(SI1A, BR02) + If(LAnd(LNotEqual(BR02, 0), LNotEqual(BR02, 0xFFFFF000))) + { + CreateDWordField(^RBUF, ^SCB2._LEN, LN02) + Store(SI1L, LN02) + } + + CreateDWordField(^RBUF, ^SCB3._BAS, BR03) + Store(SD1A, BR03) + If(LAnd(LNotEqual(BR03, 0), LNotEqual(BR03, 0xFFFFF000))) + { + CreateDWordField(^RBUF, ^SCB3._LEN, LN03) + Store(SD1L, LN03) + } + + CreateDWordField(^RBUF, ^L10B._BAS, BR04) + Store(D11A, BR04) + If(LAnd(LNotEqual(BR04, 0), LNotEqual(BR04, 0xFFFFF000))) + { + CreateDWordField(^RBUF, ^L10B._LEN, LN04) + Store(D11L, LN04) + } + + CreateDWordField(^RBUF, ^L11B._BAS, BR05) + Store(P11A, BR05) + If(LAnd(LNotEqual(BR05, 0), LNotEqual(BR05, 0xFFFFF000))) + { + CreateDWordField(^RBUF, ^L11B._LEN, LN05) + Store(P11L, LN05) + } + + CreateDWordField(^RBUF, ^L12B._BAS, BR06) + Store(P21A, BR06) + If(LAnd(LNotEqual(BR06, 0), LNotEqual(BR06, 0xFFFFF000))) + { + CreateDWordField(^RBUF, ^L12B._LEN, LN06) + Store(P21L, LN06) + } + + CreateDWordField(^RBUF, ^L13B._BAS, BR07) + Store(U11A, BR07) + If(LAnd(LNotEqual(BR07, 0), LNotEqual(BR07, 0xFFFFF000))) + { + CreateDWordField(^RBUF, ^L13B._LEN, LN07) + Store(U11L, LN07) + } + + CreateDWordField(^RBUF, ^L14B._BAS, BR08) + Store(U21A, BR08) + If(LAnd(LNotEqual(BR08, 0), LNotEqual(BR08, 0xFFFFF000))) + { + CreateDWordField(^RBUF, ^L14B._LEN, LN08) + Store(U21L, LN08) + } + + CreateDWordField(^RBUF, ^L15B._BAS, BR09) + Store(SP1A, BR09) + If(Land(LNotEqual(BR09, 0), LNotEqual(BR09, 0xFFFFF000))) + { + CreateDWordField(^RBUF, ^L15B._LEN, LN09) + Store(SP1L, LN09) + } + + CreateDWordField(^RBUF, ^L16B._BAS, BR10) + Store(S21A, BR10) + If(LAnd(LNotEqual(BR10, 0), LNotEqual(BR10, 0xFFFFF000))) + { + CreateDWordField(^RBUF, ^L16B._LEN, LN10) + Store(S21L, LN10) + } + + CreateDWordField(^RBUF, ^L17B._BAS, BR11) + Store(S31A, BR11) + If(LAnd(LNotEqual(BR11, 0), LNotEqual(BR11, 0xFFFFF000))) + { + CreateDWordField(^RBUF, ^L17B._LEN, LN11) + Store(S31L, LN11) + } + + CreateDWordField(^RBUF, ^L20B._BAS, BR12) + Store(D21A, BR12) + If(LAnd(LNotEqual(BR12, 0), LNotEqual(BR12, 0xFFFFF000))) + { + CreateDWordField(^RBUF, ^L20B._LEN, LN12) + Store(D21L, LN12) + } + + CreateDWordField(^RBUF, ^L21B._BAS, BR13) + Store(I11A, BR13) + If(LAnd(LNotEqual(BR13, 0), LNotEqual(BR13, 0xFFFFF000))) + { + CreateDWordField(^RBUF, ^L21B._LEN, LN13) + Store(I11L, LN13) + } + + CreateDWordField(^RBUF, ^L22B._BAS, BR14) + Store(I21A, BR14) + If(LAnd(LNotEqual(BR14, 0), LNotEqual(BR14, 0xFFFFF000))) + { + CreateDWordField(^RBUF, ^L22B._LEN, LN14) + Store(I21L, LN14) + } + + CreateDWordField(^RBUF, ^L23B._BAS, BR15) + Store(I31A, BR15) + If(LAnd(LNotEqual(BR15, 0), LNotEqual(BR15, 0xFFFFF000))) + { + CreateDWordField(^RBUF, ^L23B._LEN, LN15) + Store(I31L, LN15) + } + + CreateDWordField(^RBUF, ^L24B._BAS, BR16) + Store(I41A, BR16) + If(LAnd(LNotEqual(BR16, 0), LNotEqual(BR16, 0xFFFFF000))) + { + CreateDWordField(^RBUF, ^L24B._LEN, LN16) + Store(I41L, LN16) + } + + CreateDWordField(^RBUF, ^L25B._BAS, BR17) + Store(I51A, BR17) + If(LAnd(LNotEqual(BR17, 0), LNotEqual(BR17, 0xFFFFF000))) + { + CreateDWordField(^RBUF, ^L25B._LEN, LN17) + Store(I51L, LN17) + } + + CreateDWordField(^RBUF, ^L26B._BAS, BR18) + Store(I61A, BR18) + If(LAnd(LNotEqual(BR18, 0), LNotEqual(BR18, 0xFFFFF000))) + { + CreateDWordField(^RBUF, ^L26B._LEN, LN18) + Store(I61L, LN18) + } + + CreateDWordField(^RBUF, ^L27B._BAS, BR19) + Store(I71A, BR19) + If(LAnd(LNotEqual(BR19, 0), LNotEqual(BR19, 0xFFFFF000))) + { + CreateDWordField(^RBUF, ^L27B._LEN, LN19) + Store(I71L, LN19) + } + + Return (RBUF) + } + } // Device(SPRC) + +} // End scope (\_SB.PCI0) diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Pch/PchAudio.asl b/ChvRefCodePkg/AcpiTablesPCAT/Pch/PchAudio.asl new file mode 100644 index 0000000000..f4a1184e7e --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Pch/PchAudio.asl @@ -0,0 +1,36 @@ +/** @file + ACPI DSDT table + + Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + // + // High Definition Audio - Device 27, Function 0 + // + OperationRegion(HDAR, PCI_Config, 0x4C,0x10) + Field(HDAR,WordAcc,NoLock,Preserve) { + Offset(0x00), // 0x4C, Dock Control Register + DCKA, 1, // Dock Attach + , 7, + Offset(0x01), // 04Dh, Dock Status Register + DCKM, 1, // Dock Mated + , 6, + DCKS, 1, // Docking Supported + Offset(0x08), // 0x54, Power Management Control and Status Register + , 8, + PMEE, 1, // PME_EN + , 6, + PMES, 1 // PME Status + } + + + diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Pch/PchLpss.asl b/ChvRefCodePkg/AcpiTablesPCAT/Pch/PchLpss.asl new file mode 100644 index 0000000000..9a757cacba --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Pch/PchLpss.asl @@ -0,0 +1,953 @@ +/** @file + ACPI DSDT table + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + // + // LPIO1 DMA#1 (Synopsis GP DMA) - Windows + // + Device (GDM1) { + Name (_HID, "INTL9C60") + Name (_DDN, "Intel(R) DMA Controller #1 - INTL9C60") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00004000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {42} // DMA #1 IRQ + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(D10A, B0BA) + Store(D10L, B0LN) + Return (RBUF) + } + + Method (_STA, 0x0, NotSerialized) { + If (LOr(LEqual(D10A, 0), LEqual(L10D, 1))) + { + Return (0x0) + } + Return (0xF) + } + + Method (_PS3, 0, NotSerialized) + { + Or (PSAT, 3, PSAT) + Or (PSAT, 0, PSAT) + } + Method (_PS0, 0, NotSerialized) + { + And (PSAT, 0xFFFFFFFC, PSAT) + Or (PSAT, 0, PSAT) + } + OperationRegion (KEYS, SystemMemory, Or (D10A, 0x84), 4) + Field (KEYS, DWordAcc, NoLock, Preserve) + { + PSAT, 2 // Device Power State, 00 = D0, 01 = D3 Hot + } + } + + + // + // LPIO1 DMA#2 (Synopsis GP DMA) - Windows + // + Device (GDM3) { + Name (_HID, "INTL9C60") + Name (_DDN, "Intel(R) DMA Controller #2 - INTL9C60") + Name (_UID, 2) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00004000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {43} // DMA #2 IRQ + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(D20A, B0BA) + Store(D20L, B0LN) + Return (RBUF) + } + + Method (_STA, 0x0, NotSerialized) { + If (LOr(LEqual(D20A, 0), LEqual(L20D, 1))) + { + Return (0x0) + } + Return (0xF) + } + + Method (_PS3, 0, NotSerialized) + { + Or (PSAT, 3, PSAT) + Or (PSAT, 0, PSAT) + } + Method (_PS0, 0, NotSerialized) + { + And (PSAT, 0xFFFFFFFC, PSAT) + Or (PSAT, 0, PSAT) + } + OperationRegion (KEYS, SystemMemory, Or (D20A, 0x84), 4) + Field (KEYS, DWordAcc, NoLock, Preserve) + { + PSAT, 2 // Device Power State, 00 = D0, 01 = D3 Hot + } + } + + + // + // LPIO1 PWM #1 + // + Device(PWM1) { + Name (_HID, "80862288") + Name (_CID, "80862288") + Name (_DDN, "Intel(R) PWM Controller #1 - 80862288") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + }) + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(P10A, B0BA) + Store(P10L, B0LN) + Return (RBUF) + } + Method (_STA, 0x0, NotSerialized) + { + If (LOr(LEqual(P10A, 0), LEqual(L11D, 1))) + { + Return (0x0) + } + Return (0xF) + } + Method (_PS3, 0, NotSerialized) + { + OR(PSAT, 0x00000003, PSAT) + OR(PSAT, 0x00000000, PSAT) + } + Method (_PS0, 0, NotSerialized) + { + And(PSAT, 0xFFFFFFFC, PSAT) + OR(PSAT, 0x00000000, PSAT) + } + OperationRegion (KEYS, SystemMemory, P11A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + } + + // + // LPIO1 PWM #2 + // + Device(PWM2) { + Name (_HID, "80862288") + Name (_CID, "80862288") + Name (_DDN, "Intel(R) PWM Controller #2 - 80862289") + Name (_UID, 2) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + }) + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(P20A, B0BA) + Store(P20L, B0LN) + Return (RBUF) + } + Method (_STA, 0x0, NotSerialized) + { + If (LOr(LEqual(P20A, 0), LEqual(L12D, 1))) + { + Return (0x0) + } + Return (0xF) + } + Method (_PS3, 0, NotSerialized) + { + OR(PSAT, 0x00000003, PSAT) + OR(PSAT, 0x00000000, PSAT) + } + Method (_PS0, 0, NotSerialized) + { + And(PSAT, 0xFFFFFFFC, PSAT) + OR(PSAT, 0x00000000, PSAT) + } + OperationRegion (KEYS, SystemMemory, P21A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + } + + // + // LPIO1 HS-UART #1 + // + Device(URT1) { + Name (_HID, "8086228A") + Name (_CID, "8086228A") + Name (_DDN, "Intel(R) HS-UART Controller #1 - 8086228A") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {39} // HS-UART #1 IRQ + + FixedDMA(0x2, 0x2, Width32Bit, ) + FixedDMA(0x3, 0x3, Width32Bit, ) + }) + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(U10A, B0BA) + Store(U10L, B0LN) + Return (RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + If (LOr(LEqual(U10A, 0), LEqual(L13D, 1))) + { + Return (0x0) + } + Return (0xF) + } + Method (_PS3, 0, NotSerialized) + { + OR(PSAT, 0x00000003, PSAT) + OR(PSAT, 0x00000000, PSAT) + } + Method (_PS0, 0, NotSerialized) + { + And(PSAT, 0xFFFFFFFC, PSAT) + OR(PSAT, 0x00000000, PSAT) + } + OperationRegion (KEYS, SystemMemory, U11A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + + } // Device (URT1) + + // + // LPIO1 HS-UART #2 + // + Device(URT2) { + Name (_HID, "8086228A") + Name (_CID, "8086228A") + Name (_DDN, "Intel(R) HS-UART Controller #2 - 8086228C") + Name (_UID, 2) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {40} // HS-UART #2 IRQ + + FixedDMA(0x4, 0x4, Width32Bit, ) + FixedDMA(0x5, 0x5, Width32Bit, ) + }) + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(U20A, B0BA) + Store(U20L, B0LN) + Return (RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + If (LOr(LEqual(U20A, 0), LEqual(L14D, 1))) + { + Return (0x0) + } + Return (0xF) + } + + Method (_PS3, 0, NotSerialized) + { + OR(PSAT, 0x00000003, PSAT) + OR(PSAT, 0x00000000, PSAT) + } + Method (_PS0, 0, NotSerialized) + { + And(PSAT, 0xFFFFFFFC, PSAT) + OR(PSAT, 0x00000000, PSAT) + } + OperationRegion (KEYS, SystemMemory, U21A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + + }// Device (URT2) + + // + // LPIO1 SPI + // + Device(SPI1) { + Name (_HID, "8086228E") + Name (_CID, "8086228E") + Name (_DDN, "Intel(R) SPI Controller #1 - 8086228E") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {41} // SPI IRQ + + FixedDMA(0x0, 0x0, Width32Bit, ) + FixedDMA(0x1, 0x1, Width32Bit, ) + }) + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(SP0A, B0BA) + Store(SP0L, B0LN) + Return (RBUF) + } + Method (_STA, 0x0, NotSerialized) + { + If (LOr(LEqual(SP0A, 0), LEqual(L15D, 1))) + { + Return (0x0) + } + Return (0xF) + } + + Method (_PS3, 0, NotSerialized) + { + OR(PSAT, 0x00000003, PSAT) + OR(PSAT, 0x00000000, PSAT) + } + Method (_PS0, 0, NotSerialized) + { + And(PSAT, 0xFFFFFFFC, PSAT) + OR(PSAT, 0x00000000, PSAT) + } + OperationRegion (KEYS, SystemMemory, SP1A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + + } // Device (SPI1) + + // + // LPIO1 SPI #2 + // + Device(SPI2) { + Name (_HID, "8086228E") + Name (_CID, "8086228E") + Name (_DDN, "Intel(R) SPI Controller #2 - 80862290") + Name (_UID, 2) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {89} // SPI IRQ + + FixedDMA(0x6, 0x6, Width32Bit, ) + FixedDMA(0x7, 0x7, Width32Bit, ) + }) + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(S20A, B0BA) + Store(S20L, B0LN) + Return (RBUF) + } + Method (_STA, 0x0, NotSerialized) + { + If (LOr(LEqual(S20A, 0), LEqual(L16D, 1))) + { + Return (0x0) + } + Return (0xF) + } + + Method (_PS3, 0, NotSerialized) + { + OR(PSAT, 0x00000003, PSAT) + OR(PSAT, 0x00000000, PSAT) + } + Method (_PS0, 0, NotSerialized) + { + And(PSAT, 0xFFFFFFFC, PSAT) + OR(PSAT, 0x00000000, PSAT) + } + OperationRegion (KEYS, SystemMemory, S21A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + } // Device (SPI2) + + // + // LPIO1 SPI #3 + // + Device(SPI3) { + Name (_HID, "8086228E") + Name (_CID, "8086228E") + Name (_DDN, "Intel(R) SPI Controller #3 - 808622AC") + Name (_UID, 3) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {90} // SPI IRQ + + FixedDMA(0x8, 0x8, Width32Bit, ) + FixedDMA(0x9, 0x9, Width32Bit, ) + }) + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(S30A, B0BA) + Store(S30L, B0LN) + Return (RBUF) + } + Method (_STA, 0x0, NotSerialized) + { + If (LOr(LEqual(S30A, 0), LEqual(L16D, 1))) + { + Return (0x0) + } + Return (0xF) + } + + Method (_PS3, 0, NotSerialized) + { + OR(PSAT, 0x00000003, PSAT) + OR(PSAT, 0x00000000, PSAT) + } + Method (_PS0, 0, NotSerialized) + { + And(PSAT, 0xFFFFFFFC, PSAT) + OR(PSAT, 0x00000000, PSAT) + } + OperationRegion (KEYS, SystemMemory, S31A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + } // Device (SPI3) + + // Common _DSM method for HID I2C devices + // Arg0..3 - original arguments to _DSM method, as passed by OS + // Arg4 - HID descriptor address to be returned from Function1 + Method (CDSM, 5, Serialized) { + If (LEqual (Arg0, ToUUID ("3CDFF6F7-4267-4555-AD05-B30A3D8938DE"))) { + // Function 0 : Query Function + If (LEqual (Arg2, Zero)) { + // Revision 1 + If (LEqual (Arg1, One)) { + Return(Buffer(One) { 3 }) + } + } ElseIf (LEqual (Arg2, One)) { + // Function 1 : HID Function + Return (Arg4) // HID Descriptor Address (IHV Specific) + } + } + Return (Buffer (One) { 0x00 }) + } + + // + // LPIO2 I2C #1 + // + Device(I2C1) { + Name (_HID, "808622C1") + Name (_CID, "808622C1") + Name (_DDN, "Intel(R) I2C Controller #1 - 808622C1") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {32} // I2C #1 IRQ + + FixedDMA(0x10, 0x0, Width32Bit, ) + FixedDMA(0x11, 0x1, Width32Bit, ) + }) + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(I10A, B0BA) + Store(I10L, B0LN) + Return (RBUF) + } + Method (_STA, 0x0, NotSerialized) + { + If (LOr(LEqual(I10A, 0), LEqual(L21D, 1))) + { + Return (0x0) + } + Return (0xF) + } + + Method (_PS3, 0, NotSerialized) + { + If (LEqual(I0D3, 1)) { // If I2C 1 Runtime D3 Enabled + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + } + Method (_PS0, 0, NotSerialized) + { + If (LEqual(I0D3, 1)) { // If I2C 1 Runtime D3 Enabled + And(PSAT, 0xFFFFFFFC, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + } + OperationRegion (KEYS, SystemMemory, I11A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + + } // Device(I2C1) + + // + // LPIO2 I2C #2 + // + Device(I2C2) { + Name (_HID, "808622C1") + Name (_CID, "808622C1") + Name (_DDN, "Intel(R) I2C Controller #2 - 808622C2") + Name (_UID, 2) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {33} // I2C #2 IRQ + + FixedDMA(0x12, 0x2, Width32Bit, ) + FixedDMA(0x13, 0x3, Width32Bit, ) + }) + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(I20A, B0BA) + Store(I20L, B0LN) + Return (RBUF) + } + Method (_STA, 0x0, NotSerialized) + { + If (LOr(LEqual(I20A, 0), LEqual(L22D, 1))) + { + Return (0x0) + } + If (LEqual (BDID, CRRB)) { // If it's BSW CR board + Return (0x0) + } + Return (0xF) + } + + Method (_PS3, 0, NotSerialized) + { + If (LEqual(I1D3, 1)) { // If I2C 2 Runtime D3 Enabled + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + } + Method (_PS0, 0, NotSerialized) + { + If (LEqual(I1D3, 1)) { // If I2C 2 Runtime D3 Enabled + And(PSAT, 0xFFFFFFFC, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + } + OperationRegion (KEYS, SystemMemory, I21A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + + } // Device (I2C2) + + // + // LPIO2 I2C #3 + // + Device(I2C3) { + Name (_HID, "808622C1") + Name (_CID, "808622C1") + Name (_DDN, "Intel(R) I2C Controller #3 - 808622C3") + Name (_UID, 3) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {34} // I2C #3 IRQ + + FixedDMA(0x14, 0x4, Width32Bit, ) + FixedDMA(0x15, 0x5, Width32Bit, ) + }) + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(I30A, B0BA) + Store(I30L, B0LN) + Return (RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + If (LOr(LEqual(I30A, 0), LEqual(L23D, 1))) + { + Return (0x0) + } + Return (0xF) + } + + Method (_PS3, 0, NotSerialized) + { + If (LEqual(I2D3, 1)) { // If I2C 3 Runtime D3 Enabled + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + } + Method (_PS0, 0, NotSerialized) + { + If (LEqual(I2D3, 1)) { // If I2C 3 Runtime D3 Enabled + And(PSAT, 0xFFFFFFFC, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + } + OperationRegion (KEYS, SystemMemory, I31A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + + PowerResource (CLK0, 0x00, 0x0000) + { + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (CKC0) + } + + Method (_ON, 0, NotSerialized) // _ON_: Power On + { + Store (One, CKC0) + Sleep(5) + } + + Method (_OFF, 0, NotSerialized) // _OFF: Power Off + { + Store (0x02, CKC0) + } + } + + } // Device(I2C3) + + // + // LPIO2 I2C #4 + // + Device(I2C4) { + Name (_HID, "808622C1") + Name (_CID, "808622C1") + Name (_DDN, "Intel(R) I2C Controller #4 - 808622C4") + Name (_UID, 4) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {35} // I2C #4 IRQ + + FixedDMA(0x16, 0x6, Width32Bit, ) + FixedDMA(0x17, 0x7, Width32Bit, ) + }) + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(I40A, B0BA) + Store(I40L, B0LN) + Return (RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + If (LOr(LEqual(I40A, 0), LEqual(L24D, 1))) + { + Return (0x0) + } + Return (0xF) + } + + Method (_PS3, 0, NotSerialized) + { + If (LEqual(I3D3, 1)) { // If I2C 4 Runtime D3 Enabled + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + } + Method (_PS0, 0, NotSerialized) + { + If (LEqual(I3D3, 1)) { // If I2C 4 Runtime D3 Enabled + And(PSAT, 0xFFFFFFFC, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + } + OperationRegion (KEYS, SystemMemory, I41A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + + PowerResource (CLK0, 0x00, 0x0000) + { + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (CKC0) + } + + Method (_ON, 0, NotSerialized) // _ON_: Power On + { + Store (One, CKC0) + Sleep(5) + } + + Method (_OFF, 0, NotSerialized) // _OFF: Power Off + { + Store (0x02, CKC0) + } + } + PowerResource (CLK1, 0x00, 0x0000) + { + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (CKC1) + } + + Method (_ON, 0, NotSerialized) // _ON_: Power On + { + Store (One, CKC1) + Sleep(5) + } + + Method (_OFF, 0, NotSerialized) // _OFF: Power Off + { + Store (0x02, CKC1) + } + } + + } // End LPIO2 I2C #4 + + // + // LPIO2 I2C #5 + // + Device(I2C5) { + Name (_HID, "808622C1") + Name (_CID, "808622C1") + Name (_DDN, "Intel(R) I2C Controller #5 - 808622C5") + Name (_UID, 5) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {36} // I2C #5 IRQ + + FixedDMA(0x18, 0x0, Width32Bit, ) + FixedDMA(0x19, 0x1, Width32Bit, ) + }) + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(I50A, B0BA) + Store(I50L, B0LN) + Return (RBUF) + } + Method (_STA, 0x0, NotSerialized) + { + If (LOr(LEqual(I50A, 0), LEqual(L25D, 1))) + { + Return (0x0) + } + If (LEqual(BDID, CRRB)) { // If it's BSW CR board + Return (0xF) + } + Return (0) // RVP uses this I2C wires as DDI2 DDC SCL & SDA + } + + Method (_PS3, 0, NotSerialized) + { + If (LEqual(I4D3, 1)) { // If I2C 5 Runtime D3 Enabled + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + } + Method (_PS0, 0, NotSerialized) + { + If (LEqual(I4D3, 1)) { // If I2C 5 Runtime D3 Enabled + And(PSAT, 0xFFFFFFFC, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + } + OperationRegion (KEYS, SystemMemory, I51A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + + } // Device(I2C5) + + // + // LPIO2 I2C #6 + // + Device(I2C6) { + Name (_HID, "808622C1") + Name (_CID, "808622C1") + Name (_DDN, "Intel(R) I2C Controller #6 - 808622C6") + Name (_UID, 6) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {37} // I2C #6 IRQ + + FixedDMA(0x1A, 0x02, Width32Bit, ) + FixedDMA(0x1B, 0x03, Width32Bit, ) + }) + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(I60A, B0BA) + Store(I60L, B0LN) + Return (RBUF) + } + Method (_STA, 0x0, NotSerialized) + { + If (LOr(LEqual(I60A, 0), LEqual(L26D, 1))) + { + Return (0x0) + } + Return (0xF) + } + + Method (_PS3, 0, NotSerialized) + { + If (LEqual(I5D3, 1)) { // If I2C 6 Runtime D3 Enabled + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + } + Method (_PS0, 0, NotSerialized) + { + If (LEqual(I5D3, 1)) { // If I2C 6 Runtime D3 Enabled + And(PSAT, 0xFFFFFFFC, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + } + OperationRegion (KEYS, SystemMemory, I61A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + + } // End Device(I2C6) + + // + // LPIO2 I2C #7 + // + Device(I2C7) { + Name (_HID, "808622C1") + Name (_CID, "808622C1") + Name (_DDN, "Intel(R) I2C Controller #7 - 808622C7") + Name (_UID, 7) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {38} // I2C #7 IRQ + + FixedDMA(0x1C, 0x4, Width32Bit, ) + FixedDMA(0x1D, 0x5, Width32Bit, ) + }) + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(I70A, B0BA) + Store(I70L, B0LN) + Return (RBUF) + } + Method (_STA, 0x0, NotSerialized) + { + If (LOr(LEqual(I70A, 0), LEqual(L27D, 1))) + { + Return (0x0) + } + Return (0xF) + } + + Method (_PS3, 0, NotSerialized) + { + If (LEqual(I6D3, 1)) { // If I2C 7 Runtime D3 Enabled + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + } + Method (_PS0, 0, NotSerialized) + { + If (LEqual(I6D3, 1)) { // If I2C 7 Runtime D3 Enabled + And(PSAT, 0xFFFFFFFC, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + } + OperationRegion (KEYS, SystemMemory, I71A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + + } // End Device(I2C7) + diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Pch/PchPcie.asl b/ChvRefCodePkg/AcpiTablesPCAT/Pch/PchPcie.asl new file mode 100644 index 0000000000..745b6ef79d --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Pch/PchPcie.asl @@ -0,0 +1,88 @@ +/** @file + ACPI DSDT table + + Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + OperationRegion(PXCS,PCI_Config,0x40,0xC0) + Field(PXCS,AnyAcc, NoLock, Preserve) + { + Offset(0x10), // LCTL - Link Control Register + L0SE, 1, // 0, L0s Entry Enabled + , 7, + Offset(0x12), // LSTS - Link Status Register + , 13, + LASX, 1, // 0, Link Active Status + Offset(0x1A), // SLSTS[7:0] - Slot Status Register + ABPX, 1, // 0, Attention Button Pressed + , 2, + PDCX, 1, // 3, Presence Detect Changed + , 2, + PDSX, 1, // 6, Presence Detect State + , 1, + Offset(0x20), // RSTS - Root Status Register + , 16, + PSPX, 1, // 16, PME Status + Offset(0x98), // MPC - Miscellaneous Port Configuration Register + , 30, + } + Field(PXCS,AnyAcc, NoLock, WriteAsZeros) + { + Offset(0x9C), // SMSCS - SMI/SCI Status Register + , 30, + HPSX, 1, // 30, Hot Plug SCI Status + PMSX, 1 // 31, Power Management SCI Status + } + + Device(PXSX) + { + Name(_ADR, 0x00000000) + + // NOTE: Any PCIE Hot-Plug dependency for this port is + // specific to the CRB. Please modify the code based on + // your platform requirements. + + Name(_PRW, Package(){0x09, 4}) + + } + + // + // PCI_EXP_STS Handler for PCIE Root Port + // + Method(HPME,0,Serialized) + { + If(PMSX) { + // + // Clear the PME SCI status bit with timout + // + Store(200,Local0) + While(Local0) { + // + // Clear PME SCI Status + // + Store(1, PMSX) + // + // If PME SCI Status is still set, keep clearing it. + // Otherwise, break the while loop. + // + If(PMSX) { + Decrement(Local0) + } else { + Store(0,Local0) + } + } + // + // Notify PCIE Endpoint Devices + // + Notify(PXSX, 0x02) + } + } diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Pch/PchScc.asl b/ChvRefCodePkg/AcpiTablesPCAT/Pch/PchScc.asl new file mode 100644 index 0000000000..e92cfd3850 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Pch/PchScc.asl @@ -0,0 +1,309 @@ +/** @file + ACPI DSDT table + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + // + // eMMC (ACPI Mode) + // + Device(SDHA) { + Name (_HID, "80860F14") + Name (_CID, "PNP0D40") + Name (_DDN, "Intel(R) eMMC Controller - 80862294") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {45} // eMMC IRQ + }) + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(eM0A, B0BA) + Store(eM0L, B0LN) + Return (RBUF) + } + Method (_STA, 0x0, NotSerialized) + { + If (LOr(LEqual(eM0A, 0), LEqual(SD1D, 1))) + { + Return (0x0) + } + Return (0xF) + } + + Method (_PS3, 0, NotSerialized) + { + OR(PSAT, 0x00000003, PSAT) + OR(PSAT, 0x00000000, PSAT) + } + Method (_PS0, 0, NotSerialized) + { + And(PSAT, 0xFFFFFFFC, PSAT) + OR(PSAT, 0x00000000, PSAT) + } + OperationRegion (KEYS, SystemMemory, eM1A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + + Method (_DIS, 0x0, NotSerialized) + { + // Adding dummy disable methods for device EMM0 + } + + Device (EMMD) + { + Name (_ADR, 0x00000008) // Slot 0, Function 8 + Method (_RMV, 0, NotSerialized) + { + Return (0x0) + } + } + } // Device(SDHA) + + // + // eMMC (PCI Mode) + // + Device(PEMC) { + Name(_ADR, 0x00100000) + OperationRegion(SDIO, PCI_Config, 0x84, 0x4) + Field(SDIO,WordAcc,NoLock,Preserve) + { + Offset(0x00), // 0x84, PMCR + , 8, + PMEE, 1, //PME_EN + , 6, + PMES, 1 //PME_STS + } + + Method (_STA, 0x0, NotSerialized) + { + If (LAnd(LEqual(eM0A, 0), LEqual(SD1D, 0))) + { + Return(0xF) + } + Else + { + Return(0x0) + } + } + + Method(_DSW, 3) + { + } // End _DSW + + Device (CARD) + { + Name (_ADR, 0x00000008) + Method(_RMV, 0x0, NotSerialized) + { + Return (0) + } // End _RMV + } + } // Device(PEMC) + + // + // SDIO + // + Device(SDHB) { + Name(_ADR, 0x00110000) + Name (_HID, "INT33BB") + Name (_CID, "PNP0D40") + Name (_DDN, "Intel(R) SDIO Controller - 80862295") + Name (_UID, 2) + Name (_HRV, 2) + Name (_DEP, Package() {\_SB.GPO1}) + Name (PSTS, 0x0) + + Name (ABUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {46} // SDIO IRQ + // Added here for Android Support ++ + GpioIo(Exclusive, PullNone, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {5} // COMBO_WLAN _R_EN to GPIO N5 + // Added here for Android Support -- + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^ABUF, ^BAR0._BAS, B0BA) + CreateDwordField(^ABUF, ^BAR0._LEN, B0LN) + Store(SI0A, B0BA) + Store(SI0L, B0LN) + Return(ABUF) + } + Method (_STA, 0x0, NotSerialized) + { + If (LOr(LEqual(SI0A, 0), LEqual(SD2D, 1))) + { + Return (0x0) + } + Return (0xF) + } + Method (_DIS, 0x0, NotSerialized) + { + // Adding dummy disable methods for device EMM0 + } + + Method (_PS3, 0, NotSerialized) + { + OR(PSAT, 0x00000003, PSAT) + OR(PSAT, 0x00000000, PSAT) + } + Method (_PS0, 0, NotSerialized) + { + And(PSAT, 0xFFFFFFFC, PSAT) + OR(PSAT, 0x00000000, PSAT) + If(LEqual(\_SB.PCI0.SDHB.PSTS, 0x0)) + { + If(LEqual (\_SB.GPO1.AVBL, 1)) { + Store( 0x01, \_SB.GPO1.CWLE ) // COMBO_WLAN_EN = 1 put WLAN to enabled state + } + Store( 0x01, \_SB.PCI0.SDHB.PSTS) // Indicates that the device is powered on + } + } + OperationRegion (KEYS, SystemMemory, SI1A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + + } // Device(SDHB) + + // + // SD Card + // + Device(SDHC) { + Name(_ADR, 0x00120000) + Name (_HID, "80860F14") + Name (_CID, "PNP0D40") + Name (_HRV, 0x0001) + Name (_DDN, "Intel(R) SD Card Controller - 80862296") + Name (_UID, 3) + Name (ABUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {47} // SD Card IRQ + GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 10000, "\\_SB.GPO3", 0, ResourceConsumer, , ) {81} // SE81 + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionInputOnly, "\\_SB.GPO3", 0, ResourceConsumer, , ) {81} // SE81 + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionInputOnly, "\\_SB.GPO3", 0, ResourceConsumer, , ) {85} // SE85 + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionInputOnly, "\\_SB.GPO3", 0, ResourceConsumer, , ) {78} // SE78 + }) + Name (WBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BARA) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {47} // SD Card IRQ + GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 10000, "\\_SB.GPO3", 0, ResourceConsumer, , ) {81} // SE81 + GpioIO(Shared, PullDefault, 0, 0, IoRestrictionInputOnly, "\\_SB.GPO3", 0, ResourceConsumer, , ) {81} // SE81 + }) + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^ABUF, ^BAR0._BAS, B0BA) + CreateDwordField(^ABUF, ^BAR0._LEN, B0LN) + Store(SD0A, B0BA) + Store(SD0L, B0LN) + CreateDwordField(^WBUF, ^BARA._BAS, B01A) + CreateDwordField(^WBUF, ^BARA._LEN, B01N) + Store(SD0A, B01A) + Store(SD0L, B01N) + //CreateDwordField(^RBUF, BAR1._BAS, B1BA) + //CreateDwordField(^RBUF, BAR1._LEN, B1LN) + //Store(SD1A, B1BA) + //Store(SD1L, B1LN) + If (LEqual(OSID,2)) + { + Return (ABUF) + } + Return(WBUF) + } + Method (_STA, 0x0, NotSerialized) + { + If (LOr(LEqual(SD0A, 0), LEqual(SD3D, 1))) + { + Return (0x0) + } + Return (0xF) + } + + Method (_PS3, 0, NotSerialized) + { + + OR(PSAT, 0x00000003, PSAT) + OR(PSAT, 0x00000000, PSAT) + } + Method (_PS0, 0, NotSerialized) + { + And(PSAT, 0xFFFFFFFC, PSAT) + OR(PSAT, 0x00000000, PSAT) + Sleep (1000) + } + OperationRegion (KEYS, SystemMemory, SD1A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + + Method(_DSM, 0x4, NotSerialized) + { + If(LEqual(Arg0, Buffer(0x10) { + 0xa5, 0x3e, 0xc1, 0xf6, 0xcd, 0x65, 0x1f, 0x46, 0xab, 0x7a, 0x29, 0xf7, + 0xe8, 0xd5, 0xbd, 0x61 + })) { + If (LEqual (Arg1, Zero)) { + If (LEqual (Arg2, Zero)) { + Return (Buffer (0x4) + { + 0x1F,0x0,0x0,0x0 + }) + } + If (LEqual (Arg2, One)) { + // + // Clear Power Control Register + // + Sleep (5) // Delay for Clear +VSDIO Power Control + Return (One) + } + If (LEqual (Arg2, 2)) { + // + // Set Power Control Register + // + Return (0x2) + } + If (LEqual (Arg2, 3)) { + // + // Set 1.8v signalling + // + Sleep (VS18) // Delay for 1.8 Volt +VSDIO switching + Return (0x3) + } + If (LEqual (Arg2, 4)) { + // + // Set 3.3v signalling + // + Sleep (VD33) // Delay for 3.3 Volt +VSDIO switching + Return (0x4) + } + } Else { + Return (Zero) + } + Return (Zero) + } + } + } // Device (SDHC) diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Pch/PchSmb.asl b/ChvRefCodePkg/AcpiTablesPCAT/Pch/PchSmb.asl new file mode 100644 index 0000000000..ad48359ca9 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Pch/PchSmb.asl @@ -0,0 +1,592 @@ +/** @file + ACPI DSDT table + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// Define various SMBus PCI Configuration Space Registers. + +OperationRegion(SMBP,PCI_Config,0x40,0xC0) +Field(SMBP,DWordAcc,NoLock,Preserve) +{ + , 2, + I2CE, 1 +} + +OperationRegion(SMPB,PCI_Config,0x20,4) +Field(SMPB,DWordAcc,NoLock,Preserve) +{ + , 5, + SBAR, 11 +} + +// Define various SMBus IO Mapped Registers. + +OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10) +Field(SMBI,ByteAcc,NoLock,Preserve) +{ + HSTS, 8, // 0 - Host Status Register + Offset(0x02), + HCON, 8, // 2 - Host Control + HCOM, 8, // 3 - Host Command + TXSA, 8, // 4 - Transmit Slave Address + DAT0, 8, // 5 - Host Data 0 + DAT1, 8, // 6 - Host Data 1 + HBDR, 8, // 7 - Host Block Data + PECR, 8, // 8 - Packer Error Check + RXSA, 8, // 9 - Receive Slave Address + SDAT, 16, // A - Slave Data +} + +// SMBus Send Byte - This function will write a single byte of +// data to a specific Slave Device per SMBus Send Byte Protocol. +// Arg0 = Address +// Arg1 = Data +// Return: Success = 1 +// Failure = 0 + +Method(SSXB,2,Serialized) +{ + // Step 1: Confirm the ICHx SMBus is ready to perform + // communication. + + If(STRT()) + { + Return(0) + } + + // Step 2: Initiate a Send Byte. + + Store(0,I2CE) // Ensure SMbus Mode. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Arg0,TXSA) // Write Address in TXSA. + Store(Arg1,HCOM) // Data in HCOM. + + // Set the SMBus Host control register to 0x48. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 001 = Byte Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x48,HCON) + + // Step 3: Exit the Method correctly. + + If(COMP) + { + Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others.. + Return(1) // Return Success. + } + + Return(0) +} + +// SMBus Receive Byte - This function will write a single byte +// of data to a specific Slave Device per SMBus Receive Byte +// Protocol. +// Arg0 = Address +// Return: Success = Byte-Size Value +// Failure = Word-Size Value = FFFFh. + +Method(SRXB,1,Serialized) +{ + // Step 1: Confirm the ICHx SMBus is ready to perform + // communication. + + If(STRT()) + { + Return(0xFFFF) + } + + // Step 2: Initiate a Receive Byte. + + Store(0,I2CE) // Ensure SMbus Mode. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Or(Arg0,1),TXSA) // Read Address in TXSA. + + // Set the SMBus Host control register to 0x48. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 001 = Byte Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x44,HCON) + + // Step 3: Exit the Method correctly. + + If(COMP) + { + Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others.. + Return(DAT0) // Return Success. + } + + Return(0xFFFF) // Return Failure. +} + +// SMBus Write Byte - This function will write a single byte +// of data to a specific Slave Device per SMBus Write Byte +// Protocol. +// Arg0 = Address +// Arg1 = Command +// Arg2 = Data +// Return: Success = 1 +// Failure = 0 + +Method(SWRB,3,Serialized) +{ + // Step 1: Confirm the ICHx SMBus is ready to perform communication. + + If(STRT()) + { + Return(0) + } + + // Step 2: Initiate a Write Byte. + + Store(0,I2CE) // Ensure SMbus Mode. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Arg0,TXSA) // Write Address in TXSA. + Store(Arg1,HCOM) // Command in HCOM. + Store(Arg2,DAT0) // Data in DAT0. + + // Set the SMBus Host control register to 0x48. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 010 = Byte Data Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x48,HCON) + + // Step 3: Exit the Method correctly. + + If(COMP) + { + Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others.. + Return(1) // Return Success. + } + + Return(0) // Return Failure. +} + +// SMBus Read Byte - This function will read a single byte of data +// from a specific slave device per SMBus Read Byte Protocol. +// Arg0 = Address +// Arg1 = Command +// Return: Success = Byte-Size Value +// Failure = Word-Size Value + +Method(SRDB,2,Serialized) +{ + // Step 1: Confirm the ICHx SMBus is ready to perform communication. + + If(STRT()) + { + Return(0xFFFF) + } + + // Step 2: Initiate a Read Byte. + + Store(0,I2CE) // Ensure SMbus Mode. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Or(Arg0,1),TXSA) // Read Address in TXSA. + Store(Arg1,HCOM) // Command in HCOM. + + // Set the SMBus Host control register to 0x48. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 010 = Byte Data Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x48,HCON) + + // Step 3: Exit the Method correctly. + + If(COMP) + { + Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others.. + Return(DAT0) // Return Success. + } + + Return(0xFFFF) // Return Failure. +} + +// SMBus Write Word - This function will write a single word +// of data to a specific Slave Device per SMBus Write Word +// Protocol. +// Arg0 = Address +// Arg1 = Command +// Arg2 = Data (16 bits in size) +// Return: Success = 1 +// Failure = 0 + +Method(SWRW,3,Serialized) +{ + // Step 1: Confirm the ICHx SMBus is ready to perform communication. + + If(STRT()) + { + Return(0) + } + + // Step 2: Initiate a Write Word. + + Store(0,I2CE) // Ensure SMbus Mode. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Arg0,TXSA) // Write Address in TXSA. + Store(Arg1,HCOM) // Command in HCOM. + And(Arg2,0xFF,DAT1) // Low byte Data in DAT1. + And(ShiftRight(Arg2,8),0xFF,DAT0) // High byte Data in DAT0. + + // Set the SMBus Host control register to 0x4C. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 011 = Word Data Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x4C,HCON) + + // Step 3: Exit the Method correctly. + + If(COMP()) + { + Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others. + Return(1) // Return Success. + } + + Return(0) // Return Failure. +} + +// SMBus Read Word - This function will read a single byte of data +// from a specific slave device per SMBus Read Word Protocol. +// Arg0 = Address +// Arg1 = Command +// Return: Success = Word-Size Value +// Failure = Dword-Size Value + +Method(SRDW,2,Serialized) +{ + // Step 1: Confirm the ICHx SMBus is ready to perform communication. + + If(STRT()) + { + Return(0xFFFF) + } + + // Step 2: Initiate a Read Word. + + Store(0,I2CE) // Ensure SMbus Mode. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Or(Arg0,1),TXSA) // Read Address in TXSA. + Store(Arg1,HCOM) // Command in HCOM. + + // Set the SMBus Host control register to 0x4C. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 011 = Word Data Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x4C,HCON) + + // Step 3: Exit the Method correctly. + + If(COMP()) + { + Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others. + Return(Or(ShiftLeft(DAT0,8),DAT1)) // Return Success. + } + + Return(0xFFFFFFFF) // Return Failure. +} + +// SMBus Block Write - This function will write an entire block of data +// to a specific slave device per SMBus Block Write Protocol. +// Arg0 = Address +// Arg1 = Command +// Arg2 = Buffer of Data to Write +// Arg3 = 1 = I2C Block Write, 0 = SMBus Block Write +// Return: Success = 1 +// Failure = 0 + +Method(SBLW,4,Serialized) +{ + // Step 1: Confirm the ICHx SMBus is ready to perform communication. + + If(STRT()) + { + Return(0) + } + + // Step 2: Initiate a Block Write. + + Store(Arg3,I2CE) // Select the proper protocol. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Arg0,TXSA) // Write Address in TXSA. + Store(Arg1,HCOM) // Command in HCOM. + Store(Sizeof(Arg2),DAT0) // Count in DAT0. + Store(0,Local1) // Init Pointer to Buffer. + Store(DerefOf(Index(Arg2,0)),HBDR) // First Byte in HBD Register. + + // Set the SMBus Host control register to 0x48. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 101 = Block Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x54,HCON) + + // Step 3: Send the entire Block of Data. + + While(LGreater(Sizeof(Arg2),Local1)) + { + // Wait up to 200ms for Host Status to get set. + + Store(4000,Local0) // 4000 * 50us = 200ms. + + While(LAnd(LNot(And(HSTS,0x80)),Local0)) + { + Decrement(Local0) // Decrement Count. + Stall(50) // Delay = 50us. + } + + If(LNot(Local0)) // Timeout? + { + KILL() // Yes. Kill Communication. + Return(0) // Return failure. + } + + Store(0x80,HSTS) // Clear Host Status. + Increment(Local1) // Point to Next Byte. + + // Place next byte in HBDR if last byte has not been sent. + + If(LGreater(Sizeof(Arg2),Local1)) + { + Store(DerefOf(Index(Arg2,Local1)),HBDR) + } + } + + // Step 4: Exit the Method correctly. + + If(COMP()) + { + Or(HSTS,0xFF,HSTS) // Clear all status bits. + Return(1) // Return Success. + } + + Return(0) // Return Failure. +} + +// SMBus Block Read - This function will read a block of data from +// a specific slave device per SMBus Block Read Protocol. +// Arg0 = Address +// Arg1 = Command +// Arg2 = 1 = I2C Block Write, 0 = SMBus Block Write +// Return: Success = Data Buffer (First Byte = length) +// Failure = 0 + +Method(SBLR,3,Serialized) +{ + Name(TBUF, Buffer(256) {}) + + // Step 1: Confirm the ICHx SMBus is ready to perform communication. + + If(STRT()) + { + Return(0) + } + + // Step 2: Initiate a Block Read. + + Store(Arg2,I2CE) // Select the proper protocol. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Or(Arg0,1),TXSA) // Read Address in TXSA. + Store(Arg1,HCOM) // Command in HCOM. + + // Set the SMBus Host control register to 0x48. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 101 = Block Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x54,HCON) + + // Step 3: Wait up to 200ms to get the Data Count. + + Store(4000,Local0) // 4000 * 50us = 200ms. + + While(LAnd(LNot(And(HSTS,0x80)),Local0)) + { + Decrement(Local0) // Decrement Count. + Stall(50) // Delay = 50us. + } + + If(LNot(Local0)) // Timeout? + { + KILL() // Yes. Kill Communication. + Return(0) // Return failure. + } + + Store(DAT0,Index(TBUF,0)) // Get the Data Count. + Store(0x80,HSTS) // Clear Host Status. + Store(1,Local1) // Local1 = Buffer Pointer. + + // Step 4: Get the Block Data and store it. + + While(LLess(Local1,DerefOf(Index(TBUF,0)))) + { + // Wait up to 200ms for Host Status to get set. + + Store(4000,Local0) // 4000 * 50us = 200ms. + + While(LAnd(LNot(And(HSTS,0x80)),Local0)) + { + Decrement(Local0) // Decrement Count. + Stall(50) // Delay = 50us. + } + + If(LNot(Local0)) // Timeout? + { + KILL() // Yes. Kill Communication. + Return(0) // Return failure. + } + + Store(HBDR,Index(TBUF,Local1)) // Place into Buffer. + Store(0x80,HSTS) // Clear Host Status. + Increment(Local1) + } + + // Step 5: Exit the Method correctly. + + If(COMP()) + { + Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others. + Return(TBUF) // Return Success. + } + + Return(0) // Return Failure. +} + + +// SMBus Start Check +// Return: Success = 0 +// Failure = 1 + +Method(STRT,0,Serialized) +{ + // Wait up to 200ms to confirm the SMBus Semaphore has been + // released (In Use Status = 0). Note that the Sleep time may take + // longer as the This function will yield the Processor such that it + // may perform different tasks during the delay. + + Store(200,Local0) // 200 * 1ms = 200ms. + + While(Local0) + { + If(And(HSTS,0x40)) // In Use Set? + { + Decrement(Local0) // Yes. Decrement Count. + Sleep(1) // Delay = 1ms. + If(LEqual(Local0,0)) // Count = 0? + { + Return(1) // Return failure. + } + } + Else + { + Store(0,Local0) // In Use Clear. Continue. + } + } + + // In Use Status = 0 during last read, which will make subsequent + // reads return In Use Status = 1 until software clears it. All + // software using ICHx SMBus should check this bit before initiating + // any SMBus communication. + + // Wait up to 200ms to confirm the Host Interface is + // not processing a command. + + Store(4000,Local0) // 4000 * 50us = 200ms. + + While(Local0) + { + If(And(HSTS,0x01)) // Host Busy Set? + { + Decrement(Local0) // Decrement Count. + Stall(50) // Delay = 50us. + If(LEqual(Local0,0)) // Count = 0? + { + KILL() // Yes. Kill Communication. + } + } + Else + { + Return(0) + } + } + + Return(1) // Timeout. Return failure. +} + +// SMBus Completion Check +// Return: Success = 1 +// Failure = 0 + +Method(COMP,0,Serialized) +{ + // Wait for up to 200ms for the Completion Command + // Status to get set. + + Store(4000,Local0) // 4000 * 50us = 200ms. + + While(Local0) + { + If(And(HSTS,0x02)) // Completion Status Set? + { + Return(1) // Yes. We are done. + } + Else + { + Decrement(Local0) // Decrement Count. + Stall(50) // Delay 50us. + If(LEqual(Local0,0)) // Count = 0? + { + KILL() // Yes. Kill Communication. + } + } + } + + Return(0) // Timeout. Return Failure. +} + +// SMBus Kill Command + +Method(KILL,0,Serialized) +{ + Or(HCON,0x02,HCON) // Yes. Send Kill command. + Or(HSTS,0xFF,HSTS) // Clear all status. +} diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Pch/PchXhci.asl b/ChvRefCodePkg/AcpiTablesPCAT/Pch/PchXhci.asl new file mode 100644 index 0000000000..5982637ac1 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Pch/PchXhci.asl @@ -0,0 +1,443 @@ +/** @file + ACPI DSDT table + + Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Scope(\_SB) + { + // + // Dummy power resource for USB D3 cold support + // + PowerResource(USBC, 0, 0) + { + Method(_STA) { Return (0xF) } + Method(_ON) {} + Method(_OFF) {} + } + } + + // + // xHCI Controller - Device 20, Function 0 + // + Device(XHC1) { + Name(_ADR, 0x00140000) + Name(_PRW, Package() {0x0D, 4}) + Name (_S3D, 2) + Name (_S4D, 2) + Name (XFLT, 0x0) + + Method (_PS3, 0, NotSerialized) + { + } + + Method (_PS0, 0, NotSerialized) + { + Store (1, PMEB) + } + + Method(_DSM, 0x4, Serialized) + { + // + // GUID Match + // + If(LEqual(Arg0, Buffer(0x10) + { + 0xb7, 0x0c, 0x34, 0xac, 0x01, 0xe9, 0xbf, 0x45, 0xb7, 0xe6, 0x2b, 0x34, + 0xec, 0x93, 0x1e, 0x23 + })) + { + // + // Only Supported value is "0x3" + // + If(LEqual(Arg1, 0x3)) + { + Store(Arg1,XFLT) + } + } + } + + Method(_S0W, 0x0, NotSerialized) + { + If (\_OSI("Android")) // FOR AOS case Return D3 + { + Return (0x3) + } + If (LEqual(XFLT, Zero)) // Filter Driver will set XFLT for WOS + { + Return (0x0) + } Else { + Return (0x3) + } + } + + OperationRegion (USBR, PCI_Config, 0x00, 0x98) + Field (USBR, WordAcc, NoLock, Preserve) + { + Offset (0x10), + BAR0, 32, + Offset (0x74), + , 8, + PMEE, 1, + , 6, + PMES, 1 + } + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + Return (Zero) + } + + Method (_PR3, 0, NotSerialized) // _PR3: Power Resources for D3hot + { + Return (Package (0x01) + { + USBC + }) + } + + Device(RHUB) + { + Name(_ADR, Zero) + + // + // High Speed Ports + // + Device(HS01) // Pair with SSP1 + { + Name(_ADR, 0x01) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { + 0xFF, // Port is connectable if the value is non-zero + 0x03, // USB 3 Standard-A connector + 0x00, + 0x00 + }) + Return(UPCP) + } + + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10) + { + 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x61, 0x0C, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }) + Return (PLDP) + } + } // end of HS01 + + Device(HS02) // Pair with SSP2 + { + Name(_ADR, 0x02) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { + 0xFF, // Port is connectable if the value is non-zero + 0x03, // USB 3 Standard-A connector + 0x00, + 0x00 + }) + Return(UPCP) + } + + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10) + { + 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x61, 0x0C, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00 + } + }) + Return (PLDP) + } + } // end of HS02 + + Device(HS03) // Pair with SSP3 + { + Name(_ADR, 0x03) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { + 0xFF, // Port is connectable if the value is non-zero + 0xFF, // Proprietary connector, also set _PLD bit64 User Visible to 0. + 0x00, + 0x00 + }) + Return(UPCP) + } + + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10) + { + 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x60, 0x0C, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00 + } + }) + Return (PLDP) + } + } // end of HS03 + + Device(HS04) // Pair with SSP4 + { + Name(_ADR, 0x04) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { + 0xFF, // Port is connectable if the value is non-zero + 0xFF, // Proprietary connector, also set _PLD bit64 User Visible to 0. + 0x00, + 0x00 + }) + Return(UPCP) + } + + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10) + { + 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x60, 0x0C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00 + } + }) + Return (PLDP) + } + } // end of HS04 + + Device(HS05) + { + Name(_ADR, 0x05) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { + 0xFF, // Port is connectable if the value is non-zero + 0x00, // Type 'A' connector + 0x00, + 0x00 + }) + Return(UPCP) + } + + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10) + { + 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x61, 0x0C, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00 + } + }) + Return (PLDP) + } + } // end of HS05 + + Device(HS06) // HSIC Port, pair with SSP5 + { + Name(_ADR, 0x06) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { + 0xFF, // Port is connectable if the value is non-zero + 0xFF, // Proprietary connector + 0x00, + 0x00 + }) + Return(UPCP) + } + + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10) + { + 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x60, 0x0C, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00 + } + }) + Return (PLDP) + } + } // end of HS06 + + Device(HS07) // HSIC Port, pair with SSP6 + { + Name(_ADR, 0x07) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { + 0xFF, // Port is connectable if the value is non-zero + 0xFF, // Proprietary connector + 0x00, + 0x00 + }) + Return(UPCP) + } + + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10) + { + 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x60, 0x0C, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00 + } + }) + Return (PLDP) + } + } // end of HS07 + + // + // Super Speed Ports - must match _UPC declarations of the coresponding High Speed Ports. + // + Device(SSP1) // Pair with HS01 + { + Name(_ADR, 0x08) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { + 0xFF, // Port is connectable if the value is non-zero. + 0x03, // USB 3 Standard-A connector + 0x00, + 0x00 + }) + Return(UPCP) + } + + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10) + { + 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x61, 0x0C, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }) + Return (PLDP) + } + } // end of SSP1 + + Device(SSP2) // Pair with HS02 + { + Name(_ADR, 0x09) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { + 0xFF, // Port is connectable if the value is non-zero. + 0x03, // USB 3 Standard-A connector + 0x00, + 0x00 + }) + Return(UPCP) + } + + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10) + { + 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x61, 0x0C, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00 + } + }) + Return (PLDP) + } + } // end of SSP2 + + Device(SSP3) // Pair with HS03 + { + Name(_ADR, 0x0A) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { + 0xFF, // Port is connectable if the value is non-zero. + 0xFF, // Proprietary connector, also set _PLD bit64 User Visible to 0. + 0x00, + 0x00 + }) + Return(UPCP) + } + + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10) + { + 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x60, 0x0C, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00 + } + }) + Return (PLDP) + } + } // end of SSP3 + + Device(SSP4) // Pair with HS04 + { + Name(_ADR, 0x0B) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { + 0xFF, // Port is connectable if the value is non-zero. + 0xFF, // Proprietary connector, also set _PLD bit64 User Visible to 0. + 0x00, + 0x00 + }) + Return(UPCP) + } + + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10) + { + 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x60, 0x0C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00 + } + }) + Return (PLDP) + } + } // end of SSP4 + + Device(SSP5) // SSIC Port, pair with HS06 + { + Name(_ADR, 0x0C) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { + 0xFF, // Port is connectable if the value is non-zero. + 0xFF, // Proprietary connector + 0x00, + 0x00 + }) + Return(UPCP) + } + + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10) + { + 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x60, 0x0C, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00 + } + }) + Return (PLDP) + } + } // end of SSP5 + + Device(SSP6) // SSIC Port, pair with HS07 + { + Name(_ADR, 0x0D) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { + 0xFF, // Port is connectable if the value is non-zero. + 0xFF, // Proprietary connector + 0x00, + 0x00 + }) + Return(UPCP) + } + + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x10) + { + 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x60, 0x0C, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00 + } + }) + Return (PLDP) + } + } // end of SSP6 + + } // end of RHUB + } // end of XHC1 diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Pch/PciTree.asl b/ChvRefCodePkg/AcpiTablesPCAT/Pch/PciTree.asl new file mode 100644 index 0000000000..4df759d6df --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Pch/PciTree.asl @@ -0,0 +1,254 @@ +/** @file + ACPI DSDT table + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(\_SB) { + + Name(PR00, Package(){ +// Host Bridge +// Mobile IGFX + Package(){0x0002FFFF, 0, LNKA, 0 }, +// IUNIT + Package(){0x0003FFFF, 0, LNKB, 0 }, +// ISH + Package(){0x000AFFFF, 0, LNKE, 0 }, +// PUNIT + Package(){0x000BFFFF, 0, LNKF, 0 }, +// SD Host #0 - eMMC + Package(){0x0010FFFF, 0, LNKA, 0 }, +// SD Host #1 - SDIO + Package(){0x0011FFFF, 0, LNKB, 0 }, +// SD Host #2 - SD Card + Package(){0x0012FFFF, 0, LNKC, 0 }, +// SATA Controller + Package(){0x0013FFFF, 0, LNKD, 0 }, +// xHCI Host + Package(){0x0014FFFF, 0, LNKE, 0 }, +// Low Power Audio Engine + Package(){0x0015FFFF, 0, LNKF, 0 }, +// USB OTG + Package(){0x0016FFFF, 0, LNKH, 0 }, +// LPIO2 DMA +// LPIO2 I2C #4 + Package(){0x0018FFFF, 0, LNKB, 0 }, +// LPIO2 I2C #1 +// LPIO2 I2C #5 + Package(){0x0018FFFF, 2, LNKD, 0 }, +// LPIO2 I2C #2 +// LPIO2 I2C #6 + Package(){0x0018FFFF, 3, LNKC, 0 }, +// LPIO2 I2C #3 +// LPIO2 I2C #7 + Package(){0x0018FFFF, 1, LNKA, 0 }, +// SeC + Package(){0x001AFFFF, 0, LNKF, 0 }, +// High Definition Audio Controller + Package(){0x001BFFFF, 0, LNKG, 0 }, +// LPIO1 DMA +// LPIO1 HS-UART #2 + Package(){0x001EFFFF, 0, LNKD, 0 }, +// LPIO1 PWM #1 +// LPIO1 SPI #1 + Package(){0x001EFFFF, 3, LNKA, 0 }, +// LPIO1 PWM #2 +// LPIO1 SPI #2 + Package(){0x001EFFFF, 1, LNKB, 0 }, +// LPIO1 HS-UART #1 +// LPIO1 SPI #3 + Package(){0x001EFFFF, 2, LNKC, 0 }, +// LPC Bridge +// SMBus Controller + Package(){0x001FFFFF, 1, LNKC, 0 }, +// PCIE Root Port #1 + Package(){0x001CFFFF, 0, LNKA, 0 }, +// PCIE Root Port #2 + Package(){0x001CFFFF, 1, LNKB, 0 }, +// PCIE Root Port #3 + Package(){0x001CFFFF, 2, LNKC, 0 }, +// PCIE Root Port #4 + Package(){0x001CFFFF, 3, LNKD, 0 }, + }) + + Name(AR00, Package(){ +// Host Bridge +// Mobile IGFX + Package(){0x0002FFFF, 0, 0, 16 }, +// IUNIT + Package(){0x0003FFFF, 0, 0, 17 }, +// ISH + Package(){0x000AFFFF, 0, 0, 20 }, +// PUNIT + Package(){0x000BFFFF, 0, 0, 21 }, +// SD Host #0 - eMMC + Package(){0x0010FFFF, 0, 0, 16 }, +// SD Host #1 - SDIO + Package(){0x0011FFFF, 0, 0, 17 }, +// SD Host #2 - SD Card + Package(){0x0012FFFF, 0, 0, 18 }, +// SATA Controller + Package(){0x0013FFFF, 0, 0, 19 }, +// xHCI Host + Package(){0x0014FFFF, 0, 0, 20 }, +// Low Power Audio Engine + Package(){0x0015FFFF, 0, 0, 21 }, +// USB OTG + Package(){0x0016FFFF, 0, 0, 23 }, +// LPIO2 DMA +// LPIO2 I2C #4 + Package(){0x0018FFFF, 0, 0, 17 }, +// LPIO2 I2C #1 +// LPIO2 I2C #5 + Package(){0x0018FFFF, 2, 0, 19 }, +// LPIO2 I2C #2 +// LPIO2 I2C #6 + Package(){0x0018FFFF, 3, 0, 18 }, +// LPIO2 I2C #3 +// LPIO2 I2C #7 + Package(){0x0018FFFF, 1, 0, 16 }, +// SeC + Package(){0x001AFFFF, 0, 0, 21 }, +// High Definition Audio Controller + Package(){0x001BFFFF, 0, 0, 22 }, +// LPIO1 DMA +// LPIO1 HS-UART #2 + Package(){0x001EFFFF, 0, 0, 19 }, +// LPIO1 PWM #1 +// LPIO1 SPI #1 + Package(){0x001EFFFF, 3, 0, 16 }, +// LPIO1 PWM #2 +// LPIO1 SPI #2 + Package(){0x001EFFFF, 1, 0, 17 }, +// LPIO1 HS-UART #1 +// LPIO1 SPI #3 + Package(){0x001EFFFF, 2, 0, 18 }, +// LPC Bridge +// SMBus Controller + Package(){0x001FFFFF, 1, 0, 18 }, +// PCIE Root Port #1 + Package(){0x001CFFFF, 0, 0, 16 }, +// PCIE Root Port #2 + Package(){0x001CFFFF, 1, 0, 17 }, +// PCIE Root Port #3 + Package(){0x001CFFFF, 2, 0, 18 }, +// PCIE Root Port #4 + Package(){0x001CFFFF, 3, 0, 19 }, + }) + + Name(PR04, Package(){ +// PCIE Port #1 Slot + Package(){0x0000FFFF, 0, LNKA, 0 }, + Package(){0x0000FFFF, 1, LNKB, 0 }, + Package(){0x0000FFFF, 2, LNKC, 0 }, + Package(){0x0000FFFF, 3, LNKD, 0 }, + }) + + Name(AR04, Package(){ +// PCIE Port #1 Slot + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PR05, Package(){ +// PCIE Port #2 Slot + Package(){0x0000FFFF, 0, LNKB, 0 }, + Package(){0x0000FFFF, 1, LNKC, 0 }, + Package(){0x0000FFFF, 2, LNKD, 0 }, + Package(){0x0000FFFF, 3, LNKA, 0 }, + }) + + Name(AR05, Package(){ +// PCIE Port #2 Slot + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PR06, Package(){ +// PCIE Port #3 Slot + Package(){0x0000FFFF, 0, LNKC, 0 }, + Package(){0x0000FFFF, 1, LNKD, 0 }, + Package(){0x0000FFFF, 2, LNKA, 0 }, + Package(){0x0000FFFF, 3, LNKB, 0 }, + }) + + Name(AR06, Package(){ +// PCIE Port #3 Slot + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PR07, Package(){ +// PCIE Port #4 Slot + Package(){0x0000FFFF, 0, LNKD, 0 }, + Package(){0x0000FFFF, 1, LNKA, 0 }, + Package(){0x0000FFFF, 2, LNKB, 0 }, + Package(){0x0000FFFF, 3, LNKC, 0 }, + }) + + Name(AR07, Package(){ +// PCIE Port #4 Slot + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + +//--------------------------------------------------------------------------- +// List of IRQ resource buffers compatible with _PRS return format. +//--------------------------------------------------------------------------- +// Naming legend: +// RSxy, PRSy - name of the IRQ resource buffer to be returned by _PRS, "xy" - last two characters of IRQ Link name. +// Note. PRSy name is generated if IRQ Link name starts from "LNK". +// HLxy , LLxy - reference names, can be used to access bit mask of available IRQs. HL and LL stand for active High(Low) Level triggered Irq model. +//--------------------------------------------------------------------------- + Name(PRSA, ResourceTemplate(){ // Link name: LNKA + IRQ(Level, ActiveLow, Shared, LLKA) {3,4,5,6,10,11,12,14,15} + }) + Alias(PRSA,PRSB) // Link name: LNKB + Alias(PRSA,PRSC) // Link name: LNKC + Alias(PRSA,PRSD) // Link name: LNKD + Alias(PRSA,PRSE) // Link name: LNKE + Alias(PRSA,PRSF) // Link name: LNKF + Alias(PRSA,PRSG) // Link name: LNKG + Alias(PRSA,PRSH) // Link name: LNKH +//--------------------------------------------------------------------------- +// Begin PCI tree object scope +//--------------------------------------------------------------------------- + + Device(PCI0) { // PCI Bridge "Host Bridge" + Name(_HID, EISAID("PNP0A08")) // Indicates PCI Express/PCI-X Mode2 host hierarchy + Name(_CID, EISAID("PNP0A03")) // To support legacy OS that doesn't understand the new HID + Name(_ADR, 0x00000000) + Method(^BN00, 0) { return(0x0000) } // Returns default Bus number for Peer PCI busses. Name can be overriden with control method placed directly under Device scope + Method(_BBN, 0) { return(BN00()) } // Bus number, optional for the Root PCI Bus + Name(_UID, 0x0000) // Unique Bus ID, optional + + Method(_PRT,0) { + If(PICM) {Return(AR00)} // APIC mode + Return (PR00) // PIC Mode + } // end _PRT + + include("SystemAgent/HostBus.asl") + Device(LPCB) { // LPC Bridge + Name(_ADR, 0x001F0000) + include("Pch/LpcB.asl") + } // end "LPC Bridge" + + } // end PCI0 Bridge "Host Bridge" +} // end _SB scope diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Audio/Audio.asl b/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Audio/Audio.asl new file mode 100644 index 0000000000..4271301048 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Audio/Audio.asl @@ -0,0 +1,60 @@ +/** @file + ACPI DSDT table + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + //<<<>>> diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Audio/Realtek.asl b/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Audio/Realtek.asl new file mode 100644 index 0000000000..af547c4ad7 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Audio/Realtek.asl @@ -0,0 +1,68 @@ +/** @file + ACPI DSDT table + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + // + // Realtek Audio Codec + // + Device (RTEK) //Audio Codec driver I2C + { + Name (_ADR, 0) + Name (_HID, "10EC5670") + Name (_CID, "10EC5670") + Name (_DDN, "RTEK Codec Controller " ) + Name (_UID, 1) + + Method(_CRS, 0x0, NotSerialized) + { + Name(SBUF,ResourceTemplate () + { + I2CSerialBus( + 0x1C, // SlaveAddress: bus address + , // SlaveMode: default to ControllerInitiated + 400000, // ConnectionSpeed: in Hz + , // Addressing Mode: default to 7 bit + "\\_SB.PCI0.I2C2", // ResourceSource: I2C bus controller name + , // Descriptor Name: creates name for offset of resource descriptor + ) //VendorData + ///Interrupt (ResourceConsumer, Edge, ActiveHigh, ExclusiveAndWake, , , ) {92} // SE77 Line#0 route to IOAPIC IRQ 92 + GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullNone, 0,"\\_SB.GPO3") {77} // SE77: GPIO_ALERT from AUDIO_CODEC_INT + }) + Return (SBUF) + } + + Method (_PS3, 0, NotSerialized) // _PS3: Power State 3 + { + Store (Zero, CKC3) + } + + Method (_PS0, 0, NotSerialized) // _PS0: Power State 0 + { + Store (One, CKC3) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method(_STA, 0x0, NotSerialized) + { + If (LEqual(LPES, 2)) // LPE Audio ACPI Mode = 2 + { + Return (0xF) + } + Return (0x0) + } + + } // Device (RTEK) diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Bluetooth/Broadcom.asl b/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Bluetooth/Broadcom.asl new file mode 100644 index 0000000000..e81e89f0f1 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Bluetooth/Broadcom.asl @@ -0,0 +1,90 @@ +/** @file + ACPI DSDT table + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + // + // Bluetooth controller using serial interface + // + Device(BTH0) // Bluetooth for Android + { + Name (_HID, "BCM2E1A") // Vendor BRCM request to change to 2E1A for CHT, #4753211 + Method (_STA, 0x0, NotSerialized) + { + If (And(\_OSI("Android"),LNotEqual(BDID, CHRB))) + { + Return (0x0F) + } + Return(0) + } // _STA + + Method(_CRS, 0x0, NotSerialized) + { + Name(UBUF, ResourceTemplate () { + // UARTSerial Bus Connection Descriptor + UARTSerialBus(115200, // InitialBaudRate: in bits ber second + , // BitsPerByte: default to 8 bits + , // StopBits: Defaults to one bit + 0xfc, // LinesInUse: 8 1-bit flags to declare line enabled + , // IsBigEndian: default to LittleEndian + , // Parity: Defaults to no parity + , // FlowControl: Defaults to no flow control + 32, // ReceiveBufferSize + 32, // TransmitBufferSize + "\\_SB.PCIO.URT1", // ResourceSource: UART bus controller name + ,) // DescriptorName: creates name for offset of resource descriptor + // Interrupt (ResourceConsumer, Edge, ActiveHigh, ExclusiveAndWake, , , ) {94} // SE60 INT Line#2, IOAPIC 94 + GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO3", ) {62} // GPIO SE62, COMBO_BT_WAKEUP + GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO3", ) {64} // GPIO SE64, COMBO_BT_RESET_N + GpioInt(Level, ActiveHigh, Exclusive, PullNone, 0, "\\_SB.GPO3", ) {60} // GPIO SE60, COMBO_UART_WAKE_R + }) + Return(UBUF) + } + } // Device BTH0 + + Device (BTH1) // Bluetooth for Windows OS + { + Name (_HID, "BCM2E64") + + Method (_STA, 0x0, NotSerialized) + { + If (Or(\_OSI("Android"),LEqual(BDID, CHRB))) + { + Return (0) + } + Return(0xF) + } // _STA + + Method(_CRS, 0x0, NotSerialized) + { + Name(BBUF, ResourceTemplate () { //For Cherrytrail CRB + // UARTSerial Bus Connection Descriptor + UARTSerialBus(115200, // InitialBaudRate: in bits ber second + , // BitsPerByte: default to 8 bits + , // StopBits: Defaults to one bit + 0xfc, // LinesInUse: 8 1-bit flags to declare line enabled + , // IsBigEndian: default to LittleEndian + , // Parity: Defaults to no parity + , // FlowControl: Defaults to no flow control + 32, // ReceiveBufferSize + 32, // TransmitBufferSize + "\\_SB.PCI0.URT1", // ResourceSource: UART bus controller name + ,) // DescriptorName: creates name for offset of resource descriptor + //Interrupt (ResourceConsumer, Edge, ActiveHigh, ExclusiveAndWake, , , ) {94} // SE60 INT Line#2, IOAPIC 94 + GpioInt(Level, ActiveLow, Exclusive, PullNone, 0, "\\_SB.GPO3", ) {60} // GPIO SE60, COMBO_UART_WAKE_R + GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO3", ) {62} // GPIO SE62, COMBO_BT_WAKEUP + GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO3", ) {64} // GPIO SE64, COMBO_BT_RESET_N + }) + Return(BBUF) + } + } // Device BTH1 diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Camera/Camera.asl b/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Camera/Camera.asl new file mode 100644 index 0000000000..5723c62d1e --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Camera/Camera.asl @@ -0,0 +1,270 @@ +/** @file + ACPI DSDT table + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + External(\RCAM, IntObj) + + Device (CAMD) + { + Name (_ADR, Zero) // _ADR: Address + Name (_HID, "INT33F7") // _HID: Hardware ID + Name (_CID, "INT33F7") // _CID: Compatible ID + Name (_SUB, "INTL0000") // _SUB: Subsystem ID + Name (_DDN, "OV2724") // _DDN: DOS Device Name + Name (_UID, One) // _UID: Unique ID + Name (_PR0, Package (1) // _PR0: Power Resources for D0 + { + CLK0 + }) + Name (PLDB, Package (0x01) + { + Buffer (0x14) + { + /* 0000 */ 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0008 */ 0x61, 0x0C, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + /* 0010 */ 0xFF, 0xFF, 0xFF, 0xFF + } + }) + Method (_PLD, 0, Serialized) // _PLD: Physical Location of Device + { + Return (PLDB) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (LEqual (RCAM, 1)) { // CRD_B v2.1 OV5693 + OV2724 + Return (0x0F) + } + Return (0) + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (SBUF, ResourceTemplate () // I2C Resource define + { + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, + "\\_SB.GPO1", 0x00, ResourceConsumer, , + ) + { // Pin list + 0x0035 // N"53" DOVDD18 + } + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, + "\\_SB.GPO1", 0x00, ResourceConsumer, , + ) + { // Pin list + 0x002E // N"46" AVDD28 + } + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, + "\\_SB.GPO1", 0x00, ResourceConsumer, , + ) + { // Pin list + 0x0034 // N"52" RESET + } + + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, + "\\_SB.GPO1", 0x00, ResourceConsumer, , + ) + { // Pin list + 0x0030 // N"48" DVDD12 + } + I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , + ) + }) + Return (SBUF) + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + If (LEqual (Arg0, Buffer (0x10) + { + /* 0000 */ 0x6A, 0xA7, 0x7B, 0x37, 0x90, 0xF3, 0xFF, 0x4A, + /* 0008 */ 0xAB, 0x38, 0x9B, 0x1B, 0xF3, 0x3A, 0x30, 0x15 + })) + { + Return ("INT33F7") + } + + If (LEqual (Arg0, Buffer (0x10) + { + /* 0000 */ 0xAA, 0xAA, 0x62, 0x3C, 0xE0, 0xD8, 0x1A, 0x40, + /* 0008 */ 0x84, 0xC3, 0xFC, 0x05, 0x65, 0x6F, 0xA2, 0x8C + })) + { + Return ("OV2724") + } + + If (LEqual (Arg0, Buffer (0x10) + { + /* 0000 */ 0x8F, 0xCE, 0x2A, 0x82, 0x14, 0x28, 0x74, 0x41, + /* 0008 */ 0xA5, 0x6B, 0x5F, 0x02, 0x9F, 0xE0, 0x79, 0xEE + })) + { + Return ("3SF201T2") // IHV Part Numbe + } + + If (LEqual (Arg0, Buffer (0x10) + { + /* 0000 */ 0x2A, 0x51, 0x59, 0x29, 0x8C, 0x02, 0x46, 0x46, + /* 0008 */ 0xB7, 0x3D, 0x4D, 0x1B, 0x56, 0x72, 0xFA, 0xD8 + })) + { + Return ("BSW_ITL_RVP") + } + + If (LEqual (Arg0, Buffer (0x10) // mipiport + { + /* 0000 */ 0xD8, 0x7B, 0x3B, 0xEA, 0x9B, 0xE0, 0x39, 0x42, + /* 0008 */ 0xAD, 0x6E, 0xED, 0x52, 0x5F, 0x3F, 0x26, 0xAB + })) + { + If (LEqual(BDID, CRRB)) { // If it's BSW CR board + Return (0x1011) // BSW CR supports only single lane OV2724 sensor module + } + Return (0x1021) + } + + If (LEqual (Arg0, Buffer (0x10) // func + { + /* 0000 */ 0x92, 0xC4, 0x5A, 0xB6, 0x30, 0x9E, 0x60, 0x4D, + /* 0008 */ 0xB5, 0xB2, 0xF4, 0x97, 0xC7, 0x90, 0xD9, 0xCF + })) + { + Return (Zero) + } + + If (LEqual (Arg0, Buffer (0x10) // rom + { + /* 0000 */ 0x0F, 0xAB, 0x70, 0xE7, 0x44, 0x26, 0xAB, 0x4B, + /* 0008 */ 0x86, 0x28, 0xD6, 0x2F, 0x16, 0x83, 0xFB, 0x9D + })) + { + Return (Zero) + } + + If (LEqual (Arg0, Buffer (0x10) // power + { + /* 0000 */ 0xB2, 0x4A, 0xA5, 0x1E, 0x84, 0xCD, 0xCC, 0x48, + /* 0008 */ 0x9D, 0xD4, 0x7F, 0x59, 0x4E, 0xC3, 0xB0, 0x15 + })) + { + Return (0x2) + } + + If (LEqual (Arg0, Buffer (0x10) // mclk + { + /* 0000 */ 0x39, 0xA6, 0xC9, 0x75, 0x8A, 0x5C, 0x00, 0x4A, + /* 0008 */ 0x9F, 0x48, 0xA9, 0xC3, 0xB5, 0xDA, 0x78, 0x9F + })) + { + Return (Zero) + } + + // Dsm2PlatformStr + If(LEqual(Arg0, ToUUID("2FA9BB94-9C5D-4AEB-8E6E-27434F81E3D3"))) + { + Return ("BSW") + } + + // Dsm2PlatformSubStr + If(LEqual(Arg0, ToUUID("647A6CA2-8B29-49AC-8806-D58B3D2D3EF5"))) + { + Return ("FFD") + } + + // Dsm2SiliconStr + If(LEqual(Arg0, ToUUID("A6E922A1-F7B3-4399-B56A-406AE416843B"))) + { + Return ("BSW") + } + + // Dsm2PlatformStr + If(LEqual(Arg0, ToUUID("5960313B-0AB0-4940-8840-2CAFA420C015"))) + { + Return ("INTEL") + } + + // Dsm2Info + If(LEqual(Arg0, ToUUID("F486D39F-D657-484B-84A6-42A565712B92"))) + { + If (LEqual(BDID, CRRB)) { // If it's BSW CR board + Return (Buffer (32) // BSW CR supports only single lane OV2724 sensor module + { + 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x07, 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }) + } + Return (Buffer (32) + { + 0x01, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x07, 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }) + } + + If (LEqual (Arg0, Buffer (0x10) // I2C + { + /* 0000 */ 0x49, 0x75, 0x25, 0x26, 0x71, 0x92, 0xA4, 0x4C, + /* 0008 */ 0xBB, 0x43, 0xC4, 0x89, 0x9D, 0x5A, 0x48, 0x81 + })) + { + If (LEqual (Arg2, One)) // total number + { + Return (One) + } + + If (LEqual (Arg2, 0x02)) // bus4 cmos 0x10 400000 + { + Return (0x02003600) + } + } + + If (LEqual (Arg0, Buffer (0x10) // gpio + { + /* 0000 */ 0x40, 0x46, 0x23, 0x79, 0x10, 0x9E, 0xEA, 0x4F, + /* 0008 */ 0xA5, 0xC1, 0xB5, 0xAA, 0x8B, 0x19, 0x75, 0x6F + })) + { + If (LEqual (Arg2, One)) // total number + { + Return (0x04) + } + + If (LEqual (Arg2, 0x02)) + { + Return (0x01003507) // 1.8V + } + If (LEqual (Arg2, 0x03)) + { + Return (0x01002E08) // 2.8V + } + + If (LEqual (Arg2, 0x04)) + { + Return (0x01003400) // RESET + } + + If (LEqual (Arg2, 0x05)) + { + Return (0x01003001) // 1.2V + } + } + + Return (Zero) + } + } diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Camera/Camera2.asl b/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Camera/Camera2.asl new file mode 100644 index 0000000000..cc0598c1bc --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Camera/Camera2.asl @@ -0,0 +1,815 @@ +/** @file + ACPI DSDT table + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + External(\RCAM, IntObj) + + // + // Device CAM1-----Back Camera + // + Device (CAM1) + { + Name(_ADR, 0x00) + Name(_HID, "INTCF1A") + Name(_CID, "INTCF1A") + Name(_SUB, "INTL0000") + Name(_DDN, "Sony IMX175") + Name(_UID, 0x01) + + Name (_PR0, Package (1) // _PR0: Power Resources for D0 + { + CLK0 + }) + + Name (PLDB, Package(1) + { + Buffer(0x14) + { + 0x82,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00, + 0x69,0x0c,0x00,0x00, + 0x03,0x00,0x00,0x00, + 0xFF,0xFF,0xFF,0xFF + } + }) + + Method(_PLD,0,Serialized) + { + Return (PLDB) + } + + Method (_STA, 0, NotSerialized) { + If (LEqual (RCAM, 0)) { // Cynthiana_A IMX175 + OV2722 + Return (0x0F) + } + Return (0) + } + + Method (_CRS, 0x0, Serialized) + { + Name(SBUF,ResourceTemplate () + { + //GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {49} // MUX_CAM1_PWRDWN + GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {52} // CAM_1_RST_N + //GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {48} // MUX_CAM_ACT_LED + + I2CSerialBus(0x10, //SlaveAddress: bus address + , //SlaveMode: default to ControllerInitiated + 400000, //ConnectionSpeed: in Hz + , //Addressing Mode: default to 7 bit + "\\_SB.PCI0.I2C4", //ResourceSource: I2C bus controller name + , //ResourceSourceIndex: defaults to 0 + , //ResourceUsage: Defaults to ResourceConsumer + , //Descriptor Name: creates name for offset of resource descriptor + ) //VendorData + I2CSerialBus(0xC, //SlaveAddress: bus address + , //SlaveMode: default to ControllerInitiated + 400000, //ConnectionSpeed: in Hz + , //Addressing Mode: default to 7 bit + "\\_SB.PCI0.I2C4", //ResourceSource: I2C bus controller name + , //ResourceSourceIndex: defaults to 0 + , //ResourceUsage: Defaults to ResourceConsumer + , //Descriptor Name: creates name for offset of resource descriptor + ) //VendorData + I2CSerialBus(0x54, //SlaveAddress: bus address + , //SlaveMode: default to ControllerInitiated + 400000, //ConnectionSpeed: in Hz + , //Addressing Mode: default to 7 bit + "\\_SB.PCI0.I2C4", //ResourceSource: I2C bus controller name + , //ResourceSourceIndex: defaults to 0 + , //ResourceUsage: Defaults to ResourceConsumer + , //Descriptor Name: creates name for offset of resource descriptor + ) //VendorData + }) + Return (SBUF) + } + + Method(_DSM, 0x4, NotSerialized) + { + If(LEqual(Arg0, ToUUID("377BA76A-F390-4AFF-AB38-9B1BF33A3015"))) // HWID + { + Return("INTCF1A"); + } + If(LEqual(Arg0, ToUUID("3C62AAAA-D8E0-401A-84C3-FC05656FA28C"))) // Sensor CMOS Name + { + Return("IMX175") + } + If(LEqual(Arg0, ToUUID("822ACE8F-2814-4174-A56B-5F029FE079EE"))) // module name + { + Return("13P2BA807") + } + If(LEqual(Arg0, ToUUID("2959512A-028C-4646-B73D-4D1B5672FAD8"))) // Customer/platform info string + { + Return("INTEL_RVP") + } + If(LEqual(Arg0, ToUUID("918AB242-C37C-450A-9D0F-F47AB97C3DEA"))) // MIPI lanes count + { + Return(0x0104) // 4 lanes + } + If(LEqual(Arg0, ToUUID("EA3B7BD8-E09B-4239-AD6E-ED525F3F26AB"))) //MIPI Port + { + Return(0x01) // csi portx4 + } + If(LEqual(Arg0, ToUUID("B65AC492-9E30-4D60-B5B2-F497C790D9CF"))) //DIR + { + Return(0x0) // degree 0 + } + If(LEqual(Arg0, ToUUID("E770AB0F-2644-4BAB-8628-D62F1683FB9D"))) //ROM + { + Return(0x2) // eeprom + } + If(LEqual(Arg0, ToUUID("1EA54AB2-CD84-48CC-9DD4-7F594EC3B015"))) // old power option + { + Return(0x00) + } + If(LEqual(Arg0, ToUUID("8DBE2651-70C1-4C6F-AC87-A37CB46E4AF6"))) // old mclk option + { + Return(0x00) + } + If(LEqual(Arg0, ToUUID("75C9A639-5C8A-4A00-9F48-A9C3B5DA789F"))) //Reserved, default return 0x0 + { + Return(0x0) + } + If(LEqual(Arg0, ToUUID("26257549-9271-4CA4-BB43-C4899D5A4881"))) //I2c + { + if(LEqual(Arg2, 1)) // Count + { + Return(0x3); + } + if(LEqual(Arg2, 2)) // Function 1 - general + { + Return(0x04001000); + } + if(LEqual(Arg2, 3)) // Function 2 - vcm + { + Return(0x04000c01); + } + if(LEqual(Arg2, 4)) // Function 3 - eeprom + { + Return(0x04005402); + } + } + If(LEqual(Arg0, ToUUID("79234640-9E10-4FEA-A5C1-B5AA8B19756F"))) //GPIO + { + if(LEqual(Arg2, 1)) // Count + { + Return(0x1); + } + if(LEqual(Arg2, 2)) // Function 1 - RST + { + Return(0x01001800); + } + } + Return(0x00) + } + } // End CAM1 + + // + // Device CAM2---Front Camera + // + Device (CAM2) + { + Name(_ADR, 0x00) + Name(_HID, "INT33FB") + Name(_CID, "INT33FB") + Name(_SUB, "INTL0000") + Name(_DDN, "OV2722") + Name(_UID, 0x01) + Name (_PR0, Package (1) // _PR0: Power Resources for D0 + { + CLK1 + }) + + Name (PLDB, Package(1) + { + Buffer(0x14) + { + 0x82,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00, + 0x61,0x0c,0x00,0x00, + 0x03,0x00,0x00,0x00, + 0xFF,0xFF,0xFF,0xFF + } + }) + + Method(_PLD,0,Serialized) + { + Return (PLDB) + } + + Method (_STA, 0, NotSerialized) + { + If (LEqual (RCAM, 0)) { // Cynthiana_A IMX175 + OV2722 + Return (0x0F) + } + Return (0) + } + + Method (_CRS, 0x0, Serialized) + { + Name(SBUF,ResourceTemplate () + { + GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {54} //MUX_CAM2_PWRDWN + GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {50} //CAM_2_RST_N + I2CSerialBus(0x36, //SlaveAddress: bus address + , //SlaveMode: default to ControllerInitiated + 400000, //ConnectionSpeed: in Hz + , //Addressing Mode: default to 7 bit + "\\_SB.PCI0.I2C4", //ResourceSource: I2C bus controller name + , //ResourceSourceIndex: defaults to 0 + , //ResourceUsage: Defaults to ResourceConsumer + , //Descriptor Name: creates name for offset of resource descriptor + ) //VendorData + }) + Return (SBUF) + } + + Method(_DSM, 0x4, NotSerialized) + { + If(LEqual(Arg0, ToUUID("377BA76A-F390-4AFF-AB38-9B1BF33A3015"))) // HWID + { + Return("INT33FB"); + } + If(LEqual(Arg0, ToUUID("3C62AAAA-D8E0-401A-84C3-FC05656FA28C"))) // Sensor CMOS Name + { + Return("OV2722") + } + If(LEqual(Arg0, ToUUID("822ACE8F-2814-4174-A56B-5F029FE079EE"))) // module name + { + Return("12P2SF220") + } + If(LEqual(Arg0, ToUUID("2959512A-028C-4646-B73D-4D1B5672FAD8"))) // Customer/platform info string + { + Return("INTEL_RVP") + } + If(LEqual(Arg0, ToUUID("918AB242-C37C-450A-9D0F-F47AB97C3DEA"))) // MIPI lanes count + { + Return(0x0101) // 1 lanes + } + If(LEqual(Arg0, ToUUID("EA3B7BD8-E09B-4239-AD6E-ED525F3F26AB"))) // MIPI Port + { + Return(0x00) // csi portx1 + } + If(LEqual(Arg0, ToUUID("B65AC492-9E30-4D60-B5B2-F497C790D9CF"))) // DIR + { + Return(0x0) // degree 0 + } + If(LEqual(Arg0, ToUUID("E770AB0F-2644-4BAB-8628-D62F1683FB9D"))) // ROM + { + Return(0x0) // none + } + If(LEqual(Arg0, ToUUID("1EA54AB2-CD84-48CC-9DD4-7F594EC3B015"))) // old power option + { + Return(0x00) + } + If(LEqual(Arg0, ToUUID("8DBE2651-70C1-4C6F-AC87-A37CB46E4AF6"))) // old mclk option + { + Return(0x01) + } + If(LEqual(Arg0, ToUUID("75C9A639-5C8A-4A00-9F48-A9C3B5DA789F"))) // Reserved, default return 0x0 + { + Return(0x0) + } + If(LEqual(Arg0, ToUUID("26257549-9271-4CA4-BB43-C4899D5A4881"))) // I2C + { + if(LEqual(Arg2, 1)) // Count + { + Return(0x1); + } + if(LEqual(Arg2, 2)) // Function 1 - general + { + Return(0x04003600); + } + } + If(LEqual(Arg0, ToUUID("79234640-9E10-4FEA-A5C1-B5AA8B19756F"))) // GPIO + { + if(LEqual(Arg2, 1)) // Count + { + Return(0x2); + } + if(LEqual(Arg2, 2)) // Function 1 - RST + { + Return(0x01001600); + } + if(LEqual(Arg2, 3)) // Function 2 - PWDN + { + Return(0x01001901); + } + } + Return(0x00) + } + } // End CAM2 + + // + // Device STRA + // + Device (STRA) + { + Name(_ADR, 0x00) + Name(_HID, "INTCF1C") + Name(_CID, "INTCF1C") + Name(_SUB, "INTL0000") + Name(_DDN, "Flash LM3554") + Name(_UID, 0x01) + //Return the PowerResource of D0 & D3, used for OS + //Name(_PR0,Package(){P28X, P18X}) + + Method (_STA, 0, NotSerialized) { + If (LEqual (RCAM, 0)) { // Flash for Cynthiana_A IMX175 + OV2722 + Return (0x0F) + } + Return (0) + } + + Method (_CRS, 0x0, Serialized) + { + Name(SBUF,ResourceTemplate () + { + GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {56} // MUX_FLASH_TRIG + GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {47} // MUX_FLASH_TORCH + GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {53} // MUX_FLASH_RESET_N + GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {46} // MUX_GP_CAMERASB02 + I2CSerialBus(0x53, //SlaveAddress: bus address + , //SlaveMode: default to ControllerInitiated + 400000, //ConnectionSpeed: in Hz + , //Addressing Mode: default to 7 bit + "\\_SB.PCI0.I2C4", //ResourceSource: I2C bus controller name + , //ResourceSourceIndex: defaults to 0 + , //ResourceUsage: Defaults to ResourceConsumer + , //Descriptor Name: creates name for offset of resource descriptor + ) //VendorData + }) + Return (SBUF) + } + + Method(_DSM, 0x4, NotSerialized) + { + If(LEqual(Arg0, ToUUID("377BA76A-F390-4AFF-AB38-9B1BF33A3015"))) //HWID + { + Return("INTCF1C"); + } + If(LEqual(Arg0, ToUUID("822ACE8F-2814-4174-A56B-5F029FE079EE"))) //module name + { + Return("LM3554") + } + If(LEqual(Arg0, ToUUID("2959512A-028C-4646-B73D-4D1B5672FAD8"))) //Customer/platform info string + { + Return("INTEL_RVP") + } + If(LEqual(Arg0, ToUUID("75C9A639-5C8A-4A00-9F48-A9C3B5DA789F"))) //Reserved, default return 0x0 + { + Return(0x0) + } + If(LEqual(Arg0, ToUUID("26257549-9271-4CA4-BB43-C4899D5A4881"))) //I2c + { + if(LEqual(Arg2, 1)) // Count + { + Return(0x1); + } + if(LEqual(Arg2, 2)) // Function 1 - general + { + Return(0x04005300); + } + } + If(LEqual(Arg0, ToUUID("79234640-9E10-4FEA-A5C1-B5AA8B19756F"))) //GPIO + { + if(LEqual(Arg2, 1)) // Count + { + Return(0x4); + } + if(LEqual(Arg2, 2)) // Function 1 - Strobe + { + Return(0x01001302); + } + if(LEqual(Arg2, 3)) // Function 2 - Torch + { + Return(0x01001403); + } + if(LEqual(Arg2, 4)) // Function 3 - Strobe + { + Return(0x01001001); + } + if(LEqual(Arg2, 5)) // Function 4 - Torch + { + Return(0x01001104); + } + } + Return(0x00) + } + } //End STRA + + // + // Device CAM3-----Rear Camera + // + Device (CAM3) + { + Name (_ADR, Zero) // _ADR: Address + Name (_HID, "INT33BE") // _HID: Hardware ID + Name (_CID, "INT33BE") // _CID: Compatible ID + Name (_SUB, "INTL0000") // _SUB: Subsystem ID + Name (_DDN, "OV5693") // _DDN: DOS Device Name + Name (_UID, One) // _UID: Unique ID + Name (_PR0, Package (1) // _PR0: Power Resources for D0 + { + CLK1 + }) + Name (PLDB, Package (0x01) + { + Buffer (0x14) + { + /* 0000 */ 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0008 */ 0x69, 0x0C, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + /* 0010 */ 0xFF, 0xFF, 0xFF, 0xFF + } + }) + Method (_PLD, 0, Serialized) // _PLD: Physical Location of Device + { + Return (PLDB) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (LEqual (RCAM, 1)) { // CRD_B v2.1 OV5693 + OV2724 + Return (0x0F) + } + Return (0) + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (SBUF, ResourceTemplate () // I2C Resource define + { + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, + "\\_SB.GPO1", 0x00, ResourceConsumer, , + ) + { // Pin list + 0x0032 // GPIO N"50" + } + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, + "\\_SB.GPO1", 0x00, ResourceConsumer, , + ) + { // Pin list + 0x0033 // GPIO dvdd12 camerasb03 N"51" + } + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, + "\\_SB.GPO1", 0x00, ResourceConsumer, , + ) + { // Pin list + 0x0038 // GPIO dvdd18 camerasb04 N"56" + } + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, + "\\_SB.GPO1", 0x00, ResourceConsumer, , + ) + { // Pin list + 0x002D // GPIO avdd28 camerasb08 N"45" + } + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, + "\\_SB.GPO1", 0x00, ResourceConsumer, , + ) + { // Pin list + 0x0031 // GPIO vcm camerasb06 N"49" + } + I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C4", + 0x00, ResourceConsumer, , + ) + I2cSerialBus (0x000C, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C4", + 0x00, ResourceConsumer, , + ) + I2cSerialBus (0x0054, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C4", + 0x00, ResourceConsumer, , + ) + }) + Return (SBUF) + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + If (LEqual (Arg0, Buffer (0x10) + { + /* 0000 */ 0x6A, 0xA7, 0x7B, 0x37, 0x90, 0xF3, 0xFF, 0x4A, + /* 0008 */ 0xAB, 0x38, 0x9B, 0x1B, 0xF3, 0x3A, 0x30, 0x15 + })) + { + Return ("INT33BE") + } + + If (LEqual (Arg0, Buffer (0x10) + { + /* 0000 */ 0xAA, 0xAA, 0x62, 0x3C, 0xE0, 0xD8, 0x1A, 0x40, + /* 0008 */ 0x84, 0xC3, 0xFC, 0x05, 0x65, 0x6F, 0xA2, 0x8C + })) + { + Return ("OV5693") + } + + If (LEqual (Arg0, Buffer (0x10) + { + /* 0000 */ 0x8F, 0xCE, 0x2A, 0x82, 0x14, 0x28, 0x74, 0x41, + /* 0008 */ 0xA5, 0x6B, 0x5F, 0x02, 0x9F, 0xE0, 0x79, 0xEE + })) + { + Return ("13P2BA540") // IHV Part Numbe + } + + If (LEqual (Arg0, Buffer (0x10) + { + /* 0000 */ 0x2A, 0x51, 0x59, 0x29, 0x8C, 0x02, 0x46, 0x46, + /* 0008 */ 0xB7, 0x3D, 0x4D, 0x1B, 0x56, 0x72, 0xFA, 0xD8 + })) + { + Return ("BSW_ITL_RVP") + } + + If (LEqual (Arg0, Buffer (0x10) + { + /* 0000 */ 0xD8, 0x7B, 0x3B, 0xEA, 0x9B, 0xE0, 0x39, 0x42, + /* 0008 */ 0xAD, 0x6E, 0xED, 0x52, 0x5F, 0x3F, 0x26, 0xAB + })) + { + Return (0x1020) + } + + If (LEqual (Arg0, Buffer (0x10) + { + /* 0000 */ 0x92, 0xC4, 0x5A, 0xB6, 0x30, 0x9E, 0x60, 0x4D, + /* 0008 */ 0xB5, 0xB2, 0xF4, 0x97, 0xC7, 0x90, 0xD9, 0xCF + })) + { + Return (Zero) + } + + If (LEqual (Arg0, Buffer (0x10) + { + /* 0000 */ 0x0F, 0xAB, 0x70, 0xE7, 0x44, 0x26, 0xAB, 0x4B, + /* 0008 */ 0x86, 0x28, 0xD6, 0x2F, 0x16, 0x83, 0xFB, 0x9D + })) + { + Return (One) + } + + If (LEqual (Arg0, Buffer (0x10) + { + /* 0000 */ 0xB2, 0x4A, 0xA5, 0x1E, 0x84, 0xCD, 0xCC, 0x48, + /* 0008 */ 0x9D, 0xD4, 0x7F, 0x59, 0x4E, 0xC3, 0xB0, 0x15 + })) + { + Return (0x2) + } + + If (LEqual (Arg0, Buffer (0x10) // mclk + { + /* 0000 */ 0x39, 0xA6, 0xC9, 0x75, 0x8A, 0x5C, 0x00, 0x4A, + /* 0008 */ 0x9F, 0x48, 0xA9, 0xC3, 0xB5, 0xDA, 0x78, 0x9F + })) + { + Return ("AD5823") + } + + //Dsm2PlatformStr + If(LEqual(Arg0, ToUUID("2FA9BB94-9C5D-4AEB-8E6E-27434F81E3D3"))) + { + Return ("BSW") + } + + //Dsm2PlatformSubStr + If(LEqual(Arg0, ToUUID("647A6CA2-8B29-49AC-8806-D58B3D2D3EF5"))) + { + Return ("FFD") + } + + //Dsm2SiliconStr + If(LEqual(Arg0, ToUUID("A6E922A1-F7B3-4399-B56A-406AE416843B"))) + { + Return ("BSW") + } + + //Dsm2PlatformStr + If(LEqual(Arg0, ToUUID("5960313B-0AB0-4940-8840-2CAFA420C015"))) + { + Return ("INTEL") + } + + //Dsm2Info + If(LEqual(Arg0, ToUUID("F486D39F-D657-484B-84A6-42A565712B92"))) + { + Return (Buffer (32) + { + 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02, 0x02, + 0x07, 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }) + } + + If (LEqual (Arg0, Buffer (0x10) // I2C + { + /* 0000 */ 0x49, 0x75, 0x25, 0x26, 0x71, 0x92, 0xA4, 0x4C, + /* 0008 */ 0xBB, 0x43, 0xC4, 0x89, 0x9D, 0x5A, 0x48, 0x81 + })) + { + If (LEqual (Arg2, One)) + { + Return (0x03) + } + + If (LEqual (Arg2, 0x02)) + { + Return (0x04001000) + } + + If (LEqual (Arg2, 0x03)) + { + Return (0x04000C01) + } + + If (LEqual (Arg2, 0x04)) + { + Return (0x04005402) + } + } + + If (LEqual (Arg0, Buffer (0x10) // GPIO + { + /* 0000 */ 0x40, 0x46, 0x23, 0x79, 0x10, 0x9E, 0xEA, 0x4F, + /* 0008 */ 0xA5, 0xC1, 0xB5, 0xAA, 0x8B, 0x19, 0x75, 0x6F + })) + { + If (LEqual (Arg2, One)) + { + Return (0x5) // total number + } + + If (LEqual (Arg2, 0x02)) + { + Return (0x01003200) // GPIO N"50" HIGH POWER EFFECITVE + } + If (LEqual (Arg2, 0x03)) + { + Return (0x01003301) // GPIO N"51" HIGH POWER 12 EFFECITVE + } + If (LEqual (Arg2, 0x04)) + { + Return (0x01003807) // GPIO N"56" HIGH POWER 18 EFFECITVE + } + If (LEqual (Arg2, 0x05)) + { + Return (0x01002D08) // GPIO N"45" HIGH POWER 28 EFFECITVE + } + If (LEqual (Arg2, 0x06)) + { + Return (0x01003109) // GPIO N"49" HIGH POWER 28 EFFECITVE + } + } + Return (Zero) + } + } + + // + // Device STRB + // + Device (STRB) + { + Name (_ADR, Zero) // _ADR: Address + Name (_HID, "INTCF1C") // _HID: Hardware ID + Name (_CID, "INTCF1C") // _CID: Compatible ID + Name (_SUB, "INTL0000") // _SUB: Subsystem ID + Name (_DDN, "Flash LM3554") // _DDN: DOS Device Name + Name (_UID, One) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (LEqual (RCAM, 1)) { // Flash for CRD_B v2.1 OV5693 + OV2724 + Return (0x0F) + } + Return (0) + } + + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + Name (SBUF, ResourceTemplate () + { + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, + "\\_SB.GPO1", 0x00, ResourceConsumer, , + ) + { // Pin list + 0x0036 + } + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, + "\\_SB.GPO1", 0x00, ResourceConsumer, , + ) + { // Pin list + 0x002F + } + + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, + "\\_SB.GPO1", 0x00, ResourceConsumer, , + ) + { // Pin list + 0x0037 //for camera led camerasb11 + } + + I2cSerialBus (0x0053, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C4", + 0x00, ResourceConsumer, , + ) + }) + Return (SBUF) + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + If (LEqual (Arg0, Buffer (0x10) + { + /* 0000 */ 0x6A, 0xA7, 0x7B, 0x37, 0x90, 0xF3, 0xFF, 0x4A, + /* 0008 */ 0xAB, 0x38, 0x9B, 0x1B, 0xF3, 0x3A, 0x30, 0x15 + })) + { + Return ("INTCF1C") + } + + If (LEqual (Arg0, Buffer (0x10) + { + /* 0000 */ 0x8F, 0xCE, 0x2A, 0x82, 0x14, 0x28, 0x74, 0x41, + /* 0008 */ 0xA5, 0x6B, 0x5F, 0x02, 0x9F, 0xE0, 0x79, 0xEE + })) + { + Return ("LM3554") + } + + If (LEqual (Arg0, Buffer (0x10) + { + /* 0000 */ 0x2A, 0x51, 0x59, 0x29, 0x8C, 0x02, 0x46, 0x46, + /* 0008 */ 0xB7, 0x3D, 0x4D, 0x1B, 0x56, 0x72, 0xFA, 0xD8 + })) + { + Return ("BSW_ITL_RVP") + } + + If (LEqual (Arg0, Buffer (0x10) + { + /* 0000 */ 0x39, 0xA6, 0xC9, 0x75, 0x8A, 0x5C, 0x00, 0x4A, + /* 0008 */ 0x9F, 0x48, 0xA9, 0xC3, 0xB5, 0xDA, 0x78, 0x9F + })) + { + Return (Zero) + } + + If (LEqual (Arg0, Buffer (0x10) + { + /* 0000 */ 0x49, 0x75, 0x25, 0x26, 0x71, 0x92, 0xA4, 0x4C, + /* 0008 */ 0xBB, 0x43, 0xC4, 0x89, 0x9D, 0x5A, 0x48, 0x81 + })) + { + If (LEqual (Arg2, One)) + { + Return (One) + } + + If (LEqual (Arg2, 0x02)) + { + Return (0x04005300) + } + } + + If (LEqual (Arg0, Buffer (0x10) + { + /* 0000 */ 0x40, 0x46, 0x23, 0x79, 0x10, 0x9E, 0xEA, 0x4F, + /* 0008 */ 0xA5, 0xC1, 0xB5, 0xAA, 0x8B, 0x19, 0x75, 0x6F + })) + { + If (LEqual (Arg2, One)) + { + Return (0x03) + } + + If (LEqual (Arg2, 0x02)) + { + Return (0x01003601) + } + + If (LEqual (Arg2, 0x03)) + { + Return (0x01002F02) + } + If (LEqual (Arg2, 0x04)) + { + Return (0x01003705) + } + } + + Return (Zero) + } + } // End STRB diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/FingerPrint/AuthenTec.asl b/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/FingerPrint/AuthenTec.asl new file mode 100644 index 0000000000..496701cfd7 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/FingerPrint/AuthenTec.asl @@ -0,0 +1,47 @@ +/** @file + ACPI DSDT table + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Device(FPNT) + { + Name(_HID, "AUTH2750") // AuthenTec AES2750 + Name(_DDN, "AuthenTec AES2750") + Method(_CRS, 0x0, NotSerialized) + { + // SpiSerial Bus Connection Descriptor + Name(UBUF, ResourceTemplate () { + SPISerialBus( + 1, // Device selection + PolarityLow, // Device selection polarity + FourWireMode, // wiremode + 8, // databit len + ControllerInitiated, // slave mode + 8000000, // Connection speed + ClockPolarityLow, // Clock polarity + ClockPhaseSecond, // clock phase + "\\_SB.PCI0.SPI1", // ResourceSource: SPI bus controller name + 0, // ResourceSourceIndex + ResourceConsumer, // Resource usage + , // DescriptorName: creates name for offset of resource descriptor + ) // Vendor Data + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {72} + //GpioInt(Edge, ActiveHigh, Exclusive, PullNone, 0, "\\_SB.GPO2", ) {1} + }) + Return (UBUF) + } + Method (_STA, 0x0, NotSerialized) + { + Return (0x0) + } + } // Device(FPNT) diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Gps/Broadcom.asl b/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Gps/Broadcom.asl new file mode 100644 index 0000000000..1896f38d97 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Gps/Broadcom.asl @@ -0,0 +1,136 @@ +/** @file + ACPI DSDT table + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Device(GPS0) // GPS for Android OS + { + Name(_HID, "BCM4752") + Name(_HRV, 0) + Name (UART, One) + Name (ENAB, Zero) + Name (HSTW, One) + + Method(_STA, 0x0, NotSerialized) + { + If (And(\_OSI("Android"),LNotEqual(BDID, CHRB))) + { + Return (0x0F) + } + Return(0) + } + + Method(_CRS, 0x0, NotSerialized) + { + // UARTSerial Bus Connection Descriptor + + Name(UBUF, ResourceTemplate () { // Resource for BSW RVP board + UARTSerialBus( + 115200, // InitialBaudRate: in bits ber second + , // BitsPerByte: default to 8 bits + , // StopBits: Defaults to one bit + 0xfc, // LinesInUse: 8 1-bit flags to declare line enabled + , // IsBigEndian: default to LittleEndian + , // Parity: Defaults to no parity + FlowControlHardware, // FlowControl: Defaults to no flow control + 32, // ReceiveBufferSize + 32, // TransmitBufferSize + "\\_SB.PCI0.URT2", // ResourceSource: UART bus controller name + ,) // DescriptorName: creates name for offset of resource descriptor + + GpioInt(Level, ActiveHigh, Exclusive, PullNone, 0, "\\_SB.GPO3", ) {7} // GPS_HOSTREQ SE07 + GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO3", ) {3} // GPS_R_WAKEUP SE03 + //GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO3", ) {6} // COMBO_GPS_RESET_N SE06 + }) + Name(RBUF, ResourceTemplate () { // Resource for BSW CR board + UARTSerialBus( + 115200, // InitialBaudRate: in bits ber second + , // BitsPerByte: default to 8 bits + , // StopBits: Defaults to one bit + 0xfc, // LinesInUse: 8 1-bit flags to declare line enabled + , // IsBigEndian: default to LittleEndian + , // Parity: Defaults to no parity + FlowControlHardware, // FlowControl: Defaults to no flow control + 32, // ReceiveBufferSize + 32, // TransmitBufferSize + "\\_SB.PCI0.URT2", // ResourceSource: UART bus controller name + ,) // DescriptorName: creates name for offset of resource descriptor + + GpioInt(Level, ActiveHigh, Exclusive, PullNone, 0, "\\_SB.GPO3", ) {7} // GPS_HOSTREQ SE07 + GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {3} // GPS_R_WAKEUP N03 + //GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {7} // COMBO_GPS_RESET_N N07 + }) + If (LEqual(BDID, CRRB)) { // If it's BSW CR board + Return (RBUF) + } + Return (UBUF) + } + } // Device GPS0 + Device(GPS1)//GPS for Windows OS. + { + Name(_HID, "BCM4752") // Vendor: test GPS device for CHT + Name(_HRV, 1) + + Method(_STA, 0x0, NotSerialized) + { + If (OR(\_OSI("Android"),LEqual(BDID, CHRB))) + { + Return (0) + } + Return(0xF) + } + + Method(_CRS, 0x0, NotSerialized) + { + // UARTSerial Bus Connection Descriptor + + Name(BBUF, ResourceTemplate () { // Resource for BSW RVP board + UARTSerialBus( + 115200, // InitialBaudRate: in bits ber second + , // BitsPerByte: default to 8 bits + , // StopBits: Defaults to one bit + 0xfc, // LinesInUse: 8 1-bit flags to declare line enabled + , // IsBigEndian: default to LittleEndian + , // Parity: Defaults to no parity + FlowControlHardware, // FlowControl: Defaults to no flow control + 32, // ReceiveBufferSize + 32, // TransmitBufferSize + "\\_SB.PCI0.URT2", // ResourceSource: UART bus controller name + ,) // DescriptorName: creates name for offset of resource descriptor + //GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO3", ) {6} // COMBO_GPS_RESET_N SE06 + //Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {62} // GPS_HOSTREQ SE07 Line1 maps to direct IRQ 62 + GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO3", ) {3} // GPS_R_WAKEUP SE03 + }) + Name(CBUF, ResourceTemplate () { // Resource for BSW CR board + UARTSerialBus( + 115200, // InitialBaudRate: in bits ber second + , // BitsPerByte: default to 8 bits + , // StopBits: Defaults to one bit + 0xfc, // LinesInUse: 8 1-bit flags to declare line enabled + , // IsBigEndian: default to LittleEndian + , // Parity: Defaults to no parity + FlowControlHardware, // FlowControl: Defaults to no flow control + 32, // ReceiveBufferSize + 32, // TransmitBufferSize + "\\_SB.PCI0.URT2", // ResourceSource: UART bus controller name + ,) // DescriptorName: creates name for offset of resource descriptor + //GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {7} // COMBO_GPS_RESET_N N07 + //Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {62} // GPS_HOSTREQ SE07 Line1 maps to direct IRQ 62 + GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {3} // GPS_R_WAKEUP N03 + }) + If (LEqual(BDID, CRRB)) { // If it's BSW CR board + Return (CBUF) + } + Return (BBUF) + } + } // Device GPS1 diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Nfc/Nxp1.asl b/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Nfc/Nxp1.asl new file mode 100644 index 0000000000..28d99341e8 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Nfc/Nxp1.asl @@ -0,0 +1,55 @@ +/** @file + ACPI DSDT table + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + External(\NFCS, IntObj) + + // + // NFC Device + // + Device (NFC1) + { + Name (_ADR, 0x00) + Name (_HID, "NXP7471") + Name (_CID, "NXP7471") + Name (_DDN, "NXP NFC" ) + Name (_UID, 0x01) + + Method (_CRS, 0, NotSerialized) { + Name(SBUF,ResourceTemplate () + { + I2CSerialBus( + 0x29, // SlaveAddress: bus address // liuzhi: for PinoleC, it's TI's fuel guage. + , // SlaveMode: default to ControllerInitiated + 400000, // ConnectionSpeed: in Hz + , // Addressing Mode: default to 7 bit + "\\_SB.PCI0.I2C7", // ResourceSource: I2C bus controller name + , // Descriptor Name: creates name for offset of resource descriptor + ) // VendorData + + GpioInt(Level, ActiveHigh, Exclusive, PullNone, 0, "\\_SB.GPO1", ) {23} // N23, NFC_HOST_INT + GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {27} // N27, NFC_RST_N + GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {16} // N16, NFC_ENABLE_N + }) + Return (SBUF) + } + Method (_STA) + { + If (And(LLessEqual(NFCS, 1),LNotEqual (BDID, CHRB))) + { + Return (0xF) + } + Return (0x0) + } + } // End Device (NFC1) diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Nfc/Nxp2.asl b/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Nfc/Nxp2.asl new file mode 100644 index 0000000000..bf0b785859 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Nfc/Nxp2.asl @@ -0,0 +1,33 @@ +/** @file + ACPI DSDT table + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + External(\NFCS, IntObj) + + Device (NFC2) + { + Name (_ADR, Zero) + Name (_HID, "NXP1002") + Name (_CID, "NXP1002") + Name (_DDN, "NXP NFC") + Name (_UID, One) + Method (_STA, 0, NotSerialized) + { + If (LEqual(NFCS, 2)) + { + Return (0xF) + } + Return (0x0) + } + } diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Rfid/Impinj.asl b/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Rfid/Impinj.asl new file mode 100644 index 0000000000..c8a0f92fc5 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Rfid/Impinj.asl @@ -0,0 +1,88 @@ +/** @file + ACPI DSDT table + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + // + // PSS Device + // + Device (IMP2) //Pss Driver I2c + { + Name (_ADR, 0) + Name (_HID, "IMPJ0002") + Name (_CID, "IMPJ0002") + Name (_UID, 0x1) + + Method(_CRS, 0x0, NotSerialized) + { + Name (SBUF, ResourceTemplate () + { + I2cSerialBus ( + 0x6F, //SlaveAddress + ControllerInitiated, //SlaveMode + 100000, //ConnectionSpeed + AddressingMode7Bit, //Addressing Mode + "\\_SB.PCI0.I2C2", //ResourceSource + 0x00, //Descriptor Name + ResourceConsumer, + , + ) + }) + Return (SBUF) + } + + Method(_STA, 0x0, NotSerialized) + { + If (And(LEqual(PSDE, 1),LNotEqual (BDID, CHRB))) { + Return(0xF) + } + Return(0) + } //_STA + } // Device (Pss Chip 1) + + // + // Pss Chip (Monza 8k Dura) + // + Device (IMP3) + { + Name (_ADR, 0) // _ADR: Address + Name (_HID, "IMPJ0003") // _HID: Hardware ID + Name (_CID, "IMPJ0003") // _CID: Compatible ID + Name (_UID, 1) // _UID: Unique ID + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (SBUF, ResourceTemplate () + { + I2cSerialBus ( + 0x6E, //SlaveAddress + ControllerInitiated, //SlaveMode + 100000, //ConnectionSpeed + AddressingMode7Bit, //Addressing Mode + "\\_SB.PCI0.I2C2", //ResourceSource + 0x00, //Descriptor Name + ResourceConsumer, + , + ) + }) + Return (SBUF) + } //_CRS + + Method(_STA, 0x0, NotSerialized) + { + If (And(LEqual(PSDE, 2),LNotEqual (BDID, CHRB))) { + Return(0xF) + } + Return(0) + } //_STA + } // End of Device IMP3 diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/SensorHub/STMicroelectronics.asl b/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/SensorHub/STMicroelectronics.asl new file mode 100644 index 0000000000..7e2e92e72c --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/SensorHub/STMicroelectronics.asl @@ -0,0 +1,87 @@ +/** @file + ACPI DSDT table + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + External(\_SB.GPO2.AVBL, IntObj) + External(CDSM, MethodObj) + External(\GBA2, IntObj) + External(\_SB.GPO2.SHD3, IntObj) + + // + // Sensor hub + // + Device(SHUB) + { + Name (_ADR, 0x0) + Name (_HID, "SMO91D0") + Name (_CID, "PNP0C50") + Name (_DDN, "STM32F103RD") + Name (_UID, 0x1) + Name (_S0W, 3) // Put device to 0=D0, 3=D3 Hot, 4=D3 Cold during S0 idle + Name (_DEP, Package() {\_SB.GPO2}) + Method (_DSM, 0x4, Serialized) { + Return (CDSM (Arg0, Arg1, Arg2, Arg3, 1)) // HID Descriptor Address = 1 (IHV Specific) + } + Method (_STA, 0x0, NotSerialized) + { + If (LEqual (BDID, CHRB)) { + Return (0x0) + } + Return (0x0F) + } + + OperationRegion (GPM2, SystemMemory, Or(\GBA2, 0x4820), 4) + Field (GPM2, DWordAcc, Lock, Preserve) { + , 1, + SHD3, 1 // [1] GPIO Tx State of GPIO E19: SENSOR_HUB_RESET + } + + Method (_PS3, 0, Serialized) { + If (\_OSI ("Android")) { + If (LEqual (\_SB.GPO2.AVBL, 1)) { + Store (0x00, \_SB.GPO2.SHD3 ) // SENSOR_HUB_RESET = 0 puts the device in reset state + } + } Else { + Store (0, ^SHD3) // SENSOR_HUB_RESET = 0 for WOS + } + } + Method (_PS0, 0, Serialized) { + If (\_OSI ("Android")) { + If (LEqual (\_SB.GPO2.AVBL, 1)) { + Store (0x01, \_SB.GPO2.SHD3 ) // SENSOR_HUB_RESET = 1 put the device to normal state + } + } Else { + Store (1, ^SHD3) // SENSOR_HUB_RESET = 1 for WOS + } + Sleep (100) + } + + Method(_CRS, 0x0, NotSerialized) + { + Name(SBUF,ResourceTemplate () { + I2CSerialBus (0x40, // SlaveAddress: bus address + , // SlaveMode: default to ControllerInitiated + 400000, // ConnectionSpeed: in Hz + , // Addressing Mode: default to 7 bit + "\\_SB.PCI0.I2C1", // ResourceSource: I2C bus controller name + , // Descriptor Name: creates name for offset of resource descriptor + ) // VendorData + //Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {67} + GpioInt(Level, ActiveLow, Exclusive, PullUp, 0, "\\_SB.GPO2", ) {22} // E22, SENSOR_HUB_INT + GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO2", ) {19} // E19, SENSOR_HUB_RESET + GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO2", ) {16} // E16, SENSOR_HUB_WAKE + }) + Return (SBUF) + } + } // Device SHUB diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/TouchPad/Atmel.asl b/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/TouchPad/Atmel.asl new file mode 100644 index 0000000000..4f2d478d43 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/TouchPad/Atmel.asl @@ -0,0 +1,160 @@ +/** @file + ACPI DSDT table + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + External(CDSM, MethodObj) + + // Common _PS3 method for I2C Panel devices + Method (TPS3, 0, Serialized) { + If (LEqual (\_SB.GPO0.AVBL, 1)) { + If (LEqual(BDID, CRRB)) { // If it's BSW CR board + Store( 0, \_SB.GPO0.TSRR ) // Reset BSW CR TOUCH + } ElseIf (LEqual(FBID, 2)) { // If it's BSW RVP FAB 2 board + Store( 0, \_SB.GPO0.TSR2 ) // Reset BSW RVP FAB 2 TOUCH + } Else { + Store( 0, \_SB.GPO0.TSRS ) // Reset BSW RVP FAB 2 TOUCH + } + } + } + + // Common _PS0 method for I2C Panel devices + Method (TPS0, 0, Serialized) { + If (LEqual (\_SB.GPO0.AVBL, 1)) { + If (LEqual(BDID, CRRB)) { // If it's BSW CR board + Store( 1, \_SB.GPO0.TSRR ) // Reset BSW CR TOUCH Done + } ElseIf (LEqual(FBID, 2)) { // If it's BSW RVP FAB 2 board + Store( 1, \_SB.GPO0.TSR2 ) // Reset BSW RVP FAB 2 TOUCH Done + } Else { + Store( 1, \_SB.GPO0.TSRS ) // Reset BSW RVP FAB 2 TOUCH Done + } + } + Sleep(100) + } + + // Common _CRS method for I2C Panel devices + // Arg0 - Panel's Slave Address + Method (TCRS, 0x1, Serialized) + { + Name (RSTL, ResourceTemplate () // Resource for BSW RVP FAB 1 2 & CR board + { + I2cSerialBus ( + 0x4A, // SlaveAddress: bus address + ControllerInitiated, // SlaveMode: Default to ControllerInitiated + 400000, // ConnectionSpeed: in Hz + AddressingMode7Bit, // Addressing Mode: default to 7 bit + "\\_SB.PCI0.I2C6", // ResourceSource: I2C bus controller name + , // ResourceSourceIndex: defaults to 0 + , // ResourceUsage: Defaults to ResourceConsumer + PI2C // Descriptor Name: creates name for offset of resource descriptor + ) // VendorData + ///Interrupt(ResourceConsumer, Level, ActiveLow, Exclusive, , ,) {59} // SW76, Line0, IRQ 59 + GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO0",,, TRST) {75} // SW75, TOUCH_RST_N + GpioInt(Level, ActiveLow, Shared, PullDefault, 0, "\\_SB.GPO0", ) {76} // SW76, TOUCH_INT_N + }) + CreateByteField (RSTL, PI2C._ADR, VAL0) // Panel's Slave Address Connection Descriptor + Store (Arg0, VAL0) // Set Panel's Slave Address from Arg0 + CreateByteField (RSTL, TRST._PIN, VAL1) // TOUCH_RST_N Connection Descriptor + If (LEqual (BDID, CRRB)) { // If it's BSW CR board + Store (75, VAL1) // SW75 to BSW CR TOUCH_RST_N + } ElseIf (LEqual (FBID, 2)) { // If it's BSW RVP FAB2 board + Store (78, VAL1) // SW78 to BSW RVP FAB2 TOUCH_RST_N + } Else { // If it's BSW RVP FAB1 board + Store (80, VAL1) // SW80 to BSW RVP FAB1 TOUCH_RST_N + } + Return (RSTL) + } + + //------------------------ + // Atmel Touch Panel using ATMEL7000 over SHARP display + // Model name currently not known + //------------------------ + Device (TSC0) + { + Name (_HID, "ATML7000") + Name (_CID, "PNP0C50") + Name (HIDA, 0x00) // HID Descriptor Address + Name (_S0W, 3) // Put device to 0=D0, 3=D3 Hot, 4=D3 Cold during S0 idle + Name (_DEP, Package () {\_SB.GPO0}) + Method (_DSM, 0x4, Serialized) { + Return (CDSM (Arg0, Arg1, Arg2, Arg3, HIDA)) + } + Method(_STA, 0, NotSerialized) { + If (LEqual (BDID, CHRB)) { + Return (0x0) + } + If (LEqual (ITSA, 0)) { // If Panel I2C Addr is AUTO + If (LEqual (BDID, CRRB)) { // If it's BSW CR board + Return (0x00) // RVP & CR Defaults are CHEMEI when AUTO + } Else { + Return (0x00) + } + } + If (LEqual (ITSA, 0x4A)) { // If Panel I2C Addr is 0x4A + Return (0x0F) + } + Return (0x00) + } + Method (_PS3, 0, Serialized) { + ^^TPS3 () + } + Method (_PS0, 0, Serialized) { + ^^TPS0 () + } + Method (_CRS, 0, NotSerialized) { + Return (^^TCRS (0x4A)) // Use I2C Slave Adress 0x4A + } + } // End Device (TSC0) + + //------------------------ + // Atmel Touch Panel using ATMEL1000 over CHEMEI INNOLUX display + // Model name is N133HSE - EA1, resolution 1920 x 1080 + //------------------------ + Device(TCS1) + { + Name (_ADR, Zero) + Name (_HID, "ATML1000") + Name (_CID, "PNP0C50") + Name (HIDA, 0x00) // HID Descriptor Address + Name (_UID, One) + Name (_S0W, 3) // Put device to 0=D0, 3=D3 Hot, 4=D3 Cold during S0 idle + Name (_DEP, Package() {\_SB.GPO0}) + Method (_DSM, 0x4, Serialized) { + Return (CDSM (Arg0, Arg1, Arg2, Arg3, HIDA)) + } + Method(_STA, 0, NotSerialized) { + If (LEqual (BDID, CHRB)) { + Return (0x0) + } + If (LEqual (ITSA, 0)) { // If Panel I2C Addr is AUTO + If (LEqual (BDID, CRRB)) { // If it's BSW CR board + Return (0x0F) // RVP & CR Defaults are CHEMEI when AUTO + } Else { + Return (0x0F) + } + } + If (LEqual (ITSA, 0x4C)) { // If Panel I2C Addr is 0x4C + Return (0x0F) + } + Return (0x00) + } + Method (_PS3, 0, Serialized) { + ^^TPS3 () + } + Method (_PS0, 0, Serialized) { + ^^TPS0 () + } + Method (_CRS, 0, NotSerialized) { + Return (^^TCRS (0x4C)) // Use I2C Slave Adress 0x4C + } + } // End Device(TSC1) diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/TouchPad/Synaptics.asl b/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/TouchPad/Synaptics.asl new file mode 100644 index 0000000000..b44049cfcf --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/TouchPad/Synaptics.asl @@ -0,0 +1,60 @@ +/** @file + ACPI DSDT table + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + External(CDSM, MethodObj) + + //------------------------ + // Synaptics Precision touchpad for CR board + //------------------------ + Device (TPDC) + { + Name (_ADR, One) + Name (_HID, "MSFT0002") + Name (_CID, "PNP0C50") + Name (_UID, One) + Name (_S0W, 3) // Required to put the device to D3 Hot during S0 idle + Method (_DSM, 0x4, Serialized) { + Return (CDSM (Arg0, Arg1, Arg2, Arg3, 0x20)) // HID Descriptor Address = 0x20 (IHV Specific) + } + + Method (_STA, 0, NotSerialized) + { + If (LEqual(BDID, CRRB)) { // If it's BSW CR board + Return (0xF) + } + Return (0) + } + + Method (_CRS, 0, Serialized) + { + Name (SBFI, ResourceTemplate () + { + I2cSerialBus ( + 0x20, //SlaveAddress: bus address + ControllerInitiated, //SlaveMode: Default to ControllerInitiated + 400000, //ConnectionSpeed: in Hz + AddressingMode7Bit, //Addressing Mode: default to 7 bit + "\\_SB.PCI0.I2C5", //ResourceSource: I2C bus controller name + , //ResourceSourceIndex: defaults to 0 + , //ResourceUsage: Defaults to ResourceConsumer + , //Descriptor Name: creates name for offset of resource descriptor + ) //VendorData + + //Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {93} // SE77, Line1, IRQ93 + GpioInt(Level, ActiveLow, Shared, PullDefault, 0,"\\_SB.GPO3",) {77} // SE77, TCH_PAD_INT_N to GPIO_ALERT + }) + Return (SBFI) + } + } // End Device (TPDC) diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/TouchPad/Synaptics2.asl b/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/TouchPad/Synaptics2.asl new file mode 100644 index 0000000000..05c43302be --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/TouchPad/Synaptics2.asl @@ -0,0 +1,60 @@ +/** @file + ACPI DSDT table + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + External(CDSM, MethodObj) + + //------------------------ + // Synaptics Precision touchpad + //------------------------ + Device (TPD1) + { + Name (_ADR, One) + Name (_HID, "MSFT0002") + Name (_CID, "PNP0C50") + Name (_UID, One) + Name (_S0W, 3) // Put device to 0=D0, 3=D3 Hot, 4=D3 Cold during S0 idle + Method (_DSM, 0x4, Serialized) { + Return (CDSM (Arg0, Arg1, Arg2, Arg3, 0x20)) // HID Descriptor Address = 0x20 (IHV Specific) + } + + Method (_STA, 0, NotSerialized) + { + If (Or(LEqual (BDID, CRRB),LEqual (BDID, CHRB))) { // If it's BSW CR/CH board + Return (0) + } + Return (0x0F) + } + + Method (_CRS, 0, Serialized) + { + Name (SBFI, ResourceTemplate () + { + I2cSerialBus ( + 0x20, // SlaveAddress: bus address + ControllerInitiated, // SlaveMode: Default to ControllerInitiated + 400000, // ConnectionSpeed: in Hz + AddressingMode7Bit, // Addressing Mode: default to 7 bit + "\\_SB.PCI0.I2C6", // ResourceSource: I2C bus controller name + , // ResourceSourceIndex: defaults to 0 + , // ResourceUsage: Defaults to ResourceConsumer + , // Descriptor Name: creates name for offset of resource descriptor + ) // VendorData + + //Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {94} // SE77, Line2, IRQ94 + GpioInt(Level, ActiveLow, Exclusive, PullNone, 0,"\\_SB.GPO3",) {77} // SE77, TCH_PAD_INT_N to GPIO_ALERT + }) + Return (SBFI) + } + } // End Device (TPD1) diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Wifi/Broadcom.asl b/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Wifi/Broadcom.asl new file mode 100644 index 0000000000..9a4f178265 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Pch/SampleDevice/Wifi/Broadcom.asl @@ -0,0 +1,164 @@ +/** @file + ACPI DSDT table + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Device (BRCM) // WIFI For Android + { + Name (_ADR, 0x01) // SlotNumber + Function + Name (_DEP, Package() {\_SB.GPO1}) + // Added here for Android Support ++ + Name (_HID, "BCM43241") // _HID: Hardware ID + Name (_CID, "BCM43241") // _CID: Compatible ID + // Added here for Android Support -- + Method(_STA, 0x0, NotSerialized) + { + If (LEqual(WIFD, 1)) + { + Return (0x0F) + } + Return(0x0) + } + + Method (_RMV, 0, NotSerialized) + { + Return (0x0) + } + + Name (_PRW, Package() {0, 0}) + Name (_S4W, 2) + Name (_S0W, 2) + + Method (_CRS, 0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + Interrupt (ResourceConsumer, Edge, ActiveHigh, ExclusiveAndWake, , , ) {53} // N21 Line#2 to IOAPIC IRQ 53 + GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullNone, 0,"\\_SB.GPO1") {21} // COMBO_WLAN_IRQ to GPIO N21 + GpioIo(Exclusive, PullNone, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {5} // COMBO_WLAN _R_EN to GPIO N5 + }) + Return (RBUF) + } + + Method (_PS3, 0, NotSerialized) + { + If(LEqual (\_SB.GPO1.AVBL, 1)) { + Store( 0x00, \_SB.GPO1.CWLE ) // COMBO_WLAN_EN = 0 put WLAN to disabled state + } + Store( 0x00, \_SB.PCI0.SDHB.PSTS) // Indicates that the device is powered off + } + Method (_PS0, 0, NotSerialized) + { + If(LEqual(\_SB.PCI0.SDHB.PSTS, 0x0)) + { + If(LEqual (\_SB.GPO1.AVBL, 1)) { + Store( 0x01, \_SB.GPO1.CWLE ) // COMBO_WLAN_EN = 1 put WLAN to enabled state + } + Store( 0x01, \_SB.PCI0.SDHB.PSTS) // Indicates that the device is powered on + } + } + + } // Device (BRCM) + Device (BRC1) // WIFI for Windows + { + Name (_ADR, 0x02) // SlotNumber + Function + Name (_DEP, Package() {\_SB.GPO1}) + Method(_STA, 0x0, NotSerialized) + { + If (LEqual(WIFD, 0)) + { + Return (0x0F) + } + Return(0) + } + Method (_RMV, 0, NotSerialized) + { + Return (0x0) + } + Name (_PRW, Package() {0, 0}) + Name (_S4W, 2) + Name (_S0W, 2) + + Method (_CRS, 0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + Interrupt (ResourceConsumer, Edge, ActiveHigh, ExclusiveAndWake, , , ) {53} // N21 Line#2 to IOAPIC IRQ 53 + //GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullNone, 0,"\\_SB.GPO1") {21} // COMBO_WLAN_IRQ to GPIO N21 + //GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {5} // COMBO_WLAN _R_EN to GPIO N5 + }) + Return (RBUF) + } + + Method (_PS3, 0, NotSerialized) + { + If(LEqual (\_SB.GPO1.AVBL, 1)) { + Store( 0x00, \_SB.GPO1.CWLE ) // COMBO_WLAN_EN = 0 put WLAN to disabled state + } + Store( 0x00, \_SB.PCI0.SDHB.PSTS) // Indicates that the device is powered off + } + Method (_PS0, 0, NotSerialized) + { + If(LEqual(\_SB.PCI0.SDHB.PSTS, 0x0)) + { + If(LEqual (\_SB.GPO1.AVBL, 1)) { + Store( 0x01, \_SB.GPO1.CWLE ) // COMBO_WLAN_EN = 1 put WLAN to enabled state + } + Store( 0x01, \_SB.PCI0.SDHB.PSTS) // Indicates that the device is powered on + } + } + } // Device (BRC1) + + + // + // Secondary Broadcom WIFI function + // + Device(BRC2) + { + Name(_ADR, 0x2) // function 2 + Name(_STA, 0xf) + // + // The device is not removable. This must be a method. + // + Method(_RMV, 0x0, NotSerialized) + { + Return(0x0) + } + + // + // Describe a vendor-defined connection between this device and the + // primary wifi device + // + + Method(_CRS) { + Name(NAM, Buffer() {"\\_SB.PCI0.SDHB.BRC1"}) + Name(SPB, Buffer() { + 0x8E, // SPB Descriptor + 0x1D, 0x00, // Length including NAM above + 0x01, // +0x00 SPB Descriptor Revision + 0x00, // +0x01 Resource Source Index + 0xc0, // +0x02 Bus type - vendor defined + 0x02, // +0x03 Consumer + controller initiated + 0x00, 0x00, // +0x04 Type specific flags + 0x01, // +0x06 Type specific revision + 0x00, 0x00 // +0x07 type specific data length + // +0x09 - 0xf bytes for NULL-terminated NAM + // Length = 0x18 + }) + + Name(END, Buffer() {0x79, 0x00}) + Concatenate(SPB, NAM, Local0) + Concatenate(Local0, END, Local1) + Return(Local1) + } + } diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Platform/Bat0Virt.asl b/ChvRefCodePkg/AcpiTablesPCAT/Platform/Bat0Virt.asl new file mode 100644 index 0000000000..5b6ce90f13 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Platform/Bat0Virt.asl @@ -0,0 +1,331 @@ +/** @file + ACPI DSDT table + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +/* Already defined in GloblNvs.asl +Scope(\) +{ + // these fields come from the Global NVS area + Field(GNVS,AnyAcc,Lock,Preserve) + { + Offset(31), + B0SC, 8, // (31) Battery 0 Stored Capacity + Offset(34), + B0SS, 8, // (34) Battery 0 Stored Status + } +} +*/ + +Method(_Q53) +{ + P8XH(0,0x53) // show query number on Port 80 + VBSE() // Virtual Battery Switch Event, remove if not needed. +} + + +// Virtual Battery Switch Event: +// This method handles the Virtual Battery switch on the CRB. +// +// Arguments: +// None +// +// Return Value: +// None +Method(VBSE,0,Serialized) // called from _Q53 +{ + // Check for Virtual Battery Mode. If the CRB is + // running on real batteries, skip this whole section. + + If(LEqual(BNUM,0)) + { + // Check that the current and NVS Power States + // are different. The 2 may be out of sync due to + // Virtual Battery hot-key support. + + If(LNotEqual(VPWR,PWRS)) + { + // Update NVS Power State. + + Store(VPWR,PWRS) + + // Perform needed ACPI Notifications. + + PNOT() + } + } +} + + +// +// called from EC.asl _Q52 method +// +// Virtual Battery Hot Keys: +// This method passes the hot key scan code to the BTTM method. +// +// Arguments: +// None +// +// Return Value: +// None +Method(VBHK,0,Serialized) +{ + // 1/! Scan Code = 0x02 + + If(LEqual(SCAN,0x02)) // Battery = 10%. + { + BTTM(10) + } + + // 2/@ Scan Code = 0x03 + + If(LEqual(SCAN,0x03)) // Battery = 20%. + { + BTTM(20) + } + + // 3/# Scan Code = 0x04 + + If(LEqual(SCAN,0x04)) // Battery = 30%. + { + BTTM(30) + } + + // 4/$ Scan Code = 0x05 + + If(LEqual(SCAN,0x05)) // Battery = 40%. + { + BTTM(40) + } + + // 5/% Scan Code = 0x06 + + If(LEqual(SCAN,0x06)) // Battery = 50%. + { + BTTM(50) + } + + // 6/^ Scan Code = 0x07 + + If(LEqual(SCAN,0x07)) // Battery = 60%. + { + BTTM(60) + } + + // 7/& Scan Code = 0x08 + + If(LEqual(SCAN,0x08)) // Battery = 70%. + { + BTTM(70) + } + + // 8/* Scan Code = 0x09 + + If(LEqual(SCAN,0x09)) // Battery = 80%. + { + BTTM(80) + } + + // 9/( Scan Code = 0x0A + + If(LEqual(SCAN,0x0A)) // Battery = 90%. + { + BTTM(90) + } + + // 0/) Scan Code = 0x0B + + If(LEqual(SCAN,0x0B)) // Battery = 100%. + { + BTTM(100) + } + + // _/- Scan Code = 0x0C + + If(LEqual(SCAN,0x0C)) // Battery = Battery - 2%. + { + If(LGreaterEqual(B0SC,2)) + { + BTTM(Subtract(B0SC,2)) + } + } + + // +/= Scan Code = 0x0D + + If(LEqual(SCAN,0x0D)) // Battery = Battery + 2%. + { + If(LLessEqual(B0SC,98)) + { + BTTM(Add(B0SC,2)) + } + } + + // F5 Scan Code = 0x3F + + If(LEqual(SCAN,0x3F)) // Virtual Power State Change. + { + // Check for Virtual Battery Mode. If the CRB is + // running on real batteries, skip this whole section. + + If(LEqual(BNUM,0)) + { + // Toggle the Virtual Power State. + Xor(PWRS,1,PWRS) + + + // Perform needed ACPI Notifications. + PNOT() + } + } +} + + +// Battery Test Method: +// This method updates the Virtual Battery percentages and +// notifies the OS of these changes. +// +// Arguments: +// Arg0: The desired Virtual Battery Percentage. +// +// Return Value: +// None + +Method(BTTM,1,Serialized) +{ + If(PWRS) + { + If(LGreaterEqual(Arg0,B0SC)) + { + Store(Arg0,B0SC) + Notify(BAT0,0x80) + } + } + Else + { + If(LLessEqual(Arg0,B0SC)) + { + Store(Arg0,B0SC) + Notify(BAT0,0x80) + } + } +} + + // Define the Virtual Battery 0 Control Method. + + Device(BAT0) + { + Name(_HID,EISAID("PNP0C0A")) + + Name(_UID,0) + + Method(_STA,0) + { + If(And(BNUM,1)) // Battery 1 present? + { + Return(0x000B) // Yes. Hide Virtual. + } + + Return(0x001F) // No. Show Virtual. + } + + Method(_BIF,0) + { + Return(Package() { + 0x00000000, // Power Unit = mWh. + 0x00002710, // 10000 mWh Design Capacity. + 0x00002710, // 10000 mWh Last Full Charge. + 0x00000001, // Secondary Battery Technology. + 0xFFFFFFFF, // Unknown Design Voltage. + 0x000003E8, // 10% Warning Level. + 0x00000190, // 4% Low Level. + 0x00000064, // 1% Granularity Level 1. + 0x00000064, // 1% Granularity Level 2. + "CRB Battery 0", + "Battery 0", + "Fake", + "-Virtual Battery 0-"}) + } + + Method(_BIX,0) + { + Name(BIXP, Package() { //Data Package for _BIX + 0x00, // Integer Revision + 0x00000000, // Power Unit 0 = mWh, 1=mAh. + 0x00002710, // Unknown Design Capacity. + 0x00002710, // Unknown Last Full Charge. + 0x00000001, // Battery Technology.(0x00 - Primary(Non-Rechargeable), 0x001 - Secondary(Rechargeable)) + 0xFFFFFFFF, // Unknown Design Voltage. + 0x000003E8, // 10% Warning Level. + 0x00000190, // 4% Low Level. + 0x100, // Cycle Count, MUST not be 0xFFFFFFFF + 0x40, // Measurement Accuracy 95% + 0x320, // Max sampling time, MSFT No specific requirement. + 0x251C, // Min sampling time, MSFT No specific requirement. + 0x00000000, // Max averaging interval, MSFT No specific requirement. + 0x00000000, // Min averaging interval, MSFT No specific requirement. + 0x00000064, // Battery capacity granularity 1 + 0x00000064, // Battery capacity granularity 2 + "CRB Battery 0", // Model number //String (ASCIIZ) + "Battery 0", //Serial Number //String (ASCIIZ) + "Fake", // Battery type //String (ASCIIZ) + "-Virtual Battery 0-" // OEM information //String (ASCIIZ) + }) + + Return (BIXP) + } + + Method(_BST,0) + { + Name(PKG0,Package() { + 0xFFFFFFFF, // Battery State. + 0xFFFFFFFF, // Battery Present Rate. + 0xFFFFFFFF, // Battery Remaining Capacity. + 0xFFFFFFFF // Battery Present Voltage. + }) + + // Virtual AC/Battery Check. + + If(PWRS) + { + // Return Charging. + + Store(2,Index(PKG0,0)) + } + Else + { + // Return Discharging. + + Store(1,Index(PKG0,0)) + } + Store(0x7FFFFFFF,Index(PKG0,1)) + Store(Multiply(B0SC,100),Index(PKG0,2)) + Return(PKG0) + } + + Method(_BTP,1) + { + // arg0 = Trip Point, sent to EC as Threshold. + // transfer input value from mWh to % + // TODO + Return() + + } + + // Return that everything runs off Battery. + + Method(_PCL,0) + { + Return(\_SB) + } + } + diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Platform/Bat1Real.asl b/ChvRefCodePkg/AcpiTablesPCAT/Platform/Bat1Real.asl new file mode 100644 index 0000000000..38590b7608 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Platform/Bat1Real.asl @@ -0,0 +1,197 @@ +/** @file + ACPI DSDT table + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +/* Already defined in GloblNvs.asl +Scope(\) +{ + // these fields come from the Global NVS area + Field(GNVS,AnyAcc,Lock,Preserve) + { + Offset(30), // Battery Support Registers: + BNUM, 8, // (30) Battery Number Present + Offset(32), + B1SC, 8, // (32) Battery 1 Stored Capacity + Offset(35), + B1SS, 8, // (35) Battery 1 Stored Status + } +} +*/ + // Define the Real Battery 1 Control Method. + + Device(BAT1) + { + Name(_HID,EISAID("PNP0C0A")) + + Name(_UID,1) + + Method(_STA,0) + { + If(And(BNUM,1)) // Battery 1 present? + { + Return(0x001F) // Yes. Show it. + } + + Return(0x000B) // No. Hide it. + } + + Method(_BIF,0) + { + Name(BPKG, Package() { + 0x00000000, // Power Unit = mWh. + 0x00002710, // 10000 mWh Design Capacity. + 0x00002710, // 10000 mWh Last Full Charge. + 0x00000001, // Secondary Battery Technology. + 0xFFFFFFFF, // Unknown Design Voltage. + 0x000003E8, // 10% Warning Level. + 0x00000190, // 4% Low Level. + 0x00000064, // 1% Granularity Level 1. + 0x00000064, // 1% Granularity Level 2. + "CRB Battery 1", + "Battery 1", + "Real", + "-Real Battery 1-" + }) + + // Fix up the design capacity + If (ECON) + { + Store(Multiply(\_SB.PCI0.LPCB.H_EC.B1DC,10), Index(BPKG,1)) + + // Fix up the full charge capacity + Store(Multiply(\_SB.PCI0.LPCB.H_EC.B1FC,10) , Index(BPKG,2)) + + // Fix up the design voltage + Store(\_SB.PCI0.LPCB.H_EC.B1FV, Index(BPKG,4)) + + + If(\_SB.PCI0.LPCB.H_EC.B1FC) + { + Store(Divide(Multiply(\_SB.PCI0.LPCB.H_EC.B1FC, 10),10), Index(BPKG,5)) + Store(Divide(Multiply(\_SB.PCI0.LPCB.H_EC.B1FC, 10),25), Index(BPKG,6)) + Store(Divide(Multiply(\_SB.PCI0.LPCB.H_EC.B1DC, 10),100), Index(BPKG,7)) + } + } + + Return (BPKG) + } + + Method(_BIX,0) + { + Name(BIXP, Package() { //Data Package for _BIX + 0x00, // Integer Revision + 0x00000000, // Power Unit 0 = mWh, 1=mAh. + 0xFFFFFFFF, // Unknown Design Capacity. + 0xFFFFFFFF, // Unknown Last Full Charge. + 0x00000001, // Battery Technology.(0x00 - Primary(Non-Rechargeable), 0x001 - Secondary(Rechargeable)) + 0xFFFFFFFF, // Unknown Design Voltage. + 0x00000000, // 10% Warning Level. + 0x00000000, // 4% Low Level. + 0xFFFFFFFF, // Cycle Count, MUST not be 0xFFFFFFFF + 0xFFFFFFFF, // Measurement Accuracy 95% + 0xFFFFFFFF, // Max sampling time, MSFT No specific requirement. + 0xFFFFFFFF, // Min sampling time, MSFT No specific requirement. + 0x00000000, // Max averaging interval, MSFT No specific requirement. + 0x00000000, // Min averaging interval, MSFT No specific requirement. + 0x00000001, // Battery capacity granularity 1 + 0x00000001, // Battery capacity granularity 2 + "Harris Beach", // Model number //String (ASCIIZ) + "123456789", //Serial Number //String (ASCIIZ) + "LION", // Battery type //String (ASCIIZ) + "Intel SR 1" // OEM information //String (ASCIIZ) + }) + + Store(Multiply(\_SB.PCI0.LPCB.H_EC.B1DC,10), Index(BIXP,2)) + + // Fix up the full charge capacity + Store(Multiply(\_SB.PCI0.LPCB.H_EC.B1FC,10) , Index(BIXP,3)) + + // Fix up the design voltage + Store(\_SB.PCI0.LPCB.H_EC.B1FV, Index(BIXP,5)) + + + If(\_SB.PCI0.LPCB.H_EC.B1FC) + { + Store(Divide(Multiply(\_SB.PCI0.LPCB.H_EC.B1FC, 10),10), Index(BIXP,6)) + Store(Divide(Multiply(\_SB.PCI0.LPCB.H_EC.B1FC, 10),25), Index(BIXP,7)) + Store(Divide(Multiply(\_SB.PCI0.LPCB.H_EC.B1DC, 10),100), Index(BIXP,8)) + //Store(0x100, Index(BIXP,8)) + Store(0x40, Index(BIXP,9)) + Store(0x320, Index(BIXP,10)) + Store(0x251C, Index(BIXP,11)) + } + + Return (BIXP) + } + + Method(_BST,0) + { + Name(PKG1,Package() { + 0xFFFFFFFF, // Battery State. + 0xFFFFFFFF, // Battery Present Rate. (in mWh) + 0xFFFFFFFF, // Battery Remaining Capacity. (in mWh) + 0xFFFFFFFF // Battery Present Voltage. (in mV) + }) + + // Fix up the Battery Status. + Store(And(B1ST, 0x07),Index(PKG1,0)) + If(And(B1ST, 0x01)) + { + // Calculate discharge rate + // Return Rate in mW since we report _BIF data in mW + Store(Multiply(B1DI, B1FV), Local0) + Store(Divide(Local0, 1000), Local0) + Store(Local0, Index(PKG1,1)) + } + Else + { + If(And(B1ST, 0x02)) + { + // Calculate charge rate + // Return Rate in mW since we report _BIF data in mW + Store(Multiply(B1CI, B1FV), Local0) + Store(Divide(Local0, 1000), Local0) + Store(Local0, Index(PKG1,1)) + } + } + + // Calculate Remaining Capacity in mWh = + // (Remaininng Capacity (mAh) * Design Voltage (mV))/1000 + // Use Remaininng Capacity in mAh multiply with a fixed Design Voltage + // for Remaininng Capacity in mWh + Store(Multiply(\_SB.PCI0.LPCB.H_EC.B1RC,10),Index(PKG1,2)) + + // Report Battery Present Voltage (mV) + Store(B1FV, Index(PKG1,3)) + + Return(PKG1) + } + + Method(_BTP,1) + { + // arg0 = Trip Point, sent to EC as Threshold. + // transfer input value from mWh to % + // TODO + Return() + + } + + // Return that everything runs off Battery. + + Method(_PCL,0) + { + Return(\_SB) + } + } + diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Platform/Ec.asl b/ChvRefCodePkg/AcpiTablesPCAT/Platform/Ec.asl new file mode 100644 index 0000000000..073782c7aa --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Platform/Ec.asl @@ -0,0 +1,1369 @@ +/** @file + ACPI DSDT table + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +External(LLID) +External(OTGM) +External(HGAS, MethodObj) +External(CHPS, MethodObj) +External(HPFS, MethodObj) +External(HBRT, MethodObj) +External(\_SB.PCI0.B0DB.CLPO, PkgObj) + +#define POWER_BUTTON 0 +#define WINDOWS_BUTTON 1 +#define VOLUME_UP_BUTTON 2 +#define VOLUME_DOWN_BUTTON 3 +#define ROTATION_LOCK_BUTTON 4 +#define CONVERTIBLE_BUTTON 6 +#define DOCK_INDICATOR 7 + +Device (ECRD) +{ + Name (_ADR, Zero) // _ADR: Address + Name (_HID, "BSWEC001") // _HID: Hardware ID + Name (_CID, "BSWEC001") // _CID: Compatible ID + Name (_DDN, "EC Resource Controller") // _DDN: DOS Device Name + Method (_CRS, 0x0, Serialized) // _CRS: Current Resource Settings + { + Name (SBUF, ResourceTemplate () + { + GpioInt (Edge, ActiveLow, Exclusive, PullDefault, 0x1770, + "\\_SB.GPO0", 0x00, ResourceConsumer, , + ) + { // Pin list + 0x0000 + } + }) + Return (SBUF) + } + Method (_STA, 0x0, NotSerialized) + { + If (LEqual(OSID, 1)) + { + Return (0xF) + } + Return (0x0) + } +} + +Device(H_EC) // Nuvoton Embedded Controller +{ + Name(_HID, EISAID("PNP0C09")) + + Name(_UID,1) + + Method(_CRS, 0, Serialized) + { + Name(BFFR, ResourceTemplate() + { + IO(Decode16,0x62,0x62,0,1) // DIN/DOUT + IO(Decode16,0x66,0x66,0,1) // CMD/STS + }) + + Return(BFFR) + } + + Method(_STA) + { + If(LEqual(ECSP,0)) { + Store(0,ECON) + Return(0x00) + } Else { + Store(1,ECON) + Return(0x0F) + } + } + + Name(_GPE,22) // Core GPI0_SUS6 - GPE22 - INT14 - Runtime SCI + + OperationRegion(ECF2,EmbeddedControl,0,0xFF) + Field(ECF2,ByteAcc,Lock,Preserve) + { + Offset(1), + TMPR, 8, // 1 CPU temp remote, U1H5,ADT7421, Celsius temperature + LTMP, 8, // 2 CPU temp local, U1H5,ADT7421, Celsius temperature + RPWR, 1, // 3.0 Real AC Power (AC Present = 1) + , 2, // 3.2:1 Reserved + CFAN, 1, // 3.3 CPU Fan (Fan On = 1) + , 2, // 3.5:4 Reserved + LSTE, 1, // 3.6 Lid State (Lid Open = 1) + , 1, // 3.7 Reserved + SPTR, 8, // 4 SMBus Protocol Register + SSTS, 8, // 5 SMBus Status Register + SADR, 8, // 6 SMBus Address Register + SCMD, 8, // 7 SMBus Command Register + SBFR, 256, // 8 SMBus Block Buffer + SCNT, 8, // 40 SMBus Block Count + + Offset(47), + CTMP, 8, // 47 EC Critical Temperature + , 3, // 48.2:0, Reserved + PBNS, 1, // 48.3 Power Button State (0 = Pressed) + VPWR, 1, // 48.4 Virtual AC Power (AC Present = 1) + , 3, // 48.7:5 Reserved + SCAN, 8, // 49 Hot-Key Scan Code + B1ST, 8, // 50 Battery 1 Status + B1CR, 8, // 51 Battery 1 Current Rate + B1CC, 8, // 52 Battery 1 Current Capacity + B1VT, 8, // 53 Battery 1 Voltage + B2ST, 8, // 54 Battery 2 Status + B2CR, 8, // 55 Battery 2 Current Rate + B2CC, 8, // 56 Battery 2 Current Capacity + B2VT, 8, // 57 Battery 2 Voltage + CMDR, 8, // 58, KSC command register + LUXL, 8, // 59 LUX - Low Byte + LUXH, 8, // 60 LUX - High Byte + ACH0, 8, // 61, Channel 0 RAW Value + ACH1, 8, // 62, Channel 1 RAW VAlue + + Offset(65), + FNSL, 8, // 65 bitwise PWM port select (0-7), BIT0 is set for the CPU Fan + + Offset(68), + FDCY, 8, // 68 final PWM value, output duty cycle %, range from 1 to 100 + + Offset(80), + ART1, 8, // 80, Ambient temp remote 1, U3A1, ADT7481 + + Offset(82), // 82-85 DPTF fields + TSI, 4, // Hysteresis selection is global and meant for all four sensors. + // ADT7421Remote 0 ACPIRemoteTemp[1] + // ADT7421Local 1 ACPILocalTemp[2] + // ADT7481Remote 2 NBAmbientTemp[80/50] + // ADT7481Local 3 NBAmbientTempLocal[186/BA] + // ADT7481Remote2 4 NBAmbientTempRemote2[187/BB] + // ADM1032Remote 5 ACPIOBDIMM0Temp[126/7E] + // ADM1032Local 6 ACPIOBDIMM0TempLocal[185/B9] + HYST, 4, // 82.4-7 Hysteresis in deg C + TSHT, 8, // 83 Thermal Sensor (N) high trip point + TSLT, 8, // 84 Thermal Sensor (N) low trip point + TSSR, 8, // 85 TSSR- thermal sensor status register: + // TSSR bits defined: + // BIT0- ADT7421Remote + // BIT1- ADT7421Local 1 + // BIT2- ADT7481Remote + // BIT3- ADT7481Local 3 + // BIT4- ADT7481Remote2 4 + // BIT5- ADM1032Remote 5 + // BIT6- ADM1032Local 6 + + Offset(86), + B1CM, 8, // 86 Battery 1 Command (Place holder for now) + B1DC, 16, // 87 Battery 1 Design Capacity (mWh) + B1RC, 16, // 89 Battery 1 Remaining Capacity (mWh) + B1FC, 16, // 91 Battery 1 Full Charge Capacity (mWh) + B1FV, 16, // 93 Battery 1 Full Resolution Voltage (mV) + B1DI, 16, // 95 Battery 1 Full Resolution Discharge Current (mA) + B1CI, 16, // 97 Battery 1 Full Resolution Charge Current (mA) + Offset(115), + CFSP, 16, // 115 CPU Fan speed in rpm + Offset(120), + , 1, + PB10, 1, //120.1 10s power button enable bit(0=4s, 1=10s) + Offset(126), + DM0T, 8, // 126 DDR3 On-board TS temp remote, U2F1,ADM1032 + + Offset(177), + ISTS, 8, // 177 ISCT Status (Reserved for BIOS update) + IWRS, 8, // 178 ISCT Wake Reason (Reserved for BIOS update) + S3T0, 8, // 179 ISCT S3 Time-Out value Bit 7-0 + S3T1, 8, // 180 ISCT S3 Time-Out value Bit 15-8 + S3T2, 8, // 181 ISCT S3 Time-Out value Bit 23-16 + S0IS, 8, // 182 S0-ISCT Status, bit 0 -> S0-ISCT Mode (1 - S0-ISCT Enable Mode; 0 = S0-ISCT Disable mode) + // bit 1 -> AC Status (1 - On AC, 0 - On Battery); bit 2- 7 -> Reserved + S3WR, 8, // 183 Get Platform Wake Reason (Provided by EC) + IPNC, 8, // 184 ISCT Power Enable to Network Card + // 184.0 Reserved, Always 0 + // 184.1 WLAN module powered in S3 (0=Disabled, 1=Enabled) + // 184.2 WLAN module powered in S4 (0=Disabled, 1=Enabled) + // 184.3 WLAN module powered in S5 (0=Disabled, 1=Enabled) + // 184.4 WWAN module powered in S3 (0=Disabled, 1=Enabled) + // 184.5 WWAN module powered in S4 (0=Disabled, 1=Enabled) + // 184.6 WWAN module powered in S5 (0=Disabled, 1=Enabled) + // 184.7 Reserved + + Offset(185), + D0TL, 8, // 185 DDR3 local temp, U2F1,ADM1032 + ALT1, 8, // 186 Ambient local temp, U3A1,ADT7481 + ART2, 8, // 187 Ambient temp remote 2, U3A1,ADT7481 + + Offset(190), + B1DV, 16, // 190 Battery 1 Design Voltage (mV) + + Offset(194), + B1ML, 8, // 194 BattAPmaxL - Battery Pack A maximum low byte + B1MH, 8, // 195 BattAPmaxH - Battery Pack A maximum high byte + + Offset(198), + BCC1, 16, // 198 Battery charge rate value + BTHV, 8, // 200 Battery critical threshold value + Offset(206), + BATL, 8, //206 Battery Temperature Low + BATH, 8, //207 Battery Temperature High + Offset(214), + BTPL, 8, // 214 Battery 1 Trip Point low byte + BTPH, 8, // 215 Battery 1 Trip Point high byte + Offset(217), + BCLM, 16, // 217 Battery charge limit + offset(221), + OVBS, 2, // 221.0 OTDID and VBUSSNS. + } + + // ECMD (Embedded Controller Command) + // + // Handle all commands sent to EC by BIOS + // + // Arguments: (1) + // Arg0 - EC command + // Return Value: + // 0x00 = Success + // 0xFF = Failure + // + Method(ECMD,1,Serialized) + { + If(\ECON) + { + While(\_SB.PCI0.LPCB.H_EC.CMDR){Stall(20)} + Store(Arg0, \_SB.PCI0.LPCB.H_EC.CMDR) + Return (0x00) + } Else { + Return (0xFF) + } + } + +// Include("SystemAgent/Als.asl") //will be enabled later + + // Virtual battery code + // + Include("Platform/Bat0Virt.asl") + + // Real battery code + // + Include("Platform/Bat1Real.asl") + + // The _REG Method is needed because communication with the EC + // before the driver is loaded is prohibited in WIN2000/WINXP. + + Name( IGDF, 0 ) // Internal graphics display flag, set externally if display is IGD + + Method(_REG, 2 ) + { + If(LAnd(LEqual(Arg0,3),LEqual(Arg1,1))) + { + // Must be running NT 5.0 OS. + + If(LEqual(ECSP,0)) + { + Store(0,ECON) + } + Else + { + Store(1,ECON) + } + + // Turn off the CPU Fan if Active Cooling + // is disabled. + + If(LEqual(0,ACTT)) + { + Store(0,CFAN) + } + + // Update the Ambiant Light Illuminence Values. + +// Store(LUXH,LHIH) +// Store(LUXL,LLOW) + + // Fix up the Lid State if needed. + + // Save the Lid State in global NVS and IGD OpRegion. + If (LEqual(LSTE, 0)) + { + Store(0,\_SB.PCI0.GFX0.CLID) + } + If (LEqual(LSTE, 1)) + { + Store(3,\_SB.PCI0.GFX0.CLID) + } + Store(LSTE,LIDS) + + // Unconditionally fix up the Battery and Power State. + + // Initialize the Number of Present Batteries. + // 0 = Virtual Support + // 1 = Real Battery 1 is present + + Store(0,BNUM) + Or(BNUM,ShiftRight(And(B1ST,0x08),3),BNUM) + + // Save the current Power State for later. + + // Initialize the Power State. + // BNUM = 0 = Virtual Power State + // BNUM > 0 = Real Power State + + If(LEqual(BNUM,0)) + { + Store(VPWR,PWRS) + } + Else + { + Store(RPWR,PWRS) + } + Store (5, BTHV) + ECMD (0x34) + // Perform needed ACPI Notifications. + + PNOT() + } + + // Perform OTG changes based on EC OpRegion + OTID() + VBUT() + } + + Method(_Q30) // Real Battery AC Insertion Event. + { + P8XH(0,0x30) + + // Set Global Power State = AC Mode. + + Store(1,PWRS) + + // Notify Android BSP charger driver + If (LEqual(OSID, 1)) + { + Notify(\_SB.ADP1, 0x80) + } + + + // Perform needed ACPI Notifications. + + PNOT() + } + + Method(_Q31) // Real Battery AC Removal Event. + { + P8XH(0,0x31) + + // Set Global Power State = Battery Mode. + + Store(0,PWRS) + + // Notify Android BSP charger driver + If (LEqual(OSID, 1)) + { + Notify(\_SB.ADP1, 0x80) + } + + // Perform needed ACPI Notifications. + + PNOT() + } + + Method(_Q32) // Real Battery Capacity Change. + { + P8XH(0,0x32) + + // Perform needed ACPI Notifications. + + PNOT() + } + + Method(_Q33) // Real Battery Insertion/Removal Event. + { + P8XH(0,0x33) + + // Initialize the Number of Present Batteries. + // 0 = Virtual Support + // 1 = Real Battery 1 is present + + Store(0,BNUM) + Or(BNUM,ShiftRight(And(B1ST,0x08),3),BNUM) + + // Perform needed ACPI Notifications. + + PNOT() + } + + + Method(_Q51) // Lid Switch Event. + { + P8XH(0,0x51) + + // Update Lid NVS State. + Store(LSTE,LIDS) + + Store (1, Local0) + Store (LLID, Local1) + And(LLID, 0x80, LLID) + If (LEqual(LLID, 0x80)) // resume from S3 + { + And (Local1, 0x7F, LLID) + If (LEqual(LLID, LIDS)) + { + Store (0, Local0) + } + } + If (LNotEqual(Local0, 0)) + { + \_SB.PCI0.GFX0.GLID(LIDS) + + Notify(\_SB.LID0,0x80) + } + } + + Method(_Q52) // Hot-Key Event. + { + P8XH(0,0x52) + + // This event will be generated whenever a + // CRTL+ALT+SHIFT+"Next Key" is hit. This event handler + // will base code execution on the "Next Key" Scan Code + // stored in the EC Memory Space. + + P8XH(1,SCAN) + + + // "D" Scan Code = 0x20 (=Narrator settings screen) + + If(LEqual(SCAN,0x20)) + { + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + // + // Ctrl + Alt + Shift + D test emulation mode + // 1. Windows press notify 0xC2 + // 2. Volume up press notify 0xC4 + // 3. Volume up release notify 0xC5 + // 4. Windows release notify 0xC3 + // + + Sleep(1000) // 1sec delay is needed for Powerbutton and Windows Home button. + + ^VGBI.UPBT(WINDOWS_BUTTON, One) // Update VBDS + Notify(^VGBI, 0xC2) // Notify Virtual GPIO driver that Windows Home button is pressed. + + ^VGBI.UPBT(VOLUME_UP_BUTTON, One) + Notify(^VGBI, 0xC4) // Notify Virtual GPIO driver that Vol up button is pressed. + + ^VGBI.UPBT(VOLUME_UP_BUTTON, Zero) + Notify(^VGBI, 0xC5) // Notify Virtual GPIO driver that Vol up button is released. + + ^VGBI.UPBT(WINDOWS_BUTTON, Zero) + Notify(^VGBI, 0xC3) // Notify Virtual GPIO driver that Windows Home button is released. + } + } + + // "F" Scan Code = 0x21 (=PrintScreen/ScreenShot) + + ElseIf(LEqual(SCAN,0x21)) + { + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + // + // Ctrl + Alt + Shift + F test emulation mode + // 1. Windows press notify 0xC2 + // 2. Volume Down press notify 0xC6 + // 3. Volume Down release notify 0xC7 + // 4. Windows release notify 0xC3 + // + + Sleep(1000) // 1sec delay is needed for Powerbutton and Windows Home button. + + ^VGBI.UPBT(WINDOWS_BUTTON, One) // Update VBDS + Notify(^VGBI, 0xC2) // Notify Virtual GPIO driver that Windows Home button is pressed. + + ^VGBI.UPBT(VOLUME_DOWN_BUTTON, One) + Notify(^VGBI, 0xC6) // Notify Virtual GPIO driver that Vol down button is pressed. + + ^VGBI.UPBT(VOLUME_DOWN_BUTTON, Zero) + Notify(^VGBI, 0xC7) // Notify Virtual GPIO driver that Vol down button is released. + + ^VGBI.UPBT(WINDOWS_BUTTON, Zero) + Notify(^VGBI, 0xC3) // Notify Virtual GPIO driver that Windows Home button is released. + } + } + + + // "G" Scan Code = 0x22 (=Ctrl+Alt+Del) + + ElseIf(LEqual(SCAN,0x22)) + { + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + // + // CAS+G test emulation mode + // 1. Windows press notify 0xC2 + // 2. Powerbutton press notify 0xC0 + // 3. Powerbutton release notify 0xC1 + // 4. Windows release notify 0xC3 + // + + Sleep(1000) // 1sec delay is needed for Powerbutton and Windows Home button + + ^VGBI.UPBT(WINDOWS_BUTTON, One) + Notify(^VGBI, 0xC2) // Notify Virtual GPIO driver that Windows Home button is pressed. + + ^VGBI.UPBT(POWER_BUTTON, One) + Notify(^VGBI, 0xC0) // Notify Virtual GPIO driver that Power button is pressed. + + ^VGBI.UPBT(POWER_BUTTON, Zero) + Notify(^VGBI, 0xC1) // Notify Virtual GPIO driver that Power button is released. + + ^VGBI.UPBT(WINDOWS_BUTTON, Zero) + Notify(^VGBI, 0xC3) // Notify Virtual GPIO driver that Windows Home button is released. + } + + } + + // "H" Scan Code = 0x23 (=Windows Home) + + ElseIf(LEqual(SCAN,0x23)) + { + // Windows Button. If HID Event Driver loaded, use it. Otherwise, use GFX Driver. + + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + Sleep(1000) + + ^VGBI.UPBT(WINDOWS_BUTTON, One) + Notify(^VGBI, 0xC2) // Notify Virtual GPIO driver that Windows Home button is pressed. + + ^VGBI.UPBT(WINDOWS_BUTTON, Zero) + Notify(^VGBI, 0xC3) // Notify Virtual GPIO driver that Windows Home button is released. + } + } + + // "J" Scan Code = 0x24 (=Volume Up) + + ElseIf(LEqual(SCAN,0x24)) + { + // Volume Up. If HID Event Driver loaded, use it. Otherwise, use GFX Driver. + + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + Sleep(1000) + + ^VGBI.UPBT(VOLUME_UP_BUTTON, One) + Notify(^VGBI, 0xC4) // Notify Virtual GPIO driver that Volume UP button is pressed. + + ^VGBI.UPBT(VOLUME_UP_BUTTON, Zero) + Notify(^VGBI, 0xC5) // Notify Virtual GPIO driver that Volume UP button is released. + } + } + + // "K" Scan Code = 0x25 (Volume Down) + + ElseIf(LEqual(SCAN,0x25)) + { + // Volume Down. If HID Event Driver loaded, use it. Otherwise, use GFX Driver. + + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + Sleep(1000) + + ^VGBI.UPBT(VOLUME_DOWN_BUTTON, One) + Notify(^VGBI, 0xC6) // Notify Virtual GPIO driver that Volue Down button is pressed. + + ^VGBI.UPBT(VOLUME_DOWN_BUTTON, Zero) + Notify(^VGBI, 0xC7) // Notify Virtual GPIO driver that Volue Down button is released. + } + } + + // "L" Scan Code = 0x26 (Rotation Lock) + + ElseIf(LEqual(SCAN,0x26)) + { + // Rotation Lock. If HID Event Driver loaded, use it. Otherwise, use GFX Driver. + + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + Sleep(1000) + + ^VGBI.UPBT(ROTATION_LOCK_BUTTON, One) + Notify(^VGBI, 0xC8) // Notify Virtual GPIO driver that Rotation Lock button is pressed. + + ^VGBI.UPBT(ROTATION_LOCK_BUTTON, Zero) + Notify(^VGBI, 0xC9) // Notify Virtual GPIO driver that Rotation Lock button is released. + } + } + + + // ":;" Scan Code = 0x27 (switch Slate/Clamshell mode) + + ElseIf(LEqual(SCAN,0x27)) + { + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + Sleep(1000) + + If(And(PB1E, 0x08)) // Slave/Laptop Mode changed 0 -> 1 Laptop mode + { + P8XH(0,0x1) + ^VGBI.UPBT(CONVERTIBLE_BUTTON, Zero) + Notify(^VGBI, 0xCC) // Notify Virtual GPIO driver that the system is now in Laptop mode. + } + Else + { // Slave/Laptop Mode Changed 1 -> 0 Slate/Tablet Mode + P8XH(0,0x0) + ^VGBI.UPBT(CONVERTIBLE_BUTTON, One) + Notify(^VGBI, 0xCD) // Notify Virtual GPIO driver that the system is now in Slate/Tablet mode. + } + Xor(PB1E, 0x08, PB1E) // Toggle Slate/Laptop Lock Status + } + + } + + // "'"" Scan Code = 0x28 (switch Dock/UnDock mode) + + ElseIf(LEqual(SCAN,0x28)) + { + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) + { + Sleep(1000) + + If(And(PB1E, 0x10)) // Dock/Undock status changed 0 -> 1 Dock mode + { + P8XH(0,0x1) + ^VGBI.UPBT(DOCK_INDICATOR, Zero) + Notify(^VGBI, 0xCB) // Notify Virtual GPIO driver that the system is now in Dock mode. + } + Else + { // Dock/Undock status Changed 1 -> 0 Undock mode + P8XH(0,0x0) + ^VGBI.UPBT(DOCK_INDICATOR, One) + Notify(^VGBI, 0xCA) // Notify Virtual GPIO driver that the system is now in Undock mode. + } + Xor(PB1E, 0x10, PB1E) // Toggle Dock/Undock Status + } + } + + + // F1 Scan Code = 0x3B + + If(LEqual(SCAN,0x3B)) // Hot Key Display Switch. + { + If(IGDS) + { + \_SB.PCI0.GFX0.GHDS(0) // GMCH SCI hotkey display switch, table index 0 + } + } + + // F2 Scan Code = 0x3C + + If(LEqual(SCAN,0x3C)) // Hot Key Display Switch. + { + If(IGDS) + { + \_SB.PCI0.GFX0.GHDS(1) // GMCH SCI hotkey display switch, table index 1 + } + } + + // F3 Scan Code = 0x3D + + If(LEqual(SCAN,0x3D)) // Hot Key Display Switch. + { + If(IGDS) + { + \_SB.PCI0.GFX0.GHDS(2) // GMCH SCI hotkey display switch, table index 2 + } + } + + // F4 Scan Code = 0x3E + + If(LEqual(SCAN,0x3E)) // Hot Key Display Switch. + { + If(IGDS) + { + \_SB.PCI0.GFX0.GHDS(3) // GMCH SCI hotkey display switch, table index 3 + } + } + + // F5 Scan Code = 0x3F + + // Virtual Battery Hot Keys(VBHK) - VBHK uses keys 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, -, + and F5. + + If(LEqual(BNUM,0)) // Check for Virtual Battery Mode before testing the hot-keys specific to Virtual Battery Support. + { + VBHK() // remove this call if no virtual battery is needed. + } + + + // F6 Scan Code = 0x40 + + If(LEqual(SCAN,0x40)) // Cycle Brightness + { + If(IGDS) + { + If(CondRefOf(HGAS)) + { + HGAS() + } + Else + { + If(And(4,DSEN)) + { + BRTN(0x85) + } + } + } + } + + // F7 Scan Code = 0x41 + + If(LEqual(SCAN,0x41)) // Zero Brightness + { + If(IGDS) + { + If(CondRefOf(CHPS)) + { + CHPS() //Display the current hybrid policy on Port 80 header + } + Else + { + If(And(4,DSEN)) + { + BRTN(0x88) + } + } + } + } + + // F8 Scan Code = 0x42 + + If(LEqual(SCAN,0x42)) // Panel Fitting Hot Key. + { + If(IGDS) + { + If(CondRefOf(HPFS)) + { + HPFS() + } + Else + { + \_SB.PCI0.GFX0.AINT(2, 0) + } + } + } + + // F9 Scan Code = 0x43 + + If(LEqual(SCAN,0x43)) // Decrease Brightness Level. + { + If(CondRefOf(HBRT)) + { + HBRT(4) + } + + If(IGDS) + { + If(And(4,DSEN)) + { + BRTN(0x87) + } + Else + { + Store(BRTL, Local0) + + // Current brightness is a percentage. + // This must be done if ALS is enabled, + // as the driver will change the + // brightness based on ambient light. + Store(\_SB.PCI0.GFX0.CBLV, BRTL) + + // 1 % will be lost in the conversion + // so need to make sure we account for it. + AND(Add(BRTL, 1),0xFE, BRTL) + + + If(LGreaterEqual(BRTL, 10)) + { + Subtract(BRTL, 10, BRTL) + } + + \_SB.PCI0.GFX0.AINT(1, BRTL) + } + } + + } + + // F10 Scan Code = 0x44 + + If(LEqual(SCAN,0x44)) // Increase Brightness Level. + { + If(CondRefOf(HBRT)) + { + HBRT(3) + } + + If(IGDS) + { + If(And(4,DSEN)) + { + BRTN(0x86) + } + Else + { + Store(BRTL, Local0) + + // Current brightness is a percentage. + // This must be done if ALS is enabled, + // as the driver will change the + // brightness based on ambient light. + Store(\_SB.PCI0.GFX0.CBLV, BRTL) + + // 1 % will be lost in the conversion + // so need to make sure we account for it. + AND(Add(BRTL, 1),0xFE, BRTL) + + If(LLessEqual(BRTL, 90)) + { + Add(BRTL, 10, BRTL) + } + + \_SB.PCI0.GFX0.AINT(1, BRTL) + } + } + + } + + } // end Method(_Q52) hot key event + + +// +// Hardware Buttons. +// + Method(_Q80) // Volume Up + { + // Volume Up. + // If VirtualButton driver loaded + // use VirtualButton driver + // Else If HID Event Driver loaded + // use HID Event Driver + // Else + // use GFX Driver. + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) + { + P8XH(0,0x80) + ^VGBI.UPBT(VOLUME_UP_BUTTON, One) + Notify(^VGBI, 0xC4) // Notify Virtual GPIO driver that Volume UP button is pressed. + ^VGBI.UPBT(VOLUME_UP_BUTTON, Zero) + Notify(^VGBI, 0xC5) // Notify Virtual GPIO driver that Volume UP button is released. + } //EndIf + + //Notify Android PIND driver + If (\_OSI("Android")) + { + Notify(\_SB.PIND, 0x80) // VOL_UP event index + } + } + + Method(_Q81) // Volume Down + { + // Volume Down. + // If VirtualButton driver loaded + // use VirtualButton driver + // Else If HID Event Driver loaded + // use HID Event Driver + // Else + // use GFX Driver. + + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) + { + P8XH(0,0x81) + ^VGBI.UPBT(VOLUME_DOWN_BUTTON, One) + Notify(^VGBI, 0xC6) // Notify Virtual GPIO driver that Volue Down button is pressed. + ^VGBI.UPBT(VOLUME_DOWN_BUTTON, Zero) + Notify(^VGBI, 0xC7) // Notify Virtual GPIO driver that Volue Down button is released. + } + //Notify Android PIND driver + If (\_OSI("Android")) + { + Notify(\_SB.PIND, 0x81) // VOL_DOWN event index + } + } + + Method(_Q85) // Windows Home button + { + // Windows Home Button + // If VirtualButton driver loaded + // use VirtualButton driver + // Else If HID Event Driver loaded + // use HID Event Driver + // Else + // use GFX Driver. + + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) + { + P8XH(0,0x85) + ^VGBI.UPBT(WINDOWS_BUTTON, One) + Notify(^VGBI, 0xC2) // Notify Virtual GPIO driver that Windows Home button is pressed. + ^VGBI.UPBT(WINDOWS_BUTTON, Zero) + Notify(^VGBI, 0xC3) // Notify Virtual GPIO driver that Windows Home button is released. + } + + //Notify Android PIND driver + If (\_OSI("Android")) + { + Notify(\_SB.PIND, 0x82) // HOME_BUTTON event index + } + } + + Method(_Q86) // Power button + { + // Power button + // If VirtualButton driver loaded + // use VirtualButton driver + // Else If HID Event Driver loaded + // use HID Event Driver + // Else + // use GFX Driver. + + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) + { + P8XH(0,0x86) + ^VGBI.UPBT(POWER_BUTTON, One) + Notify(^VGBI, 0xC0) // Notify Virtual GPIO driver that Power button is pressed. + ^VGBI.UPBT(POWER_BUTTON, Zero) + Notify(^VGBI, 0xC1) // Notify Virtual GPIO driver that Power button is released. + } + } + + Method(_Q87) // Rotation Lock button + { + // Rotation Lock button + // If VirtualButton driver loaded + // use VirtualButton driver + // Else If HID Event Driver loaded + // use HID Event Driver + // Else + // use GFX Driver. + + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) + { + P8XH(0,0x87) + ^VGBI.UPBT(ROTATION_LOCK_BUTTON, One) + Notify(^VGBI, 0xC8) // Notify Virtual GPIO driver that Rotation Lock button is pressed. + ^VGBI.UPBT(ROTATION_LOCK_BUTTON, Zero) + Notify(^VGBI, 0xC9) // Notify Virtual GPIO driver that Rotation Lock button is released. + } + } + + Method(_QD5) // 10 second power button press. + { + P8XH(0,0xD5) + If(LEqual(\_SB.PWRB.PBST, 0x1)) { // Using Control Method Power Button + Notify(\_SB.PWRB, 0x80) // Send press notification to Power Button device + Store(1, \_SB.PWRB.PBLV) // Keep track of Power Button Level + } + + }// End of Method + + Method(_QD6) // 10 second power button de-press. + { + P8XH(0,0xD6) + If(LEqual(\_SB.PWRB.PBST, 0x1)) { // Using Control Method Power Button + \_SB.PWRB.PBUP() // Send release notification to Power Button device if requested + Store(0, \_SB.PWRB.PBLV) //// Keep track of Power Button Level + } + + }// End of Method + + Method(_QD7) // OTGID Toggle + { + P8XH(0,0xD7) + OTID() + }// End of Method + + + Method(_QD8) // VBUSSNS Toggle + { + P8XH(0,0xD8) + VBUT() + }// End of Method + + + Method(_QF0) // Thermal Event. + { + ADBG("_QF0 SCI") + Notify(\_TZ.TZ01,0x80) + } + + + Method(OTID,0,Serialized) + { + ADBG ( OTGM ) + If(LNotEqual(OTGM, 0)) + { + AND(\_SB.PCI0.XHC1.BAR0, 0xFFFFFFF0, Local0) + If(LAnd(LNotEqual(Local0, 0), LNotEqual(Local0, 0xFFFFFFFF))) + { + OperationRegion(XBAR, SystemMemory, Local0, 0x80E0) + Field(XBAR, DWordAcc, NoLock, Preserve) + { + Offset(0x80D8), + OTGR, 32, // OTG MUX to set Host/Device Mode + OTGS, 32 // OTG MUX to verify complete transition + } + + OperationRegion(PBKL, SystemMemory, 0x0FED88000, 0x8000) + Field(PBKL, DWordAcc, Lock, Preserve) { + Offset(0x5400), // USB3_BP0_PWR_EN to GPIO N60: PANEL0_BKLTEN + , 1, + USBP, 1 + } + + AND(OVBS, 0x1, Local1) + If(LEqual(Local1,0x0)) // OTGID-0 Host Mode + { + AND(OTGR, 0xFEEFFFFF, OTGR) // Clear Bit 20 Host Mode and Bit 24 VBUSSNS + Store(200, Local2) // 200 * 50us = 10ms. + While( Local2 ) + { + If(And(OTGS,0x20000000)) //Activate VBUS after Host mode is set + { + Store(0,Local2) + } else { + Decrement(Local2) + } + } + Store(1,USBP) + Notify(\_SB.PCI0.UOTG, 0x80) + } + + If(LEqual(Local1,0x1)) //Cable Disconnet + { + Store(0,USBP) + AND(OTGR, 0xFEFFFFFF, OTGR) + OR(OTGR, 0x00100000, OTGR) + } + } + } + } + + Method(VBUT,0,Serialized) + { + If(LNotEqual(OTGM, 0)) + { + AND(\_SB.PCI0.XHC1.BAR0, 0xFFFFFFF0, Local0) + If(LAnd(LNotEqual(Local0, 0), LNotEqual(Local0, 0xFFFFFFFF))) + { + OperationRegion(XBAR, SystemMemory, Local0, 0x80E0) + Field(XBAR, DWordAcc, NoLock, Preserve) + { + Offset(0x80D8), + OTGR, 32, // OTG MUX to set Host/Device Mode + OTGS, 32 // OTG MUX to verify complete transition + } + + OperationRegion(PBKL, SystemMemory, 0x0FED88000, 0x8000) + Field(PBKL, DWordAcc, Lock, Preserve) { + Offset(0x5400), // USB3_BP0_PWR_EN to GPIO N60: PANEL0_BKLTEN + , 1, + USBP, 1 + } + + AND(OVBS, 0x1, Local1) // OTG ID + AND(OVBS, 0x2, Local2) // VBUSSNS + + If(LEqual(Local1, 0x1)) { //Cable Disconnect + If(LEqual(Local2, 0x0)) { + Store(0,USBP) + AND(OTGR, 0xFEFFFFFF, OTGR) + OR(OTGR, 0x00100000, OTGR) + Notify(\_SB.PCI0.UOTG, 0x83) + } + If(LEqual(Local2, 0x2)) { //Device Mode + Store(0,USBP) + OR(OTGR, 0x01000000, OTGR) + OR(OTGR, 0x00100000, OTGR) + Notify(\_SB.PCI0.UOTG, 0x82) + } + } + } + } + } + + // + // Hardware Button Array support + // + Device(BIND) // Button Indicators. + { + Name(_HID, "INT33D2") + Name(_CID, "PNP0C40") + + Method(_STA, 0,Serialized) + { + If(LGreaterEqual(OSYS, 2013)) + { + If(And(PB1E, 1)) // Virtual Power Button is enabled? + { + Return(0x000F) + + } + Else + { + Return(0x000B) // Not visible in UI + } + } + Return(0x00) + } + // + // _DSM : Device Specific Method for the Windows Compatible Button Array. + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision Level + // Arg2: Integer Function Index + // Arg3: Package Parameters + // + Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) + { + // Compare passed in UUID to supported UUID. + + If (LEqual(Arg0, ToUUID ("DFBCF3C5-E7A5-44E6-9C1F-29C76F6E059C"))) + { + If (LEqual(0,ToInteger(Arg1))) // Revision 0. + { + Switch (ToInteger(Arg2)) // Switch to Function Index. + { + // + // Function 0, Query of supported functions. + // + + Case (0) + { + Return (Buffer() {0x03}) + } + + // + // Function 1, Windows Compatible Button Array Power Button Properties. + // + + Case (1) + { + // Only return support if platform enabled via setup. + + If(LEqual(And(PB1E, 1), 1)) + { + Return (0x07) + } + + Return(0x00) + + } + } // End Switch statement + } // End Revision check + } // End UUID check + + // If the code falls through to this point, just return a buffer of 0. + + Return (Buffer() {0x00}) + + } // End _DSM Method + } + + Device(CIND) // Convertible Indicators. + { + Name(_HID, "INT33D3") + Name(_CID, "PNP0C60") + + Method(_STA, 0,Serialized) + { + //If(LAnd(And(IUCE,1), LGreaterEqual(OSYS, 2012))) + If(LGreaterEqual(OSYS, 2012)) + { + If(And(PB1E, 1)) // Virtual Power Button is enabled? + { + Return(0x000F) + } + } + Return(0x00) + } + } + + Device(DOCK) // docking/undocking. + { + Name(_HID, "INT33D4") + Name(_CID, "PNP0C70") // define for dock + + Method(_STA, 0,Serialized) + { + If(LGreaterEqual(OSYS, 2012)) + { + Return(0x000F) + } + Return(0x00) + } + } + + Device(VGBI) // Virtual GPIO Button "Interface." + { + + Name(_HID, EISAID("INT33D6")) // HID for Intel Virtual GPIO Button Interface. + Name(VBDS,0) + Name(ONTM,0) // Temporary variable to initialise VBDS only once in the boot + + Method(_STA,0,Serialized) + { + If(LGreaterEqual(OSYS,2013)) // Virtual Button applicable for Winblue and higher version of WinOS + { + If(And(PB1E, 1)) // Virtual Power Button is enabled? + { + Return(0x0F) // Device present,enabled and should be shown in UI. + } + } + Return(0x00) // Device NOT present + }// End of _STA + + Method(VBDL,0,Serialized) // Virtual Button Driver Load - Refer Bios Arch Spec + { + //10s power button is not supported, so simply ignore it + + // + // Here we know V-GPIO driver is loaded but 10s PB is disabled. + // Set PBST so that the default power button can handle the request. + // +// If(CondRefOf(\_SB.PWRB.PBST)) +// { +// Store(1, \_SB.PWRB.PBST) +// Notify(\_SB.PWRB, 1) // Device check +// } + } + + Method(VGBS,0,Serialized) // Virtual GPIO Button Status - Refer Bios Arch Spec + { + // Bit[7] : Docking Indicatory Status -- 0 (No Docking support on BBAY) + // Bit[6] : Convertible/Slate Indicator Status -- 0 (Slate Mode) + // Bit[5] : Reserved -- 0 + // Bit[4] : Rotation Lock Button Status + // Bit[3] : Volume Down Button Status + // Bit[2] : Volume Up Button Status + // Bit[1] : Windows Home Button Status + // Bit[0] : Power Button Status + + If(LEqual(ONTM,0)) + { + // Initial setup option on VBDS and thereafter hotkeys should be updating the VBDS + if(LEqual(And(PB1E,0x08),0x08)) // Slate/Laptop(CalmShell) + { + UPBT(CONVERTIBLE_BUTTON,One) + } + Else + { + UPBT(CONVERTIBLE_BUTTON,Zero) + } + + if(LEqual(And(PB1E,0x10),0x10)) // Undock/Dock + { + UPBT(DOCK_INDICATOR,One) + } + Else + { + UPBT(DOCK_INDICATOR,Zero) + } + Store(One,ONTM) + } + Return(VBDS) + }// End of Method + + // + // UPBT Update Button Status + // + // Arg0: Bit location of the target button + // 0: Power Button + // 1: Windows Button + // 2: Volume up Button + // 3: Volume down Button + // 4: Rotation Lock Button + // 5: Reserved + // 6: Convertible state 0 - Slate, 1 - Notebook + // 7: Dock Indicator 0 - Undock, 1 - Dock + // + // Arg1: On/Off state, 0 - Clear the target bit, 1 - Set the target bit. + // + Method(UPBT,2,Serialized) // Update Button Status + { + ShiftLeft(One, Arg0, Local0) + if(Arg1){ // Button Press/ON + Or(VBDS, Local0, VBDS) + } Else { // Button Press/OFF + And(VBDS, Not(Local0),VBDS) + } + } // End of UPBT + + } // End of VGBI + + +} // Device H_EC + +// System Bus +Scope(\_SB) +{ + // Define AC Device + Device(ADP1) + { + Name(_HID,"ACPI0003") //only one ACPI0003 is allowed in system + + Method(_STA) + { + If (LEqual(ECON,1)){ + Return(0x0F) + } + Return(0x00) + } + + // Return the value that determines if running + // from AC or not. + + Method(_PSR,0) + { + Return(PWRS) + } + + // Return that everything runs off of AC. + Method(_PCL,0) + { + Return(\_SB) + } + + } //Device(ADP1) + + + // Define a Lid Switch. + Device(LID0) + { + Name(_HID,EISAID("PNP0C0D")) + + Method(_STA) + { + If(LEqual(ECON,1)){ + Return(0x0F) + } + Return(0x00) + } + + Method(_LID,0) + { + // 0 = Closed, 1 = Open. + + Return(\_SB.PCI0.LPCB.H_EC.LSTE) + } + } + + +}//end scope _SB + + diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Platform/Gpe.asl b/ChvRefCodePkg/AcpiTablesPCAT/Platform/Gpe.asl new file mode 100644 index 0000000000..d86655c1a3 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Platform/Gpe.asl @@ -0,0 +1,229 @@ +/** @file + ACPI DSDT table + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// General Purpose Events. This Scope handles the Run-time and +// Wake-time SCIs. The specific method called will be determined by +// the _Lxx value, where xx equals the bit location in the General +// Purpose Event register(s). +External(HGLS, MethodObj) +External(HGAS, MethodObj) + +Scope(\_GPE) +{ + // + // PCI Express Hot-Plug caused the wake event. + // + Method(_L01) + { + Add(L01C,1,L01C) // Increment L01 Entry Count. + + P8XH(0,0x01) // Output information to Port 80h. + P8XH(1,L01C) + + // Check Root Port 1 for a Hot Plug Event if the Port is + // enabled. + + If(LAnd(LEqual(RP1D,0),\_SB.PCI0.RP01.HPSX)) + { + // Delay for 100ms to meet the timing requirements + // of the PCI Express Base Specification, Revision + // 1.0A, Section 6.6 ("...software must wait at + // least 100ms from the end of reset of one or more + // device before it is permitted to issue + // Configuration Requests to those devices"). + + Sleep(100) + + If(\_SB.PCI0.RP01.PDCX) + { + // Clear all status bits first. + + Store(1,\_SB.PCI0.RP01.PDCX) + Store(1,\_SB.PCI0.RP01.HPSX) + + // + // CHV BIOS Spec, Section 13.X PCI Express* Hot-Plug BIOS Support + // In addition, BIOS should intercept Presence Detect Changed interrupt, enable L0s on + // hot plug and disable L0s on hot unplug. BIOS should also make sure the L0s is + // disabled on empty slots prior booting to OS. + // + If(LNot(\_SB.PCI0.RP01.PDSX)) { + // The PCI Express slot is empty, so disable L0s on hot unplug + // + Store(0,\_SB.PCI0.RP01.L0SE) + + } + + // Perform proper notification + // to the OS. + + Notify(\_SB.PCI0.RP01,0) + } + Else + { + // False event. Clear Hot-Plug Status + // then exit. + + Store(1,\_SB.PCI0.RP01.HPSX) + } + } + + // Check Root Port 2 for a Hot Plug Event if the Port is + // enabled. + + If(LAnd(LEqual(RP2D,0),\_SB.PCI0.RP02.HPSX)) + { + Sleep(100) + + If(\_SB.PCI0.RP02.PDCX) + { + Store(1,\_SB.PCI0.RP02.PDCX) + Store(1,\_SB.PCI0.RP02.HPSX) + + If(LNot(\_SB.PCI0.RP02.PDSX)) { + Store(0,\_SB.PCI0.RP02.L0SE) + } + + Notify(\_SB.PCI0.RP02,0) + } + Else + { + Store(1,\_SB.PCI0.RP02.HPSX) + } + } + + // Check Root Port 3 for a Hot Plug Event if the Port is + // enabled. + + If(LAnd(LEqual(RP3D,0),\_SB.PCI0.RP03.HPSX)) + { + Sleep(100) + + If(\_SB.PCI0.RP03.PDCX) + { + Store(1,\_SB.PCI0.RP03.PDCX) + Store(1,\_SB.PCI0.RP03.HPSX) + + If(LNot(\_SB.PCI0.RP03.PDSX)) { + Store(0,\_SB.PCI0.RP03.L0SE) + } + + Notify(\_SB.PCI0.RP03,0) + } + Else + { + Store(1,\_SB.PCI0.RP03.HPSX) + } + } + + // Check Root Port 4 for a Hot Plug Event if the Port is + // enabled. + + If(LAnd(LEqual(RP4D,0),\_SB.PCI0.RP04.HPSX)) + { + Sleep(100) + + If(\_SB.PCI0.RP04.PDCX) + { + Store(1,\_SB.PCI0.RP04.PDCX) + Store(1,\_SB.PCI0.RP04.HPSX) + + If(LNot(\_SB.PCI0.RP04.PDSX)) { + Store(0,\_SB.PCI0.RP04.L0SE) + } + + Notify(\_SB.PCI0.RP04,0) + } + Else + { + Store(1,\_SB.PCI0.RP04.HPSX) + } + } + } + + // + // Software GPE caused the event. + // + Method(_L02) + { + // Clear the SWGPE Status Bit. + Store(0,GPEC) + + // Handle the DTS Thermal Event. + Notify(\_TZ.TZ01,0x80) + } + + // + // PUNIT SCI event. + // + Method(_L04) + { + // Clear the PUNIT Status Bit. + Store(1, PSCI) + } + + // + // IGD OpRegion SCI event (see IGD OpRegion/Software SCI BIOS SPEC). + // + Method(_L05) + { + If(LAnd(\_SB.PCI0.GFX0.GSSE, LNot(GSMI))) // Graphics software SCI event? + { + \_SB.PCI0.GFX0.GSCI() // Handle the SWSCI + } + } + + // + // This PME event (PCH's GPE #9) is received on one or more of the PCI Express* ports or + // an assert PMEGPE message received via DMI + // + Method(_L09, 0) { + // + // If the Root Port is enabled, run PCI_EXP_STS handler + // + If(LEqual(RP1D,0)) + { + \_SB.PCI0.RP01.HPME() + Notify(\_SB.PCI0.RP01, 0x02) + } + + If(LEqual(RP2D,0)) + { + \_SB.PCI0.RP02.HPME() + Notify(\_SB.PCI0.RP02, 0x02) + } + + If(LEqual(RP3D,0)) + { + \_SB.PCI0.RP03.HPME() + Notify(\_SB.PCI0.RP03, 0x02) + } + + If(LEqual(RP4D,0)) + { + \_SB.PCI0.RP04.HPME() + Notify(\_SB.PCI0.RP04, 0x02) + } + } + + // + // This PME event (PCH's GPE #13) is received when any PCH internal device with PCI Power Management capabilities + // on bus 0 asserts the equivalent of the PME# signal. + // + Method(_L0D, 0) { + Notify(\_SB.PCI0.HDEF, 0x02) + Notify(\_SB.PCI0.XHC1, 0x02) + } +} diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Platform/PciDrc.asl b/ChvRefCodePkg/AcpiTablesPCAT/Platform/PciDrc.asl new file mode 100644 index 0000000000..8db4e1b400 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Platform/PciDrc.asl @@ -0,0 +1,105 @@ +/** @file + ACPI DSDT table + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + +Scope (\_SB.PCI0) { + + Device(PDRC) // PCI Device Resource Consumption + { + Name(_HID,EISAID("PNP0C02")) + + Name(_UID,1) + + Name(BUF0,ResourceTemplate() + { + // + // PCI Express BAR _BAS and _LEN will be updated in _CRS below according to B0:D0:F0:Reg.60h + // Forced hard code at the moment. + // + //Memory32Fixed (ReadWrite, 0, 0, PCIX) // PCIEX BAR + Memory32Fixed (ReadWrite, 0x0E0000000, 0x010000000, PCIX) + + // + // MPHY BAR. Check if the hard code meets the real configuration. + // If not, dynamically update it like the _CRS method below. + // + Memory32Fixed (ReadWrite, 0x0FEA00000, 0x0100000, MPHB) // MPHY BAR + + // + // SPI BAR. Check if the hard code meets the real configuration. + // If not, dynamically update it like the _CRS method below. + // + Memory32Fixed (ReadWrite, 0x0FED01000, 0x01000,SPIB) // SPI BAR + + // + // PMC BAR. Check if the hard code meets the real configuration. + // If not, dynamically update it like the _CRS method below. + // + Memory32Fixed (ReadWrite, 0x0FED03000, 0x01000,PMCB) // PMC BAR + + // + // PUNIT BAR. Check if the hard code meets the real configuration. + // If not, dynamically update it like the _CRS method below. + // + Memory32Fixed (ReadWrite, 0x0FED06000, 0x01000, PUNB) // PUNIT BAR + + // + // ILB BAR. Check if the hard code meets the real configuration. + // If not, dynamically update it like the _CRS method below. + // + Memory32Fixed (ReadWrite, 0x0FED08000, 0x02000, ILBB) // ILB BAR + + // + // IO BAR. Check if the hard code meets the real configuration. + // If not, dynamically update it like the _CRS method below. + // + Memory32Fixed (ReadWrite, 0x0FED80000, 0x040000, IOBR) // IO BAR + + // + // RCRB BAR _BAS will be updated in _CRS below according to B0:D31:F0:Reg.F0h + // + Memory32Fixed (ReadWrite, 0x0FED1C000, 0x01000, RCRB) // RCRB BAR + + // + // Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) + // + Memory32Fixed (ReadOnly, 0x0FEE00000, 0x0100000, LIOH) + }) + + Method(_CRS,0,Serialized) + { +/* + // + // Update RCBA Base Address + // + CreateDwordField(BUF0,^RCRB._BAS,RBR0) + ShiftLeft(\_SB.PCI0.LPCB.RCBA,14,RBR0) + + // + // Update PCIEX Base Address + // + CreateDwordField(BUF0,^PCIX._BAS,XBR0) + ShiftLeft(\_SB.PCI0.PXBR,26,XBR0) + + // + // Update PCIEX Length + // + CreateDwordField(BUF0,^PCIX._LEN,XSZ0) + ShiftRight(0x10000000, \_SB.PCI0.PXSZ,XSZ0) +*/ + Return(BUF0) + } + } +} diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Platform/Platform.asl b/ChvRefCodePkg/AcpiTablesPCAT/Platform/Platform.asl new file mode 100644 index 0000000000..e9913f6ac8 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Platform/Platform.asl @@ -0,0 +1,1086 @@ +/** @file + ACPI DSDT table + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Name (PICM, 0) // Global Name, returns current Interrupt controller mode; updated from _PIC control method + +// Define the following External variables to prevent a WARNING when +// using ASL.EXE and an ERROR when using IASL.EXE. + +External(PDC0) +External(PDC1) +External(PDC2) +External(PDC3) +External(CFGD) +External(\_PR.CPU0._PPC, IntObj) +External(\_SB.PCI0.LPCB.TPM.PTS, MethodObj) +External(\_SB.TCHG, DeviceObj) + +// +// Create a Global MUTEX. +// +Mutex (MUTX, 0) + +// Define Port 80 as an ACPI Operating Region to use for debugging. Please +// note that the Intel CRBs have the ability to ouput an entire DWord to +// Port 80h for debugging purposes, so the model implemented here may not be +// able to be used on OEM Designs. + +OperationRegion (PRT0, SystemIO, 0x80, 4) +Field (PRT0, DwordAcc, Lock, Preserve) +{ + P80H, 32 +} + +// Port 80h Update: +// Update 8 bits of the 32-bit Port 80h. +// +// Arguments: +// Arg0: 0 = Write Port 80h, Bits 7:0 Only. +// 1 = Write Port 80h, Bits 15:8 Only. +// 2 = Write Port 80h, Bits 23:16 Only. +// 3 = Write Port 80h, Bits 31:24 Only. +// Arg1: 8-bit Value to write +// +// Return Value: +// None + +Method (P8XH, 2, Serialized) +{ + If (LEqual(Arg0, 0)) { // Write Port 80h, Bits 7:0. + Store (Or(And(P80D, 0xFFFFFF00), Arg1), P80D) + } ElseIf (LEqual(Arg0, 1)) { // Write Port 80h, Bits 15:8. + Store (Or (And (P80D, 0xFFFF00FF), ShiftLeft (Arg1, 8)), P80D) + } ElseIf (LEqual(Arg0, 2)) { // Write Port 80h, Bits 23:16. + Store (Or (And (P80D, 0xFF00FFFF), ShiftLeft (Arg1, 16)), P80D) + } ElseIf (LEqual(Arg0, 3)) { // Write Port 80h, Bits 31:24. + Store (Or (And (P80D, 0x00FFFFFF), ShiftLeft (Arg1, 24)), P80D) + } + + Store (P80D, P80H) +} + +// +// Define SW SMI port as an ACPI Operating Region to use for generate SW SMI. +// +OperationRegion (SPRT, SystemIO, 0xB2, 2) +Field (SPRT, ByteAcc, Lock, Preserve) { + SSMP, 8 +} + +// The _PIC Control Method is optional for ACPI design. It allows the +// OS to inform the ASL code which interrupt controller is being used, +// the 8259 or APIC. The reference code in this document will address +// PCI IRQ Routing and resource allocation for both cases. +// +// The values passed into _PIC are: +// 0 = 8259 +// 1 = IOAPIC + +Method (\_PIC, 1) +{ + Store(Arg0, GPIC) + Store(Arg0, PICM) +} + +OperationRegion(SWC0, SystemIO, 0x610, 0x0F) +Field(SWC0, ByteAcc, NoLock, Preserve) +{ + G1S, 8, //SWC GPE1_STS + Offset(0x4), + G1E, 8, + Offset(0xA), + G1S2, 8, //SWC GPE1_STS_2 + G1S3, 8 //SWC GPE1_STS_3 +} + +OperationRegion (SWC1, SystemIO, \PMBS, 0x2C) +Field(SWC1, DWordAcc, NoLock, Preserve) +{ + Offset(0x20), + G0S, 32, //GPE0_STS + Offset(0x28), + G0EN, 32 //GPE0_EN +} + +OperationRegion(SCWS, SystemMemory, Or(\GBA1, 0x200), 4) +Field(SCWS, DWordAcc, Lock, Preserve) { + , 9, + SOCW, 1 // SOC_WAKE_SCI_N Wake Status bit of GPIO N25: GPIO_SUS6 +} + +OperationRegion(TPIS, SystemMemory, Or(\GBA3, 0x204), 4) +Field(TPIS, DWordAcc, Lock, Preserve) { + , 14, + PADW, 1 // TCH_PAD_INT_N Status bit of GPIO SE77: GPIO_ALERT +} + +// +// Prepare to Sleep. The hook is called when the OS is about to +// enter a sleep state. The argument passed is the numeric value of +// the Sx state. +// +Method (_PTS, 1) +{ + Store (0, P80D) // Zero out the entire Port 80h DWord. + P8XH (0, Arg0) // Output Sleep State to Port 80h, Byte 0. + And (\XMMA, 0xFFFFFFF0, \XMIO) // Save xHCIBAR + + If (\_OSI("Android")) + { + If(LEqual(\_SB.PWRB.UPPS, 0x1)) + { + Store (0, \_SB.PCI0.LPCB.H_EC.PB10) + } + } + + + // Clear the 3 SWC status bits + Store (Ones, G1S3) + Store (Ones, G1S2) + Store (1, G1S) + + // Set SWC GPE1_EN + Store (1, G1E) + + // Clear GPE0_STS + Store (Ones, G0S) + + If (LEqual (BDID, CRRB)) { // If it's BSW CR board + // Clear SOC_WAKE_SCI_N status + Store (1, ^SOCW) + } + + // Clear TCH_PAD_INT_N status + Store (1, ^PADW) + + // + // Check whether TPM Module support is included in the project or not + // + If(CondRefOf(TCGM)) // Check if TCGM defined + { + // + // Call TPM PTS method + // + \_SB.PCI0.LPCB.TPM.PTS (Arg0) + } +} + +Name (XMIO, 0) +OperationRegion (XPEB, SystemMemory, Add (\PEBS, ShiftLeft(20, 15)), 0x78) +Field (XPEB, DWordAcc, NoLock, Preserve) { // XHCI PCIE MEM + Offset (0x04), + , 1, + XMSE, 1, + Offset (0x10), + XMMA, 32, + Offset (0x74), + XHDX, 2 +} + +/// +/// Check if PmcBase + C0h[14]set, if set write xHCIBAR + 80A4h[28] +/// WA for XHCI PME event status can't be cleared when S3 resuming +/// Arg0: Debug Port Output Byte Value if Workaround code executed +/// +Method (XWAM, 1, Serialized) +{ + If (LEqual (^XPME, 1)) { // PmcBase + C0h[14] = 1 + If (LAnd (LNotEqual (\XMIO, 0), LNotEqual (\XMIO, 0xFFFFFFF0))) { + Store (^XHDX, Local0) // Save xHCI Device State + Store (^XMMA, Local1) // Save MMIO Base Address + Store (\XMSE, Local2) // Save MMIO Sapce Enable + Store (^XMIO, ^XMMA) // Load MMIO Base Address + Store (0, ^XHDX) // xHCI Device State-> D0 + Store (1, ^XMSE) // Enable xHCI MMIO Space + OperationRegion (XWAM, SystemMemory, Add (\XMIO, 0x80A4), 0x4) + Field (XWAM, DWordAcc, NoLock, Preserve) { // xHCIBAR + , 28, + PMEC, 1 + } + Store (1, PMEC) // Clear xHCI BAR 0x80A4[28] + Store (1, \PMEB) // Clear PMEB Status + Store (Local2, ^XMSE) // Restore MMIO Eanble + Store (Local1, ^XMMA) // Restore MMIO Base + Store (Local0, ^XHDX) // Restore Device State + P8XH (1, Arg0) // Output Debug Port + } + } +} + +// Wake. This hook is called when the OS is about to wake from a +// sleep state. The argument passed is the numeric value of the +// sleep state the system is waking from. +Name (LLID, 0) +Method (_WAK, 1, Serialized) +{ + P8XH (1, 0xAB) // Beginning of _WAK. + + if (LEqual (Arg0, 3)) { + ^XWAM (0xAE) + } + + If (NEXP) + { + // Reinitialize the Native PCI Express after resume + If (And(OSCC, 0x02)) + { + \_SB.PCI0.NHPG () + } + + If (And(OSCC,0x04)) // PME control granted? + { + \_SB.PCI0.NPME () + } + } + + Return (Package () {0, 0}) +} + +/* +// Get Buffer: +// This method will take a buffer passed into the method and +// create then return a smaller buffer based on the pointer +// and size parameters passed in. +// +// Arguments: +// Arg0: Pointer to start of new Buffer in passed in Buffer. +// Arg1: Size of Buffer to create. +// Arg2: Original Buffer +// +// Return Value: +// Newly created buffer. + +Method (GETB, 3, Serialized) +{ + Multiply (Arg0, 8, Local0) // Convert Index. + Multiply (Arg1, 8, Local1) // Convert Size. + CreateField (Arg2, Local0, Local1, TBF3) // Create Buffer. + + Return (TBF3) // Return Buffer. +} +*/ +// Power Notification: +// Perform all needed OS notifications during a +// Power Switch. +// +// Arguments: +// None +// +// Return Value: +// None + +Method (PNOT, 0, Serialized) +{ + // If MP enabled and driver support is present, notify both + // processors. + + If (MPEN) + { + If (And (PDC0, 0x0008)) + { + Notify (\_PR.CPU0,0x80) // Eval CPU0 _PPC. + + If (And (PDC0, 0x0010)) + { + Sleep (100) + Notify (\_PR.CPU0, 0x81) // Eval _CST. + } + } + + If (And (PDC1, 0x0008)) + { + Notify (\_PR.CPU1, 0x80) // Eval CPU1 _PPC. + + If (And (PDC1, 0x0010)) + { + Sleep (100) + Notify (\_PR.CPU1, 0x81) // Eval _CST. + } + } + + If (And (PDC2, 0x0008)) + { + Notify (\_PR.CPU2, 0x80) // Eval CPU2 _PPC. + + If (And (PDC2, 0x0010)) + { + Sleep (100) + Notify (\_PR.CPU2, 0x81) // Eval _CST. + } + } + + If (And (PDC3, 0x0008)) + { + Notify (\_PR.CPU3, 0x80) // Eval CPU3 _PPC. + + If (And (PDC3, 0x0010)) + { + Sleep (100) + Notify (\_PR.CPU3, 0x81) // Eval _CST. + } + } + } + Else + { + Notify (\_PR.CPU0, 0x80) // Eval _PPC. + Sleep (100) + Notify (\_PR.CPU0, 0x81) // Eval _CST + } + // Update the Battery 1 Stored Capacity and Stored Status. + // Battery 0 information is always accurrate. + + If (LEqual (PFLV, FMBL)) + { + If (LNotEqual (BTSP, 0)) + { + Store (\_SB.PCI0.LPCB.H_EC.B1CC, B1SC) + Store (\_SB.PCI0.LPCB.H_EC.B1ST, B1SS) + + // Perform update to all Batteries in the System. + If (LGreaterEqual (OSYS, 2006)) // Vista and Win7 later on OS + { + Notify (\_SB.PCI0.LPCB.H_EC.BAT0, 0x81) // Eval BAT0 _BIF. + Notify (\_SB.PCI0.LPCB.H_EC.BAT1, 0x81) // Eval BAT1 _BIF. + } + Else + { + Notify (\_SB.PCI0.LPCB.H_EC.BAT0, 0x80) // Eval BAT0 _BST. + Notify (\_SB.PCI0.LPCB.H_EC.BAT1, 0x80) // Eval BAT1 _BST. + } + } + } + If (LEqual (\DPTE, 1)){ + If (LEqual (\CHGR, 1)){ + Notify (\_SB.TCHG, 0x80) // PPPC/PPDL reevaluation after AC/DC transtion has occurred. + } + } +} + +// +// System Bus +// +Scope (\_SB) +{ + + // Define a (Control Method) Power Button. + Device (PWRB) + { + Name (_HID,EISAID ("PNP0C0C")) + + // GPI13 = GPE29 = Waketime SCI. The PRW isn't working when + // placed in any of the logical locations ( PS2K, PS2M), + // so a Power Button Device was created specifically + // for the WAKETIME_SCI PRW. + + Name(_PRW, Package () {29, 4}) + + // + // Power button status flag + // + Name (PBST, 1) + + // + // Up Press Register flag. Set when OS register to recieve the up press of the power button + // + Name (UPPS, 0) + + // + // Status of Power Button Level when EC is in mode where SCI is sent for both press and release of power button + // + Name (PBLV, 0) + + Method (_STA, 0) + { + If (LAnd (LEqual (ECON, 1), PBST)){ + Return (0x0F) + } + Return (0x00) + } + + Method (PBUP, 0) { + If (UPPS) { + Notify (\_SB.PWRB, 0xC0) // Send release notification to Power Button device + } + } + + Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) { + // Compare passed in UUID to supported UUID. + If (LEqual (Arg0, ToUUID ("9C355BCB-35FA-44f7-8A67-447359C36A03"))) + { + If (LEqual (0, ToInteger (Arg1))) // Revision 0. + { + Switch (ToInteger (Arg2)) // Switch to Function Index. + { + // + // Function 0, Query of supported functions. + // + + Case (0) + { + Return (Buffer() {0x07}) // Supports Function 1,2. + } + + // + // Function 1, Windows Compatible Button Array Power Button Properties. + // + + Case (1) + { + Store (0x1, UPPS) // OS has registered to recieve notify on release of power button + // + // Place EC into mode where SCI is sent for both press and release of power button + // + \_SB.PCI0.LPCB.H_EC.ECMD (0x74) + Store (1, \_SB.PCI0.LPCB.H_EC.PB10) + Return (0x00) + + } + + // + // Function 2, Power Button Level. + // + Case (2) + { + If (UPPS) { // If OS has registered to recieve notify on release of power button + If (LNot (PBLV)) { + Return (0x00) // Power button not pressed + } Else { + Return (0x01) // Power button pressed + } + } + } + } // End Switch statement + } // End Revision check + } // End UUID check + + // + // If the code falls through to this point, just return a buffer of 0. + // + Return (Buffer() {0x00}) + } // End _DSM Method + + } + + Device (SLPB) + { + Name (_HID, EISAID ("PNP0C0E")) + } // END SLPB + + Scope (PCI0) + { + Method (_INI, 0) + { + // Determine the OS and store the value, where: + // + // OSYS = 2000 = WIN2000. + // OSYS = 2001 = WINXP, RTM or SP1. + // OSYS = 2002 = WINXP SP2. + // OSYS = 2006 = Vista. + // OSYS = 2009 = Windows 7 and Windows Server 2008 R2. + // OSYS = 2012 = Windows 8 and Windows Server 2012. + // OSYS = 2013 = Windows Blue + // OSYS = 2015 = Windows Threshold + // + // Assume Windows 2000 at a minimum. + + Store(2000, OSYS) + + // Check for a specific OS which supports _OSI. + + If (CondRefOf (\_OSI, Local0)) + { + // Linux returns _OSI = TRUE for numerous Windows + // strings so that it is fully compatible with + // BIOSes available in the market today. There are + // currently 2 known exceptions to this model: + // 1) Video Repost - Linux supports S3 without + // requireing a Driver, meaning a Video + // Repost will be required. + // 2) On-Screen Branding - a full CMT Logo + // is limited to the WIN2K and WINXP + // Operating Systems only. + + // Use OSYS for Windows Compatibility. + + If (\_OSI ("Windows 2001")) // Windows XP + { + Store (2001, OSYS) + } + + If (\_OSI ("Windows 2001 SP1")) // Windows XP SP1 + { + Store (2001, OSYS) + } + + If (\_OSI ("Windows 2001 SP2")) // Windows XP SP2 + { + Store (2002, OSYS) + } + + If (\_OSI ("Windows 2006")) // Windows Vista + { + Store (2006, OSYS) + } + + If (\_OSI ("Windows 2009")) // Windows 7 or Windows Server 2008 R2 + { + Store (2009, OSYS) + } + + If (\_OSI ("Windows 2012")) // Windows 8 or Windows Server 2012 + { + Store (2012, OSYS) + } + + If (\_OSI ("Windows 2013")) //Windows Blue + { + Store (2013, OSYS) + } + + If(\_OSI("Windows 2015")) //Windows Threshold + { + Store(2015,OSYS) + } + // + // If CMP is enabled, enable SMM C-State + // coordination. SMM C-State coordination + // will be disabled in _PDC if driver support + // for independent C-States deeper than C1 + // is indicated. + } + } + + Method (NHPG, 0, Serialized) + { + + } + + Method (NPME, 0, Serialized) + { + + } + } // end Scope (PCI0) + + Device (GPED) // virtual GPIO device for ASL based AC/Battery/Expection notification + { + Name (_ADR, 0) + Name (_HID, "INT0002") + Name (_CID, "INT0002") + Name (_DDN, "Virtual GPIO controller" ) + Name (_UID, 1) + Name (INST, One) + Name (XTMP, Zero) + + // + // Declare an op-region for accessing the PMC PME_STS register. + // L02 ASL will use these bits to identify the cause of the wake. + // This register is valid for B1 and later steppings only. + // + OperationRegion (SCIS, SystemMemory, 0xFED030C0, 0x4) + Field (SCIS, DWordAcc, NoLock, Preserve) + { + , 1, // Bit 0 + LHAD, 1, + LATA, 1, + LDIO, 1, + LARD, 1, + LIO1, 1, + LCEP, 1, // Bit 6 SEC0 + LANB, 1, + LHCI, 1, // Bit 8 XHCI + LOTG, 1, + LECI, 1, + LHSI, 1 + } + + + Method (_DSM, 0x4, NotSerialized) + { + // DSM UUID . + If (LEqual (Arg0, ToUUID ("8B38B469-6F95-4B08-9B02-2DEFCC2D2C35"))) + { + // Function 0 : Query Function + If (LEqual (Arg2, Zero)) + { + // Revision 1 + If (LEqual (Arg1, One)) + { + Return (Buffer (One) { 0x03 }) + } + } + // Function 1 : return PMBASE+0x20 + If (LEqual (Arg2, One)) + { + Return (Add (PMBS,0x20)) + } + + Return (0x00) + } + Else + { + Return (Buffer (One) { 0x00 }) + } + + } + + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {9} // should be 108 + }) + Return (RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + If (LGreaterEqual (OSYS,2013)) // Virtual Button applicable for Winblue and higher version of WinOS + { + If (And (PB1E, 1)) // Virtual Power Button is enabled? + { + Return (0x00) // Device present,enabled and should be shown in UI. + } + } + Return (0x00) // Device NOT present + } + + Method (_AEI, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate() + { + GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullDown,,"\\_SB.GPED",) {2} //pin 2 + }) + Return (RBUF) + } + + Method (_E02) { // _Exx method will be called when interrupt is raised + If (LEqual (PWBS, 1)) { + Store (1, PWBS) // Clear PowerButton Status + Notify (\_SB.PWRB, 0x80) + } + If (LEqual (PMEB, 1)) { + Store (1, PMEB) //Clear PME_B0_STS + } + + If (LEqual (\_SB.PCI0.SATA.PMES, 1)) { + Store (1, \_SB.PCI0.SATA.PMES) + Notify (\_SB.PCI0.SATA, 0x02) + } + + + If (LEqual (\_SB.PCI0.HDEF.PMES, 1)) { + Store (1, \_SB.PCI0.HDEF.PMES) + Notify (\_SB.PCI0.HDEF, 0x02) + } + + If (LEqual (\_SB.PCI0.XHC1.PMES, 1)) + { + Store (1, \_SB.PCI0.XHC1.PMES) + Notify (\_SB.PCI0.XHC1, 0x02) + } + } + } // Device (GPED) + + //-------------------- + // GPIO + //-------------------- + Device (GPO0) + { + Name (_ADR, 0) + Name (_HID, "INT33FF") + Name (_CID, "INT33FF") + Name (_DDN, "General Purpose Input/Output (GPIO) controller - SOUTHWEST") + Name (_UID, 1) + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + //IO(Decode16,0x0500,0x0500,0x01,0xFF) + Memory32Fixed (ReadWrite, 0x0FED80000, 0x00008000) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {49} + }) + Return (RBUF) + } + + OperationRegion (GPM0, SystemMemory, Or(\GBA0, 0x5800), 0x30) + Field (GPM0, DWordAcc, Lock, Preserve) { + , 1, + TSRR, 1, // GPIO Tx State of GPIO SW75: TOUCH_RST_N for BSW CR + Offset(0x18), + , 1, + TSR2, 1, // GPIO Tx State of GPIO SW78: TOUCH_RST_N for BSW RVP FAB2 + Offset(0x28), + , 1, + TSRS, 1 // GPIO Tx State of GPIO SW80: TOUCH_RST_N for BSW RVP + } + + Name (AVBL, 1) + Method (_REG, 2) { + If (Lequal (Arg0, 0)) { + Store (Arg1, ^AVBL) + } + } + + Method (_STA, 0x0, NotSerialized) + { + If (\_OSI ("Android")) { // Android would parse GPIO _REG but Win8.1 won't + Store (0, ^AVBL) + } + if (LEqual (GOAE, 1)) { // If LPSS with GPIO Devices Support Enabled + Return (0xF) + } + Return (0) + } + } // Device (GPO0) + + Device (GPO1) + { + Name (_ADR, 0) + Name (_HID, "INT33FF") + Name (_CID, "INT33FF") + Name (_DDN, "General Purpose Input/Output (GPIO) controller - NORTH" ) + Name (_UID, 2) + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x0FED88000, 0x00008000) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {48} + }) + Return (RBUF) + } + + OperationRegion (GPM1, SystemMemory, Or (\GBA1, 0x4428), 4) + Field (GPM1, DWordAcc, Lock, Preserve) { + , 1, + CWLE, 1 // Tx bit of SoC GPIO N05: GPIO_DFX4 to COMBO_WLAN_EN + } + + Name (AVBL, 1) + Method (_REG, 2) { + If (Lequal (Arg0, 0)) { + Store (Arg1, ^AVBL) + } + } + + Method (_STA, 0x0, NotSerialized) + { + If (\_OSI ("Android")) { // Android would parse GPIO _REG but Win8.1 won't + Store (0, ^AVBL) + } + if (LEqual (GOAE, 1)) { // If LPSS with GPIO Devices Support Enabled + Return (0xF) + } + Return (0) + } + } // Device (GPO1) + + Device (GPO2) + { + Name (_ADR, 0) + Name (_HID, "INT33FF") + Name (_CID, "INT33FF") + Name (_DDN, "General Purpose Input/Output (GPIO) controller - EAST" ) + Name (_UID, 3) + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x0FED90000, 0x00008000) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {50} + }) + Return (RBUF) + } + + OperationRegion (GPM2, SystemMemory, Or(\GBA2, 0x4820), 4) + Field (GPM2, DWordAcc, Lock, Preserve) { + , 1, + SHD3, 1 // [1] GPIO Tx State of GPIO E19: SENSOR_HUB_RESET + } + + Name (AVBL, 1) + Method (_REG, 2) { + If (Lequal (Arg0, 0)) { + Store (Arg1, ^AVBL) + } + } + + Method (_STA, 0x0, NotSerialized) + { + If (\_OSI ("Android")) { // Android would parse GPIO _REG but Win8.1 won't + Store (0, ^AVBL) + } + if (LEqual (GOAE, 1)) { // If LPSS with GPIO Devices Support Enabled + Return (0xF) + } + Return (0) + } + } // Device (GPO2) + + Device (GPO3) + { + Name (_ADR, 0) + Name (_HID, "INT33FF") + Name (_CID, "INT33FF") + Name (_DDN, "General Purpose Input/Output (GPIO) controller - SOUTHEAST" ) + Name (_UID, 4) + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x0FED98000, 0x00008000) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {91} + }) + Return (RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + if (LEqual (GOAE, 1)) { // If LPSS with GPIO Devices Support Enabled + Return (0xF) + } + Return (0) + } + } // Device (GPO3) + + + Device (TBAD) // Button device + { + Name (_HID, "INTCFD9") + Name (_CID, "PNP0C40") + Name (_DDN, "Keyboard less system - 5 Button Array Device" ) + + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate () + { + // Resources have to appear in order (power, windows, volup, voldown, rotationlock) + GpioInt (Edge, ActiveBoth, Exclusive, PullDefault, 6000, "\\_SB.GPO0", ) {6} // Home + GpioInt (Edge, ActiveBoth, Exclusive, PullDefault, 6000, "\\_SB.GPO0", ) {5} // Volume up + GpioInt (Edge, ActiveBoth, Exclusive, PullDefault, 6000, "\\_SB.GPO0", ) {4} // Volume down + GpioInt (Edge, ActiveBoth, Exclusive, PullDefault, 6000, "\\_SB.GPO0", ) {2} // rotationlock + }) + Return (RBUF) + } + + Method(_STA) + { + Return (0x00) // Used for non-EC system + } + + Method(_DSM, 0x4, NotSerialized) + { + Store ("Method _DSM for Button Device", Debug) + // Switch based on which unique function identifier was passed in + // Windows Button Array device UUID: {DFBCF3C5-E7A5-44E6-9C1F-29C76F6E059C} + // + If (LEqual (Arg0, ToUUID ("DFBCF3C5-E7A5-44E6-9C1F-29C76F6E059C"))) { + switch (Arg2) { + // Function 0: Return supported functions, based on revision + Case (0) + { + // revision 0: function 0 & 1 are supported. + return (Buffer () {0x3}) + } // Case (0) + // Function 1: For Windows Button Array device, returns an integer with the bits set for + // ACPI 10 seconds reset timer and level-detection on power button. + Case (1) + { + //An integer (DWORD) with the following bit-wise definition: + //Bits 31 - 2: Reserved (must be 0). + //Bit 1: This bit should be set if power button is wired to an interrupt controller (GPIO or otherwise) + // that supports level-detection. + //Bit 0: This bit should be set if the platform supports ACPI reset time of 10 seconds or greater. + //Otherwise it should be clear. + return (0x3) + } //Case (1) + } // end of switch + }// if + else { + // If not one of the function identifiers we recognize, then return a buffer + // with bit 0 set to 0 indicating no functions supported. + return (Buffer () {0}) + } + } //End of _DSM Method + } // end of TBAD device + + // + // Device for Message Bus Interface + // + Device (MBID) { + Name (_HID, "INT33BD") + Name (_CID, "INT33BD") + Name (_HRV, 2)//different from CLT's + Name (_UID, 1) + + Method (_CRS, 0, Serialized){ + Name (RBUF, ResourceTemplate (){ + Memory32Fixed ( + ReadWrite, + 0xE00000D0, // Address Base + 0xC, // Address Length (MCR/MDR/MCRX) + ) + }) + Return (RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + Return (0x00) // Device not present, disabled and hided in UI. + } + + // + // custom opregion for MBI access + // + OperationRegion (REGS, 0x87, 0x0, 0x30) + Field (REGS, DWordAcc, NoLock, Preserve) + { + PORT, 32, // Message Port + REG, 32, // Message Target Register Address + DATA, 32, // Message Data + MASK, 32, // Mask bits for modify operation + BE, 32, // Message Write Byte enables: 0 - BYTE; 1 - WORD; 2 - DWORD + OP, 32 // Operations: 0 - read; 1 - write; 2 - modify + } + + // + // availability of the custom opregion + // + Name (AVBL, 0) + Method (_REG, 2) { + If (Lequal(Arg0, 0x87)) { + Store (Arg1, ^AVBL) + } + } + + // + // Method Name: READ + // Arguments: + // Arg0: PORT + // Arg1: REG + // Arg2: BE + // Return Value: + // DATA + // + Method(READ, 3, Serialized) { + Store (0xFFFFFFFF , Local0) + If (Lequal (AVBL, 1)) { + Store (0, OP) // must be set at first, do not change! + Store (Arg0, PORT) + Store (Arg1, REG) + Store (Arg2, BE) + Store (DATA, Local0) + } + return (Local0) + } + + // + // Method Name: WRIT + // Arguments: + // Arg0: PORT + // Arg1: REG + // Arg2: BE + // Arg3: DATA + // Return Value: + // NONE + // + Method (WRIT, 4, Serialized) { + If (Lequal (AVBL, 1)) { + Store (1, OP) // must be set at first, do not change! + Store (Arg0, PORT) + Store (Arg1, REG) + Store (Arg2, BE) + Store (Arg3, DATA) + } + } + + // + // Method Name: MODI + // Arguments: + // Arg0: PORT + // Arg1: REG + // Arg2: BE + // Arg3: DATA + // Arg4: MASK + // Return Value: + // NONE + // + Method (MODI, 5, Serialized) { + If (Lequal (AVBL, 1)) { + Store (2, OP) // must be set at first, do not change! + Store (Arg0, PORT) + Store (Arg1, REG) + Store (Arg2, BE) + Store (Arg3, DATA) + Store (Arg4, MASK) + } + } + } + +// +// Platform Indicator device PIND +// handles platform events, buttons and indicators such as: +// VOLUME_UP, VOLUME_DOWN, BRIGHTNESS, ROTATION_LOCK, MUTE, LID, DOCK, POWER_BUTTON +// SLEEP_BUTTON, WIFI, TABLET_MODE +// +Device (PIND) { + Name (_HID, "INT3497") + Name (_UID, 0) + + Method (_STA) { + If (\_OSI ("Android")) + { + Return (0xF) + } + Return (0x0) + } + + + + // + // Supported TYPES: + // 0x00 - Undefined + // 0x01 - Interrupt source (GpioInt() or Interrupt()) defined in the _CRS method, + // Descriptor field returns type, zero based index of interrupt sources found in _CRS method. + // 0x02 - interrupt event that is not listed in CRS table. This interrupt is delivered + // through a notify () event where the notify event value is a pointer + // to the package indexed within the package returned by the _IND method. Descriptor field returns type only. + // 0x03 - Level, descriptor field returnd type, current value (1 or 0). + // 0x04 - Numerical, descriptor field returnd type, an integer value + // 0x05 - Percentage, descriptor field returnd type, value between 0 - 100 + // 0x06 - Range, descriptor field returnd type, Minimum Value, Max Value, and current value + // 0x07 - 0xNN - Reserved for future types + // + Name (PDAT, Package () { + // Name, Descriptor: Type, value/Index + Package (2) {"VOLUME_UP", Package (1) {0x02 }}, // Pulse event + Package (2) {"VOLUME_DOWN", Package (1) {0x02 }}, // Pulse event + Package (2) {"HOME_BUTTON", Package (1) {0x02 }} // Pulse event + }) + + Method (_IND, 0, Serialized) { + // If required read any items that need to be updated before returning package PDAT. + return (PDAT) + } +} // end device PIND + + + +} // end Scope(\_SB) + diff --git a/ChvRefCodePkg/AcpiTablesPCAT/Platform/Thermal.asl b/ChvRefCodePkg/AcpiTablesPCAT/Platform/Thermal.asl new file mode 100644 index 0000000000..312a4cd832 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/Platform/Thermal.asl @@ -0,0 +1,218 @@ +/** @file + ACPI DSDT table + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// Thermal.asl represents a Thermal Zone to be used for testing on the +// Customer Reference Boards. + +External(\_SB.DPTF.CTOK, MethodObj) + +Scope(\_TZ) +{ + // Notes: + // 1) WIN2K strictly uses interrupt driven thermal events. + // 2) Temperature values are stored in tenths of Kelvin to + // eliminate the decimal place. + // 3) Kelvin = Celsius + 273.2. + // 4) All temperature must be >= 289K. + + // Flag to indicate Legacy thermal control. + // 1 = Legacy thermal control + // 0 = other thermal control, like DPTF + Name(LEGA, 1) // for Active Policy + Name(LEGP, 1) // for Passive Policy + Name(LEGC, 1) // for Critical Policy + + // Fan 0 = Package Processor Fan. + PowerResource(FN00,0,0) + { + Method(_STA,0,Serialized) + { + If(LEqual(FNSP,0)) { + Return(0x0) + } + // Return Virtual Fan 0 status. + Return(VFN0) + } + + Method(_ON,0,Serialized) + { + // Set Virtual Fan 0 On. + Store(1,VFN0) + + // If EC access is enabled. + If(LAnd(\ECON, \_TZ.LEGA)) + { + Store(1, \_SB.PCI0.LPCB.H_EC.FNSL) // Set bit-0 to select CPU Fan. + Store(100, \_SB.PCI0.LPCB.H_EC.FDCY) // Fan set to 100% duty cycle. + \_SB.PCI0.LPCB.H_EC.ECMD(0x1A) // Fan command. + } + } + + Method(_OFF,0,Serialized) + { + // Set Virtual Fan 0 Off. + Store(0,VFN0) + + // If EC access is enabled. + If(LAnd(\ECON, \_TZ.LEGA)) + { + Store(1, \_SB.PCI0.LPCB.H_EC.FNSL) // Set bit-0 to select CPU Fan. + Store(0, \_SB.PCI0.LPCB.H_EC.FDCY) // Fan set to 0% duty cycle. + \_SB.PCI0.LPCB.H_EC.ECMD(0x1A) // Fan command. + } + } + } + + // Associate Virtual Fan 0 Power Resource with the FAN0 Device. + Device(FAN0) + { + Name(_HID, EISAID("PNP0C0B")) + Name(_UID,0) + Name(_PR0, Package(1){FN00}) + } + + // Thermal Zone 1 = Package Thermal Zone. + // Package Thermal Zone is used for Active and Critical Policy Control + // Package Thermal Zone returns the maximum temperature + // of all components within the package + ThermalZone(TZ01) + { + // Temporary variable for holding the current temprature reading + Name(PTMP, 3000) + Name(SINI, 0) + Name(ADDR, 0x96) // SMBUS Address of temperature sensor + Name(LTV0, 0) // Local Temperature Value + Name(RTV1, 1) // Remote 1 Temperature Value + Name(RTV2, 0x30) // Remote 2 Temperature Value + Name(HITP, 0x55) // Temp High Limit + + // Notifies ASL Code the current cooling mode. + // 0 - Active cooling + // 1 - Passive cooling + Method(_SCP, 1, Serialized) + { + Store(Arg0, CTYP) + } + + // Return the temperature at which the OS must perform a Critcal Shutdown. + Method(_CRT,0,Serialized) + { + If (LEqual(\_TZ.LEGC,0)){ Return(Add(2732,Multiply(210,10)))} // 210 degree C + Return(Add(2732,Multiply(\CRTT,10))) + } + + // We are not using Active Cooling in legacy mode so hard code some values for WHQL. + Method(_AC0,0,Serialized) + { + Return(Add(2732,Multiply(110,10))) // 110 degree C + } + + // Returns the Device to turn on when _ACx is exceeded. + Name(_AL0, Package(){FAN0}) + + // _TMP (Temperature) + // + // Return the highest of the CPU temperatures to the OS. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the current temperature of the thermal zone (in tenths of degrees Kelvin) + // + Method(_TMP,0,Serialized) + { + // + // If DTS enabled, return higher temperature of the 2 cores + // + If (DTSE) + { + If (LGreater(DTS2, DTS1)) + { + Store(DTS2,Local0) + } Else { + Store(DTS1,Local0) + } + Return (Add(2732,Multiply(Local0,10))) + } + // + // Return the higher of EC temperature sensors. + // + If (\ECON) + { + If (LGreater(\_SB.PCI0.LPCB.H_EC.LTMP, \_SB.PCI0.LPCB.H_EC.TMPR)) + { + Return (Add(2732,Multiply(\_SB.PCI0.LPCB.H_EC.LTMP,10))) + } Else { + Return (Add(2732,Multiply(\_SB.PCI0.LPCB.H_EC.TMPR,10))) + } + } + // + // Return a static value if both EC and DTS are unavailable. + // + Return (3000) // (3000-2732)/10 = 26.8 degree C + } // End of_TMP scope + + // Return the Processor(s) used for Passive Cooling. + Method(_PSL,0,Serialized) + { + If(LEqual(MPEN, 4)) + { + // CMP - Throttling controls all four logical CPUs. + Return(Package(){\_PR.CPU0,\_PR.CPU1,\_PR.CPU2,\_PR.CPU3}) + } + + If(MPEN) + { + // CMP - Throttling controls both CPUs. + Return(Package(){\_PR.CPU0,\_PR.CPU1}) + } + + Return(Package(){\_PR.CPU0}) + } + + // Returns the temperature at which the OS initiates CPU throttling. + Method(_PSV,0,Serialized) + { + If (LEqual(\_TZ.LEGP,0)){ Return(Add(2732,Multiply(110,10)))} // 110 degree C + Return(Add(2732,Multiply(\PSVT,10))) + } + + // Returns TC1 value used in the passive cooling formula. + Method(_TC1,0,Serialized) + { + Return(TC1V) + } + + // Returns TC2 value used in the passive cooling formula. + Method(_TC2,0,Serialized) + { + Return(TC2V) + } + + // Returns the sampling period used in the passive cooling formula. + Method(_TSP,0,Serialized) + { + Return(TSPV) + } + + // Returns Hot Temperature + Method(_HOT,0,Serialized) + { + If (LEqual(\_TZ.LEGC,0)){ Return(Add(2732,Multiply(205,10)))} // 205 degree C + Subtract(\CRTT, 5, Local0) + Return(Add(2732,Multiply(Local0,10))) + } + } // End of thermal zone +} // End of scope diff --git a/ChvRefCodePkg/AcpiTablesPCAT/SampleCode/Include/SamplePlatformDefinition.h b/ChvRefCodePkg/AcpiTablesPCAT/SampleCode/Include/SamplePlatformDefinition.h new file mode 100644 index 0000000000..186004324f --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/SampleCode/Include/SamplePlatformDefinition.h @@ -0,0 +1,35 @@ +/** @file + Header file for ACPI MADT and MCFG table + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// +// I/O APIC IDs, the code uses math to generate the numbers +// instead of using these defines. +// +#define ICH_IOAPIC (1 << 0) +#define ICH_IOAPIC_ID 0x08 + +// +// CPU Equates +// +#define MAX_THREAD 2 +#define MAX_CORE 1 +#define MAX_DIE 2 +#define MAX_CPU_SOCKET 1 +#define MAX_CPU_NUM (MAX_THREAD * MAX_CORE * MAX_DIE * MAX_CPU_SOCKET) + +// +// Platform Max Bus Number +// +#define PLATFORM_MAX_BUS_NUM 0x3f diff --git a/ChvRefCodePkg/AcpiTablesPCAT/SampleCode/Madt/Madt.h b/ChvRefCodePkg/AcpiTablesPCAT/SampleCode/Madt/Madt.h new file mode 100644 index 0000000000..d6e161fb8b --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/SampleCode/Madt/Madt.h @@ -0,0 +1,188 @@ +/** @file + This file describes the contents of the ACPI Multiple APIC Description + Table (MADT). Some additional ACPI values are defined in Acpi1_0.h and + Acpi2_0.h. + To make changes to the MADT, it is necessary to update the count for the + APIC structure being updated, and to modify table found in Madt.c. + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _MADT_H +#define _MADT_H + +// +// Statements that include other files +// +#include "AcpiTablePlatform.h" +#include +#include +#include +#include "PlatformBaseAddresses.h" +#include + +// +// MADT Definitions +// +#define EFI_ACPI_OEM_MADT_REVISION 0x00000000 +// +// Multiple APIC Flags are defined in AcpiX.0.h +// +#define EFI_ACPI_1_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_1_0_PCAT_COMPAT) +#define EFI_ACPI_2_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_2_0_PCAT_COMPAT) +#define EFI_ACPI_3_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_3_0_PCAT_COMPAT) +#define EFI_ACPI_4_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_4_0_PCAT_COMPAT) + +// +// Define the number of each table type. +// This is where the table layout is modified. +// +#define EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT MAX_CPU_NUM +#define EFI_ACPI_LOCAL_APIC_NMI_COUNT MAX_CPU_NUM +#define EFI_ACPI_IO_APIC_COUNT 1 +#define EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT 2 +#define EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT 0 +#define EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT 0 +#define EFI_ACPI_IO_SAPIC_COUNT 0 +#define EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT 0 +#define EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT 0 + +// +// MADT structure +// +// +// Ensure proper structure formats +// +#pragma pack(1) +// +// ACPI 1.0 Table structure +// +typedef struct { + EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + +#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0 + EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT]; +#endif + +#if EFI_ACPI_IO_APIC_COUNT > 0 + EFI_ACPI_1_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT]; +#endif + +#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0 + EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT]; +#endif + +#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0 + EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT]; +#endif + +#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0 + EFI_ACPI_1_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT]; +#endif + +#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0 + EFI_ACPI_1_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT]; +#endif + +} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + +// +// ACPI 2.0 Table structure +// +typedef struct { + EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + +#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0 + EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT]; +#endif + +#if EFI_ACPI_IO_APIC_COUNT > 0 + EFI_ACPI_2_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT]; +#endif + +#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0 + EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT]; +#endif + +#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0 + EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT]; +#endif + +#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0 + EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT]; +#endif + +#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0 + EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT]; +#endif + +#if EFI_ACPI_IO_SAPIC_COUNT > 0 + EFI_ACPI_2_0_IO_SAPIC_STRUCTURE IoSapic[EFI_ACPI_IO_SAPIC_COUNT]; +#endif + +#if EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT > 0 + EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE LocalSapic[EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT]; +#endif + +#if EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT > 0 + EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE PlatformInterruptSources[EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT]; +#endif + +} EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + +// +// ACPI 3.0 Table structure +// +typedef struct { + EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + +#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0 // Type 0x00 + EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT]; +#endif + +#if EFI_ACPI_IO_APIC_COUNT > 0 // Type 0x01 + EFI_ACPI_3_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT]; +#endif + +#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0 // Type 0x02 + EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT]; +#endif + +#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0 // Type 0x03 + EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT]; +#endif + +#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0 // Type 0x04 + EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT]; +#endif + +#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0 // Type 0x05 + EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT]; +#endif + +#if EFI_ACPI_IO_SAPIC_COUNT > 0 // Type 0x06 + EFI_ACPI_3_0_IO_SAPIC_STRUCTURE IoSapic[EFI_ACPI_IO_SAPIC_COUNT]; +#endif + +#if EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT > 0 // Type 0x07 : This table changes in madt 2.0 + EFI_ACPI_3_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE LocalSapic[EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT]; +#endif + +#if EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT > 0 // Type 0x08 + EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE PlatformInterruptSources[EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT]; +#endif + +} EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + +#pragma pack() + +#endif diff --git a/ChvRefCodePkg/AcpiTablesPCAT/SampleCode/Madt/Madt30.aslc b/ChvRefCodePkg/AcpiTablesPCAT/SampleCode/Madt/Madt30.aslc new file mode 100644 index 0000000000..ed5c7643fa --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/SampleCode/Madt/Madt30.aslc @@ -0,0 +1,215 @@ +/** @file + This file contains a structure definition for the ACPI 2.0 Multiple APIC + Description Table (MADT). Any changes to the MADT table require updating the + respective structure count in Madt.h and then adding the structure to the + MADT defined in this file. The table layout is defined in Madt.h and the + table contents are defined in Acpi3_0.h and Madt.h. + + Copyright (c) 1996 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// +// Statements that include other files +// +#include "Madt.h" +#include + +// +// Multiple APIC Description Table +// +// http://www.microsoft.com/whdc/system/cec/acpi-mp.mspx +// +EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { + EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, // **Signatures are the same 1.0-3.0 because it says "APIC". + sizeof (EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE), // **Length + EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION, + // + // EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION, // **Table Revision must be 2.0 for ACPI 3.0 + // Checksum will be updated at runtime + // + 0x00, // **Check sum + // + // It is expected that these values will be programmed at runtime + // + ' ', // OEMID + ' ', // Creative way to + ' ', // make six bytes + ' ', // of space in + ' ', // a table for + ' ', // **OEMID + 0, // **OEM Table ID + EFI_ACPI_OEM_MADT_REVISION, // **OEM Revision + 0, // **Creator ID + 0, // **Creator Revision + // + // MADT specific fields + // + LOCAL_APIC_ADDRESS, // **Local APIC Address + EFI_ACPI_4_0_MULTIPLE_APIC_FLAGS, // **Flags + // + // Processor Local APIC Structure + // Correct processor order, Primary threads first then Hyper threads + // And correct APIC-ids + // This text below is included as a reference until Thurley is 100%: + // According to EDS the Local APIC ID is determined based of a bit structure + // Bit 24: Core ID Bit 25: Core Pair ID Bit 26-27: Reserved Bit 28-30: Socket ID Bit 31: Reserved + // 4 Sockets and 4 Cores per Socket. + // So possible LAPIC IDs 00, 01, 02, 03, 10, 11, 12, 13, 20, 21, 22, 23, 30, 31, 32, 33 + // Static Entries 00, 10, 20, 30, 01, 11, 21, 31, 02, 12, 22, 32, 03, 13, 23, 33 + // BSP needs to be first entry in table. Check before boot. If BSP non zero need to rotate the entries. + // Suppore BSP is LAPIC ID xy. Rotate the table by using formula [x + (y * 4)] + // So if BSP LAPIC ID is 21 then table rotated 6 times. + // End of Reference Text. + // Thurley is supposed to be 2 sockets, 4 cores, and hyperthreading available per each core. + // 2 (sockets) x 4 (cores) = 8 (processors non-HT), 8 (processors non-HT) x 2 (HT/proc) = 16 (HT procs) + // Rhyme & reason of the ordering below. This is a best guess ordering for now, + // Thurley EPS may give better info on LAPIC numbers. + // Ordering was established to help dissipate heat across two sockets evenly. + // Since logical processor number only has to be unique, I followed + // a similar approach to high end servers and have the first digit of the LAPIC + // id the socket number. + // + EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC, // Type 0x00 + sizeof (EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x01, // Processor ID + 0x00, // Local APIC ID + 0x00000001, // Flags - Disabled (until initialized by platform driver) + EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC, // Type + sizeof (EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x02, // Processor ID + 0x02, // Local APIC ID + 0x00000001, // Flags - Disabled (until initialized by platform driver) + EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC, // Type + sizeof (EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x03, // Processor ID + 0x04, // Local APIC ID + 0x00000001, // Flags - Disabled (until initialized by platform driver) + EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC, // Type + sizeof (EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x04, // Processor ID + 0x06, // Local APIC ID + 0x00000001, // Flags - Disabled (until initialized by platform driver) + // + // *************** IO APIC Structure ****************** + // + // + // + // ************************** I/O APIC (ICH) ************** + // + EFI_ACPI_3_0_IO_APIC, // Type 0x01 + sizeof (EFI_ACPI_3_0_IO_APIC_STRUCTURE), // Length + ICH_IOAPIC_ID, // IO APIC ID + EFI_ACPI_RESERVED_BYTE, // Reserved EFI_ACPI_RESERVED_BYTE + IO_APIC_ADDRESS, // IO APIC Address (physical) 0xFEC00000 + 0x18 * 0, // Global System Interrupt Base + + // + // Interrupt Source Override Structure: Sample + // + // EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE, // Type 0x02 + // sizeof (EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE),// Length + // 0x00, // Bus + // 0x00, // Source + // 0x00000000, // Global System Interrupt + // 0x0000, // Flags + // + // IRQ0=>IRQ2 Interrupt Source Override Structure + // + EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE, // Type 0x02 + sizeof (EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE), // Length + 0x00, // Bus - ISA + 0x00, // Source - IRQ0 + 0x00000002, // Global System Interrupt - IRQ2 + 0x0000, // Flags - Conforms to specifications of the bus + // + // ISO (SCI Active High) Interrupt Source Override Structure + // + EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE, // Type 0x02 + sizeof (EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE), // Length + 0x00, // Bus - ISA + 0x09, // Source - IRQ0 + 0x00000009, // Global System Interrupt - IRQ2 + 0x000D, // Flags - Level-tiggered, Active High + + // + // Non-Maskable Interrupt (NMIs) Source Structure: Sample + // + // EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE, // Type 0x03 + // sizeof (EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE), // Length + // 0x0000, // Flags + // 0x00000000, // Global System Interrupt + // + // Local APIC NMI Structure: Sample + // + // EFI_ACPI_2_0_LOCAL_APIC_NMI, // Type 0x04 + // sizeof (EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE), // Length + // 0x00, // ACPI Processor ID + // 0x0000, // Flags + // 0x00, // Local APIC LINT# + // >>> CORE_m008 Add Local APIC NMI tables for 2nd, 3rd and 4th physical processors. + // + // Assuming here that only need to entries for two sockets. + // + EFI_ACPI_3_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x01, // ACPI Processor ID + 0x000D, // Flags - Level-tiggered, Active High + 0x01, // Local APIC LINT# + EFI_ACPI_3_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x02, // ACPI Processor ID + 0x000D, // Flags - Level-tiggered, Active High + 0x01, // Local APIC LINT# + EFI_ACPI_3_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x03, // ACPI Processor ID + 0x000D, // Flags - Level-tiggered, Active High + 0x01, // Local APIC LINT# + EFI_ACPI_3_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x04, // ACPI Processor ID + 0x000D, // Flags - Level-tiggered, Active High + 0x01, // Local APIC LINT# + + // + // Local APIC Address Override Structure: Sample + // + // EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE, // Type 0x5 + // sizeof (EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE), // Length + // EFI_ACPI_RESERVED_WORD, // Reserved + // 0x0000000000000000, // Local APIC Address + // + // Sample Platform Interrupt Sources Structure + // + // EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES, // Type 0x8 + // sizeof (EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE), // Length + // 0x0000, // Flags + // 0x00, // Interrupt Type + // 0x00, // Processor ID + // 0x00, // Processor EID + // 0x00, // IO SAPIC Vector + // 0x00000000, // Global System Interrupt + // EFI_ACPI_RESERVED_DWORD, // Reserved + // +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from + // removing the data structure from the executable + // + return (VOID*)&Madt; +} diff --git a/ChvRefCodePkg/AcpiTablesPCAT/SampleCode/Mcfg/Mcfg.aslc b/ChvRefCodePkg/AcpiTablesPCAT/SampleCode/Mcfg/Mcfg.aslc new file mode 100644 index 0000000000..aec2d72b97 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/SampleCode/Mcfg/Mcfg.aslc @@ -0,0 +1,83 @@ +/** @file + This file contains a structure definition for the ACPI Memory mapped + configuration space base address Description Table (MCFG). Any changes + to the MCFG table require updating the respective structure count in + Mcfg.h and then adding the structure to the MCFG defined in this file. + The table layout is defined in Mcfg.h and the table contents are defined + in McfgTable.h and Mcfg.h. + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// +// Statements that include other files +// +#include + +// +// MCFG Table definition +// +EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE MCFG = { + EFI_ACPI_3_0_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_SIGNATURE, + sizeof (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE), + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_REVISION, + // + // Checksum will be updated at runtime + // + 0x00, + // + // It is expected that these values will be programmed at runtime + // + ' ', + ' ', + ' ', + ' ', + ' ', + ' ', + + 0, + EFI_ACPI_OEM_MCFG_REVISION, + 0, + 0, + // + // Beginning of MCFG specific fields + // + EFI_ACPI_RESERVED_QWORD, + // + // Sample Memory Mapped Configuration Space Base Address Structure + // + // 0x0, // Base Address + // 0x0, // PCI Segment Group Number + // 0x0, // Start Bus Number + // 0x0, // End Bus Number + // EFI_ACPI_RESERVED_DWORD, // Reserved + // + // Memory Mapped Configuration Space Base Address Structure for BNB + // + 0x0, // Base Address, will be updated by AcpiPlatform + 0x0, // PCI Segment Group Number + 0x0, // Start Bus Number + PLATFORM_MAX_BUS_NUM, // End Bus Number + EFI_ACPI_RESERVED_DWORD, // Reserved +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from + // removing the data structure from the executable + // + return (VOID*)&MCFG; +} diff --git a/ChvRefCodePkg/AcpiTablesPCAT/SampleCode/Mcfg/Mcfg.h b/ChvRefCodePkg/AcpiTablesPCAT/SampleCode/Mcfg/Mcfg.h new file mode 100644 index 0000000000..55d8b1b5fb --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/SampleCode/Mcfg/Mcfg.h @@ -0,0 +1,64 @@ +/** @file + ACPI Memory mapped configuration space base address Description Table + implementation, based on PCI Firmware Specification Revision 3.0 final draft, + downloadable at http://www.pcisig.com/home + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _MCFG_H_ +#define _MCFG_H_ + +// +// Statements that include other files +// +#include +#include "McfgTable.h" +#include +// +// "MCFG" Static Resource Affinity Table +// +#define EFI_ACPI_3_0_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_SIGNATURE 0x4746434D + +// +// MCFG Definitions, see specification for details. +// +#define EFI_ACPI_OEM_MCFG_REVISION 0x00000001 + +// +// Define the number of each table type. +// This is where the table layout is modified. +// +#define EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE_COUNT 1 + +// +// MCFG Table definition. The table must be defined in a platform +// specific manner. +// +// +// Ensure proper structure formats +// +#pragma pack(1) + +typedef struct { + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header; + +#if EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE_COUNT > 0 + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE Segment[ + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE_COUNT]; +#endif + +} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE; + +#pragma pack() + +#endif // _MCFG_H_ diff --git a/ChvRefCodePkg/AcpiTablesPCAT/SampleCode/Mcfg/McfgTable.h b/ChvRefCodePkg/AcpiTablesPCAT/SampleCode/Mcfg/McfgTable.h new file mode 100644 index 0000000000..afe461bb60 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/SampleCode/Mcfg/McfgTable.h @@ -0,0 +1,61 @@ +/** @file + ACPI Memory mapped configuration space base address Description Table + definition, based on PCI Firmware Specification Revision 3.0 final draft, + downloadable at http://www.pcisig.com/home + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _MCFG_TABLE_H_ +#define _MCFG_TABLE_H_ + +// +// Include files +// +#include + +// +// Ensure proper structure formats +// +#pragma pack(1) +// +// MCFG Revision (defined in spec) +// +#define EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_REVISION 0x01 + +// +// MCFG Structure Definitions +// +// +// Memory Mapped Enhanced Configuration Base Address Allocation +// Structure Definition +// +typedef struct { + UINT64 BaseAddress; + UINT16 PciSegmentGroupNumber; + UINT8 StartBusNumber; + UINT8 EndBusNumber; + UINT32 Reserved; +} EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE; + +// +// MCFG Table header definition. The rest of the table +// must be defined in a platform specific manner. +// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 Reserved; +} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER; + +#pragma pack() + +#endif // _MCFG_TABLE_H diff --git a/ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/Als.asl b/ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/Als.asl new file mode 100644 index 0000000000..7ae83984b1 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/Als.asl @@ -0,0 +1,60 @@ +/** @file + ACPI DSDT table + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Device(ALSD) +{ + Name(_HID,"ACPI0008") + Name(_CID,EISAID("PNP0C01")) + + Method(_STA,0) + { + If(LEqual(ALSE,2)) + { + Return(0x000F) // ALS Enabled. Show it. + } + + Return(0x0000) // ALS Disabled. Hide it. + } + + Method(_ALI) + { + Return (Or(ShiftLeft(LHIH,8),LLOW)) + } + +// TODO +// Method(_ALT) +// { +// Return(3000) +// } + +// TODO - These are "best guess" values. + + Name(_ALR, Package() + { + Package() {70, 0}, + Package() {73, 10}, + Package() {85, 80}, + Package() {100, 300}, + Package() {150, 1000} + }) + +// TODO - CRB designs don't require this as the KSC performas the polling +// and notifies ASL via Q70 when a change occurs. +// +// Method(_ALP) +// { +// } + +} diff --git a/ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/Chv.asl b/ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/Chv.asl new file mode 100644 index 0000000000..3ce50c62c1 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/Chv.asl @@ -0,0 +1,56 @@ +/** @file + ACPI DSDT table + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope (\_SB.PCI0) { + // + // IUNIT - Device 3, Function 0 + // + Device (ISP3) + { + Name (_ADR, 0x00030000) + Method (_PR3, 0, NotSerialized) + { + Return (Package (0x01) + { + ID3C + }) + } + + PowerResource (ID3C, 0x00, 0x0000) + { + Method (_STA, 0, NotSerialized) + { + If(LEqual(ISPD,2)) { + Return (0x0F) + } Else { + Return (0x0) + } + } + Method (_ON, 0, NotSerialized) + { + } + Method (_OFF, 0, NotSerialized) + { + } + } + } + + Device(GFX0) { // Mobile I.G.D + Name(_ADR, 0x00020000) + Name (_S0W, 3) + include("SystemAgent/IntelGraphics.asl") + include("SystemAgent/IntelIspDev2.asl") + } // end "Mobile I.G.D" +}//end scope diff --git a/ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/HostBus.asl b/ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/HostBus.asl new file mode 100644 index 0000000000..0d90934b47 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/HostBus.asl @@ -0,0 +1,412 @@ +/** @file + ACPI DSDT table + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Device(CHVC) +{ + Name(_ADR, 0x00000000) // Device 0, Function 0 + // + // Define various MCH Controller PCI Configuration Space + // registers which will be used to dynamically produce all + // resources in the Host Bus _CRS. + // + OperationRegion(HBUS, PCI_Config, 0x00, 0xFF) + Field(HBUS, DWordAcc, NoLock, Preserve) + { + Offset(0xD0), + SMCR, 32, // Message Control Register (0xD0) + Offset(0xD4), + SMDR, 32, // Message Data Register (0xD4) + Offset(0xD8), + MCRX, 32, // Message Control Register Extension (0xD8) + Offset(0xDC), + MCXX, 32, // Message Control Register Double Extension (0xDC) + } + // + // Define a method to read a 32-bit register on the Message bus. + // Arg0 = Port + // Arg1 = Register + // + // Returns 32-bit register value + // + Method(RMBR, 2, Serialized) + { + // + // Initiate regsiter read message on Message Bus MCR + // + Or(ShiftLeft(Arg0, 16), ShiftLeft(Arg1, 8), Local0) + Or(0x100000F0, Local0, SMCR) + // + // Read register value from Message Data Register + // + Return(SMDR) + } + + // + // Define a method to write a 32-bit register on the Message bus MDR. + // Arg0 = Port + // Arg1 = Register + // Arg2 = 32-bit value + // + Method(WMBR, 3, Serialized) + { + // + // Write register value to Message Data Register + // + Store(Arg2, SMDR) + // + // Initiate register write message on Message Bus + // + Or(ShiftLeft(Arg0, 16), ShiftLeft(Arg1, 8), Local0) + Or(0x110000F0, Local0, SMCR) + } + // + // Define an extended IOSF-SB access method to read a 32-bit message bus register. + // Arg0 = Port + // Arg1 = Register + // Arg2 = ReadOpcode + // Arg3 = Bar + // Arg4 = Device + // Arg5 = Function + // + // Returns 32-bit register value + // + Method(RMBX, 6, Serialized) + { + // + // Initiate regsiter read message on Message Bus MCR + // (((Bar & 0x07) << 8) | (((Device << 3) | (Function)) & 0xFF)) + // + And(Arg3, 0x07, Local4) // (Bar & 0x07) + Store(ShiftLeft(Local4, 8), Local4) // ((Bar & 0x07) << 8) + Or(ShiftLeft(Arg4, 3), Arg5, Local5) // ((Device << 3) | (Function)) + And(Local5, 0xFF, Local5) // (((Device << 3) | (Function)) & 0xFF) + Or(Local4, Local5, MCXX) + And(Arg1, 0xFFFFFF00, Local3) + Store(Local3, MCRX) + // + // Perform the Operation: + // (ReadOpCode << 24) | (PortId << 16) | ((Register & 0x000000FF) << 8) | 0xF0 + // + And(Arg1, 0x000000FF, Local0) + Or(ShiftLeft(Arg2, 24), ShiftLeft(Arg0, 16), Local1) + And(Local1, 0xFFFF0000, Local1) + Or(ShiftLeft(Local0, 8), 0xf0, Local2) + And(Local2, 0x0000FFFF, Local2) + Or(Local1, Local2, SMCR) + // + // Read register value from Message Data Register + // + Return(SMDR) + } + + // + // Define an extended IOSF-SB access method to write a 32-bit message bus register. + // Arg0 = Port + // Arg1 = Register + // Arg2 = 32-bit value + // Arg3 = WriteOpcode + // Arg4 = Bar + // Arg5 = Device + // Arg6 = Function + // + Method(WMBX, 7, Serialized) + { + // + // Write register value to Message Data Register + // (((Bar & 0x07) << 8) | (((Device << 3) | (Function)) & 0xFF)) + // + And(Arg4, 0x07, Local4) // (Bar & 0x07) + Store(ShiftLeft(Local4, 8), Local4) // ((Bar & 0x07) << 8) + Or(ShiftLeft(Arg5, 3), Arg6, Local5) // ((Device << 3) | (Function)) + And(Local5, 0xFF, Local5) // (((Device << 3) | (Function)) & 0xFF) + Or(Local4, Local5, MCXX) + And(Arg1,0xFFFFFF00, Local3) + Store(Local3, MCRX) + Store(Arg2, SMDR) + // + // Initiate register write message on Message Bus + // (WriteOpCode << 24) | (PortId << 16) | ((Register & 0x000000FF) << 8) | 0xF0 + // + And(Arg1,0x000000FF, Local0) + Or(ShiftLeft(Arg3, 24), ShiftLeft(Arg0, 16), Local1) + And(Local1,0xFFFF0000, Local1) + Or(ShiftLeft(Local0, 8), 0xf0, Local2) + And(Local2, 0x0000FFFF, Local2) + Or(Local1, Local2, SMCR) + } +} + +// +// BUS, I/O, and MMIO resources +// +Method(_CRS,0,Serialized) { + + Name(FTSZ,0x100000) // FTPM size + + // + // Update LPEA reserved memory + // + CreateDwordField(RES0, ^LPA0._MIN,LPMN) + CreateDwordField(RES0, ^LPA0._MAX,LPMX) + CreateDwordField(RES0, ^LPA0._LEN,LPLN) + If (LAnd(LNotEqual(LPE2, 0), LEqual(LPED, 0))) { + Store (LPE2, LPMN) + Add (LPMN, LPLN, LPMX) + Subtract(LPMX, 1, LPMX) + } Else { + Store (0, LPMN) + Store (0, LPMX) + Store (0, LPLN) + } + + //Update ISP0 reserved memory + CreateDwordField(RES0, ^ISP0._MIN,ISMN) + CreateDwordField(RES0, ^ISP0._MAX,ISMX) + CreateDwordField(RES0, ^ISP0._LEN,ISLN) + If (LEqual(ISPD,1)){ + Store (ISPA, ISMN) + Add (ISMN, ISLN, ISMX) + Subtract(ISMX, 1, ISMX) + } Else { + Store (0, ISMN) + Store (0, ISMX) + Store (0, ISLN) + } + + ////PCI MMIO SPACE + CreateDwordField(RES0, ^PM01._MIN,M1MN) + CreateDwordField(RES0, ^PM01._MAX,M1MX) + CreateDwordField(RES0, ^PM01._LEN,M1LN) + + ///Get dBMBOUND Base + And(BMBD, 0xFF000000, M1MN) + + // Calculate Length + Add(Subtract(M1MX, M1MN), 1, M1LN) + + + Return(RES0) +} + +Name( RES0,ResourceTemplate() { + WORDBusNumber ( // Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity + 0x0000, // Min + 0x00FF, // Max + 0x0000, // Translation + 0x0100 // Range Length = Max-Min+1 + ) + + IO (Decode16, 0x70, 0x77, 0x01, 0x08) //Consumed resource (0xCF8-0xCFF) + IO (Decode16, 0xCF8, 0xCF8, 0x01, 0x08) //Consumed resource (0xCF8-0xCFF) + + WORDIO ( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity + 0x0000, // Min + 0x006F, // Max + 0x0000, // Translation + 0x0070 // Range Length + ) + + WORDIO ( // Consumed-and-produced resource + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity + 0x0078, // Min + 0x0CF7, // Max + 0x0000, // Translation + 0x0C80 // Range Length + ) + + WORDIO ( // Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity + 0x0D00, // Min + 0xFFFF, // Max + 0x0000, // Translation + 0xF300 // Range Length + ) + + DWORDMEMORY ( // Descriptor for legacy VGA video RAM + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Min + 0x000BFFFF, // Max + 0x00000000, // Translation + 0x00020000 // Range Length + ) + + DWORDMEMORY ( // Descriptor for legacy OptionRom + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x000C0000, // Min + 0x000DFFFF, // Max + 0x00000000, // Translation + 0x00020000 // Range Length + ) + + DWORDMEMORY ( // Descriptor for BIOS Area + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x000E0000, // Min + 0x000FFFFF, // Max + 0x00000000, // Translation + 0x00020000 // Range Length + ) + + DWORDMEMORY ( // Descriptor for LPEA Area + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x20000000, // Min + 0x201FFFFF, // Max + 0x00000000, // Translation + 0x00200000 // Range Length + ,,, + LPA0 + ) + + DWORDMEMORY ( // Descriptor for ISP0 reserved Mem + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x7A000000, // Min + 0x7A3FFFFF, // Max + 0x00000000, // Translation + 0x00400000 // Range Length + ,,, + ISP0 + ) + + DWORDMEMORY ( // Descriptor for PCI MMIO + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x80000000, // Min + 0xDFFFFFFF, // Max + 0x00000000, // Translation + 0x60000000 // Range Length + ,,, + PM01 + ) + +}) + +//Name(GUID,UUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) +Name(GUID,Buffer(){0x5b, 0x4d, 0xdb, 0x33, + 0xf7, 0x1f, + 0x1c, 0x40, + 0x96, 0x57, + 0x74, 0x41, 0xc0, 0x3d, 0xd7, 0x66}) + + +Name(SUPP,0) // PCI _OSC Support Field value +Name(CTRL,0) // PCI _OSC Control Field value + +Method(_OSC,4,Serialized) +{ // Check for proper UUID + // Save the capabilities buffer + Store(Arg3,Local0) + + // Create DWord-adressable fields from the Capabilties Buffer + CreateDWordField(Local0,0,CDW1) + CreateDWordField(Local0,4,CDW2) + CreateDWordField(Local0,8,CDW3) + + // Check for proper UUID + If(LAnd(LEqual(Arg0,GUID),NEXP)) + { + // Save Capabilities DWord2 & 3 + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // You can clear bits in CTRL here if you don't want OS to take + // control + +// And(CTRL, 0xFFFFFFF8, CTRL) // disable Native hot plug, PME + + If(Not(And(CDW1,1))) // Query flag clear? + { // Disable GPEs for features granted native control. + If(And(CTRL,0x02)) + { + NHPG() + } + If(And(CTRL,0x04)) // PME control granted? + { + NPME() + } + } + + If(LNotEqual(Arg1,One)) + { // Unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) + { // Capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // Update DWORD3 in the buffer + Store(CTRL,CDW3) + Store(CTRL,OSCC) + Return(Local0) + } Else { + Or(CDW1,4,CDW1) // Unrecognized UUID + Return(Local0) + } +} // End _OSC diff --git a/ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/IgdOpGbda.asl b/ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/IgdOpGbda.asl new file mode 100644 index 0000000000..2aebdd1009 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/IgdOpGbda.asl @@ -0,0 +1,153 @@ +/** @file + ACPI DSDT table + IGD OpRegion/Software SCI Reference Code for the CherryView Family. + This file contains Get BIOS Data Area funciton support for the + Integrated Graphics Device (IGD) OpRegion/Software SCI mechanism. + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + +Method (GBDA, 0, Serialized) +{ + + // Supported calls: Sub-function 0 + + If (LEqual(GESF, 0)) + { + // Update implementation specific supported calls. Reference + // code is set to Intel's validated implementation. + + Store(0x0000279, PARM) + + Store(Zero, GESF) // Clear the exit parameter + Return(SUCC) // Success + } + + // Requested callbacks: Sub-function 1 + + If (LEqual(GESF, 1)) + { + + // Update implementation specific system BIOS requested call + // back functions. Call back functions are where the driver calls the + // system BIOS at function indicated event. + + Store(0x00000240, PARM) + + Store(Zero, GESF) // Clear the exit parameter + Return(SUCC) // Success + } + + // Get Boot display Preferences: Sub-function 4 + + If (LEqual(GESF, 4)) + { + + // Update the implementation specific Get Boot Display + // Preferences function. + + And(PARM, 0xEFFF0000, PARM) // PARM[30:16] = Boot device ports + And(PARM, ShiftLeft(DeRefOf(Index(DBTB, IBTT)), 16), PARM) + Or(IBTT, PARM, PARM) // PARM[7:0] = Boot device type + + Store(Zero, GESF) // Clear the exit parameter + Return(SUCC) // Success + } + + // Panel details: Sub-function 5 + + If (LEqual(GESF, 5)) + { + + // Update the implementation specific Get Panel Details + // function. + + Store(IPSC, PARM) // Report the scaling setting + Or(PARM, ShiftLeft(IPAT, 8), PARM) + Add(PARM, 0x100, PARM) // Adjust panel type, 0 = VBT default + Or(PARM, ShiftLeft(LIDS, 16), PARM) // Report the lid state + Add(PARM, 0x10000, PARM) // Adjust the lid state, 0 = Unknown + Or(PARM, ShiftLeft(IBLC, 18), PARM) // Report the BLC setting + Or(PARM, ShiftLeft(IBIA, 20), PARM) // Report the BIA setting + Store(Zero, GESF) + Return(SUCC) + } + + // TV-standard/Video-connector: Sub-function 6 + + If (LEqual(GESF, 6)) + { + + // Update the implementation specific Get + // TV-standard/Video-connectorPanel function. + + Store(ITVF, PARM) + Or(PARM, ShiftLeft(ITVM, 4), PARM) + Store(Zero, GESF) + Return(SUCC) + } + + // Internal graphics: Sub-function 7 + + If (LEqual(GESF, 7)) + { + Store(GIVD, PARM) // PARM[0] - VGA mode(1=VGA) + Xor(PARM, 1, PARM) // Invert the VGA mode polarity + Or(PARM, ShiftLeft(GMFN, 1), PARM) // PARM[1] - # IGD PCI functions-1 + // PARM[3:2] - Reserved + // PARM[4] - IGD D3 support(0=cold) + // PARM[10:5] - Reserved + Or(PARM, ShiftLeft(3, 11), PARM) // PARM[12:11] - DVMT mode(11b = 5.0) + + // + // Report DVMT 5.0 Total Graphics memory size. + // + Or(PARM, ShiftLeft(IDMS, 17), PARM) // Bits 20:17 are for Gfx total memory size + + // If the "Set Internal Graphics" call is supported, the modified + // settings flag must be programmed per the specification. This means + // that the flag must be set to indicate that system BIOS requests + // these settings. Once "Set Internal Graphics" is called, the + // modified settings flag must be cleared on all subsequent calls to + // this function. + + // Report the graphics frequency based on DISPLAY_CLOCK_FREQUENCY_ENCODING [MMADR+0x20C8] + + Or(ShiftLeft(Derefof(Index(CDCT, DCFE)), 21),PARM, PARM) + + Store(1, GESF) // Set the modified settings flag + Return(SUCC) + } + + // Spread spectrum clocks: Sub-function 10 + + If (LEqual(GESF, 10)) + { + + Store(0, PARM) // Assume SSC is disabled + + If(ISSC) + { + Or(PARM, 3, PARM) // If SSC enabled, return SSC1+Enabled + } + + Store(0, GESF) // Set the modified settings flag + Return(SUCC) // Success + } + + + // A call to a reserved "Get BIOS data" function was received. + + Store(Zero, GESF) // Clear the exit parameter + Return(CRIT) // Reserved, "Critical failure" +} diff --git a/ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/IgdOpMobf.asl b/ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/IgdOpMobf.asl new file mode 100644 index 0000000000..bd52b4d91e --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/IgdOpMobf.asl @@ -0,0 +1,483 @@ +/** @file + ACPI DSDT table + IGD OpRegion/Software SCI Reference Code for the CherryView Family. + This file contains ASL code with the purpose of handling events + i.e. hotkeys and other system interrupts. + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + +// Notes: +// 1. The following routines are to be called from the appropriate event +// handlers. +// 2. This code cannot comprehend the exact implementation in the OEM's BIOS. +// Therefore, an OEM must call these methods from the existing event +// handler infrastructure. Details on when/why to call each method is +// included in the method header under the "usage" section. + + +/************************************************************************; +;* ACPI Notification Methods +;************************************************************************/ + + +/************************************************************************; +;* +;* Name: PDRD +;* +;* Description: Check if the graphics driver is ready to process +;* notifications and video extensions. +;* +;* Usage: This method is to be called prior to performing any +;* notifications or handling video extensions. +;* Ex: If (PDRD()) {Return (FAIL)} +;* +;* Input: None +;* +;* Output: None +;* +;* References: DRDY (Driver ready status), ASLP (Driver recommended +;* sleep timeout value). +;* +;************************************************************************/ + +Method(PDRD) +{ + If(LNot(DRDY)) + { + + // Sleep for ASLP milliseconds if the driver is not ready. + + Sleep(ASLP) + } + + // If DRDY is clear, the driver is not ready. If the return value is + // !=0, do not perform any notifications or video extension handling. + + Return(LNot(DRDY)) +} + + +/************************************************************************; +;* +;* Name: PSTS +;* +;* Description: Check if the graphics driver has completed the previous +;* "notify" command. +;* +;* Usage: This method is called before every "notify" command. A +;* "notify" should only be set if the driver has completed the +;* previous command. Else, ignore the event and exit the parent +;* method. +;* Ex: If (PSTS()) {Return (FAIL)} +;* +;* Input: None +;* +;* Output: None +;* +;* References: CSTS (Notification status), ASLP (Driver recommended sleep +;* timeout value). +;* +;************************************************************************/ + +Method(PSTS) +{ + If(LGreater(CSTS, 2)) + { + // Sleep for ASLP milliseconds if the status is not "success, + // failure, or pending" + // + Sleep(ASLP) + } + + Return(LEqual(CSTS, 3)) // Return True if still Dispatched +} + + +/************************************************************************; +;* +;* Name: GNOT +;* +;* Description: Call the appropriate methods to query the graphics driver +;* status. If all methods return success, do a notification of +;* the graphics device. +;* +;* Usage: This method is to be called when a graphics device +;* notification is required (display switch hotkey, etc). +;* +;* Input: Arg0 = Current event type: +;* 1 = display switch +;* 2 = lid +;* 3 = dock +;* Arg1 = Notification type: +;* 0 = Re-enumeration +;* 0x80 = Display switch +;* +;* Output: Returns 0 = success, 1 = failure +;* +;* References: PDRD and PSTS methods. OSYS (OS version) +;* +;************************************************************************/ + +Method(GNOT, 2) +{ + // Check for 1. Driver loaded, 2. Driver ready. + // If any of these cases is not met, skip this event and return failure. + // + If(PDRD()) + { + Return(0x1) // Return failure if driver not loaded. + } + + Store(Arg0, CEVT) // Set up the current event value + Store(3, CSTS) // CSTS=BIOS dispatched an event + + If(LAnd(LEqual(CHPD, 0), LEqual(Arg1, 0))) // Do not re-enum if driver supports hotplug + { + If(LOr(LGreater(OSYS, 2000), LLess(OSYS, 2006))) + { + // + // WINXP requires that the entire PCI Bridge be re-enumerated. + // + Notify(\_SB.PCI0, Arg1) + } + Else + { + // + // Re-enumerate the Graphics Device for non-XP operating systems. + // + Notify(\_SB.PCI0.GFX0, Arg1) + } + } + + Notify(\_SB.PCI0.GFX0,0x80) + + + Return(0x0) // Return success +} + + +/************************************************************************; +;* +;* Name: GHDS +;* +;* Description: Handle a hotkey display switching event (performs a +;* Notify(GFX0, 0). +;* +;* Usage: This method must be called when a hotkey event occurs and the +;* purpose of that hotkey is to do a display switch. +;* +;* Input: Arg0 = Toggle table number. +;* +;* Output: Returns 0 = success, 1 = failure. +;* CEVT and TIDX are indirect outputs. +;* +;* References: TIDX, GNOT +;* +;************************************************************************/ + +Method(GHDS, 1) +{ + Store(Arg0, TIDX) // Store the table number + + // Call GNOT for CEVT = 1 = hotkey, notify value = 0 + + Return(GNOT(1, 0)) // Return stats from GNOT +} + + +/************************************************************************; +;* +;* Name: GLID +;* +;* Description: Handle a lid event (performs the Notify(GFX0, 0), but not the +;* lid notify). +;* +;* Usage: This method must be called when a lid event occurs. A +;* Notify(LID0, 0x80) must follow the call to this method. +;* +;* Input: Arg0 = Lid state: +;* 0 = All closed +;* 1 = internal LFP lid open +;* 2 = external lid open +;* 3 = both external and internal open +;* +;* Output: Returns 0=success, 1=failure. +;* CLID and CEVT are indirect outputs. +;* +;* References: CLID, GNOT +;* +;************************************************************************/ + +Method(GLID, 1) +{ + Store(Arg0, CLID) // Store the current lid state + + // Call GNOT for CEVT=2=Lid, notify value = 0 + + Return(GNOT(2, 0)) // Return stats from GNOT +} + + +/************************************************************************; +;* +;* Name: GDCK +;* +;* Description: Handle a docking event by updating the current docking status +;* and doing a notification. +;* +;* Usage: This method must be called when a docking event occurs. +;* +;* Input: Arg0 = Docking state: +;* 0 = Undocked +;* 1 = Docked +;* +;* Output: Returns 0=success, 1=failure. +;* CDCK and CEVT are indirect outputs. +;* +;* References: CDCK, GNOT +;* +;************************************************************************/ + +Method(GDCK, 1) +{ + Store(Arg0, CDCK) // Store the current dock state + + // Call GNOT for CEVT=4=Dock, notify value = 0 + + Return(GNOT(4, 0)) // Return stats from GNOT +} + + +/************************************************************************; +;* ASLE Interrupt Methods +;************************************************************************/ + + +/************************************************************************; +;* +;* Name: PARD +;* +;* Description: Check if the driver is ready to handle ASLE interrupts +;* generate by the system BIOS. +;* +;* Usage: This method must be called before generating each ASLE +;* interrupt. +;* +;* Input: None +;* +;* Output: Returns 0 = success, 1 = failure. +;* +;* References: ARDY (Driver readiness), ASLP (Driver recommended sleep +;* timeout value) +;* +;************************************************************************/ + +Method(PARD) +{ + If(LNot(ARDY)) + { + + // Sleep for ASLP milliseconds if the driver is not ready. + + Sleep(ASLP) + } + + // If ARDY is clear, the driver is not ready. If the return value is + // !=0, do not generate the ASLE interrupt. + + Return(LNot(ARDY)) +} + + +/************************************************************************; +;* +;* Name: AINT +;* +;* Description: Call the appropriate methods to generate an ASLE interrupt. +;* This process includes ensuring the graphics driver is ready +;* to process the interrupt, ensuring the driver supports the +;* interrupt of interest, and passing information about the event +;* to the graphics driver. +;* +;* Usage: This method must called to generate an ASLE interrupt. +;* +;* Input: Arg0 = ASLE command function code: +;* 0 = Set ALS illuminance +;* 1 = Set backlight brightness +;* 2 = Do Panel Fitting +;* Arg1 = If Arg0 = 0, current ALS reading: +;* 0 = Reading below sensor range +;* 1-0xFFFE = Current sensor reading +;* 0xFFFF = Reading above sensor range +;* Arg1 = If Arg0 = 1, requested backlight percentage +;* +;* Output: Returns 0 = success, 1 = failure +;* +;* References: PARD method. +;* +;************************************************************************/ + +Method(AINT, 2) +{ + + // Return failure if the requested feature is not supported by the + // driver. + + If(LNot(And(TCHE, ShiftLeft(1, Arg0)))) + { + Return(0x1) + } + + // Return failure if the driver is not ready to handle an ASLE + // interrupt. + + If(PARD()) + { + Return(0x1) + } + + // Evaluate the first argument (Panel fitting, backlight brightness, or ALS). + + If(LEqual(Arg0, 2)) // Arg0 = 2, so request a panel fitting mode change. + { + If(CPFM) // If current mode field is non-zero use it. + { + And(CPFM, 0x0F, Local0) // Create variables without reserved + And(EPFM, 0x0F, Local1) // or valid bits. + + If(LEqual(Local0, 1)) // If current mode is centered, + { + If(And(Local1, 6)) // and if stretched is enabled, + { + Store(6, PFIT) // request stretched. + } + Else // Otherwise, + { + If(And(Local1, 8)) // if aspect ratio is enabled, + { + Store(8, PFIT) // request aspect ratio. + } + Else // Only centered mode is enabled + { + Store(1, PFIT) // so request centered. (No change.) + } + } + } + If(LEqual(Local0, 6)) // If current mode is stretched, + { + If(And(Local1, 8)) // and if aspect ratio is enabled, + { + Store(8, PFIT) // request aspect ratio. + } + Else // Otherwise, + { + If(And(Local1, 1)) // if centered is enabled, + { + Store(1, PFIT) // request centered. + } + Else // Only stretched mode is enabled + { + Store(6, PFIT) // so request stretched. (No change.) + } + } + } + If(LEqual(Local0, 8)) // If current mode is aspect ratio, + { + If(And(Local1, 1)) // and if centered is enabled, + { + Store(1, PFIT) // request centered. + } + Else // Otherwise, + { + If(And(Local1, 6)) // if stretched is enabled, + { + Store(6, PFIT) // request stretched. + } + Else // Only aspect ratio mode is enabled + { + Store(8, PFIT) // so request aspect ratio. (No change.) + } + } + } + } + + // The following code for panel fitting (within the Else condition) is retained for backward compatiblity. + + Else // If CFPM field is zero use PFIT and toggle the + { + Xor(PFIT,7,PFIT) // mode setting between stretched and centered only. + } + + Or(PFIT,0x80000000,PFIT) // Set the valid bit for all cases. + + Store(4, ASLC) // Store "Panel fitting event" to ASLC[31:1] + } + Else + { + If(LEqual(Arg0, 1)) // Arg0=1, so set the backlight brightness. + { + Store(Divide(Multiply(Arg1, 255), 100), BCLP) // Convert from percent to 0-255. + + Or(BCLP, 0x80000000, BCLP) // Set the valid bit. + + Store(2, ASLC) // Store "Backlight control event" to ASLC[31:1] + } + Else + { + If(LEqual(Arg0, 0)) // Arg0=0, so set the ALS illuminace + { + Store(Arg1, ALSI) + + Store(1, ASLC) // Store "ALS event" to ASLC[31:1] + } + Else + { + Return(0x1) // Unsupported function + } + } + } + + Store(0x01, ASLE) // Generate ASLE interrupt + Return(0x0) // Return success +} + + +/************************************************************************; +;* +;* Name: SCIP +;* +;* Description: Checks the presence of the OpRegion and SCI +;* +;* Usage: This method is called before other OpRegion methods. The +;* former "GSMI True/False is not always valid. This method +;* checks if the OpRegion Version is non-zero and if non-zero, +;* (present and readable) then checks the GSMI flag. +;* +;* Input: None +;* +;* Output: Boolean True = SCI present. +;* +;* References: None +;* +;************************************************************************/ + +Method(SCIP) +{ + If(LNotEqual(OVER,0)) // If OpRegion Version not 0. + { + Return(LNot(GSMI)) // Return True if SCI. + } + + Return(0) // Else Return False. +} diff --git a/ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/IgdOpRn.ASL b/ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/IgdOpRn.ASL new file mode 100644 index 0000000000..528e1653f4 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/IgdOpRn.ASL @@ -0,0 +1,298 @@ +/** @file + ACPI DSDT table + IGD OpRegion/Software SCI Reference Code for the CherryView Family. + This file contains the interrupt handler code for the Integrated + Graphics Device (IGD) OpRegion/Software SCI mechanism. + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + +//NOTES: +// +// (1) The code contained in this file inherits the scope in which it +// was included. So BIOS developers must be sure to include this +// file in the scope associated with the graphics device +// (ex. \_SB.PCI0.GFX0). +// (2) Create a _L06 method under the GPE scope to handle the event +// generated by the graphics driver. The _L06 method must call +// the GSCI method in this file. +// (3) The MCHP operation region assumes that _ADR and _BBN names +// corresponding to bus 0, device0, function 0 have been declared +// under the PCI0 scope. +// (4) Before the first execution of the GSCI method, the base address +// of the GMCH SCI OpRegion must be programmed where the driver can +// access it. A 32bit scratch register at 0xFC in the IGD PCI +// configuration space (B0/D2/F0/R0FCh) is used for this purpose. + +// Define an OperationRegion to cover the GMCH PCI configuration space as +// described in the IGD OpRegion specificiation. + +// Define an OperationRegion to cover the IGD PCI configuration space as +// described in the IGD OpRegion specificiation. + +OperationRegion(IGDP, PCI_Config,0x00,0x100) +Field(IGDP, AnyAcc, NoLock, Preserve) +{ + Offset(0x00), // Device and Vendor ID + GVID, 32, + Offset(0x10), // GTTMMADR + MADR, 32, + Offset(0x50), // GMCH Graphics Control Register + , 1, + GIVD, 1, // IGD VGA disable bit + , 1, + GUMA, 5, // Stolen memory size + , 8, + Offset(0x54), + , 4, + GMFN, 1, // Gfx function 1 enable + , 27, + Offset(0x5C), // Stolen Memory Base Address + GSTM, 32, + Offset(0xE0), // Reg 0xE8, SWSCI control register + GSSE, 1, // Graphics SCI event (1=event pending) + GSSB, 14, // Graphics SCI scratchpad bits + GSES, 1, // Graphics event select (1=SCI) + Offset(0xE4), + ASLE, 8, // Reg 0xE4, ASLE interrupt register + , 24, // Only use first byte of ASLE reg + Offset(0xFC), + ASLS, 32, // Reg 0xFC, Address of the IGD OpRegion +} + +Method (GTTM, 0, Serialized) +{ + If (LEqual (GVID, 0xFFFFFFFF)) { + Return (ABTR) + } Else { + Return (MADR) + } +} + +OperationRegion(IGMM, SystemMemory, GTTM(), 0x3000) +Field(IGMM,AnyAcc, NoLock, Preserve) +{ + Offset(0X20C8), + , 4, + DCFE, 4, // DISPLAY_CLOCK_FREQUENCY_ENCODING +} + +// Define an OperationRegion to cover the IGD OpRegion layout. + +OperationRegion(IGDM, SystemMemory, ASLB, 0x2000) +Field(IGDM, AnyAcc, NoLock, Preserve) +{ + + // OpRegion Header + + SIGN, 128, // Signature-"IntelGraphicsMem" + SIZE, 32, // OpRegion Size + OVER, 32, // OpRegion Version + SVER, 256, // System BIOS Version + VVER, 128, // VBIOS Version + GVER, 128, // Driver version + MBOX, 32, // Mailboxes supported + DMOD, 32, // Driver Model + + // OpRegion Mailbox 1 (Public ACPI Methods) + // Note: Mailbox 1 is normally reserved for desktop platforms. + + Offset(0x100), + DRDY, 32, // Driver readiness (ACPI notification) + CSTS, 32, // Notification status + CEVT, 32, // Current event + Offset(0x120), + DIDL, 32, // Supported display device ID list + DDL2, 32, // Allows for 8 devices + DDL3, 32, + DDL4, 32, + DDL5, 32, + DDL6, 32, + DDL7, 32, + DDL8, 32, + CPDL, 32, // Currently present display list + CPL2, 32, // Allows for 8 devices + CPL3, 32, + CPL4, 32, + CPL5, 32, + CPL6, 32, + CPL7, 32, + CPL8, 32, + CAD1, 32, // Currently active display list + CAL2, 32, // Allows for 8 devices + CAL3, 32, + CAL4, 32, + CAL5, 32, + CAL6, 32, + CAL7, 32, + CAL8, 32, + NADL, 32, // Next active display list + NDL2, 32, // Allows for 8 devices + NDL3, 32, + NDL4, 32, + NDL5, 32, + NDL6, 32, + NDL7, 32, + NDL8, 32, + ASLP, 32, // ASL sleep timeout + TIDX, 32, // Toggle table index + CHPD, 32, // Current hot plug enable indicator + CLID, 32, // Current lid state indicator + CDCK, 32, // Current docking state indicator + SXSW, 32, // Display switch notify on resume + EVTS, 32, // Events supported by ASL (diag only) + CNOT, 32, // Current OS notifications (diag only) + NRDY, 32, + + // OpRegion Mailbox 2 (Software SCI Interface) + + Offset(0x200), // SCIC + SCIE, 1, // SCI entry bit (1=call unserviced) + GEFC, 4, // Entry function code + GXFC, 3, // Exit result + GESF, 8, // Entry/exit sub-function/parameter + , 16, // SCIC[31:16] reserved + Offset(0x204), // PARM + PARM, 32, // PARM register (extra parameters) + DSLP, 32, // Driver sleep time out + + // OpRegion Mailbox 3 (BIOS to Driver Notification) + // Note: Mailbox 3 is normally reserved for desktop platforms. + + Offset(0x300), + ARDY, 32, // Driver readiness (power conservation) + ASLC, 32, // ASLE interrupt command/status + TCHE, 32, // Technology enabled indicator + ALSI, 32, // Current ALS illuminance reading + BCLP, 32, // Backlight brightness + PFIT, 32, // Panel fitting state or request + CBLV, 32, // Current brightness level + BCLM, 320, // Backlight brightness level duty cycle mapping table + CPFM, 32, // Current panel fitting mode + EPFM, 32, // Enabled panel fitting modes + PLUT, 592, // Optional. 74-byte Panel LUT Table + PFMB, 32, // Optional. PWM Frequency and Minimum Brightness + CCDV, 32, // Optional. Gamma, Brightness, Contrast values. + PCFT, 32, // Optional. Power Conservation Features + + // OpRegion Mailbox 4 (VBT) + + Offset(0x400), + GVD1, 0xC000, // 6K bytes maximum VBT image + + // OpRegion Mailbox 5 (BIOS to Driver Notification Extension) + + Offset(0x1C00), + PHED, 32, // Panel Header + BDDC, 2048, // Panel EDID (Max 256 bytes) + +} + + + +// Convert boot display type into a port mask. + +Name (DBTB, Package() +{ + 0x0000, // Automatic + 0x0007, // Port-0 : Integrated CRT + 0x0038, // Port-1 : DVO-A, or Integrated LVDS + 0x01C0, // Port-2 : SDVO-B, or SDVO-B/C + 0x0E00, // Port-3 : SDVO-C + 0x003F, // [CRT + DVO-A / Integrated LVDS] + 0x01C7, // [CRT + SDVO-B] or [CRT + SDVO-B/C] + 0x0E07, // [CRT + SDVO-C] + 0x01F8, // [DVO-A / Integrated LVDS + SDVO-B] + 0x0E38, // [DVO-A / Integrated LVDS + SDVO-C] + 0x0FC0, // [SDVO-B + SDVO-C] + 0x0000, // Reserved + 0x0000, // Reserved + 0x0000, // Reserved + 0x0000, // Reserved + 0x0000, // Reserved + 0x7000, // Port-4: Integrated TV + 0x7007, // [Integrated TV + CRT] + 0x7038, // [Integrated TV + LVDS] + 0x71C0, // [Integrated TV + DVOB] + 0x7E00 // [Integrated TV + DVOC] +}) + +// Core display clock value table. + +Name (CDCT, Package() +{ + Package() {160}, + Package() {200}, + Package() {267}, + Package() {320}, + Package() {356}, + Package() {400}, +}) + +// Defined exit result values: + +Name (SUCC, 1) // Exit result: Success +Name (NVLD, 2) // Exit result: Invalid parameter +Name (CRIT, 4) // Exit result: Critical failure +Name (NCRT, 6) // Exit result: Non-critical failure + + +/************************************************************************; +;* +;* Name: GSCI +;* +;* Description: Handles an SCI generated by the graphics driver. The +;* PARM and SCIC input fields are parsed to determine the +;* functionality requested by the driver. GBDA or SBCB +;* is called based on the input data in SCIC. +;* +;* Usage: The method must be called in response to a GPE 06 event +;* which will be generated by the graphics driver. +;* Ex: Method(\_GPE._L06) {Return(\_SB.PCI0.GFX0.GSCI())} +;* +;* Input: PARM and SCIC are indirect inputs +;* +;* Output: PARM and SIC are indirect outputs +;* +;* References: GBDA (Get BIOS Data method), SBCB (System BIOS Callback +;* method) +;* +;************************************************************************/ + +Method (GSCI, 0, Serialized) +{ + Include("SystemAgent/IgdOpGbda.asl") // "Get BIOS Data" Functions + Include("SystemAgent/IgdOpSbcb.asl") // "System BIOS CallBacks" + + If (LNotEqual(GVID, 0xFFFFFFFF)) { + If (LEqual(GEFC, 4)) + { + Store(GBDA(), GXFC) // Process Get BIOS Data functions + } + + If (LEqual(GEFC, 6)) + { + Store(SBCB(), GXFC) // Process BIOS Callback functions + } + + Store(0, GEFC) // Wipe out the entry function code + Store(0, GSSE) // Clear the SCI generation bit in PCI space. + Store(0, SCIE) // Clr SCI serviced bit to signal completion + } + Store(1, SCIS) // Clear the GUNIT SCI status bit in PCH ACPI I/O space. + + Return(Zero) +} + +// Include MOBLFEAT.ASL for mobile systems only. Remove for desktop. +Include("SystemAgent/IgdOpMobf.asl") // IGD SCI mobile features diff --git a/ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/IgdOpSbcb.asl b/ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/IgdOpSbcb.asl new file mode 100644 index 0000000000..72ee150898 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/IgdOpSbcb.asl @@ -0,0 +1,287 @@ +/** @file + ACPI DSDT table + IGD OpRegion/Software SCI Reference Code for the CherryView Family. + This file contains the system BIOS call back functionality for the + OpRegion/Software SCI mechanism. + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + +Method (SBCB, 0, Serialized) +{ + + // Supported Callbacks: Sub-function 0 + + If (LEqual(GESF, 0x0)) + { + + // An OEM may support the driver->SBIOS status callbacks, but + // the supported callbacks value must be modified. The code that is + // executed upon reception of the callbacks must be also be updated + // to perform the desired functionality. + + Store(0x00000000, PARM) // No callbacks supported + //Store(0x000787FD, PARM) // Used for Intel test implementaion + + // + + If(LEqual(PFLV,FMBL)) + { + Store(0x000F87FD, PARM) // Mobile + } + If(LEqual(PFLV,FDTP)) + { + Store(0x000F87BD, PARM) // Desktop + } + + // + + Store(Zero, GESF) // Clear the exit parameter + Return(SUCC) // "Success" + } + + // BIOS POST Completion: Sub-function 1 + + If (LEqual(GESF, 1)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // Pre-Hires Set Mode: Sub-function 3 + + If (LEqual(GESF, 3)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // Post-Hires Set Mode: Sub-function 4 + + If (LEqual(GESF, 4)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // Display Switch: Sub-function 5 + + If (LEqual(GESF, 5)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // Set TV format: Sub-function 6 + + If (LEqual(GESF, 6)) + { + + // If implemented, the input values must be saved into + // non-volatile storage for parsing during the next boot. The + // following Sample code is Intel validated implementation. + + Store(And(PARM, 0x0F), ITVF) + Store(ShiftRight(And(PARM, 0xF0), 4), ITVM) + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) + } + + // Adapter Power State: Sub-function 7 + + If (LEqual(GESF, 7)) + { + + // Upon notification from driver that the Adapter Power State = D0, + // check if previous lid event failed. If it did, retry the lid + // event here. + If(LEqual(PARM, 0)) + { + Store(CLID, Local0) + If(And(0x80000000,Local0)) + { + And(CLID, 0x0000000F, CLID) + GLID(CLID) + } + } + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // Display Power State: Sub-function 8 + + If (LEqual(GESF, 8)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // Set Boot Display: Sub-function 9 + + If (LEqual(GESF, 9)) + { + + // An OEM may elect to implement this method. In that case, + // the input values must be saved into non-volatile storage for + // parsing during the next boot. The following Sample code is Intel + // validated implementation. + + And(PARM, 0xFF, IBTT) // Save the boot display to NVS + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Reserved, "Critical failure" + } + + // Set Panel Details: Sub-function 10 (0Ah) + + If (LEqual(GESF, 10)) + { + + // An OEM may elect to implement this method. In that case, + // the input values must be saved into non-volatile storage for + // parsing during the next boot. The following Sample code is Intel + // validated implementation. + + // Set the panel-related NVRAM variables based the input from the driver. + + And(PARM, 0xFF, IPSC) + + // Change panel type if a change is requested by the driver (Change if + // panel type input is non-zero). Zero=No change requested. + + If(And(ShiftRight(PARM, 8), 0xFF)) + { + And(ShiftRight(PARM, 8), 0xFF, IPAT) + Decrement(IPAT) // 0 = no change, so fit to CMOS map + } + And(ShiftRight(PARM, 18), 0x3, IBLC) + And(ShiftRight(PARM, 20), 0x7, IBIA) + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Success + } + + // Set Internal Graphics: Sub-function 11 (0Bh) + + If (LEqual(GESF, 11)) + { + + // An OEM may elect to implement this method. In that case, + // the input values must be saved into non-volatile storage for + // parsing during the next boot. The following Sample code is Intel + // validated implementation. + + And(ShiftRight(PARM, 1), 1, IF1E) // Program the function 1 option + + //If(And(PARM, ShiftLeft(0xF, 13))) // Use fixed memory if fixed size != 0 + //{ + + // Fixed memory + + //And(ShiftRight(PARM, 13), 0xF, IDMS) // Program fixed memory size + //} + //Else + //{ + + // Fixed memory/DVMT memory + + And(ShiftRight(PARM, 17), 0xF, IDMS) // Program DVMT/fixed memory size + //} + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Success + } + + // Post-Hires to DOS FS: Sub-function 16 (10h) + + If (LEqual(GESF, 16)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // APM Complete: Sub-function 17 (11h) + + If (LEqual(GESF, 17)) + { + + Store(ShiftLeft(LIDS, 8), PARM) // Report the lid state + Add(PARM, 0x100, PARM) // Adjust the lid state, 0 = Unknown + + Store(Zero, GESF) // Clear the exit parameter + Return(SUCC) // Not supported, but no failure + } + + // Set Spread Spectrum Clocks: Sub-function 18 (12h) + + If (LEqual(GESF, 18)) + { + + // An OEM may elect to implement this method. In that case, + // the input values must be saved into non-volatile storage for + // parsing during the next boot. The following Sample code is Intel + // validated implementation. + + If(And(PARM, 1)) + { + If(LEqual(ShiftRight(PARM, 1), 1)) + { + Store(1, ISSC) // Enable HW SSC, only for clock 1 + } + Else + { + Store(Zero, GESF) + Return(CRIT) // Failure, as the SSC clock must be 1 + } + } + Else + { + Store(0, ISSC) // Disable SSC + } + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Success + } + + // Post VBE/PM Callback: Sub-function 19 (13h) + + If (LEqual(GESF, 19)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // Set PAVP Data: Sub-function 20 (14h) + + If (LEqual(GESF, 20)) + { + And(PARM, 0xF, PAVP) // Store PAVP info + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Success + } + + // A call to a reserved "System BIOS callbacks" function was received + + Store(Zero, GESF) // Clear the exit parameter + Return(SUCC) // Reserved, "Critical failure" +} diff --git a/ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/IntelGraphics.asl b/ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/IntelGraphics.asl new file mode 100644 index 0000000000..d7e45fd7b2 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/IntelGraphics.asl @@ -0,0 +1,1009 @@ +/** @file + ACPI DSDT table + IGD OpRegion/Software ACPI Reference Code for the CherryView Family. + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +//Device(GFX0) +//{ +// Name(_ADR, 0x00020000) + + // Enable/Disable Output Switching. In WIN2K/WINXP, _DOS = 0 will + // get called during initialization to prepare for an ACPI Display + // Switch Event. During an ACPI Display Switch, the OS will call + // _DOS = 2 immediately after a Notify=0x80 to temporarily disable + // all Display Switching. After ACPI Display Switching is complete, + // the OS will call _DOS = 0 to re-enable ACPI Display Switching. + + Method(_DOS,1) + { + // Store Display Switching and LCD brightness BIOS control bit + Store(And(Arg0,7),DSEN) + } + + // Enumerate the Display Environment. This method will return + // valid addresses for all display device encoders present in the + // system. The Miniport Driver will reject the addresses for every + // encoder that does not have an attached display device. After + // enumeration is complete, the OS will call the _DGS methods + // during a display switch only for the addresses accepted by the + // Miniport Driver. For hot-insertion and removal of display + // devices, a re-enumeration notification will be required so the + // address of the newly present display device will be accepted by + // the Miniport Driver. + + Method(_DOD,0) + { + If (LEqual(ISPE,1)) { + // + // Increment number of devices if ISP is enabled + // + Store(1, NDID) + } Else { + Store(0, NDID) + } + If(LNotEqual(DIDL, Zero)) + { + Store(SDDL(DIDL),DID1) + } + If(LNotEqual(DDL2, Zero)) + { + Store(SDDL(DDL2),DID2) + } + If(LNotEqual(DDL3, Zero)) + { + Store(SDDL(DDL3),DID3) + } + If(LNotEqual(DDL4, Zero)) + { + Store(SDDL(DDL4),DID4) + } + If(LNotEqual(DDL5, Zero)) + { + Store(SDDL(DDL5),DID5) + } + If(LNotEqual(DDL6, Zero)) + { + Store(SDDL(DDL6),DID6) + } + If(LNotEqual(DDL7, Zero)) + { + Store(SDDL(DDL7),DID7) + } + If(LNotEqual(DDL8, Zero)) + { + Store(SDDL(DDL8),DID8) + } + + // TODO - This level of flexibility is not needed for a true + // OEM design. Simply determine the greatest number of + // encoders the platform will suppport then remove all + // return packages beyond that value. Note that for + // current silicon, the maximum number of encoders + // possible is 8. + + If(LEqual(NDID,1)) + { + Name(TMP1,Package() { + 0xFFFFFFFF}) + If (LEqual(ISPE,1)) { + // + // IGFX need report ISP Device as GFX0 child + // + Store(0x000222B8,Index(TMP1,0)) + } Else { + Store(Or(0x10000,DID1),Index(TMP1,0)) + } + Return(TMP1) + } + + If(LEqual(NDID,2)) + { + Name(TMP2,Package() { + 0xFFFFFFFF, + 0xFFFFFFFF}) + If (LEqual(ISPE,1)) { + // + // IGFX need report ISP Device as GFX0 child + // + Store(Or(0x10000,DID1),Index(TMP2,0)) + Store(0x000222B8,Index(TMP2,1)) + } Else { + Store(Or(0x10000,DID1),Index(TMP2,0)) + Store(Or(0x10000,DID2),Index(TMP2,1)) + } + Return(TMP2) + } + + If(LEqual(NDID,3)) + { + Name(TMP3,Package() { + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + If (LEqual(ISPE,1)) { + // + // IGFX need report ISP Device as GFX0 child + // + Store(Or(0x10000,DID1),Index(TMP3,0)) + Store(Or(0x10000,DID2),Index(TMP3,1)) + Store(0x000222B8,Index(TMP3,2)) + } Else { + Store(Or(0x10000,DID1),Index(TMP3,0)) + Store(Or(0x10000,DID2),Index(TMP3,1)) + Store(Or(0x10000,DID3),Index(TMP3,2)) + } + Return(TMP3) + } + + If(LEqual(NDID,4)) + { + Name(TMP4,Package() { + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + If (LEqual(ISPE,1)) { + // + // IGFX need report ISP Device as GFX0 child + // + Store(Or(0x10000,DID1),Index(TMP4,0)) + Store(Or(0x10000,DID2),Index(TMP4,1)) + Store(Or(0x10000,DID3),Index(TMP4,2)) + Store(0x000222B8,Index(TMP4,3)) + } Else { + Store(Or(0x10000,DID1),Index(TMP4,0)) + Store(Or(0x10000,DID2),Index(TMP4,1)) + Store(Or(0x10000,DID3),Index(TMP4,2)) + Store(Or(0x10000,DID4),Index(TMP4,3)) + } + Return(TMP4) + } + + If(LEqual(NDID,5)) + { + Name(TMP5,Package() { + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + If (LEqual(ISPE,1)) { + // + // IGFX need report ISP Device as GFX0 child + // + Store(Or(0x10000,DID1),Index(TMP5,0)) + Store(Or(0x10000,DID2),Index(TMP5,1)) + Store(Or(0x10000,DID3),Index(TMP5,2)) + Store(Or(0x10000,DID4),Index(TMP5,3)) + Store(0x000222B8,Index(TMP5,4)) + } Else { + Store(Or(0x10000,DID1),Index(TMP5,0)) + Store(Or(0x10000,DID2),Index(TMP5,1)) + Store(Or(0x10000,DID3),Index(TMP5,2)) + Store(Or(0x10000,DID4),Index(TMP5,3)) + Store(Or(0x10000,DID5),Index(TMP5,4)) + } + Return(TMP5) + } + + If(LEqual(NDID,6)) + { + Name(TMP6,Package() { + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + If (LEqual(ISPE,1)) { + // + // IGFX need report ISP Device as GFX0 child + // + Store(Or(0x10000,DID1),Index(TMP6,0)) + Store(Or(0x10000,DID2),Index(TMP6,1)) + Store(Or(0x10000,DID3),Index(TMP6,2)) + Store(Or(0x10000,DID4),Index(TMP6,3)) + Store(Or(0x10000,DID5),Index(TMP6,4)) + Store(0x000222B8,Index(TMP6,5)) + } Else { + Store(Or(0x10000,DID1),Index(TMP6,0)) + Store(Or(0x10000,DID2),Index(TMP6,1)) + Store(Or(0x10000,DID3),Index(TMP6,2)) + Store(Or(0x10000,DID4),Index(TMP6,3)) + Store(Or(0x10000,DID5),Index(TMP6,4)) + Store(Or(0x10000,DID6),Index(TMP6,5)) + } + Return(TMP6) + } + + If(LEqual(NDID,7)) + { + Name(TMP7,Package() { + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + If (LEqual(ISPE,1)) { + // + // IGFX need report ISP Device as GFX0 child + // + Store(Or(0x10000,DID1),Index(TMP7,0)) + Store(Or(0x10000,DID2),Index(TMP7,1)) + Store(Or(0x10000,DID3),Index(TMP7,2)) + Store(Or(0x10000,DID4),Index(TMP7,3)) + Store(Or(0x10000,DID5),Index(TMP7,4)) + Store(Or(0x10000,DID6),Index(TMP7,5)) + Store(0x000222B8,Index(TMP7,6)) + } Else { + Store(Or(0x10000,DID1),Index(TMP7,0)) + Store(Or(0x10000,DID2),Index(TMP7,1)) + Store(Or(0x10000,DID3),Index(TMP7,2)) + Store(Or(0x10000,DID4),Index(TMP7,3)) + Store(Or(0x10000,DID5),Index(TMP7,4)) + Store(Or(0x10000,DID6),Index(TMP7,5)) + Store(Or(0x10000,DID7),Index(TMP7,6)) + } + Return(TMP7) + } + + If(LGreater(NDID,7)) + { + Name(TMP8,Package() { + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + If (LEqual(ISPE,1)) { + // + // IGFX need report ISP Device as GFX0 child + // + Store(Or(0x10000,DID1),Index(TMP8,0)) + Store(Or(0x10000,DID2),Index(TMP8,1)) + Store(Or(0x10000,DID3),Index(TMP8,2)) + Store(Or(0x10000,DID4),Index(TMP8,3)) + Store(Or(0x10000,DID5),Index(TMP8,4)) + Store(Or(0x10000,DID6),Index(TMP8,5)) + Store(Or(0x10000,DID7),Index(TMP8,6)) + Store(0x000222B8,Index(TMP8,7)) + } Else { + Store(Or(0x10000,DID1),Index(TMP8,0)) + Store(Or(0x10000,DID2),Index(TMP8,1)) + Store(Or(0x10000,DID3),Index(TMP8,2)) + Store(Or(0x10000,DID4),Index(TMP8,3)) + Store(Or(0x10000,DID5),Index(TMP8,4)) + Store(Or(0x10000,DID6),Index(TMP8,5)) + Store(Or(0x10000,DID7),Index(TMP8,6)) + Store(Or(0x10000,DID8),Index(TMP8,7)) + } + Return(TMP8) + } + + // If nothing else, return Unknown LFP. + // (Prevents compiler warning.) + + //Add ISP device to GFX0 + Return(Package() {0x00000400, + 0x000222B8}) + } + +Device(DD01) +{ + // + // Return Unique ID. + // + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID1),0x400)) + { + Store(0x1, EDPV) + Store(DID1, DIDX) + Return(1) + } + If(LEqual(DID1,0)) + { + Return(1) + } + Else + { + Return(And(0xFFFF,DID1)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + Return(CDDS(DID1)) + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + Return(NDDS(DID1)) + } + + // Device Set State. + + // _DSS Table: + // + // BIT31 BIT30 Execution + // 0 0 Don't implement. + // 0 1 Cache change. Nothing to Implement. + // 1 0 Don't Implement. + // 1 1 Display Switch Complete. Implement. + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } + } + +Device(DD02) +{ + // + // Return Unique ID. + // + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID2),0x400)) + { + Store(0x2, EDPV) + Store(DID2, DIDX) + Return(2) + } + If(LEqual(DID2,0)) + { + Return(2) + } + Else + { + Return(And(0xFFFF,DID2)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + Return(CDDS(DID2)) + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + // Return the Next State. + Return(NDDS(DID2)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } + } + +Device(DD03) +{ + // + // Return Unique ID. + // + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID3),0x400)) + { + Store(0x3, EDPV) + Store(DID3, DIDX) + Return(3) + } + If(LEqual(DID3,0)) + { + Return(3) + } + Else + { + Return(And(0xFFFF,DID3)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DID3,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID3)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + Return(NDDS(DID3)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } + + } + +Device(DD04) +{ + // + // Return Unique ID. + // + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID4),0x400)) + { + Store(0x4, EDPV) + Store(DID4, DIDX) + Return(4) + } + If(LEqual(DID4,0)) + { + Return(4) + } + Else + { + Return(And(0xFFFF,DID4)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DID4,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID4)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + Return(NDDS(DID4)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } + } + +Device(DD05) +{ + // + // Return Unique ID. + // + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID5),0x400)) + { + Store(0x5, EDPV) + Store(DID5, DIDX) + Return(5) + } + If(LEqual(DID5,0)) + { + Return(5) + } + Else + { + Return(And(0xFFFF,DID5)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DID5,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID5)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + Return(NDDS(DID5)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } + } + +Device(DD06) +{ + // + // Return Unique ID. + // + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID6),0x400)) + { + Store(0x6, EDPV) + Store(DID6, DIDX) + Return(6) + } + If(LEqual(DID6,0)) + { + Return(6) + } + Else + { + Return(And(0xFFFF,DID6)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DID6,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID6)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + Return(NDDS(DID6)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } + + } + + + Device(DD07) + { + + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID7),0x400)) + { + Store(0x7, EDPV) + Store(DID7, DIDX) + Return(7) + } + If(LEqual(DID7,0)) + { + Return(7) + } + Else + { + Return(And(0xFFFF,DID7)) + } + } + + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DID7,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID7)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + Return(NDDS(DID7)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } + } + + Device(DD08) + { + // + // Return Unique ID. + // + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID8),0x400)) + { + Store(0x8, EDPV) + Store(DID8, DIDX) + Return(8) + } + If(LEqual(DID8,0)) + { + Return(8) + } + Else + { + Return(And(0xFFFF,DID8)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DID8,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID8)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + Return(NDDS(DID8)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } + + } + + +// +//Device for eDP +// +Device(DD1F) +{ + // + // Return Unique ID. + // + Method(_ADR,0,Serialized) + { + If(LEqual(EDPV, 0x0)) + { + Return(0x1F) + } + Else + { + Return(And(0xFFFF,DIDX)) + } + } + + // Return the Current Status. + + // + // Return the Current Status. + // + Method(_DCS,0) + { + If(LEqual(EDPV, 0x0)) + { + Return(0x00) + } + Else + { + Return(CDDS(DIDX)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + Return(NDDS(DIDX)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } + + + // + // Query List of Brightness Control Levels Supported. + // + Method(_BCL,0) + { + // + // List of supported brightness levels in the following sequence. + // Level when machine has full power. + // Level when machine is on batteries. + // Other supported levels. + // + Return(Package(){80, 50, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100}) + } + + // + // Set the Brightness Level. + // + Method (_BCM,1) + { + // + // Set the requested level if it is between 0 and 100%. + // + If(LAnd(LGreaterEqual(Arg0,0),LLessEqual(Arg0,100))) + { + \_SB.PCI0.GFX0.AINT(1, Arg0) + Store(Arg0,BRTL) // Store Brightness Level. + } + } + + // + // Brightness Query Current level. + // + Method (_BQC,0) + { + Return(BRTL) + } +} + + Method(SDDL,1) + { + Increment(NDID) + Store(And(Arg0,0xF0F),Local0) + Or(0x80000000,Local0, Local1) + If(LEqual(DIDL,Local0)) + { + Return(Local1) + } + If(LEqual(DDL2,Local0)) + { + Return(Local1) + } + If(LEqual(DDL3,Local0)) + { + Return(Local1) + } + If(LEqual(DDL4,Local0)) + { + Return(Local1) + } + If(LEqual(DDL5,Local0)) + { + Return(Local1) + } + If(LEqual(DDL6,Local0)) + { + Return(Local1) + } + If(LEqual(DDL7,Local0)) + { + Return(Local1) + } + If(LEqual(DDL8,Local0)) + { + Return(Local1) + } + Return(0) + } + + Method(CDDS,1) + { + Store(And(Arg0,0xF0F),Local0) + + If(LEqual(0, Local0)) + { + Return(0x1D) + } + If(LEqual(CADL, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL2, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL3, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL4, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL5, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL6, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL7, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL8, Local0)) + { + Return(0x1F) + } + Return(0x1D) + } + + Method(NDDS,1) + { + Store(And(Arg0,0xF0F),Local0) + + If(LEqual(0, Local0)) + { + Return(0) + } + If(LEqual(NADL, Local0)) + { + Return(1) + } + If(LEqual(NDL2, Local0)) + { + Return(1) + } + If(LEqual(NDL3, Local0)) + { + Return(1) + } + If(LEqual(NDL4, Local0)) + { + Return(1) + } + If(LEqual(NDL5, Local0)) + { + Return(1) + } + If(LEqual(NDL6, Local0)) + { + Return(1) + } + If(LEqual(NDL7, Local0)) + { + Return(1) + } + If(LEqual(NDL8, Local0)) + { + Return(1) + } + Return(0) + } + + // Include IGD OpRegion/Software SCI interrupt handler which is use by + // the graphics drivers to request data from system BIOS. + // + include("SystemAgent/IgdOpRn.ASL") diff --git a/ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/IntelIspDev2.asl b/ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/IntelIspDev2.asl new file mode 100644 index 0000000000..18419e3d42 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/IntelIspDev2.asl @@ -0,0 +1,66 @@ +/** @file + ACPI DSDT table + ISP Exist as B0D2F0 Software ACPI Reference Code for the CherryView Family. + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + // + // Device ISP0 + // + Device(ISP0) { + Name(_ADR, 0x22B8) + Name(_DDN, "CHV ISP - 808622B8") + Name(_UID, 0x01) + + Method (_STA, 0, NotSerialized) { + // + // Dev2 need report ISP0 as GFX0 child + // + If (LAnd(LNotEqual(ISPA, 0), LEqual(ISPD,1))) + { + Return (0xF) + } + Else + { + Return (0x0) + } + } + Name(SBUF,ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x00000000, 0x00400000, ISP0) + }) + Method(_CRS, 0x0, NotSerialized) { + CreateDwordField(^SBUF, ^ISP0._BAS, B0BA) + Store(ISPA, B0BA) + Return (SBUF) + } + Method (_SRS, 0x1, NotSerialized) + { + } + Method (_DIS, 0x0, NotSerialized) + { + } + Method(_DSM, 0x4, NotSerialized) { + If (LEqual (Arg0, 0x01)) { + // Switch ISP to D3H + Return (0x01) + } + Elseif (LEqual (Arg0, 0x02)) { + // Switch ISP to D0 + Return (0x02) + } + Else + { + //Do nothing + Return (0x0F) + } + } + } // End ISP0 diff --git a/ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/Video.asl b/ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/Video.asl new file mode 100644 index 0000000000..f27817b6d6 --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/SystemAgent/Video.asl @@ -0,0 +1,32 @@ +/**@file + ACPI DSDT table + + Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// Brightness Notification: +// Generate a brightness related notification +// to the LFP if its populated. +// +// Arguments: +// Arg0: Notification value. +// +// Return Value: +// None + +Method(BRTN,1,Serialized) +{ + If(LEqual(And(DIDX,0x0F00),0x400)) + { + Notify(\_SB.PCI0.GFX0.DD1F,Arg0) + } +} diff --git a/ChvRefCodePkg/AcpiTablesPCAT/token.asl b/ChvRefCodePkg/AcpiTablesPCAT/token.asl new file mode 100644 index 0000000000..ea3a5d629f --- /dev/null +++ b/ChvRefCodePkg/AcpiTablesPCAT/token.asl @@ -0,0 +1,62 @@ +/** @file + ACPI DSDT table + + Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Name(SP3O, 0x2e) // Super I/O (Winbond 3xx) Index/Data configuration port for ASL. +Name(IO4B, 0xa20) // Super I/O (Winbond 3xx) GPIO base address +Name(IO4L, 0x20) // Super I/O (Winbond 3xx) GPIO base address length +Name(SP1O, 0x4e) // Super IO Index/Data configuration port for ASL. +Name(PMBS, 0x400) // ASL alias for ACPI I/O base address. +Name(SMIP, 0xb2) // I/O port to trigger SMI +Name(APCB, 0xfec00000) // Default I/O APIC(s) memory start address, 0x0FEC00000 - default, 0 - I/O APIC's disabled +Name(APCL, 0x1000) // I/O APIC(s) memory decoded range, 0x1000 - default, 0 - I/O APIC's not decoded +Name(PMCB, 0xfed03000) // PMC Base Address +Name(PUNB, 0xfed06000) // PUNIT Base Address +Name(IBAS, 0xfed08000) // ILB Base Address +Name(SRCB, 0xfed1c000) // RCBA (Root Complex Base Address) +Name(HPTB, 0xfed00000) // Same as HPET_BASE_ADDRESS for ASL use +Name(GBA0, 0x0FED80000) // GPIO Group 0 Base Adress +Name(GBA1, 0x0FED88000) // GPIO Group 1 Base Adress +Name(GBA2, 0x0FED90000) // GPIO Group 2 Base Adress +Name(GBA3, 0x0FED98000) // GPIO Group 3 Base Adress +Name(ABTR, 0x0FEB00000) // ABORT Region, 0xFEB00000 to 0xFEBFFFFF, any access to this region will be aborted. +Name(PEBS, 0xe0000000) // +Name(PELN, 0x10000000) // +Name(GCDD, 0x1) // GET_CURRENT_DISPLAY_DEVICE_SMI +Name(DSTA, 0xa) // DISPLAY_SWITCH_TOGGLE_ACPI_SMI +Name(DSLO, 0x2) // DISPLAY_SWITCH_LID_OPEN_ACPI_SMI +Name(DSLC, 0x3) // DISPLAY_SWITCH_LID_CLOSE_ACPI_SMI +Name(PITS, 0x10) // POPUP_ICON_TOGGLE_SMI +Name(SBCS, 0x12) // SET_BACKLIGHT_CONTROL_SMI +Name(SALS, 0x13) // SET_ALI_LEVEL_SMI +Name(LSSS, 0x2a) // LID_STATE_SWITCH_SMI +Name(PSSS, 0x2b) // POWER_STATE_SWITCH_SMI +Name(SOOT, 0x35) // SAVE_OSB_OS_TYPE_SMI +Name(ESCS, 0x48) // ENABLE_SMI_C_STATE_COORDINATION_SMI +Name(SDGV, 0x1c) // UHCI Controller HOST_ALERT's bit offset within the GPE block. GPIO[0:15] corresponding to GPE[16:31] +Name(ACPH, 0xde) // North Bridge Scratchpad Data Register for patch ACPI. +Name(ASSB, 0x0) // ACPI Sleep State Buffer for BIOS Usage. +Name(AOTB, 0x0) // ACPI OS Type Buffer for BIOS Usage. +Name(AAXB, 0x0) // ACPI Auxiliary Buffer for BIOS Usage. +Name(PEHP, 0x1) // _OSC: Pci Express Native Hot Plug Control +Name(SHPC, 0x0) // _OSC: Standard Hot Plug Controller (SHPC) Native Hot Plug control +Name(PEPM, 0x1) // _OSC: Pci Express Native Power Management Events control +Name(PEER, 0x1) // _OSC: Pci Express Advanced Error Reporting control +Name(PECS, 0x1) // _OSC: Pci Express Capability Structure control +Name(ITKE, 0x0) // This will be overridden by the ITK module. +Name(FMBL, 0x1) // Platform Flavor - Mobile flavor for ASL code. +Name(FDTP, 0x2) // Platform Flavor - Desktop flavor for ASL code. +Name(FTBL, 0x4) // Platform Flavor - Tablet flavor for ASL code. +Name(CHRB, 0x80) // Cherry Hill reference board +Name(CRRB, 0x55) // Braswell CR reference board -- cgit v1.2.3