From 49cc8d22159c3b7946a712ce31d965cf122b304c Mon Sep 17 00:00:00 2001
From: lgao4 <lgao4@6f19259b-4bc3-4df7-8a09-765794883524>
Date: Tue, 6 Dec 2011 04:26:55 +0000
Subject: Fix ICC11 build failure. Signed-off-by: lgao4 Reviewed-by: mdkinney

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12821 6f19259b-4bc3-4df7-8a09-765794883524
---
 .../EdkIIGlueLib/Library/BaseLib/BaseLib.inf       |   6 +-
 .../Library/BaseLib/Ipf/CpuBreakpointMsc.c         | 118 +++++++++++++++++++++
 2 files changed, 121 insertions(+), 3 deletions(-)
 create mode 100644 EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/CpuBreakpointMsc.c

(limited to 'EdkCompatibilityPkg/Foundation')

diff --git a/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/BaseLib.inf b/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/BaseLib.inf
index 166fceae14..c7a4b718e1 100644
--- a/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/BaseLib.inf
+++ b/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/BaseLib.inf
@@ -1,6 +1,6 @@
 #/*++
 #
-# Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2004 - 2011, Intel Corporation. All rights reserved.<BR>
 # This program and the accompanying materials                          
 # are licensed and made available under the terms and conditions of the BSD License         
 # which accompanies this distribution.  The full text of the license may be found at        
@@ -587,8 +587,8 @@ COMPONENT_TYPE  = LIBRARY
   Ipf/ReadCpuid.s
   Ipf/AccessGp.s
   Math64.c
-  Ipf/CpuBreakpoint.c   | INTEL
-  Ipf/CpuBreakpoint.c   | MSFT
+  Ipf/CpuBreakpoint.c      | INTEL
+  Ipf/CpuBreakpointMsc.c   | MSFT
   Synchronization.c     | INTEL 
   SynchronizationMsc.c  | MSFT 
   SynchronizationGcc.c  | GCC 
diff --git a/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/CpuBreakpointMsc.c b/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/CpuBreakpointMsc.c
new file mode 100644
index 0000000000..4171185088
--- /dev/null
+++ b/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/CpuBreakpointMsc.c
@@ -0,0 +1,118 @@
+/** @file
+  Base Library CPU functions for Itanium
+
+  Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#include "BaseLibInternals.h"
+
+#pragma intrinsic (_enable)
+#pragma intrinsic (_disable)
+#pragma intrinsic (__break)
+#pragma intrinsic (__mfa)
+
+/**
+  Generates a breakpoint on the CPU.
+
+  Generates a breakpoint on the CPU. The breakpoint must be implemented such
+  that code can resume normal execution after the breakpoint.
+
+**/
+VOID
+EFIAPI
+CpuBreakpoint (
+  VOID
+  )
+{
+  __break (0);
+}
+
+/**
+  Used to serialize load and store operations.
+
+  All loads and stores that proceed calls to this function are guaranteed to be
+  globally visible when this function returns.
+
+**/
+VOID
+EFIAPI
+MemoryFence (
+  VOID
+  )
+{
+  __mfa ();
+}
+
+/**
+  Disables CPU interrupts.
+
+  Disables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+DisableInterrupts (
+  VOID
+  )
+{
+  _disable ();
+}
+
+/**
+  Enables CPU interrupts.
+
+  Enables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+EnableInterrupts (
+  VOID
+  )
+{
+  _enable ();
+}
+
+/**
+  Enables CPU interrupts for the smallest window required to capture any
+  pending interrupts.
+
+  Enables CPU interrupts for the smallest window required to capture any
+  pending interrupts.
+
+**/
+VOID
+EFIAPI
+EnableDisableInterrupts (
+  VOID
+  )
+{
+  EnableInterrupts ();
+  DisableInterrupts ();
+}
+
+/**
+  Places the CPU in a sleep state until an interrupt is received.
+
+  Places the CPU in a sleep state until an interrupt is received. If interrupts
+  are disabled prior to calling this function, then the CPU will be placed in a
+  sleep state indefinitely.
+
+**/
+VOID
+EFIAPI
+CpuSleep (
+  VOID
+  )
+{
+  PalCallStatic (NULL, 29, 0, 0, 0);
+}
-- 
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