From 405103a4290b3627a09d96a7f572aae2ac4d99a1 Mon Sep 17 00:00:00 2001 From: Guo Mang Date: Thu, 22 Dec 2016 18:23:11 +0800 Subject: IntelFspPkg: Remove unused Package Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang --- IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm | 601 ------------------ IntelFspPkg/FspSecCore/Ia32/FspApiEntry.s | 813 ------------------------- IntelFspPkg/FspSecCore/Ia32/FspHelper.asm | 73 --- IntelFspPkg/FspSecCore/Ia32/FspHelper.s | 71 --- IntelFspPkg/FspSecCore/Ia32/InitializeFpu.asm | 79 --- IntelFspPkg/FspSecCore/Ia32/InitializeFpu.s | 73 --- IntelFspPkg/FspSecCore/Ia32/MicrocodeLoad.inc | 49 -- IntelFspPkg/FspSecCore/Ia32/ResetVec.asm16 | 103 ---- IntelFspPkg/FspSecCore/Ia32/SaveRestoreSse.inc | 184 ------ IntelFspPkg/FspSecCore/Ia32/Stack.asm | 82 --- IntelFspPkg/FspSecCore/Ia32/Stacks.s | 86 --- 11 files changed, 2214 deletions(-) delete mode 100644 IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm delete mode 100644 IntelFspPkg/FspSecCore/Ia32/FspApiEntry.s delete mode 100644 IntelFspPkg/FspSecCore/Ia32/FspHelper.asm delete mode 100644 IntelFspPkg/FspSecCore/Ia32/FspHelper.s delete mode 100644 IntelFspPkg/FspSecCore/Ia32/InitializeFpu.asm delete mode 100644 IntelFspPkg/FspSecCore/Ia32/InitializeFpu.s delete mode 100644 IntelFspPkg/FspSecCore/Ia32/MicrocodeLoad.inc delete mode 100644 IntelFspPkg/FspSecCore/Ia32/ResetVec.asm16 delete mode 100644 IntelFspPkg/FspSecCore/Ia32/SaveRestoreSse.inc delete mode 100644 IntelFspPkg/FspSecCore/Ia32/Stack.asm delete mode 100644 IntelFspPkg/FspSecCore/Ia32/Stacks.s (limited to 'IntelFspPkg/FspSecCore/Ia32') diff --git a/IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm b/IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm deleted file mode 100644 index 71e3e5a1e2..0000000000 --- a/IntelFspPkg/FspSecCore/Ia32/FspApiEntry.asm +++ /dev/null @@ -1,601 +0,0 @@ -;; @file -; Provide FSP API entry points. -; -; Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.
-; This program and the accompanying materials -; are licensed and made available under the terms and conditions of the BSD License -; which accompanies this distribution. The full text of the license may be found at -; http://opensource.org/licenses/bsd-license.php. -; -; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -;; - - .586p - .model flat,C - .code - .xmm - -INCLUDE SaveRestoreSse.inc -INCLUDE MicrocodeLoad.inc - -; -; Following are fixed PCDs -; -EXTERN PcdGet32(PcdTemporaryRamBase):DWORD -EXTERN PcdGet32(PcdTemporaryRamSize):DWORD -EXTERN PcdGet32(PcdFspTemporaryRamSize):DWORD -EXTERN PcdGet32(PcdFspAreaSize):DWORD - -; -; Following functions will be provided in C -; - -EXTERN SecStartup:PROC -EXTERN FspApiCallingCheck:PROC - -; -; Following functions will be provided in PlatformSecLib -; -EXTERN AsmGetFspBaseAddress:PROC -EXTERN AsmGetFspInfoHeader:PROC -EXTERN GetBootFirmwareVolumeOffset:PROC -EXTERN Loader2PeiSwitchStack:PROC -EXTERN LoadMicrocode(LoadMicrocodeDefault):PROC -EXTERN SecPlatformInit(SecPlatformInitDefault):PROC -EXTERN SecCarInit:PROC - -; -; Define the data length that we saved on the stack top -; -DATA_LEN_OF_PER0 EQU 18h -DATA_LEN_OF_MCUD EQU 18h -DATA_LEN_AT_STACK_TOP EQU (DATA_LEN_OF_PER0 + DATA_LEN_OF_MCUD + 4) - -; -; Define SSE macros -; -LOAD_MMX_EXT MACRO ReturnAddress, MmxRegister - mov esi, ReturnAddress - movd MmxRegister, esi ; save ReturnAddress into MMX -ENDM - -CALL_MMX_EXT MACRO RoutineLabel, MmxRegister - local ReturnAddress - mov esi, offset ReturnAddress - movd MmxRegister, esi ; save ReturnAddress into MMX - jmp RoutineLabel -ReturnAddress: -ENDM - -RET_ESI_EXT MACRO MmxRegister - movd esi, MmxRegister ; move ReturnAddress from MMX to ESI - jmp esi -ENDM - -CALL_MMX MACRO RoutineLabel - CALL_MMX_EXT RoutineLabel, mm7 -ENDM - -RET_ESI MACRO - RET_ESI_EXT mm7 -ENDM - -;------------------------------------------------------------------------------ -SecPlatformInitDefault PROC NEAR PUBLIC - ; Inputs: - ; mm7 -> Return address - ; Outputs: - ; eax -> 0 - Successful, Non-zero - Failed. - ; Register Usage: - ; eax is cleared and ebp is used for return address. - ; All others reserved. - - ; Save return address to EBP - movd ebp, mm7 - - xor eax, eax -exit: - jmp ebp -SecPlatformInitDefault ENDP - -;------------------------------------------------------------------------------ -LoadMicrocodeDefault PROC NEAR PUBLIC - ; Inputs: - ; esp -> LoadMicrocodeParams pointer - ; Register Usage: - ; esp Preserved - ; All others destroyed - ; Assumptions: - ; No memory available, stack is hard-coded and used for return address - ; Executed by SBSP and NBSP - ; Beginning of microcode update region starts on paragraph boundary - - ; - ; - ; Save return address to EBP - movd ebp, mm7 - - cmp esp, 0 - jz paramerror - mov eax, dword ptr [esp + 4] ; Parameter pointer - cmp eax, 0 - jz paramerror - mov esp, eax - mov esi, [esp].LoadMicrocodeParams.MicrocodeCodeAddr - cmp esi, 0 - jnz check_main_header - -paramerror: - mov eax, 080000002h - jmp exit - - mov esi, [esp].LoadMicrocodeParams.MicrocodeCodeAddr - -check_main_header: - ; Get processor signature and platform ID from the installed processor - ; and save into registers for later use - ; ebx = processor signature - ; edx = platform ID - mov eax, 1 - cpuid - mov ebx, eax - mov ecx, MSR_IA32_PLATFORM_ID - rdmsr - mov ecx, edx - shr ecx, 50-32 ; shift (50d-32d=18d=0x12) bits - and ecx, 7h ; platform id at bit[52..50] - mov edx, 1 - shl edx, cl - - ; Current register usage - ; esp -> stack with paramters - ; esi -> microcode update to check - ; ebx = processor signature - ; edx = platform ID - - ; Check for valid microcode header - ; Minimal test checking for header version and loader version as 1 - mov eax, dword ptr 1 - cmp [esi].MicrocodeHdr.MicrocodeHdrVersion, eax - jne advance_fixed_size - cmp [esi].MicrocodeHdr.MicrocodeHdrLoader, eax - jne advance_fixed_size - - ; Check if signature and plaform ID match - cmp ebx, [esi].MicrocodeHdr.MicrocodeHdrProcessor - jne @f - test edx, [esi].MicrocodeHdr.MicrocodeHdrFlags - jnz load_check ; Jif signature and platform ID match - -@@: - ; Check if extended header exists - ; First check if MicrocodeHdrTotalSize and MicrocodeHdrDataSize are valid - xor eax, eax - cmp [esi].MicrocodeHdr.MicrocodeHdrTotalSize, eax - je next_microcode - cmp [esi].MicrocodeHdr.MicrocodeHdrDataSize, eax - je next_microcode - - ; Then verify total size - sizeof header > data size - mov ecx, [esi].MicrocodeHdr.MicrocodeHdrTotalSize - sub ecx, sizeof MicrocodeHdr - cmp ecx, [esi].MicrocodeHdr.MicrocodeHdrDataSize - jng next_microcode ; Jif extended header does not exist - - ; Set edi -> extended header - mov edi, esi - add edi, sizeof MicrocodeHdr - add edi, [esi].MicrocodeHdr.MicrocodeHdrDataSize - - ; Get count of extended structures - mov ecx, [edi].ExtSigHdr.ExtSigHdrCount - - ; Move pointer to first signature structure - add edi, sizeof ExtSigHdr - -check_ext_sig: - ; Check if extended signature and platform ID match - cmp [edi].ExtSig.ExtSigProcessor, ebx - jne @f - test [edi].ExtSig.ExtSigFlags, edx - jnz load_check ; Jif signature and platform ID match -@@: - ; Check if any more extended signatures exist - add edi, sizeof ExtSig - loop check_ext_sig - -next_microcode: - ; Advance just after end of this microcode - xor eax, eax - cmp [esi].MicrocodeHdr.MicrocodeHdrTotalSize, eax - je @f - add esi, [esi].MicrocodeHdr.MicrocodeHdrTotalSize - jmp check_address -@@: - add esi, dword ptr 2048 - jmp check_address - -advance_fixed_size: - ; Advance by 4X dwords - add esi, dword ptr 1024 - -check_address: - ; Is valid Microcode start point ? - cmp dword ptr [esi].MicrocodeHdr.MicrocodeHdrVersion, 0ffffffffh - jz done - - ; Is automatic size detection ? - mov eax, [esp].LoadMicrocodeParams.MicrocodeCodeSize - cmp eax, 0ffffffffh - jz @f - - ; Address >= microcode region address + microcode region size? - add eax, [esp].LoadMicrocodeParams.MicrocodeCodeAddr - cmp esi, eax - jae done ;Jif address is outside of microcode region - jmp check_main_header - -@@: -load_check: - ; Get the revision of the current microcode update loaded - mov ecx, MSR_IA32_BIOS_SIGN_ID - xor eax, eax ; Clear EAX - xor edx, edx ; Clear EDX - wrmsr ; Load 0 to MSR at 8Bh - - mov eax, 1 - cpuid - mov ecx, MSR_IA32_BIOS_SIGN_ID - rdmsr ; Get current microcode signature - - ; Verify this microcode update is not already loaded - cmp [esi].MicrocodeHdr.MicrocodeHdrRevision, edx - je continue - -load_microcode: - ; EAX contains the linear address of the start of the Update Data - ; EDX contains zero - ; ECX contains 79h (IA32_BIOS_UPDT_TRIG) - ; Start microcode load with wrmsr - mov eax, esi - add eax, sizeof MicrocodeHdr - xor edx, edx - mov ecx, MSR_IA32_BIOS_UPDT_TRIG - wrmsr - mov eax, 1 - cpuid - -continue: - jmp next_microcode - -done: - mov eax, 1 - cpuid - mov ecx, MSR_IA32_BIOS_SIGN_ID - rdmsr ; Get current microcode signature - xor eax, eax - cmp edx, 0 - jnz exit - mov eax, 08000000Eh - -exit: - jmp ebp - -LoadMicrocodeDefault ENDP - -EstablishStackFsp PROC NEAR PRIVATE - ; - ; Save parameter pointer in edx - ; - mov edx, dword ptr [esp + 4] - - ; - ; Enable FSP STACK - ; - mov esp, PcdGet32 (PcdTemporaryRamBase) - add esp, PcdGet32 (PcdTemporaryRamSize) - - push DATA_LEN_OF_MCUD ; Size of the data region - push 4455434Dh ; Signature of the data region 'MCUD' - push dword ptr [edx + 12] ; Code size - push dword ptr [edx + 8] ; Code base - push dword ptr [edx + 4] ; Microcode size - push dword ptr [edx] ; Microcode base - - ; - ; Save API entry/exit timestamp into stack - ; - push DATA_LEN_OF_PER0 ; Size of the data region - push 30524550h ; Signature of the data region 'PER0' - LOAD_EDX - push edx - LOAD_EAX - push eax - rdtsc - push edx - push eax - - ; - ; Terminator for the data on stack - ; - push 0 - - ; - ; Set ECX/EDX to the BootLoader temporary memory range - ; - mov ecx, PcdGet32 (PcdTemporaryRamBase) - mov edx, ecx - add edx, PcdGet32 (PcdTemporaryRamSize) - sub edx, PcdGet32 (PcdFspTemporaryRamSize) - - xor eax, eax - - RET_ESI - -EstablishStackFsp ENDP - - -;---------------------------------------------------------------------------- -; TempRamInit API -; -; This FSP API will load the microcode update, enable code caching for the -; region specified by the boot loader and also setup a temporary stack to be -; used till main memory is initialized. -; -;---------------------------------------------------------------------------- -TempRamInitApi PROC NEAR PUBLIC - ; - ; Ensure SSE is enabled - ; - ENABLE_SSE - - ; - ; Save EBP, EBX, ESI, EDI & ESP in XMM7 & XMM6 - ; - SAVE_REGS - - ; - ; Save timestamp into XMM6 - ; - rdtsc - SAVE_EAX - SAVE_EDX - - ; - ; Check Parameter - ; - mov eax, dword ptr [esp + 4] - cmp eax, 0 - mov eax, 80000002h - jz TempRamInitExit - - ; - ; Sec Platform Init - ; - CALL_MMX SecPlatformInit - cmp eax, 0 - jnz TempRamInitExit - - ; Load microcode - LOAD_ESP - CALL_MMX LoadMicrocode - SXMMN xmm6, 3, eax ;Save microcode return status in ECX-SLOT 3 in xmm6. - ;@note If return value eax is not 0, microcode did not load, but continue and attempt to boot. - - ; Call Sec CAR Init - LOAD_ESP - CALL_MMX SecCarInit - cmp eax, 0 - jnz TempRamInitExit - - LOAD_ESP - CALL_MMX EstablishStackFsp - - LXMMN xmm6, eax, 3 ;Restore microcode status if no CAR init error from ECX-SLOT 3 in xmm6. - -TempRamInitExit: - ; - ; Load EBP, EBX, ESI, EDI & ESP from XMM7 & XMM6 - ; - LOAD_REGS - ret -TempRamInitApi ENDP - -;---------------------------------------------------------------------------- -; FspInit API -; -; This FSP API will perform the processor and chipset initialization. -; This API will not return. Instead, it transfers the control to the -; ContinuationFunc provided in the parameter. -; -;---------------------------------------------------------------------------- -FspInitApi PROC NEAR PUBLIC - mov eax, 1 - jmp FspApiCommon - FspInitApi ENDP - -;---------------------------------------------------------------------------- -; NotifyPhase API -; -; This FSP API will notify the FSP about the different phases in the boot -; process -; -;---------------------------------------------------------------------------- -NotifyPhaseApi PROC C PUBLIC - mov eax, 2 - jmp FspApiCommon -NotifyPhaseApi ENDP - -;---------------------------------------------------------------------------- -; FspMemoryInit API -; -; This FSP API is called after TempRamInit and initializes the memory. -; -;---------------------------------------------------------------------------- -FspMemoryInitApi PROC NEAR PUBLIC - mov eax, 3 - jmp FspApiCommon -FspMemoryInitApi ENDP - - -;---------------------------------------------------------------------------- -; TempRamExitApi API -; -; This API tears down temporary RAM -; -;---------------------------------------------------------------------------- -TempRamExitApi PROC C PUBLIC - mov eax, 4 - jmp FspApiCommon -TempRamExitApi ENDP - - -;---------------------------------------------------------------------------- -; FspSiliconInit API -; -; This FSP API initializes the CPU and the chipset including the IO -; controllers in the chipset to enable normal operation of these devices. -; -;---------------------------------------------------------------------------- -FspSiliconInitApi PROC C PUBLIC - mov eax, 5 - jmp FspApiCommon -FspSiliconInitApi ENDP - -;---------------------------------------------------------------------------- -; FspApiCommon API -; -; This is the FSP API common entry point to resume the FSP execution -; -;---------------------------------------------------------------------------- -FspApiCommon PROC C PUBLIC - ; - ; EAX holds the API index - ; - - ; - ; Stack must be ready - ; - push eax - add esp, 4 - cmp eax, dword ptr [esp - 4] - jz @F - mov eax, 080000003h - jmp exit - -@@: - ; - ; Verify the calling condition - ; - pushad - push [esp + 4 * 8 + 4] ; push ApiParam - push eax ; push ApiIdx - call FspApiCallingCheck - add esp, 8 - cmp eax, 0 - jz @F - mov dword ptr [esp + 4 * 7], eax - popad - ret - -@@: - popad - cmp eax, 1 ; FspInit API - jz @F - cmp eax, 3 ; FspMemoryInit API - jz @F - - call AsmGetFspInfoHeader - jmp Loader2PeiSwitchStack - -@@: - ; - ; FspInit and FspMemoryInit APIs, setup the initial stack frame - ; - - ; - ; Place holder to store the FspInfoHeader pointer - ; - push eax - - ; - ; Update the FspInfoHeader pointer - ; - push eax - call AsmGetFspInfoHeader - mov [esp + 4], eax - pop eax - - ; - ; Create a Task Frame in the stack for the Boot Loader - ; - pushfd ; 2 pushf for 4 byte alignment - cli - pushad - - ; Reserve 8 bytes for IDT save/restore - sub esp, 8 - sidt fword ptr [esp] - - ; - ; Setup new FSP stack - ; - mov edi, esp - mov esp, PcdGet32(PcdTemporaryRamBase) - add esp, PcdGet32(PcdTemporaryRamSize) - sub esp, (DATA_LEN_AT_STACK_TOP + 40h) - - ; - ; Pass the API Idx to SecStartup - ; - push eax - - ; - ; Pass the BootLoader stack to SecStartup - ; - push edi - - ; - ; Pass entry point of the PEI core - ; - call AsmGetFspBaseAddress - mov edi, eax - add edi, PcdGet32 (PcdFspAreaSize) - sub edi, 20h - add eax, DWORD PTR ds:[edi] - push eax - - ; - ; Pass BFV into the PEI Core - ; It uses relative address to calucate the actual boot FV base - ; For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase and - ; PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs, - ; they are different. The code below can handle both cases. - ; - call AsmGetFspBaseAddress - mov edi, eax - call GetBootFirmwareVolumeOffset - add eax, edi - push eax - - ; - ; Pass stack base and size into the PEI Core - ; - mov eax, PcdGet32(PcdTemporaryRamBase) - add eax, PcdGet32(PcdTemporaryRamSize) - sub eax, PcdGet32(PcdFspTemporaryRamSize) - push eax - push PcdGet32(PcdFspTemporaryRamSize) - - ; - ; Pass Control into the PEI Core - ; - call SecStartup - add esp, 4 -exit: - ret - -FspApiCommon ENDP - -END diff --git a/IntelFspPkg/FspSecCore/Ia32/FspApiEntry.s b/IntelFspPkg/FspSecCore/Ia32/FspApiEntry.s deleted file mode 100644 index d9cfcc3390..0000000000 --- a/IntelFspPkg/FspSecCore/Ia32/FspApiEntry.s +++ /dev/null @@ -1,813 +0,0 @@ -#------------------------------------------------------------------------------ -# -# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.
-# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php. -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -# Abstract: -# -# Provide FSP API entry points. -# -#------------------------------------------------------------------------------ - - -.equ MSR_IA32_PLATFORM_ID, 0x00000017 -.equ MSR_IA32_BIOS_UPDT_TRIG, 0x00000079 -.equ MSR_IA32_BIOS_SIGN_ID, 0x0000008b - - -MicrocodeHdr: -.equ MicrocodeHdrVersion, 0x0000 -.equ MicrocodeHdrRevision, 0x0004 -.equ MicrocodeHdrDate, 0x0008 -.equ MicrocodeHdrProcessor, 0x000c -.equ MicrocodeHdrChecksum, 0x0010 -.equ MicrocodeHdrLoader, 0x0014 -.equ MicrocodeHdrFlags, 0x0018 -.equ MicrocodeHdrDataSize, 0x001C -.equ MicrocodeHdrTotalSize, 0x0020 -.equ MicrocodeHdrRsvd, 0x0024 -MicrocodeHdrEnd: -.equ MicrocodeHdrLength, 0x0030 # MicrocodeHdrLength = MicrocodeHdrEnd - MicrocodeHdr - - -ExtSigHdr: -.equ ExtSigHdrCount, 0x0000 -.equ ExtSigHdrChecksum, 0x0004 -.equ ExtSigHdrRsvd, 0x0008 -ExtSigHdrEnd: -.equ ExtSigHdrLength, 0x0014 #ExtSigHdrLength = ExtSigHdrEnd - ExtSigHdr - -ExtSig: -.equ ExtSigProcessor, 0x0000 -.equ ExtSigFlags, 0x0004 -.equ ExtSigChecksum, 0x0008 -ExtSigEnd: -.equ ExtSigLength, 0x000C #ExtSigLength = ExtSigEnd - ExtSig - -LoadMicrocodeParams: -.equ MicrocodeCodeAddr, 0x0000 -.equ MicrocodeCodeSize, 0x0004 -LoadMicrocodeParamsEnd: - - - -.macro SAVE_REGS - pinsrw $0x00, %ebp, %xmm7 - ror $0x10, %ebp - pinsrw $0x01, %ebp, %xmm7 - ror $0x10, %ebp -# - pinsrw $0x02, %ebx, %xmm7 - ror $0x10, %ebx - pinsrw $0x03, %ebx, %xmm7 - ror $0x10, %ebx -# - pinsrw $0x04, %esi, %xmm7 - ror $0x10, %esi - pinsrw $0x05, %esi, %xmm7 - ror $0x10, %esi -# - pinsrw $0x06, %edi, %xmm7 - ror $0x10, %edi - pinsrw $0x07, %edi, %xmm7 - ror $0x10, %edi -# - pinsrw $0x00, %esp, %xmm6 - ror $0x10, %esp - pinsrw $0x01, %esp, %xmm6 - ror $0x10, %esp -.endm - -.macro LOAD_REGS - pshufd $0xe4, %xmm7, %xmm7 - movd %xmm7, %ebp - pshufd $0xe4, %xmm7, %xmm7 -# - pshufd $0x39, %xmm7, %xmm7 - movd %xmm7, %ebx - pshufd $0x93, %xmm7, %xmm7 -# - pshufd $0x4e, %xmm7, %xmm7 - movd %xmm7, %esi - pshufd $0x4e, %xmm7, %xmm7 -# - pshufd $0x93, %xmm7, %xmm7 - movd %xmm7, %edi - pshufd $0x39, %xmm7, %xmm7 -# - movd %xmm6, %esp -.endm - -.macro LOAD_EAX - pshufd $0x39, %xmm6, %xmm6 - movd %xmm6, %eax - pshufd $0x93, %xmm6, %xmm6 -.endm - -.macro LOAD_EDX - pshufd $0xe4, %xmm6, %xmm6 - movd %xmm6, %edx - pshufd $0xe4, %xmm6, %xmm6 -.endm - -.macro SAVE_EAX - pinsrw $0x02, %eax, %xmm6 - ror $0x10, %eax - pinsrw $0x03, %eax, %xmm6 - ror $0x10, %eax -.endm - -.macro SAVE_EDX - pinsrw $0x04, %edx, %xmm6 - ror $0x10, %edx - pinsrw $0x05, %edx, %xmm6 - ror $0x10, %edx -.endm - -.macro LOAD_ESP - movd %xmm6, %esp -.endm - -.macro ENABLE_SSE - jmp NextAddress -.align 4 - # - # Float control word initial value: - # all exceptions masked, double-precision, round-to-nearest - # -ASM_PFX(mFpuControlWord): .word 0x027F - # - # Multimedia-extensions control word: - # all exceptions masked, round-to-nearest, flush to zero for masked underflow - # -ASM_PFX(mMmxControlWord): .long 0x01F80 -SseError: - # - # Processor has to support SSE - # - jmp SseError -NextAddress: - # - # Initialize floating point units - # - finit - fldcw ASM_PFX(mFpuControlWord) - - # - # Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test - # whether the processor supports SSE instruction. - # - movl $1, %eax - cpuid - btl $25, %edx - jnc SseError - - # - # Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10) - # - movl %cr4, %eax - orl $BIT9, %eax - movl %eax, %cr4 - - # - # The processor should support SSE instruction and we can use - # ldmxcsr instruction - # - ldmxcsr ASM_PFX(mMmxControlWord) -.endm - -#Save in ECX-SLOT 3 in xmm6. -.macro SAVE_EAX_MICROCODE_RET_STATUS - pinsrw $0x6, %eax, %xmm6 - ror $0x10, %eax - pinsrw $0x7, %eax, %xmm6 - rol $0x10, %eax -.endm - -#Restore from ECX-SLOT 3 in xmm6. -.macro LOAD_EAX_MICROCODE_RET_STATUS - pshufd $0x93, %xmm6, %xmm6 - movd %xmm6, %eax - pshufd $0x39, %xmm6, %xmm6 -.endm - - - -# -# Following are fixed PCDs -# -ASM_GLOBAL ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamBase) -ASM_GLOBAL ASM_PFX(_gPcd_FixedAtBuild_PcdTemporaryRamSize) -ASM_GLOBAL ASM_PFX(_gPcd_FixedAtBuild_PcdFspTemporaryRamSize) - -# -# Following functions will be provided in C -# -ASM_GLOBAL ASM_PFX(SecStartup) -ASM_GLOBAL ASM_PFX(FspApiCallingCheck) - -# -# Following functions will be provided in PlatformSecLib -# -ASM_GLOBAL ASM_PFX(AsmGetFspBaseAddress) -ASM_GLOBAL ASM_PFX(AsmGetFspInfoHeader) -ASM_GLOBAL ASM_PFX(GetBootFirmwareVolumeOffset) -ASM_GLOBAL ASM_PFX(Loader2PeiSwitchStack) - - -# -# Define the data length that we saved on the stack top -# -.equ DATA_LEN_OF_PER0, 0x018 -.equ DATA_LEN_OF_MCUD, 0x018 -.equ DATA_LEN_AT_STACK_TOP, (DATA_LEN_OF_PER0 + DATA_LEN_OF_MCUD + 4) - -#------------------------------------------------------------------------------ -# SecPlatformInitDefault -# Inputs: -# mm7 -> Return address -# Outputs: -# eax -> 0 - Successful, Non-zero - Failed. -# Register Usage: -# eax is cleared and ebp is used for return address. -# All others reserved. -#------------------------------------------------------------------------------ -ASM_GLOBAL ASM_PFX(SecPlatformInitDefault) -ASM_PFX(SecPlatformInitDefault): - # - # Save return address to EBP - # - movd %mm7, %ebp - xorl %eax, %eax - -SecPlatformInitDefaultExit: - jmp *%ebp - - -#------------------------------------------------------------------------------ -# LoadMicrocodeDefault -# -# Inputs: -# esp -> LoadMicrocodeParams pointer -# Register Usage: -# esp Preserved -# All others destroyed -# Assumptions: -# No memory available, stack is hard-coded and used for return address -# Executed by SBSP and NBSP -# Beginning of microcode update region starts on paragraph boundary -#------------------------------------------------------------------------------ -ASM_GLOBAL ASM_PFX(LoadMicrocodeDefault) -ASM_PFX(LoadMicrocodeDefault): - # - # Save return address to EBP - # - movd %mm7, %ebp - - cmpl $0x00, %esp - jz ParamError - movl 4(%esp), %eax #dword ptr [] Parameter pointer - cmpl $0x00, %eax - jz ParamError - movl %eax, %esp - movl MicrocodeCodeAddr(%esp), %esi - cmpl $0x00, %esi - jnz CheckMainHeader - -ParamError: - movl $0x080000002, %eax - jmp LoadMicrocodeExit - -CheckMainHeader: - # - # Get processor signature and platform ID from the installed processor - # and save into registers for later use - # ebx = processor signature - # edx = platform ID - # - movl $0x01, %eax - cpuid - movl %eax, %ebx - movl $MSR_IA32_PLATFORM_ID, %ecx - rdmsr - movl %edx, %ecx - shrl $0x12, %ecx # shift (50d-32d=18d=0x12) bits - andl $0x07, %ecx # platform id at bit[52..50] - movl $0x01, %edx - shll %cl,%edx - - # - # Current register usage - # esp -> stack with paramters - # esi -> microcode update to check - # ebx = processor signature - # edx = platform ID - # - - # - # Check for valid microcode header - # Minimal test checking for header version and loader version as 1 - # - movl $0x01, %eax - cmpl %eax, MicrocodeHdrVersion(%esi) - jne AdvanceFixedSize - cmpl %eax, MicrocodeHdrLoader(%esi) - jne AdvanceFixedSize - - # - # Check if signature and plaform ID match - # - cmpl MicrocodeHdrProcessor(%esi), %ebx - jne LoadMicrocodeL0 - testl MicrocodeHdrFlags(%esi), %edx - jnz LoadCheck #Jif signature and platform ID match - -LoadMicrocodeL0: - # - # Check if extended header exists - # First check if MicrocodeHdrTotalSize and MicrocodeHdrDataSize are valid - # - xorl %eax, %eax - cmpl %eax, MicrocodeHdrTotalSize(%esi) - je NextMicrocode - cmpl %eax, MicrocodeHdrDataSize(%esi) - je NextMicrocode - - # - # Then verify total size - sizeof header > data size - # - movl MicrocodeHdrTotalSize(%esi), %ecx - subl $MicrocodeHdrLength, %ecx - cmpl MicrocodeHdrDataSize(%esi), %ecx - jle NextMicrocode - - # - # Set edi -> extended header - # - movl %esi, %edi - addl $MicrocodeHdrLength, %edi - addl MicrocodeHdrDataSize(%esi), %edi - - # - # Get count of extended structures - # - movl ExtSigHdrCount(%edi), %ecx - - # - # Move pointer to first signature structure - # - addl ExtSigHdrLength, %edi - -CheckExtSig: - # - # Check if extended signature and platform ID match - # - cmpl %ebx, ExtSigProcessor(%edi) - jne LoadMicrocodeL1 - test %edx, ExtSigFlags(%edi) - jnz LoadCheck # Jif signature and platform ID match -LoadMicrocodeL1: - # - # Check if any more extended signatures exist - # - addl $ExtSigLength, %edi - loop CheckExtSig - -NextMicrocode: - # - # Advance just after end of this microcode - # - xorl %eax, %eax - cmpl %eax, MicrocodeHdrTotalSize(%esi) - je LoadMicrocodeL2 - addl MicrocodeHdrTotalSize(%esi), %esi - jmp CheckAddress -LoadMicrocodeL2: - addl $0x800, %esi #add esi, dword ptr 2048 - jmp CheckAddress - -AdvanceFixedSize: - # - # Advance by 4X dwords - # - addl $0x400, %esi #add esi, dword ptr 1024 - -CheckAddress: - # - # Is valid Microcode start point ? - # - cmpl $0x0ffffffff, MicrocodeHdrVersion(%esi) - - # - # Is automatic size detection ? - # - movl MicrocodeCodeSize(%esp), %eax - cmpl $0x0ffffffff, %eax - jz LoadMicrocodeL3 - # - # Address >= microcode region address + microcode region size? - # - addl MicrocodeCodeAddr(%esp), %eax - - cmpl %eax, %esi - jae Done #Jif address is outside of microcode region - jmp CheckMainHeader - -LoadMicrocodeL3: -LoadCheck: - # - # Get the revision of the current microcode update loaded - # - movl $MSR_IA32_BIOS_SIGN_ID, %ecx - xorl %eax, %eax # Clear EAX - xorl %edx, %edx # Clear EDX - wrmsr # Load 0 to MSR at 8Bh - - movl $0x01, %eax - cpuid - movl $MSR_IA32_BIOS_SIGN_ID, %ecx - rdmsr # Get current microcode signature - - # - # Verify this microcode update is not already loaded - # - cmpl %edx, MicrocodeHdrRevision(%esi) - je Continue - -LoadMicrocode0: - # - # EAX contains the linear address of the start of the Update Data - # EDX contains zero - # ECX contains 79h (IA32_BIOS_UPDT_TRIG) - # Start microcode load with wrmsr - # - movl %esi, %eax - addl $MicrocodeHdrLength, %eax - xorl %edx, %edx - movl $MSR_IA32_BIOS_UPDT_TRIG, %ecx - wrmsr - movl $0x01, %eax - cpuid - -Continue: - jmp NextMicrocode - -Done: - movl $0x01, %eax - cpuid - movl $MSR_IA32_BIOS_SIGN_ID, %ecx - rdmsr # Get current microcode signature - xorl %eax, %eax - cmpl $0x00, %edx - jnz LoadMicrocodeExit - movl $0x08000000E, %eax - -LoadMicrocodeExit: - jmp *%ebp - - -#---------------------------------------------------------------------------- -# EstablishStackFsp -# -#---------------------------------------------------------------------------- -ASM_GLOBAL ASM_PFX(EstablishStackFsp) -ASM_PFX(EstablishStackFsp): - # - # Save parameter pointer in edx - # - movl 4(%esp), %edx - - # - # Enable FSP STACK - # - movl PcdGet32(PcdTemporaryRamBase), %esp - addl PcdGet32(PcdTemporaryRamSize), %esp - - pushl $DATA_LEN_OF_MCUD # Size of the data region - pushl $0x4455434D # Signature of the data region 'MCUD' - pushl 12(%edx) # Code size - pushl 8(%edx) # Code base - pushl 4(%edx) # Microcode size - pushl (%edx) # Microcode base - - # - # Save API entry/exit timestamp into stack - # - pushl $DATA_LEN_OF_PER0 # Size of the data region - pushl $0x30524550 # Signature of the data region 'PER0' - LOAD_EDX - pushl %edx - LOAD_EAX - pushl %eax - rdtsc - pushl %edx - pushl %eax - - # - # Terminator for the data on stack - # - push $0x00 - - # - # Set ECX/EDX to the BootLoader temporary memory range - # - movl PcdGet32 (PcdTemporaryRamBase), %ecx - movl %ecx, %edx - addl PcdGet32 (PcdTemporaryRamSize), %edx - subl PcdGet32 (PcdFspTemporaryRamSize), %edx - - xorl %eax, %eax - - movd %mm7, %esi #RET_ESI - jmp *%esi - -#---------------------------------------------------------------------------- -# TempRamInit API -# -# This FSP API will load the microcode update, enable code caching for the -# region specified by the boot loader and also setup a temporary stack to be -# used till main memory is initialized. -# -#---------------------------------------------------------------------------- -ASM_GLOBAL ASM_PFX(TempRamInitApi) -ASM_PFX(TempRamInitApi): - # - # Ensure SSE is enabled - # - ENABLE_SSE - - # - # Save EBP, EBX, ESI, EDI & ESP in XMM7 & XMM6 - # - SAVE_REGS - - # - # Save timestamp into XMM6 - # - rdtsc - SAVE_EAX - SAVE_EDX - - # - # Check Parameter - # - movl 4(%esp), %eax - cmpl $0x00, %eax - movl $0x80000002, %eax - jz NemInitExit - - # - # Sec Platform Init - # - movl $TempRamInitApiL1, %esi #CALL_MMX SecPlatformInit - movd %esi, %mm7 - .weak ASM_PFX(SecPlatformInit) - .set ASM_PFX(SecPlatformInit), ASM_PFX(SecPlatformInitDefault) - jmp ASM_PFX(SecPlatformInit) -TempRamInitApiL1: - cmpl $0x00, %eax - jnz NemInitExit - - # - # Load microcode - # - LOAD_ESP - movl $TempRamInitApiL2, %esi #CALL_MMX LoadMicrocode - movd %esi, %mm7 - .weak ASM_PFX(LoadMicrocode) - .set ASM_PFX(LoadMicrocode), ASM_PFX(LoadMicrocodeDefault) - jmp ASM_PFX(LoadMicrocode) -TempRamInitApiL2: - SAVE_EAX_MICROCODE_RET_STATUS #Save microcode return status in ECX-SLOT 3 in xmm6. - #@note If return value eax is not 0, microcode did not load, but continue and attempt to boot from ECX-SLOT 3 in xmm6. - - # - # Call Sec CAR Init - # - LOAD_ESP - movl $TempRamInitApiL3, %esi #CALL_MMX SecCarInit - movd %esi, %mm7 - jmp ASM_PFX(SecCarInit) -TempRamInitApiL3: - cmpl $0x00, %eax - jnz NemInitExit - - # - # EstablishStackFsp - # - LOAD_ESP - movl $TempRamInitApiL4, %esi #CALL_MMX EstablishStackFsp - movd %esi, %mm7 - jmp ASM_PFX(EstablishStackFsp) -TempRamInitApiL4: - - LOAD_EAX_MICROCODE_RET_STATUS #Restore microcode status if no CAR init error. - -NemInitExit: - # - # Load EBP, EBX, ESI, EDI & ESP from XMM7 & XMM6 - # - LOAD_REGS - ret - - -#---------------------------------------------------------------------------- -# FspInit API -# -# This FSP API will perform the processor and chipset initialization. -# This API will not return. Instead, it transfers the control to the -# ContinuationFunc provided in the parameter. -# -#---------------------------------------------------------------------------- -ASM_GLOBAL ASM_PFX(FspInitApi) -ASM_PFX(FspInitApi): - movl $0x01, %eax - jmp FspApiCommon - -#---------------------------------------------------------------------------- -# NotifyPhase API -# -# This FSP API will notify the FSP about the different phases in the boot -# process -# -#---------------------------------------------------------------------------- -ASM_GLOBAL ASM_PFX(NotifyPhaseApi) -ASM_PFX(NotifyPhaseApi): - movl $0x02, %eax - jmp FspApiCommon - -#---------------------------------------------------------------------------- -# FspMemoryInit API -# -# This FSP API is called after TempRamInit and initializes the memory. -# -#---------------------------------------------------------------------------- -ASM_GLOBAL ASM_PFX(FspMemoryInitApi) -ASM_PFX(FspMemoryInitApi): - movl $0x03, %eax - jmp FspApiCommon - -#---------------------------------------------------------------------------- -# TempRamExitApi API -# -# This API tears down temporary RAM -# -#---------------------------------------------------------------------------- -ASM_GLOBAL ASM_PFX(TempRamExitApi) -ASM_PFX(TempRamExitApi): - movl $0x04, %eax - jmp FspApiCommon - -#---------------------------------------------------------------------------- -# FspSiliconInit API -# -# This FSP API initializes the CPU and the chipset including the IO -# controllers in the chipset to enable normal operation of these devices. -# -#---------------------------------------------------------------------------- -ASM_GLOBAL ASM_PFX(FspSiliconInitApi) -ASM_PFX(FspSiliconInitApi): - movl $0x05, %eax - jmp FspApiCommon - -#---------------------------------------------------------------------------- -# FspApiCommon API -# -# This is the FSP API common entry point to resume the FSP execution -# -#---------------------------------------------------------------------------- -ASM_GLOBAL ASM_PFX(FspApiCommon) -ASM_PFX(FspApiCommon): - # - # EAX holds the API index - # - - # - # Stack must be ready - # - pushl %eax - addl $0x04, %esp - cmpl -4(%esp), %eax - jz FspApiCommonL0 - movl $0x080000003, %eax - jmp FspApiCommonExit - -FspApiCommonL0: - # - # Verify the calling condition - # - pushal - pushl 36(%esp) #push ApiParam [esp + 4 * 8 + 4] - pushl %eax #push ApiIdx - call ASM_PFX(FspApiCallingCheck) - addl $0x08, %esp - cmpl $0x00, %eax - jz FspApiCommonL1 - movl %eax, 0x1C(%esp) # mov dword ptr [esp + 4 * 7], eax - popal - ret - -FspApiCommonL1: - popal - cmpl $0x01, %eax # FspInit API - jz FspApiCommonL2 - cmpl $0x03, %eax # FspMemoryInit API - jz FspApiCommonL2 - call ASM_PFX(AsmGetFspInfoHeader) - jmp Loader2PeiSwitchStack - -FspApiCommonL2: - # - # FspInit and FspMemoryInit APIs, setup the initial stack frame - # - - # - # Place holder to store the FspInfoHeader pointer - # - pushl %eax - - # - # Update the FspInfoHeader pointer - # - pushl %eax - call ASM_PFX(AsmGetFspInfoHeader) - movl %eax, 4(%esp) - popl %eax - - # - # Create a Task Frame in the stack for the Boot Loader - # - pushfl # 2 pushf for 4 byte alignment - cli - pushal - - # - # Reserve 8 bytes for IDT save/restore - # - subl $0x08, %esp - sidt (%esp) - - # - # Setup new FSP stack - # - movl %esp, %edi - movl PcdGet32(PcdTemporaryRamBase), %esp - addl PcdGet32(PcdTemporaryRamSize), %esp - subl $(DATA_LEN_AT_STACK_TOP + 0x40), %esp - - # - # Pass the API Idx to SecStartup - # - pushl %eax - - # - # Pass the BootLoader stack to SecStartup - # - pushl %edi - - # - # Pass entry point of the PEI core - # - call ASM_PFX(AsmGetFspBaseAddress) - movl %eax, %edi - addl PcdGet32(PcdFspAreaSize), %edi - subl $0x20, %edi - addl %ds:(%edi), %eax - pushl %eax - - # - # Pass BFV into the PEI Core - # It uses relative address to calucate the actual boot FV base - # For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase and - # PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs, - # they are different. The code below can handle both cases. - # - call ASM_PFX(AsmGetFspBaseAddress) - movl %eax, %edi - call ASM_PFX(GetBootFirmwareVolumeOffset) - addl %edi, %eax - pushl %eax - - # - # Pass stack base and size into the PEI Core - # - movl PcdGet32(PcdTemporaryRamBase), %eax - addl PcdGet32(PcdTemporaryRamSize), %eax - subl PcdGet32(PcdFspTemporaryRamSize), %eax - pushl %eax - pushl PcdGet32(PcdFspTemporaryRamSize) - - # - # Pass Control into the PEI Core - # - call ASM_PFX(SecStartup) - addl $4, %esp -FspApiCommonExit: - ret - diff --git a/IntelFspPkg/FspSecCore/Ia32/FspHelper.asm b/IntelFspPkg/FspSecCore/Ia32/FspHelper.asm deleted file mode 100644 index b991386c77..0000000000 --- a/IntelFspPkg/FspSecCore/Ia32/FspHelper.asm +++ /dev/null @@ -1,73 +0,0 @@ -;; @file -; Provide FSP helper function. -; -; Copyright (c) 2015, Intel Corporation. All rights reserved.
-; This program and the accompanying materials -; are licensed and made available under the terms and conditions of the BSD License -; which accompanies this distribution. The full text of the license may be found at -; http://opensource.org/licenses/bsd-license.php. -; -; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -;; - - .586p - .model flat,C - .code - -; -; FspInfoHeaderRelativeOff is patched during build process and initialized to offset of the AsmGetFspBaseAddress -; from the FSP Info header. -; -FspInfoHeaderRelativeOff PROC NEAR PUBLIC - ; - ; This value will be pached by the build script - ; - DD 012345678h -FspInfoHeaderRelativeOff ENDP - -; -; Returns FSP Base Address. -; -; This function gets the FSP Info Header using relative addressing and returns the FSP Base from the header structure -; -AsmGetFspBaseAddress PROC NEAR PUBLIC - mov eax, AsmGetFspBaseAddress - sub eax, dword ptr [FspInfoHeaderRelativeOff] - add eax, 01Ch - mov eax, dword ptr [eax] - ret -AsmGetFspBaseAddress ENDP - -; -; No stack counter part of AsmGetFspBaseAddress. Return address is in edi. -; -AsmGetFspBaseAddressNoStack PROC NEAR PUBLIC - mov eax, AsmGetFspBaseAddress - sub eax, dword ptr [FspInfoHeaderRelativeOff] - add eax, 01Ch - mov eax, dword ptr [eax] - jmp edi -AsmGetFspBaseAddressNoStack ENDP - -; -; Returns FSP Info Header. -; -; This function gets the FSP Info Header using relative addressing and returns it -; -AsmGetFspInfoHeader PROC NEAR PUBLIC - mov eax, AsmGetFspBaseAddress - sub eax, dword ptr [FspInfoHeaderRelativeOff] - ret -AsmGetFspInfoHeader ENDP - -; -; No stack counter part of AsmGetFspInfoHeader. Return address is in edi. -; -AsmGetFspInfoHeaderNoStack PROC NEAR PUBLIC - mov eax, AsmGetFspBaseAddress - sub eax, dword ptr [FspInfoHeaderRelativeOff] - jmp edi -AsmGetFspInfoHeaderNoStack ENDP - - END \ No newline at end of file diff --git a/IntelFspPkg/FspSecCore/Ia32/FspHelper.s b/IntelFspPkg/FspSecCore/Ia32/FspHelper.s deleted file mode 100644 index 55d8ae75c0..0000000000 --- a/IntelFspPkg/FspSecCore/Ia32/FspHelper.s +++ /dev/null @@ -1,71 +0,0 @@ -#------------------------------------------------------------------------------ -# -# Copyright (c) 2015, Intel Corporation. All rights reserved.
-# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php. -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -# Abstract: -# -# Provide FSP helper function. -# -#------------------------------------------------------------------------------ - -# -# FspInfoHeaderRelativeOff is patched during build process and initialized to offset of the AsmGetFspBaseAddress -# from the FSP Info header. -# -ASM_GLOBAL ASM_PFX(FspInfoHeaderRelativeOff) -ASM_PFX(FspInfoHeaderRelativeOff): - # - # This value will be pached by the build script - # - .long 0x012345678 - -# -# Returns FSP Base Address. -# -# This function gets the FSP Info Header using relative addressing and returns the FSP Base from the header structure -# -ASM_GLOBAL ASM_PFX(AsmGetFspBaseAddress) -ASM_PFX(AsmGetFspBaseAddress): - mov $AsmGetFspBaseAddress, %eax - sub FspInfoHeaderRelativeOff, %eax - add $0x01C, %eax - mov (%eax), %eax - ret - -# -# No stack counter part of AsmGetFspBaseAddress. Return address is in edi. -# -ASM_GLOBAL ASM_PFX(AsmGetFspBaseAddressNoStack) -ASM_PFX(AsmGetFspBaseAddressNoStack): - mov $AsmGetFspBaseAddress, %eax - sub FspInfoHeaderRelativeOff, %eax - add $0x01C, %eax - mov (%eax), %eax - jmp *%edi - -# -# Returns FSP Info Header. -# -# This function gets the FSP Info Header using relative addressing and returns it -# -ASM_GLOBAL ASM_PFX(AsmGetFspInfoHeader) -ASM_PFX(AsmGetFspInfoHeader): - mov $AsmGetFspBaseAddress, %eax - sub FspInfoHeaderRelativeOff, %eax - ret - -# -# No stack counter part of AsmGetFspInfoHeader. Return address is in edi. -# -ASM_GLOBAL ASM_PFX(AsmGetFspInfoHeaderNoStack) -ASM_PFX(AsmGetFspInfoHeaderNoStack): - mov $AsmGetFspBaseAddress, %eax - sub FspInfoHeaderRelativeOff, %eax - jmp *%edi diff --git a/IntelFspPkg/FspSecCore/Ia32/InitializeFpu.asm b/IntelFspPkg/FspSecCore/Ia32/InitializeFpu.asm deleted file mode 100644 index 07f504da4b..0000000000 --- a/IntelFspPkg/FspSecCore/Ia32/InitializeFpu.asm +++ /dev/null @@ -1,79 +0,0 @@ -;------------------------------------------------------------------------------ -; -; Copyright (c) 2014, Intel Corporation. All rights reserved.
-; This program and the accompanying materials -; are licensed and made available under the terms and conditions of the BSD License -; which accompanies this distribution. The full text of the license may be found at -; http://opensource.org/licenses/bsd-license.php. -; -; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -; -; Abstract: -; -;------------------------------------------------------------------------------ - - .686 - .model flat,C - .const -; -; Float control word initial value: -; all exceptions masked, double-precision, round-to-nearest -; -mFpuControlWord DW 027Fh -; -; Multimedia-extensions control word: -; all exceptions masked, round-to-nearest, flush to zero for masked underflow -; -mMmxControlWord DD 01F80h - - .xmm - .code - -; -; Initializes floating point units for requirement of UEFI specification. -; -; This function initializes floating-point control word to 0x027F (all exceptions -; masked,double-precision, round-to-nearest) and multimedia-extensions control word -; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero -; for masked underflow). -; -InitializeFloatingPointUnits PROC PUBLIC - - push ebx - - ; - ; Initialize floating point units - ; - finit - fldcw mFpuControlWord - - ; - ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test - ; whether the processor supports SSE instruction. - ; - mov eax, 1 - cpuid - bt edx, 25 - jnc Done - - ; - ; Set OSFXSR bit 9 in CR4 - ; - mov eax, cr4 - or eax, BIT9 - mov cr4, eax - - ; - ; The processor should support SSE instruction and we can use - ; ldmxcsr instruction - ; - ldmxcsr mMmxControlWord -Done: - pop ebx - - ret - -InitializeFloatingPointUnits ENDP - -END diff --git a/IntelFspPkg/FspSecCore/Ia32/InitializeFpu.s b/IntelFspPkg/FspSecCore/Ia32/InitializeFpu.s deleted file mode 100644 index ed1ce0ef57..0000000000 --- a/IntelFspPkg/FspSecCore/Ia32/InitializeFpu.s +++ /dev/null @@ -1,73 +0,0 @@ -#------------------------------------------------------------------------------ -# -# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.
-# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php. -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -# Abstract: -# -#------------------------------------------------------------------------------ - -# -# Float control word initial value: -# all exceptions masked, double-precision, round-to-nearest -# -ASM_PFX(mFpuControlWord): .word 0x027F -# -# Multimedia-extensions control word: -# all exceptions masked, round-to-nearest, flush to zero for masked underflow -# -ASM_PFX(mMmxControlWord): .long 0x01F80 - - - -# -# Initializes floating point units for requirement of UEFI specification. -# -# This function initializes floating-point control word to 0x027F (all exceptions -# masked,double-precision, round-to-nearest) and multimedia-extensions control word -# (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero -# for masked underflow). -# -ASM_GLOBAL ASM_PFX(InitializeFloatingPointUnits) -ASM_PFX(InitializeFloatingPointUnits): - - pushl %ebx - - # - # Initialize floating point units - # - finit - fldcw ASM_PFX(mFpuControlWord) - - # - # Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test - # whether the processor supports SSE instruction. - # - movl $1, %eax - cpuid - btl $25, %edx - jnc Done - - # - # Set OSFXSR bit 9 in CR4 - # - movl %cr4, %eax - orl $BIT9, %eax - movl %eax, %cr4 - - # - # The processor should support SSE instruction and we can use - # ldmxcsr instruction - # - ldmxcsr ASM_PFX(mMmxControlWord) - -Done: - popl %ebx - - ret diff --git a/IntelFspPkg/FspSecCore/Ia32/MicrocodeLoad.inc b/IntelFspPkg/FspSecCore/Ia32/MicrocodeLoad.inc deleted file mode 100644 index 6fbf430707..0000000000 --- a/IntelFspPkg/FspSecCore/Ia32/MicrocodeLoad.inc +++ /dev/null @@ -1,49 +0,0 @@ -;------------------------------------------------------------------------------ -; -; Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.
-; This program and the accompanying materials -; are licensed and made available under the terms and conditions of the BSD License -; which accompanies this distribution. The full text of the license may be found at -; http://opensource.org/licenses/bsd-license.php. -; -; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -; -; Abstract: -; -;------------------------------------------------------------------------------ - -MSR_IA32_PLATFORM_ID EQU 000000017h -MSR_IA32_BIOS_UPDT_TRIG EQU 000000079h -MSR_IA32_BIOS_SIGN_ID EQU 00000008bh - - -MicrocodeHdr STRUCT 1t - MicrocodeHdrVersion DWORD ? - MicrocodeHdrRevision DWORD ? - MicrocodeHdrDate DWORD ? - MicrocodeHdrProcessor DWORD ? - MicrocodeHdrChecksum DWORD ? - MicrocodeHdrLoader DWORD ? - MicrocodeHdrFlags DWORD ? - MicrocodeHdrDataSize DWORD ? - MicrocodeHdrTotalSize DWORD ? - MicrocodeHdrRsvd DWORD 3t DUP (?) -MicrocodeHdr ENDS - -ExtSigHdr STRUCT 1t - ExtSigHdrCount DWORD ? - ExtSigHdrChecksum DWORD ? - ExtSigHdrRsvd DWORD 3t DUP (?) -ExtSigHdr ENDS - -ExtSig STRUCT 1t - ExtSigProcessor DWORD ? - ExtSigFlags DWORD ? - ExtSigChecksum DWORD ? -ExtSig ENDS - -LoadMicrocodeParams STRUCT 1t - MicrocodeCodeAddr DWORD ? - MicrocodeCodeSize DWORD ? -LoadMicrocodeParams ENDS diff --git a/IntelFspPkg/FspSecCore/Ia32/ResetVec.asm16 b/IntelFspPkg/FspSecCore/Ia32/ResetVec.asm16 deleted file mode 100644 index f77c9a46dd..0000000000 --- a/IntelFspPkg/FspSecCore/Ia32/ResetVec.asm16 +++ /dev/null @@ -1,103 +0,0 @@ -;------------------------------------------------------------------------------ -; -; Copyright (c) 2014, Intel Corporation. All rights reserved.
-; This program and the accompanying materials -; are licensed and made available under the terms and conditions of the BSD License -; which accompanies this distribution. The full text of the license may be found at -; http://opensource.org/licenses/bsd-license.php. -; -; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -; -; Abstract: -; -; Reset Vector Data structure -; This structure is located at 0xFFFFFFC0 -; -;------------------------------------------------------------------------------ - - .model tiny - .686p - .stack 0h - .code - -; -; The layout of this file is fixed. The build tool makes assumption of the layout. -; - - ORG 0h -; -; Reserved -; -ReservedData DD 0eeeeeeeeh, 0eeeeeeeeh - - ORG 10h -; -; This is located at 0xFFFFFFD0h -; - mov di, "AP" - jmp ApStartup - - ORG 20h -; -; Pointer to the entry point of the PEI core -; It is located at 0xFFFFFFE0, and is fixed up by some build tool -; So if the value 8..1 appears in the final FD image, tool failure occurs. -; -PeiCoreEntryPoint DD 12345678h - -; -; This is the handler for all kinds of exceptions. Since it's for debugging -; purpose only, nothing except a deadloop would be done here. Developers could -; analyze the cause of the exception if a debugger had been attached. -; -InterruptHandler PROC - jmp $ - iret -InterruptHandler ENDP - - ORG 30h -; -; For IA32, the reset vector must be at 0xFFFFFFF0, i.e., 4G-16 byte -; Execution starts here upon power-on/platform-reset. -; -ResetHandler: - nop - nop - -ApStartup: - ; - ; Jmp Rel16 instruction - ; Use machine code directly in case of the assembler optimization - ; SEC entry point relatvie address will be fixed up by some build tool. - ; - ; Typically, SEC entry point is the function _ModuleEntryPoint() defined in - ; SecEntry.asm - ; - DB 0e9h - DW -3 - - - ORG 38h -; -; Ap reset vector segment address is at 0xFFFFFFF8 -; This will be fixed up by some build tool, -; so if the value 1..8 appears in the final FD image, -; tool failure occurs -; -ApSegAddress dd 12345678h - - ORG 3ch -; -; BFV Base is at 0xFFFFFFFC -; This will be fixed up by some build tool, -; so if the value 1..8 appears in the final FD image, -; tool failure occurs. -; -BfvBase DD 12345678h - -; -; Nothing can go here, otherwise the layout of this file would change. -; - - END diff --git a/IntelFspPkg/FspSecCore/Ia32/SaveRestoreSse.inc b/IntelFspPkg/FspSecCore/Ia32/SaveRestoreSse.inc deleted file mode 100644 index afc3ce061b..0000000000 --- a/IntelFspPkg/FspSecCore/Ia32/SaveRestoreSse.inc +++ /dev/null @@ -1,184 +0,0 @@ -;------------------------------------------------------------------------------ -; -; Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.
-; This program and the accompanying materials -; are licensed and made available under the terms and conditions of the BSD License -; which accompanies this distribution. The full text of the license may be found at -; http://opensource.org/licenses/bsd-license.php. -; -; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -; -; Abstract: -; -; Provide macro for register save/restore using SSE registers -; -;------------------------------------------------------------------------------ - -; -; Define SSE instruction set -; -IFDEF USE_SSE41_FLAG -; -; Define SSE macros using SSE 4.1 instructions -; -SXMMN MACRO XMM, IDX, REG - pinsrd XMM, REG, (IDX AND 3) - ENDM - -LXMMN MACRO XMM, REG, IDX - pextrd REG, XMM, (IDX AND 3) - ENDM -ELSE -; -; Define SSE macros using SSE 2 instructions -; -SXMMN MACRO XMM, IDX, REG - pinsrw XMM, REG, (IDX AND 3) * 2 - ror REG, 16 - pinsrw XMM, REG, (IDX AND 3) * 2 + 1 - rol REG, 16 - ENDM - -LXMMN MACRO XMM, REG, IDX - pshufd XMM, XMM, (0E4E4E4h SHR (IDX * 2)) AND 0FFh - movd REG, XMM - pshufd XMM, XMM, (0E4E4E4h SHR (IDX * 2 + (IDX AND 1) * 4)) AND 0FFh - ENDM -ENDIF - -; -; XMM7 to save/restore EBP, EBX, ESI, EDI -; -SAVE_REGS MACRO - SXMMN xmm7, 0, ebp - SXMMN xmm7, 1, ebx - SXMMN xmm7, 2, esi - SXMMN xmm7, 3, edi - SAVE_ESP - ENDM - -LOAD_REGS MACRO - LXMMN xmm7, ebp, 0 - LXMMN xmm7, ebx, 1 - LXMMN xmm7, esi, 2 - LXMMN xmm7, edi, 3 - LOAD_ESP - ENDM - -; -; XMM6 to save/restore EAX, EDX, ECX, ESP -; -LOAD_EAX MACRO - LXMMN xmm6, eax, 1 - ENDM - -SAVE_EAX MACRO - SXMMN xmm6, 1, eax - ENDM - -LOAD_EDX MACRO - LXMMN xmm6, edx, 2 - ENDM - -SAVE_EDX MACRO - SXMMN xmm6, 2, edx - ENDM - -SAVE_ECX MACRO - SXMMN xmm6, 3, ecx - ENDM - -LOAD_ECX MACRO - LXMMN xmm6, ecx, 3 - ENDM - -SAVE_ESP MACRO - SXMMN xmm6, 0, esp - ENDM - -LOAD_ESP MACRO - movd esp, xmm6 - ENDM - -; -; XMM5 for calling stack -; -CALL_XMM MACRO Entry - local ReturnAddress - mov esi, offset ReturnAddress - pslldq xmm5, 4 -IFDEF USE_SSE41_FLAG - pinsrd xmm5, esi, 0 -ELSE - pinsrw xmm5, esi, 0 - ror esi, 16 - pinsrw xmm5, esi, 1 -ENDIF - mov esi, Entry - jmp esi -ReturnAddress: - ENDM - -RET_XMM MACRO - movd esi, xmm5 - psrldq xmm5, 4 - jmp esi - ENDM - -ENABLE_SSE MACRO - ; - ; Initialize floating point units - ; - local NextAddress - jmp NextAddress -ALIGN 4 - ; - ; Float control word initial value: - ; all exceptions masked, double-precision, round-to-nearest - ; -FpuControlWord DW 027Fh - ; - ; Multimedia-extensions control word: - ; all exceptions masked, round-to-nearest, flush to zero for masked underflow - ; -MmxControlWord DD 01F80h -SseError: - ; - ; Processor has to support SSE - ; - jmp SseError -NextAddress: - finit - fldcw FpuControlWord - - ; - ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test - ; whether the processor supports SSE instruction. - ; - mov eax, 1 - cpuid - bt edx, 25 - jnc SseError - -IFDEF USE_SSE41_FLAG - ; - ; SSE 4.1 support - ; - bt ecx, 19 - jnc SseError -ENDIF - - ; - ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10) - ; - mov eax, cr4 - or eax, 00000600h - mov cr4, eax - - ; - ; The processor should support SSE instruction and we can use - ; ldmxcsr instruction - ; - ldmxcsr MmxControlWord - ENDM diff --git a/IntelFspPkg/FspSecCore/Ia32/Stack.asm b/IntelFspPkg/FspSecCore/Ia32/Stack.asm deleted file mode 100644 index f96a55f040..0000000000 --- a/IntelFspPkg/FspSecCore/Ia32/Stack.asm +++ /dev/null @@ -1,82 +0,0 @@ -;------------------------------------------------------------------------------ -; -; Copyright (c) 2014, Intel Corporation. All rights reserved.
-; This program and the accompanying materials -; are licensed and made available under the terms and conditions of the BSD License -; which accompanies this distribution. The full text of the license may be found at -; http://opensource.org/licenses/bsd-license.php. -; -; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -; -; Abstract: -; -; Switch the stack from temporary memory to permenent memory. -; -;------------------------------------------------------------------------------ - - .586p - .model flat,C - .code - -;------------------------------------------------------------------------------ -; VOID -; EFIAPI -; SecSwitchStack ( -; UINT32 TemporaryMemoryBase, -; UINT32 PermenentMemoryBase -; ); -;------------------------------------------------------------------------------ -SecSwitchStack PROC - ; - ; Save three register: eax, ebx, ecx - ; - push eax - push ebx - push ecx - push edx - - ; - ; !!CAUTION!! this function address's is pushed into stack after - ; migration of whole temporary memory, so need save it to permenent - ; memory at first! - ; - - mov ebx, [esp + 20] ; Save the first parameter - mov ecx, [esp + 24] ; Save the second parameter - - ; - ; Save this function's return address into permenent memory at first. - ; Then, Fixup the esp point to permenent memory - ; - mov eax, esp - sub eax, ebx - add eax, ecx - mov edx, dword ptr [esp] ; copy pushed register's value to permenent memory - mov dword ptr [eax], edx - mov edx, dword ptr [esp + 4] - mov dword ptr [eax + 4], edx - mov edx, dword ptr [esp + 8] - mov dword ptr [eax + 8], edx - mov edx, dword ptr [esp + 12] - mov dword ptr [eax + 12], edx - mov edx, dword ptr [esp + 16] ; Update this function's return address into permenent memory - mov dword ptr [eax + 16], edx - mov esp, eax ; From now, esp is pointed to permenent memory - - ; - ; Fixup the ebp point to permenent memory - ; - mov eax, ebp - sub eax, ebx - add eax, ecx - mov ebp, eax ; From now, ebp is pointed to permenent memory - - pop edx - pop ecx - pop ebx - pop eax - ret -SecSwitchStack ENDP - - END diff --git a/IntelFspPkg/FspSecCore/Ia32/Stacks.s b/IntelFspPkg/FspSecCore/Ia32/Stacks.s deleted file mode 100644 index 0ab214d0ee..0000000000 --- a/IntelFspPkg/FspSecCore/Ia32/Stacks.s +++ /dev/null @@ -1,86 +0,0 @@ -#------------------------------------------------------------------------------ -# -# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.
-# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php. -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -# Abstract: -# -# Switch the stack from temporary memory to permenent memory. -# -#------------------------------------------------------------------------------ - -ASM_GLOBAL ASM_PFX(SecSwitchStack) - -#------------------------------------------------------------------------------ -# VOID -# EFIAPI -# SecSwitchStack ( -# UINT32 TemporaryMemoryBase, -# UINT32 PermenentMemoryBase -# ) -#------------------------------------------------------------------------------ -ASM_GLOBAL ASM_PFX(SecSwitchStack) -ASM_PFX(SecSwitchStack): -# -# Save four registers: eax, ebx, ecx, edx -# - pushl %eax - pushl %ebx - pushl %ecx - pushl %edx - -# -# !!CAUTION!! this function address's is pushed into stack after -# migration of whole temporary memory, so need save it to permenent -# memory at first! -# - - movl 20(%esp), %ebx # Save the first parameter - movl 24(%esp), %ecx # Save the second parameter - -# -# Save this function's return address into permenent memory at first. -# Then, Fixup the esp point to permenent memory -# - - movl %esp, %eax - subl %ebx, %eax - addl %ecx, %eax - movl (%esp), %edx # copy pushed register's value to permenent memory - movl %edx, (%eax) - movl 4(%esp), %edx - movl %edx, 4(%eax) - movl 8(%esp), %edx - movl %edx, 8(%eax) - movl 12(%esp), %edx - movl %edx, 12(%eax) - movl 16(%esp), %edx # Update this function's return address into permenent memory - movl %edx, 16(%eax) - movl %eax, %esp # From now, esp is pointed to permenent memory - -# -# Fixup the ebp point to permenent memory -# - movl %ebp, %eax - subl %ebx, %eax - addl %ecx, %eax - movl %eax, %ebp # From now, ebp is pointed to permenent memory - -# -# Fixup callee's ebp point for PeiDispatch -# -# movl %ebp, %eax -# subl %ebx, %eax -# addl %ecx, %eax -# movl %eax, %ebp # From now, ebp is pointed to permenent memory - popl %edx - popl %ecx - popl %ebx - popl %eax - ret \ No newline at end of file -- cgit v1.2.3