From 4140a6635b4784db9d0125e96d521d01053eca2c Mon Sep 17 00:00:00 2001
From: rsun3 <rsun3@6f19259b-4bc3-4df7-8a09-765794883524>
Date: Thu, 11 Feb 2010 02:33:16 +0000
Subject: Coding style fix and minor improvements.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9977 6f19259b-4bc3-4df7-8a09-765794883524
---
 MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 26 ++++++++++++++++--------
 1 file changed, 17 insertions(+), 9 deletions(-)

(limited to 'MdeModulePkg/Core/DxeIplPeim/X64')

diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
index e58351c2ee..fedfa10713 100644
--- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
+++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
@@ -4,18 +4,18 @@
   enter Long Mode (x64 64-bit mode).
 
   While we make a 1:1 mapping (identity mapping) for all physical pages 
-  we still need to use the MTRR's to ensure that the cachability attirbutes
+  we still need to use the MTRR's to ensure that the cachability attributes
   for all memory regions is correct.
 
   The basic idea is to use 2MB page table entries where ever possible. If
   more granularity of cachability is required then 4K page tables are used.
 
   References:
-    1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel
-    2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
-    3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
+    1) IA-32 Intel(R) Architecture Software Developer's Manual Volume 1:Basic Architecture, Intel
+    2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
+    3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
 
-Copyright (c) 2006 - 2008, Intel Corporation. <BR>
+Copyright (c) 2006 - 2010, Intel Corporation. <BR>
 All rights reserved. This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD License
 which accompanies this distribution.  The full text of the license may be found at
@@ -51,8 +51,8 @@ CreateIdentityMappingPageTables (
   UINTN                                         IndexOfPml4Entries;
   UINTN                                         IndexOfPdpEntries;
   UINTN                                         IndexOfPageDirectoryEntries;
-  UINTN                                         NumberOfPml4EntriesNeeded;
-  UINTN                                         NumberOfPdpEntriesNeeded;
+  UINT32                                        NumberOfPml4EntriesNeeded;
+  UINT32                                        NumberOfPdpEntriesNeeded;
   PAGE_MAP_AND_DIRECTORY_POINTER                *PageMapLevel4Entry;
   PAGE_MAP_AND_DIRECTORY_POINTER                *PageMap;
   PAGE_MAP_AND_DIRECTORY_POINTER                *PageDirectoryPointerEntry;
@@ -71,14 +71,22 @@ CreateIdentityMappingPageTables (
     PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;
   }
 
+  //
+  // IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses.
+  //
+  ASSERT (PhysicalAddressBits <= 52);
+  if (PhysicalAddressBits > 48) {
+    PhysicalAddressBits = 48;
+  }
+
   //
   // Calculate the table entries needed.
   //
   if (PhysicalAddressBits <= 39 ) {
     NumberOfPml4EntriesNeeded = 1;
-    NumberOfPdpEntriesNeeded =  LShiftU64 (1, (PhysicalAddressBits - 30));
+    NumberOfPdpEntriesNeeded =  1 << (PhysicalAddressBits - 30);
   } else {
-    NumberOfPml4EntriesNeeded = LShiftU64 (1, (PhysicalAddressBits - 39));
+    NumberOfPml4EntriesNeeded = 1 << (PhysicalAddressBits - 39);
     NumberOfPdpEntriesNeeded = 512;
   }
 
-- 
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