From be5f16148584b0d771bdab651455cd9e27f556ce Mon Sep 17 00:00:00 2001 From: qhuang8 Date: Wed, 3 Dec 2008 02:19:49 +0000 Subject: Add AsmEnableCache() and AsmDisableCache() as the IA32 & x64 specific BaseLib API. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@6807 6f19259b-4bc3-4df7-8a09-765794883524 --- MdePkg/Include/Library/BaseLib.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'MdePkg/Include') diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h index 4ffddfd5f6..3cb2cdb154 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -5212,6 +5212,34 @@ AsmCpuidEx ( ); +/** + Set CD bit and clear NW bit of CR0 followed by a WBINVD. + + Disables the caches by setting the CD bit of CR0 to 1, clearing the NW bit of CR0 to 0, + and executing a WBINVD instruction. This function is only available on IA-32 and x64. + +**/ +VOID +EFIAPI +AsmDisableCache ( + VOID + ); + + +/** + Perform a WBINVD and clear both the CD and NW bits of CR0. + + Enables the caches by executing a WBINVD instruction and then clear both the CD and NW + bits of CR0 to 0. This function is only available on IA-32 and x64. + +**/ +VOID +EFIAPI +AsmEnableCache ( + VOID + ); + + /** Returns the lower 32-bits of a Machine Specific Register(MSR). -- cgit v1.2.3