From 9f4f2f0e15252004e06ca246300a2fe21b8bf0ae Mon Sep 17 00:00:00 2001 From: mdkinney Date: Mon, 24 Nov 2008 08:30:58 +0000 Subject: Add EnableCache() and DisableCache() implementations for IA32 and X64 to the BaseLib git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@6705 6f19259b-4bc3-4df7-8a09-765794883524 --- MdePkg/Library/BaseLib/Ia32/EnableCache.asm | 45 +++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 MdePkg/Library/BaseLib/Ia32/EnableCache.asm (limited to 'MdePkg/Library/BaseLib/Ia32/EnableCache.asm') diff --git a/MdePkg/Library/BaseLib/Ia32/EnableCache.asm b/MdePkg/Library/BaseLib/Ia32/EnableCache.asm new file mode 100644 index 0000000000..e25a5bf44d --- /dev/null +++ b/MdePkg/Library/BaseLib/Ia32/EnableCache.asm @@ -0,0 +1,45 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006, Intel Corporation +; All rights reserved. This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +; Module Name: +; +; EnableCache.Asm +; +; Abstract: +; +; Flush all caches with a WBINVD instruction, clear the CD bit of CR0 to 0, and clear +; the NW bit of CR0 to 0 +; +; Notes: +; +;------------------------------------------------------------------------------ + + .386p + .model flat,C + .code + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; AsmEnableCache ( +; VOID +; ); +;------------------------------------------------------------------------------ +AsmEnableCache PROC + wbinvd + mov eax, cr0 + btr eax, 29 + btr eax, 30 + mov cr0, eax + ret +AsmEnableCache ENDP + + END -- cgit v1.2.3