From 881813d7a93d9009c873515b043c41c4554779e4 Mon Sep 17 00:00:00 2001
From: Michael Kinney <michael.d.kinney@intel.com>
Date: Mon, 27 Apr 2015 19:37:15 +0000
Subject: MdePkg/BaseLib: Support IA32 processors without CLFLUSH

Use CPUID Leaf 01 to detect support for CLFLUSH instruction.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17212 6f19259b-4bc3-4df7-8a09-765794883524
---
 MdePkg/Library/BaseLib/Ia32/FlushCacheLine.asm | 13 ++++++++++++-
 MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c   | 18 ++++++++++++++++--
 MdePkg/Library/BaseLib/Ia32/GccInline.c        | 17 +++++++++++++++--
 3 files changed, 43 insertions(+), 5 deletions(-)

(limited to 'MdePkg/Library/BaseLib')

diff --git a/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.asm b/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.asm
index 124d761060..a64f96bf7e 100644
--- a/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.asm
+++ b/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.asm
@@ -1,6 +1,6 @@
 ;------------------------------------------------------------------------------
 ;
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
 ; This program and the accompanying materials
 ; are licensed and made available under the terms and conditions of the BSD License
 ; which accompanies this distribution.  The full text of the license may be found at
@@ -34,9 +34,20 @@
 ;   );
 ;------------------------------------------------------------------------------
 AsmFlushCacheLine   PROC
+    ;
+    ; If the CPU does not support CLFLUSH instruction, 
+    ; then promote flush range to flush entire cache.
+    ;
+    mov     eax, 1
+    cpuid
     mov     eax, [esp + 4]
+    test    edx, BIT19
+    jz      @F
     clflush [eax]
     ret
+@@:
+    wbinvd
+    ret
 AsmFlushCacheLine   ENDP
 
     END
diff --git a/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c b/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c
index 3b3a43324e..7ad12aba14 100644
--- a/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c
+++ b/MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c
@@ -1,7 +1,7 @@
 /** @file
   AsmFlushCacheLine function
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -36,9 +36,23 @@ AsmFlushCacheLine (
   IN      VOID                      *LinearAddress
   )
 {
+  //
+  // If the CPU does not support CLFLUSH instruction, 
+  // then promote flush range to flush entire cache.
+  //
   _asm {
-    mov     eax, LinearAddress
+    mov     eax, 1
+    cpuid
+    test    edx, BIT19
+    jz      NoClflush
+    mov     eax, [esp + 4]
     clflush [eax]
+    jmp     Done
+NoClflush:
+    wbinvd
+Done:
   }
+  
+  return LinearAddress;
 }
 
diff --git a/MdePkg/Library/BaseLib/Ia32/GccInline.c b/MdePkg/Library/BaseLib/Ia32/GccInline.c
index 02af3f6646..f52a1fe171 100644
--- a/MdePkg/Library/BaseLib/Ia32/GccInline.c
+++ b/MdePkg/Library/BaseLib/Ia32/GccInline.c
@@ -1,7 +1,7 @@
 /** @file
   GCC inline implementation of BaseLib processor specific functions.
   
-  Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
   Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -1745,6 +1745,19 @@ AsmFlushCacheLine (
   IN      VOID                      *LinearAddress
   )
 {
+  UINT32  RegEdx;
+
+  //
+  // If the CPU does not support CLFLUSH instruction, 
+  // then promote flush range to flush entire cache.
+  //
+  AsmCpuid (0x01, NULL, NULL, NULL, &RegEdx);
+  if ((RegEdx & BIT19) == 0) {
+    __asm__ __volatile__ ("wbinvd":::"memory");
+    return LinearAddress;
+  }
+
+
   __asm__ __volatile__ (
     "clflush (%0)"
     : "+a" (LinearAddress) 
@@ -1752,7 +1765,7 @@ AsmFlushCacheLine (
     : "memory"
     );
     
-    return LinearAddress;
+  return LinearAddress;
 }
 
 
-- 
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