From 7ecfa0aa38a3601c958a81dc36f69b5e04e40584 Mon Sep 17 00:00:00 2001 From: Laszlo Ersek Date: Thu, 1 Dec 2016 02:20:15 +0100 Subject: OvmfPkg/SmmControl2Dxe: correct PCI_CONFIG_READ_WRITE in S3 boot script EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE expects the PCI address to access in UEFI encoding, not in edk2/PciLib encoding. Introduce the POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS() macro, and with it, store the ICH9_GEN_PMCON_1 register's address to the boot script in UEFI representation. Cc: Jiewen Yao Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek Reviewed-by: Jordan Justen --- OvmfPkg/Include/IndustryStandard/Q35MchIch9.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'OvmfPkg/Include') diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h index 4dc2c39901..f480455ae4 100644 --- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h +++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h @@ -19,6 +19,9 @@ #define __Q35_MCH_ICH9_H__ #include +#include +#include +#include // // Host Bridge Device ID (DID) value for Q35/MCH @@ -75,6 +78,9 @@ #define POWER_MGMT_REGISTER_Q35(Offset) \ PCI_LIB_ADDRESS (0, 0x1f, 0, (Offset)) +#define POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS(Offset) \ + EFI_PCI_ADDRESS (0, 0x1f, 0, (Offset)) + #define ICH9_PMBASE 0x40 #define ICH9_PMBASE_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \ BIT10 | BIT9 | BIT8 | BIT7) -- cgit v1.2.3