From b4f4d5a2e507124094a8304ba75a1995b72cfadc Mon Sep 17 00:00:00 2001
From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Date: Tue, 20 Feb 2018 15:42:54 +0000
Subject: Platform/96Boards: add a driver for the Secure96 mezzanine board

Add a driver that describes the Secure96 mezzanine board, and exposes
both the information required to describe it to the OS using a DT overlay,
and to describe it to UEFI itself.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
 Platform/96Boards/Secure96Dxe/Secure96.dts | 85 ++++++++++++++++++++++++++++++
 1 file changed, 85 insertions(+)
 create mode 100644 Platform/96Boards/Secure96Dxe/Secure96.dts

(limited to 'Platform/96Boards/Secure96Dxe/Secure96.dts')

diff --git a/Platform/96Boards/Secure96Dxe/Secure96.dts b/Platform/96Boards/Secure96Dxe/Secure96.dts
new file mode 100644
index 0000000000..b56ce59985
--- /dev/null
+++ b/Platform/96Boards/Secure96Dxe/Secure96.dts
@@ -0,0 +1,85 @@
+/** @file
+ * Copyright (c) 2018, Linaro Limited. All rights reserved.
+ *
+ * This program and the accompanying materials are licensed and made
+ * available under the terms and conditions of the BSD License which
+ * accompanies this distribution.  The full text of the license may be
+ * found at http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+ * IMPLIED.
+ */
+
+#include "Secure96.h"
+
+//
+// Define a placeholder value for the GPIO phandle property cells appearing
+// in this file. It is up to the driver code to discover the actual phandle
+// value from the platform device tree and patch the overlay DTB before it
+// can be applied.
+//
+#define GPIO_PARENT_PLACEHOLDER_PHANDLE     0x0
+
+/dts-v1/;
+/plugin/;
+
+/ {
+    fragment@0 {
+        target-path = "I2C_PARENT_PLACEHOLDER_STRING";
+        __overlay__ {
+            clock-frequency = <100000>;
+
+            ATSHA204A_DT_NODENAME {
+                compatible = "atmel,atsha204a";
+                reg = <ATSHA204A_SLAVE_ADDRESS>;
+            };
+
+            ATECC508A_DT_NODENAME {
+                compatible = "atmel,atecc508a";
+                reg = <ATECC508A_SLAVE_ADDRESS>;
+            };
+        };
+    };
+
+    fragment@1 {
+        target-path = "SPI_PARENT_PLACEHOLDER_STRING";
+        __overlay__ {
+            INFINEON_SLB9670_DT_NODENAME {
+                compatible = "infineon,slb9670";
+                reg = <INFINEON_SLB9670_SPI_CS>;
+                spi-max-frequency = <22500000>;
+            };
+        };
+    };
+
+    fragment@2 {
+        target-path = "/";
+        __overlay__ {
+            gpio-leds {
+                compatible = "gpio-leds";
+
+                secure96-u1 {
+                    gpios = <GPIO_PARENT_PLACEHOLDER_PHANDLE
+                             FixedPcdGet32 (PcdGpioPinG)
+                             FixedPcdGet32 (PcdGpioPolarity)>;
+                };
+                secure96-u2 {
+                    gpios = <GPIO_PARENT_PLACEHOLDER_PHANDLE
+                             FixedPcdGet32 (PcdGpioPinF)
+                             FixedPcdGet32 (PcdGpioPolarity)>;
+                };
+                secure96-u3 {
+                    gpios = <GPIO_PARENT_PLACEHOLDER_PHANDLE
+                             FixedPcdGet32 (PcdGpioPinI)
+                             FixedPcdGet32 (PcdGpioPolarity)>;
+                };
+                secure96-u4 {
+                    gpios = <GPIO_PARENT_PLACEHOLDER_PHANDLE
+                             FixedPcdGet32 (PcdGpioPinH)
+                             FixedPcdGet32 (PcdGpioPolarity)>;
+                };
+            };
+        };
+    };
+};
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