From 430bc861413cb2e8f0e50e42b56da9860584c49a Mon Sep 17 00:00:00 2001 From: Leif Lindholm Date: Thu, 3 Aug 2017 12:24:14 +0100 Subject: Platform: import ARM ltd. platforms Import ARM Ltd. platforms Juno, FVP, TC2 at commit efd798c1eb of https://git.linaro.org/uefi/OpenPlatformPkg.git Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm --- .../ARM/JunoPkg/AcpiTables/AcpiSsdtRootPci.asl | 219 ++++++ Platform/ARM/JunoPkg/AcpiTables/AcpiTables.inf | 63 ++ Platform/ARM/JunoPkg/AcpiTables/Dbg2.aslc | 92 +++ Platform/ARM/JunoPkg/AcpiTables/Dsdt.asl | 388 +++++++++ Platform/ARM/JunoPkg/AcpiTables/Fadt.aslc | 99 +++ Platform/ARM/JunoPkg/AcpiTables/Gtdt.aslc | 113 +++ Platform/ARM/JunoPkg/AcpiTables/Madt.aslc | 131 ++++ Platform/ARM/JunoPkg/AcpiTables/Spcr.aslc | 99 +++ Platform/ARM/JunoPkg/ArmJuno.dsc | 356 +++++++++ Platform/ARM/JunoPkg/ArmJuno.fdf | 378 +++++++++ .../JunoPciHostBridgeLib/JunoPciHostBridgeLib.c | 201 +++++ .../JunoPciHostBridgeLib/JunoPciHostBridgeLib.inf | 77 ++ .../Library/JunoPciHostBridgeLib/XPressRich3.c | 182 +++++ .../Library/JunoPciHostBridgeLib/XPressRich3.h | 107 +++ .../JunoPkg/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 865 +++++++++++++++++++++ .../SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 68 ++ 16 files changed, 3438 insertions(+) create mode 100644 Platform/ARM/JunoPkg/AcpiTables/AcpiSsdtRootPci.asl create mode 100644 Platform/ARM/JunoPkg/AcpiTables/AcpiTables.inf create mode 100644 Platform/ARM/JunoPkg/AcpiTables/Dbg2.aslc create mode 100644 Platform/ARM/JunoPkg/AcpiTables/Dsdt.asl create mode 100644 Platform/ARM/JunoPkg/AcpiTables/Fadt.aslc create mode 100644 Platform/ARM/JunoPkg/AcpiTables/Gtdt.aslc create mode 100644 Platform/ARM/JunoPkg/AcpiTables/Madt.aslc create mode 100644 Platform/ARM/JunoPkg/AcpiTables/Spcr.aslc create mode 100644 Platform/ARM/JunoPkg/ArmJuno.dsc create mode 100644 Platform/ARM/JunoPkg/ArmJuno.fdf create mode 100644 Platform/ARM/JunoPkg/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.c create mode 100644 Platform/ARM/JunoPkg/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.inf create mode 100644 Platform/ARM/JunoPkg/Library/JunoPciHostBridgeLib/XPressRich3.c create mode 100644 Platform/ARM/JunoPkg/Library/JunoPciHostBridgeLib/XPressRich3.h create mode 100644 Platform/ARM/JunoPkg/SmbiosPlatformDxe/SmbiosPlatformDxe.c create mode 100644 Platform/ARM/JunoPkg/SmbiosPlatformDxe/SmbiosPlatformDxe.inf (limited to 'Platform/ARM/JunoPkg') diff --git a/Platform/ARM/JunoPkg/AcpiTables/AcpiSsdtRootPci.asl b/Platform/ARM/JunoPkg/AcpiTables/AcpiSsdtRootPci.asl new file mode 100644 index 0000000000..96f1c59305 --- /dev/null +++ b/Platform/ARM/JunoPkg/AcpiTables/AcpiSsdtRootPci.asl @@ -0,0 +1,219 @@ +/** @file + Differentiated System Description Table Fields (SSDT) + + Copyright (c) 2014-2015, ARM Ltd. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "ArmPlatform.h" + +/* + See ACPI 6.1 Section 6.2.13 + + There are two ways that _PRT can be used. ... + + In the first model, a PCI Link device is used to provide additional + configuration information such as whether the interrupt is Level or + Edge triggered, it is active High or Low, Shared or Exclusive, etc. + + In the second model, the PCI interrupts are hardwired to specific + interrupt inputs on the interrupt controller and are not + configurable. In this case, the Source field in _PRT does not + reference a device, but instead contains the value zero, and the + Source Index field contains the global system interrupt to which the + PCI interrupt is hardwired. + + We use the first model with link indirection to set the correct + interrupt type as PCI defaults (Level Triggered, Active Low) are not + compatible with GICv2. +*/ +#define LNK_DEVICE(Unique_Id, Link_Name, irq) \ + Device(Link_Name) { \ + Name(_HID, EISAID("PNP0C0F")) \ + Name(_UID, Unique_Id) \ + Name(_PRS, ResourceTemplate() { \ + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \ + }) \ + Method (_CRS, 0) { Return (_PRS) } \ + Method (_SRS, 1) { } \ + Method (_DIS) { } \ + } + +#define PRT_ENTRY(Address, Pin, Link) \ + Package (4) { \ + Address, /* uses the same format as _ADR */ \ + Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD). */ \ + Link, /* Interrupt allocated via Link device. */ \ + Zero /* global system interrupt number (no used) */ \ + } + +/* + See Reference [1] 6.1.1 + "High word–Device #, Low word–Function #. (for example, device 3, function 2 is + 0x00030002). To refer to all the functions on a device #, use a function number of FFFF)." +*/ +#define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY(0x0000FFFF, Pin, Link) + // Device 0 for Bridge. + + +DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM_REVISION) { + Scope(_SB) { + // + // PCI Root Complex + // + LNK_DEVICE(1, LNKA, 168) + LNK_DEVICE(2, LNKB, 169) + LNK_DEVICE(3, LNKC, 170) + LNK_DEVICE(4, LNKD, 171) + + Device(PCI0) + { + Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge + Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge + Name(_SEG, Zero) // PCI Segment Group number + Name(_BBN, Zero) // PCI Base Bus Number + Name(_CCA, 1) // Initially mark the PCI coherent (for JunoR1) + + // Root Complex 0 + Device (RP0) { + Name(_ADR, 0xF0000000) // Dev 0, Func 0 + } + + // PCI Routing Table + Name(_PRT, Package() { + ROOT_PRT_ENTRY(0, LNKA), // INTA + ROOT_PRT_ENTRY(1, LNKB), // INTB + ROOT_PRT_ENTRY(2, LNKC), // INTC + ROOT_PRT_ENTRY(3, LNKD), // INTD + }) + // Root complex resources + Method (_CRS, 0, Serialized) { + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, + MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256 // RangeLength - Number of Busses + ) + + DWordMemory ( // 32-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x50000000, // Min Base Address + 0x57FFFFFF, // Max Base Address + 0x00000000, // Translate + 0x08000000 // Length + ) + + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x4000000000, // Min Base Address + 0x40FFFFFFFF, // Max Base Address + 0x00000000, // Translate + 0x100000000 // Length + ) + + DWordIo ( // IO window + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x00000000, // Granularity + 0x00000000, // Min Base Address + 0x007fffff, // Max Base Address + 0x5f800000, // Translate + 0x00800000, // Length + ,,,TypeTranslation + ) + }) // Name(RBUF) + + Return (RBUF) + } // Method(_CRS) + + // + // OS Control Handoff + // + Name(SUPP, Zero) // PCI _OSC Support Field value + Name(CTRL, Zero) // PCI _OSC Control Field value + + /* + See [1] 6.2.10, [2] 4.5 + */ + Method(_OSC,4) { + // Check for proper UUID + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField(Arg3,0,CDW1) + CreateDWordField(Arg3,4,CDW2) + CreateDWordField(Arg3,8,CDW3) + + // Save Capabilities DWord2 & 3 + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // Only allow native hot plug control if OS supports: + // * ASPM + // * Clock PM + // * MSI/MSI-X + If(LNotEqual(And(SUPP, 0x16), 0x16)) { + And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits) + } + + // Always allow native PME, AER (no dependencies) + + // Never allow SHPC (no SHPC controller in this system) + And(CTRL,0x1D,CTRL) + +#if 0 + If(LNot(And(CDW1,1))) { // Query flag clear? + // Disable GPEs for features granted native control. + If(And(CTRL,0x01)) { // Hot plug control granted? + Store(0,HPCE) // clear the hot plug SCI enable bit + Store(1,HPCS) // clear the hot plug SCI status bit + } + If(And(CTRL,0x04)) { // PME control granted? + Store(0,PMCE) // clear the PME SCI enable bit + Store(1,PMCS) // clear the PME SCI status bit + } + If(And(CTRL,0x10)) { // OS restoring PCIe cap structure? + // Set status to not restore PCIe cap structure + // upon resume from S3 + Store(1,S3CR) + } + } +#endif + + If(LNotEqual(Arg1,One)) { // Unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // Update DWORD3 in the buffer + Store(CTRL,CDW3) + Return(Arg3) + } Else { + Or(CDW1,4,CDW1) // Unrecognized UUID + Return(Arg3) + } + } // End _OSC + } // PCI0 + } +} diff --git a/Platform/ARM/JunoPkg/AcpiTables/AcpiTables.inf b/Platform/ARM/JunoPkg/AcpiTables/AcpiTables.inf new file mode 100644 index 0000000000..e099c02f39 --- /dev/null +++ b/Platform/ARM/JunoPkg/AcpiTables/AcpiTables.inf @@ -0,0 +1,63 @@ +## @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2014-2016, ARM Ltd. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = JunoAcpiTables + FILE_GUID = a1dd808e-1e95-4399-abc0-653c82e8530c + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + +[Sources] + Dsdt.asl + Dbg2.aslc + Spcr.aslc + Fadt.aslc + Gtdt.aslc + Madt.aslc + AcpiSsdtRootPci.asl # Juno R1 specific + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec + ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdCoreCount + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase + + # + # PL011 UART Settings for Serial Port Console Redirection + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + gArmPlatformTokenSpaceGuid.PL011UartClkInHz + gArmPlatformTokenSpaceGuid.PL011UartInterrupt + + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase diff --git a/Platform/ARM/JunoPkg/AcpiTables/Dbg2.aslc b/Platform/ARM/JunoPkg/AcpiTables/Dbg2.aslc new file mode 100644 index 0000000000..be30cd0a65 --- /dev/null +++ b/Platform/ARM/JunoPkg/AcpiTables/Dbg2.aslc @@ -0,0 +1,92 @@ +/** @file +* DBG2 Table +* +* Copyright (c) 2012-2016, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include "ArmPlatform.h" +#include +#include +#include +#include +#include + +#pragma pack(1) + +#define DBG2_NUM_DEBUG_PORTS 1 +#define DBG2_NUMBER_OF_GENERIC_ADDRESS_REGISTERS 1 +#define DBG2_NAMESPACESTRING_FIELD_SIZE 8 +#define PL011_UART_LENGTH 0x1000 + +#define NAME_STR_UART1 {'C', 'O', 'M', '1', '\0', '\0', '\0', '\0'} + +typedef struct { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device; + EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister; + UINT32 AddressSize; + UINT8 NameSpaceString[DBG2_NAMESPACESTRING_FIELD_SIZE]; +} DBG2_DEBUG_DEVICE_INFORMATION; + +typedef struct { + EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Description; + DBG2_DEBUG_DEVICE_INFORMATION Dbg2DeviceInfo[DBG2_NUM_DEBUG_PORTS]; +} DBG2_TABLE; + + +#define DBG2_DEBUG_PORT_DDI(NumReg, SubType, UartBase, UartAddrLen, UartNameStr) { \ + { \ + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, /* UINT8 Revision */ \ + sizeof (DBG2_DEBUG_DEVICE_INFORMATION), /* UINT16 Length */ \ + NumReg, /* UINT8 NumberofGenericAddressRegisters */ \ + DBG2_NAMESPACESTRING_FIELD_SIZE, /* UINT16 NameSpaceStringLength */ \ + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString), /* UINT16 NameSpaceStringOffset */ \ + 0, /* UINT16 OemDataLength */ \ + 0, /* UINT16 OemDataOffset */ \ + EFI_ACPI_DBG2_PORT_TYPE_SERIAL, /* UINT16 Port Type */ \ + SubType, /* UINT16 Port Subtype */ \ + {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, /* UINT8 Reserved[2] */ \ + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister), /* UINT16 BaseAddressRegister Offset */ \ + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, AddressSize) /* UINT16 AddressSize Offset */ \ + }, \ + ARM_GAS32 (UartBase), /* EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister */ \ + UartAddrLen, /* UINT32 AddressSize */ \ + UartNameStr /* UINT8 NameSpaceString[MAX_DBG2_NAME_LEN] */ \ + } + + +STATIC DBG2_TABLE Dbg2 = { + { + ARM_ACPI_HEADER (EFI_ACPI_5_1_DEBUG_PORT_2_TABLE_SIGNATURE, + DBG2_TABLE, + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION), + OFFSET_OF (DBG2_TABLE, Dbg2DeviceInfo), + DBG2_NUM_DEBUG_PORTS /* UINT32 NumberDbgDeviceInfo */ + }, + { + /* + * Kernel Debug Port + */ + DBG2_DEBUG_PORT_DDI (DBG2_NUMBER_OF_GENERIC_ADDRESS_REGISTERS, + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART, + FixedPcdGet64 (PcdSerialDbgRegisterBase), + PL011_UART_LENGTH, + NAME_STR_UART1), + } +}; + +#pragma pack() + +// +// Reference the table being generated to prevent the optimizer from removing +// the data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Dbg2; diff --git a/Platform/ARM/JunoPkg/AcpiTables/Dsdt.asl b/Platform/ARM/JunoPkg/AcpiTables/Dsdt.asl new file mode 100644 index 0000000000..07e32bae21 --- /dev/null +++ b/Platform/ARM/JunoPkg/AcpiTables/Dsdt.asl @@ -0,0 +1,388 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014-2015, ARM Ltd. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "ArmPlatform.h" + +DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM_REVISION) { + Scope(_SB) { + // + // A57x2-A53x4 Processor declaration + // + Method (_OSC, 4, Serialized) { // _OSC: Operating System Capabilities + CreateDWordField (Arg3, 0x00, STS0) + CreateDWordField (Arg3, 0x04, CAP0) + If ((Arg0 == ToUUID ("0811b06e-4a27-44f9-8d60-3cbbc22e7b48") /* Platform-wide Capabilities */)) { + If (!(Arg1 == One)) { + STS0 &= ~0x1F + STS0 |= 0x0A + } Else { + If ((CAP0 & 0x100)) { + CAP0 &= ~0x100 /* No support for OS Initiated LPI */ + STS0 &= ~0x1F + STS0 |= 0x12 + } + } + } Else { + STS0 &= ~0x1F + STS0 |= 0x06 + } + Return (Arg3) + } + Device (CLU0) { // Cluster0 state + Name(_HID, "ACPI0010") + Name(_UID, 1) + Name (_LPI, Package() { + 0, // Version + 0, // Level Index + 1, // Count + Package() { // Power Gating state for Cluster + 2500, // Min residency (uS) + 1150, // Wake latency (uS) + 1, // Flags + 1, // Arch Context Flags + 100, //Residency Counter Frequency + 0, // No Parent State + 0x01000000, // Integer Entry method + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "CluPwrDn" + }, + }) + Name(PLPI, Package() { + 0, // Version + 1, // Level Index + 2, // Count + Package() { // WFI for CPU + 1, // Min residency (uS) + 1, // Wake latency (uS) + 1, // Flags + 0, // Arch Context Flags + 100, //Residency Counter Frequency + 0, // No parent state + ResourceTemplate () { + // Register Entry method + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0xFFFFFFFF, // Address + 0x03, // Access Size + ) + }, + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "WFI", + }, + Package() { // Power Gating state for CPU + 150, // Min residency (uS) + 350, // Wake latency (uS) + 1, // Flags + 1, // Arch Context Flags + 100, //Residency Counter Frequency + 1, // Parent node can be in any state + ResourceTemplate () { + // Register Entry method + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00010000, // Address + 0x03, // Access Size + ) + }, + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "CorePwrDn" + }, + }) + Device(CPU0) { // A57-0: Cluster 0, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 4) + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + } + Device(CPU1) { // A57-1: Cluster 0, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 5) + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + } + } + Device (CLU1) { // Cluster1 state + Name(_HID, "ACPI0010") + Name(_UID, 2) + Name (_LPI, Package() { + 0, // Version + 0, // Level Index + 1, // Count + Package() { // Power Gating state for Cluster + 2500, // Min residency (uS) + 1150, // Wake latency (uS) + 1, // Flags + 1, // Arch Context Flags + 100, //Residency Counter Frequency + 0, // No Parent State + 0x01000000, // Integer Entry method + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "CluPwrDn" + }, + }) + Name(PLPI, Package() { + 0, // Version + 1, // Level Index + 2, // Count + Package() { // WFI for CPU + 1, // Min residency (uS) + 1, // Wake latency (uS) + 1, // Flags + 0, // Arch Context Flags + 100, //Residency Counter Frequency + 0, // No parent state + ResourceTemplate () { + // Register Entry method + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0xFFFFFFFF, // Address + 0x03, // Access Size + ) + }, + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "WFI", + }, + Package() { // Power Gating state for CPU + 150, // Min residency (uS) + 350, // Wake latency (uS) + 1, // Flags + 1, // Arch Context Flags + 100, //Residency Counter Frequency + 1, // Parent node can be in any state + ResourceTemplate () { + // Register Entry method + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00010000, // Address + 0x03, // Access Size + ) + }, + ResourceTemplate() { // Null Residency Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + ResourceTemplate() { // Null Usage Counter + Register (SystemMemory, 0, 0, 0, 0) + }, + "CorePwrDn" + }, + }) + Device(CPU2) { // A53-0: Cluster 1, Cpu 0 + Name(_HID, "ACPI0007") + Name(_UID, 0) + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + } + Device(CPU3) { // A53-1: Cluster 1, Cpu 1 + Name(_HID, "ACPI0007") + Name(_UID, 1) + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + } + Device(CPU4) { // A53-2: Cluster 1, Cpu 2 + Name(_HID, "ACPI0007") + Name(_UID, 2) + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + } + Device(CPU5) { // A53-3: Cluster 1, Cpu 3 + Name(_HID, "ACPI0007") + Name(_UID, 3) + Method (_LPI, 0, NotSerialized) { + return(PLPI) + } + } + } + + // + // Keyboard and Mouse + // + Device(KMI0) { + Name(_HID, "ARMH0501") + Name(_CID, "PL050_KBD") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x1C060008, 0x4) + Memory32Fixed(ReadWrite, 0x1C060000, 0x4) + Memory32Fixed(ReadOnly, 0x1C060004, 0x4) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 197 } + }) + } + + // + // LAN9118 Ethernet + // + Device(ETH0) { + Name(_HID, "ARMH9118") + Name(_UID, Zero) + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x18000000, 0x1000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 192 } + }) + Name(_DSD, Package() { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package() { + Package(2) {"phy-mode", "mii"}, + Package(2) {"reg-io-width", 4 }, + Package(2) {"smsc,irq-active-high",1}, + Package(2) {"smsc,irq-push-pull",1} + } + }) // _DSD() + } + + // UART PL011 + Device(COM0) { + Name(_HID, "ARMH0011") + Name(_CID, "PL011") + Name(_UID, Zero) + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0x7FF80000, 0x1000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 115 } + }) + } + + // + // USB EHCI Host Controller + // + Device(USB0){ + Name(_HID, "ARMH0D20") + Name(_CID, "PNP0D20") + Name(_UID, 2) + Name(_CCA, 0) //EHCI on this platform is not coherent! + + Method(_CRS, 0x0, Serialized){ + Name(RBUF, ResourceTemplate(){ + Memory32Fixed(ReadWrite, 0x7FFC0000, 0x10000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {149} // INT ID=149 GIC IRQ ID=117 for Juno SoC USB EHCI Controller + }) + Return(RBUF) + } + + // + // Root Hub + // + Device(RHUB){ + Name(_ADR, 0x00000000) // Address of Root Hub should be 0 as per ACPI 5.0 spec + + // + // Ports connected to Root Hub + // + Device(HUB1){ + Name(_ADR, 0x00000001) + Name(_UPC, Package(){ + 0x00, // Port is NOT connectable + 0xFF, // Don't care + 0x00000000, // Reserved 0 must be zero + 0x00000000 // Reserved 1 must be zero + }) + + Device(PRT1){ + Name(_ADR, 0x00000001) + Name(_UPC, Package(){ + 0xFF, // Port is connectable + 0x00, // Port connector is A + 0x00000000, + 0x00000000 + }) + Name(_PLD, Package(){ + Buffer(0x10){ + 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }) + } // USB0_RHUB_HUB1_PRT1 + Device(PRT2){ + Name(_ADR, 0x00000002) + Name(_UPC, Package(){ + 0xFF, // Port is connectable + 0x00, // Port connector is A + 0x00000000, + 0x00000000 + }) + Name(_PLD, Package(){ + Buffer(0x10){ + 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }) + } // USB0_RHUB_HUB1_PRT2 + + Device(PRT3){ + Name(_ADR, 0x00000003) + Name(_UPC, Package(){ + 0xFF, // Port is connectable + 0x00, // Port connector is A + 0x00000000, + 0x00000000 + }) + Name(_PLD, Package(){ + Buffer(0x10){ + 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }) + } // USB0_RHUB_HUB1_PRT3 + + Device(PRT4){ + Name(_ADR, 0x00000004) + Name(_UPC, Package(){ + 0xFF, // Port is connectable + 0x00, // Port connector is A + 0x00000000, + 0x00000000 + }) + Name(_PLD, Package(){ + Buffer(0x10){ + 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }) + } // USB0_RHUB_HUB1_PRT4 + } // USB0_RHUB_HUB1 + } // USB0_RHUB + } // USB0 + } // Scope(_SB) +} diff --git a/Platform/ARM/JunoPkg/AcpiTables/Fadt.aslc b/Platform/ARM/JunoPkg/AcpiTables/Fadt.aslc new file mode 100644 index 0000000000..6b756292bd --- /dev/null +++ b/Platform/ARM/JunoPkg/AcpiTables/Fadt.aslc @@ -0,0 +1,99 @@ +/** @file +* Fixed ACPI Description Table (FADT) +* +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include "ArmPlatform.h" +#include +#include + +#ifdef ARM_JUNO_ACPI_5_0 +EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { + ARM_ACPI_HEADER ( + EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION + ), +#else +EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { + ARM_ACPI_HEADER ( + EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION + ), +#endif + 0, // UINT32 FirmwareCtrl + 0, // UINT32 Dsdt + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 + EFI_ACPI_5_0_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile + 0, // UINT16 SciInt + 0, // UINT32 SmiCmd + 0, // UINT8 AcpiEnable + 0, // UINT8 AcpiDisable + 0, // UINT8 S4BiosReq + 0, // UINT8 PstateCnt + 0, // UINT32 Pm1aEvtBlk + 0, // UINT32 Pm1bEvtBlk + 0, // UINT32 Pm1aCntBlk + 0, // UINT32 Pm1bCntBlk + 0, // UINT32 Pm2CntBlk + 0, // UINT32 PmTmrBlk + 0, // UINT32 Gpe0Blk + 0, // UINT32 Gpe1Blk + 0, // UINT8 Pm1EvtLen + 0, // UINT8 Pm1CntLen + 0, // UINT8 Pm2CntLen + 0, // UINT8 PmTmrLen + 0, // UINT8 Gpe0BlkLen + 0, // UINT8 Gpe1BlkLen + 0, // UINT8 Gpe1Base + 0, // UINT8 CstCnt + 0, // UINT16 PLvl2Lat + 0, // UINT16 PLvl3Lat + 0, // UINT16 FlushSize + 0, // UINT16 FlushStride + 0, // UINT8 DutyOffset + 0, // UINT8 DutyWidth + 0, // UINT8 DayAlrm + 0, // UINT8 MonAlrm + 0, // UINT8 Century + 0, // UINT16 IaPcBootArch + 0, // UINT8 Reserved1 + EFI_ACPI_5_0_HW_REDUCED_ACPI | EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg + 0, // UINT8 ResetValue +#ifdef ARM_JUNO_ACPI_5_0 + {EFI_ACPI_RESERVED_BYTE,EFI_ACPI_RESERVED_BYTE,EFI_ACPI_RESERVED_BYTE}, // UINT8 Reserved2[3] +#else + EFI_ACPI_5_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags + EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision +#endif + 0, // UINT64 XFirmwareCtrl + 0, // UINT64 XDsdt + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg + NULL_GAS // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Fadt; diff --git a/Platform/ARM/JunoPkg/AcpiTables/Gtdt.aslc b/Platform/ARM/JunoPkg/AcpiTables/Gtdt.aslc new file mode 100644 index 0000000000..5e83802d57 --- /dev/null +++ b/Platform/ARM/JunoPkg/AcpiTables/Gtdt.aslc @@ -0,0 +1,113 @@ +/** @file +* Generic Timer Description Table (GTDT) +* +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include "ArmPlatform.h" +#include +#include +#include + +#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT +#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0 +#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE +#define GTDT_GLOBAL_FLAGS_LEVEL 0 + +// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer +#ifdef SYSTEM_TIMER_BASE_ADDRESS + #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL) +#else + #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL) + #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF +#endif + +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTDT_TIMER_LEVEL_TRIGGERED 0 +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_HIGH 0 + +#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED) + +#ifdef ARM_JUNO_ACPI_5_0 + EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt = { + ARM_ACPI_HEADER( + EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE, + EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION + ), + SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress + GTDT_GLOBAL_FLAGS, // UINT32 GlobalFlags + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV + GTDT_GTIMER_FLAGS // UINT32 NonSecurePL2TimerFlags + }; +#else + #pragma pack (1) + + typedef struct { + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; +#if (JUNO_WATCHDOG_COUNT != 0) + EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[JUNO_WATCHDOG_COUNT]; +#endif + } GENERIC_TIMER_DESCRIPTION_TABLE; + + #pragma pack () + + GENERIC_TIMER_DESCRIPTION_TABLE Gtdt = { + { + ARM_ACPI_HEADER( + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + GENERIC_TIMER_DESCRIPTION_TABLE, + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION + ), + SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress + 0, // UINT32 Reserved + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags + 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress + JUNO_WATCHDOG_COUNT, // UINT32 PlatformTimerCount + sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset + }, +#if (JUNO_WATCHDOG_COUNT != 0) + { + EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( + FixedPcdGet64 (PcdGenericWatchdogRefreshBase), + FixedPcdGet64 (PcdGenericWatchdogControlBase), + 93, + 0), + EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( + FixedPcdGet64 (PcdGenericWatchdogRefreshBase), + FixedPcdGet64 (PcdGenericWatchdogControlBase), + 94, + EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER) + } +#endif + }; +#endif + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Gtdt; diff --git a/Platform/ARM/JunoPkg/AcpiTables/Madt.aslc b/Platform/ARM/JunoPkg/AcpiTables/Madt.aslc new file mode 100644 index 0000000000..dffa5d6196 --- /dev/null +++ b/Platform/ARM/JunoPkg/AcpiTables/Madt.aslc @@ -0,0 +1,131 @@ +/** @file +* Multiple APIC Description Table (MADT) +* +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include "ArmPlatform.h" +#include +#include +#include +#include + +// +// Multiple APIC Description Table +// +#ifdef ARM_JUNO_ACPI_5_0 + #pragma pack (1) + + typedef struct { + EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_5_0_GIC_STRUCTURE GicInterfaces[FixedPcdGet32 (PcdCoreCount)]; + EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + } EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + + #pragma pack () + + EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { + { + ARM_ACPI_HEADER ( + EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + ), + // + // MADT specific fields + // + 0, // LocalApicAddress + 0, // Flags + }, + { + // Format: EFI_ACPI_5_0_GIC_STRUCTURE_INIT(GicId, AcpiCpuId, Flags, PmuIrq, GicBase) + // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GIC Structure of + // ACPI v5.0). + // On Juno we can change the primary CPU changing the SCC register. It is not currently supported in the + // Trusted Firmware. When supported, we will need to code to dynamically change the ordering. + // For now we leave CPU2 (A53-0) at the first position. + // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses + // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table. + EFI_ACPI_5_0_GIC_STRUCTURE_INIT(2, 0, EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet64 (PcdGicInterruptInterfaceBase)), // A53-0 + EFI_ACPI_5_0_GIC_STRUCTURE_INIT(3, 1, EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet64 (PcdGicInterruptInterfaceBase)), // A53-1 + EFI_ACPI_5_0_GIC_STRUCTURE_INIT(4, 2, EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet64 (PcdGicInterruptInterfaceBase)), // A53-2 + EFI_ACPI_5_0_GIC_STRUCTURE_INIT(5, 3, EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet64 (PcdGicInterruptInterfaceBase)), // A53-3 + EFI_ACPI_5_0_GIC_STRUCTURE_INIT(0, 4, EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet64 (PcdGicInterruptInterfaceBase)), // A57-0 + EFI_ACPI_5_0_GIC_STRUCTURE_INIT(1, 5, EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet64 (PcdGicInterruptInterfaceBase)) // A57-1 + }, + EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0) + }; +#else + #pragma pack (1) + + typedef struct { + EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_5_1_GIC_STRUCTURE GicInterfaces[FixedPcdGet32 (PcdCoreCount)]; + EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_0_GIC_MSI_FRAME_STRUCTURE MsiFrame; + } MULTIPLE_APIC_DESCRIPTION_TABLE; + + #pragma pack () + + MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { + { + ARM_ACPI_HEADER ( + EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + ), + // + // MADT specific fields + // + 0, // LocalApicAddress + 0, // Flags + }, + { + // Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase, + // GsivId, GicRBase, Mpidr) + // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of + // ACPI v5.1). + // On Juno we can change the primary CPU changing the SCC register. It is not currently supported in the + // Trusted Firmware. When supported, we will need to code to dynamically change the ordering. + // For now we leave CPU2 (A53-0) at the first position. + // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses + // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table. + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-0 + 2, 0, GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-1 + 3, 1, GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-2 + 4, 2, GET_MPID(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-3 + 5, 3, GET_MPID(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-0 + 0, 4, GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */), + EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-1 + 1, 5, GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */), + }, + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0, 2), + // Format: EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(GicMsiFrameId, PhysicalBaseAddress, Flags, SPICount, SPIBase) + EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0, ARM_JUNO_GIV2M_MSI_BASE, 0, ARM_JUNO_GIV2M_MSI_SPI_COUNT, ARM_JUNO_GIV2M_MSI_SPI_BASE) + }; +#endif + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Madt; diff --git a/Platform/ARM/JunoPkg/AcpiTables/Spcr.aslc b/Platform/ARM/JunoPkg/AcpiTables/Spcr.aslc new file mode 100644 index 0000000000..8371669b7b --- /dev/null +++ b/Platform/ARM/JunoPkg/AcpiTables/Spcr.aslc @@ -0,0 +1,99 @@ +/** @file +* SPCR Table +* +* Copyright (c) 2014 - 2016, ARM Limited. All rights reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include "ArmPlatform.h" +#include +#include +#include +#include +#include + +/** + * References: + * Serial Port Console Redirection Table Specification Version 1.03 - August 10, 2015 + **/ + + +/// +/// SPCR Flow Control +/// +#define SPCR_FLOW_CONTROL_NONE 0 + + +STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = { + ARM_ACPI_HEADER (EFI_ACPI_5_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION), + // UINT8 InterfaceType; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART, + // UINT8 Reserved1[3]; + { + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE + }, + // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddress; + ARM_GAS32 (FixedPcdGet64 (PcdSerialRegisterBase)), + // UINT8 InterruptType; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, + // UINT8 Irq; + 0, // Not used on ARM + // UINT32 GlobalSystemInterrupt; + FixedPcdGet32 (PL011UartInterrupt), + // UINT8 BaudRate; +#if (FixedPcdGet64 (PcdUartDefaultBaudRate) == 9600) + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_9600, +#elif (FixedPcdGet64 (PcdUartDefaultBaudRate) == 19200) + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_19200, +#elif (FixedPcdGet64 (PcdUartDefaultBaudRate) == 57600) + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_57600, +#elif (FixedPcdGet64 (PcdUartDefaultBaudRate) == 115200) + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200, +#else +#error Unsupported SPCR Baud Rate +#endif + // UINT8 Parity; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, + // UINT8 StopBits; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, + // UINT8 FlowControl; + SPCR_FLOW_CONTROL_NONE, + // UINT8 TerminalType; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI, + // UINT8 Reserved2; + EFI_ACPI_RESERVED_BYTE, + // UINT16 PciDeviceId; + 0xFFFF, + // UINT16 PciVendorId; + 0xFFFF, + // UINT8 PciBusNumber; + 0x00, + // UINT8 PciDeviceNumber; + 0x00, + // UINT8 PciFunctionNumber; + 0x00, + // UINT32 PciFlags; + 0x00000000, + // UINT8 PciSegment; + 0x00, + // UINT32 Reserved3; + EFI_ACPI_RESERVED_DWORD +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Spcr; diff --git a/Platform/ARM/JunoPkg/ArmJuno.dsc b/Platform/ARM/JunoPkg/ArmJuno.dsc new file mode 100644 index 0000000000..72eab8b5be --- /dev/null +++ b/Platform/ARM/JunoPkg/ArmJuno.dsc @@ -0,0 +1,356 @@ +# +# Copyright (c) 2013-2015, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = ArmJuno + PLATFORM_GUID = ca0722fd-7d3d-45ea-948c-d62b2199807d + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010005 +!ifdef EDK2_OUT_DIR + OUTPUT_DIRECTORY = $(EDK2_OUT_DIR) +!else + OUTPUT_DIRECTORY = Build/ArmJuno +!endif + SUPPORTED_ARCHITECTURES = AARCH64|ARM + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/ARM/JunoPkg/ArmJuno.fdf + +# On RTSM, most peripherals are VExpress Motherboard peripherals +!include Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc + +[LibraryClasses.common] + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf + ArmPlatformLib|ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoLib.inf + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + + ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf + NorFlashPlatformLib|ArmPlatformPkg/ArmJunoPkg/Library/NorFlashJunoLib/NorFlashJunoLib.inf + + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf + + # USB Requirements + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + +[LibraryClasses.common.SEC] + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf + ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf + LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf + PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf + PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf + +[LibraryClasses.common.SEC, LibraryClasses.common.PEIM] + MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf + +[LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.DXE_DRIVER] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf + PciHostBridgeLib|Platform/ARM/JunoPkg/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.inf + PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf + +[BuildOptions] + *_*_*_PLATFORM_FLAGS = -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmJunoPkg/Include + GCC:*_*_ARM_PLATFORM_FLAGS = -march=armv8-a + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + +[PcdsFeatureFlag.common] + gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE + + ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. + # It could be set FALSE to save size. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE + +[PcdsFixedAtBuild.common] + gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Juno" + gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ArmJuno" + + # + # NV Storage PCDs. Use base of 0x08000000 for NOR0 + # + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0BFC0000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0BFD0000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0BFE0000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000 + + # System Memory (2GB - 16MB of Trusted DRAM at the top of the 32bit address space) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000 + + # Juno Dual-Cluster profile + gArmPlatformTokenSpaceGuid.PcdCoreCount|6 + gArmPlatformTokenSpaceGuid.PcdClusterCount|2 + + gArmTokenSpaceGuid.PcdVFPEnabled|1 + + # + # ARM PrimeCell + # + + ## PL011 - Serial Terminal + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x7FF80000 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0 + gArmPlatformTokenSpaceGuid.PL011UartClkInHz|7372800 + gArmPlatformTokenSpaceGuid.PL011UartInterrupt|115 + + ## PL011 - Serial Debug UART + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x7FF80000 + gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|7372800 + gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|115200 + + ## PL031 RealTimeClock + gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000 + + # LAN9118 Ethernet Driver + gEmbeddedTokenSpaceGuid.PcdLan9118DxeBaseAddress|0x18000000 + gEmbeddedTokenSpaceGuid.PcdLan9118DefaultMacAddress|0x1215161822242628 + gEmbeddedTokenSpaceGuid.PcdLan9118DefaultNegotiationTimeout|40000 + + # + # ARM General Interrupt Controller + # + gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C010000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C02F000 + + # + # PLDA PCI Root Complex + # + gArmTokenSpaceGuid.PcdPciBusMax|255 + gArmTokenSpaceGuid.PcdPciIoBase|0x0 + gArmTokenSpaceGuid.PcdPciIoSize|0x00800000 + gArmTokenSpaceGuid.PcdPciMmio32Base|0x50000000 + gArmTokenSpaceGuid.PcdPciMmio32Size|0x08000000 + gArmTokenSpaceGuid.PcdPciMmio64Base|0x4000000000 + gArmTokenSpaceGuid.PcdPciMmio64Size|0x100000000 + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x40000000 + gArmTokenSpaceGuid.PcdPciIoTranslation|0x5f800000 + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24 + + # List of Device Paths that support BootMonFs + gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)" + + # + # ARM OS Loader + # + gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from NOR Flash" + gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)/Image" + gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L"console=ttyAMA0,115200 earlycon=pl011,0x7ff80000 root=/dev/sda1 rootwait verbose debug" + + # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut) + gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenMsg(7D916D80-5BB1-458C-A48F-E25FDD51EF94)" + gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenMsg(7D916D80-5BB1-458C-A48F-E25FDD51EF94)" + + # + # ARM Architectural Timer Frequency + # + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|50000000 + gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000 + + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE + + # + # SMBIOS entry point version + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0300 + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev|0x0 + # + # ACPI Table Version + # + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 + +[PcdsPatchableInModule] + # Console Resolution (Full HD) + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1920 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|1080 + +[PcdsDynamicDefault.common] + # + # The size of a dynamic PCD of the (VOID*) type can not be increased at run + # time from its size at build time. Set the "PcdFdtDevicePaths" PCD to a 128 + # character "empty" string, to allow to be able to set FDT text device paths + # up to 128 characters long. + # + gEmbeddedTokenSpaceGuid.PcdFdtDevicePaths|L" " + + # Not all Juno platforms support PCI. This dynamic PCD disables or enable + # PCI support. + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|TRUE + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ +[Components.common] + # + # PEI Phase modules + # + ArmPlatformPkg/PrePi/PeiUniCore.inf + + # + # DXE + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf + } + + # + # Architectural Protocols + # + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + } + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + + # + # ACPI Support + # + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + Platform/ARM/JunoPkg/AcpiTables/AcpiTables.inf + + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf + ArmPkg/Drivers/TimerDxe/TimerDxe.inf + ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf + + # + # Semi-hosting filesystem + # + ArmPkg/Filesystem/SemihostFs/SemihostFs.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # Required by PCI + ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf + + # + # PCI Support + # + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + + # + # SATA Controller + # + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132Dxe.inf + + # + # NVMe boot devices + # + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + + # + # Networking stack + # + EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.inf +!if 0 + OptionRomPkg/MarvellYukonDxe/MarvellYukonDxe.inf +!endif + + # + # Usb Support + # + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf + + # + # Juno platform driver + # + ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf + + # + # SMBIOS/DMI + # + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + Platform/ARM/JunoPkg/SmbiosPlatformDxe/SmbiosPlatformDxe.inf + + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Application/UiApp/UiApp.inf { + + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf + } + + # + # FDT installation + # + EmbeddedPkg/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf { + + BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf + } + +[Components.AARCH64] + # + # EBC + # + MdeModulePkg/Universal/EbcDxe/EbcDxe.inf diff --git a/Platform/ARM/JunoPkg/ArmJuno.fdf b/Platform/ARM/JunoPkg/ArmJuno.fdf new file mode 100644 index 0000000000..e67c703d0e --- /dev/null +++ b/Platform/ARM/JunoPkg/ArmJuno.fdf @@ -0,0 +1,378 @@ +# +# Copyright (c) 2013-2015, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ + +[FD.BL33_AP_UEFI] +BaseAddress = 0xE0000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. +Size = 0x000F8000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +ErasePolarity = 1 + +# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x00001000 +NumBlocks = 0xF8 + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +################################################################################ + +0x00000000|0x000F8000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT + + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +[FV.FvMain] +BlockSize = 0x40 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 8 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = B73FE497-B92E-416e-8326-45AD0D270092 + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + + # + # ACPI Support + # + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + INF RuleOverride=ACPITABLE Platform/ARM/JunoPkg/AcpiTables/AcpiTables.inf + + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf + + # NOR Flash driver + INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf + + # Versatile Express FileSystem + INF ArmPlatformPkg/FileSystem/BootMonFs/BootMonFs.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatBinPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # Required by PCI + INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf + + # FV FileSystem + INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf + + # + # Usb Support + # + INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf + INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf + + # + # PCI Support + # + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + + # + # SATA Controller + # + INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + INF EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132Dxe.inf + + # + # NVMe boot devices + # + INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + + # + # Networking stack + # + INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf + INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf + INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf + INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf + INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf + INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf + INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf + INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf + INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf + INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf + INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf + INF EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.inf +!if 0 + INF OptionRomPkg/MarvellYukonDxe/MarvellYukonDxe.inf +!endif + + # + # UEFI applications + # + INF ShellPkg/Application/Shell/Shell.inf + + + # + # Juno platform driver + # + INF ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf + + # + # SMBIOS/DMI + # + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + INF Platform/ARM/JunoPkg/SmbiosPlatformDxe/SmbiosPlatformDxe.inf + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Application/UiApp/UiApp.inf + + # + # FDT installation + # + # The UEFI driver is at the end of the list of the driver to be dispatched + # after the device drivers (eg: Ethernet) to ensure we have support for them. + INF EmbeddedPkg/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf + +!if $(ARCH) == AARCH64 + # + # EBC + # + INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf +!endif + +[FV.FVMAIN_COMPACT] +FvAlignment = 8 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF ArmPlatformPkg/PrePi/PeiUniCore.inf + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } + } + + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ + + +############################################################################ +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section # +############################################################################ +# +#[Rule.Common.DXE_DRIVER] +# FILE DRIVER = $(NAMED_GUID) { +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex +# COMPRESS PI_STD { +# GUIDED { +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi +# UI STRING="$(MODULE_NAME)" Optional +# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) +# } +# } +# } +# +############################################################################ + +# +# These SEC rules are used for ArmPlatformPkg/PrePi module. +# ArmPlatformPkg/PrePi is declared as a SEC module to make GenFv patch the +# UEFI Firmware to jump to ArmPlatformPkg/PrePi entrypoint +# +[Rule.ARM.SEC] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { + TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.AARCH64.SEC] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED { + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +# A shim specific rule is required to ensure the alignment is 4K. +# Otherwise BaseTools pick up the AArch32 alignment (ie: 32) +[Rule.ARM.SEC.SHIM] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { + TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE = $(NAMED_GUID) FIXED { + TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING ="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM] + FILE PEIM = $(NAMED_GUID) FIXED { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE = $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION = $(NAMED_GUID) { + UI STRING ="$(MODULE_NAME)" Optional + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION = $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM = $(NAMED_GUID) { + RAW ACPI |.acpi + RAW ASL |.aml + } diff --git a/Platform/ARM/JunoPkg/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.c b/Platform/ARM/JunoPkg/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.c new file mode 100644 index 0000000000..5263a2985d --- /dev/null +++ b/Platform/ARM/JunoPkg/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.c @@ -0,0 +1,201 @@ +/** @file + PCI Host Bridge Library instance for ARM Juno + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "ArmPlatform.h" + +#pragma pack(1) +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; +#pragma pack () + +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath = { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), + (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) + } + }, + EISA_PNP_ID(0x0A03), // PCI + 0 + }, { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } +}; + +STATIC PCI_ROOT_BRIDGE mRootBridge = { + 0, // Segment + 0, // Supports + 0, // Attributes + TRUE, // DmaAbove4G + FALSE, // NoExtendedConfigSpace + FALSE, // ResourceAssigned + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, + { + // Bus + FixedPcdGet32 (PcdPciBusMin), + FixedPcdGet32 (PcdPciBusMax) + }, { + // Io + FixedPcdGet64 (PcdPciIoBase), + FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1 + }, { + // Mem + FixedPcdGet32 (PcdPciMmio32Base), + FixedPcdGet32 (PcdPciMmio32Base) + FixedPcdGet32 (PcdPciMmio32Size) - 1 + }, { + // MemAbove4G + FixedPcdGet64 (PcdPciMmio64Base), + FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) - 1 + }, { + // PMem + MAX_UINT64, + 0 + }, { + // PMemAbove4G + MAX_UINT64, + 0 + }, + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath +}; + +/** + Return all the root bridge instances in an array. + + @param Count Return the count of root bridge instances. + + @return All the root bridge instances in an array. + The array should be passed into PciHostBridgeFreeRootBridges() + when it's not used. +**/ +PCI_ROOT_BRIDGE * +EFIAPI +PciHostBridgeGetRootBridges ( + UINTN *Count + ) +{ + UINT32 JunoRevision; + + // + // Juno R0 has no working PCIe + // + GetJunoRevision (JunoRevision); + if (JunoRevision < JUNO_REVISION_R1) { + *Count = 0; + return NULL; + } + + *Count = 1; + + return &mRootBridge; +} + +/** + Free the root bridge instances array returned from PciHostBridgeGetRootBridges(). + + @param Bridges The root bridge instances array. + @param Count The count of the array. +**/ +VOID +EFIAPI +PciHostBridgeFreeRootBridges ( + PCI_ROOT_BRIDGE *Bridges, + UINTN Count + ) +{ +} + + +#ifndef MDEPKG_NDEBUG +STATIC CONST CHAR16 mPciHostBridgeLibAcpiAddressSpaceTypeStr[][4] = { + L"Mem", L"I/O", L"Bus" +}; +#endif + +/** + Inform the platform that the resource conflict happens. + + @param HostBridgeHandle Handle of the Host Bridge. + @param Configuration Pointer to PCI I/O and PCI memory resource + descriptors. The Configuration contains the resources + for all the root bridges. The resource for each root + bridge is terminated with END descriptor and an + additional END is appended indicating the end of the + entire resources. The resource descriptor field + values follow the description in + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + .SubmitResources(). +**/ +VOID +EFIAPI +PciHostBridgeResourceConflict ( + EFI_HANDLE HostBridgeHandle, + VOID *Configuration + ) +{ + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; + UINTN RootBridgeIndex; + DEBUG ((EFI_D_ERROR, "PciHostBridge: Resource conflict happens!\n")); + + RootBridgeIndex = 0; + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; + while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) { + DEBUG ((EFI_D_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++)); + for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) { + ASSERT (Descriptor->ResType < + ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr) + ); + DEBUG ((EFI_D_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n", + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType], + Descriptor->AddrLen, Descriptor->AddrRangeMax + )); + if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) { + DEBUG ((EFI_D_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n", + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag, + ((Descriptor->SpecificFlag & + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE + ) != 0) ? L" (Prefetchable)" : L"" + )); + } + } + // + // Skip the END descriptor for root bridge + // + ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR); + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)( + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1 + ); + } +} diff --git a/Platform/ARM/JunoPkg/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.inf b/Platform/ARM/JunoPkg/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.inf new file mode 100644 index 0000000000..68e22396cc --- /dev/null +++ b/Platform/ARM/JunoPkg/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.inf @@ -0,0 +1,77 @@ +## @file +# PCI Host Bridge Library instance for ARM Juno +# +# Copyright (c) 2017, Linaro Ltd. All rights reserved.
+# +# This program and the accompanying materials are licensed and made available +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +# IMPLIED. +# +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = JunoPciHostBridgeLib + FILE_GUID = d92c722c-87f9-4988-843e-dffd6bc8c5e3 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = PciHostBridgeLib|DXE_DRIVER + CONSTRUCTOR = HWPciRbInit + +# +# The following information is for reference only and not required by the build +# tools. +# +# VALID_ARCHITECTURES = AARCH64 ARM +# + +[Sources] + JunoPciHostBridgeLib.c + XPressRich3.c + +[Packages] + ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + BaseLib + DebugLib + DevicePathLib + IoLib + MemoryAllocationLib + UefiBootServicesTableLib + +[Pcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + +[FixedPcd] + gArmTokenSpaceGuid.PcdPciBusMin + gArmTokenSpaceGuid.PcdPciBusMax + gArmTokenSpaceGuid.PcdPciIoBase + gArmTokenSpaceGuid.PcdPciIoSize + gArmTokenSpaceGuid.PcdPciIoTranslation + gArmTokenSpaceGuid.PcdPciMmio32Base + gArmTokenSpaceGuid.PcdPciMmio32Size + gArmTokenSpaceGuid.PcdPciMmio32Translation + gArmTokenSpaceGuid.PcdPciMmio64Base + gArmTokenSpaceGuid.PcdPciMmio64Size + gArmTokenSpaceGuid.PcdPciMmio64Translation + + gArmJunoTokenSpaceGuid.PcdPcieControlBaseAddress + gArmJunoTokenSpaceGuid.PcdPcieRootPortBaseAddress + gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress + gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceSize + +[Protocols] + gEfiCpuIo2ProtocolGuid ## CONSUMES + +[Depex] + gEfiCpuIo2ProtocolGuid diff --git a/Platform/ARM/JunoPkg/Library/JunoPciHostBridgeLib/XPressRich3.c b/Platform/ARM/JunoPkg/Library/JunoPciHostBridgeLib/XPressRich3.c new file mode 100644 index 0000000000..a6d782949e --- /dev/null +++ b/Platform/ARM/JunoPkg/Library/JunoPciHostBridgeLib/XPressRich3.c @@ -0,0 +1,182 @@ +/** @file +* Initialize the XPress-RICH3 PCIe Root complex +* +* Copyright (c) 2011-2015, ARM Ltd. All rights reserved. +* Copyright (c) 2017, Linaro, Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include + +#include +#include +#include +#include + +#include + +#include "XPressRich3.h" +#include "ArmPlatform.h" + +#define PCI_BRIDGE_REVISION_ID 1 +#define CLASS_CODE_REGISTER(Class, SubClass, ProgIf) ((Class << 16) | (SubClass << 8) | ProgIf) +#define PLDA_BRIDGE_CCR CLASS_CODE_REGISTER(PCI_CLASS_BRIDGE, \ + PCI_CLASS_BRIDGE_P2P, \ + PCI_IF_BRIDGE_P2P) + +STATIC +VOID +SetTranslationAddressEntry ( + IN EFI_CPU_IO2_PROTOCOL *CpuIo, + IN UINTN Entry, + IN UINT64 SourceAddress, + IN UINT64 TranslatedAddress, + IN UINT64 TranslationSize, + IN UINT64 TranslationParameter + ) +{ + UINTN Log2Size = HighBitSet64 (TranslationSize); + + // Ensure the size is a power of two. Restriction form the AXI Translation logic + // Othwerwise we increase the translation size + if (TranslationSize != (1ULL << Log2Size)) { + DEBUG ((EFI_D_WARN, "PCI: The size 0x%lX of the region 0x%lx has been increased to " + "be a power of two for the AXI translation table.\n", + TranslationSize, SourceAddress)); + Log2Size++; + } + + PCIE_ROOTPORT_WRITE32 (Entry + PCI_ATR_SRC_ADDR_LOW_SIZE, + (UINT32)SourceAddress | ((Log2Size - 1) << 1) | 0x1); + PCIE_ROOTPORT_WRITE32 (Entry + PCI_ATR_SRC_ADDR_HI, SourceAddress >> 32); + + PCIE_ROOTPORT_WRITE32 (Entry + PCI_ATR_TRSL_ADDR_LOW, (UINT32)TranslatedAddress); + PCIE_ROOTPORT_WRITE32 (Entry + PCI_ATR_TRSL_ADDR_HI, TranslatedAddress >> 32); + + PCIE_ROOTPORT_WRITE32 (Entry + PCI_ATR_TRSL_PARAM, TranslationParameter); +} + +EFI_STATUS +HWPciRbInit ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + UINT32 Value; + UINT32 Index; + UINTN TranslationTable; + EFI_CPU_IO2_PROTOCOL *CpuIo; + EFI_STATUS Status; + + PCI_TRACE ("VExpressPciRbInit()"); + + PCI_TRACE ("PCIe Setting up Address Translation"); + + Status = gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL, + (VOID **)&CpuIo); + ASSERT_EFI_ERROR (Status); + + // The Juno PIO window is 8M, so we need full 32-bit PIO decoding. + PCIE_ROOTPORT_WRITE32 (PCIE_BAR_WIN, PCIE_BAR_WIN_SUPPORT_IO | PCIE_BAR_WIN_SUPPORT_IO32 | + PCIE_BAR_WIN_SUPPORT_MEM | PCIE_BAR_WIN_SUPPORT_MEM64); + + // Setup the PCI Configuration Registers + // Offset 0a: SubClass 04 PCI-PCI Bridge + // Offset 0b: BaseClass 06 Bridge Device + // The Class Code register is a 24 bit and can be configured by setting up the PCIE_PCI_IDS + // Refer [1] Chapter 13 + PCIE_ROOTPORT_WRITE32 (PCIE_PCI_IDS + PCIE_PCI_IDS_CLASSCODE_OFFSET, ((PLDA_BRIDGE_CCR << 8) | PCI_BRIDGE_REVISION_ID)); + + // + // PCIE Window 0 -> AXI4 Master 0 Address Translations + // + TranslationTable = VEXPRESS_ATR_PCIE_WIN0; + + // MSI Support + SetTranslationAddressEntry (CpuIo, TranslationTable, ARM_JUNO_GIV2M_MSI_BASE, ARM_JUNO_GIV2M_MSI_BASE, + ARM_JUNO_GIV2M_MSI_SZ, PCI_ATR_TRSLID_AXIDEVICE); + TranslationTable += PCI_ATR_ENTRY_SIZE; + + // System Memory Support + SetTranslationAddressEntry (CpuIo, TranslationTable, PcdGet64 (PcdSystemMemoryBase), PcdGet64 (PcdSystemMemoryBase), + PcdGet64 (PcdSystemMemorySize), PCI_ATR_TRSLID_AXIMEMORY); + TranslationTable += PCI_ATR_ENTRY_SIZE; + SetTranslationAddressEntry (CpuIo, TranslationTable, ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE, ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE, + ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ, PCI_ATR_TRSLID_AXIMEMORY); + + // + // AXI4 Slave 1 -> PCIE Window 0 Address Translations + // + TranslationTable = VEXPRESS_ATR_AXI4_SLV1; + + // PCI ECAM Support + SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_ECAM_BASE, PCI_ECAM_BASE, PCI_ECAM_SIZE, PCI_ATR_TRSLID_PCIE_CONF); + TranslationTable += PCI_ATR_ENTRY_SIZE; + + // PCI IO Support, the PIO space is translated from the arm MMIO PCI_IO_BASE address to the PIO base address of 0 + // AKA, PIO addresses used by endpoints are generally in the range of 0-64K. + SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_IO_BASE, 0, PCI_IO_SIZE, PCI_ATR_TRSLID_PCIE_IO); + TranslationTable += PCI_ATR_ENTRY_SIZE; + + // PCI MEM32 Support + SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_MEM32_BASE, PCI_MEM32_BASE, PCI_MEM32_SIZE, PCI_ATR_TRSLID_PCIE_MEMORY); + TranslationTable += PCI_ATR_ENTRY_SIZE; + + // PCI MEM64 Support + SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_MEM64_BASE, PCI_MEM64_BASE, PCI_MEM64_SIZE, PCI_ATR_TRSLID_PCIE_MEMORY); + + // Add credits + PCIE_ROOTPORT_WRITE32 (PCIE_VC_CRED, 0x00f0b818); + PCIE_ROOTPORT_WRITE32 (PCIE_VC_CRED + 4, 0x1); + + // Allow ECRC + PCIE_ROOTPORT_WRITE32 (PCIE_PEX_SPC2, 0x6006); + + // Reset controller + PCIE_CONTROL_WRITE32 (PCIE_CONTROL_RST_CTL, PCIE_CONTROL_RST_CTL_RCPHY_REL); + + // Wait for reset + for (Index = 0; Index < 1000; Index++) { + gBS->Stall (1000); + PCIE_CONTROL_READ32 (PCIE_CONTROL_RST_STS, Value); + if ((Value & PCIE_CONTROL_RST_STS_RCPHYPLL_OUT) == PCIE_CONTROL_RST_STS_RCPHYPLL_OUT) { + break; + } + } + + // Check for reset + if (!(Value & PCIE_CONTROL_RST_STS_RCPHYPLL_OUT)) { + DEBUG ((EFI_D_ERROR, "PCIe failed to come out of reset: %x.\n", Value)); + return EFI_NOT_READY; + } + + gBS->Stall (1000); + PCI_TRACE ("Checking link Status..."); + + // Wait for Link Up + for (Index = 0; Index < 1000; Index++) { + gBS->Stall (1000); + PCIE_ROOTPORT_READ32 (VEXPRESS_BASIC_STATUS, Value); + if (Value & LINK_UP) { + break; + } + } + + // Check for link up + if (!(Value & LINK_UP)) { + DEBUG ((EFI_D_ERROR, "PCIe link not up: %x.\n", Value)); + return EFI_NOT_READY; + } + + PCIE_ROOTPORT_WRITE32 (PCIE_IMASK_LOCAL, PCIE_INT_MSI | PCIE_INT_INTx); + + return EFI_SUCCESS; +} diff --git a/Platform/ARM/JunoPkg/Library/JunoPciHostBridgeLib/XPressRich3.h b/Platform/ARM/JunoPkg/Library/JunoPciHostBridgeLib/XPressRich3.h new file mode 100644 index 0000000000..07f52c210e --- /dev/null +++ b/Platform/ARM/JunoPkg/Library/JunoPciHostBridgeLib/XPressRich3.h @@ -0,0 +1,107 @@ +/** @file +* Header containing the Xpress-RICH3 PCIe Root Complex specific values +* +* Copyright (c) 2011-2015, ARM Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __XPRESS_RICH3_H__ +#define __XPRESS_RICH3_H__ + +#include +#include + +#define PCI_ECAM_BASE FixedPcdGet64 (PcdPciConfigurationSpaceBaseAddress) +#define PCI_ECAM_SIZE FixedPcdGet64 (PcdPciConfigurationSpaceSize) +#define PCI_IO_BASE FixedPcdGet64 (PcdPciIoTranslation) +#define PCI_IO_SIZE FixedPcdGet64 (PcdPciIoSize) +#define PCI_MEM32_BASE FixedPcdGet64 (PcdPciMmio32Base) +#define PCI_MEM32_SIZE FixedPcdGet64 (PcdPciMmio32Size) +#define PCI_MEM64_BASE FixedPcdGet64 (PcdPciMmio64Base) +#define PCI_MEM64_SIZE FixedPcdGet64 (PcdPciMmio64Size) + +#define PCI_TRACE(txt) DEBUG((EFI_D_VERBOSE, "ARM_PCI: " txt "\n")) + +#define PCIE_ROOTPORT_WRITE32(Add, Val) { UINT32 Value = (UINT32)(Val); CpuIo->Mem.Write (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieRootPortBaseAddress)+(Add)),1,&Value); } +#define PCIE_ROOTPORT_READ32(Add, Val) { CpuIo->Mem.Read (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieRootPortBaseAddress)+(Add)),1,&Val); } + +#define PCIE_CONTROL_WRITE32(Add, Val) { UINT32 Value = (UINT32)(Val); CpuIo->Mem.Write (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieControlBaseAddress)+(Add)),1,&Value); } +#define PCIE_CONTROL_READ32(Add, Val) { CpuIo->Mem.Read (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieControlBaseAddress)+(Add)),1,&Val); } + +/* + * Bridge Internal Registers + */ + +// PCIe Available Credit Settings +#define PCIE_VC_CRED 0x090 +// PCIe PCI Standard Configuration Identification Settings registers +#define PCIE_PCI_IDS 0x098 +#define PCIE_PCI_IDS_CLASSCODE_OFFSET 0x4 +// PCIe Specific 2 Capabilities Settings +#define PCIE_PEX_SPC2 0x0d8 +// PCIe Windows Settings register +#define PCIE_BAR_WIN 0x0FC +// Local Processor Interrupt Mask +#define PCIE_IMASK_LOCAL 0x180 + +#define PCIE_BAR_WIN_SUPPORT_IO BIT0 +#define PCIE_BAR_WIN_SUPPORT_IO32 BIT1 +#define PCIE_BAR_WIN_SUPPORT_MEM BIT2 +#define PCIE_BAR_WIN_SUPPORT_MEM64 BIT3 + +#define PCIE_INT_MSI BIT28 +#define PCIE_INT_A BIT24 +#define PCIE_INT_B BIT25 +#define PCIE_INT_C BIT26 +#define PCIE_INT_D BIT27 +#define PCIE_INT_INTx (PCIE_INT_A | PCIE_INT_B |\ + PCIE_INT_C | PCIE_INT_D) + +/* + * PCIe Control Registers + */ +#define PCIE_CONTROL_RST_CTL 0x1004 +#define PCIE_CONTROL_RST_STS 0x1008 + +/* + * PCI Express Address Translation registers + * All are offsets from PcdPcieControlBaseAddress + */ +#define VEXPRESS_ATR_PCIE_WIN0 0x600 +#define VEXPRESS_ATR_AXI4_SLV0 0x800 +#define VEXPRESS_ATR_AXI4_SLV1 0x820 + +#define PCI_ATR_ENTRY_SIZE 0x20 +#define PCI_ATR_SRC_ADDR_LOW_SIZE 0 +#define PCI_ATR_SRC_ADDR_HI 0x4 +#define PCI_ATR_TRSL_ADDR_LOW 0x8 +#define PCI_ATR_TRSL_ADDR_HI 0xc +#define PCI_ATR_TRSL_PARAM 0x10 + +#define PCI_ATR_TRSLID_AXIDEVICE 0x420004 +#define PCI_ATR_TRSLID_AXIMEMORY 0x4e0004 +#define PCI_ATR_TRSLID_PCIE_CONF 0x000001 +#define PCI_ATR_TRSLID_PCIE_IO 0x020000 +#define PCI_ATR_TRSLID_PCIE_MEMORY 0x000000 + +#define PCIE_CONTROL_RST_CTL_RC_REL (1 << 1) +#define PCIE_CONTROL_RST_CTL_PHY_REL (1 << 0) +#define PCIE_CONTROL_RST_CTL_RCPHY_REL (PCIE_CONTROL_RST_CTL_RC_REL | PCIE_CONTROL_RST_CTL_PHY_REL) + +#define PCIE_CONTROL_RST_STS_RC_ST (1 << 2) +#define PCIE_CONTROL_RST_STS_PHY_ST (1 << 1) +#define PCIE_CONTROL_RST_STS_PLL_ST (1 << 0) +#define PCIE_CONTROL_RST_STS_RCPHYPLL_OUT (PCIE_CONTROL_RST_STS_RC_ST | PCIE_CONTROL_RST_STS_PHY_ST | PCIE_CONTROL_RST_STS_PLL_ST) + +#define VEXPRESS_BASIC_STATUS 0x18 +#define LINK_UP 0xff + +#endif diff --git a/Platform/ARM/JunoPkg/SmbiosPlatformDxe/SmbiosPlatformDxe.c b/Platform/ARM/JunoPkg/SmbiosPlatformDxe/SmbiosPlatformDxe.c new file mode 100644 index 0000000000..fe5498e9fb --- /dev/null +++ b/Platform/ARM/JunoPkg/SmbiosPlatformDxe/SmbiosPlatformDxe.c @@ -0,0 +1,865 @@ +/** @file + This driver installs SMBIOS information for ARM Juno platforms + + Copyright (c) 2015, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TYPE0_STRINGS \ + "EFI Development Kit II / ARM LTD\0" /* Vendor */ \ + "EDK II\0" /* BiosVersion */ \ + __DATE__"\0" /* BiosReleaseDate */ + +#define TYPE1_STRINGS \ + "ARM LTD\0" /* Manufacturer */ \ + "ARM Juno Development Platform\0" /* Product Name */ \ + "None\0" /* Version */ \ + " \0" /* 20 character buffer */ + +#define TYPE2_STRINGS \ + "ARM LTD\0" /* Manufacturer */ \ + "ARM Juno Development Platform\0" /* Product Name */ \ + "R0\0" /* Version */ \ + "Serial Not Set\0" /* Serial */ \ + "Base of Chassis\0" /* board location */ \ + "R1\0" /* Version */ \ + "R2\0" /* Version */ + +#define TYPE3_STRINGS \ + "ARM LTD\0" /* Manufacturer */ \ + "None\0" /* Version */ \ + "Serial Not Set\0" /* Serial */ + +#define TYPE4_STRINGS \ + "BGA-1156\0" /* socket type */ \ + "ARM LTD\0" /* manufactuer */ \ + "Cortex-A57\0" /* processor 1 description */ \ + "Cortex-A53\0" /* processor 2 description */ \ + "Cortex-A72\0" /* processor 2 description */ \ + "0xd03\0" /* A53 part number */ \ + "0xd07\0" /* A57 part number */ \ + "0xd08\0" /* A72 part number */ + +#define TYPE7_STRINGS \ + "L1 Instruction\0" /* L1I */ \ + "L1 Data\0" /* L1D */ \ + "L2\0" /* L2 */ + +#define TYPE9_STRINGS \ + "PCIE_SLOT0\0" /* Slot0 */ \ + "PCIE_SLOT1\0" /* Slot1 */ \ + "PCIE_SLOT2\0" /* Slot2 */ \ + "PCIE_SLOT3\0" /* Slot3 */ + +#define TYPE16_STRINGS \ + "\0" /* nothing */ + +#define TYPE17_STRINGS \ + "RIGHT SIDE\0" /* location */ \ + "BANK 0\0" /* bank description */ + +#define TYPE19_STRINGS \ + "\0" /* nothing */ + +#define TYPE32_STRINGS \ + "\0" /* nothing */ + + +// +// Type definition and contents of the default SMBIOS table. +// This table covers only the minimum structures required by +// the SMBIOS specification (section 6.2, version 3.0) +// +#pragma pack(1) +typedef struct { + SMBIOS_TABLE_TYPE0 Base; + INT8 Strings[sizeof(TYPE0_STRINGS)]; +} ARM_TYPE0; + +typedef struct { + SMBIOS_TABLE_TYPE1 Base; + UINT8 Strings[sizeof(TYPE1_STRINGS)]; +} ARM_TYPE1; + +typedef struct { + SMBIOS_TABLE_TYPE2 Base; + UINT8 Strings[sizeof(TYPE2_STRINGS)]; +} ARM_TYPE2; + +typedef struct { + SMBIOS_TABLE_TYPE3 Base; + UINT8 Strings[sizeof(TYPE3_STRINGS)]; +} ARM_TYPE3; + +typedef struct { + SMBIOS_TABLE_TYPE4 Base; + UINT8 Strings[sizeof(TYPE4_STRINGS)]; +} ARM_TYPE4; + +typedef struct { + SMBIOS_TABLE_TYPE7 Base; + UINT8 Strings[sizeof(TYPE7_STRINGS)]; +} ARM_TYPE7; + +typedef struct { + SMBIOS_TABLE_TYPE9 Base; + UINT8 Strings[sizeof(TYPE9_STRINGS)]; +} ARM_TYPE9; + +typedef struct { + SMBIOS_TABLE_TYPE16 Base; + UINT8 Strings[sizeof(TYPE16_STRINGS)]; +} ARM_TYPE16; + +typedef struct { + SMBIOS_TABLE_TYPE17 Base; + UINT8 Strings[sizeof(TYPE17_STRINGS)]; +} ARM_TYPE17; + +typedef struct { + SMBIOS_TABLE_TYPE19 Base; + UINT8 Strings[sizeof(TYPE19_STRINGS)]; +} ARM_TYPE19; + +typedef struct { + SMBIOS_TABLE_TYPE32 Base; + UINT8 Strings[sizeof(TYPE32_STRINGS)]; +} ARM_TYPE32; + +// SMBIOS tables often reference each other using +// fixed constants, define a list of these constants +// for our hardcoded tables +enum SMBIOS_REFRENCE_HANDLES { + SMBIOS_HANDLE_A57_L1I = 0x1000, + SMBIOS_HANDLE_A57_L1D, + SMBIOS_HANDLE_A57_L2, + SMBIOS_HANDLE_A53_L1I, + SMBIOS_HANDLE_A53_L1D, + SMBIOS_HANDLE_A53_L2, + SMBIOS_HANDLE_MOTHERBOARD, + SMBIOS_HANDLE_CHASSIS, + SMBIOS_HANDLE_A72_CLUSTER, + SMBIOS_HANDLE_A57_CLUSTER, + SMBIOS_HANDLE_A53_CLUSTER, + SMBIOS_HANDLE_MEMORY, + SMBIOS_HANDLE_DIMM +}; + +#define SERIAL_LEN 10 //this must be less than the buffer len allocated in the type1 structure + +#pragma pack() + +// BIOS information (section 7.1) +STATIC ARM_TYPE0 mArmDefaultType0 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_BIOS_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE0), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED, + }, + 1, // SMBIOS_TABLE_STRING Vendor + 2, // SMBIOS_TABLE_STRING BiosVersion + 0xE800,// UINT16 BiosSegment + 3, // SMBIOS_TABLE_STRING BiosReleaseDate + 0, // UINT8 BiosSize + { + 0,0,0,0,0,0, + 1, //PCI supported + 0, + 1, //PNP supported + 0, + 1, //BIOS upgradable + 0, 0, 0, + 1, //Boot from CD + 1, //selectable boot + }, // MISC_BIOS_CHARACTERISTICS BiosCharacteristics + { // BIOSCharacteristicsExtensionBytes[2] + 0x3, + 0xC, + }, + 0, // UINT8 SystemBiosMajorRelease + 0, // UINT8 SystemBiosMinorRelease + 0xFF, // UINT8 EmbeddedControllerFirmwareMajorRelease + 0xFF // UINT8 EmbeddedControllerFirmwareMinorRelease + }, + // Text strings (unformatted area) + TYPE0_STRINGS +}; + +// System information (section 7.2) +STATIC CONST ARM_TYPE1 mArmDefaultType1 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_INFORMATION, + sizeof(SMBIOS_TABLE_TYPE1), + SMBIOS_HANDLE_PI_RESERVED, + }, + 1, //Manufacturer + 2, //Product Name + 3, //Version + 4, //Serial + { 0x8a95d198, 0x7f46, 0x11e5, { 0xbf,0x8b,0x08,0x00,0x27,0x04,0xd4,0x8e }}, //UUID + 6, //Wakeup type + 0, //SKU + 0, //Family + }, + // Text strings (unformatted) + TYPE1_STRINGS +}; + +// Baseboard (section 7.3) +STATIC ARM_TYPE2 mArmDefaultType2 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE2), // UINT8 Length + SMBIOS_HANDLE_MOTHERBOARD, + }, + 1, //Manufacturer + 2, //Product Name + 3, //Version + 4, //Serial + 0, //Asset tag + {1}, //motherboard, not replaceable + 5, //location of board + SMBIOS_HANDLE_CHASSIS, + BaseBoardTypeMotherBoard, + 1, + {SMBIOS_HANDLE_A53_CLUSTER}, //,SMBIOS_HANDLE_A53_CLUSTER,SMBIOS_HANDLE_MEMORY}, + }, + TYPE2_STRINGS +}; + +// Enclosure +STATIC CONST ARM_TYPE3 mArmDefaultType3 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE3), // UINT8 Length + SMBIOS_HANDLE_CHASSIS, + }, + 1, //Manufacturer + 4, //enclosure type (low profile desktop) + 2, //version + 3, //serial + 0, //asset tag + ChassisStateUnknown, //boot chassis state + ChassisStateSafe, //power supply state + ChassisStateSafe, //thermal state + ChassisSecurityStatusNone, //security state + {0,0,0,0,}, //OEM defined + 1, //1U height + 1, //number of power cords + 0, //no contained elements + }, + TYPE3_STRINGS +}; + +// Processor +STATIC CONST ARM_TYPE4 mArmDefaultType4_a72 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE4), // UINT8 Length + SMBIOS_HANDLE_A72_CLUSTER, + }, + 1, //socket type + 3, //processor type CPU + ProcessorFamilyIndicatorFamily2, //processor family, acquire from field2 + 2, //manufactuer + {{0,},{0.}}, //processor id + 5, //version + {0,0,0,0,0,1}, //voltage + 0, //external clock + 1200, //max speed + 1200, //current speed + 0x41, //status + ProcessorUpgradeOther, + SMBIOS_HANDLE_A57_L1I, //l1 cache handle + SMBIOS_HANDLE_A57_L2, //l2 cache handle + 0xFFFF, //l3 cache handle + 0, //serial not set + 0, //asset not set + 8, //part number + 2, //core count in socket + 2, //enabled core count in socket + 0, //threads per socket + 0xEC, // processor characteristics + ProcessorFamilyARM, //ARM core + }, + TYPE4_STRINGS +}; + +STATIC CONST ARM_TYPE4 mArmDefaultType4_a57 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE4), // UINT8 Length + SMBIOS_HANDLE_A57_CLUSTER, + }, + 1, //socket type + 3, //processor type CPU + ProcessorFamilyIndicatorFamily2, //processor family, acquire from field2 + 2, //manufactuer + {{0,},{0.}}, //processor id + 3, //version + {0,0,0,0,0,1}, //voltage + 0, //external clock + 1200, //max speed + 1200, //current speed + 0x41, //status + ProcessorUpgradeOther, + SMBIOS_HANDLE_A57_L1I, //l1 cache handle + SMBIOS_HANDLE_A57_L2, //l2 cache handle + 0xFFFF, //l3 cache handle + 0, //serial not set + 0, //asset not set + 7, //part number + 2, //core count in socket + 2, //enabled core count in socket + 0, //threads per socket + 0xEC, // processor characteristics + ProcessorFamilyARM, //ARM core + }, + TYPE4_STRINGS +}; + +STATIC CONST ARM_TYPE4 mArmDefaultType4_a53 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE4), // UINT8 Length + SMBIOS_HANDLE_A53_CLUSTER, + }, + 1, //socket type + 3, //processor type CPU + ProcessorFamilyIndicatorFamily2, //processor family, acquire from field2 + 2, //manufactuer + {{0,},{0.}}, //processor id + 4, //version + {0,0,0,0,0,1}, //voltage + 0, //external clock + 650, //max speed + 650, //current speed + 0x41, //status + ProcessorUpgradeOther, + SMBIOS_HANDLE_A53_L1I, //l1 cache handle + SMBIOS_HANDLE_A53_L2, //l2 cache handle + 0xFFFF, //l3 cache handle + 0, //serial not set + 0, //asset not set + 6, //part number + 4, //core count in socket + 4, //enabled core count in socket + 0, //threads per socket + 0xEC, // processor characteristics + ProcessorFamilyARM, //ARM core + }, + TYPE4_STRINGS +}; + +// Cache +STATIC CONST ARM_TYPE7 mArmDefaultType7_a57_l1i = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length + SMBIOS_HANDLE_A57_L1I, + }, + 1, + 0x380, //L1 enabled, unknown WB + 48, //48k i cache max + 48, //48k installed + {0,1}, //SRAM type + {0,1}, //SRAM type + 0, //unkown speed + CacheErrorParity, //parity checking + CacheTypeInstruction, //instruction cache + CacheAssociativityOther, //three way + }, + TYPE7_STRINGS +}; + +STATIC CONST ARM_TYPE7 mArmDefaultType7_a53_l1i = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length + SMBIOS_HANDLE_A53_L1I, + }, + 1, + 0x380, //L1 enabled, unknown WB + 32, //32k i cache max + 32, //32k installed + {0,1}, //SRAM type + {0,1}, //SRAM type + 0, //unkown speed + CacheErrorParity, //parity checking + CacheTypeInstruction, //instruction cache + CacheAssociativity2Way, //two way + }, + TYPE7_STRINGS +}; + +STATIC CONST ARM_TYPE7 mArmDefaultType7_a57_l1d = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length + SMBIOS_HANDLE_A57_L1D, + }, + 2, + 0x180, //L1 enabled, WB + 32, //32k d cache max + 32, //32k installed + {0,1}, //SRAM type + {0,1}, //SRAM type + 0, //unkown speed + CacheErrorSingleBit, //ECC checking + CacheTypeData, //instruction cache + CacheAssociativity2Way, //two way associative + }, + TYPE7_STRINGS +}; + +STATIC CONST ARM_TYPE7 mArmDefaultType7_a53_l1d = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length + SMBIOS_HANDLE_A53_L1D, + }, + 2, + 0x180, //L1 enabled, WB + 32, //32k d cache max + 32, //32k installed + {0,1}, //SRAM type + {0,1}, //SRAM type + 0, //unkown speed + CacheErrorSingleBit, //ECC checking + CacheTypeData, //instruction cache + CacheAssociativity4Way, //four way associative + }, + TYPE7_STRINGS +}; + +STATIC CONST ARM_TYPE7 mArmDefaultType7_a57_l2 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length + SMBIOS_HANDLE_A57_L2, + }, + 3, + 0x181, //L2 enabled, WB + 2048, //2M d cache max + 2048, //2M installed + {0,1}, //SRAM type + {0,1}, //SRAM type + 0, //unkown speed + CacheErrorSingleBit, //ECC checking + CacheTypeUnified, //instruction cache + CacheAssociativity16Way, //16 way associative + }, + TYPE7_STRINGS +}; + +STATIC CONST ARM_TYPE7 mArmDefaultType7_a53_l2 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_CACHE_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE7), // UINT8 Length + SMBIOS_HANDLE_A53_L2, + }, + 3, + 0x181, //L2 enabled, WB + 1024, //1M D cache max + 1024, //1M installed + {0,1}, //SRAM type + {0,1}, //SRAM type + 0, //unkown speed + CacheErrorSingleBit, //ECC checking + CacheTypeUnified, //instruction cache + CacheAssociativity16Way, //16 way associative + }, + TYPE7_STRINGS +}; + +// Slots +STATIC CONST ARM_TYPE9 mArmDefaultType9_0 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED, + }, + 1, //slot 0 + SlotTypePciExpressGen2X4, + SlotDataBusWidth1X, + SlotUsageUnknown, + SlotLengthShort, + 0, + {1}, //unknown + {1,0,1}, //PME and SMBUS + 0, + 2, + 1, + }, + TYPE9_STRINGS +}; + +STATIC CONST ARM_TYPE9 mArmDefaultType9_1 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED, + }, + 1, //slot 0 + SlotTypePciExpressGen2X4, + SlotDataBusWidth1X, + SlotUsageUnknown, + SlotLengthShort, + 0, + {1}, + {1,0,1}, //PME and SMBUS + 0, + 2, + 2, + }, + TYPE9_STRINGS +}; + +STATIC CONST ARM_TYPE9 mArmDefaultType9_2 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED, + }, + 1, //slot 0 + SlotTypePciExpressGen2X8, + SlotDataBusWidth4X, + SlotUsageUnknown, + SlotLengthShort, + 0, + {1}, + {1,0,1}, //PME and SMBUS + 0, + 2, + 3, + }, + TYPE9_STRINGS +}; + +STATIC CONST ARM_TYPE9 mArmDefaultType9_3 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED, + }, + 1, //slot 0 + SlotTypePciExpressGen2X16, + SlotDataBusWidth4X, + SlotUsageUnknown, + SlotLengthShort, + 0, + {1}, + {1,0,1}, //PME and SMBUS + 0, + 2, + 0xc, + }, + TYPE9_STRINGS +}; + +// Memory array +STATIC CONST ARM_TYPE16 mArmDefaultType16 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE16), // UINT8 Length + SMBIOS_HANDLE_MEMORY, + }, + MemoryArrayLocationSystemBoard, //on motherboard + MemoryArrayUseSystemMemory, //system RAM + MemoryErrorCorrectionNone, //Juno doesn't have ECC RAM + 0x800000, //8GB + 0xFFFE, //No error information structure + 0x1, //soldered memory + }, + TYPE16_STRINGS +}; + +// Memory device +STATIC CONST ARM_TYPE17 mArmDefaultType17 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_MEMORY_DEVICE, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE17), // UINT8 Length + SMBIOS_HANDLE_DIMM, + }, + SMBIOS_HANDLE_MEMORY, //array to which this module belongs + 0xFFFE, //no errors + 64, //single DIMM, no ECC is 64bits (for ecc this would be 72) + 64, //data width of this device (64-bits) + 0x2000, //8GB + 0x0B, //row of chips + 0, //not part of a set + 1, //right side of board + 2, //bank 0 +// MemoryTypeLpddr3, //LP DDR3, isn't defined yet + MemoryTypeDdr3, //LP DDR3 + {0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, //unbuffered + 1600, //1600Mhz DDR + 0, //varies between diffrent production runs + 0, //serial + 0, //asset tag + 0, //part number + 0, //rank + }, + TYPE17_STRINGS +}; + +// Memory array mapped address, this structure +// is overridden by InstallMemoryStructure +STATIC CONST ARM_TYPE19 mArmDefaultType19 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE19), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED, + }, + 0xFFFFFFFF, //invalid, look at extended addr field + 0xFFFFFFFF, + SMBIOS_HANDLE_DIMM, //handle + 1, + 0x080000000, //starting addr of first 2GB + 0x100000000, //ending addr of first 2GB + }, + TYPE19_STRINGS +}; + +// System boot info +STATIC CONST ARM_TYPE32 mArmDefaultType32 = { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, // UINT8 Type + sizeof (SMBIOS_TABLE_TYPE32), // UINT8 Length + SMBIOS_HANDLE_PI_RESERVED, + }, + {0,0,0,0,0,0}, //reserved + BootInformationStatusNoError, + }, + TYPE32_STRINGS +}; + +STATIC CONST VOID *DefaultCommonTables[]= +{ + &mArmDefaultType0, + &mArmDefaultType1, + &mArmDefaultType2, + &mArmDefaultType3, + &mArmDefaultType7_a53_l1i, + &mArmDefaultType7_a53_l1d, + &mArmDefaultType7_a53_l2, + &mArmDefaultType4_a53, + &mArmDefaultType9_0, + &mArmDefaultType9_1, + &mArmDefaultType9_2, + &mArmDefaultType9_3, + &mArmDefaultType16, + &mArmDefaultType17, +// &mArmDefaultType19, //memory range type 19 dynamically generated + &mArmDefaultType32, + NULL +}; + +STATIC CONST VOID *DefaultTablesR0R1[]= +{ + &mArmDefaultType7_a57_l1i, + &mArmDefaultType7_a57_l1d, + &mArmDefaultType7_a57_l2, + &mArmDefaultType4_a57, + NULL +}; + +STATIC CONST VOID *DefaultTablesR2[]= +{ + &mArmDefaultType7_a57_l1i, // Cache layout is the same on the A72 vs A57 + &mArmDefaultType7_a57_l1d, + &mArmDefaultType7_a57_l2, + &mArmDefaultType4_a72, + NULL +}; + + +/** + Installs a memory descriptor (type19) for the given address range + + @param Smbios SMBIOS protocol + +**/ +EFI_STATUS +InstallMemoryStructure ( + IN EFI_SMBIOS_PROTOCOL *Smbios, + IN UINT64 StartingAddress, + IN UINT64 RegionLength + ) +{ + EFI_SMBIOS_HANDLE SmbiosHandle; + ARM_TYPE19 MemoryDescriptor; + EFI_STATUS Status = EFI_SUCCESS; + + CopyMem( &MemoryDescriptor, &mArmDefaultType19, sizeof(ARM_TYPE19)); + + MemoryDescriptor.Base.ExtendedStartingAddress = StartingAddress; + MemoryDescriptor.Base.ExtendedEndingAddress = StartingAddress+RegionLength; + SmbiosHandle = MemoryDescriptor.Base.Hdr.Handle; + + Status = Smbios->Add ( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER*) &MemoryDescriptor + ); + return Status; +} + +/** + Install a whole table worth of structructures + + @parm +**/ +EFI_STATUS +InstallStructures ( + IN EFI_SMBIOS_PROTOCOL *Smbios, + IN CONST VOID *DefaultTables[] + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + EFI_SMBIOS_HANDLE SmbiosHandle; + + int TableEntry; + for ( TableEntry=0; DefaultTables[TableEntry] != NULL; TableEntry++) + { + SmbiosHandle = ((EFI_SMBIOS_TABLE_HEADER*)DefaultTables[TableEntry])->Handle; + Status = Smbios->Add ( + Smbios, + NULL, + &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER*) DefaultTables[TableEntry] + ); + if (EFI_ERROR(Status)) + break; + } + return Status; +} + + +/** + Install all structures from the DefaultTables structure + + @param Smbios SMBIOS protocol + +**/ +EFI_STATUS +InstallAllStructures ( + IN EFI_SMBIOS_PROTOCOL *Smbios + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINT32 JunoRevision; + VOID *ExtraTables = DefaultTablesR0R1; + + GetJunoRevision(JunoRevision); + + // Fixup some table values + mArmDefaultType0.Base.SystemBiosMajorRelease = (PcdGet32 ( PcdFirmwareRevision ) >> 16) & 0xFF; + mArmDefaultType0.Base.SystemBiosMinorRelease = PcdGet32 ( PcdFirmwareRevision ) & 0xFF; + if ( JunoRevision == JUNO_REVISION_R1 ) + { + mArmDefaultType2.Base.Version = 6; + } + else if ( JunoRevision == JUNO_REVISION_R2 ) + { + mArmDefaultType2.Base.Version = 7; + ExtraTables=DefaultTablesR2; + } + + // + // Add all Juno table entries + // + Status=InstallStructures (Smbios,DefaultCommonTables); + ASSERT_EFI_ERROR (Status); + + Status=InstallStructures (Smbios,ExtraTables); + ASSERT_EFI_ERROR (Status); + + // Generate memory descriptors for the two memory ranges we know about + Status = InstallMemoryStructure ( Smbios, PcdGet64 (PcdSystemMemoryBase), PcdGet64 (PcdSystemMemorySize)); + ASSERT_EFI_ERROR (Status); + Status = InstallMemoryStructure ( Smbios, ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE, ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ); + ASSERT_EFI_ERROR (Status); + + return Status; +} + +/** + Installs SMBIOS information for ARM platforms + + @param ImageHandle Module's image handle + @param SystemTable Pointer of EFI_SYSTEM_TABLE + + @retval EFI_SUCCESS Smbios data successfully installed + @retval Other Smbios data was not installed + +**/ +EFI_STATUS +EFIAPI +SmbiosTablePublishEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_SMBIOS_PROTOCOL *Smbios; + + // + // Find the SMBIOS protocol + // + Status = gBS->LocateProtocol ( + &gEfiSmbiosProtocolGuid, + NULL, + (VOID**)&Smbios + ); + if (EFI_ERROR (Status)) { + return Status; + } + + Status = InstallAllStructures (Smbios); + + return Status; +} diff --git a/Platform/ARM/JunoPkg/SmbiosPlatformDxe/SmbiosPlatformDxe.inf b/Platform/ARM/JunoPkg/SmbiosPlatformDxe/SmbiosPlatformDxe.inf new file mode 100644 index 0000000000..457e1ff552 --- /dev/null +++ b/Platform/ARM/JunoPkg/SmbiosPlatformDxe/SmbiosPlatformDxe.inf @@ -0,0 +1,68 @@ +## @file +# This driver installs SMBIOS information for ArmJuno +# +# Copyright (c) 2011, Bei Guan +# Copyright (c) 2011, Intel Corporation. All rights reserved. +# Copyright (c) 2015, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SmbiosPlatformDxe + FILE_GUID = 4110465d-5ff3-4f4b-b580-24ed0d06747a + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = SmbiosTablePublishEntry + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + SmbiosPlatformDxe.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + ArmLib + BaseMemoryLib + BaseLib + DebugLib + HobLib + IoLib + MemoryAllocationLib + PcdLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Guids] + gEfiGlobalVariableGuid + +[FixedPcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision + +[Protocols] + gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED + +[Guids] + +[Depex] + gEfiSmbiosProtocolGuid -- cgit v1.2.3