From 3f843b9795039ed65a655c5f6391fe58cade8644 Mon Sep 17 00:00:00 2001 From: Guo Mang Date: Mon, 23 Jan 2017 13:31:17 +0800 Subject: Fix MRC parameters restore failure issue Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang --- .../Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c | 19 ++++++++++++++++--- .../LeafHill/BoardInitPreMem/BoardInitPreMem.inf | 3 ++- .../MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c | 19 ++++++++++++++++--- .../MinnowBoard3/BoardInitPreMem/BoardInitPreMem.inf | 3 ++- 4 files changed, 36 insertions(+), 8 deletions(-) (limited to 'Platform/BroxtonPlatformPkg/Board') diff --git a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c index 0a932015e0..fe8ece0b88 100644 --- a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c +++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c @@ -1,7 +1,7 @@ /** @file This file does Multiplatform initialization. - Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License @@ -14,6 +14,7 @@ **/ #include "BoardInitMiscs.h" +#include "MmrcData.h" UPDATE_FSPM_UPD_FUNC mLhUpdateFspmUpdPtr = LhUpdateFspmUpd; DRAM_CREATE_POLICY_DEFAULTS_FUNC mLhDramCreatePolicyDefaultsPtr = LhDramCreatePolicyDefaults; @@ -29,6 +30,9 @@ LhUpdateFspmUpd ( EFI_PLATFORM_INFO_HOB *PlatformInfo = NULL; DRAM_POLICY_PPI *DramPolicy; EFI_STATUS Status; + MRC_NV_DATA_FRAME *MrcNvData; + MRC_PARAMS_SAVE_RESTORE *MrcParamsHob; + BOOT_VARIABLE_NV_DATA *BootVariableNvDataHob; Status = (*PeiServices)->LocatePpi ( PeiServices, @@ -64,11 +68,20 @@ LhUpdateFspmUpd ( FspUpdRgn->FspmConfig.InterleavedMode = DramPolicy->InterleavedMode; FspUpdRgn->FspmConfig.MinRefRate2xEnable = DramPolicy->MinRefRate2xEnabled; FspUpdRgn->FspmConfig.DualRankSupportEnable = DramPolicy->DualRankSupportEnabled; - FspUpdRgn->FspmArchUpd.NvsBufferPtr = (VOID *)(UINT32)DramPolicy->MrcTrainingDataPtr; - FspUpdRgn->FspmConfig.MrcBootDataPtr = (VOID *)(UINT32)DramPolicy->MrcBootDataPtr; CopyMem (&(FspUpdRgn->FspmConfig.Ch0_RankEnable), &DramPolicy->ChDrp, sizeof (DramPolicy->ChDrp)); CopyMem (&(FspUpdRgn->FspmConfig.Ch0_Bit_swizzling), &DramPolicy->ChSwizzle, sizeof (DramPolicy->ChSwizzle)); + + if (((VOID *)(UINT32)DramPolicy->MrcTrainingDataPtr != 0) && + ((VOID *)(UINT32)DramPolicy->MrcBootDataPtr != 0)) { + MrcNvData = (MRC_NV_DATA_FRAME *) AllocateZeroPool (sizeof (MRC_NV_DATA_FRAME)); + MrcParamsHob = (MRC_PARAMS_SAVE_RESTORE*)((UINT32)DramPolicy->MrcTrainingDataPtr); + BootVariableNvDataHob = (BOOT_VARIABLE_NV_DATA*)((UINT32)DramPolicy->MrcBootDataPtr); + CopyMem(&(MrcNvData->MrcParamsSaveRestore), MrcParamsHob, sizeof (MRC_PARAMS_SAVE_RESTORE)); + CopyMem(&(MrcNvData->BootVariableNvData), BootVariableNvDataHob, sizeof (BOOT_VARIABLE_NV_DATA)); + FspUpdRgn->FspmArchUpd.NvsBufferPtr = (VOID *)(UINT32)MrcNvData; + } + } // // override RankEnable settings for Minnow diff --git a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitPreMem.inf b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitPreMem.inf index 97ed7b2342..c526bc2c09 100644 --- a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitPreMem.inf +++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitPreMem.inf @@ -2,7 +2,7 @@ # Board detected module for Intel(R) Atom(TM) x5 Processor Series. # It will detect the board ID. # -# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -39,6 +39,7 @@ IntelFsp2Pkg/IntelFsp2Pkg.dec BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + Silicon\BroxtonSoC\BroxtonSiPkg\NorthCluster\MemoryInit\MemoryInit.dec [Pcd] gPlatformModuleTokenSpaceGuid.PcdBoardId diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c index edf6147b18..9e535ca8e9 100644 --- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c @@ -1,7 +1,7 @@ /** @file This file does Multiplatform initialization. - Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License @@ -14,6 +14,7 @@ **/ #include "BoardInitMiscs.h" +#include "MmrcData.h" UPDATE_FSPM_UPD_FUNC mMb3UpdateFspmUpdPtr = Mb3UpdateFspmUpd; DRAM_CREATE_POLICY_DEFAULTS_FUNC mMb3DramCreatePolicyDefaultsPtr = Mb3DramCreatePolicyDefaults; @@ -29,6 +30,9 @@ Mb3UpdateFspmUpd ( EFI_PLATFORM_INFO_HOB *PlatformInfo = NULL; DRAM_POLICY_PPI *DramPolicy; EFI_STATUS Status; + MRC_NV_DATA_FRAME *MrcNvData; + MRC_PARAMS_SAVE_RESTORE *MrcParamsHob; + BOOT_VARIABLE_NV_DATA *BootVariableNvDataHob; Status = (*PeiServices)->LocatePpi ( PeiServices, @@ -64,11 +68,20 @@ Mb3UpdateFspmUpd ( FspUpdRgn->FspmConfig.InterleavedMode = DramPolicy->InterleavedMode; FspUpdRgn->FspmConfig.MinRefRate2xEnable = DramPolicy->MinRefRate2xEnabled; FspUpdRgn->FspmConfig.DualRankSupportEnable = DramPolicy->DualRankSupportEnabled; - FspUpdRgn->FspmArchUpd.NvsBufferPtr = (VOID *)(UINT32)DramPolicy->MrcTrainingDataPtr; - FspUpdRgn->FspmConfig.MrcBootDataPtr = (VOID *)(UINT32)DramPolicy->MrcBootDataPtr; CopyMem (&(FspUpdRgn->FspmConfig.Ch0_RankEnable), &DramPolicy->ChDrp, sizeof(DramPolicy->ChDrp)); CopyMem (&(FspUpdRgn->FspmConfig.Ch0_Bit_swizzling), &DramPolicy->ChSwizzle, sizeof (DramPolicy->ChSwizzle)); + + if (((VOID *)(UINT32)DramPolicy->MrcTrainingDataPtr != 0) && + ((VOID *)(UINT32)DramPolicy->MrcBootDataPtr != 0)) { + MrcNvData = (MRC_NV_DATA_FRAME *) AllocateZeroPool (sizeof (MRC_NV_DATA_FRAME)); + MrcParamsHob = (MRC_PARAMS_SAVE_RESTORE*)((UINT32)DramPolicy->MrcTrainingDataPtr); + BootVariableNvDataHob = (BOOT_VARIABLE_NV_DATA*)((UINT32)DramPolicy->MrcBootDataPtr); + CopyMem(&(MrcNvData->MrcParamsSaveRestore), MrcParamsHob, sizeof (MRC_PARAMS_SAVE_RESTORE)); + CopyMem(&(MrcNvData->BootVariableNvData), BootVariableNvDataHob, sizeof (BOOT_VARIABLE_NV_DATA)); + FspUpdRgn->FspmArchUpd.NvsBufferPtr = (VOID *)(UINT32)MrcNvData; + } + } // // override RankEnable settings for Minnow diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitPreMem.inf b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitPreMem.inf index 81448e365b..9135fb8612 100644 --- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitPreMem.inf +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitPreMem.inf @@ -2,7 +2,7 @@ # Board detected module for Intel(R) Atom(TM) x5 Processor Series. # It will detect the board ID. # -# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -39,6 +39,7 @@ IntelFsp2Pkg/IntelFsp2Pkg.dec BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + Silicon\BroxtonSoC\BroxtonSiPkg\NorthCluster\MemoryInit\MemoryInit.dec [Pcd] gPlatformModuleTokenSpaceGuid.PcdBoardId -- cgit v1.2.3