From a56cf5fd57d9853b8ee62c8a5dc6c1ca374d3c15 Mon Sep 17 00:00:00 2001 From: Guo Mang Date: Fri, 23 Dec 2016 13:37:43 +0800 Subject: BroxtonPlatformPkg: Add AcpiTablesPCAT Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang --- .../Common/Acpi/AcpiTablesPCAT/98_LINK.ASL | 589 +++++++++++++++ .../Common/Acpi/AcpiTablesPCAT/AMLUPD.asl | 26 + .../Common/Acpi/AcpiTablesPCAT/AcpiTablePlatform.h | 68 ++ .../Common/Acpi/AcpiTablesPCAT/AcpiTables.inf | 46 ++ .../Common/Acpi/AcpiTablesPCAT/Bxt.asl | 64 ++ .../Common/Acpi/AcpiTablesPCAT/BxtPGpioDefine.asl | 274 +++++++ .../Common/Acpi/AcpiTablesPCAT/CPU.asl | 44 ++ .../Common/Acpi/AcpiTablesPCAT/CSRT.aslc | 221 ++++++ .../Common/Acpi/AcpiTablesPCAT/Csrt.h | 82 ++ .../Common/Acpi/AcpiTablesPCAT/DBG2/DBG2.aslc | 77 ++ .../Common/Acpi/AcpiTablesPCAT/DBGP/DBGP.aslc | 57 ++ .../Common/Acpi/AcpiTablesPCAT/DSDT.ASL | 95 +++ .../Common/Acpi/AcpiTablesPCAT/Dmar/Dmar.aslc | 188 +++++ .../Common/Acpi/AcpiTablesPCAT/Dmar/Dmar.h | 33 + .../Acpi/AcpiTablesPCAT/DptfAcpiTable/Art.asl | 46 ++ .../AcpiTablesPCAT/DptfAcpiTable/BiosDataVault.asl | 15 + .../DptfAcpiTable/DPLYParticipant.asl | 155 ++++ .../Acpi/AcpiTablesPCAT/DptfAcpiTable/Dppm.asl | 63 ++ .../Acpi/AcpiTablesPCAT/DptfAcpiTable/Dptf.asl | 641 ++++++++++++++++ .../DptfAcpiTable/Gen1Participant.asl | 349 +++++++++ .../DptfAcpiTable/Gen2Participant.asl | 349 +++++++++ .../DptfAcpiTable/Gen3Participant.asl | 349 +++++++++ .../DptfAcpiTable/Gen4Participant.asl | 349 +++++++++ .../Acpi/AcpiTablesPCAT/DptfAcpiTable/Psvt.asl | 33 + .../DptfAcpiTable/SEN1Participant.asl | 343 +++++++++ .../DptfAcpiTable/TFN1Participant.asl | 138 ++++ .../DptfAcpiTable/TPwrParticipant.asl | 288 +++++++ .../DptfAcpiTable/TcpuParticipant.asl | 568 ++++++++++++++ .../Acpi/AcpiTablesPCAT/DptfAcpiTable/Trt.asl | 52 ++ .../DptfAcpiTable/Vir1Participant.asl | 454 +++++++++++ .../DptfAcpiTable/Vir2Participant.asl | 454 +++++++++++ .../DptfAcpiTable/Vir3Participant.asl | 454 +++++++++++ .../Common/Acpi/AcpiTablesPCAT/Facp/Facp.aslc | 182 +++++ .../Common/Acpi/AcpiTablesPCAT/Facs/Facs.aslc | 77 ++ .../Common/Acpi/AcpiTablesPCAT/GloblNvs.asl | 478 ++++++++++++ .../Common/Acpi/AcpiTablesPCAT/Gpe.asl | 73 ++ .../Common/Acpi/AcpiTablesPCAT/GpioLib.asl | 163 ++++ .../Common/Acpi/AcpiTablesPCAT/HOST_BUS.ASL | 334 ++++++++ .../Common/Acpi/AcpiTablesPCAT/Hpet/Hpet.aslc | 59 ++ .../Common/Acpi/AcpiTablesPCAT/LPC_DEV.ASL | 115 +++ .../Common/Acpi/AcpiTablesPCAT/LpcB.asl | 49 ++ .../Common/Acpi/AcpiTablesPCAT/Lpit/Lpit.aslc | 191 +++++ .../Common/Acpi/AcpiTablesPCAT/Lpit/Lpit.h | 121 +++ .../Common/Acpi/AcpiTablesPCAT/Madt/Madt.h | 188 +++++ .../Common/Acpi/AcpiTablesPCAT/Madt/Madt30.aslc | 209 +++++ .../Common/Acpi/AcpiTablesPCAT/Mcfg/Mcfg.aslc | 78 ++ .../Common/Acpi/AcpiTablesPCAT/PCI_DRC.ASL | 83 ++ .../Common/Acpi/AcpiTablesPCAT/PciTree.asl | 199 +++++ .../Acpi/AcpiTablesPCAT/PcieRpPxsxWrapper.asl | 43 ++ .../Common/Acpi/AcpiTablesPCAT/Pep/Pep.asl | 255 +++++++ .../Common/Acpi/AcpiTablesPCAT/Platform.asl | 783 +++++++++++++++++++ .../PlatformSsdt/Audio/AudioCodec_INT343A.asl | 57 ++ .../PlatformSsdt/Audio/AudioCodec_INT34C1.asl | 57 ++ .../PlatformSsdt/Bluetooth/Bluetooth_BCM2E40.asl | 55 ++ .../PlatformSsdt/Bluetooth/Bluetooth_BCM2EA1.asl | 55 ++ .../PlatformSsdt/Camera/Camera_INT3471.asl | 187 +++++ .../PlatformSsdt/Camera/Camera_INT3474.asl | 196 +++++ .../PlatformSsdt/Camera/Camera_Sony214A.asl | 188 +++++ .../PlatformSsdt/Camera/Flash_TPS61311.asl | 93 +++ .../PlatformSsdt/Fingerprint/Fingerprint_FPC.asl | 50 ++ .../Acpi/AcpiTablesPCAT/PlatformSsdt/Gps/Gps.asl | 56 ++ .../Acpi/AcpiTablesPCAT/PlatformSsdt/Irmt.asl | 99 +++ .../Acpi/AcpiTablesPCAT/PlatformSsdt/Nfc/Nfc.asl | 70 ++ .../PlatformSsdt/PSS/MonzaX2K_IMPJ0003.asl | 51 ++ .../AcpiTablesPCAT/PlatformSsdt/PlatformSsdt.asl | 71 ++ .../AcpiTablesPCAT/PlatformSsdt/PlatformSsdt.inf | 31 + .../PlatformSsdt/Touch/TouchPads_I2C4.asl | 115 +++ .../PlatformSsdt/Touch/TouchPanel_I2C3.asl | 142 ++++ .../PlatformSsdt/Wifi/WIFI_Broadcom1.asl | 68 ++ .../PlatformSsdt/Wifi/WIFI_Broadcom2.asl | 49 ++ .../Common/Acpi/AcpiTablesPCAT/Pram/Pram.aslc | 61 ++ .../Common/Acpi/AcpiTablesPCAT/Sc.asl | 292 +++++++ .../Common/Acpi/AcpiTablesPCAT/ScAudio.asl | 248 ++++++ .../Common/Acpi/AcpiTablesPCAT/ScLpss.asl | 579 ++++++++++++++ .../Common/Acpi/AcpiTablesPCAT/ScPcie.asl | 88 +++ .../Common/Acpi/AcpiTablesPCAT/ScSata.asl | 66 ++ .../Common/Acpi/AcpiTablesPCAT/ScScc.asl | 719 ++++++++++++++++++ .../Common/Acpi/AcpiTablesPCAT/ScSmb.asl | 558 ++++++++++++++ .../Common/Acpi/AcpiTablesPCAT/ScXdci.asl | 300 ++++++++ .../Common/Acpi/AcpiTablesPCAT/ScXhci.asl | 611 +++++++++++++++ .../Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtPcie.asl | 312 ++++++++ .../Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtSata.asl | 216 ++++++ .../Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtUsb.asl | 63 ++ .../AcpiTablesPCAT/SsdtRtd3/Rtd3BxtUsbWwan.asl | 90 +++ .../Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3Common.asl | 91 +++ .../Acpi/AcpiTablesPCAT/SsdtRtd3/RvpRtd3.asl | 841 +++++++++++++++++++++ .../Common/Acpi/AcpiTablesPCAT/THERMAL.ASL | 201 +++++ .../Common/Acpi/AcpiTablesPCAT/UsbSbd.asl | 68 ++ .../Acpi/AcpiTablesPCAT/UsbTypeC/UsbTypeC.asl | 148 ++++ .../Common/Acpi/AcpiTablesPCAT/Video.asl | 32 + .../Common/Acpi/AcpiTablesPCAT/Wifi.asl | 57 ++ .../Common/Acpi/AcpiTablesPCAT/Wsmt/WSMT.h | 57 ++ .../Common/Acpi/AcpiTablesPCAT/Wsmt/Wsmt.act | 82 ++ .../Common/Acpi/AcpiTablesPCAT/token.asl | 55 ++ 94 files changed, 18169 insertions(+) create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/98_LINK.ASL create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/AMLUPD.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/AcpiTablePlatform.h create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/AcpiTables.inf create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Bxt.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/BxtPGpioDefine.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/CPU.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/CSRT.aslc create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Csrt.h create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DBG2/DBG2.aslc create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DBGP/DBGP.aslc create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DSDT.ASL create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Dmar/Dmar.aslc create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Dmar/Dmar.h create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Art.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/BiosDataVault.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/DPLYParticipant.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Dppm.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Dptf.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Gen1Participant.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Gen2Participant.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Gen3Participant.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Gen4Participant.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Psvt.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/SEN1Participant.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/TFN1Participant.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/TPwrParticipant.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/TcpuParticipant.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Trt.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Vir1Participant.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Vir2Participant.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Vir3Participant.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Facp/Facp.aslc create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Facs/Facs.aslc create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/GloblNvs.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Gpe.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/GpioLib.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/HOST_BUS.ASL create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Hpet/Hpet.aslc create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/LPC_DEV.ASL create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/LpcB.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Lpit/Lpit.aslc create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Lpit/Lpit.h create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Madt/Madt.h create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Madt/Madt30.aslc create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Mcfg/Mcfg.aslc create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PCI_DRC.ASL create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PciTree.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PcieRpPxsxWrapper.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Pep/Pep.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Platform.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Audio/AudioCodec_INT343A.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Audio/AudioCodec_INT34C1.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Bluetooth/Bluetooth_BCM2E40.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Bluetooth/Bluetooth_BCM2EA1.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Camera/Camera_INT3471.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Camera/Camera_INT3474.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Camera/Camera_Sony214A.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Camera/Flash_TPS61311.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Fingerprint/Fingerprint_FPC.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Gps/Gps.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Irmt.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Nfc/Nfc.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/PSS/MonzaX2K_IMPJ0003.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/PlatformSsdt.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/PlatformSsdt.inf create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Touch/TouchPads_I2C4.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Touch/TouchPanel_I2C3.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Wifi/WIFI_Broadcom1.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Wifi/WIFI_Broadcom2.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Pram/Pram.aslc create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Sc.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScAudio.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScLpss.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScPcie.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScSata.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScScc.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScSmb.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScXdci.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScXhci.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtPcie.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtSata.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtUsb.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtUsbWwan.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3Common.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/RvpRtd3.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/THERMAL.ASL create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/UsbSbd.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/UsbTypeC/UsbTypeC.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Video.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Wifi.asl create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Wsmt/WSMT.h create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Wsmt/Wsmt.act create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/token.asl (limited to 'Platform/BroxtonPlatformPkg/Common') diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/98_LINK.ASL b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/98_LINK.ASL new file mode 100644 index 0000000000..eb3ca15800 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/98_LINK.ASL @@ -0,0 +1,589 @@ +/** @file + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// Use this information when determining the Possible IRQs that can be +// used in a given system. +// +// The following IRQs are always in use by legacy devices: +// 0 = System Timer +// 2 = 8259 PIC +// 8 = RTC +// 9 = SCI Interrupt (It may be used, we choose not to) +// 13 = Co-processor Error +// +// The following may be in use by legacy devices: +// 1 = If using PS/2 Keyboard +// 3 = If COMx Port Enabled and IRQ = 3 +// 4 = If COMx Port Enabled and IRQ = 4 +// 5 = If LPT Port Enabled and IRQ = 5 +// 6 = If FDC Enabled +// 7 = If LPT Port Enabled and IRQ = 7 +// 12 = If using PS/2 Mouse +// 14 = Primary IDE (If populated and in Compatibility Mode) +// 15 = Secondary IDE (If populated and in Compatibility Mode) +// +// The following will never be in use by legacy devices: +// 10 = Assign to PARC, PCRC, PERC, PGRC +// 11 = Assign to PBRC, PDRC, PFRC, PHRC + +Device(LNKA) // PARC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) // PCI Interrupt Link Device + + Name(_UID,1) // Unique to other Link Devices + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PARC,0x80,PARC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSA) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLA,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLA,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PARC,0x0F),IRQ0) + + Return(RTLA) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PARC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If (And(PARC,0x80)) { + Return(0x0009) + } Else { + Return(0x000B) + } + } +} + +Device(LNKB) // PBRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,2) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PBRC,0x80,PBRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSB) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLB,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLB,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PBRC,0x0F),IRQ0) + + Return(RTLB) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PBRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If (And(PBRC,0x80)) { + Return(0x0009) + } Else { + Return(0x000B) + } + } +} + +Device(LNKC) // PCRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,3) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PCRC,0x80,PCRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSC) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLC,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLC,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PCRC,0x0F),IRQ0) + + Return(RTLC) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PCRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If (And(PCRC,0x80)) { + Return(0x0009) + } Else { + Return(0x000B) + } + } +} + +Device(LNKD) // PDRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,4) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PDRC,0x80,PDRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSD) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLD,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLD,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PDRC,0x0F),IRQ0) + + Return(RTLD) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PDRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If (And(PDRC,0x80)) { + Return(0x0009) + } Else { + Return(0x000B) + } + } +} + +Device(LNKE) // PERC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,5) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PERC,0x80,PERC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSE) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLE,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLE,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PERC,0x0F),IRQ0) + + Return(RTLE) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PERC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If (And(PERC,0x80)) { + Return(0x0009) + } Else { + Return(0x000B) + } + } +} + +Device(LNKF) // PFRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,6) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PFRC,0x80,PFRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSF) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLF,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLF,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PFRC,0x0F),IRQ0) + + Return(RTLF) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PFRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If (And(PFRC,0x80)) { + Return(0x0009) + } Else { + Return(0x000B) + } + } +} + +Device(LNKG) // PGRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,7) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PGRC,0x80,PGRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSG) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLG,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLG,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PGRC,0x0F),IRQ0) + + Return(RTLG) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PGRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If (And(PGRC,0x80)) { + Return(0x0009) + } Else { + Return(0x000B) + } + } +} + +Device(LNKH) // PHRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,8) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PHRC,0x80,PHRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSH) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLH,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLH,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PHRC,0x0F),IRQ0) + + Return(RTLH) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PHRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If (And(PHRC,0x80)) { + Return(0x0009) + } Else { + Return(0x000B) + } + } +} diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/AMLUPD.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/AMLUPD.asl new file mode 100644 index 0000000000..32c4f7f1b7 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/AMLUPD.asl @@ -0,0 +1,26 @@ +/** @file + ACPI DSDT table + + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +/////////////////////////////////////////////////////////////////////////////////// +//Values are set like this to have ASL compiler reserve enough space for objects +/////////////////////////////////////////////////////////////////////////////////// +// +// Available Sleep states +// +Name(SS1,0) +Name(SS2,0) +Name(SS3,1) +Name(SS4,1) + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/AcpiTablePlatform.h b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/AcpiTablePlatform.h new file mode 100644 index 0000000000..f588165198 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/AcpiTablePlatform.h @@ -0,0 +1,68 @@ +/** @file + This file describes the contents of the ACPI Fixed ACPI Description Table + (FADT). + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _Platform_h_INCLUDED_ +#define _Platform_h_INCLUDED_ + +#include + +// +// ACPI table information used to initialize tables. +// +#define EFI_ACPI_OEM_ID 'I','N','T','E','L',' ' // OEMID 6 bytes long +#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('L','A','N','F','O','R','D','C') // OEM table id 8 bytes long +#define EFI_ACPI_OEM_REVISION 0x00000005 +#define EFI_ACPI_CREATOR_ID SIGNATURE_32('M','S','F','T') +#define EFI_ACPI_CREATOR_REVISION 0x0100000D +#define INT_MODEL 0x01 +#define PM_PROFILE EFI_ACPI_4_0_PM_PROFILE_MOBILE +#define SCI_INT_VECTOR 0x0009 +#define SMI_CMD_IO_PORT 0x000000B2 +#define ACPI_ENABLE 0x0A0 +#define ACPI_DISABLE 0x0A1 +#define S4BIOS_REQ 0x00 +#define PSTATE_CNT 0x00 +#define PM1a_EVT_BLK 0x400 +#define PM1b_EVT_BLK 0x00000000 +#define PM1a_CNT_BLK 0x404 +#define PM1b_CNT_BLK 0x00000000 +#define PM2_CNT_BLK 0x450 +#define PM_TMR_BLK 0x408 +#define GPE0_BLK 0x420 +#define GPE1_BLK 0x00000000 +#define PM1_EVT_LEN 0x04 +#define PM1_CNT_LEN 0x02 +#define PM2_CNT_LEN 0x01 +#define PM_TM_LEN 0x04 +#define GPE0_BLK_LEN 0x20 +#define GPE1_BLK_LEN 0x00 +#define GPE1_BASE 0x00 +#define CST_CNT 0x00 +#define P_LVL2_LAT 0x0032 +#define P_LVL3_LAT 0x0096 +#define FLUSH_SIZE 0x0400 +#define FLUSH_STRIDE 0x0010 +#define DUTY_OFFSET 0x01 +#define DUTY_WIDTH 0x03 +#define DAY_ALRM 0x0D +#define MON_ALRM 0x00 +#define CENTURY 0x32 +#define FLAG (EFI_ACPI_5_0_WBINVD | EFI_ACPI_5_0_SLP_BUTTON | EFI_ACPI_5_0_RESET_REG_SUP | EFI_ACPI_5_0_RTC_S4) +#define IAPC_BOOT_ARCH (EFI_ACPI_5_0_8042 | EFI_ACPI_5_0_LEGACY_DEVICES) +#define RESERVED 0x00 + +#endif + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/AcpiTables.inf b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/AcpiTables.inf new file mode 100644 index 0000000000..1e456e3405 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/AcpiTables.inf @@ -0,0 +1,46 @@ +## @file +# Component information file for the ACPI tables. +# +# Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[defines] + INF_VERSION = 0x00010005 + BASE_NAME = AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + EDK_RELEASE_VERSION = 0x00020000 + EFI_SPECIFICATION_VERSION = 0x00020000 + +[sources.common] + DSDT.ASL + Facs/Facs.aslc + Facp/Facp.aslc + Madt/Madt30.aslc + Mcfg/Mcfg.aslc + Hpet/Hpet.aslc + Dmar/Dmar.aslc + Dmar/Dmar.h + Lpit/Lpit.aslc + Lpit/Lpit.h + SsdtRtd3/RvpRtd3.asl + DBG2/DBG2.aslc + DBGP/DBGP.aslc + DptfAcpiTable/Dptf.asl + UsbTypeC/UsbTypeC.asl + Wsmt/Wsmt.act + +[Packages] + MdePkg/MdePkg.dec + BroxtonPlatformPkg/PlatformPkg.dec + BroxtonSiPkg/BroxtonSiPkg.dec diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Bxt.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Bxt.asl new file mode 100644 index 0000000000..aa06bda436 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Bxt.asl @@ -0,0 +1,64 @@ +/** @file + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope (\_SB.PCI0) { + // + // Integrated Sensor Hub - Device 17, Function 0 + // + Device(ISH0) { + Name(_ADR, 0x00110000) + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + //-------------------- + // Intel Proprietary Wake up Event solution + //-------------------- + Method(_DSM, 0x4, Serialized) + { + If (LEqual(Arg0, ToUUID("1730E71D-E5DD-4A34-BE57-4D76B6A2FE37"))) { + // Function 0 : Query Function + If (LEqual(Arg2, Zero)) { + // Revision 0 + If (LEqual(Arg1, Zero)) { + Return(Buffer(One) { 0x03 }) // There are 1 function defined other than Query. + } Else { + Return(0) // Revision mismatch + } + } + // Function 1 : + If (LEqual(Arg2, One)) { + Store(DerefOf(Index(Arg3, Zero)), Local0) + If (LEqual(Local0, Zero)) { + + } Else { + //Handle sleep, dock, un-dock events here + } + Return(0) + } Else { + Return(0) // Function number mismatch but normal return. + } + } Else { + Return(Buffer(One) { 0x00 }) // Guid mismatch + } + } + + Method (_PS0, 0, NotSerialized) { // _PS0: Power State 0 + } + + Method (_PS3, 0, NotSerialized) { // _PS3: Power State 3 + } + } + +}//end scope + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/BxtPGpioDefine.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/BxtPGpioDefine.asl new file mode 100644 index 0000000000..69b8ec2fb3 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/BxtPGpioDefine.asl @@ -0,0 +1,274 @@ +/** @file + Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _BXTP_GPIO_DEFINE_ASL_ +#define _BXTP_GPIO_DEFINE_ASL_ + +// +// GPIO pad and offset definition as GPIO HAS +// North community GPIO pad definition +// +#define N_GPIO_0 0x00C50500 //GPIO_0 +#define N_GPIO_1 0x00C50508 //GPIO_1 +#define N_GPIO_2 0x00C50510 //GPIO_2 +#define N_GPIO_3 0x00C50518 //GPIO_3 +#define N_GPIO_4 0x00C50520 //GPIO_4 +#define N_GPIO_5 0x00C50528 //GPIO_5 +#define N_GPIO_6 0x00C50530 //GPIO_6 +#define N_GPIO_7 0x00C50538 //GPIO_7 +#define N_GPIO_8 0x00C50540 //GPIO_8 +#define N_GPIO_9 0x00C50548 //GPIO_9 +#define N_GPIO_10 0x00C50550 //GPIO_10 +#define N_GPIO_11 0x00C50558 //GPIO_11 +#define N_GPIO_12 0x00C50560 //GPIO_12 +#define N_GPIO_13 0x00C50568 //GPIO_13 +#define N_GPIO_14 0x00C50570 //GPIO_14 +#define N_GPIO_15 0x00C50578 //GPIO_15 +#define N_GPIO_16 0x00C50580 //GPIO_16 +#define N_GPIO_17 0x00C50588 //GPIO_17 +#define N_GPIO_18 0x00C50590 //GPIO_18 +#define N_GPIO_19 0x00C50598 //GPIO_19 +#define N_GPIO_20 0x00C505A0 //GPIO_20 +#define N_GPIO_21 0x00C505A8 //GPIO_21 +#define N_GPIO_22 0x00C505B0 //GPIO_22 +#define N_GPIO_23 0x00C505B8 //GPIO_23 +#define N_GPIO_24 0x00C505C0 //GPIO_24 +#define N_GPIO_25 0x00C505C8 //GPIO_25 +#define N_GPIO_26 0x00C505D0 //GPIO_26 +#define N_GPIO_27 0x00C505D8 //GPIO_27 +#define N_GPIO_28 0x00C505E0 //GPIO_28 +#define N_GPIO_29 0x00C505E8 //GPIO_29 +#define N_GPIO_30 0x00C505F0 //GPIO_30 +#define N_GPIO_31 0x00C505F8 //GPIO_31 +#define N_GPIO_32 0x00C50600 //GPIO_32 +#define N_GPIO_33 0x00C50608 //GPIO_33 +#define N_GPIO_34 0x00C50610 //PWM0 +#define N_GPIO_35 0x00C50618 //PWM1 +#define N_GPIO_36 0x00C50620 //PWM2 +#define N_GPIO_37 0x00C50628 //PWM3 +#define N_GPIO_38 0x00C50630 //LPSS_UART0_RXD +#define N_GPIO_39 0x00C50638 //LPSS_UART0_TXD +#define N_GPIO_40 0x00C50640 //LPSS_UART0_RTS_B +#define N_GPIO_41 0x00C50648 //LPSS_UART0_CTS_B +#define N_GPIO_42 0x00C50650 //LPSS_UART1_RXD +#define N_GPIO_43 0x00C50658 //LPSS_UART1_TXD +#define N_GPIO_44 0x00C50660 //LPSS_UART1_RTS_B +#define N_GPIO_45 0x00C50668 //LPSS_UART1_CTS_B +#define N_GPIO_46 0x00C50670 //LPSS_UART2_RXD +#define N_GPIO_47 0x00C50678 //LPSS_UART2_TXD +#define N_GPIO_48 0x00C50680 //LPSS_UART2_RTS_B +#define N_GPIO_49 0x00C50688 //LPSS_UART2_CTS_B +#define N_GPIO_62 0x00C50690 //GP_CAMERASB00 +#define N_GPIO_63 0x00C50698 //GP_CAMERASB01 +#define N_GPIO_64 0x00C506A0 //GP_CAMERASB02 +#define N_GPIO_65 0x00C506A8 //GP_CAMERASB03 +#define N_GPIO_66 0x00C506B0 //GP_CAMERASB04 +#define N_GPIO_67 0x00C506B8 //GP_CAMERASB05 +#define N_GPIO_68 0x00C506C0 //GP_CAMERASB06 +#define N_GPIO_69 0x00C506C8 //GP_CAMERASB07 +#define N_GPIO_70 0x00C506D0 //GP_CAMERASB08 +#define N_GPIO_71 0x00C506D8 //GP_CAMERASB09 +#define N_GPIO_72 0x00C506E0 //GP_CAMERASB10 +#define N_GPIO_73 0x00C506E8 //GP_CAMERASB11 +#define N_TCK 0x00C506F0 //TCK +#define N_TRST_B 0x00C506F8 //TRST_B +#define N_TMS 0x00C50700 //TMS +#define N_TDI 0x00C50708 //TDI +#define N_CX_PMODE 0x00C50710 //CX_PMODE +#define N_CX_PREQ_B 0x00C50718 //CX_PREQ_B +#define N_JTAGX 0x00C50720 //JTAGX +#define N_CX_PRDY_B 0x00C50728 //CXPRDY_B +#define N_TDO 0x00C50730 //TDO +#define N_CNV_BRI_DT 0x00C50738 //CNV_BRI_DT +#define N_CNV_BRI_RSP 0x00C50740 //CNV_BRI_RSP +#define N_CNV_RGI_DT 0x00C50748 //CNV_RGI_DT +#define N_CNV_RGI_RSP 0x00C50750 //CNV_RGI_RSP +#define N_SVID0_ALERT_B 0x00C50758 //SVID0_ALERT_B +#define N_SVID0_DATA 0x00C50760 //SVID0_DATA +#define N_SVID0_CLK 0x00C50768 //SVID0_CLK + +// Northwest community GPIO pad definition +#define NW_GPIO_187 0x00C40500 //HV_DDI0_DDC_SDA +#define NW_GPIO_188 0x00C40508 //HV_DDI0_DDC_SCL +#define NW_GPIO_189 0x00C40510 //HV_DDI1_DDC_SDA +#define NW_GPIO_190 0x00C40518 //HV_DDI1_DDC_SCL +#define NW_GPIO_191 0x00C40520 //DBI_SDA +#define NW_GPIO_192 0x00C40528 //DBI_SCL +#define NW_GPIO_193 0x00C40530 //PANEL0_VDDEN +#define NW_GPIO_194 0x00C40538 //PANEL0_BKLTEN +#define NW_GPIO_195 0x00C40540 //PANEL0_BKLTCTL +#define NW_GPIO_196 0x00C40548 //PANEL1_VDDEN +#define NW_GPIO_197 0x00C40550 //PANEL1_BKLTEN +#define NW_GPIO_198 0x00C40558 //PANEL1_BKLTCTL +#define NW_GPIO_199 0x00C40560 //DBI_CSX +#define NW_GPIO_200 0x00C40568 //DBI_RESX +#define NW_GPIO_201 0x00C40570 //GP_INTD_DSI_TE1 +#define NW_GPIO_202 0x00C40578 //GP_INTD_DSI_TE2 +#define NW_GPIO_203 0x00C40580 //USB_OC0_B +#define NW_GPIO_204 0x00C40588 //USB_OC1_B +#define NW_PMC_SPI_FS0 0x00C40590 //PMC_SPI_FS0 +#define NW_PMC_SPI_FS1 0x00C40598 //PMC_SPI_FS1 +#define NW_PMC_SPI_FS2 0x00C405A0 //PMC_SPI_FS2 +#define NW_PMC_SPI_RXD 0x00C405A8 //PMC_SPI_RXD +#define NW_PMC_SPI_TXD 0x00C405B0 //PMC_SPI_TXD +#define NW_PMC_SPI_CLK 0x00C405B8 //PMC_SPI_CLK +#define NW_PMIC_PWRGOOD 0x00C405C0 //PMIC_PWRGOOD +#define NW_PMIC_RESET_B 0x00C405C8 //PMIC_RESET_B +#define NW_GPIO_213 0x00C405D0 //PMIC_SDWN_B +#define NW_GPIO_214 0x00C405D8 //PMIC_BCUDISW2 +#define NW_GPIO_215 0x00C405E0 //PMIC_BCUDISCRIT +#define NW_PMIC_THERMTRIP_B 0x00C405E8 //PMIC_THERMTRIP_B +#define NW_PMIC_STDBY 0x00C405F0 //PMIC_STDBY +#define NW_PROCHOT_B 0x00C405F8 //PROCHOT_B +#define NW_PMIC_I2C_SCL 0x00C40600 //PMIC_I2C_SCL +#define NW_PMIC_I2C_SDA 0x00C40608 //PMIC_I2C_SDA +#define NW_GPIO_74 0x00C40610 //AVS_I2S1_MCLK +#define NW_GPIO_75 0x00C40618 //AVS_I2S1_BCLK +#define NW_GPIO_76 0x00C40620 //AVS_I2S1_WS_SYNC +#define NW_GPIO_77 0x00C40628 //AVS_I2S1_SDI +#define NW_GPIO_78 0x00C40630 //AVS_I2S1_SDO +#define NW_GPIO_79 0x00C40638 //AVS_M_CLK_A1 +#define NW_GPIO_80 0x00C40640 //AVS_M_CLK_B1 +#define NW_GPIO_81 0x00C40648 //AVS_M_DATA_1 +#define NW_GPIO_82 0x00C40650 //AVS_M_CLK_AB2 +#define NW_GPIO_83 0x00C40658 //AVS_M_DATA_2 +#define NW_GPIO_84 0x00C40660 //AVS_I2S2_MCLK +#define NW_GPIO_85 0x00C40668 //AVS_I2S2_BCLK +#define NW_GPIO_86 0x00C40670 //AVS_I2S2_WS_SYNC +#define NW_GPIO_87 0x00C40678 //AVS_I2S2_SDI +#define NW_GPIO_88 0x00C40680 //AVS_I2S2_SDO +#define NW_GPIO_89 0x00C40688 //AVS_I2S3_BCLK +#define NW_GPIO_90 0x00C40690 //AVS_I2S3_WS_SYNC +#define NW_GPIO_91 0x00C40698 //AVS_I2S3_SDI +#define NW_GPIO_92 0x00C406A0 //AVS_I2S3_SDO +#define NW_GPIO_97 0x00C406A8 //FST_SPI_CS0_B +#define NW_GPIO_98 0x00C406B0 //FST_SPI_CS1_B +#define NW_GPIO_99 0x00C406B8 //FST_SPI_MOSI_IO0 +#define NW_GPIO_100 0x00C406C0 //FST_SPI_MISO_IO1 +#define NW_GPIO_101 0x00C406C8 //FST_SPI_IO2 +#define NW_GPIO_102 0x00C406D0 //FST_SPI_IO3 +#define NW_GPIO_103 0x00C406D8 //FST_SPI_CLK +#define NW_FST_SPI_CLK_FB 0x00C406E0 //FST_SPI_CLK_FB +#define NW_GPIO_104 0x00C406E8 //GP_SSP_0_CLK +#define NW_GPIO_105 0x00C406F0 //GP_SSP_0_FS0 +#define NW_GPIO_106 0x00C406F8 //GP_SSP_0_FS1 +#define NW_GPIO_109 0x00C40700 //GP_SSP_0_RXD +#define NW_GPIO_110 0x00C40708 //GP_SSP_0_TXD +#define NW_GPIO_111 0x00C40710 //GP_SSP_1_CLK +#define NW_GPIO_112 0x00C40718 //GP_SSP_1_FS0 +#define NW_GPIO_113 0x00C40720 //GP_SSP_1_FS1 +#define NW_GPIO_116 0x00C40728 //GP_SSP_1_RXD +#define NW_GPIO_117 0x00C40730 //GP_SSP_1_TXD +#define NW_GPIO_118 0x00C40738 //GP_SSP_2_CLK +#define NW_GPIO_119 0x00C40740 //GP_SSP_2_FS0 +#define NW_GPIO_120 0x00C40748 //GP_SSP_2_FS1 +#define NW_GPIO_121 0x00C40750 //GP_SSP_2_FS2 +#define NW_GPIO_122 0x00C40758 //GP_SSP_2_RXD +#define NW_GPIO_123 0x00C40760 //GP_SSP_2_TXD + +// West community GPIO pad definition +#define W_GPIO_124 0x00C70500 //LPSS_I2S0_SDA +#define W_GPIO_125 0x00C70508 //LPSS_I2S0_SCL +#define W_GPIO_126 0x00C70510 //LPSS_I2S1_SDA +#define W_GPIO_127 0x00C70518 //LPSS_I2S1_SCL +#define W_GPIO_128 0x00C70520 //LPSS_I2S2_SDA +#define W_GPIO_129 0x00C70528 //LPSS_I2S2_SCL +#define W_GPIO_130 0x00C70530 //LPSS_I2S3_SDA +#define W_GPIO_131 0x00C70538 //LPSS_I2S3_SCL +#define W_GPIO_132 0x00C70540 //LPSS_I2S4_SDA +#define W_GPIO_133 0x00C70548 //LPSS_I2S4_SCL +#define W_GPIO_134 0x00C70550 //LPSS_I2S5_SDA +#define W_GPIO_135 0x00C70558 //LPSS_I2S5_SCL +#define W_GPIO_136 0x00C70560 //LPSS_I2S6_SDA +#define W_GPIO_137 0x00C70568 //LPSS_I2S6_SCL +#define W_GPIO_138 0x00C70570 //LPSS_I2S7_SDA +#define W_GPIO_139 0x00C70578 //LPSS_I2S7_SCL +#define W_GPIO_146 0x00C70580 //ISH_GPIO_0 +#define W_GPIO_147 0x00C70588 //ISH_GPIO_1 +#define W_GPIO_148 0x00C70590 //ISH_GPIO_2 +#define W_GPIO_149 0x00C70598 //ISH_GPIO_3 +#define W_GPIO_150 0x00C705a0 //ISH_GPIO_4 +#define W_GPIO_151 0x00C705a8 //ISH_GPIO_5 +#define W_GPIO_152 0x00C705b0 //ISH_GPIO_6 +#define W_GPIO_153 0x00C705b8 //ISH_GPIO_7 +#define W_GPIO_154 0x00C705c0 //ISH_GPIO_8 +#define W_GPIO_155 0x00C705c8 //ISH_GPIO_9 +#define W_GPIO_209 0x00C705d0 //PCIE_CLKREQ0_B +#define W_GPIO_210 0x00C705d8 //PCIE_CLKREQ1_B +#define W_GPIO_211 0x00C705e0 //PCIE_CLKREQ2_B +#define W_GPIO_212 0x00C705e8 //PCIE_CLKREQ3_B +#define W_OSC_CLK_OUT_0 0x00C705f0 //OSC_CLK_OUT0 +#define W_OSC_CLK_OUT_1 0x00C705f8 //OSC_CLK_OUT1 +#define W_OSC_CLK_OUT_2 0x00C70600 //OSC_CLK_OUT2 +#define W_OSC_CLK_OUT_3 0x00C70608 //OSC_CLK_OUT3 +#define W_OSC_CLK_OUT_4 0x00C70610 //OSC_CLK_OUT4 +#define W_PMU_AC_PRESENT 0x00C70618 //PMU_AC_PRESENT +#define W_PMU_BATLOW_B 0x00C70620 //PMU_BATLOW_B +#define W_PMU_PLTRST_B 0x00C70628 //PMU_PLTRST_B +#define W_PMU_PWRBTN_B 0x00C70630 //PMU_PWRBTN_B +#define W_PMU_RESETBUTTON_B 0x00C70638 //PMU_RESETBUTTON_B +#define W_PMU_SLP_S0_B 0x00C70640 //PMU_SLP_S0_B +#define W_PMU_SLP_S3_B 0x00C70648 //PMU_SLP_S3_B +#define W_PMU_SLP_S4_B 0x00C70650 //PMU_SLP_S4_B +#define W_PMU_SUSCLK 0x00C70658 //PMU_SUSCLK +#define W_PMU_WAKE_B 0x00C70660 //PMU_WAKE_B +#define W_SUS_STAT_B 0x00C70668 //SUS_STAT_B +#define W_SUSPWRDNACK 0x00C70670 //SUSPWRDNACK + +// Southwest community GPIO pad definition +#define SW_GPIO_205 0x00C00500 //PCIE_WAKE0_B +#define SW_GPIO_206 0x00C00508 //PCIE_WAKE1_B +#define SW_GPIO_207 0x00C00510 //PCIE_WAKE2_B +#define SW_GPIO_208 0x00C00518 //PCIE_WAKE3_B +#define SW_GPIO_156 0x00C00520 //EMMC0_CLK +#define SW_GPIO_157 0x00C00528 //EMMC0_D0 +#define SW_GPIO_158 0x00C00530 //EMMC0_D1 +#define SW_GPIO_159 0x00C00538 //EMMC0_D2 +#define SW_GPIO_160 0x00C00540 //EMMC0_D3 +#define SW_GPIO_161 0x00C00548 //EMMC0_D4 +#define SW_GPIO_162 0x00C00550 //EMMC0_D5 +#define SW_GPIO_163 0x00C00558 //EMMC0_D6 +#define SW_GPIO_164 0x00C00560 //EMMC0_D7 +#define SW_GPIO_165 0x00C00568 //EMMC0_CMD0 +#define SW_GPIO_166 0x00C00570 //SDIO_CLK +#define SW_GPIO_167 0x00C00578 //SDIO_D0 +#define SW_GPIO_168 0x00C00580 //SDIO_D1 +#define SW_GPIO_169 0x00C00588 //SDIO_D2 +#define SW_GPIO_170 0x00C00590 //SDIO_D3 +#define SW_GPIO_171 0x00C00598 //SDIO_CMD +#define SW_GPIO_172 0x00C005A0 //SDCARD_CLK +#define SW_GPIO_179 0x00C005A8 //SDCARD_CLK_FB +#define SW_GPIO_173 0x00C005B0 //SDCARD_D0 +#define SW_GPIO_174 0x00C005B8 //SDCARD_D1 +#define SW_GPIO_175 0x00C005C0 //SDCARD_D2 +#define SW_GPIO_176 0x00C005C8 //SDCARD_D3 +#define SW_GPIO_177 0x00C005D0 //SDCARD_CD_B +#define SW_GPIO_178 0x00C005D8 //SDCARD_CMD +#define SW_GPIO_186 0x00C005E0 //SDCARD_LVL_WP +#define SW_GPIO_182 0x00C005E8 //EMMC0_STROBE +#define SW_GPIO_183 0x00C005F0 //SDIO_PWR_DOWN_B +#define SW_SMB_ALERTB 0x00C005F8 //SMB_ALERTB +#define SW_SMB_CLK 0x00C00600 //SMB_CLK +#define SW_SMB_DATA 0x00C00608 //SMB_DATA +#define SW_LPC_ILB_SERIRQ 0x00C00610 //LPC_ILB_SERIRQ +#define SW_LPC_CLKOUT0 0x00C00618 //LPC_CLKOUT0 +#define SW_LPC_CLKOUT1 0x00C00620 //LPC_CLKOUT1 +#define SW_LPC_AD0 0x00C00628 //LPC_AD0 +#define SW_LPC_AD1 0x00C00630 //LPC_AD1 +#define SW_LPC_AD2 0x00C00638 //LPC_AD2 +#define SW_LPC_AD3 0x00C00640 //LPC_AD3 +#define SW_LPC_CLKRUN 0x00C00648 //LPC_CLKRUN +#define SW_LPC_FRAMEB 0x00C00650 //LPC_FRAMEB + +#endif + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/CPU.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/CPU.asl new file mode 100644 index 0000000000..982f2475d2 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/CPU.asl @@ -0,0 +1,44 @@ +/** @file + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + // NOTE: The _PDC Implementation is out of the scope of this + // reference code. Please see the latest Hyper-Threading Technology + // Reference Code for complete implementation details. + + Scope(\_PR) + { + Processor(CPU0, // Unique name for Processor 0. + 1, // Unique ID for Processor 0. + 0x00, // CPU0 ACPI P_BLK address = ACPIBASE + 10h. + 0) // CPU0 ICH7M P_BLK length = 6 bytes. + {} + + Processor(CPU1, // Unique name for Processor 1. + 2, // Unique ID for Processor 1. + 0x00, + 0) // CPU1 P_BLK length = 6 bytes. + {} + + Processor(CPU2, // Unique name for Processor 2. + 3, // Unique ID for Processor 2. + 0x00, + 0) // CPU2 P_BLK length = 6 bytes. + {} + + Processor(CPU3, // Unique name for Processor 3. + 4, // Unique ID for Processor 3. + 0x00, + 0) // CPU3 P_BLK length = 6 bytes. + {} + } // End _PR + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/CSRT.aslc b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/CSRT.aslc new file mode 100644 index 0000000000..99d16ff017 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/CSRT.aslc @@ -0,0 +1,221 @@ +/** @file + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "acpitablePlatform.h" +#include "Csrt.h" + +// +// Debug Port Table +// +EFI_ACPI_CSRT_TABLE Csrt = +{ + { //EFI_ACPI_DESCRIPTION_HEADER Start + EFI_ACPI_4_0_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE, + sizeof(EFI_ACPI_CSRT_TABLE), + EFI_ACPI_CSRT_TABLE_REVISION, + 0, // to make sum of entire table == 0 + EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field + EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long) + EFI_ACPI_OEM_REVISION, // OEM revision + EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID + EFI_ACPI_CREATOR_REVISION // ASL compiler revision number + }, //EFI_ACPI_DESCRIPTION_HEADER End + { + // + // LPIO1 DMA RESOURCE_GROUP_INFO1 + // + { //RESOURCE_GROUP_HEADER Start + sizeof(RESOURCE_GROUP_INFO1),// sizeof(RESOURCE_GROUP_INFO) + 0x4C544E49, + 0x00000000, + 0x0004, + 0x0000, + 0x0001, + 0x0000, + sizeof(SHARED_INFO_SECTION), + { + // Shared Info Section + 0x0001, // Major Version 1 + 0x0000, // Minor Version 0 + 0x55AA55AA, // MMIO Base - Low Part + 0x00000000, // MMIO Base - High Part + 0x0000002A, // Interrupt GSI 42 + 0x02, // Interrupt Polarity + 0x00, // Interrupt Mode + 0x06, // Number of Channels + 0x20, // DMA Address Width + 0x0000, // Base Request Line + 0x0010, // Number of Handshake Signals + 0x0001000 // Maximum Block Transfer Size + }, + }, // End of Resource Group header + { + { + // Controller 0 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0001, // Resource Type + 0x20495053 // UID - SPI + }, + { + // Channel 0 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0000, // Resource Type + 0x30414843 // UID - CHA0 + }, + { + // Channel 1 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0000, // Resource Type + 0x31414843 // UID - CHA1 + }, + { + // Channel 2 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0000, // Resource Type + 0x32414843 // UID - CHA2 + }, + { + // Channel 3 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0000, // Resource Type + 0x33414843 // UID - CHA3 + }, + { + // Channel 4 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0000, // Resource Type + 0x34414843 // UID - CHA4 + }, + { + // Channel 5 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0000, // Resource Type + 0x35414843 // UID - CHA5 + } + } + }, + { + // + // LPIO2 DMA RESOURCE_GROUP_INFO2 + // + { //RESOURCE_GROUP_HEADER Start + sizeof(RESOURCE_GROUP_INFO2),// sizeof(RESOURCE_GROUP_INFO) + 0x4C544E49, + 0x00000000, + 0x0005, + 0x0000, + 0x0001, + 0x0000, + sizeof(SHARED_INFO_SECTION), + { + // Shared Info Section + 0x0001, // Major Version 1 + 0x0000, // Minor Version 0 + 0x55AA55AA, // MMIO Base - Low Part + 0x00000000, // MMIO Base - High Part + 0x0000002B, // Interrupt GSI 43 + 0x02, // Interrupt Polarity + 0x00, // Interrupt Mode + 0x08, // Number of Channels + 0x20, // DMA Address Width + 0x0010, // Base Request Line + 0x0010, // Number of Handshake Signals + 0x0001000 // Maximum Block Transfer Size + }, + }, // End of Resource Group header + { + { + // Controller 0 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0001, // Resource Type + 0x20433249 // UID - I2C + }, + { + // Channel 0 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0000, // Resource Type + 0x30414843 // UID - CHA0 + }, + { + // Channel 1 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0000, // Resource Type + 0x31414843 // UID - CHA1 + }, + { + // Channel 2 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0000, // Resource Type + 0x32414843 // UID - CHA2 + }, + { + // Channel 3 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0000, // Resource Type + 0x33414843 // UID - CHA3 + }, + { + // Channel 4 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0000, // Resource Type + 0x34414843 // UID - CHA4 + }, + { + // Channel 5 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0000, // Resource Type + 0x35414843 // UID - CHA5 + }, + { + // Channel 6 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0000, // Resource Type + 0x36414843 // UID - CHA6 + }, + { + // Channel 7 + 0x0000000C, // Resource Descriptor Length + 0x0003, // Resource Type + 0x0000, // Resource Type + 0x37414843 // UID - CHA7 + } + } + }//LPIO2 DMA RESOURCE_GROUP_INFO2 End +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from + // removing the data structure from the executable + // + return (VOID*)&Csrt; +} \ No newline at end of file diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Csrt.h b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Csrt.h new file mode 100644 index 0000000000..4802acbbb1 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Csrt.h @@ -0,0 +1,82 @@ +/** @file + The header file of CSRT. + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#define EFI_ACPI_CSRT_TABLE_REVISION 0x00000000 +#define NUMBER_RESOURCE_GROUP_INFO 1 //2 +#define MAX_NO_CHANNEL1_SUPPORTED 7 +#define MAX_NO_CHANNEL2_SUPPORTED 9 +#define NAMESPACE_STRING_MAX_LENGTH 16 + +// +// Ensure proper structure formats +// +#pragma pack (1) + + +typedef struct _SHARED_INFO_SECTION { + UINT16 MajVersion; + UINT16 MinVersion; + UINT32 MMIOLowPart; + UINT32 MMIOHighPart; + UINT32 IntGSI; + UINT8 IntPol; + UINT8 IntMode; + UINT8 NoOfCh; + UINT8 DMAAddressWidth; + UINT16 BaseReqLine; + UINT16 NoOfHandSig; + UINT32 MaxBlockTransferSize; +} SHARED_INFO_SECTION; + +typedef struct _RESOURCE_GROUP_HEADER { + UINT32 Length; + UINT32 VendorId; + UINT32 SubVendorId; + UINT16 DeviceId; + UINT16 SubDeviceId; + UINT16 Revision; + UINT16 Reserved; + UINT32 SharedInfoLength; + SHARED_INFO_SECTION SharedInfoSection; +} RESOURCE_GROUP_HEADER; + +typedef struct _RESOURCE_DESCRIPTOR { + UINT32 Length; + UINT16 ResourceType; + UINT16 ResourceSubType; + UINT32 UUID; +} RESOURCE_DESCRIPTOR; + +typedef struct { + RESOURCE_GROUP_HEADER ResourceGroupHeaderInfo; + RESOURCE_DESCRIPTOR ResourceDescriptorInfo[MAX_NO_CHANNEL1_SUPPORTED]; +} RESOURCE_GROUP_INFO1; + +typedef struct { + RESOURCE_GROUP_HEADER ResourceGroupHeaderInfo; + RESOURCE_DESCRIPTOR ResourceDescriptorInfo[MAX_NO_CHANNEL2_SUPPORTED]; +} RESOURCE_GROUP_INFO2; + +// +// DBGP structure +// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + RESOURCE_GROUP_INFO1 ResourceGroupsInfo1; + RESOURCE_GROUP_INFO2 ResourceGroupsInfo2; +} EFI_ACPI_CSRT_TABLE; + +#pragma pack () + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DBG2/DBG2.aslc b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DBG2/DBG2.aslc new file mode 100644 index 0000000000..9e6ad8023b --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DBG2/DBG2.aslc @@ -0,0 +1,77 @@ +/** @file + Debug Port Table 2 + + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "AcpiTablePlatform.h" +#include +#include + +// +// Debug Port Table +// +EFI_ACPI_DEBUG_PORT_2_TABLE Dbg2 = { + { + EFI_ACPI_5_0_DEBUG_PORT_2_TABLE_SIGNATURE, + sizeof(EFI_ACPI_DEBUG_PORT_2_TABLE), + EFI_ACPI_OEM_DBG2_TABLE_REVISION, + 0, // to make sum of entire table == 0 + EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field + EFI_ACPI_OEM_TABLE_ID_2, // OEM table identification(8 bytes long) + EFI_ACPI_OEM_REVISION, // OEM revision + EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID + EFI_ACPI_CREATOR_REVISION // ASL compiler revision number + }, + OFFSET_OF (EFI_ACPI_DEBUG_PORT_2_TABLE, DbgDeviceInfoCom1), + NUMBER_DBG_DEVICE_INFO, + // + // LPSS-UART + // + { + DEBUG_DEVICE_INFORMATION_REVISION, + sizeof(DEBUG_DEVICE_INFORMATION), + 1, // NumberOfGenericAddressRegisters + NAMESPACE_STRING_MAX_LENGTH, + OFFSET_OF (DEBUG_DEVICE_INFORMATION, NamespaceString), + 0, // OemDataLength + 0, // OemDataOffset + 0x8000, // PortType - Serial + 0x0000, // PortSubtype - 16550 compatible + 0, // Reserved + OFFSET_OF (DEBUG_DEVICE_INFORMATION, BaseAddressRegister), + OFFSET_OF (DEBUG_DEVICE_INFORMATION, AddressSize), + { + 0x00, // Address_Space_ID = 0 System Memory, 1 System IO + 0x08, // Register_Bit_Width = 8 bits + 0x00, // Register_Bit_offset + 0x00, // Access size + 0x00000000 // Base address of COM1. NOTE: Updated in AcpiPlatform. + }, + { + sizeof (EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE) + }, + ".", + } +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from + // removing the data structure from the executable + // + return (VOID*)&Dbg2; +} \ No newline at end of file diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DBGP/DBGP.aslc b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DBGP/DBGP.aslc new file mode 100644 index 0000000000..2f8dab3951 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DBGP/DBGP.aslc @@ -0,0 +1,57 @@ +/** @file + ACPI DBGP table + + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// +// Statements that include other files +// +#include "Dbgp.h" + +EFI_ACPI_DEBUG_PORT_DESCRIPTION_TABLE Dbgp = { + EFI_ACPI_3_0_DEBUG_PORT_TABLE_SIGNATURE, + sizeof (EFI_ACPI_DEBUG_PORT_DESCRIPTION_TABLE), + EFI_ACPI_DBGP_TABLE_REVISION, + 0x00, // Checksum will be updated at runtime + ' ', // OEMID 6 BYTES - It is expected that these values will be updated at runtime + ' ', // OEMID 6 BYTES - It is expected that these values will be updated at runtime + ' ', // OEMID 6 BYTES - It is expected that these values will be updated at runtime + ' ', // OEMID 6 BYTES - It is expected that these values will be updated at runtime + ' ', // OEMID 6 BYTES - It is expected that these values will be updated at runtime + ' ', // OEMID 6 BYTES - It is expected that these values will be updated at runtime + 0, // OEM TABLE ID 8 BYTES - + EFI_ACPI_OEM_DBGP_REVISION, // OEM REVISION + 0, // CREATOR ID + 0, // CREATOR REVISION + 0, // Interfacetype, 0 = full 16550 interface + {0}, // Reserved 3 bytes, must be 0. + { + 0, + 0x08, // RegisterBitWidth + 0, // RegisterBitOffset + 0x00, + 0x00 + } // Base address. Put actual value later. +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from removing the + // data structure from the exeutable + // + return (VOID*)&Dbgp; +} \ No newline at end of file diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DSDT.ASL b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DSDT.ASL new file mode 100644 index 0000000000..49b018c536 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DSDT.ASL @@ -0,0 +1,95 @@ +/** @file + ACPI DSDT table + + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +DefinitionBlock ( + "DSDT.aml", + "DSDT", + 0x02, // DSDT revision. + // A Revision field value greater than or equal to 2 signifies that integers + // Declared within the Definition Block are to be evaluated as 64-bit values + "INTEL", // OEM ID (6 byte string) + "BXT-SOC", // OEM table ID (8 byte string) + 0x0 // OEM version of DSDT table (4 byte Integer) + ) + +{ + External(\_SB.PCI0.GFX0, DeviceObj) +// Miscellaneous services enabled in Project + include ("token.asl") + Include ("AMLUPD.asl") + include ("GloblNvs.asl") + include ("PciTree.asl") + include ("Sc.asl") + include ("LpcB.asl") + include ("Bxt.asl") + include ("CPU.asl") + include ("Platform.asl") + include ("THERMAL.ASL") + include ("PCI_DRC.ASL") + include ("Video.asl") + Include ("PcieRpPxsxWrapper.asl") + include ("Pep/Pep.asl") + include ("Gpe.asl") //Need this for xHCI D3 wake flow. + + if (LEqual(ECR1,1)) { + Scope(\_SB.PCI0) { + // + // PCI-specific method's GUID + // + Name(PCIG, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D")) + Method(PCID, 4, Serialized) { + If (LEqual(Arg0, PCIG)) { // PCIE capabilities UUID + If (LGreaterEqual(Arg1,3)) { // revision at least 3 + If (LEqual(Arg2,0)) { Return (Buffer(2){0x01,0x03}) } // function 0: list of supported functions + If (LEqual(Arg2,8)) { Return (1) } // function 8: Avoiding Power-On Reset Delay Duplication on Sx Resume + If (LEqual(Arg2,9)) { Return (Package(5){50000,Ones,Ones,50000,Ones}) } // function 9: Specifying Device Readiness Durations + } + } + return (Buffer(1){0}) + } + } //scope + } //if + + Scope(\_SB.PCI0) { + //PciCheck, Arg0=UUID, returns true if support for 'PCI delays optimization ECR' is enabled and the UUID is correct + Method(PCIC,1,Serialized) { + If (LEqual(ECR1,1)) { + If (LEqual(Arg0, PCIG)) { + return (1) + } + } + return (0) + } + } + +// Sleep states supported by Chipset/Board. +//---------------------------------------------------------------------- +// SSx - BIOS setup controlled enabled _Sx Sleep state status +// Values to be written to SLP_TYPE register are provided by SBACPI.SDL (South Bridge ACPI ModulePart) + + Name(\_S0, Package(4) {0x0,0x0,0,0}) // mandatory System state + if (SS1) {Name(\_S1, Package(4) {0x1,0x0,0,0})} + if (SS3) {Name(\_S3, Package(4) {0x5,0x0,0,0})} + if (SS4) {Name(\_S4, Package(4) {0x6,0x0,0,0})} + Name(\_S5, Package(4) {0x7,0x0,0,0}) // mandatory System state + + Method(PTS, 1) { // METHOD CALLED FROM _PTS PRIOR TO ENTER ANY SLEEP STATE + If (Arg0) { + // entering any sleep state + } + } + Method(WAK, 1) { // METHOD CALLED FROM _WAK RIGHT AFTER WAKE UP + } +}// End of ASL File diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Dmar/Dmar.aslc b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Dmar/Dmar.aslc new file mode 100644 index 0000000000..98ffab2c86 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Dmar/Dmar.aslc @@ -0,0 +1,188 @@ +/** @file + ACPI DMA address Remapping table + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "Dmar.h" + +EFI_ACPI_DMAR_TABLE DmarTable = { + + EFI_ACPI_VTD_DMAR_TABLE_SIGNATURE, + sizeof (EFI_ACPI_DMAR_TABLE), + EFI_ACPI_DMAR_TABLE_REVISION, + + // + // Checksum will be updated at runtime + // + 0x00, + + // + // It is expected that these values will be programmed at runtime + // + 'I', 'N', 'T', 'E', 'L', ' ', + EFI_ACPI_DMAR_OEM_TABLE_ID, + 0x1, + EFI_ACPI_DMAR_OEM_CREATOR_ID, + 1, + + // + // DMAR table specific entries below: + // + + // + // 39-bit addressing Host Address Width + // + 38, + + // + // Flags + // + 0, + + // + // Reserved fields + // + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + // + // First DRHD structure, VT-d Engine #1 + // + { + 0, // Type = 0 (DRHD) + sizeof (EFI_ACPI_DRHD_ENGINE1_STRUCT), // Length of structure + 0, // Flag - Do not include all - bugbug - not clear what this means + 0, // Reserved fields + 0, // Segment + 0x00000000, // Base address of DMA-remapping hardware - Updated at boot time + + // + // Device Scopes + // + { + 1, // Type + sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length + 0, // Segment number + 0, // Reserved + 0, // Start bus number + {2, 0} // PCI path + } + }, + + //Second DRHD structure VT-d Engine# 2 + { + 0, // Type = 0 (DRHD) + sizeof(EFI_ACPI_DRHD_ENGINE2_STRUCT), // Length of strucure. + 1, // Flag - Include all + 0, // Reserved + 0, // Segment Number + 0x00000000, // Base address of DMA-remapping hardware. + + { + // + // Device Scopes + // + { + 3, // Type=IO APIC + sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length + 0, // Reserved + 1, // Enumeration ID + 0xFA, // Start bus number + {31, 0} // PCI path + }, + // + // Device Scopes + // + { + 4, // Type=HPET + sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length + 0, // Reserved + 0, // Enumeration ID + 0xFA, // Start bus number + {15, 0} // PCI path + } + } + }, + + //RMRR structure for USB devices. + { + 0x1, // Type 1 - RMRR structure + sizeof(EFI_ACPI_RMRR_USB_STRUC), // Length + 0x0000, // Reserved + 0x0000, // Segment Num + 0x0000000000000000, // RMRR Base address - Updated in runtime. + 0x0000000000000000, // RMRR Limit address - Updated in runtime. + { + { + 1, // Type + sizeof(EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length + 0, // Reserved + 0, // Enum ID + 0, // Start bus number + {21, 0} // PCI path + }, + { + 1, // Type + sizeof(EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length + 0, // Reserved + 0, // Enum ID + 0, // Start bus number + {21, 1} // PCI path + } + } + }, + + //RMRR structure for IGD device. + { + 1, // Type 1 - RMRR structure + sizeof(EFI_ACPI_RMRR_IGD_STRUC), // Length + 0x0000, // Reserved + 0x0000, // Segment Num + 0x0000000000000000, // RMRR Base address - Updated in runtime. + 0x0000000000000000, // RMRR Limit address - Updated in runtime. + { + { + 1, // Type + sizeof(EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length + 0, // Reserved + 0, // Enum ID + 0, // Start bus number + {2, 0} // PCI path + } + } + } +}; + +// +// Dummy function required for build tools +// +#if defined (__GNUC__) +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from removing the + // data structure from the executable + // + return (VOID*)&DmarTable; +} +#else +int +main ( + VOID + ) +{ + return 0; +} +#endif \ No newline at end of file diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Dmar/Dmar.h b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Dmar/Dmar.h new file mode 100644 index 0000000000..558a96408e --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Dmar/Dmar.h @@ -0,0 +1,33 @@ +/** @file + This file describes the contents of the ACPI DMA address Remapping + Some additional ACPI values are defined in Acpi1_0.h and Acpi2_0.h. + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SA_DMAR_H_ +#define _SA_DMAR_H_ + +/// +/// Include standard ACPI table definitions +/// +#include +#include + +#pragma pack(1) + +#define EFI_ACPI_DMAR_OEM_TABLE_ID 0x20574442 ///< "BDW " +#define EFI_ACPI_DMAR_OEM_CREATOR_ID 0x4C544E49 ///< "INTL" +#pragma pack() + +#endif + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Art.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Art.asl new file mode 100644 index 0000000000..7e858d4cc9 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Art.asl @@ -0,0 +1,46 @@ +/** @file + ACPI Active Cooling Relationship Table + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(\_SB.IETM) +{ + // _ART (Active Cooling Relationship Table) + // + // Arguments: + // None + // Return Value: + // A variable-length Package containing a Revision ID and a list of Active Relationship Packages as described below: + // + // Return Value Information + // Package { + // Revision, // Integer - Current revision is: 0 + // ActiveRelationship[0] // Package + // ... + // ActiveRelationship[n] // Package + // } + // + Name(_ART, Package() + { + 0, // Revision + // Source Target Weight, AC0MaxLevel, AC1MaxLevel, AC2MaxLevel, AC3MaxLevel, AC4MaxLevel, AC5MaxLevel, AC6MaxLevel, AC7MaxLevel, AC8MaxLevel, AC9MaxLevel + Package(){\_SB.TFN1, \_SB.PCI0.TCPU, 100, 100, 80, 50, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + Package(){\_SB.TFN1, \_SB.SEN1, 100, 100, 80, 50, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + Package(){\_SB.TFN1, \_SB.GEN1, 100, 100, 80, 50, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + Package(){\_SB.TFN1, \_SB.GEN2, 100, 100, 80, 50, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + Package(){\_SB.TFN1, \_SB.GEN3, 100, 100, 80, 50, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + Package(){\_SB.TFN1, \_SB.GEN4, 100, 100, 80, 50, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF} + }) + +} // End of Scope \_SB.IETM + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/BiosDataVault.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/BiosDataVault.asl new file mode 100644 index 0000000000..adbd8a186b --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/BiosDataVault.asl @@ -0,0 +1,15 @@ +/** @file + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +0xE5,0x1F,0x0C,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00 + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/DPLYParticipant.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/DPLYParticipant.asl new file mode 100644 index 0000000000..8519ffe30a --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/DPLYParticipant.asl @@ -0,0 +1,155 @@ +/** @file + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(\_SB) +{ + Device(TDSP) + { + Name(_HID, EISAID("INT3406")) // Intel DPTF Display Device + Name(_UID, "DPLY") + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If(LEqual(\DDSP,0)){ + Return(0x00) + } + Return(0x0F) + } + + // DDDL (DPTF Display Depth Limit) + // + // The DDDL object indicates dynamically a lower limit on the brightness control levels currently supported by the platform + // for the participant. Value returned must be a Percentage value that is in the _BCL brightness list. + // + // Arguments: (0) + // None + // Return Value: + // Brightness Display Depth Limit in percent + // + Method(DDDL) + { + Return(30) // 30% - This value must appear in the _BCL package + } + + // DDPC ( DPTF Display Power/Performance Control) + // + // The DDPC object indicates dynamically a higher limit (ceiling) on the brightness control levels currently supported by + // the platform for the participant. Value returned must be a Percentage value that is in the _BCL brightness list. + // + // Arguments: (0) + // None + // Return Value: + // Display Power/Performance Control in percent + // + Method(DDPC) + { + Return(80) // 80% - This value must appear in the _BCL package + } + + // _BCL (Query List of Brightness Control Levels Supported) + // + // Arguments: (0) + // None + // Return Value: + // A variable-length Package containing a list of integers representing the supported brightness + // levels. Each integer has 8 bits of significant dat + // Notes: + // List of supported brightness levels in the following sequence: + // Level when machine has full power. + // Level when machine is on batteries. + // Other supported levels. + // + Method(_BCL,,,,PkgObj) + { + Return(Package(){80, 50, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70, 75, 80, 85, 90, 95, 100}) + } + + // _BCM (Set the Brightness Level) + // + // Arguments: (1) + // Arg0 - An Integer containing the new brightness level + // Return Value: + // None + // + Method(_BCM,1) + { + If(CondRefOf(\_SB.PCI0.GFX0.DD1F._BCM)) + { + \_SB.PCI0.GFX0.DD1F._BCM(Arg0) // call the core Graphics method + } + } + + // _BQC (Brightness Query Current level) + // + // This method returns the current brightness level of a built-in display output device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the current brightness level (must be one of the values returned from the + // _BCL method) + // + Method(_BQC,0) + { + If(CondRefOf(\_SB.PCI0.GFX0.DD1F._BQC)) + { + Return(\_SB.PCI0.GFX0.DD1F._BQC()) // call the core Graphics method + } Else { + Return(0x00) + } + } + + // _DCS (Return the Status of Output Device) + // + // This method is required if hotkey display switching is supported. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the device status (32 bits) + // Bit Definitions: + // [0] - Output connector exists in the system now + // [1] - Output is activated + // [2] - Output is ready to switch + // [3] - Output is not defective (it is functioning properly) + // [4] - Device is attached (this is optional) + // [31:5] Reserved (must be zero) + // + Method(_DCS,0) + { + If(CondRefOf(\_SB.PCI0.GFX0.DD1F._DCS)) + { + Return(\_SB.PCI0.GFX0.DD1F._DCS()) // call the core Graphics method + } Else { + Return(0x00) + } + } + + } // End TDSP Device +}// end Scope(\_SB) + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Dppm.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Dppm.asl new file mode 100644 index 0000000000..d85f776118 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Dppm.asl @@ -0,0 +1,63 @@ +/** @file + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(\_SB.IETM) +{ + // + // DPPM Passive Policy 2.0 + // + Name (DP2P, Package () + { + ToUUID("9E04115A-AE87-4D1C-9500-0F3E340BFE75") + }) + + // + // DPPM Passive Policy 1.0 + // + Name (DPSP, Package () + { + ToUUID("42A441D6-AE6A-462B-A84B-4A8CE79027D3") + }) + + // DPPM Active Policy + // + Name (DASP, Package () + { + ToUUID("3A95C389-E4B8-4629-A526-C52C88626BAE") + }) + + // + // DPPM Crtical Policy + // + Name (DCSP, Package() + { + ToUUID("97C68AE7-15FA-499c-B8C9-5DA81D606E0A") + }) + + // + // Power Boss Policy + // + Name (POBP, Package () + { + ToUUID("F5A35014-C209-46A4-993A-EB56DE7530A1") + }) + + // + // Virtual Sensor Policy + // + Name (DVSP, Package () + { + ToUUID("6ED722A7-9240-48a5-B479-31EEF723D7CF") + }) +} + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Dptf.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Dptf.asl new file mode 100644 index 0000000000..6cedff40e3 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Dptf.asl @@ -0,0 +1,641 @@ +/** @file + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +DefinitionBlock ( + "Dptf.aml", + "SSDT", + 2, + "DptfTab", + "DptfTab", + 0x1000 + ) +{ + External(\P8XH, MethodObj) + External(\ECON, IntObj) + External(\OSSL, IntObj) + External(\PSVT, IntObj) + External(\CRTT, IntObj) + External(\ACTT, IntObj) + External(\PWRS, IntObj) + + External(\_TZ.ETMD, IntObj) + External(\_TZ.TZ01, ThermalZoneObj) + External(\_TZ.LEGA, IntObj) + External(\_TZ.LEGP, IntObj) + External(\_TZ.LEGC, IntObj) + + External(\_PR.CPU0, DeviceObj) + External(\_PR.CPU1, DeviceObj) + External(\_PR.CPU2, DeviceObj) + External(\_PR.CPU3, DeviceObj) + + External(\DPTE, IntObj) // DptfEnable + External(\DCFE, IntObj) // EnableDCFG + + External(\DPSR, IntObj) // DptfProcessor + External(\DPCT, IntObj) // DptfProcCriticalTemperature + External(\DPPT, IntObj) // DptfProcPassiveTemperature + External(\DPAT, IntObj) // DptfProcActiveTemperature + External(\DPC3, IntObj) // DptfProcCriticalTemperatureS3 + External(\DPHT, IntObj) // DptfProcHotThermalTripPoint + External(\CPUS, IntObj) // ThermalSamplingPeriodTCPU + + External(\DDSP, IntObj) // DptfDisplayDevice + + External(\S1DE, IntObj) // EnableSen1Participant + External(\S1AT, IntObj) // ActiveThermalTripPointSen1 + External(\S1PT, IntObj) // PassiveThermalTripPointSen1 + External(\S1CT, IntObj) // CriticalThermalTripPointSen1 + External(\S1S3, IntObj) // CriticalThermalTripPointSen1S3 + External(\S1HT, IntObj) // HotThermalTripPointSen1 + External(\SSP1, IntObj) // SensorSamplingPeriodSen1 + + External(\GN1E, IntObj) // EnableGen1Participant + External(\G1AT, IntObj) // ActiveThermalTripPointGen1 + External(\G1PT, IntObj) // PassiveThermalTripPointGen1 + External(\G1CT, IntObj) // CriticalThermalTripPointGen1 + External(\G1C3, IntObj) // CriticalThermalTripPointGen1S3 + External(\G1HT, IntObj) // HotThermalTripPointGen1 + External(\TSP1, IntObj) // ThermistorSamplingPeriodGen1 + + External(\GN2E, IntObj) // EnableGen2Participant + External(\G2AT, IntObj) // ActiveThermalTripPointGen2 + External(\G2PT, IntObj) // PassiveThermalTripPointGen2 + External(\G2CT, IntObj) // CriticalThermalTripPointGen2 + External(\G2C3, IntObj) // CriticalThermalTripPointGen2S3 + External(\G2HT, IntObj) // HotThermalTripPointGen2 + External(\TSP2, IntObj) // ThermistorSamplingPeriodGen2 + + External(\GN3E, IntObj) // EnableGen3Participant + External(\G3AT, IntObj) // ActiveThermalTripPointGen3 + External(\G3PT, IntObj) // PassiveThermalTripPointGen3 + External(\G3CT, IntObj) // CriticalThermalTripPointGen3 + External(\G3C3, IntObj) // CriticalThermalTripPointGen3S3 + External(\G3HT, IntObj) // HotThermalTripPointGen3 + External(\TSP3, IntObj) // ThermistorSamplingPeriodGen3 + + External(\GN4E, IntObj) // EnableGen4Participant + External(\G4AT, IntObj) // ActiveThermalTripPointGen4 + External(\G4PT, IntObj) // PassiveThermalTripPointGen4 + External(\G4CT, IntObj) // CriticalThermalTripPointGen4 + External(\G4C3, IntObj) // CriticalThermalTripPointGen4S3 + External(\G4HT, IntObj) // HotThermalTripPointGen4 + External(\TSP4, IntObj) // ThermistorSamplingPeriodGen4 + + External(\VSP1, IntObj) // EnableVS1Participant + External(\V1AT, IntObj) // ActiveThermalTripPointVS1 + External(\V1PV, IntObj) // PassiveThermalTripPointVS1 + External(\V1CR, IntObj) // CriticalThermalTripPointVS1 + External(\V1C3, IntObj) // CriticalThermalTripPointVS1S3 + External(\V1HT, IntObj) // HotThermalTripPointVS1 + + External(\VSP2, IntObj) // EnableVS2Participant + External(\V2AT, IntObj) // ActiveThermalTripPointVS2 + External(\V2PV, IntObj) // PassiveThermalTripPointVS2 + External(\V2CR, IntObj) // CriticalThermalTripPointVS2 + External(\V2C3, IntObj) // CriticalThermalTripPointVS2S3 + External(\V2HT, IntObj) // HotThermalTripPointVS2 + + External(\VSP3, IntObj) // EnableVS3Participant + External(\V3AT, IntObj) // ActiveThermalTripPointVS3 + External(\V3PV, IntObj) // PassiveThermalTripPointVS3 + External(\V3CR, IntObj) // CriticalThermalTripPointVS3 + External(\V3C3, IntObj) // CriticalThermalTripPointVS3S3 + External(\V3HT, IntObj) // HotThermalTripPointVS3 + + External(\DPAP, IntObj) // EnableActivePolicy + External(\DPPP, IntObj) // EnablePassivePolicy + External(\TRTV, IntObj) // TrtRevision + External(\DPCP, IntObj) // EnableCriticalPolicy + External(\PBPE, IntObj) // EnablePowerBossPolicy + External(\VSPE, IntObj) // EnableVSPolicy + + External(\DFAN, IntObj) // DptfFanDevice + External(\CHGE, IntObj) // DptfChargerDevice + External(\PWRE, IntObj) // EnablePowerParticipant + External(\PPPR, IntObj) // PowerParticipantPollingRate + + External(\ODV0, IntObj) // OemDesignVariable0 + External(\ODV1, IntObj) // OemDesignVariable1 + External(\ODV2, IntObj) // OemDesignVariable2 + External(\ODV3, IntObj) // OemDesignVariable3 + External(\ODV4, IntObj) // OemDesignVariable4 + External(\ODV5, IntObj) // OemDesignVariable5 + + External(\_SB.PCI0, DeviceObj) + External(\_SB.PCI0.VLVC.MHBR, FieldUnitObj) + + + External(\_PR.CPU0._PSS, MethodObj) + External(\_PR.CPU0.NPSS, PkgObj) + External(\_PR.CPU0.SPSS, PkgObj) + External(\_PR.CPU0._PPC, IntObj) + External(\_PR.CPU0._TSS, MethodObj) + External(\_PR.CPU0._PTC, MethodObj) + External(\_PR.CPU0._TSD, MethodObj) + External(\_PR.CPU0._TPC, IntObj) + External(\_PR.CPU0._TDL, MethodObj) + + External(\_SB.PCI0.GFX0, DeviceObj) + External(\_SB.PCI0.GFX0.DD1F, DeviceObj) + External(\_SB.PCI0.GFX0.DD1F._BCM, MethodObj) + External(\_SB.PCI0.GFX0.DD1F._BQC, MethodObj) + External(\_SB.PCI0.GFX0.DD1F._DCS, MethodObj) + +Scope(\_SB) +{ + // + // DPTF Thermal Zone Device + // + Device(IETM){ + // + // Intel DPTF Thermal Framework Device + // + Name(_HID, EISAID("INT3400")) + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (LEqual(\DPTE,1)) { + Return(0x0F) + } Else { + Return(0x00) + } + } + + // + // Note: the number of GUID package elements in TMPP must be equal or greater than the number + // of store statements in IDSP in order to prevent an overrun. + // + Name(TMPP,Package() + { + ToUUID("00000000-0000-0000-0000-000000000000"), + ToUUID("00000000-0000-0000-0000-000000000000"), + ToUUID("00000000-0000-0000-0000-000000000000"), + ToUUID("00000000-0000-0000-0000-000000000000"), + ToUUID("00000000-0000-0000-0000-000000000000") + }) + + // IDSP (Intel DPTF Supported Policies) + // + // This object evaluates to a package of packages, with each package containing the UUID + // values to represent a policy implemented and supported by the Intel DPTF software stack. + // + // Arguments: (0) + // None + // Return Value: + // Package of Guid packages + // + Method(IDSP,0,Serialized,,PkgObj) + { + Name(TMPI,0) + + // Passive Policy 2.0 GUID + If (LAnd(LEqual(\DPPP,2),CondRefOf(DP2P))) { + Store(DeRefOf(Index(DP2P,0)), Index(TMPP,TMPI)) + Increment(TMPI) + } + + // Passive Policy 1.0 GUID + If (LAnd(LEqual(\DPPP,1),CondRefOf(DPSP))) { + Store(DeRefOf(Index(DPSP,0)), Index(TMPP,TMPI)) + Increment(TMPI) + } + + // Active Policy GUID + If (LAnd(LEqual(\DPAP,1),CondRefOf(DASP))) { + Store(DeRefOf(Index(DASP,0)), Index(TMPP,TMPI)) + Increment(TMPI) + } + + // Critical Policy GUID + If (LAnd(LEqual(\DPCP,1),CondRefOf(DCSP))) { + Store(DeRefOf(Index(DCSP,0)), Index(TMPP,TMPI)) + Increment(TMPI) + } + + // Power Boss Policy GUID + If (LAnd(LEqual(\PBPE,1),CondRefOf(POBP))) { + Store(DeRefOf(Index(POBP,0)), Index(TMPP,TMPI)) + Increment(TMPI) + } + + // Virtual Sensor Policy GUID + If (LAnd(LEqual(\VSPE,1),CondRefOf(DVSP))) { + Store(DeRefOf(Index(DVSP,0)), Index(TMPP,TMPI)) + Increment(TMPI) + } + + Return(TMPP) + } + + // + // Save original trip points so _OSC method can enable/disable Legacy thermal policies by manipulating trip points. + // + Name (PTRP,0) // Passive trip point + Name (PSEM,0) // Passive semaphore + Name (ATRP,0) // Active trip point + Name (ASEM,0) // Active semaphore + Name (YTRP,0) // Critical trip point + Name (YSEM,0) // Critical semaphore + + // _OSC (Operating System Capabilities) + // + // This object is evaluated by each DPTF policy implementation to communicate to the platform of the existence and/or control transfer. + // + // Arguments: (4) + // Arg0 - A Buffer containing a UUID + // Arg1 - An Integer containing a Revision ID of the buffer format + // Arg2 - An Integer containing a count of entries in Arg3 + // Arg3 - A Buffer containing a list of DWORD capabilities + // Return Value: + // A Buffer containing a list of capabilities + // + Method(_OSC, 4,Serialized,,BuffObj,{BuffObj,IntObj,IntObj,BuffObj}) + { + Name (NUMP,0) + Name (UID2,ToUUID("FFFFFFFF-FFFF-FFFF-FFFF-FFFFFFFFFFFF")) + + // Point to Status DWORD in the Arg3 buffer (STATUS) + CreateDWordField(Arg3, 0, STS1) + + // Point to Caps DWORDs of the Arg3 buffer (CAPABILITIES) + CreateDWordField(Arg3, 4, CAP1) + + // + // _OSC needs to validate the UUID and Revision. + // + // IF Unrecognized UUID + // Return Unrecognized UUID _OSC Failure + // IF Unsupported Revision + // Return Unsupported Revision _OSC Failure + // + // STS0[0] = Reserved + // STS0[1] = _OSC Failure + // STS0[2] = Unrecognized UUID + // STS0[3] = Unsupported Revision + // STS0[4] = Capabilities masked + // + // Get the platform UUID's that are available, this will be a package of packages. + // + IDSP() // initialize TMPP with GUID's + Store(SizeOf(TMPP),NUMP) // how many GUID's in the package? + + // Note: The comparison method used is necessary due to + // limitations of certain OSes which cannot perform direct + // buffer comparisons. + // + // Create a set of "Input" UUID fields. + // + CreateDWordField(Arg0, 0x0, IID0) + CreateDWordField(Arg0, 0x4, IID1) + CreateDWordField(Arg0, 0x8, IID2) + CreateDWordField(Arg0, 0xC, IID3) + // + // Create a set of "Expected" UUID fields. + // + CreateDWordField(UID2, 0x0, EID0) + CreateDWordField(UID2, 0x4, EID1) + CreateDWordField(UID2, 0x8, EID2) + CreateDWordField(UID2, 0xC, EID3) + // + // Compare the input UUID to the list of UUID's in the system. + // + While(NUMP){ + // + // copy one uuid from TMPP to UID2 + // + Store(DeRefOf (Index (TMPP, Subtract(NUMP,1))),UID2) + // + // Verify the input UUID matches the expected UUID. + // + If (LAnd(LAnd(LEqual(IID0, EID0), LEqual(IID1, EID1)), LAnd(LEqual(IID2, EID2), LEqual(IID3, EID3)))) { + Break // break out of while loop when matching UUID is found + } + Decrement(NUMP) + } + + If (LEqual(NUMP,0)) { + // + // Return Unrecognized UUID _OSC Failure + // + And(STS1,0xFFFFFF00,STS1) + Or(STS1,0x6,STS1) + Return(Arg3) + } + + If (LNot(LEqual(Arg1, 1))) + { + // + // Return Unsupported Revision _OSC Failure + // + And(STS1,0xFFFFFF00,STS1) + Or(STS1,0xA,STS1) + Return(Arg3) + } + + If (LNot(LEqual(Arg2, 2))) + { + // + // Return Argument 3 Buffer Count not sufficient + // + And(STS1,0xFFFFFF00,STS1) + Or(STS1,0x2,STS1) + Return(Arg3) + } + + // + // Passive Policy 2.0 GUID + // + If (CondRefOf(\PSVT)) { + If (LEqual(PSEM,0)) { + Store(1,PSEM) // use semaphore so variable is only initialized once + Store(\PSVT,PTRP) // save trip point in case we have to restore it + } + // + // copy the GUID to UID2 + // + If (CondRefOf(DP2P)) { + Store(DeRefOf (Index (DP2P, 0)),UID2) + } + // + // Verify the test UUID matches the input UUID. + // + If (LAnd(LAnd(LEqual(IID0, EID0), LEqual(IID1, EID1)), LAnd(LEqual(IID2, EID2), LEqual(IID3, EID3)))) { + // do passive notify + If(Not(And(STS1, 0x01))) // Test Query Flag + { // Not a query operation, so process the request + If (And(CAP1, 0x01)) { + // Enable DPTF + // Nullify the legacy thermal zone. + Store(110,\PSVT) // spoof legacy trip point with high value + Store(0, \_TZ.LEGP) // disable legacy thermal management + } Else { // policy unloading, re-enable legacy thermal zone + Store(PTRP,\PSVT) // restore passive value + Store(1, \_TZ.LEGP) // enable legacy thermal management + } + // Send notification to legacy thermal zone for legacy policy to be enabled/disabled + Notify (\_TZ.TZ01, 0x81) + } + Return (Arg3) + } + } + + // + // Active Policy GUID + // + If (CondRefOf(\ACTT)) { + If (LEqual(ASEM,0)) { + Store(1,ASEM) // use semaphore so variable is only initialized once + Store(\ACTT,ATRP) // save trip point in case we have to restore it + } + // + // copy the GUID to UID2 + // + If (CondRefOf(DASP)) { + Store(DeRefOf (Index (DASP, 0)),UID2) + } + // + // Verify the test UUID matches the input UUID. + // + If (LAnd(LAnd(LEqual(IID0, EID0), LEqual(IID1, EID1)), LAnd(LEqual(IID2, EID2), LEqual(IID3, EID3)))) { + // do active notify + If (Not(And(STS1, 0x01))) { + // Test Query Flag + // Not a query operation, so process the request + If(And(CAP1, 0x01)) { + // Enable DPTF + // Nullify the legacy thermal zone. + Store(110,\ACTT) // spoof legacy trip point with high value + Store(0, \_TZ.LEGA) // disable legacy thermal management + } Else { // policy unloading, re-enable legacy thermal zone + Store(ATRP,\ACTT) // restore legacy value + Store(1, \_TZ.LEGA) // enable legacy thermal management + } + // Send notification to legacy thermal zone for legacy policy to be enabled/disabled + Notify(\_TZ.TZ01, 0x81) + } + Return(Arg3) + } + } + + // + // Critical Policy GUID + // + If (CondRefOf(\CRTT)) { + If (LEqual(YSEM,0)) { + Store(1,YSEM) // use semaphore so variable is only initialized once + Store(\CRTT,YTRP) // save trip point in case we have to restore it + } + // + // copy the GUID to UID2 + // + If (CondRefOf(DCSP)) { + Store(DeRefOf (Index (DCSP, 0)),UID2) + } + // + // Verify the test UUID matches the input UUID. + // + If (LAnd(LAnd(LEqual(IID0, EID0), LEqual(IID1, EID1)), LAnd(LEqual(IID2, EID2), LEqual(IID3, EID3)))) { + // do critical notify + If (Not(And(STS1, 0x01))) { + // Test Query Flag + // Not a query operation, so process the request + If (And(CAP1, 0x01)) { + // Enable DPTF + // Nullify the legacy thermal zone. + Store(210,\CRTT) // spoof legacy trip point with high value + Store(0, \_TZ.LEGC) // disable legacy thermal management + } Else { // policy unloading, re-enable legacy thermal zone + Store(YTRP,\CRTT) // restore legacy value + Store(1, \_TZ.LEGC) // enable legacy thermal management + } + // Send notification to legacy thermal zone for legacy policy to be enabled/disabled + Notify(\_TZ.TZ01, 0x81) + } + Return(Arg3) + } + } + + Return(Arg3) + } // _OSC + + // KTOC (Kelvin to Celsius) + // + // This control method converts from 10ths of degree Kelvin to Celsius. + // + // Arguments: (1) + // Arg0 - Temperature in 10ths of degree Kelvin + // Return Value: + // Temperature in Celsius + // + Method(KTOC,1,Serialized) + { + If (LGreater(Arg0,2732)) { // make sure we have a temperature above zero Celcius + Return(Divide(Subtract(Arg0,2732),10)) + } Else { + Return(0) // negative temperatures Celcius are changed to 0 degrees Celcius + } + } + + // CTOK (Celsius to Kelvin) + // + // This control method converts from Celsius to 10ths of degree Kelvin. + // + // Arguments: (1) + // Arg0 - Temperature in Celsius + // Return Value: + // Temperature in 10ths of degree Kelvin + // + Method(CTOK,1,Serialized) + { + Return(Add(Multiply(Arg0,10),2732)) + } + + // DCFG (DPTF Configuration) + // + // Returns a DWORD data representing the desired behavior of DPTF besides supported DSP and participants. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the DPTF Configuration bitmap: + // Bit 0 = Generic UI Access Control (0 - enable as default, 1 - disable access) + // Bit 1 = Restricted UI Access Control ( 0 - enable as default, 1 - disable access ) + // Bit 2 = Shell Access Control ( 0 - enable as default, 1 - disable access) + // Bit 3 = Environment Monitoring Report Control ( 0 - report is allowed as default, 1 - No environmental monitoring report to Microsoft ) + // Bit 4 = Thermal Mitigation Report Control ( 0 - No mitigation report to Microsoft as default, 1 - report is allowed) + // Bit 5 = Thermal Policy Report Control ( 0 - No policy report to Microsoft as default, 1 - report is allowed) + // Bits[31:6] - Reserved (must be cleared). + // + Method(DCFG) + { + Return(\DCFE) + } + + // ODVP (Oem Design Variables Package) + // + // Variables for OEM's to customize DPTF behavior based on platform changes. + // + Name(ODVX,Package(){0,0,0,0,0,0}) + + // ODVP (Oem Design Variables Package) + // + // Variables for OEM's to customize DPTF behavior based on platform changes. + // + // Arguments: (0) + // None + // Return Value: + // Package of integers + // + Method(ODVP,0,Serialized,,PkgObj) + { + Store(\ODV0,Index(ODVX,0)) + Store(\ODV1,Index(ODVX,1)) + Store(\ODV2,Index(ODVX,2)) + Store(\ODV3,Index(ODVX,3)) + Store(\ODV4,Index(ODVX,4)) + Store(\ODV5,Index(ODVX,5)) + Return(ODVX) + } + + } // End IETM Device +} // End \_SB Scope + + + + +// +// CPU Participant +// +Include("TCPUParticipant.asl") + +Include("DPLYParticipant.asl") + +// +// Participants using motherboard sensors. +// +Include("SEN1Participant.asl") + +// +// Fan participant. +// +Include("TFN1Participant.asl") + +// +// Participants using device sensors. +// +Include("TPWRParticipant.asl") + +// +// Participants using motherboard thermistors. +// +Include("Gen1Participant.asl") +Include("Gen2Participant.asl") +Include("Gen3Participant.asl") +Include("Gen4Participant.asl") + +// +// Policy support files +// +Include("Art.asl") +Include("Trt.asl") +Include("Psvt.asl") +Include("Dppm.asl") + +// +// Participants using virtual sensors. +// +Include("Vir1Participant.asl") +Include("Vir2Participant.asl") +Include("Vir3Participant.asl") + +Scope(\_SB.IETM) +{ + // GDDV (Get Dptf Data Vault) + // + // The data vault can contain APCT, APAT, and PSVT tables. + // + // Arguments: (0) + // None + // Return Value: + // A package containing the data vault + // + Method(GDDV,0,Serialized,0,PkgObj) + { + Return(Package() + { + Buffer() + { + Include("BiosDataVault.asl") // empty data vault for documentation purposes + } + }) + } +} // End Scope(\_SB.IETM) + +} // End SSDT + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Gen1Participant.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Gen1Participant.asl new file mode 100644 index 0000000000..290a11fb77 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Gen1Participant.asl @@ -0,0 +1,349 @@ +/** @file + Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(\_SB) +{ + Device(GEN1) // Generic participant + { + Name(_HID, EISAID("INT3403")) + Name(_UID, "GEN1") + Name(_STR, Unicode ("Thermistor 1 CPU_VR_RT5D1")) + Name(PTYP, 0x12) + + Name(FAUX, 0) + Name(SAUX, 0) + Name(CTYP,0) // Mode + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (\GN1E) { + Return(0x0F) + } Else { + Return(0x00) + } + } + + // _TMP (Temperature) + // + // This control method returns the thermal zone's current operating temperature. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the current temperature of the thermal zone (in tenths of degrees Kelvin) + // + Method(_TMP,0,Serialized) + { + + Return(3000) // degrees kelvin + + } + + // Returns Number of Aux Trips available + Name(PATC, 2) + + // PATx (Participant Programmable Auxiliary Trip) - Sets Aux Trip Point + // + // The PATx objects shall take a single integer parameter, in tenths of degree Kelvin, which + // represents the temperature at which the device should notify the participant driver of + // an auxiliary trip event. A PATx control method returns no value. + // + // Arguments: (1) + // Arg0 - temperature in tenths of degree Kelvin + // Return Value: + // None + // + Method(PAT0,1,Serialized) // send Arg0 to EC as Programmable Auxiliary Trip Point 0 + { + + } + + // PATx (Participant Programmable Auxiliary Trip) - Sets Aux Trip Point + // + // The PATx objects shall take a single integer parameter, in tenths of degree Kelvin, which + // represents the temperature at which the device should notify the participant driver of + // an auxiliary trip event. A PATx control method returns no value. + // + // Arguments: (1) + // Arg0 - temperature in tenths of degree Kelvin + // Return Value: + // None + // + Method(PAT1,1,Serialized) // send Arg0 to EC as Programmable Auxiliary Trip Point 1 + { + + } + + // Thermal Sensor Hysteresis, 2 degrees + Name(GTSH, 20) + + Name(LSTM,0) // Last temperature reported + + // _DTI (Device Temperature Indication) + // + // Conveys the temperature of a device's internal temperature sensor to the platform when a temperature trip point + // is crossed or when a meaningful temperature change occurs. + // + // Arguments: (1) + // Arg0 - An Integer containing the current value of the temperature sensor (in tenths Kelvin) + // Return Value: + // None + // + Method(_DTI, 1) + { + Store(Arg0,LSTM) + Notify(\_SB.GEN1, 0x91) // notify the participant of a trip point change event + } + + // _NTT (Notification Temperature Threshold) + // + // Returns the temperature change threshold for devices containing native temperature sensors to cause + // evaluation of the _DTI object + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the temperature threshold in tenths of degrees Kelvin. + // + Method(_NTT, 0) + { + Return(2782) // 5 degree Celcius, this could be a platform policy with setup item + } + + // _TSP (Thermal Sampling Period) + // + // Sets the polling interval in 10ths of seconds. A value of 0 tells the driver to use interrupts. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the polling rate in tenths of seconds. + // A value of 0 will specify using interrupts through the ACPI notifications. + // + // The granularity of the sampling period is 0.1 seconds. For example, if the sampling period is 30.0 + // seconds, then _TSP needs to report 300; if the sampling period is 0.5 seconds, then it will report 5. + // + Method(_TSP,0,Serialized) + { + Return(\TSP1) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC0,0,Serialized) + { + If (LEqual(\G1AT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\G1AT)) // Active Cooling Policy + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC1,0,Serialized) + { + If (LEqual(\G1AT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(Subtract(\_SB.IETM.CTOK(\G1AT),100)) // 10 degrees less than _AC0 + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC2,0,Serialized) + { + If (LEqual(\G1AT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(Subtract(\_SB.IETM.CTOK(\G1AT),200)) // 20 degrees less than _AC0 + } + + // _PSV (Passive) + // + // This optional object, if present under a thermal zone, evaluates to the temperature + // at which OSPM must activate passive cooling policy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the passive cooling temperature threshold in tenths of degrees Kelvin + // + Method(_PSV,0,Serialized) + { + If (LEqual(\G1PT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\G1PT)) // Passive Cooling Policy + } + + // _CRT (Critical Temperature) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM must shutdown the system. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CRT,0,Serialized) + { + If (LEqual(\G1CT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\G1CT)) + } + + // _CR3 (Critical Temperature for S3/CS) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM + // must transition to Standby or Connected Standy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CR3,0,Serialized) + { + If (LEqual(\G1C3,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\G1C3)) + } + + // _HOT (Hot Temperature) + // + // This optional object, when defined under a thermal zone, returns the critical temperature + // at which OSPM may choose to transition the system into the S4 sleeping state. + // + // Arguments: (0) + // None + // Return Value: + // The return value is an integer that represents the critical sleep threshold tenths of degrees Kelvin. + // + Method(_HOT,0,Serialized) + { + If (LEqual(\G1HT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\G1HT)) + } + + // _SCP (Set Cooling Policy) + // + // Arguments: (3) + // Arg0 - Mode An Integer containing the cooling mode policy code + // Arg1 - AcousticLimit An Integer containing the acoustic limit + // Arg2 - PowerLimit An Integer containing the power limit + // Return Value: + // None + // + // Argument Information: + // Mode - 0 = Active, 1 = Passive + // Acoustic Limit - Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit - Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // + Method(_SCP, 3, Serialized) + { + If (LOr(LEqual(Arg0,0),LEqual(Arg0,1))) { + Store(Arg0, CTYP) + Notify(\_SB.GEN1, 0x91) + } + } + + Name(VERS,0) // Version + Name(ALMT,0) // Acoustic Limit + Name(PLMT,0) // Power Limit + Name(WKLD,0) // Workload Hint + Name(DSTA,0) // Device State Hint + Name(RES1,0) // Reserved 1 + + // DSCP (DPTF Set Cooling Policy) + // + // Arguments: (7) + // Arg0 - Version: For DPTF 8.0, this value is always 0. + // Arg1 - Mode: Integer containing the cooling mode policy code + // Arg2 - Acoustic Limit: Acoustic Limit value as defined in ACPI specification + // Arg3 - Power Limit: Power Limit value as defined in ACPI specification + // Arg4 - Workload Hint: Arbitrary Platform defined Integer that indicates to the platform the type of workload run in the OS. + // Arg5 - Device State Hint: An integer value that indicates the state of the device. + // Arg6 - Reserved 1 + // Return Value: + // None + // + // Argument Information: + // Mode: 0 = Active(Typically AC Power Source), 1 = Passive(Typically Battery Power Source) + // Acoustic Limit: Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit: Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // Workload Hint: Refer to Intel DPTF Configuration Guide on how to set this value for various workloads for each Operating System. + // Device State Hint: An integer value that indicates the state of the device. + // First byte indicates portrait or landscape mode. + // Second byte indicates horizontal or vertical orientation. + // Third byte indicates proximity sensor status (if available). + // Fourth byte is unused. + // xxxxxx00h: Portrait + // xxxxxx01h: Landscape + // xxxx00xxh: Horizontal + // xxxx01xxh: Vertical + // xx00xxxxh: Proximity sensor Off (Device not in proximity to user) + // xx01xxxxh: Proximity sensor On (Device in proximity to user) + // + Method(DSCP, 7, Serialized) + { + If (LOr(LEqual(Arg1,0),LEqual(Arg1,1))) { + Store(Arg0, VERS) + Store(Arg1, CTYP) + Store(Arg2, ALMT) + Store(Arg3, PLMT) + Store(Arg4, WKLD) + Store(Arg5, DSTA) + Store(Arg6, RES1) + Notify(\_SB.GEN1, 0x91) + } + } + + } // End of Device(Gen1) +} + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Gen2Participant.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Gen2Participant.asl new file mode 100644 index 0000000000..b1fb98da4c --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Gen2Participant.asl @@ -0,0 +1,349 @@ +/** @file + Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(\_SB) +{ + Device(GEN2) // Generic participant + { + Name(_HID, EISAID("INT3403")) + Name(_UID, "GEN2") + Name(_STR, Unicode ("Thermistor 2 DIMM0_RT1E1")) + Name(PTYP, 0x12) + + Name(FAUX, 0) + Name(SAUX, 0) + Name(CTYP,0) // Mode + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (\GN2E) { + Return(0x0F) + } Else { + Return(0x00) + } + } + + // _TMP (Temperature) + // + // This control method returns the thermal zone's current operating temperature. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the current temperature of the thermal zone (in tenths of degrees Kelvin) + // + Method(_TMP,0,Serialized) + { + + Return(3000) // degrees kelvin + + } + + // Returns Number of Aux Trips available + Name(PATC, 2) + + // PATx (Participant Programmable Auxiliary Trip) - Sets Aux Trip Point + // + // The PATx objects shall take a single integer parameter, in tenths of degree Kelvin, which + // represents the temperature at which the device should notify the participant driver of + // an auxiliary trip event. A PATx control method returns no value. + // + // Arguments: (1) + // Arg0 - temperature in tenths of degree Kelvin + // Return Value: + // None + // + Method(PAT0,1,Serialized) // send Arg0 to EC as Programmable Auxiliary Trip Point 0 + { + + } + + // PATx (Participant Programmable Auxiliary Trip) - Sets Aux Trip Point + // + // The PATx objects shall take a single integer parameter, in tenths of degree Kelvin, which + // represents the temperature at which the device should notify the participant driver of + // an auxiliary trip event. A PATx control method returns no value. + // + // Arguments: (1) + // Arg0 - temperature in tenths of degree Kelvin + // Return Value: + // None + // + Method(PAT1,1,Serialized) // send Arg0 to EC as Programmable Auxiliary Trip Point 1 + { + + } + + // Thermal Sensor Hysteresis, 2 degrees + Name(GTSH, 20) + + Name(LSTM,0) // Last temperature reported + + // _DTI (Device Temperature Indication) + // + // Conveys the temperature of a device's internal temperature sensor to the platform when a temperature trip point + // is crossed or when a meaningful temperature change occurs. + // + // Arguments: (1) + // Arg0 - An Integer containing the current value of the temperature sensor (in tenths Kelvin) + // Return Value: + // None + // + Method(_DTI, 1) + { + Store(Arg0,LSTM) + Notify(\_SB.GEN2, 0x91) // notify the participant of a trip point change event + } + + // _NTT (Notification Temperature Threshold) + // + // Returns the temperature change threshold for devices containing native temperature sensors to cause + // evaluation of the _DTI object + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the temperature threshold in tenths of degrees Kelvin. + // + Method(_NTT, 0) + { + Return(2782) // 5 degree Celcius, this could be a platform policy with setup item + } + + // _TSP (Thermal Sampling Period) + // + // Sets the polling interval in 10ths of seconds. A value of 0 tells the driver to use interrupts. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the polling rate in tenths of seconds. + // A value of 0 will specify using interrupts through the ACPI notifications. + // + // The granularity of the sampling period is 0.1 seconds. For example, if the sampling period is 30.0 + // seconds, then _TSP needs to report 300; if the sampling period is 0.5 seconds, then it will report 5. + // + Method(_TSP,0,Serialized) + { + Return(\TSP2) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC0,0,Serialized) + { + If (LEqual(\G2AT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\G2AT)) // Active Cooling Policy + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC1,0,Serialized) + { + If (LEqual(\G2AT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(Subtract(\_SB.IETM.CTOK(\G2AT),100)) // 10 degrees less than _AC0 + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC2,0,Serialized) + { + If (LEqual(\G2AT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(Subtract(\_SB.IETM.CTOK(\G2AT),200)) // 20 degrees less than _AC0 + } + + // _PSV (Passive) + // + // This optional object, if present under a thermal zone, evaluates to the temperature + // at which OSPM must activate passive cooling policy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the passive cooling temperature threshold in tenths of degrees Kelvin + // + Method(_PSV,0,Serialized) + { + If (LEqual(\G2PT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\G2PT)) // Passive Cooling Policy + } + + // _CRT (Critical Temperature) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM must shutdown the system. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CRT,0,Serialized) + { + If (LEqual(\G2CT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\G2CT)) + } + + // _CR3 (Critical Temperature for S3/CS) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM + // must transition to Standby or Connected Standy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CR3,0,Serialized) + { + If (LEqual(\G2C3,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\G2C3)) + } + + // _HOT (Hot Temperature) + // + // This optional object, when defined under a thermal zone, returns the critical temperature + // at which OSPM may choose to transition the system into the S4 sleeping state. + // + // Arguments: (0) + // None + // Return Value: + // The return value is an integer that represents the critical sleep threshold tenths of degrees Kelvin. + // + Method(_HOT,0,Serialized) + { + If (LEqual(\G2HT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\G2HT)) + } + + // _SCP (Set Cooling Policy) + // + // Arguments: (3) + // Arg0 - Mode An Integer containing the cooling mode policy code + // Arg1 - AcousticLimit An Integer containing the acoustic limit + // Arg2 - PowerLimit An Integer containing the power limit + // Return Value: + // None + // + // Argument Information: + // Mode - 0 = Active, 1 = Passive + // Acoustic Limit - Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit - Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // + Method(_SCP, 3, Serialized) + { + If (LOr(LEqual(Arg0,0),LEqual(Arg0,1))) { + Store(Arg0, CTYP) + Notify(\_SB.GEN2, 0x91) + } + } + + Name(VERS,0) // Version + Name(ALMT,0) // Acoustic Limit + Name(PLMT,0) // Power Limit + Name(WKLD,0) // Workload Hint + Name(DSTA,0) // Device State Hint + Name(RES1,0) // Reserved 1 + + // DSCP (DPTF Set Cooling Policy) + // + // Arguments: (7) + // Arg0 - Version: For DPTF 8.0, this value is always 0. + // Arg1 - Mode: Integer containing the cooling mode policy code + // Arg2 - Acoustic Limit: Acoustic Limit value as defined in ACPI specification + // Arg3 - Power Limit: Power Limit value as defined in ACPI specification + // Arg4 - Workload Hint: Arbitrary Platform defined Integer that indicates to the platform the type of workload run in the OS. + // Arg5 - Device State Hint: An integer value that indicates the state of the device. + // Arg6 - Reserved 1 + // Return Value: + // None + // + // Argument Information: + // Mode: 0 = Active(Typically AC Power Source), 1 = Passive(Typically Battery Power Source) + // Acoustic Limit: Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit: Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // Workload Hint: Refer to Intel DPTF Configuration Guide on how to set this value for various workloads for each Operating System. + // Device State Hint: An integer value that indicates the state of the device. + // First byte indicates portrait or landscape mode. + // Second byte indicates horizontal or vertical orientation. + // Third byte indicates proximity sensor status (if available). + // Fourth byte is unused. + // xxxxxx00h: Portrait + // xxxxxx01h: Landscape + // xxxx00xxh: Horizontal + // xxxx01xxh: Vertical + // xx00xxxxh: Proximity sensor Off (Device not in proximity to user) + // xx01xxxxh: Proximity sensor On (Device in proximity to user) + // + Method(DSCP, 7, Serialized) + { + If (LOr(LEqual(Arg1,0),LEqual(Arg1,1))) { + Store(Arg0, VERS) + Store(Arg1, CTYP) + Store(Arg2, ALMT) + Store(Arg3, PLMT) + Store(Arg4, WKLD) + Store(Arg5, DSTA) + Store(Arg6, RES1) + Notify(\_SB.GEN2, 0x91) + } + } + + } // End of Device(Gen2) +} + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Gen3Participant.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Gen3Participant.asl new file mode 100644 index 0000000000..591ba5f3a3 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Gen3Participant.asl @@ -0,0 +1,349 @@ +/** @file + Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(\_SB) +{ + Device(GEN3) // Generic participant + { + Name(_HID, EISAID("INT3403")) + Name(_UID, "GEN3") + Name(_STR, Unicode ("Thermistor 3 AMBIENT_TEMP_RT4B1")) + Name(PTYP, 0x12) + + Name(FAUX, 0) + Name(SAUX, 0) + Name(CTYP,0) // Mode + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (\GN3E) { + Return(0x0F) + } Else { + Return(0x00) + } + } + + // _TMP (Temperature) + // + // This control method returns the thermal zone's current operating temperature. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the current temperature of the thermal zone (in tenths of degrees Kelvin) + // + Method(_TMP,0,Serialized) + { + + Return(3000) // degrees kelvin + + } + + // Returns Number of Aux Trips available + Name(PATC, 2) + + // PATx (Participant Programmable Auxiliary Trip) - Sets Aux Trip Point + // + // The PATx objects shall take a single integer parameter, in tenths of degree Kelvin, which + // represents the temperature at which the device should notify the participant driver of + // an auxiliary trip event. A PATx control method returns no value. + // + // Arguments: (1) + // Arg0 - temperature in tenths of degree Kelvin + // Return Value: + // None + // + Method(PAT0,1,Serialized) // send Arg0 to EC as Programmable Auxiliary Trip Point 0 + { + + } + + // PATx (Participant Programmable Auxiliary Trip) - Sets Aux Trip Point + // + // The PATx objects shall take a single integer parameter, in tenths of degree Kelvin, which + // represents the temperature at which the device should notify the participant driver of + // an auxiliary trip event. A PATx control method returns no value. + // + // Arguments: (1) + // Arg0 - temperature in tenths of degree Kelvin + // Return Value: + // None + // + Method(PAT1,1,Serialized) // send Arg0 to EC as Programmable Auxiliary Trip Point 1 + { + + } + + // Thermal Sensor Hysteresis, 2 degrees + Name(GTSH, 20) + + Name(LSTM,0) // Last temperature reported + + // _DTI (Device Temperature Indication) + // + // Conveys the temperature of a device's internal temperature sensor to the platform when a temperature trip point + // is crossed or when a meaningful temperature change occurs. + // + // Arguments: (1) + // Arg0 - An Integer containing the current value of the temperature sensor (in tenths Kelvin) + // Return Value: + // None + // + Method(_DTI, 1) + { + Store(Arg0,LSTM) + Notify(\_SB.GEN3, 0x91) // notify the participant of a trip point change event + } + + // _NTT (Notification Temperature Threshold) + // + // Returns the temperature change threshold for devices containing native temperature sensors to cause + // evaluation of the _DTI object + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the temperature threshold in tenths of degrees Kelvin. + // + Method(_NTT, 0) + { + Return(2782) // 5 degree Celcius, this could be a platform policy with setup item + } + + // _TSP (Thermal Sampling Period) + // + // Sets the polling interval in 10ths of seconds. A value of 0 tells the driver to use interrupts. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the polling rate in tenths of seconds. + // A value of 0 will specify using interrupts through the ACPI notifications. + // + // The granularity of the sampling period is 0.1 seconds. For example, if the sampling period is 30.0 + // seconds, then _TSP needs to report 300; if the sampling period is 0.5 seconds, then it will report 5. + // + Method(_TSP,0,Serialized) + { + Return(\TSP3) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC0,0,Serialized) + { + If (LEqual(\G3AT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\G3AT)) // Active Cooling Policy + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC1,0,Serialized) + { + If (LEqual(\G3AT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(Subtract(\_SB.IETM.CTOK(\G3AT),100)) // 10 degrees less than _AC0 + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC2,0,Serialized) + { + If (LEqual(\G3AT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(Subtract(\_SB.IETM.CTOK(\G3AT),200)) // 20 degrees less than _AC0 + } + + // _PSV (Passive) + // + // This optional object, if present under a thermal zone, evaluates to the temperature + // at which OSPM must activate passive cooling policy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the passive cooling temperature threshold in tenths of degrees Kelvin + // + Method(_PSV,0,Serialized) + { + If (LEqual(\G3PT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\G3PT)) // Passive Cooling Policy + } + + // _CRT (Critical Temperature) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM must shutdown the system. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CRT,0,Serialized) + { + If (LEqual(\G3CT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\G3CT)) + } + + // _CR3 (Critical Temperature for S3/CS) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM + // must transition to Standby or Connected Standy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CR3,0,Serialized) + { + If (LEqual(\G3C3,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\G3C3)) + } + + // _HOT (Hot Temperature) + // + // This optional object, when defined under a thermal zone, returns the critical temperature + // at which OSPM may choose to transition the system into the S4 sleeping state. + // + // Arguments: (0) + // None + // Return Value: + // The return value is an integer that represents the critical sleep threshold tenths of degrees Kelvin. + // + Method(_HOT,0,Serialized) + { + If (LEqual(\G3HT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\G3HT)) + } + + // _SCP (Set Cooling Policy) + // + // Arguments: (3) + // Arg0 - Mode An Integer containing the cooling mode policy code + // Arg1 - AcousticLimit An Integer containing the acoustic limit + // Arg2 - PowerLimit An Integer containing the power limit + // Return Value: + // None + // + // Argument Information: + // Mode - 0 = Active, 1 = Passive + // Acoustic Limit - Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit - Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // + Method(_SCP, 3, Serialized) + { + If (LOr(LEqual(Arg0,0),LEqual(Arg0,1))) { + Store(Arg0, CTYP) + Notify(\_SB.GEN3, 0x91) + } + } + + Name(VERS,0) // Version + Name(ALMT,0) // Acoustic Limit + Name(PLMT,0) // Power Limit + Name(WKLD,0) // Workload Hint + Name(DSTA,0) // Device State Hint + Name(RES1,0) // Reserved 1 + + // DSCP (DPTF Set Cooling Policy) + // + // Arguments: (7) + // Arg0 - Version: For DPTF 8.0, this value is always 0. + // Arg1 - Mode: Integer containing the cooling mode policy code + // Arg2 - Acoustic Limit: Acoustic Limit value as defined in ACPI specification + // Arg3 - Power Limit: Power Limit value as defined in ACPI specification + // Arg4 - Workload Hint: Arbitrary Platform defined Integer that indicates to the platform the type of workload run in the OS. + // Arg5 - Device State Hint: An integer value that indicates the state of the device. + // Arg6 - Reserved 1 + // Return Value: + // None + // + // Argument Information: + // Mode: 0 = Active(Typically AC Power Source), 1 = Passive(Typically Battery Power Source) + // Acoustic Limit: Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit: Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // Workload Hint: Refer to Intel DPTF Configuration Guide on how to set this value for various workloads for each Operating System. + // Device State Hint: An integer value that indicates the state of the device. + // First byte indicates portrait or landscape mode. + // Second byte indicates horizontal or vertical orientation. + // Third byte indicates proximity sensor status (if available). + // Fourth byte is unused. + // xxxxxx00h: Portrait + // xxxxxx01h: Landscape + // xxxx00xxh: Horizontal + // xxxx01xxh: Vertical + // xx00xxxxh: Proximity sensor Off (Device not in proximity to user) + // xx01xxxxh: Proximity sensor On (Device in proximity to user) + // + Method(DSCP, 7, Serialized) + { + If (LOr(LEqual(Arg1,0),LEqual(Arg1,1))) { + Store(Arg0, VERS) + Store(Arg1, CTYP) + Store(Arg2, ALMT) + Store(Arg3, PLMT) + Store(Arg4, WKLD) + Store(Arg5, DSTA) + Store(Arg6, RES1) + Notify(\_SB.GEN3, 0x91) + } + } + + } // End of Device(Gen3) +} + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Gen4Participant.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Gen4Participant.asl new file mode 100644 index 0000000000..128295cfd6 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Gen4Participant.asl @@ -0,0 +1,349 @@ +/** @file + Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(\_SB) +{ + Device(GEN4) // Generic participant + { + Name(_HID, EISAID("INT3403")) + Name(_UID, "GEN4") + Name(_STR, Unicode ("Thermistor 4 SKIN_RT3H1")) + Name(PTYP, 0x12) + + Name(FAUX, 0) + Name(SAUX, 0) + Name(CTYP,0) // Mode + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (\GN4E) { + Return(0x0F) + } Else { + Return(0x00) + } + } + + // _TMP (Temperature) + // + // This control method returns the thermal zone's current operating temperature. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the current temperature of the thermal zone (in tenths of degrees Kelvin) + // + Method(_TMP,0,Serialized) + { + + Return(3000) // degrees kelvin + + } + + // Returns Number of Aux Trips available + Name(PATC, 2) + + // PATx (Participant Programmable Auxiliary Trip) - Sets Aux Trip Point + // + // The PATx objects shall take a single integer parameter, in tenths of degree Kelvin, which + // represents the temperature at which the device should notify the participant driver of + // an auxiliary trip event. A PATx control method returns no value. + // + // Arguments: (1) + // Arg0 - temperature in tenths of degree Kelvin + // Return Value: + // None + // + Method(PAT0,1,Serialized) // send Arg0 to EC as Programmable Auxiliary Trip Point 0 + { + + } + + // PATx (Participant Programmable Auxiliary Trip) - Sets Aux Trip Point + // + // The PATx objects shall take a single integer parameter, in tenths of degree Kelvin, which + // represents the temperature at which the device should notify the participant driver of + // an auxiliary trip event. A PATx control method returns no value. + // + // Arguments: (1) + // Arg0 - temperature in tenths of degree Kelvin + // Return Value: + // None + // + Method(PAT1,1,Serialized) // send Arg0 to EC as Programmable Auxiliary Trip Point 1 + { + + } + + // Thermal Sensor Hysteresis, 2 degrees + Name(GTSH, 20) + + Name(LSTM,0) // Last temperature reported + + // _DTI (Device Temperature Indication) + // + // Conveys the temperature of a device's internal temperature sensor to the platform when a temperature trip point + // is crossed or when a meaningful temperature change occurs. + // + // Arguments: (1) + // Arg0 - An Integer containing the current value of the temperature sensor (in tenths Kelvin) + // Return Value: + // None + // + Method(_DTI, 1) + { + Store(Arg0,LSTM) + Notify(\_SB.GEN4, 0x91) // notify the participant of a trip point change event + } + + // _NTT (Notification Temperature Threshold) + // + // Returns the temperature change threshold for devices containing native temperature sensors to cause + // evaluation of the _DTI object + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the temperature threshold in tenths of degrees Kelvin. + // + Method(_NTT, 0) + { + Return(2782) // 5 degree Celcius, this could be a platform policy with setup item + } + + // _TSP (Thermal Sampling Period) + // + // Sets the polling interval in 10ths of seconds. A value of 0 tells the driver to use interrupts. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the polling rate in tenths of seconds. + // A value of 0 will specify using interrupts through the ACPI notifications. + // + // The granularity of the sampling period is 0.1 seconds. For example, if the sampling period is 30.0 + // seconds, then _TSP needs to report 300; if the sampling period is 0.5 seconds, then it will report 5. + // + Method(_TSP,0,Serialized) + { + Return(\TSP4) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC0,0,Serialized) + { + If (LEqual(\G4AT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\G4AT)) // Active Cooling Policy + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC1,0,Serialized) + { + If (LEqual(\G4AT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(Subtract(\_SB.IETM.CTOK(\G4AT),100)) // 10 degrees less than _AC0 + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC2,0,Serialized) + { + If (LEqual(\G4AT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(Subtract(\_SB.IETM.CTOK(\G4AT),200)) // 20 degrees less than _AC0 + } + + // _PSV (Passive) + // + // This optional object, if present under a thermal zone, evaluates to the temperature + // at which OSPM must activate passive cooling policy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the passive cooling temperature threshold in tenths of degrees Kelvin + // + Method(_PSV,0,Serialized) + { + If (LEqual(\G4PT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\G4PT)) // Passive Cooling Policy + } + + // _CRT (Critical Temperature) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM must shutdown the system. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CRT,0,Serialized) + { + If (LEqual(\G4CT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\G4CT)) + } + + // _CR3 (Critical Temperature for S3/CS) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM + // must transition to Standby or Connected Standy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CR3,0,Serialized) + { + If (LEqual(\G4C3,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\G4C3)) + } + + // _HOT (Hot Temperature) + // + // This optional object, when defined under a thermal zone, returns the critical temperature + // at which OSPM may choose to transition the system into the S4 sleeping state. + // + // Arguments: (0) + // None + // Return Value: + // The return value is an integer that represents the critical sleep threshold tenths of degrees Kelvin. + // + Method(_HOT,0,Serialized) + { + If (LEqual(\G4HT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\G4HT)) + } + + // _SCP (Set Cooling Policy) + // + // Arguments: (3) + // Arg0 - Mode An Integer containing the cooling mode policy code + // Arg1 - AcousticLimit An Integer containing the acoustic limit + // Arg2 - PowerLimit An Integer containing the power limit + // Return Value: + // None + // + // Argument Information: + // Mode - 0 = Active, 1 = Passive + // Acoustic Limit - Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit - Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // + Method(_SCP, 3, Serialized) + { + If (LOr(LEqual(Arg0,0),LEqual(Arg0,1))) { + Store(Arg0, CTYP) + Notify(\_SB.GEN4, 0x91) + } + } + + Name(VERS,0) // Version + Name(ALMT,0) // Acoustic Limit + Name(PLMT,0) // Power Limit + Name(WKLD,0) // Workload Hint + Name(DSTA,0) // Device State Hint + Name(RES1,0) // Reserved 1 + + // DSCP (DPTF Set Cooling Policy) + // + // Arguments: (7) + // Arg0 - Version: For DPTF 8.0, this value is always 0. + // Arg1 - Mode: Integer containing the cooling mode policy code + // Arg2 - Acoustic Limit: Acoustic Limit value as defined in ACPI specification + // Arg3 - Power Limit: Power Limit value as defined in ACPI specification + // Arg4 - Workload Hint: Arbitrary Platform defined Integer that indicates to the platform the type of workload run in the OS. + // Arg5 - Device State Hint: An integer value that indicates the state of the device. + // Arg6 - Reserved 1 + // Return Value: + // None + // + // Argument Information: + // Mode: 0 = Active(Typically AC Power Source), 1 = Passive(Typically Battery Power Source) + // Acoustic Limit: Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit: Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // Workload Hint: Refer to Intel DPTF Configuration Guide on how to set this value for various workloads for each Operating System. + // Device State Hint: An integer value that indicates the state of the device. + // First byte indicates portrait or landscape mode. + // Second byte indicates horizontal or vertical orientation. + // Third byte indicates proximity sensor status (if available). + // Fourth byte is unused. + // xxxxxx00h: Portrait + // xxxxxx01h: Landscape + // xxxx00xxh: Horizontal + // xxxx01xxh: Vertical + // xx00xxxxh: Proximity sensor Off (Device not in proximity to user) + // xx01xxxxh: Proximity sensor On (Device in proximity to user) + // + Method(DSCP, 7, Serialized) + { + If (LOr(LEqual(Arg1,0),LEqual(Arg1,1))) { + Store(Arg0, VERS) + Store(Arg1, CTYP) + Store(Arg2, ALMT) + Store(Arg3, PLMT) + Store(Arg4, WKLD) + Store(Arg5, DSTA) + Store(Arg6, RES1) + Notify(\_SB.GEN4, 0x91) + } + } + + } // End of Device(Gen4) +} + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Psvt.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Psvt.asl new file mode 100644 index 0000000000..c0aef55a07 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Psvt.asl @@ -0,0 +1,33 @@ +/** @file + Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(\_SB.IETM) +{ + // PTTL (Participant Temperature Tolerance Level) + // This object evaluates to an integer representing the temperature range within which any change + // in participant temperature is considered acceptable and no policy actions will be taken by the + // policy. The temperature tolerance level is expressed in the units of 10s of Kelvin. + // + Name (PTTL, 20) // ToleranceLevel + Name (PSVT, Package() + { + 2, + Package(){\_SB.PCI0.TCPU, \_SB.SEN1, 2, 300, 3032, 9, 0x00010000, 12000, 500, 10, 20, 0}, + Package(){\_SB.PCI0.TCPU, \_SB.SEN1, 2, 300, 3082, 9, 0x00010000, 9000, 500, 10, 20, 0}, + Package(){\_SB.PCI0.TCPU, \_SB.SEN1, 2, 300, 3132, 9, 0x00010000, 6000, 500, 10, 20, 0}, + Package(){\_SB.PCI0.TCPU, \_SB.SEN1, 1, 300, 3232, 9, 0x00010000, "MIN", 500, 10, 20, 0}, + Package(){\_SB.PCI0.TCPU, \_SB.PCI0.TCPU,1,50,3532, 9, 0x00010000, "MIN", 500, 10, 20, 0} + }) + +}// end Scope(\_SB.IETM) + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/SEN1Participant.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/SEN1Participant.asl new file mode 100644 index 0000000000..7050021faf --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/SEN1Participant.asl @@ -0,0 +1,343 @@ +/** @file + Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(\_SB) +{ + Device(SEN1) + { + Name(_HID, EISAID("INT3403")) // Intel DPTF Temperature Sensor Device + Name(_UID, "SEN1") + Name(_STR, Unicode ("Sensor 1 CPU VR Temp")) + Name(PTYP, 0x03) + + Name(FAUX, 0) + Name(SAUX, 0) + Name(CTYP,0) // Mode + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (LEqual(\S1DE,1)) { + Return(0x0F) + } Else { + Return(0x00) + } + } + + // _TMP (Temperature) + // + // This control method returns the thermal zone's current operating temperature. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the current temperature of the thermal zone (in tenths of degrees Kelvin) + // + Method(_TMP,0,Serialized) + { + + Return(3000) + + } + + // Returns Number of Aux Trips available + Name(PATC, 2) + + // PATx (Participant Programmable Auxiliary Trip) - Sets Aux Trip Point + // + // The PATx objects shall take a single integer parameter, in tenths of degree Kelvin, which + // represents the temperature at which the device should notify the participant driver of + // an auxiliary trip event. A PATx control method returns no value. + // + // Arguments: (1) + // Arg0 - temperature in tenths of degree Kelvin + // Return Value: + // None + // + + + // PATx (Participant Programmable Auxiliary Trip) - Sets Aux Trip Point + // + // The PATx objects shall take a single integer parameter, in tenths of degree Kelvin, which + // represents the temperature at which the device should notify the participant driver of + // an auxiliary trip event. A PATx control method returns no value. + // + // Arguments: (1) + // Arg0 - temperature in tenths of degree Kelvin + // Return Value: + // None + // + + + // Thermal Sensor Hysteresis, 2 degrees + Name(GTSH, 20) + + Name(LSTM,0) // Last temperature reported + + // _DTI (Device Temperature Indication) + // + // Conveys the temperature of a device's internal temperature sensor to the platform when a temperature trip point + // is crossed or when a meaningful temperature change occurs. + // + // Arguments: (1) + // Arg0 - An Integer containing the current value of the temperature sensor (in tenths Kelvin) + // Return Value: + // None + // + Method(_DTI, 1) + { + Store(Arg0,LSTM) + Notify(\_SB.SEN1, 0x91) // notify the participant of a trip point change event + } + + // _NTT (Notification Temperature Threshold) + // + // Returns the temperature change threshold for devices containing native temperature sensors to cause + // evaluation of the _DTI object + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the temperature threshold in tenths of degrees Kelvin. + // + Method(_NTT, 0) + { + Return(2782) // 5 degree Celcius, this could be a platform policy with setup item + } + + // _TSP (Thermal Sampling Period) + // + // Sets the polling interval in 10ths of seconds. A value of 0 tells the driver to use interrupts. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the polling rate in tenths of seconds. + // A value of 0 will specify using interrupts through the ACPI notifications. + // + // The granularity of the sampling period is 0.1 seconds. For example, if the sampling period is 30.0 + // seconds, then _TSP needs to report 300; if the sampling period is 0.5 seconds, then it will report 5. + // + Method(_TSP,0,Serialized) + { + Return(\SSP1) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC0,0,Serialized) + { + If (LEqual(\S1AT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\S1AT)) // Active Cooling Policy + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC1,0,Serialized) + { + If (LEqual(\S1AT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(Subtract(\_SB.IETM.CTOK(\S1AT),100)) // 10 degrees less than _AC0 + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC2,0,Serialized) + { + If (LEqual(\S1AT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(Subtract(\_SB.IETM.CTOK(\S1AT),200)) // 20 degrees less than _AC0 + } + + // _PSV (Passive) + // + // This optional object, if present under a thermal zone, evaluates to the temperature + // at which OSPM must activate passive cooling policy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the passive cooling temperature threshold in tenths of degrees Kelvin + // + Method(_PSV,0,Serialized) + { + If (LEqual(\S1PT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\S1PT)) // Passive Cooling Policy + } + + // _CRT (Critical Temperature) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM must shutdown the system. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CRT,0,Serialized) + { + If (LEqual(\S1CT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\S1CT)) + } + + // _CR3 (Critical Temperature for S3/CS) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM + // must transition to Standby or Connected Standy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CR3,0,Serialized) + { + If (LEqual(\S1S3,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\S1S3)) + } + + // _HOT (Hot Temperature) + // + // This optional object, when defined under a thermal zone, returns the critical temperature + // at which OSPM may choose to transition the system into the S4 sleeping state. + // + // Arguments: (0) + // None + // Return Value: + // The return value is an integer that represents the critical sleep threshold tenths of degrees Kelvin. + // + Method(_HOT,0,Serialized) + { + If (LEqual(\S1HT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\S1HT)) + } + + // _SCP (Set Cooling Policy) + // + // Arguments: (3) + // Arg0 - Mode An Integer containing the cooling mode policy code + // Arg1 - AcousticLimit An Integer containing the acoustic limit + // Arg2 - PowerLimit An Integer containing the power limit + // Return Value: + // None + // + // Argument Information: + // Mode - 0 = Active, 1 = Passive + // Acoustic Limit - Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit - Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // + Method(_SCP, 3, Serialized) + { + If (LOr(LEqual(Arg0,0),LEqual(Arg0,1))) { + Store(Arg0, CTYP) + Notify(\_SB.SEN1, 0x91) + } + } + + Name(VERS,0) // Version + Name(ALMT,0) // Acoustic Limit + Name(PLMT,0) // Power Limit + Name(WKLD,0) // Workload Hint + Name(DSTA,0) // Device State Hint + Name(RES1,0) // Reserved 1 + + // DSCP (DPTF Set Cooling Policy) + // + // Arguments: (7) + // Arg0 - Version: For DPTF 8.0, this value is always 0. + // Arg1 - Mode: Integer containing the cooling mode policy code + // Arg2 - Acoustic Limit: Acoustic Limit value as defined in ACPI specification + // Arg3 - Power Limit: Power Limit value as defined in ACPI specification + // Arg4 - Workload Hint: Arbitrary Platform defined Integer that indicates to the platform the type of workload run in the OS. + // Arg5 - Device State Hint: An integer value that indicates the state of the device. + // Arg6 - Reserved 1 + // Return Value: + // None + // + // Argument Information: + // Mode: 0 = Active(Typically AC Power Source), 1 = Passive(Typically Battery Power Source) + // Acoustic Limit: Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit: Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // Workload Hint: Refer to Intel DPTF Configuration Guide on how to set this value for various workloads for each Operating System. + // Device State Hint: An integer value that indicates the state of the device. + // First byte indicates portrait or landscape mode. + // Second byte indicates horizontal or vertical orientation. + // Third byte indicates proximity sensor status (if available). + // Fourth byte is unused. + // xxxxxx00h: Portrait + // xxxxxx01h: Landscape + // xxxx00xxh: Horizontal + // xxxx01xxh: Vertical + // xx00xxxxh: Proximity sensor Off (Device not in proximity to user) + // xx01xxxxh: Proximity sensor On (Device in proximity to user) + // + Method(DSCP, 7, Serialized) + { + If (LOr(LEqual(Arg1,0),LEqual(Arg1,1))) { + Store(Arg0, VERS) + Store(Arg1, CTYP) + Store(Arg2, ALMT) + Store(Arg3, PLMT) + Store(Arg4, WKLD) + Store(Arg5, DSTA) + Store(Arg6, RES1) + Notify(\_SB.SEN1, 0x91) + } + } + + } // End SEN1 Device +}// end Scope(\_SB) + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/TFN1Participant.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/TFN1Participant.asl new file mode 100644 index 0000000000..c3f6e46f39 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/TFN1Participant.asl @@ -0,0 +1,138 @@ +/** @file + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(\_SB) +{ + Device(TFN1) + { + Name(_HID, EISAID("INT3404")) // Intel DPTF Fan Device + Name(_UID, "TFN1") + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (LEqual(\DFAN,1)) { + Return(0x0F) + } Else { + Return(0x00) + } + } + + // _FIF (Fan Information) + // + // The optional _FIF object provides OSPM with fan device capability information. + // + // Arguments: (0) + // None + // Return Value: + // A Package containing the fan device parameters. + // + Method(_FIF) + { + Return (Package (){ + 0, // Revision:Integer + 1, // FineGrainControl:Integer Boolean + 2, // StepSize:Integer DWORD + 0 // LowSpeedNotificationSupport:Integer Boolean + }) + } + + // _FPS (Fan Performance States) + // + // Evaluates to a variable-length package containing a list of packages that describe the fan device's performance states. + // + // Arguments: (0) + // None + // Return Value: + // A variable-length Package containing a Revision ID and a list of Packages that describe the fan device's performance states. + // + Method(_FPS,,,,PkgObj) + { + Return (Package() + { + 0, // Revision:Integer + // Control, TripPoint, Speed, NoiseLevel, Power + Package(){100, 0xFFFFFFFF, 12200, 500, 5000}, + Package(){ 95, 0xFFFFFFFF, 11600, 475, 4750}, + Package(){ 90, 0xFFFFFFFF, 11100, 450, 4500}, + Package(){ 85, 0xFFFFFFFF, 10500, 425, 4250}, + Package(){ 80, 0xFFFFFFFF, 9900, 400, 4000}, + Package(){ 75, 0xFFFFFFFF, 9300, 375, 3750}, + Package(){ 70, 0xFFFFFFFF, 8600, 350, 3500}, + Package(){ 60, 0xFFFFFFFF, 7400, 300, 3000}, + Package(){ 50, 0xFFFFFFFF, 6200, 250, 2500}, + Package(){ 40, 0xFFFFFFFF, 4850, 200, 2000}, + Package(){ 25, 0xFFFFFFFF, 2900, 125, 1250}, + Package(){ 0, 0xFFFFFFFF, 0, 0, 0} // OFF + }) + } + + // _FSL (Fan Set Level) + // + // The optional _FSL object is a control method that OSPM evaluates to set a fan device's speed (performance state) to a specific level. + // + // Arguments: (1) + // Arg0 - Level (Integer): conveys to the platform the fan speed level to be set. + // Return Value: + // None + // + // Argument Information + // Arg0: Level. If the fan supports fine-grained control, Level is a percentage of maximum level (0-100) + // that the platform is to engage the fan. If the fan does not support fine-grained control, + // Level is a Control field value from a package in the _FPS object's package list. + // A Level value of zero causes the platform to turn off the fan. + // + Method(_FSL,1,Serialized) + { + + } + + Name(TFST, Package() + { + 0, // Revision:Integer + 0xFFFFFFFF, // Control:Integer DWORD + 0xFFFFFFFF // Speed:Integer DWORD + }) + + //_FST (Fan Status) + // + // The optional _FST object provides status information for the fan device. + // + // Arguments: (0) + // None + // Return Value: + // A Package containing fan device status information + // + Method(_FST,0,Serialized,,PkgObj) + { + + Return(TFST) + } + + } // End TFN1 Device +} // End \_SB + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/TPwrParticipant.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/TPwrParticipant.asl new file mode 100644 index 0000000000..a9eef870ff --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/TPwrParticipant.asl @@ -0,0 +1,288 @@ +/** @file + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(\_SB) +{ + Device(TPWR) // Power participant + { + Name(_HID, EISAID("INT3407")) //Intel DPTF platform power device + Name(_UID, "TPWR") + Name(_STR, Unicode ("Platform Power")) + Name(PTYP, 0x11) + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (LEqual(\PWRE,1)) { + Return(0x0F) + } Else { + Return(0x00) + } + } + + // _BST (Battery Status) + // + // Arguments: (0) + // None + // Return Value: + // A Package containing the battery status in the format below: + // Package { + // Battery State + // Battery Present Rate + // Battery Remaining Capacity + // Battery Present Voltage + // } + // + Method(_BST,,,,PkgObj) + { + Return(Package(){0,0,0,0}) + } + + // _BIX (Battery Information Extended) + // + // The _BIX object returns the static portion of the Control Method Battery information. + // This information remains constant until the battery is changed. + // The _BIX object returns all information available via the _BIF object plus additional battery information. + // The _BIF object is deprecated in lieu of _BIX in ACPI 4.0. + // + // Arguments: (0) + // None + // Return Value: + // A Package containing the battery information as described below + // Package { + // Revision + // Power Unit + // Design Capacity + // Last Full Charge Capacity + // Battery Technology + // Design Voltage + // Design Capacity of Warning + // Design Capacity of Low + // Cycle Count + // Measurement Accuracy + // Max Sampling Time + // Min Sampling Time + // Max Averaging Interval + // Min Averaging Interval + // Battery Capacity Granularity 1 + // Battery Capacity Granularity 2 + // Model Number + // Serial Number + // Battery Type + // OEM Information + // Battery Swapping Capability + // } + // + Method(_BIX,,,,PkgObj) + { + Return(Package(){0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"0","0","0","0",0}) + } + + // PSOC (Platform State of Charge) + // + // This object evaluates to the remaining battery state of charge in %. + // + // Arguments: (0) + // None + // Return Value: + // remaining battery charge in % + // + Method(PSOC) + { + + Return (0) // EC not available + + + } + + // PMAX (Platform MAXimum) + // + // The PMAX object provides maximum power that can be supported by the battery in mW. + // + // Arguments: (0) + // None + // Return Value: + // maximum power in mW + // + Method(PMAX,0,Serialized) + { + + Return(0) + + } + + // NPWR (N PoWeR) + // + // True Platform Power: Could be AC supplied+Battery Pack supplied power or AC supplied. + // + // Arguments: (0) + // None + // Return Value: + // Power required to charge battery in mW. + // + Method(NPWR) + { + Return(20000) // 20 watts + } + + // PSRC (Power SouRCe) + // + // The PSRC object provides power source type. + // + // Arguments: (0) + // None + // Return Value: (enumeration which DPTF driver expects) + // 0 = DC + // 1 = AC + // 2 = USB + // 3 = WC + // + // Notes: (Bitmap from EC) + // Bit0=1 if AC + // Bit1=1 if USB-PD + // Bit2=1 if Wireless Charger + // + Method(PSRC, 0, Serialized) + { + + + Return(0) // Default return is DC + + } + + // ARTG (Adapter RaTinG) + // + // The ARTG object provides AC adapter rating in mW. + // ARTG should return 0 if PSRC is DC (0). + // + // Arguments: (0) + // None + // Return Value: + // AC adapter rating in mW + // + Method(ARTG) + { + If (LEqual(PSRC(),1)) { + // AC check + Return(90000) // 90 watts + } Else { + Return(0) + } + } + + // CTYP (Charger TYPe) + // + // The CTYP object provides charger type. + // + // Arguments: (0) + // None + // Return Value: + // 0x01 = Traditional + // 0x02 = Hybrid + // 0x03 = NVDC + // + Method(CTYP) + { + Return(3) + } + + // PROP (Platform Rest Of worst case Power) + // + // This object provides maximum worst case platform rest of power. + // + // Arguments: (0) + // None + // Return Value: + // power in milliwatts + // + Method(PROP) + { + Return(25000) // 25 watts + } + + // APKP (Ac PeaK Power) + // + // This object provides maximum adapter power output. + // + // Arguments: (0) + // None + // Return Value: + // power in milliwatts + // + Method(APKP) + { + Return(90000) // 90 watts + } + + // APKT (Ac PeaK Time) + // + // This object provides the maximum time the adapter can maintain peak power. + // + // Arguments: (0) + // None + // Return Value: + // time in milliseconds + // + Method(APKT) + { + Return(10) // 10 milliseconds + } + + // PBSS (Power Battery Steady State) + // + // Returns max sustained power for battery. + // + // Arguments: (0) + // None + // Return Value: + // power in milliwatts + // + Method(PBSS) + { + } + + // DPSP (DPTF Power Sampling Period) + // + // Sets the polling interval in 10ths of seconds. A value of 0 tells the driver to use event notification for PMAX and PBSS.. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the polling rate in tenths of seconds. + // A value of 0 will specify using interrupts through the ACPI notifications. + // + // The granularity of the sampling period is 0.1 seconds. For example, if the sampling period is 30.0 + // seconds, then report 300; if the sampling period is 0.5 seconds, then will report 5. + // + Method(DPSP,0,Serialized) + { + Return(\PPPR) + } + + } // End TPWR Device +}// end Scope(\_SB) + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/TcpuParticipant.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/TcpuParticipant.asl new file mode 100644 index 0000000000..db27cfbf96 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/TcpuParticipant.asl @@ -0,0 +1,568 @@ +/** @file + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(\_SB.PCI0) +{ + Device(TCPU) { + Name(_ADR, 0x00000001) // Intel Dptf Processor Device 0, Function 1 + + Name(GTSH, 20) // Hystersis, 2 Degree clesius + Name(LSTM,0) // Last temperature reported + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (LEqual(\DPSR,0)) { + Return(0x00) + } + Return(0x0F) + } + + // PPCC (Participant Power Control Capabilities) + // + // The PPCC object evaluates to a package of packages that indicates to DPTF processor + // participant the power control capabilities. + // + // Arguments: (0) + // None + // Return Value: + // PPCC package of packages + // + // PPCC will be initialized by the _INI method with power on default values from the PPM code. + // + Name (PPCC, Package() { + 0x2, //Revision + Package () { //Power Limit 1 + 0, //PowerLimitIndex, 0 for Power Limit 1 + 1000, //PowerLimitMinimum in mW + 15000, //PowerLimitMaximum + 1000, //TimeWindowMinimum + 1000, //TimeWindowMaximum + 250 //StepSize + } + }) + + // _PPC (Performance Present Capabilities) + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the range of states supported + // 0 - States 0 through nth state are available (all states available) + // 1 - States 1 through nth state are available + // 2 - States 2 through nth state are available + // ... + // n - State n is available only + // + Name(_PPC,0) + + // SPPC (Set Participant Performance Capability) + // + // SPPC is a control method object that takes one integer parameter that will indicate the maximum allowable + // P-State for OSPM to use at any given time. + // + // Arguments: (1) + // Arg0 - integer + // Return Value: + // None + // + Method(SPPC,1,Serialized) + { + Store ("cpudptf: SPPC Called", Debug) + If (CondRefOf(\_PR.CPU0._PPC)) { + Store(Arg0,\_PR.CPU0._PPC) // Note: _PPC must be an Integer not a Method + } + Notify(\_PR.CPU0, 0x80) // Tell P000 driver to re-eval _PPC + Notify(\_PR.CPU1, 0x80) // Tell P000 driver to re-eval _PPC + Notify(\_PR.CPU2, 0x80) // Tell P000 driver to re-eval _PPC + Notify(\_PR.CPU3, 0x80) // Tell P000 driver to re-eval _PPC + } + + + // _DTI (Device Temperature Indication) + // + // Conveys the temperature of a device's internal temperature sensor to the platform when a temperature trip point + // is crossed or when a meaningful temperature change occurs. + // + // Arguments: (1) + // Arg0 - An Integer containing the current value of the temperature sensor (in tenths Kelvin) + // Return Value: + // None + // + Method(_DTI, 1) + { + Store(Arg0,LSTM) + Notify(TCPU, 0x91) // notify the participant of a trip point change event + } + + // _NTT (Notification Temperature Threshold) + // + // Returns the temperature change threshold for devices containing native temperature sensors to cause + // evaluation of the _DTI object + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the temperature threshold in tenths of degrees Kelvin. + // + Method(_NTT, 0) + { + Return(2782) // 5 degree Celcius, this could be a platform policy with setup item + } + + // _PSS (Performance Supported States) + // + // This optional object indicates to OSPM the number of supported processor performance states that any given system can support. + // + // Arguments: (1) + // None + // Return Value: + // A variable-length Package containing a list of Pstate sub-packages as described below + // + // Return Value Information + // Package { + // PState [0] // Package - Performance state 0 + // .... + // PState [n] // Package - Performance state n + // } + // + // Each Pstate sub-Package contains the elements described below: + // Package { + // CoreFrequency // Integer (DWORD) + // Power // Integer (DWORD) + // Latency // Integer (DWORD) + // BusMasterLatency // Integer (DWORD) + // Control // Integer (DWORD) + // Status // Integer (DWORD) + // } + // + Method(_PSS,,,,PkgObj) + { + Store ("cpudptf: _PSS Called", Debug) + If (CondRefOf(\_PR.CPU0._PSS)) { + // Ensure _PSS is present + Return(\_PR.CPU0._PSS()) + } Else { + Return(Package() + { + Package(){0,0,0,0,0,0}, + Package(){0,0,0,0,0,0} + }) + } + } + + // _TSS (Throttling Supported States) + // + // Arguments: (0) + // None + // Return Value: + // A variable-length Package containing a list of Tstate sub-packages as described below + // + // Return Value Information + // Package { + // TState [0] // Package - Throttling state 0 + // .... + // TState [n] // Package - Throttling state n + // } + // + // Each Tstate sub-Package contains the elements described below: + // Package { + // Percent // Integer (DWORD) + // Power // Integer (DWORD) + // Latency // Integer (DWORD) + // Control // Integer (DWORD) + // Status // Integer (DWORD) + // } + // + Method(_TSS,,,,PkgObj) + { + Store ("cpudptf: _TSS Called", Debug) + If (CondRefOf(\_PR.CPU0._TSS)) { + // Ensure _TSS is present + Return(\_PR.CPU0._TSS()) + } Else { + Return(Package() + { + Package(){0,0,0,0,0}, + Package(){0,0,0,0,0} + }) + } + } + + // _TPC (Throttling Present Capabilities) + // + // This optional object is a method that dynamically indicates to OSPM the number of throttling states currently supported by the platform. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the number of states supported: + // 0 - states 0 .. nth state available (all states available) + // 1 - state 1 .. nth state available + // 2 - state 2 .. nth state available + // ... + // n - state n available only + // + Method(_TPC) + { + Store ("cpudptf: _TPC Called", Debug) + If (CondRefOf(\_PR.CPU0._TPC)) { + Return(\_PR.CPU0._TPC) + } Else { + Return(0) + } + } + + // _PTC (Processor Throttling Control) + // + // _PTC is an optional object that defines a processor throttling control interface alternative to the I/O address spaced-based P_BLK throttling control register (P_CNT) + // + // Arguments: (0) + // None + // Return Value: + // A Package as described below + // + // Return Value Information + // Package { + // ControlRegister // Buffer (Resource Descriptor) + // StatusRegister // Buffer (Resource Descriptor) + // } + // + Method(_PTC) + { + Store ("cpudptf: _PTC Called", Debug) + If (CondRefOf(\_PR.CPU0._PTC)) { + Return(\_PR.CPU0._PTC()) + } Else { + Return(Package(){ + ResourceTemplate (){Register (FFixedHW,0,0,0)}, + ResourceTemplate (){Register (FFixedHW,0,0,0)} + }) + } + } + + // _TSD (T-State Dependency) + // + // This optional object provides T-state control cross logical processor dependency information to OSPM. + // + // Arguments: (0) + // None + // Return Value: + // A variable-length Package containing a list of T-state dependency Packages as described below. + // + // Return Value Information + // Package { + // NumEntries // Integer + // Revision // Integer (BYTE) + // Domain // Integer (DWORD) + // CoordType // Integer (DWORD) + // NumProcessors // Integer (DWORD) + // } + // + Method(_TSD,,,,PkgObj) + { + Store ("cpudptf: _TSD Called", Debug) + If (CondRefOf(\_PR.CPU0._TSD)) { + // Ensure _TSD is present + Return(\_PR.CPU0._TSD()) + } Else { + Return(Package() + { + Package(){5,0,0,0,0}, + Package(){5,0,0,0,0} + }) + } + } + + // _TDL (T-state Depth Limit) + // + // This optional object evaluates to the _TSS entry number of the lowest power throttling state that OSPM may use. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the Throttling Depth Limit _TSS entry number: + // 0 - throttling disabled. + // 1 - state 1 is the lowest power T-state available. + // 2 - state 2 is the lowest power T-state available. + // ... + // n - state n is the lowest power T-state available. + // + Method(_TDL) + { + Store ("cpudptf: _TDL Called", Debug) + If (CondRefOf(\_PR.CPU0._TDL)) { + Return(\_PR.CPU0._TDL()) + } Else { + Return(0) + } + } + + // _PDL (P-state Depth Limit) + // + // This optional object evaluates to the _PSS entry number of the lowest performance P-state that OSPM may use when performing passive thermal control. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the P-state Depth Limit _PSS entry number: + // Integer containing the P-state Depth Limit _PSS entry number: + // 0 - P0 is the only P-state available for OSPM use + // 1 - state 1 is the lowest power P-state available + // 2 - state 2 is the lowest power P-state available + // ... + // n - state n is the lowest power P-state available + // + Method(_PDL) + { + Store ("cpudptf: _PDL Called", Debug) + If (CondRefOf(\_PR.CPU0._PSS)) { + // Ensure _PSS is present + // OSSL means OS Selection, WOS is Zero, AOS is One + If (LEqual(\OSSL,1)) { + Return(Subtract(SizeOf(\_PR.CPU0.SPSS),1)) // PSS entry for AOS + } Else { + Return(Subtract(SizeOf(\_PR.CPU0.NPSS),1)) // PSS entry for WOS + } + } Else { + Return(0) + } + } + + // _TSP (Thermal Sampling Period) + // + // Sets the polling interval in 10ths of seconds. A value of 0 tells the driver to use interrupts. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the polling rate in tenths of seconds. + // A value of 0 will specify using interrupts through the ACPI notifications. + // + // The granularity of the sampling period is 0.1 seconds. For example, if the sampling period is 30.0 + // seconds, then _TSP needs to report 300; if the sampling period is 0.5 seconds, then it will report 5. + // + Method(_TSP,0,Serialized) + { + Return(\CPUS) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC0,0,Serialized) + { + If (LEqual(\DPAT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\DPAT)) // Active Cooling Policy + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC1,0,Serialized) + { + If (LEqual(\DPAT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(Subtract(\_SB.IETM.CTOK(\DPAT),200)) // 20 degrees less than _AC0 + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC2,0,Serialized) + { + If (LEqual(\DPAT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(Subtract(\_SB.IETM.CTOK(\DPAT),300)) // 30 degrees less than _AC0 + } + + // _PSV (Passive) + // + // This optional object, if present under a thermal zone, evaluates to the temperature + // at which OSPM must activate passive cooling policy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the passive cooling temperature threshold in tenths of degrees Kelvin + // + Method(_PSV,0,Serialized) + { + If (LEqual(\DPPT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\DPPT)) // Passive Cooling Policy. Have this in Global NVS + } + + // _CRT (Critical Temperature) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM must shutdown the system. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CRT,0,Serialized) + { + If (LEqual(\DPCT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\DPCT)) + } + + // _CR3 (Critical Temperature for S3/CS) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM + // must transition to Standby or Connected Standy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CR3,0,Serialized) + { + If (LEqual(\DPC3,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\DPC3)) + } + + // _HOT (Hot Temperature) + // + // This optional object, when defined under a thermal zone, returns the critical temperature + // at which OSPM may choose to transition the system into the S4 sleeping state. + // + // Arguments: (0) + // None + // Return Value: + // The return value is an integer that represents the critical sleep threshold tenths of degrees Kelvin. + // + Method(_HOT,0,Serialized) + { + If (LEqual(\DPHT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\DPHT)) + } + + // _SCP (Set Cooling Policy) + // + // Arguments: (3) + // Arg0 - Mode An Integer containing the cooling mode policy code + // Arg1 - AcousticLimit An Integer containing the acoustic limit + // Arg2 - PowerLimit An Integer containing the power limit + // Return Value: + // None + // + // Argument Information: + // Mode - 0 = Active, 1 = Passive + // Acoustic Limit - Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit - Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // + Method(_SCP, 3, Serialized) + { + If (LOr(LEqual(Arg0,0),LEqual(Arg0,1))) { + Store(Arg0,CTYP) + Notify(TCPU, 0x91) + } + } + + Name(VERS,0) // Version + Name(CTYP, 0) // Device specific cooling policy type + Name(ALMT,0) // Acoustic Limit + Name(PLMT,0) // Power Limit + Name(WKLD,0) // Workload Hint + Name(DSTA,0) // Device State Hint + Name(RES1,0) // Reserved 1 + + // DSCP (DPTF Set Cooling Policy) + // + // Arguments: (7) + // Arg0 - Version: For DPTF 8.0, this value is always 0. + // Arg1 - Mode: Integer containing the cooling mode policy code + // Arg2 - Acoustic Limit: Acoustic Limit value as defined in ACPI specification + // Arg3 - Power Limit: Power Limit value as defined in ACPI specification + // Arg4 - Workload Hint: Arbitrary Platform defined Integer that indicates to the platform the type of workload run in the OS. + // Arg5 - Device State Hint: An integer value that indicates the state of the device. + // Arg6 - Reserved 1 + // Return Value: + // None + // + // Argument Information: + // Mode: 0 = Active(Typically AC Power Source), 1 = Passive(Typically Battery Power Source) + // Acoustic Limit: Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit: Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // Workload Hint: Refer to Intel DPTF Configuration Guide on how to set this value for various workloads for each Operating System. + // Device State Hint: An integer value that indicates the state of the device. + // First byte indicates portrait or landscape mode. + // Second byte indicates horizontal or vertical orientation. + // Third byte indicates proximity sensor status (if available). + // Fourth byte is unused. + // xxxxxx00h: Portrait + // xxxxxx01h: Landscape + // xxxx00xxh: Horizontal + // xxxx01xxh: Vertical + // xx00xxxxh: Proximity sensor Off (Device not in proximity to user) + // xx01xxxxh: Proximity sensor On (Device in proximity to user) + // + Method(DSCP, 7, Serialized) + { + If (LOr(LEqual(Arg1,0),LEqual(Arg1,1))) { + Store(Arg0, VERS) + Store(Arg1, CTYP) + Store(Arg2, ALMT) + Store(Arg3, PLMT) + Store(Arg4, WKLD) + Store(Arg5, DSTA) + Store(Arg6, RES1) + Notify(TCPU, 0x91) + } + } + + } // End Device(TCPU) +} // End Scope(\_SB.PCI0) + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Trt.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Trt.asl new file mode 100644 index 0000000000..f395fdebd6 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Trt.asl @@ -0,0 +1,52 @@ +/** @file + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(\_SB.IETM) +{ + // _TRT (Thermal Relationship Table) + // + // Arguments: (0) + // None + // Return Value: + // A variable-length Package containing a list of Thermal Relationship Packages as described below. + // + // Return Value Information + // Package { + // ThermalRelationship[0] // Package + // ... + // ThermalRelationship[n] // Package + // } + // + Name(_TRT, Package() + { + // Source Target Influence Period Reserved + Package(){\_SB.PCI0.TCPU, \_SB.SEN1, 10, 100, 0, 0, 0, 0} + }) + + // TRTR (Thermal Relationship Table Revision) + // + // This object evaluates to an integer value that defines the revision of the _TRT object. + // + // Arguments: (0) + // None + // Return Value: + // 0: Traditional TRT as defined by the ACPI Specification. + // 1: Priority based TRT + // + Method(TRTR) + { + Return(TRTV) + } + +} // End Scope(\_SB.IETM) + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Vir1Participant.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Vir1Participant.asl new file mode 100644 index 0000000000..a04bb908fb --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Vir1Participant.asl @@ -0,0 +1,454 @@ +/** @file + Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(\_SB) +{ + Device(VIR1) + { + Name(_HID, EISAID("INT3409")) // Intel DPTF Virtual Sensor Participant Device + Name(_UID, "VIR1") + Name(PTYP, 0x15) // TypeVirtualSensor + Name(_STR, Unicode ("Top_skin")) + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (LEqual(\VSP1,1)) { + Return(0x0F) + } Else { + Return(0x00) + } + } + + // Returns Number of Aux Trips available + Name(PATC, 0) + + Name(LSTM,0) // Last temperature reported + + // _DTI (Device Temperature Indication) + // + // Conveys the temperature of a device's internal temperature sensor to the platform when a temperature trip point + // is crossed or when a meaningful temperature change occurs. + // + // Arguments: (1) + // Arg0 - An Integer containing the current value of the temperature sensor (in tenths Kelvin) + // Return Value: + // None + // + Method(_DTI, 1) + { + Store(Arg0,LSTM) + Notify(\_SB.VIR1, 0x91) // notify the participant of a trip point change event + } + + // _NTT (Notification Temperature Threshold) + // + // Returns the temperature change threshold for devices containing native temperature sensors to cause + // evaluation of the _DTI object + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the temperature threshold in tenths of degrees Kelvin. + // + Method(_NTT, 0) + { + Return(2782) // 5 degree Celcius + } + + Name (VSCT, Package() + { + 1, + Package() + { + Package () {\_SB.GEN2, 14, 0, 600, 0, 300, 2932}, + Package () {"NA", 14, 2, 1000, 0, 100, 0} + } + }) + + Name (VSPT, Package() + { + 1, + Package() + { + Package () {3031, 100}, + Package () {3131, 50}, + Package () {3231, 10} + } + }) + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC0,0,Serialized) + { + If (LEqual(\V1AT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Store(\_SB.IETM.CTOK(\V1AT),Local1) + If (LGreaterEqual(LSTM,Local1)) { + Return(Subtract(Local1,20)) // subtract 2 degrees which is the Hysteresis + } + Else + { + Return(Local1) + } + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC1,0,Serialized) + { + Return(Subtract(_AC0(), 40)) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC2,0,Serialized) + { + Return(Subtract(_AC0(), 80)) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC3,0,Serialized) + { + Return(Subtract(_AC0(), 120)) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC4,0,Serialized) + { + Return(Subtract(_AC0(), 160)) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC5,0,Serialized) + { + Return(Subtract(_AC0(), 200)) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC6,0,Serialized) + { + Return(Subtract(_AC0(), 240)) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC7,0,Serialized) + { + Return(Subtract(_AC0(), 280)) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC8,0,Serialized) + { + Return(Subtract(_AC0(), 320)) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC9,0,Serialized) + { + Return(Subtract(_AC0(), 360)) + } + + // _PSV (Passive) + // + // This optional object, if present under a thermal zone, evaluates to the temperature + // at which OSPM must activate passive cooling policy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the passive cooling temperature threshold in tenths of degrees Kelvin + // + Method(_PSV,0,Serialized) + { + If (LEqual(\V1PV,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\V1PV)) + } + + // _CRT (Critical Temperature) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM must shutdown the system. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CRT,0,Serialized) + { + If (LEqual(\V1CR,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\V1CR)) + } + + // _CR3 (Critical Temperature for S3/CS) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM + // must transition to Standby or Connected Standy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CR3,0,Serialized) + { + If (LEqual(\V1C3,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\V1C3)) + } + + // _HOT (Hot Temperature) + // + // This optional object, when defined under a thermal zone, returns the critical temperature + // at which OSPM may choose to transition the system into the S4 sleeping state. + // + // Arguments: (0) + // None + // Return Value: + // The return value is an integer that represents the critical sleep threshold tenths of degrees Kelvin. + // + Method(_HOT,0,Serialized) + { + If (LEqual(\V1HT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\V1HT)) + } + + // _SCP (Set Cooling Policy) + // + // Arguments: (3) + // Arg0 - Mode An Integer containing the cooling mode policy code + // Arg1 - AcousticLimit An Integer containing the acoustic limit + // Arg2 - PowerLimit An Integer containing the power limit + // Return Value: + // None + // + // Argument Information: + // Mode - 0 = Active, 1 = Passive + // Acoustic Limit - Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit - Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // + Method(_SCP, 3, Serialized) + { + If (LOr(LEqual(Arg0,0),LEqual(Arg0,1))) { + Store(Arg0, CTYP) + Notify(\_SB.VIR1, 0x91) + } + } + + Name(VERS,0) // Version + Name(CTYP,0) // Mode + Name(ALMT,0) // Acoustic Limit + Name(PLMT,0) // Power Limit + Name(WKLD,0) // Workload Hint + Name(DSTA,0) // Device State Hint + Name(RES1,0) // Reserved 1 + + // DSCP (DPTF Set Cooling Policy) + // + // Arguments: (7) + // Arg0 - Version: For DPTF 8.0, this value is always 0. + // Arg1 - Mode: Integer containing the cooling mode policy code + // Arg2 - Acoustic Limit: Acoustic Limit value as defined in ACPI specification + // Arg3 - Power Limit: Power Limit value as defined in ACPI specification + // Arg4 - Workload Hint: Arbitrary Platform defined Integer that indicates to the platform the type of workload run in the OS. + // Arg5 - Device State Hint: An integer value that indicates the state of the device. + // Arg6 - Reserved 1 + // Return Value: + // None + // + // Argument Information: + // Mode: 0 = Active(Typically AC Power Source), 1 = Passive(Typically Battery Power Source) + // Acoustic Limit: Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit: Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // Workload Hint: Refer to Intel DPTF Configuration Guide on how to set this value for various workloads for each Operating System. + // Device State Hint: An integer value that indicates the state of the device. + // First byte indicates portrait or landscape mode. + // Second byte indicates horizontal or vertical orientation. + // Third byte indicates proximity sensor status (if available). + // Fourth byte is unused. + // xxxxxx00h: Portrait + // xxxxxx01h: Landscape + // xxxx00xxh: Horizontal + // xxxx01xxh: Vertical + // xx00xxxxh: Proximity sensor Off (Device not in proximity to user) + // xx01xxxxh: Proximity sensor On (Device in proximity to user) + // + Method(DSCP, 7, Serialized) + { + Name(CHNG,0) // Semaphore to record policy change + + If (LNotEqual(Arg0, 0)) { + Return // unsupported version + } + + If (LOr(LEqual(Arg1,0),LEqual(Arg1,1))) { + // bounds check + If (LNotEqual(Arg1, CTYP)) { + Store(1,CHNG) + Store(Arg1, CTYP) + } + } + + If (LOr(LGreaterEqual(Arg1,0),LLessEqual(Arg1,5))) { + // bounds check + If (LNotEqual(Arg2, ALMT)) { + Store(1, CHNG) + Store(Arg2, ALMT) + } + } + + If (LOr(LGreaterEqual(Arg1,0),LLessEqual(Arg1,5))) { + // bounds check + If (LNotEqual(Arg3, PLMT)) { + Store(1, CHNG) + Store(Arg3, PLMT) + } + } + + If (LNotEqual(Arg4, WKLD)) { + Store(1, CHNG) + Store(Arg4, WKLD) + } + + If (LNotEqual(Arg5, DSTA)) { + Store(1,CHNG) + Store(Arg5, DSTA) + } + + If (LNotEqual(Arg6, RES1)) { + Store(1, CHNG) + Store(Arg6, RES1) + } + + If (CHNG) { + // only notify when change occurrs + Notify(\_SB.VIR1, 0x91) + } + } // end Method(DSCP) + + } // End VIR1 Device +}// end Scope(\_SB) + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Vir2Participant.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Vir2Participant.asl new file mode 100644 index 0000000000..1974fd5dc1 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Vir2Participant.asl @@ -0,0 +1,454 @@ +/** @file + Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(\_SB) +{ + Device(VIR2) + { + Name(_HID, EISAID("INT3409")) // Intel DPTF Virtual Sensor Participant Device + Name(_UID, "VIR2") + Name(PTYP, 0x15) // TypeVirtualSensor + Name(_STR, Unicode ("Bot_skin")) + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (LEqual(\VSP2,1)){ + Return(0x0F) + } Else { + Return(0x00) + } + } + + // Returns Number of Aux Trips available + Name(PATC, 0) + + Name(LSTM,0) // Last temperature reported + + // _DTI (Device Temperature Indication) + // + // Conveys the temperature of a device's internal temperature sensor to the platform when a temperature trip point + // is crossed or when a meaningful temperature change occurs. + // + // Arguments: (1) + // Arg0 - An Integer containing the current value of the temperature sensor (in tenths Kelvin) + // Return Value: + // None + // + Method(_DTI, 1) + { + Store(Arg0,LSTM) + Notify(\_SB.VIR2, 0x91) // notify the participant of a trip point change event + } + + // _NTT (Notification Temperature Threshold) + // + // Returns the temperature change threshold for devices containing native temperature sensors to cause + // evaluation of the _DTI object + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the temperature threshold in tenths of degrees Kelvin. + // + Method(_NTT, 0) + { + Return(2782) // 5 degree Celcius + } + + Name (VSCT, Package() + { + 1, + Package() + { + Package () {\_SB.GEN1, 14, 0, 600, 0, 300, 2932}, + Package () {"NA", 14, 2, 1000, 0, 100, 0} + } + }) + + Name (VSPT, Package() + { + 1, + Package() + { + Package () {3031, 100}, + Package () {3131, 50}, + Package () {3231, 10} + } + }) + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC0,0,Serialized) + { + If (LEqual(\V2AT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Store(\_SB.IETM.CTOK(\V2AT),Local1) + If (LGreaterEqual(LSTM,Local1)) { + Return(Subtract(Local1,20)) // subtract 2 degrees which is the Hysteresis + } + Else + { + Return(Local1) + } + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC1,0,Serialized) + { + Return(Subtract(_AC0(), 40)) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC2,0,Serialized) + { + Return(Subtract(_AC0(), 80)) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC3,0,Serialized) + { + Return(Subtract(_AC0(), 120)) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC4,0,Serialized) + { + Return(Subtract(_AC0(), 160)) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC5,0,Serialized) + { + Return(Subtract(_AC0(), 200)) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC6,0,Serialized) + { + Return(Subtract(_AC0(), 240)) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC7,0,Serialized) + { + Return(Subtract(_AC0(), 280)) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC8,0,Serialized) + { + Return(Subtract(_AC0(), 320)) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC9,0,Serialized) + { + Return(Subtract(_AC0(), 360)) + } + + // _PSV (Passive) + // + // This optional object, if present under a thermal zone, evaluates to the temperature + // at which OSPM must activate passive cooling policy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the passive cooling temperature threshold in tenths of degrees Kelvin + // + Method(_PSV,0,Serialized) + { + If (LEqual(\V2PV,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\V2PV)) + } + + // _CRT (Critical Temperature) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM must shutdown the system. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CRT,0,Serialized) + { + If (LEqual(\V2CR,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\V2CR)) + } + + // _CR3 (Critical Temperature for S3/CS) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM + // must transition to Standby or Connected Standy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CR3,0,Serialized) + { + If (LEqual(\V2C3,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\V2C3)) + } + + // _HOT (Hot Temperature) + // + // This optional object, when defined under a thermal zone, returns the critical temperature + // at which OSPM may choose to transition the system into the S4 sleeping state. + // + // Arguments: (0) + // None + // Return Value: + // The return value is an integer that represents the critical sleep threshold tenths of degrees Kelvin. + // + Method(_HOT,0,Serialized) + { + If (LEqual(\V2HT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\V2HT)) + } + + // _SCP (Set Cooling Policy) + // + // Arguments: (3) + // Arg0 - Mode An Integer containing the cooling mode policy code + // Arg1 - AcousticLimit An Integer containing the acoustic limit + // Arg2 - PowerLimit An Integer containing the power limit + // Return Value: + // None + // + // Argument Information: + // Mode - 0 = Active, 1 = Passive + // Acoustic Limit - Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit - Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // + Method(_SCP, 3, Serialized) + { + If (LOr(LEqual(Arg0,0),LEqual(Arg0,1))) { + Store(Arg0, CTYP) + Notify(\_SB.VIR2, 0x91) + } + } + + Name(VERS,0) // Version + Name(CTYP,0) // Mode + Name(ALMT,0) // Acoustic Limit + Name(PLMT,0) // Power Limit + Name(WKLD,0) // Workload Hint + Name(DSTA,0) // Device State Hint + Name(RES1,0) // Reserved 1 + + // DSCP (DPTF Set Cooling Policy) + // + // Arguments: (7) + // Arg0 - Version: For DPTF 8.0, this value is always 0. + // Arg1 - Mode: Integer containing the cooling mode policy code + // Arg2 - Acoustic Limit: Acoustic Limit value as defined in ACPI specification + // Arg3 - Power Limit: Power Limit value as defined in ACPI specification + // Arg4 - Workload Hint: Arbitrary Platform defined Integer that indicates to the platform the type of workload run in the OS. + // Arg5 - Device State Hint: An integer value that indicates the state of the device. + // Arg6 - Reserved 1 + // Return Value: + // None + // + // Argument Information: + // Mode: 0 = Active(Typically AC Power Source), 1 = Passive(Typically Battery Power Source) + // Acoustic Limit: Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit: Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // Workload Hint: Refer to Intel DPTF Configuration Guide on how to set this value for various workloads for each Operating System. + // Device State Hint: An integer value that indicates the state of the device. + // First byte indicates portrait or landscape mode. + // Second byte indicates horizontal or vertical orientation. + // Third byte indicates proximity sensor status (if available). + // Fourth byte is unused. + // xxxxxx00h: Portrait + // xxxxxx01h: Landscape + // xxxx00xxh: Horizontal + // xxxx01xxh: Vertical + // xx00xxxxh: Proximity sensor Off (Device not in proximity to user) + // xx01xxxxh: Proximity sensor On (Device in proximity to user) + // + Method(DSCP, 7, Serialized) + { + Name(CHNG,0) // Semaphore to record policy change + + If (LNotEqual(Arg0, 0)) { + Return // unsupported version + } + + If (LOr(LEqual(Arg1,0),LEqual(Arg1,1))) { + // bounds check + If (LNotEqual(Arg1, CTYP)) { + Store(1,CHNG) + Store(Arg1, CTYP) + } + } + + If (LOr(LGreaterEqual(Arg1,0),LLessEqual(Arg1,5))) { + // bounds check + If (LNotEqual(Arg2, ALMT)) { + Store(1, CHNG) + Store(Arg2, ALMT) + } + } + + If (LOr(LGreaterEqual(Arg1,0),LLessEqual(Arg1,5))) { + // bounds check + If (LNotEqual(Arg3, PLMT)) { + Store(1, CHNG) + Store(Arg3, PLMT) + } + } + + If (LNotEqual(Arg4, WKLD)) { + Store(1, CHNG) + Store(Arg4, WKLD) + } + + If (LNotEqual(Arg5, DSTA)) { + Store(1,CHNG) + Store(Arg5, DSTA) + } + + If (LNotEqual(Arg6, RES1)) { + Store(1, CHNG) + Store(Arg6, RES1) + } + + If (CHNG) { + // only notify when change occurrs + Notify(\_SB.VIR2, 0x91) + } + } // end Method(DSCP) + + } // End VIR2 Device +}// end Scope(\_SB) + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Vir3Participant.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Vir3Participant.asl new file mode 100644 index 0000000000..54d3c93697 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/DptfAcpiTable/Vir3Participant.asl @@ -0,0 +1,454 @@ +/** @file + Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(\_SB) +{ + Device(VIR3) + { + Name(_HID, EISAID("INT3409")) // Intel DPTF Virtual Sensor Participant Device + Name(_UID, "VIR3") + Name(PTYP, 0x15) // TypeVirtualSensor + Name(_STR, Unicode ("Ambient")) + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (LEqual(\VSP3,1)) { + Return(0x0F) + } Else { + Return(0x00) + } + } + + // Returns Number of Aux Trips available + Name(PATC, 0) + + Name(LSTM,0) // Last temperature reported + + // _DTI (Device Temperature Indication) + // + // Conveys the temperature of a device's internal temperature sensor to the platform when a temperature trip point + // is crossed or when a meaningful temperature change occurs. + // + // Arguments: (1) + // Arg0 - An Integer containing the current value of the temperature sensor (in tenths Kelvin) + // Return Value: + // None + // + Method(_DTI, 1) + { + Store(Arg0,LSTM) + Notify(\_SB.VIR3, 0x91) // notify the participant of a trip point change event + } + + // _NTT (Notification Temperature Threshold) + // + // Returns the temperature change threshold for devices containing native temperature sensors to cause + // evaluation of the _DTI object + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the temperature threshold in tenths of degrees Kelvin. + // + Method(_NTT, 0) + { + Return(2782) // 5 degree Celcius + } + + Name (VSCT, Package() + { + 1, + Package() + { + Package () {\_SB.GEN3, 14, 0, 500, 0, 200, 2932}, + Package () {\_SB.GEN4, 14, 0, 500, 0, 300, 2932} + } + }) + + Name (VSPT, Package() + { + 1, + Package() + { + Package () {3031, 100}, + Package () {3131, 50}, + Package () {3231, 10} + } + }) + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC0,0,Serialized) + { + If (LEqual(\V3AT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Store(\_SB.IETM.CTOK(\V3AT),Local1) + If (LGreaterEqual(LSTM,Local1)) { + Return(Subtract(Local1,20)) // subtract 2 degrees which is the Hysteresis + } + Else + { + Return(Local1) + } + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC1,0,Serialized) + { + Return(Subtract(_AC0(), 40)) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC2,0,Serialized) + { + Return(Subtract(_AC0(), 80)) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC3,0,Serialized) + { + Return(Subtract(_AC0(), 120)) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC4,0,Serialized) + { + Return(Subtract(_AC0(), 160)) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC5,0,Serialized) + { + Return(Subtract(_AC0(), 200)) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC6,0,Serialized) + { + Return(Subtract(_AC0(), 240)) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC7,0,Serialized) + { + Return(Subtract(_AC0(), 280)) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC8,0,Serialized) + { + Return(Subtract(_AC0(), 320)) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC9,0,Serialized) + { + Return(Subtract(_AC0(), 360)) + } + + // _PSV (Passive) + // + // This optional object, if present under a thermal zone, evaluates to the temperature + // at which OSPM must activate passive cooling policy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the passive cooling temperature threshold in tenths of degrees Kelvin + // + Method(_PSV,0,Serialized) + { + If (LEqual(\V3PV,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\V3PV)) + } + + // _CRT (Critical Temperature) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM must shutdown the system. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CRT,0,Serialized) + { + If (LEqual(\V3CR,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\V3CR)) + } + + // _CR3 (Critical Temperature for S3/CS) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM + // must transition to Standby or Connected Standy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CR3,0,Serialized) + { + If (LEqual(\V3C3,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\V3C3)) + } + + // _HOT (Hot Temperature) + // + // This optional object, when defined under a thermal zone, returns the critical temperature + // at which OSPM may choose to transition the system into the S4 sleeping state. + // + // Arguments: (0) + // None + // Return Value: + // The return value is an integer that represents the critical sleep threshold tenths of degrees Kelvin. + // + Method(_HOT,0,Serialized) + { + If (LEqual(\V3HT,0)) {Return(0xFFFFFFFF)} // signal DPTF driver to disable trip point + Return(\_SB.IETM.CTOK(\V3HT)) + } + + // _SCP (Set Cooling Policy) + // + // Arguments: (3) + // Arg0 - Mode An Integer containing the cooling mode policy code + // Arg1 - AcousticLimit An Integer containing the acoustic limit + // Arg2 - PowerLimit An Integer containing the power limit + // Return Value: + // None + // + // Argument Information: + // Mode - 0 = Active, 1 = Passive + // Acoustic Limit - Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit - Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // + Method(_SCP, 3, Serialized) + { + If (LOr(LEqual(Arg0,0),LEqual(Arg0,1))) { + Store(Arg0, CTYP) + Notify(\_SB.VIR3, 0x91) + } + } + + Name(VERS,0) // Version + Name(CTYP,0) // Mode + Name(ALMT,0) // Acoustic Limit + Name(PLMT,0) // Power Limit + Name(WKLD,0) // Workload Hint + Name(DSTA,0) // Device State Hint + Name(RES1,0) // Reserved 1 + + // DSCP (DPTF Set Cooling Policy) + // + // Arguments: (7) + // Arg0 - Version: For DPTF 8.0, this value is always 0. + // Arg1 - Mode: Integer containing the cooling mode policy code + // Arg2 - Acoustic Limit: Acoustic Limit value as defined in ACPI specification + // Arg3 - Power Limit: Power Limit value as defined in ACPI specification + // Arg4 - Workload Hint: Arbitrary Platform defined Integer that indicates to the platform the type of workload run in the OS. + // Arg5 - Device State Hint: An integer value that indicates the state of the device. + // Arg6 - Reserved 1 + // Return Value: + // None + // + // Argument Information: + // Mode: 0 = Active(Typically AC Power Source), 1 = Passive(Typically Battery Power Source) + // Acoustic Limit: Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit: Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // Workload Hint: Refer to Intel DPTF Configuration Guide on how to set this value for various workloads for each Operating System. + // Device State Hint: An integer value that indicates the state of the device. + // First byte indicates portrait or landscape mode. + // Second byte indicates horizontal or vertical orientation. + // Third byte indicates proximity sensor status (if available). + // Fourth byte is unused. + // xxxxxx00h: Portrait + // xxxxxx01h: Landscape + // xxxx00xxh: Horizontal + // xxxx01xxh: Vertical + // xx00xxxxh: Proximity sensor Off (Device not in proximity to user) + // xx01xxxxh: Proximity sensor On (Device in proximity to user) + // + Method(DSCP, 7, Serialized) + { + Name(CHNG,0) // Semaphore to record policy change + + If (LNotEqual(Arg0, 0)) { + Return // unsupported version + } + + If (LOr(LEqual(Arg1,0),LEqual(Arg1,1))) { + // bounds check + If (LNotEqual(Arg1, CTYP)) { + Store(1,CHNG) + Store(Arg1, CTYP) + } + } + + If (LOr(LGreaterEqual(Arg1,0),LLessEqual(Arg1,5))) { + // bounds check + If (LNotEqual(Arg2, ALMT)) { + Store(1, CHNG) + Store(Arg2, ALMT) + } + } + + If (LOr(LGreaterEqual(Arg1,0),LLessEqual(Arg1,5))) { + // bounds check + If (LNotEqual(Arg3, PLMT)) { + Store(1, CHNG) + Store(Arg3, PLMT) + } + } + + If (LNotEqual(Arg4, WKLD)) { + Store(1, CHNG) + Store(Arg4, WKLD) + } + + If (LNotEqual(Arg5, DSTA)) { + Store(1,CHNG) + Store(Arg5, DSTA) + } + + If (LNotEqual(Arg6, RES1)) { + Store(1, CHNG) + Store(Arg6, RES1) + } + + If (CHNG) { + // only notify when change occurrs + Notify(\_SB.VIR3, 0x91) + } + } // end Method(DSCP) + + } // End VIR3 Device +}// end Scope(\_SB) + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Facp/Facp.aslc b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Facp/Facp.aslc new file mode 100644 index 0000000000..3123cd16e6 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Facp/Facp.aslc @@ -0,0 +1,182 @@ +/** @file + Fixed ACPI Description Table + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include "AcpiTablePlatform.h" + +EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = { + { + EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + sizeof (EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE), + EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION, + 0, // To make sum of entire table == 0 + EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field + EFI_ACPI_OEM_TABLE_ID, // OEM table identification (8 bytes long) + EFI_ACPI_OEM_REVISION, // OEM revision number + EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID + EFI_ACPI_CREATOR_REVISION // ASL compiler revision number + }, + 0, // Physical addesss of FACS + 0, // Physical address of DSDT + INT_MODEL, // System Interrupt Model (ignored in 2k and later, must be 0 for 98) + PM_PROFILE, // Preferred PM Profile + SCI_INT_VECTOR, // System vector of SCI interrupt + SMI_CMD_IO_PORT, // Port address of SMI command port + ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI + ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI + S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state + PSTATE_CNT, // PState control + PM1a_EVT_BLK, // Port address of Power Mgt 1a Event Reg Blk + PM1b_EVT_BLK, // Port address of Power Mgt 1b Event Reg Blk + PM1a_CNT_BLK, // Port address of Power Mgt 1a Ctrl Reg Blk + PM1b_CNT_BLK, // Port address of Power Mgt 1b Ctrl Reg Blk + PM2_CNT_BLK, // Port address of Power Mgt 2 Ctrl Reg Blk + PM_TMR_BLK, // Port address of Power Mgt Timer Ctrl Reg Blk + GPE0_BLK, // Port address of General Purpose Event 0 Reg Blk + GPE1_BLK, // Port address of General Purpose Event 1 Reg Blk + PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk + PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk + PM2_CNT_LEN, // Byte Length of ports at pm2_cnt_blk + PM_TM_LEN, // Byte Length of ports at pm_tm_blk + GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk + GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk + GPE1_BASE, // Offset in gpe model where gpe1 events start + CST_CNT, // _CST support + P_LVL2_LAT, // Worst case HW latency to enter/exit C2 state + P_LVL3_LAT, // Worst case HW latency to enter/exit C3 state + FLUSH_SIZE, // Size of area read to flush caches + FLUSH_STRIDE, // Stride used in flushing caches + DUTY_OFFSET, // Bit location of duty cycle field in p_cnt reg + DUTY_WIDTH, // Bit width of duty cycle field in p_cnt reg + DAY_ALRM, // Index to day-of-month alarm in RTC CMOS RAM + MON_ALRM, // Index to month-of-year alarm in RTC CMOS RAM + CENTURY, // Index to century in RTC CMOS RAM + IAPC_BOOT_ARCH, // IA-PCI Boot Architecture Flag + RESERVED, // Reserved + FLAG, + { + EFI_ACPI_5_0_SYSTEM_IO, + 8, + 0, + 0, + 0xCF9 + }, + 0x06, // Hardware reset value + 0, 0, 0, // Reserved + 0, // XFirmwareCtrl + 0, // XDsdt + // + // X_PM1a Event Register Block + // + EFI_ACPI_5_0_SYSTEM_IO, + 0x10, + 0x00, + EFI_ACPI_3_0_WORD, + PM1a_EVT_BLK, + + // + // X_PM1b Event Register Block + // + EFI_ACPI_5_0_SYSTEM_IO, + 0x00, + 0x00, + EFI_ACPI_RESERVED_BYTE, + PM1b_EVT_BLK, + + // + // X_PM1a Control Register Block + // + EFI_ACPI_5_0_SYSTEM_IO, + 0x10, + 0x00, + EFI_ACPI_5_0_WORD, + PM1a_CNT_BLK, + + // + // X_PM1b Control Register Block + // + EFI_ACPI_5_0_SYSTEM_IO, + 0x00, + 0x00, + EFI_ACPI_5_0_UNDEFINED, + PM1b_CNT_BLK, + + // + // X_PM2 Control Register Block + // + EFI_ACPI_5_0_SYSTEM_IO, + 0x08, + 0x00, + EFI_ACPI_5_0_BYTE, + PM2_CNT_BLK, + + // + // X_PM Timer Control Register Block + // + EFI_ACPI_5_0_SYSTEM_IO, + 0x20, + 0x00, + EFI_ACPI_5_0_DWORD, + PM_TMR_BLK, + + // + // X_General Purpose Event 0 Register Block + // + EFI_ACPI_5_0_SYSTEM_IO, + 0x100, + 0x00, + EFI_ACPI_5_0_BYTE, + GPE0_BLK, + + // + // X_General Purpose Event 1 Register Block + // + EFI_ACPI_5_0_SYSTEM_IO, + 0x00, + 0x00, + EFI_ACPI_5_0_UNDEFINED, + GPE1_BLK, + + // + // Sleep Control Register Block + // + EFI_ACPI_5_0_SYSTEM_IO, + 0x08, + 0x00, + EFI_ACPI_5_0_BYTE, + 0x405, + + // + // Sleep Status Register Block + // + EFI_ACPI_5_0_SYSTEM_IO, + 0x08, + 0x00, + EFI_ACPI_5_0_BYTE, + 0x401, +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from + // removing the data structure from the executable + // + return (VOID*)&FACP; +} diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Facs/Facs.aslc b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Facs/Facs.aslc new file mode 100644 index 0000000000..8bb6cfebde --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Facs/Facs.aslc @@ -0,0 +1,77 @@ +/** @file + Firmware ACPI Control Structure Table + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// +// Statements that include other files +// + +#include +#include +#include "AcpiTablePlatform.h" + +EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE FACS = { + EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, + sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE), + + // + // Hardware Signature will be updated at runtime + // + 0x00000000, //HardwareSignature + 0x00000000, //FirmwareWakingVector + 0x00000000, //GlobalLock + 0x00000000, //Flags + 0x0000000000000000, //XFirmwareWakingVector + EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, + EFI_ACPI_RESERVED_BYTE, //Reserved0[3] + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + 0x00000000, //OspmFlags + EFI_ACPI_RESERVED_BYTE, //Reserved1[24] + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from + // removing the data structure from the executable + // + return (VOID*)&FACS; +} diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/GloblNvs.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/GloblNvs.asl new file mode 100644 index 0000000000..b2f6f56093 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/GloblNvs.asl @@ -0,0 +1,478 @@ +/** @file + ACPI GNVS + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + // + // Define a Global region of ACPI NVS Region that may be used for any + // type of implementation. The starting offset and size will be fixed + // up by the System BIOS during POST. Note that the Size must be a word + // in size to be fixed up correctly. + // + + OperationRegion(GNVS, SystemMemory, 0xFFFF0000, 0xAA55) + Field(GNVS, AnyAcc, Lock, Preserve) + { + Offset(0), // Miscellaneous Dynamic Registers: +// Name-----Size-------Offset----Description + OSYS, 16, // (00) Operating System + LIDS, 8, // (02) Lid State (Lid Open = 1) + PWRS, 8, // (03) Power State (AC Mode = 1) + ACTT, 8, // (04) Active Trip Point + CRTT, 8, // (05) Critical Trip Point + DTS1, 8, // (06) Digital Thermal Sensor 1 Reading + DTS2, 8, // (07) Digital Thermal Sensor 2 Reading + APIC, 8, // (08) APIC Enabled by SBIOS (APIC Enabled = 1) + MPEN, 8, // (09) Number of Logical Processors if MP Enabled != 0 + CADL, 8, // (10) Current Attached Device List + CSTE, 16, // (11) Current Display State + NSTE, 16, // (13) Next Display State + NDID, 8, // (15) Number of Valid Device IDs + DID1, 32, // (16) Device ID 1 + DID2, 32, // (20) Device ID 2 + DID3, 32, // (24) Device ID 3 + DID4, 32, // (28) Device ID 4 + DID5, 32, // (32) Device ID 5 + BLCS, 8, // (36) Backlight Control Support + BRTL, 8, // (37) Brightness Level Percentage + ALSE, 8, // (38) ALS Enable + MORD, 8, // (39) Memory Overwrite Request Data + PPRP, 32, // (40) Physical Presence request operation response + PPRQ, 8, // (44) Physical Presence request operation + LPPR, 8, // (45) Last Physical Presence request operation + BDID, 8, // (46) Platform board id + ASLB, 32, // (47) IGD OpRegion base address + IBTT, 8, // (51) IGD Boot Display Device + IPAT, 8, // (52) IGD Panel Type CMOs option + ITVF, 8, // (53) IGD TV Format CMOS option + ITVM, 8, // (54) IGD TV Minor Format CMOS option + IPSC, 8, // (55) IGD Panel Scaling + IBLC, 8, // (56) IGD BLC Configuration + IBIA, 8, // (57) IGD BIA Configuration + ISSC, 8, // (58) IGD SSC Configuration + I409, 8, // (59) IGD 0409 Modified Settings Flag + I509, 8, // (60) IGD 0509 Modified Settings Flag + I609, 8, // (61) IGD 0609 Modified Settings Flag + I709, 8, // (62) IGD 0709 Modified Settings Flag + IDMS, 8, // (63) IGD DVMT Memory Size + IF1E, 8, // (64) IGD Function 1 Enable + GSMI, 8, // (65) GMCH SMI/SCI mode (0=SCI) + PAVP, 8, // (66) IGD PAVP data + OSCC, 8, // (67) PCIE OSC Control + NEXP, 8, // (68) Native PCIE Setup Value + DSEN, 8, // (69) _DOS Display Support Flag. + GPIC, 8, // (70) Global IOAPIC/8259 Interrupt Mode Flag. + CTYP, 8, // (71) Global Cooling Type Flag. + L01C, 8, // (72) Global L01 Counter. + DID6, 32, // (73) Device ID 6 + DID7, 32, // (77) Device ID 7 + DID8, 32, // (81) Device ID 8 + DID9, 32, // (85) Device ID 9 + DIDA, 32, // (89) Device ID 10 + DIDB, 32, // (93) Device ID 11 + DIDC, 32, // (97) Device ID 12 + DIDD, 32, // (101) Device ID 13 + DIDE, 32, // (105) Device ID 14 + DIDF, 32, // (109) Device ID 15 + NHLA, 32, // (113) HD-Audio NHLT ACPI address + NHLL, 32, // (117) HD-Audio NHLT ACPI length + ADFM, 32, // (121) HD-Audio DSP Feature Mask + PFLV, 8, // (125) Platform Flavor + BREV, 8, // (126) Board Rev + XHCI, 8, // (127) xHCI controller mode + PMEN, 8, // (128) PMIC enable/disable + IPUD, 8, // (129) IPU device Acpi type -- 0: Auto; 1: Acpi Igfx; 2: Acpi no Igfx + U21A, 32, // (130) HSUART2 BAR1 + GP0A, 32, // (134) GPIO0 BAR + GP0L, 32, // (138) GPIO0 BAR Length + GP1A, 32, // (142) GPIO1 BAR + GP1L, 32, // (146) GPIO1 BAR Length + GP2A, 32, // (150) GPIO2 BAR + GP2L, 32, // (154) GPIO2 BAR Length + GP3A, 32, // (158) GPIO3 BAR + GP3L, 32, // (162) GPIO3 BAR Length + GP4A, 32, // (166) GPIO4 BAR + GP4L, 32, // (170) GPIO4 BAR Length + eM0A, 32, // (174) eMMC BAR0 + eM0L, 32, // (178) eMMC BAR0 Length + eM1A, 32, // (182) eMMC BAR1 + eM1L, 32, // (186) eMMC BAR1 Length + DPTE, 8, // (190) DPTF Enable + S0DE, 8, // (191) EnableSen0Participant + S0PT, 8, // (192) PassiveThermalTripPointSen0 + S0C3, 8, // (193) CriticalThermalTripPointSen0S3 + S0HT, 8, // (194) HotThermalTripPointSen0 + S0CT, 8, // (195) CriticalThermalTripPointSen0 + CHGE, 8, // (196) DptfChargerDevice + DDSP, 8, // (197) DPTFDisplayDevice + DFAN, 8, // (198) DPTF Fan device + DPSR, 8, // (199) DPTF Processor device + DPCT, 32, // (200) DPTF Processor participant critical temperature + DPPT, 32, // (204) DPTF Processor participant passive temperature + DGC0, 32, // (208) DPTF Generic sensor0 participant critical temperature + DGP0, 32, // (212) DPTF Generic sensor0 participant passive temperature + DGC1, 32, // (216) DPTF Generic sensor1 participant critical temperature + DGP1, 32, // (220) DPTF Generic sensor1 participant passive temperature + DGC2, 32, // (224) DPTF Generic sensor2 participant critical temperature + DGP2, 32, // (228) DPTF Generic sensor2 participant passive temperature + DGC3, 32, // (232) DPTF Generic sensor3 participant critical temperature + DGP3, 32, // (236) DPTF Generic sensor3 participant passive temperature + DGC4, 32, // (240) DPTF Generic sensor3 participant critical temperature + DGP4, 32, // (244) DPTF Generic sensor3 participant passive temperature + DLPM, 8, // (248) DPTF Current low power mode setting + DSC0, 32, // (249) DPTF Critical threshold0 for SCU + DSC1, 32, // (253) DPTF Critical threshold1 for SCU + DSC2, 32, // (257) DPTF Critical threshold2 for SCU + DSC3, 32, // (261) DPTF Critical threshold3 for SCU + DSC4, 32, // (265) DPTF Critical threshold4 for SCU + , 8, // (269) Reserved + LPOE, 32, // (270) DPTF LPO Enable + LPPS, 32, // (274) P-State start index + LPST, 32, // (278) Step size + LPPC, 32, // (282) Power control setting + LPPF, 32, // (286) Performance control setting + DPME, 8, // (290) DPTF DPPM enable/disable + BCSL, 8, // (291) Battery charging solution 0-CLV 1-ULPMC + TPMA, 32, // (292) TPM Base Address + TPML, 32, // (296) TPM Length + PSSD, 8, // (300) PSS Device: 0 - None, 1 - Monzax 2K, 2 - Monzax 8K + MDMS, 8, // (301) Modem selection: 0: Disabled, 1: 7260; 2: 7360; + GPSM, 8, // (302) GNSS/GPS mode selection, 0: LPSS mode, 1: ISH mode + ADPM, 32, // (303) Hd-Audio DSP Post-Processing Module Mask + OSSL, 8, // (307) OS Selection 0: WOS 1:AOS: 2:Legacy OS + WIFD, 8, // (308) Wi-Fi Device Select 0: Lightning Peak 1: Broadcom: only used by BXT-M + DD1A, 32, // (309) IPC Bar0 Address + DD1L, 32, // (313) IPC Bar0 Length + DD3A, 32, // (317) IPC Bar1 Address + DD3L, 32, // (321) IPC Bar1 Length + BMDA, 32, // (325) IPC BIOS mail box data + BMIA, 32, // (329) IPC BIOS mail box interface + P2BA, 32, // (333) P2SB Base Address: only used by BXT-M + EDPV, 8, // (337) Check for eDP display device: only used by BXT-M + DIDX, 32, // (338) Device ID for eDP device: only used by BXT-M + EPCS, 8, // (342) SGX Feature Status + EMNA, 64, // (343) SGX Feature PRMRR Base address + ELNG, 64, // (351) SGX Feature PRMRR Length (854-861) + WCAS, 8, // (359) 0 - Disable, 1 - IMX214, 2 - IMX135 + UCAS, 8, // (360) 0 - Disable, 1 - OV2740 + ADOS, 8, // (361) 0 - Disable, 1 - WM8281, 2 - WM8998 +//------------------Delta between BXTM and BXTP-------------------- + D11A, 32, // (362) DMA1 BAR1 + D11L, 32, // (366) DMA1 BAR1 Length >> Not used in BXT + ECDB, 8, // (370) [CSDebugLightEC] EC Debug Light (CAPS LOCK) for when in Low Power S0 Idle State + ECLP, 8, // (371) EC Low Power Mode: 1 - Enabled, 0 - Disabled + ECNO, 8, // (372) [CSNotifyEC] EC Notification of Low Power S0 Idle State + EMOD, 8, // (373) Enable / Disable Modern Standby Mode + I21A, 32, // (374) I2C2 BAR1 + I21L, 32, // (378) I2C2 BAR1 Length + I31A, 32, // (382) I2C3 BAR1 + I31L, 32, // (386) I2C3 BAR1 Length + I41A, 32, // (390) I2C4 BAR1 + I41L, 32, // (394) I2C4 BAR1 Length + I51A, 32, // (398) I2C5 BAR1 + I51L, 32, // (402) I2C5 BAR1 Length + I61A, 32, // (406) I2C6 BAR1 + I61L, 32, // (410) I2C6 BAR1 Length + I71A, 32, // (414) I2C7 BAR1 + I71L, 32, // (418) I2C7 BAR1 Length + OTG0, 32, // (422) USB OTG BAR0 + OTG1, 32, // (426) USB OTG BAR1 + P10A, 32, // (430) PWM1 BAR0 + P10L, 32, // (434) PWM1 BAR0 Length + P11A, 32, // (438) PWM1 BAR1 + P11L, 32, // (442) PWM1 BAR1 Length + P21A, 32, // (446) PWM2 BAR1 + P21L, 32, // (450) PWM2 BAR1 Length >> Not used in BXT + P80D, 32, // (454) Port 80 Debug Port Value + PEP0, 8, // (458) [Rtd3P0dl] User selectable Delay for Device D0 transition. + PEPC, 16, // (459) [LowPowerS0IdleConstraint] PEP Constraints + // Bit[1:0] - SATA (0:None, 1:SATA Ports[all], 2:SATA Controller) + // [2] - En/Dis UART 0 + // [3] - UART 1 + // [4] - SDIO + // [5] - I2C 0 + // [6] - I2C 1 + // [7] - XHCI + // [8] - HD Audio (includes ADSP) + // [9] - Gfx + // [10] - EMMC + // [11] - SDXC + // [12] - CPU + PEPY, 8, // (461) [PepList] RTD3 PEP support list(BIT0 - GFx , BIT1 - Sata, BIT2 - UART, BIT3 - SDHC, Bit4 - I2C0, BIT5 - I2C1, Bit6 - XHCI, Bit7 - Audio) + PLCS, 8, // (462) [PL1LimitCS] set PL1 limit when entering CS + PLVL, 16, // (463) [PL1LimitCSValue] PL1 limit value + PSCP, 8, // (465) [PstateCapping] P-state Capping + PSVT, 8, // (466) Passive Trip Point + RCG0, 16, // (467) [RTD3Config0] RTD3 Config Setting + //(BIT0:ZPODD,BIT1:USB Camera Port4, BIT2/3:SATA Port3, Bit4/5:Sata Port1/2, Bit6:Card Reader, Bit7:WWAN, Bit8:WSB SIP FAB1 Card reader) + RTD3, 8, // (469) Runtime D3 support. + S0ID, 8, // (470) [LowPowerS0Idle] Low Power S0 Idle Enable + S21A, 32, // (471) SPI2 BAR1 + S21L, 32, // (475) SPI2 BAR1 Length + S31A, 32, // (479) SPI3 BAR1 + S31L, 32, // (483) SPI3 BAR1 Length + SD1A, 32, // (487) SDCard BAR1 + SD1L, 32, // (491) SDCard BAR1 Length + SI1A, 32, // (495) SDIO BAR1 + SI1L, 32, // (499) SDIO BAR1 Length + SP1A, 32, // (503) SPI BAR1 + SP1L, 32, // (507) SPI BAR1 Length + SPST, 8, // (511) [SataPortState] SATA port state, Bit0 - Port0, Bit1 - Port1, Bit2 - Port2, Bit3 - Port3 + U11A, 32, // (512) HSUART BAR1 + U11L, 32, // (516) HSUART BAR1 Length + U21L, 32, // (520) HSUART2 BAR1 Length + W381, 8, // (524) WPCN381U: only used by BXT-P + ECON, 8, // (525) Embedded Controller Availability Flag. + PB1E, 8, // (526) 10sec Power button support + // Bit0: 10 sec P-button Enable/Disable + // Bit1: Internal Flag + // Bit2: Rotation Lock flag, 0:unlock, 1:lock + // Bit3: Slate/Laptop Mode Flag, 0: Slate, 1: Laptop + // Bit4: Undock / Dock Flag, 0: Undock, 1: Dock + // Bit5: VBDL Flag. 0: VBDL is not called, 1: VBDL is called, Virtual Button Driver is loaded. + // Bit6: Reserved for future use. + // Bit7: EC 10sec PB Override state for S3/S4 wake up. + DBGS, 8, // (527) Debug State + IPUA, 32, // (528) IPU Base Address + BNUM, 8, // (532) Number of batteries + B0SC, 8, // (533) Battery 0 Stored Capacity + ECR1, 8, // (534) PciDelayOptimizationEcr + HVCO, 8, // (535) HPLL VCO + UBCB, 32, // (536) USB Type C OpRegion base address + SBTD, 8, // (540) SelectBtDevice + // + // DPPM Devices and trip points + // + DPAT, 32, // (541) DptfProcActiveTemperature + , 8, // + , 8, // + , 8, // + , 8, // + , 8, // + Offset(550), + S1DE, 8, // (550) EnableSen1Participant + S1AT, 8, // (551) ActiveThermalTripPointSen1 + S1PT, 8, // (552) PassiveThermalTripPointSen1 + S1CT, 8, // (553) CriticalThermalTripPointSen1 + SSP1, 8, // (554) SensorSamplingPeriodSen1 + // + // DPPM Policies + // + DPAP, 8, // (555) EnableActivePolicy + DPPP, 8, // (556) EnablePassivePolicy + DPCP, 8, // (557) EnableCriticalPolicy + , 8, // (558) DPTF Reserved + + TC1V, 8, // (559) Passive Trip Point TC1 Value + TC2V, 8, // (560) Passive Trip Point TC2 Value + TSPV, 8, // (561) Passive Trip Point TSP Value + DTSE, 8, // (562) Digital Thermal Sensor Enable + , 8, // (563) Dptf Reserved + IGDS, 8, // (564) IGD State + HPME, 8, // (565) Enable/Disable HighPerformance mode for Dptf + WWEN, 8, // (566) WWAN Enable + // + // Offset (567) to (572) used by BXT-M DPTF + // + Offset(573), + PASL, 8, // (573) Panel AOB 0 - Disable, 1 - TIANMA , 2 - TRULY Fab B TypeC, 3 - TRULY Fab B, 4 -TRULY Fab B Command Mode, 5 - TRULY Fab B Command Mode TypeC + IRMC, 8, // (574) IRMT CONFIGURATION + CPUS, 8, // (575) ThermalSamplingPeriodTCPU + STEP, 8, // (576) BXT Stepping ID + RVD1, 8, // (577) Reserved + LTR1, 8, // (578) Latency Tolerance Reporting Enable + LTR2, 8, // (579) Latency Tolerance Reporting Enable + LTR3, 8, // (580) Latency Tolerance Reporting Enable + LTR4, 8, // (581) Latency Tolerance Reporting Enable + LTR5, 8, // (582) Latency Tolerance Reporting Enable + LTR6, 8, // (583) Latency Tolerance Reporting Enable + OBF1, 8, // (584) Optimized Buffer Flush and Fill + OBF2, 8, // (585) Optimized Buffer Flush and Fill + OBF3, 8, // (586) Optimized Buffer Flush and Fill + OBF4, 8, // (587) Optimized Buffer Flush and Fill + OBF5, 8, // (588) Optimized Buffer Flush and Fill + OBF6, 8, // (589) Optimized Buffer Flush and Fill + RPA1, 32, // (590) Root Port address 1 + RPA2, 32, // (594) Root Port address 2 + RPA3, 32, // (598) Root Port address 3 + RPA4, 32, // (602) Root Port address 4 + RPA5, 32, // (606) Root Port address 5 + RPA6, 32, // (610) Root Port address 6 + PML1, 16, // (614) PCIE LTR max snoop Latency 1 + PML2, 16, // (616) PCIE LTR max snoop Latency 2 + PML3, 16, // (618) PCIE LTR max snoop Latency 3 + PML4, 16, // (620) PCIE LTR max snoop Latency 4 + PML5, 16, // (622) PCIE LTR max snoop Latency 5 + PML6, 16, // (624) PCIE LTR max snoop Latency 6 + PNL1, 16, // (626) PCIE LTR max no snoop Latency 1 + PNL2, 16, // (628) PCIE LTR max no snoop Latency 2 + PNL3, 16, // (630) PCIE LTR max no snoop Latency 3 + PNL4, 16, // (632) PCIE LTR max no snoop Latency 4 + PNL5, 16, // (634) PCIE LTR max no snoop Latency 5 + PNL6, 16, // (636) PCIE LTR max no snoop Latency 6 + TRTV, 8, // (638) TrtRevision + WWPS, 32, // (639) WWAN PSV + PWRE, 8, // (643) EnablePowerParticipant + PBPE, 8, // (644) EnablePowerBossPolicy + HGEN, 8, // (645) HG Enabled (0=Disabled, 1=Enabled) + XBAS, 32, // (646) Any Device's PCIe Config Space Base Address + DLPW, 16, // (650) Delay after Power Enable + DLHR, 16, // (652) Delay after Hold Reset + HRCO, 32, // (654) dGPU HLD RST GPIO Community Offset + HRPO, 16, // (658) dGPU HLD RST GPIO Pin Offset + HRAI, 8, // (660) dGPU HLD RST GPIO Active Information + PECO, 32, // (661) dGPU PWR Enable GPIO Community Offset + PEPO, 16, // (665) dGPU PWR Enable GPIO Pin Offset + PEAI, 8, // (667) dGPU PWR Enable GPIO Active Information + SCBN, 8, // (668) PCIe Endpoint Bus Number + EECP, 8, // (669) PCIe Endpoint PCIe Capability Structure Offset + RPBA, 32, // (670) dGPU Root Port Base Address + NVGA, 32, // (674) NVIG opregion address + NVHA, 32, // (678) NVHM opregion address + AMDA, 32, // (682) AMDA opregion address + GN1E, 8, // (686) EnableGen1Participant + GN2E, 8, // (687) EnableGen2Participant + GN3E, 8, // (688) EnableGen3Participant + GN4E, 8, // (689) EnableGen4Participant + G1AT, 8, // (690) ActiveThermalTripPointGen1 + G1PT, 8, // (691) PassiveThermalTripPointGen1 + G1CT, 8, // (692) CriticalThermalTripPointGen1 + G1HT, 8, // (693) HotThermalTripPointGen1 + G1C3, 8, // (694) CriticalThermalTripPointGen1S3 + TSP1, 8, // (695) ThermistorSamplingPeriodGen1 + G2AT, 8, // (696) ActiveThermalTripPointGen2 + G2PT, 8, // (697) PassiveThermalTripPointGen2 + G2CT, 8, // (698) CriticalThermalTripPointGen2 + G2HT, 8, // (699) HotThermalTripPointGen2 + G2C3, 8, // (700) CriticalThermalTripPointGen2S3 + TSP2, 8, // (701) ThermistorSamplingPeriodGen2 + G3AT, 8, // (702) ActiveThermalTripPointGen3 + G3PT, 8, // (703) PassiveThermalTripPointGen3 + G3CT, 8, // (704) CriticalThermalTripPointGen3 + G3HT, 8, // (705) HotThermalTripPointGen3 + G3C3, 8, // (706) CriticalThermalTripPointGen3S3 + TSP3, 8, // (707) ThermistorSamplingPeriodGen3 + G4AT, 8, // (708) ActiveThermalTripPointGen4 + G4PT, 8, // (709) PassiveThermalTripPointGen4 + G4CT, 8, // (710) CriticalThermalTripPointGen4 + G4HT, 8, // (711) HotThermalTripPointGen4 + G4C3, 8, // (712) CriticalThermalTripPointGen4S3 + TSP4, 8, // (713) ThermistorSamplingPeriodGen4 + DPC3, 32, // (714) DptfProcCriticalTemperatureS3 + DPHT, 32, // (718) DptfProcHotThermalTripPoint + S1S3, 8, // (722) CriticalThermalTripPointSen1S3 + S1HT, 8, // (723) HotThermalTripPointSen1 + PCSP, 8, // (724) PMIC Stepping + IOBF, 8, // (725) ScHdAudioIoBufferOwnership + XDCE, 8, // (726) Xdci Enabled + RSVD, 16, // (727) Reserved[2] + VTKB, 8, // (729) Virtual keyboard Function 0- Disable 1- Discrete Touch 2- Integrated Touch + // + //WiGig for BXTM B0 + // + WGEN, 8, // (730) WiGig Enable switch, for BXTM B0 + WGPL, 16, // (731) WiGig SPLC Power Limit + WGTW, 32, // (733) WiGig SPLC Time Window + + PSME, 8, // (737) WiGig Power sharing manager enabling + PSD0, 8, // (738) WiGig PSM SPLC0 Domain Type + PSP0, 16, // (739) WiGig PSM SPLC0 Power Limit + PST0, 32, // (741) WiGig PSM SPLC0 Time Window + PSD1, 8, // (745) WiGig PSM SPLC1 Domain Type + PSP1, 16, // (746) WiGig PSM SPLC1 Power Limit + PST1, 32, // (748) WiGig PSM SPLC1 Time Window + + PDD0, 8, // (752) WiGig PSM DPLC0 Domain Type + PDP0, 8, // (753) WiGig PSM DPLC0 Domain Preference + PDI0, 8, // (754) WiGig PSM DPLC0 Power Limit Index + PDL0, 16, // (755) WiGig PSM DPLC0 Power Limit + PDT0, 32, // (757) WiGig PSM DPLC0 Time Window + + PDD1, 8, // (761) WiGig PSM DPLC1 Domain Type + PDP1, 8, // (762) WiGig PSM DPLC1 Domain Preference + PDI1, 8, // (763) WiGig PSM DPLC1 Power Limit Index + PDL1, 16, // (764) WiGig PSM DPLC1 Power Limit + PDT1, 32, // (766) WiGig PSM DPLC1 Time Window + IS3A, 8, // (770) I2S audio codec device - INT343A + ISC1, 8, // (771) I2S audio codec device - INT34C1 + NFCN, 8, // (772) I2C NFC device - NXP1001 + PSSI, 8, // (773) I2S PSS device - IMPJ0003 + , 8, // (774) (not used) + GSBC, 8, // (775) UART GPS device - BCM4752 + + AG1L, 64, // (776) + AG1H, 64, // (784) + AG2L, 64, // (792) + AG2H, 64, // (800) + AG3L, 64, // (808) + AG3H, 64, // (816) + + PPPR, 16, // (824) PowerParticipantPollingRate + DCFE, 16, // (826) EnableDCFG (DPTF Configuration) + + ODV0, 8, // (828) DPTF OemDesignVariable0 + ODV1, 8, // (829) DPTF OemDesignVariable1 + ODV2, 8, // (830) DPTF OemDesignVariable2 + ODV3, 8, // (831) DPTF OemDesignVariable3 + ODV4, 8, // (832) DPTF OemDesignVariable4 + ODV5, 8, // (833) DPTF OemDesignVariable5 + + VSP1, 8, // (834) EnableVS1Participant + V1AT, 8, // (835) ActiveThermalTripPointVS1 + V1PV, 8, // (836) PassiveThermalTripPointVS1 + V1CR, 8, // (837) CriticalThermalTripPointVS1 + V1C3, 8, // (838) CriticalThermalTripPointVS1S3 + V1HT, 8, // (839) HotThermalTripPointVS1 + VSP2, 8, // (840) EnableVS2Participant + V2AT, 8, // (841) ActiveThermalTripPointVS2 + V2PV, 8, // (842) PassiveThermalTripPointVS2 + V2CR, 8, // (843) CriticalThermalTripPointVS2 + V2C3, 8, // (844) CriticalThermalTripPointVS2S3 + V2HT, 8, // (845) HotThermalTripPointVS2 + VSP3, 8, // (846) EnableVS3Participant + V3AT, 8, // (847) ActiveThermalTripPointVS3 + V3PV, 8, // (848) PassiveThermalTripPointVS3 + V3CR, 8, // (849) CriticalThermalTripPointVS3 + V3C3, 8, // (850) CriticalThermalTripPointVS3S3 + V3HT, 8, // (851) HotThermalTripPointVS3 + + VSPE, 8, // (852) EnableVsPolicy + SDS1, 8, // (853) SPI1 Fingerprint device - FPC1020/FPC1021 + NFCS, 8, // (854) NFC device select: 0: disabled; 1: NFC (IPT)/secure NFC; 2: NFC; + , 16, // (855) reserved + , 32, // (857) reserved + PNSL, 8, // (861) Panel Selection (0=eDP, >=1 for MIPI) + EEPI, 8, // (862) EPIEnable + ETYC, 8, // (863) TypeCEnable + WWPT, 8, // (864) PassiveThermalTripPointWWAN + WWC3, 8, // (865) CriticalThermalTripPointWWANS3 + WWHT, 8, // (866) HotThermalTripPointWWAN + WWCT, 8, // (867) CriticalThermalTripPointWWAN + DPHL, 8, // (868) DisplayHighLimit + DPLL, 8, // (869) DisplayLowLimit + ODBG, 8, // (871) OsDbgEnable + M32B, 32, // (874) PCIE MMIO resource base + M32L, 32, // (878) PCIE MMIO resource length + CROT, 8, // (883) Camera Sensor Rotation Angle + TCPL, 8, // (884) I2c Touch Panel + TCPD, 8, // (885) I2c Touch pad + IC0S, 32, // (886) I2C0 Speed - Standard mode/Fast mode/FastPlus mode/HighSpeed mode + IC1S, 32, // (890) I2C1 Speed - Standard mode/Fast mode/FastPlus mode/HighSpeed mode + IC2S, 32, // (894) I2C2 Speed - Standard mode/Fast mode/FastPlus mode/HighSpeed mode + IC3S, 32, // (898) I2C3 Speed - Standard mode/Fast mode/FastPlus mode/HighSpeed mode + IC4S, 32, // (902) I2C4 Speed - Standard mode/Fast mode/FastPlus mode/HighSpeed mode + IC5S, 32, // (906) I2C5 Speed - Standard mode/Fast mode/FastPlus mode/HighSpeed mode + IC6S, 32, // (910) I2C6 Speed - Standard mode/Fast mode/FastPlus mode/HighSpeed mode + IC7S, 32, // (914) I2C7 Speed - Standard mode/Fast mode/FastPlus mode/HighSpeed mode +} + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Gpe.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Gpe.asl new file mode 100644 index 0000000000..e0bc9326ae --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Gpe.asl @@ -0,0 +1,73 @@ +/** @file + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + +// General Purpose Events. This Scope handles the Run-time and +// Wake-time SCIs. The specific method called will be determined by +// the _Lxx value, where xx equals the bit location in the General +// Purpose Event register(s). + +External(HGLS, MethodObj) +External(HGAS, MethodObj) + +Scope(\_GPE) +{ + Method(_L0D, 0) { + Notify(\_SB.PCI0.XHC, 0x02) + } + + Method(_L0E, 0) { + Notify(\_SB.PCI0.HDAS, 0x02) + } + + // Dummy method for the Tier 1 GPIO SCI enable bit + Method(_L0F, 0) {} + + Method(_L39){ + // Required for ACPI 5.0 native Windows support + Notify(\_SB.PCI0.SATA.PRT0, 2) // Device Wake (Windows) + } + + Method(_L08, 0) { + \_SB.PCI0.RP02.HPME() + Notify(\_SB.PCI0.RP02, 0x02) + } + + Method(_L09, 0) { + If (LEqual(RP1D,0)) { + \_SB.PCI0.RP01.HPME() + Notify(\_SB.PCI0.RP01, 0x02) + } + If(LEqual(RP2D,0)) { + \_SB.PCI0.RP02.HPME() + Notify(\_SB.PCI0.RP02, 0x02) + } + If(LEqual(RP3D,0)) { + \_SB.PCI0.RP03.HPME() + Notify(\_SB.PCI0.RP03, 0x02) + } + If(LEqual(RP4D,0)) { + \_SB.PCI0.RP04.HPME() + Notify(\_SB.PCI0.RP04, 0x02) + } + If(LEqual(RP5D,0)) { + \_SB.PCI0.RP05.HPME() + Notify(\_SB.PCI0.RP05, 0x02) + } + If(LEqual(RP6D,0)) { + \_SB.PCI0.RP06.HPME() + Notify(\_SB.PCI0.RP06, 0x02) + } + } +} + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/GpioLib.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/GpioLib.asl new file mode 100644 index 0000000000..c1166a4077 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/GpioLib.asl @@ -0,0 +1,163 @@ +/** @file + Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +include ("BxtPGpioDefine.asl") + +// +// GPIO Access Library +// +Scope(\_SB) +{ + // + // Get Pad Configuration DW0 register value + // + Method(GPC0, 0x1, Serialized) + { + // + // Arg0 - (GpioCommunityAddress + Gpio MMIO_Offset) + // + + // Local0 = (GpioCommunityAddress + Gpio MMIO_Offset) + Store(Arg0, Local0) + OperationRegion(PDW0, SystemMemory, Or (P2BA, Local0), 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + TEMP,32 + } + Return(TEMP) + } + + // + // Set Pad Configuration DW0 register value + // + Method(SPC0, 0x2, Serialized) + { + // + // Arg0 - (GpioCommunityAddress + Gpio MMIO_Offset) + // Arg1 - Value for DW0 register + // + + // Local0 = (GpioCommunityAddress + Gpio MMIO_Offset) + Store(Arg0, Local0) + OperationRegion(PDW0, SystemMemory, Or (P2BA, Local0), 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + TEMP,32 + } + Store(Arg1,TEMP) + } + + // + // Get Pad Configuration DW1 register value + // + Method(GPC1, 0x1, Serialized) + { + // + // Arg0 -Local0 = (GpioCommunityAddress + Gpio MMIO_Offset) + 0x4 + // + + // Local0 = (GpioCommunityAddress + Gpio MMIO_Offset) + 0x4 + Store( Add( Arg0, 0x4), Local0) + OperationRegion(PDW1, SystemMemory, Or (P2BA, Local0), 4) + Field(PDW1, AnyAcc, NoLock, Preserve) { + Offset(0x0), + TEMP,32 + } + Return(TEMP) + } + + // + // Set Pad Configuration DW1 register value + // + Method(SPC1, 0x2, Serialized) + { + // + // Arg0 - (GpioCommunityAddress + Gpio MMIO_Offset) + 0x4 + // Arg1 - Value for DW1 register + // + + // Local0 = (GpioCommunityAddress + Gpio MMIO_Offset) + 0x4 + Store( Add( Arg0, 0x4), Local0) + OperationRegion(PDW1, SystemMemory, Or (P2BA, Local0), 4) + Field(PDW1, AnyAcc, NoLock, Preserve) { + Offset(0x0), + TEMP,32 + } + Store(Arg1,TEMP) + } + + // + // Get GPI Input Value + // + Method(GGIV, 0x1, Serialized) + { + // + // Arg0 - (GpioCommunityAddress + Gpio MMIO_Offset) + // + + // Local0 = (GpioCommunityAddress + Gpio MMIO_Offset) + Store( Arg0, Local0) + OperationRegion(PDW0, SystemMemory, Or (P2BA, Local0), 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + , 1, + TEMP,1, + , 30 + } + Return(TEMP) + } + + // + // Get GPO Output Value + // + Method(GGOV, 0x1, Serialized) + { + // + // Arg0 - (GpioCommunityAddress + Gpio MMIO_Offset) + // + + // Local0 = (GpioCommunityAddress + Gpio MMIO_Offset) + Store( Arg0, Local0) + OperationRegion(PDW0, SystemMemory, Or (P2BA, Local0), 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + TEMP,1, + , 31 + } + Return(TEMP) + } + + // + // Set GPO Output Value + // + Method(SGOV, 0x2, Serialized) + { + // + // Arg0 - (GpioCommunityAddress + Gpio MMIO_Offset) + // Arg1 - Value of GPIO Tx State + // + + // Local0 = (GpioCommunityAddress + Gpio MMIO_Offset) + Store( Arg0, Local0) + OperationRegion(PDW0, SystemMemory, Or (P2BA, Local0), 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + TEMP,1, + , 31 + } + Store(Arg1,TEMP) + } + +} // \_SB Scope + + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/HOST_BUS.ASL b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/HOST_BUS.ASL new file mode 100644 index 0000000000..059259d141 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/HOST_BUS.ASL @@ -0,0 +1,334 @@ +/** @file + This file contains the Broxton PCI configuration space definition. + It defines various Broxton PCI Configuration Space registers + which will be used to dynamically produce all resources in the Host Bus. + @note This ASL file needs to be included as part of platform ACPI DSDT table. + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Device(VLVC) +{ + Name(_ADR, 0x00000000) // Device 0, Function 0 + + // Define various MCH Controller PCI Configuration Space + // registers which will be used to dynamically produce all + // resources in the Host Bus _CRS. + + OperationRegion(HBUS, PCI_Config, 0x00, 0xFF) + Field(HBUS, DWordAcc, NoLock, Preserve) + { + Offset(0x48), // MCHBAR (0:0:0:48) + MHEN, 1, // Enable + , 14, + MHBR, 24, // MCHBAR [38:15] + Offset(0xB0), + BDSM, 32, // Base of Data Stolen Memory + BGSM, 32, // Base of Graphics Stolen Memory + Offset(0xBC), + TOLD, 32, // Top of Low Useable DRAM + } +} + +// +// BUS, I/O, and MMIO resources +// +Method(_CRS,0,Serialized) { + // + // Create pointers to PCI MMIO values + // + CreateDwordField(RES0, ^PM01._MIN, M1MN) + CreateDwordField(RES0, ^PM01._MAX, M1MX) + CreateDwordField(RES0, ^PM01._LEN, M1LN) + + // + // Set Memory Size Values. TLUD represents bits 31:20 of phyical + // TOM, so shift these bits into the correct position and fix up + // the Memory Region available to PCI. + // + Store (M32L, M1LN) + Store (M32B, M1MN) + Subtract (Add (M1MN, M1LN), 1, M1MX) + + // + // Create pointers to Base of Data Stolen Memory Values + // + CreateDwordField(RES0, ^DSM1._MIN, GSMN) + CreateDwordField(RES0, ^DSM1._MAX, GSMX) + CreateDwordField(RES0, ^DSM1._LEN, GSLN) + + // Read C-Unit PCI CFG Reg. 0xB0 for BDSM + Store(^VLVC.BDSM, GSMN) + + // Read C-Unit PCI CFG Reg. 0xBC for TOLUD + And(^VLVC.TOLD, 0xFFFFF000, GSMX) + Decrement(GSMX) + + Add(Subtract(GSMX, GSMN), 1, GSLN) + + // + // Create pointers to Base of Graphics Stolen Memory Values + // + CreateDwordField(RES0, ^GSM1._MIN, GDMN) + CreateDwordField(RES0, ^GSM1._MAX, GDMX) + CreateDwordField(RES0, ^GSM1._LEN, GDLN) + + // Read C-Unit PCI CFG Reg. 0xB4 for BGSM + Store(^VLVC.BGSM, GDMN) + + // Read C-Unit PCI CFG Reg. 0xBC for TOLUD + And(^VLVC.BDSM, 0xFFFFF000, GDMX) + Decrement(GDMX) + + Add(Subtract(GDMX, GDMN), 1, GDLN) + + Return(RES0) +} + +Name( RES0,ResourceTemplate() { + WORDBusNumber ( // Bus number resource (0); the bridge produces bus numbers for its subsequent buses + ResourceProducer, // bit 0 of general flags is 1 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, // PosDecode + 0x0000, // Granularity + 0x0000, // Min + 0x00FF, // Max + 0x0000, // Translation + 0x0100 // Range Length = Max-Min+1 + ) + + IO (Decode16, 0x70, 0x77, 0x01, 0x08) //Consumed resource (0xCF8-0xCFF) + IO (Decode16, 0xCF8, 0xCF8, 0x01, 0x08) //Consumed resource (0xCF8-0xCFF) + + WORDIO ( // Consumed-and-produced resource (all I/O below CF8) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity + 0x0000, // Min + 0x006F, // Max + 0x0000, // Translation + 0x0070 // Range Length + ) + + WORDIO ( // Consumed-and-produced resource + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity + 0x0078, // Min + 0x0CF7, // Max + 0x0000, // Translation + 0x0C80 // Range Length + ) + + WORDIO ( // Consumed-and-produced resource (all I/O above CFF) + ResourceProducer, // bit 0 of general flags is 0 + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + PosDecode, + EntireRange, + 0x0000, // Granularity + 0x0D00, // Min + 0xFFFF, // Max + 0x0000, // Translation + 0xF300 // Range Length + ) + + DWORDMEMORY ( // Descriptor for legacy VGA video RAM + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Min + 0x000BFFFF, // Max + 0x00000000, // Translation + 0x00020000 // Range Length + ,,, + LGB1 + ) + + DWORDMEMORY ( // Descriptor for legacy OptionRom + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x000C0000, // Min + 0x000DFFFF, // Max + 0x00000000, // Translation + 0x00020000 // Range Length + ,,, + LGB2 + ) + + DWORDMEMORY ( // Descriptor for BIOS Area + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x000E0000, // Min + 0x000FFFFF, // Max + 0x00000000, // Translation + 0x00020000 // Range Length + ,,, + LGB3 + ) + + DWORDMEMORY ( // Descriptor for Base of Data Stolen Memory + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x3be00000, // Min + 0x3FFFFFFF, // Max + 0x00000000, // Translation + 0x04200000 // Range Length + ,,, + DSM1 + ) + + DWORDMEMORY ( // Descriptor for Base of Graphics Stolen Memory + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x3be00000, // Min + 0x3FFFFFFF, // Max + 0x00000000, // Translation + 0x04200000 // Range Length + ,,, + GSM1 + ) + + DWORDMEMORY ( // Descriptor for PCI MMIO + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity + 0x80000000, // Min + 0xBFFFFFFF, // Max + 0x00000000, // Translation + 0x40000000 // Range Length + ,,, + PM01 + ) + + DWORDMEMORY ( // Descriptor for PCI CFG Space + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + NonCacheable, + ReadWrite, + 0x00000000, // Granularity + 0xE0000000, // Min + 0xEFFFFFFF, // Max + 0x00000000, // Translation + 0x10000000 // Range Length + ,,, + PM02 + ) + +}) + +Name(GUID,Buffer(){0x5b, 0x4d, 0xdb, 0x33, + 0xf7, 0x1f, + 0x1c, 0x40, + 0x96, 0x57, + 0x74, 0x41, 0xc0, 0x3d, 0xd7, 0x66}) + + +Name(SUPP,0) // PCI _OSC Support Field value +Name(CTRL,0) // PCI _OSC Control Field value + +Method(_OSC,4,Serialized) +{ + // + // Check for proper UUID + // Save the capabilities buffer + // + Store(Arg3,Local0) + + // + // Create DWord-adressable fields from the Capabilties Buffer + // + CreateDWordField(Local0,0,CDW1) + CreateDWordField(Local0,4,CDW2) + CreateDWordField(Local0,8,CDW3) + + // + // Check for proper UUID + // + If (LAnd(LEqual(Arg0,GUID),NEXP)) { + // Save Capabilities DWord2 & 3 + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + If (Not(And(CDW1,1))) { + // Query flag clear? + // Disable GPEs for features granted native control. + If (And(CTRL,0x01)) { + NHPG() + } + If (And(CTRL,0x04)) { + // PME control granted? + NPME() + } + } + + If (LNotEqual(Arg1,One)) { + // + // Unknown revision + // + Or(CDW1,0x08,CDW1) + } + + If (LNotEqual(CDW3,CTRL)) { + // + // Capabilities bits were masked + // + Or(CDW1,0x10,CDW1) + } + // + // Update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Store(CTRL,OSCC) + Return(Local0) + } Else { + Or(CDW1,4,CDW1) // Unrecognized UUID + Return(Local0) + } +} // End _OSC diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Hpet/Hpet.aslc b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Hpet/Hpet.aslc new file mode 100644 index 0000000000..312a4cadbb --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Hpet/Hpet.aslc @@ -0,0 +1,59 @@ +/** @file + The High Precision Event Timer Table + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// +// Statements that include other files +// + +#include +#include "AcpiTablePlatform.h" + +// Hpet Table +EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER HPET = { + { + EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE, + sizeof (EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER), + EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_REVISION, + 0, // to make sum of entire table == 0 + EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field + EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long) + EFI_ACPI_OEM_REVISION, // OEM revision + EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID + EFI_ACPI_CREATOR_REVISION // ASL compiler revision number + }, + 0x0, // EventTimerBlockId + { + 0x00, // Address_Space_ID = System Memory + 0x40, // Register_Bit_Width = 32 bits, mentioned about write failures when in 64bit in SCU HAS + 0x00, // Register_Bit_offset + 0x00, // Dword access + HPET_BASE_ADDRESS, // Base addresse of HPET + }, + 0x0, // Only HPET's _UID in Namespace + MAIN_COUNTER_MIN_PERIODIC_CLOCK_TICKS, + 0x0 +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from + // removing the data structure from the executable + // + return (VOID*)&HPET; +} diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/LPC_DEV.ASL b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/LPC_DEV.ASL new file mode 100644 index 0000000000..3d2cebe834 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/LPC_DEV.ASL @@ -0,0 +1,115 @@ +/** @file + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +scope (\_SB) { + + Device(RTC) // RTC + { + Name(_HID,EISAID("PNP0B00")) + + Name(_CRS,ResourceTemplate() + { + IO(Decode16,0x70,0x70,0x01,0x08) + }) + } + + Device(HPET) // High Performance Event Timer + { + Name (_HID, EisaId ("PNP0103")) + Name (_UID, 0x00) + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Method (_CRS, 0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) + { + 0x00000008, //0xB HPET-2 + } + }) + Return (RBUF) + } + } +} + +Device(IPIC) // 8259 PIC +{ + Name(_HID,EISAID("PNP0000")) + + Name(_CRS,ResourceTemplate() + { + IO(Decode16,0x20,0x20,0x01,0x02) + IO(Decode16,0x24,0x24,0x01,0x02) + IO(Decode16,0x28,0x28,0x01,0x02) + IO(Decode16,0x2C,0x2C,0x01,0x02) + IO(Decode16,0x30,0x30,0x01,0x02) + IO(Decode16,0x34,0x34,0x01,0x02) + IO(Decode16,0x38,0x38,0x01,0x02) + IO(Decode16,0x3C,0x3C,0x01,0x02) + IO(Decode16,0xA0,0xA0,0x01,0x02) + IO(Decode16,0xA4,0xA4,0x01,0x02) + IO(Decode16,0xA8,0xA8,0x01,0x02) + IO(Decode16,0xAC,0xAC,0x01,0x02) + IO(Decode16,0xB0,0xB0,0x01,0x02) + IO(Decode16,0xB4,0xB4,0x01,0x02) + IO(Decode16,0xB8,0xB8,0x01,0x02) + IO(Decode16,0xBC,0xBC,0x01,0x02) + IO(Decode16,0x4D0,0x4D0,0x01,0x02) + IRQNoFlags() {2} + }) +} + +Device(LDRC) // LPC Device Resource Consumption +{ + Name(_HID,EISAID("PNP0C02")) + + Name(_UID,2) + + Name(_CRS,ResourceTemplate() + { + IO(Decode16,0x2E,0x2E,0x1,0x02) // WPCN381U SIO Config Index + Data. + IO(Decode16,0x4E,0x4E,0x1,0x02) // LPC Slot Access. + IO(Decode16,0x61,0x61,0x1,0x1) // NMI Status. + IO(Decode16,0x63,0x63,0x1,0x1) // Processor I/F. + IO(Decode16,0x65,0x65,0x1,0x1) // Processor I/F. + IO(Decode16,0x67,0x67,0x1,0x1) // Processor I/F. + IO(Decode16,0x70,0x70,0x1,0x1) // NMI Enable. + IO(Decode16,0x80,0x80,0x1,0x10) // Postcode. + IO(Decode16,0x92,0x92,0x1,0x1) // Processor I/F. + IO(Decode16,0xB2,0xB2,0x01,0x02) // Software SMI. + IO(Decode16,0x680,0x680,0x1,0x20) // 32 Byte I/O. + IO(Decode16,0x400,0x400,0x1,0x80) // ACPI Base. + IO(Decode16,0x500,0x500,0x1,0xFF) // GPIO Base. + IO(Decode16,0x600,0x600,0x1,0x20) // WPCN381U SIO SWC + ACPI Base. + IO(Decode16,0x164e,0x164e,0x1,0x02) // WPCN381U SIO Config Index1 + Data1. + }) +} +Device(TIMR) // 8254 Timer +{ + Name(_HID,EISAID("PNP0100")) + + Name(_CRS,ResourceTemplate() + { + IO(Decode16,0x40,0x40,0x01,0x04) + IO(Decode16,0x50,0x50,0x10,0x04) + IRQNoFlags() {0} + }) +} diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/LpcB.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/LpcB.asl new file mode 100644 index 0000000000..c39dba7d78 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/LpcB.asl @@ -0,0 +1,49 @@ +/** @file + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// LPC Bridge - Device 31, Function 0 +// Define the needed LPC registers used by ASL. + +scope(\_SB) { + OperationRegion(ILBR, SystemMemory, \IBAS, 0x8C) + Field(ILBR, AnyAcc, NoLock, Preserve) { + Offset(0x08), // 0x08 + PARC, 8, + PBRC, 8, + PCRC, 8, + PDRC, 8, + PERC, 8, + PFRC, 8, + PGRC, 8, + PHRC, 8, + Offset(0x88), // 0x88 + , 4, + UI4E, 1 + } + + Include ("98_LINK.ASL") +} +// LPC Bridge - Device 31, Function 0 +scope (\_SB.PCI0.LPCB) { + OperationRegion(LPC0, PCI_Config, 0x40, 0xC0) + Field(LPC0, AnyAcc, NoLock, Preserve) + { + Offset(0x040), // 0x80 + C1EN, 1, // COM1 Enable + , 31 + } + + Include ("LPC_DEV.ASL") + +} //end of SCOPE + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Lpit/Lpit.aslc b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Lpit/Lpit.aslc new file mode 100644 index 0000000000..c018f57caa --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Lpit/Lpit.aslc @@ -0,0 +1,191 @@ +/** @file + Low Power Idle Table + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// +// Include files +// + +#include +#include + + +// +// LPIT Definitions +// + +#define EFI_ACPI_LOW_POWER_IDLE_TABLE_REVISION 0x1 + +// +// Ensure proper structure formats +// +#pragma pack(1) + +typedef union _EFI_ACPI_LPI_STATE_FLAGS { + struct { + UINT32 Disabled :1; + UINT32 CounterUnavailable :1; + UINT32 Reserved :30; + }; + UINT32 AsUlong; +} EFI_ACPI_LPI_STATE_FLAGS, *PEFI_ACPI_LPI_STATE_FLAGS; + +// Only Mwait LPI here: + +typedef struct _EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR { + UINT32 Type; // offset: 0 + UINT32 Length; // offset: 4 + UINT16 UniqueId; // offset: 8 + UINT8 Reserved[2]; // offset: 9 + EFI_ACPI_LPI_STATE_FLAGS Flags; // offset: 12 + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EntryTrigger; // offset: 16 + UINT32 Residency; // offset: 28 + UINT32 Latency; // offset: 32 + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE ResidencyCounter; // offset: 36 + UINT64 ResidencyCounterFrequency; //offset: 48 +} EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR; + + +// +// Defines for LPIT table, some are CHV specific +// + + +// signature "LPIT" +#define EFI_ACPI_LOW_POWER_IDLE_TABLE_SIGNATURE 0x5449504c + +#define EFI_ACPI_OEM_LPIT_REVISION 0x00000000 + +#define EFI_ACPI_LOW_POWER_IDLE_MWAIT_TYPE 0x0 +#define EFI_ACPI_LOW_POWER_IDLE_DEFAULT_FLAG 0x0 +#define EFI_ACPI_LOW_POWER_IDLE_RES_FREQ 0x0 + +// +// LPI state count (4 on BXT: S0ir, S0i1, S0i2, S0i3) +// + +#define EFI_ACPI_BXT_LPI_STATE_COUNT 0x1 + +// +// LPI TRIGGER (HW C7 on CHV), +// TOFIX!!! +// +#define EFI_ACPI_BXT_LPI_TRIGGER {0x7f, 1, 2, 0x0, 0x60} + +// +// LPI residency counter (MSR based) +// + +#define EFI_ACPI_BXT_LPI_RES_COUNTER0 {0x7F,64,0x0,0x0,0x632} +#define EFI_ACPI_BXT_LPI_RES_COUNTER1 {0x7F,64,0x0,0x0,0x630} +#define EFI_ACPI_BXT_LPI_RES_COUNTER2 {0x7F,64,0x0,0x0,0x631} +#define EFI_ACPI_BXT_LPI_RES_COUNTER3 {0x7F,64,0x0,0x0,0x632} + + +// +// LPI break-even residency in us - all match S0i3 residency +// Residency estimate: Latency x 3 +// +#define EFI_ACPI_BXT_LPI_MIN_RES0 30000 +#define EFI_ACPI_BXT_LPI_MIN_RES1 15000 +#define EFI_ACPI_BXT_LPI_MIN_RES2 15000 +#define EFI_ACPI_BXT_LPI_MIN_RES3 15000 + +// +// LPI latency in us - all match S0i3 latency +// +#define EFI_ACPI_BXT_LPI_LATENCY0 3000 +#define EFI_ACPI_BXT_LPI_LATENCY1 5000 +#define EFI_ACPI_BXT_LPI_LATENCY2 5000 +#define EFI_ACPI_BXT_LPI_LATENCY3 5000 + +// +// LPI ID +// +#define EFI_ACPI_BXT_LPI_UNIQUE_ID0 0 +#define EFI_ACPI_BXT_LPI_UNIQUE_ID1 1 +#define EFI_ACPI_BXT_LPI_UNIQUE_ID2 2 +#define EFI_ACPI_BXT_LPI_UNIQUE_ID3 3 + +// +// LPI ACPI table header +// + + +typedef struct _EFI_ACPI_LOW_POWER_IDLE_TABLE { + EFI_ACPI_DESCRIPTION_HEADER Header; + EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR LpiStates[EFI_ACPI_BXT_LPI_STATE_COUNT]; +} EFI_ACPI_LOW_POWER_IDLE_TABLE; + +#pragma pack() + +EFI_ACPI_LOW_POWER_IDLE_TABLE Lpit = { + + // + // Header + // + + + EFI_ACPI_LOW_POWER_IDLE_TABLE_SIGNATURE, + sizeof (EFI_ACPI_LOW_POWER_IDLE_TABLE), + EFI_ACPI_LOW_POWER_IDLE_TABLE_REVISION , + + // + // Checksum will be updated at runtime + // + 0x00, + + // + // It is expected that these values will be updated at runtime + // + ' ', ' ', ' ', ' ', ' ', ' ', + + 0, + EFI_ACPI_OEM_LPIT_REVISION, + 0, + 0, + + + + // + // Descriptor + // + { + { + EFI_ACPI_LOW_POWER_IDLE_MWAIT_TYPE, + sizeof(EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR), + EFI_ACPI_BXT_LPI_UNIQUE_ID0, + {0,0}, + {EFI_ACPI_LOW_POWER_IDLE_DEFAULT_FLAG}, //Flags + EFI_ACPI_BXT_LPI_TRIGGER, //EntryTrigger + EFI_ACPI_BXT_LPI_MIN_RES0, //Residency + EFI_ACPI_BXT_LPI_LATENCY0, //Latency + EFI_ACPI_BXT_LPI_RES_COUNTER0, //ResidencyCounter + EFI_ACPI_LOW_POWER_IDLE_RES_FREQ //Residency counter frequency + } + } +}; + + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from + // removing the data structure from the executable + // + return (VOID*)&Lpit; +} diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Lpit/Lpit.h b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Lpit/Lpit.h new file mode 100644 index 0000000000..bd5219caad --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Lpit/Lpit.h @@ -0,0 +1,121 @@ +/** @file + The header file of Low Power Idle Table. + + Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _LPIT_H_ +#define _LPIT_H_ + +// +// Statements that include other files +// + +#include + +// signature "LPIT" +#define ACPI_LOW_POWER_IDLE_TABLE_SIGNATURE 0x5449504c +#define ACPI_OEM_LPIT_REVISION 0x00000000 + +#define ACPI_LOW_POWER_IDLE_MWAIT_TYPE 0x0 +#define ACPI_LOW_POWER_IDLE_DEFAULT_FLAG 0x0 +#define ACPI_LOW_POWER_IDLE_NO_RES_COUNTER_FLAG 0x2 +#define ACPI_LOW_POWER_IDLE_RES_FREQ_TSC 0x0 + +// +// LPI state count +// +#define ACPI_LPI_STATE_COUNT 2 + +// +// LPI TRIGGER (HW C10) +// +#define ACPI_LPI_TRIGGER {0x7F,0x1,0x2,0x0,0x60} + +// +// LPI residency counter (HW C10) +// +#define ACPI_LPI_RES_COUNTER {0x7F,64,0x0,0x0,0x632} + +// +// LPI DUMMY COUNTER +// +#define ACPI_DUMMY_RES_COUNTER {0x0,0,0x0,0x0,0x0} + + +// +// LPI break-even residency in us (HW C10) +// +#define ACPI_LPI_MIN_RES 30000 + +// +// LPI latency in us (HW C10) +// +#define ACPI_LPI_LATENCY 3000 + +// +// LPI ID (HW C10 audio) +// +#define ACPI_LPI_AUDIO_ID 0 + +// +// LPI ID (HW C10 CS) +// +#define ACPI_LPI_CS_ID 1 + +#define EFI_ACPI_LOW_POWER_IDLE_TABLE_REVISION 0x1 + +// +// Ensure proper structure formats +// +#pragma pack(1) + +typedef union _EFI_ACPI_LPI_STATE_FLAGS { + struct { + UINT32 Disabled :1; + UINT32 CounterUnavailable :1; + UINT32 Reserved :30; + }; + UINT32 AsUlong; +} EFI_ACPI_LPI_STATE_FLAGS, *PEFI_ACPI_LPI_STATE_FLAGS; + +// Only Mwait LPI here: + +typedef struct _EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR { + UINT32 Type; // offset: 0 + UINT32 Length; // offset: 4 + UINT16 UniqueId; // offset: 8 + UINT8 Reserved[2]; // offset: 10 + EFI_ACPI_LPI_STATE_FLAGS Flags; // offset: 12 + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EntryTrigger; // offset: 16 + UINT32 Residency; // offset: 28 + UINT32 Latency; // offset: 32 + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE ResidencyCounter; // offset: 36 + UINT64 ResidencyCounterFrequency; //offset: 48 +} EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR; + +#pragma pack() + +// +// LPI ACPI table header +// +#pragma pack(1) + +typedef struct _ACPI_LOW_POWER_IDLE_TABLE { + EFI_ACPI_DESCRIPTION_HEADER Header; + EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR LpiStates[ACPI_LPI_STATE_COUNT]; +} ACPI_LOW_POWER_IDLE_TABLE; + +#pragma pack() + +#endif //_LPIT_H_ + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Madt/Madt.h b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Madt/Madt.h new file mode 100644 index 0000000000..b575e73a26 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Madt/Madt.h @@ -0,0 +1,188 @@ +/** @file + This file describes the contents of the ACPI Multiple APIC Description + Table (MADT). Some additional ACPI values are defined in Acpi1_0.h and + Acpi2_0.h. + To make changes to the MADT, it is necessary to update the count for the + APIC structure being updated, and to modify table found in Madt.c. + + Copyright (c) 1996 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _MADT_H +#define _MADT_H + +// +// Statements that include other files +// +#include "AcpiTablePlatform.h" +#include +#include +#include +#include "Platform.h" + +// +// MADT Definitions +// +#define EFI_ACPI_OEM_MADT_REVISION 0x00000000 +// +// Multiple APIC Flags are defined in AcpiX.0.h +// +#define EFI_ACPI_1_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_1_0_PCAT_COMPAT) +#define EFI_ACPI_2_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_2_0_PCAT_COMPAT) +#define EFI_ACPI_3_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_3_0_PCAT_COMPAT) +#define EFI_ACPI_4_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_4_0_PCAT_COMPAT) + +// +// Define the number of each table type. +// This is where the table layout is modified. +// +#define EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT MAX_CPU_NUM +#define EFI_ACPI_LOCAL_APIC_NMI_COUNT MAX_CPU_NUM +#define EFI_ACPI_IO_APIC_COUNT 1 +#define EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT 2 +#define EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT 0 +#define EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT 0 +#define EFI_ACPI_IO_SAPIC_COUNT 0 +#define EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT 0 +#define EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT 0 + +// +// MADT structure +// +// +// Ensure proper structure formats +// +#pragma pack(1) +// +// ACPI 1.0 Table structure +// +typedef struct { + EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + +#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0 + EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT]; +#endif + +#if EFI_ACPI_IO_APIC_COUNT > 0 + EFI_ACPI_1_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT]; +#endif + +#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0 + EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT]; +#endif + +#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0 + EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT]; +#endif + +#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0 + EFI_ACPI_1_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT]; +#endif + +#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0 + EFI_ACPI_1_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT]; +#endif + +} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + +// +// ACPI 2.0 Table structure +// +typedef struct { + EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + +#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0 + EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT]; +#endif + +#if EFI_ACPI_IO_APIC_COUNT > 0 + EFI_ACPI_2_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT]; +#endif + +#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0 + EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT]; +#endif + +#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0 + EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT]; +#endif + +#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0 + EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT]; +#endif + +#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0 + EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT]; +#endif + +#if EFI_ACPI_IO_SAPIC_COUNT > 0 + EFI_ACPI_2_0_IO_SAPIC_STRUCTURE IoSapic[EFI_ACPI_IO_SAPIC_COUNT]; +#endif + +#if EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT > 0 + EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE LocalSapic[EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT]; +#endif + +#if EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT > 0 + EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE PlatformInterruptSources[EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT]; +#endif + +} EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + +// +// ACPI 3.0 Table structure +// +typedef struct { + EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + +#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0 // Type 0x00 + EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT]; +#endif + +#if EFI_ACPI_IO_APIC_COUNT > 0 // Type 0x01 + EFI_ACPI_3_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT]; +#endif + +#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0 // Type 0x02 + EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT]; +#endif + +#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0 // Type 0x03 + EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT]; +#endif + +#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0 // Type 0x04 + EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT]; +#endif + +#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0 // Type 0x05 + EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT]; +#endif + +#if EFI_ACPI_IO_SAPIC_COUNT > 0 // Type 0x06 + EFI_ACPI_3_0_IO_SAPIC_STRUCTURE IoSapic[EFI_ACPI_IO_SAPIC_COUNT]; +#endif + +#if EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT > 0 // Type 0x07 : This table changes in madt 2.0 + EFI_ACPI_3_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE LocalSapic[EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT]; +#endif + +#if EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT > 0 // Type 0x08 + EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE PlatformInterruptSources[EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT]; +#endif + +} EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + +#pragma pack() + +#endif + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Madt/Madt30.aslc b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Madt/Madt30.aslc new file mode 100644 index 0000000000..6c595dbf1b --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Madt/Madt30.aslc @@ -0,0 +1,209 @@ +/** @file + Multiple APIC Description Table + + Copyright (c) 1996 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// +// Statements that include other files +// +#include "Madt.h" +#include + +// +// Multiple APIC Description Table +// +EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { + EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, // **Signatures are the same 1.0-3.0 because it says "APIC". + sizeof (EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE), // **Length + EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION, + // + // EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION, // **Table Revision must be 2.0 for ACPI 3.0 + // Checksum will be updated at runtime + // + 0x00, // **Check sum + // + // It is expected that these values will be programmed at runtime + // + ' ', // OEMID + ' ', // Creative way to + ' ', // make six bytes + ' ', // of space in + ' ', // a table for + ' ', // **OEMID + 0, // **OEM Table ID + EFI_ACPI_OEM_MADT_REVISION, // **OEM Revision + 0, // **Creator ID + 0, // **Creator Revision + // + // MADT specific fields + // + LOCAL_APIC_BASE_ADDRESS, // **Local APIC Address + EFI_ACPI_4_0_MULTIPLE_APIC_FLAGS, // **Flags + // + // Processor Local APIC Structure + // Correct processor order, Primary threads first then Hyper threads + // And correct APIC-ids + // This text below is included as a reference until Thurley is 100%: + // According to EDS the Local APIC ID is determined based of a bit structure + // Bit 24: Core ID Bit 25: Core Pair ID Bit 26-27: Reserved Bit 28-30: Socket ID Bit 31: Reserved + // 4 Sockets and 4 Cores per Socket. + // So possible LAPIC IDs 00, 01, 02, 03, 10, 11, 12, 13, 20, 21, 22, 23, 30, 31, 32, 33 + // Static Entries 00, 10, 20, 30, 01, 11, 21, 31, 02, 12, 22, 32, 03, 13, 23, 33 + // BSP needs to be first entry in table. Check before boot. If BSP non zero need to rotate the entries. + // Suppore BSP is LAPIC ID xy. Rotate the table by using formula [x + (y * 4)] + // So if BSP LAPIC ID is 21 then table rotated 6 times. + // End of Reference Text. + // Thurley is supposed to be 2 sockets, 4 cores, and hyperthreading available per each core. + // 2 (sockets) x 4 (cores) = 8 (processors non-HT), 8 (processors non-HT) x 2 (HT/proc) = 16 (HT procs) + // Rhyme & reason of the ordering below. This is a best guess ordering for now, + // Thurley EPS may give better info on LAPIC numbers. + // Ordering was established to help dissipate heat across two sockets evenly. + // Since logical processor number only has to be unique, I followed + // a similar approach to high end servers and have the first digit of the LAPIC + // id the socket number. + // + EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC, // Type 0x00 + sizeof (EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x01, // Processor ID + 0x00, // Local APIC ID + 0x00000001, // Flags - Disabled (until initialized by platform driver) + EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC, // Type + sizeof (EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x02, // Processor ID + 0x02, // Local APIC ID + 0x00000001, // Flags - Disabled (until initialized by platform driver) + EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC, // Type + sizeof (EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x03, // Processor ID + 0x04, // Local APIC ID + 0x00000001, // Flags - Disabled (until initialized by platform driver) + EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC, // Type + sizeof (EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length + 0x04, // Processor ID + 0x06, // Local APIC ID + 0x00000001, // Flags - Disabled (until initialized by platform driver) + // + // *************** IO APIC Structure ****************** + // + // + // + // ************************** I/O APIC (ICH) ************** + // + EFI_ACPI_3_0_IO_APIC, // Type 0x01 + sizeof (EFI_ACPI_3_0_IO_APIC_STRUCTURE), // Length + ICH_IOAPIC_ID, // IO APIC ID + EFI_ACPI_RESERVED_BYTE, // Reserved EFI_ACPI_RESERVED_BYTE + IO_APIC_BASE_ADDRESS, // IO APIC Address (physical) 0xFEC00000 + 0x18 * 0, // Global System Interrupt Base + + // + // Interrupt Source Override Structure: Sample + // + // EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE, // Type 0x02 + // sizeof (EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE),// Length + // 0x00, // Bus + // 0x00, // Source + // 0x00000000, // Global System Interrupt + // 0x0000, // Flags + // + // IRQ0=>IRQ2 Interrupt Source Override Structure + // + EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE, // Type 0x02 + sizeof (EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE), // Length + 0x00, // Bus - ISA + 0x00, // Source - IRQ0 + 0x00000002, // Global System Interrupt - IRQ2 + 0x0000, // Flags - Conforms to specifications of the bus + // + // ISO (SCI Active High) Interrupt Source Override Structure + // + EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE, // Type 0x02 + sizeof (EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE), // Length + 0x00, // Bus - ISA + 0x09, // Source - IRQ0 + 0x00000009, // Global System Interrupt - IRQ2 + 0x000F, // Flags - Level-tiggered, Active Low + + // + // Non-Maskable Interrupt (NMIs) Source Structure: Sample + // + // EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE, // Type 0x03 + // sizeof (EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE), // Length + // 0x0000, // Flags + // 0x00000000, // Global System Interrupt + // + // Local APIC NMI Structure: Sample + // + // EFI_ACPI_2_0_LOCAL_APIC_NMI, // Type 0x04 + // sizeof (EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE), // Length + // 0x00, // ACPI Processor ID + // 0x0000, // Flags + // 0x00, // Local APIC LINT# + // >>> CORE_m008 Add Local APIC NMI tables for 2nd, 3rd and 4th physical processors. + // + // Assuming here that only need to entries for two sockets. + // + EFI_ACPI_3_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x01, // ACPI Processor ID + 0x000D, // Flags - Level-tiggered, Active High + 0x01, // Local APIC LINT# + EFI_ACPI_3_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x02, // ACPI Processor ID + 0x000D, // Flags - Level-tiggered, Active High + 0x01, // Local APIC LINT# + EFI_ACPI_3_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x03, // ACPI Processor ID + 0x000D, // Flags - Level-tiggered, Active High + 0x01, // Local APIC LINT# + EFI_ACPI_3_0_LOCAL_APIC_NMI, // Type + sizeof (EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE), // Length + 0x04, // ACPI Processor ID + 0x000D, // Flags - Level-tiggered, Active High + 0x01, // Local APIC LINT# + + // + // Local APIC Address Override Structure: Sample + // + // EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE, // Type 0x5 + // sizeof (EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE), // Length + // EFI_ACPI_RESERVED_WORD, // Reserved + // 0x0000000000000000, // Local APIC Address + // + // Sample Platform Interrupt Sources Structure + // + // EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES, // Type 0x8 + // sizeof (EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE), // Length + // 0x0000, // Flags + // 0x00, // Interrupt Type + // 0x00, // Processor ID + // 0x00, // Processor EID + // 0x00, // IO SAPIC Vector + // 0x00000000, // Global System Interrupt + // EFI_ACPI_RESERVED_DWORD, // Reserved + // +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from + // removing the data structure from the executable + // + return (VOID*)&Madt; +} \ No newline at end of file diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Mcfg/Mcfg.aslc b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Mcfg/Mcfg.aslc new file mode 100644 index 0000000000..e3120e83f3 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Mcfg/Mcfg.aslc @@ -0,0 +1,78 @@ +/** @file + ACPI Memory mapped configuration space base address Description Table + + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// +// Statements that include other files +// +#include + +// +// MCFG Table definition +// +EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE MCFG = { + EFI_ACPI_3_0_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_SIGNATURE, + sizeof (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE), + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_REVISION, + // + // Checksum will be updated at runtime + // + 0x00, + // + // It is expected that these values will be programmed at runtime + // + ' ', + ' ', + ' ', + ' ', + ' ', + ' ', + + 0, + EFI_ACPI_OEM_MCFG_REVISION, + 0, + 0, + // + // Beginning of MCFG specific fields + // + EFI_ACPI_RESERVED_QWORD, + // + // Sample Memory Mapped Configuration Space Base Address Structure + // + // 0x0, // Base Address + // 0x0, // PCI Segment Group Number + // 0x0, // Start Bus Number + // 0x0, // End Bus Number + // EFI_ACPI_RESERVED_DWORD, // Reserved + // + // Memory Mapped Configuration Space Base Address Structure for BNB + // + 0x0, // Base Address, will be updated by AcpiPlatform + 0x0, // PCI Segment Group Number + 0x0, // Start Bus Number + PLATFORM_MAX_BUS_NUM, // End Bus Number + EFI_ACPI_RESERVED_DWORD, // Reserved +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from + // removing the data structure from the executable + // + return (VOID*)&MCFG; +} diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PCI_DRC.ASL b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PCI_DRC.ASL new file mode 100644 index 0000000000..f6b4e53368 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PCI_DRC.ASL @@ -0,0 +1,83 @@ +/** @file + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope (\_SB.PCI0) { + + Device(PDRC) // PCI Device Resource Consumption + { + Name(_HID,EISAID("PNP0C02")) + + Name(_UID,1) + + Name(BUF0,ResourceTemplate() + { + // + // PCI Express BAR _BAS and _LEN will be updated in _CRS below according to B0:D0:F0:Reg.60h + // Forced hard code at the moment. + // + //Memory32Fixed (ReadWrite, 0, 0, PCIX) // PCIEX BAR + Memory32Fixed (ReadWrite, 0x0E0000000, 0x010000000, PCIX) + + // + // MPHY BAR. Check if the hard code meets the real configuration. + // If not, dynamically update it like the _CRS method below. + // + Memory32Fixed (ReadWrite, 0x0FEA00000, 0x0100000, MPHB) // MPHY BAR + + // + // SPI BAR. Check if the hard code meets the real configuration. + // If not, dynamically update it like the _CRS method below. + // + Memory32Fixed (ReadWrite, 0x0FED01000, 0x01000,SPIB) // SPI BAR + + // + // PMC BAR. Check if the hard code meets the real configuration. + // If not, dynamically update it like the _CRS method below. + // + Memory32Fixed (ReadWrite, 0x0FED03000, 0x01000,PMCB) // PMC BAR + + // + // PUNIT BAR. Check if the hard code meets the real configuration. + // If not, dynamically update it like the _CRS method below. + // + Memory32Fixed (ReadWrite, 0x0FED06000, 0x01000, PUNB) // PUNIT BAR + + // + // ILB BAR. Check if the hard code meets the real configuration. + // If not, dynamically update it like the _CRS method below. + // + Memory32Fixed (ReadWrite, 0x0FED08000, 0x02000, ILBB) // ILB BAR + + // + // IO BAR. Check if the hard code meets the real configuration. + // If not, dynamically update it like the _CRS method below. + // + Memory32Fixed (ReadWrite, 0x0FED80000, 0x040000, IOBR) // IO BAR + + // + // RCRB BAR _BAS will be updated in _CRS below according to B0:D31:F0:Reg.F0h + // + Memory32Fixed (ReadWrite, 0x0FED1C000, 0x01000, RCRB) // RCRB BAR + + // + // Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) + // + Memory32Fixed (ReadOnly, 0x0FEE00000, 0x0100000, LIOH) + }) + + Method(_CRS,0,Serialized) + { + Return(BUF0) + } + } +} diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PciTree.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PciTree.asl new file mode 100644 index 0000000000..7f66fb2834 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PciTree.asl @@ -0,0 +1,199 @@ +/** @file + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(\_SB) { + Name(PR00, Package(){ +// Host Bridge + Package(){0x0000FFFF, 2, LNKA, 0 }, // NPK + Package(){0x0002FFFF, 0, LNKD, 0 }, // Mobile IGFX + Package(){0x0003FFFF, 0, LNKF, 0 }, // IUNIT + Package(){0x000AFFFF, 0, LNKE, 0 }, // ISH + Package(){0x000BFFFF, 0, LNKF, 0 }, // PUNIT + Package(){0x000CFFFF, 0, LNKH, 0 }, // GMM + + Package(){0x000EFFFF, 0, LNKA, 0 }, // D14: Low Power Audio Engine + Package(){0x000FFFFF, 0, LNKE, 0 }, // CSE + Package(){0x0012FFFF, 0, LNKD, 0 }, // D18: SATA Controller + + Package(){0x0013FFFF, 0, LNKG, 0 }, // D19: PCI Express Port 3-6 + Package(){0x0013FFFF, 1, LNKH, 0 }, // D19: PCI Express Port 3-6 + Package(){0x0013FFFF, 2, LNKE, 0 }, // D19: PCI Express Port 3-6 + Package(){0x0013FFFF, 3, LNKF, 0 }, // D19: PCI Express Port 3-6 + + Package(){0x0014FFFF, 0, LNKG, 0 }, // D20: PCI Express Port 1-2 + Package(){0x0014FFFF, 1, LNKH, 0 }, // D20: PCI Express Port 1-2 + + Package(){0x0015FFFF, 0, LNKB, 0 }, // D21: xHCI Host, xDCI + Package(){0x0015FFFF, 1, LNKC, 0 }, + + Package(){0x001FFFFF, 0, LNKE, 0 }, // SMBus + }) + + Name(AR00, Package() { + +// Fields: Address, +// PCI Pin, +// Source (0 is global interrupt pool), +// Source Index (IRQ if Source=0) + + Package(){0x0000FFFF, 0, 0, 16 }, // NPK Device + Package(){0x0000FFFF, 1, 0, 24 }, // PUNIT Device (INTB -> 24) + Package(){0x0002FFFF, 0, 0, 19 }, // GEN (Intel GFX) + Package(){0x0003FFFF, 0, 0, 21 }, // IUNIT + Package(){0x000DFFFF, 1, 0, 40 }, // PMC + Package(){0x000EFFFF, 0, 0, 25 }, // HD-Audio + Package(){0x000FFFFF, 0, 0, 20 }, // CSE + Package(){0x0011FFFF, 0, 0, 26 }, // ISH + Package(){0x0012FFFF, 0, 0, 19 }, // SATA + +// D19: PCI Express Port 3-6 + Package(){0x0013FFFF, 0, 0, 22 }, // PCIE0 + Package(){0x0013FFFF, 1, 0, 23 }, // PCIE0 + Package(){0x0013FFFF, 2, 0, 20 }, // PCIE0 + Package(){0x0013FFFF, 3, 0, 21 }, // PCIE0 + +// D20: PCI Express Port 1-2 + Package(){0x0014FFFF, 0, 0, 22 }, // PCIE1 + Package(){0x0014FFFF, 1, 0, 23 }, // PCIE1 + + Package(){0x0015FFFF, 0, 0, 17 }, // xHCI + Package(){0x0015FFFF, 1, 0, 13 }, // xDCI + + Package(){0x0016FFFF, 0, 0, 27 }, // I2C0 + Package(){0x0016FFFF, 1, 0, 28 }, // I2C1 + Package(){0x0016FFFF, 2, 0, 29 }, // I2C2 + Package(){0x0016FFFF, 3, 0, 30 }, // I2C3 // usage note: taking this line as an example, device 0x16, function 3 will use apic irq 30 + + Package(){0x0017FFFF, 0, 0, 31 }, // I2C4 + Package(){0x0017FFFF, 1, 0, 32 }, // I2C5 + Package(){0x0017FFFF, 2, 0, 33 }, // I2C6 + Package(){0x0017FFFF, 3, 0, 34 }, // I2C7 + + Package(){0x0018FFFF, 0, 0, 4 }, // UART1 + Package(){0x0018FFFF, 1, 0, 5 }, // UART2 + Package(){0x0018FFFF, 2, 0, 6 }, // UART3 + Package(){0x0018FFFF, 3, 0, 7 }, // UART4 + + Package(){0x0019FFFF, 0, 0, 35 }, // SPI1 + Package(){0x0019FFFF, 1, 0, 36 }, // SPI2 + Package(){0x0019FFFF, 2, 0, 37 }, // SPI3 + + Package(){0x001BFFFF, 0, 0, 3 }, // SDCard + Package(){0x001CFFFF, 0, 0, 39 }, // eMMC + Package(){0x001EFFFF, 0, 0, 42 }, // SDIO + + Package(){0x001FFFFF, 0, 0, 20 } // SMBus + }) + + Name(PR04, Package(){ +// PCIE Port #1 Slot + Package(){0x0000FFFF, 0, LNKG, 0 }, + Package(){0x0000FFFF, 1, LNKH, 0 }, + Package(){0x0000FFFF, 2, LNKE, 0 }, + Package(){0x0000FFFF, 3, LNKF, 0 }, + }) + + Name(AR04, Package(){ +// PCIE Port #1 Slot + Package(){0x0000FFFF, 0, 0, 22 }, + Package(){0x0000FFFF, 1, 0, 23 }, + Package(){0x0000FFFF, 2, 0, 20 }, + Package(){0x0000FFFF, 3, 0, 21 }, + }) + + Name(PR05, Package(){ +// PCIE Port #2 Slot + Package(){0x0000FFFF, 0, LNKH, 0 }, + Package(){0x0000FFFF, 1, LNKE, 0 }, + Package(){0x0000FFFF, 2, LNKF, 0 }, + Package(){0x0000FFFF, 3, LNKG, 0 }, + }) + + Name(AR05, Package(){ +// PCIE Port #2 Slot + Package(){0x0000FFFF, 0, 0, 23 }, + Package(){0x0000FFFF, 1, 0, 20 }, + Package(){0x0000FFFF, 2, 0, 21 }, + Package(){0x0000FFFF, 3, 0, 22 }, + }) + + Name(PR06, Package(){ +// PCIE Port #3 Slot + Package(){0x0000FFFF, 0, LNKE, 0 }, + Package(){0x0000FFFF, 1, LNKF, 0 }, + Package(){0x0000FFFF, 2, LNKG, 0 }, + Package(){0x0000FFFF, 3, LNKH, 0 }, + }) + + Name(AR06, Package(){ +// PCIE Port #3 Slot + Package(){0x0000FFFF, 0, 0, 20 }, + Package(){0x0000FFFF, 1, 0, 21 }, + Package(){0x0000FFFF, 2, 0, 22 }, + Package(){0x0000FFFF, 3, 0, 23 }, + }) + + Name(PR07, Package(){ +// PCIE Port #4 Slot + Package(){0x0000FFFF, 0, LNKF, 0 }, + Package(){0x0000FFFF, 1, LNKG, 0 }, + Package(){0x0000FFFF, 2, LNKH, 0 }, + Package(){0x0000FFFF, 3, LNKE, 0 }, + }) + + Name(AR07, Package(){ +// PCIE Port #4 Slot + Package(){0x0000FFFF, 0, 0, 21 }, + Package(){0x0000FFFF, 1, 0, 22 }, + Package(){0x0000FFFF, 2, 0, 23 }, + Package(){0x0000FFFF, 3, 0, 20 }, + }) + +//--------------------------------------------------------------------------- +// List of IRQ resource buffers compatible with _PRS return format. +//--------------------------------------------------------------------------- +// Naming legend: +// RSxy, PRSy - name of the IRQ resource buffer to be returned by _PRS, "xy" - last two characters of IRQ Link name. +// Note. PRSy name is generated if IRQ Link name starts from "LNK". +// HLxy , LLxy - reference names, can be used to access bit mask of available IRQs. HL and LL stand for active High(Low) Level triggered Irq model. +//--------------------------------------------------------------------------- + Name(PRSA, ResourceTemplate(){ // Link name: LNKA + IRQ(Level, ActiveLow, Shared, LLKA) {3,4,5,6,10,11,12,14,15} + }) + Alias(PRSA,PRSB) // Link name: LNKB + Alias(PRSA,PRSC) // Link name: LNKC + Alias(PRSA,PRSD) // Link name: LNKD + Alias(PRSA,PRSE) // Link name: LNKE + Alias(PRSA,PRSF) // Link name: LNKF + Alias(PRSA,PRSG) // Link name: LNKG + Alias(PRSA,PRSH) // Link name: LNKH +//--------------------------------------------------------------------------- +// Begin PCI tree object scope +//--------------------------------------------------------------------------- + + Device(PCI0) { // PCI Bridge "Host Bridge" + Name(_HID, EISAID("PNP0A08")) // Indicates PCI Express/PCI-X Mode2 host hierarchy + Name(_CID, EISAID("PNP0A03")) // To support legacy OS that doesn't understand the new HID + Name(_ADR, 0x00000000) + Method(^BN00, 0) { return(0x0000) } // Returns default Bus number for Peer PCI buses. Name can be overriden with control method placed directly under Device scope + Method(_BBN, 0) { return(BN00()) } // Bus number, optional for the Root PCI Bus + Name(_UID, 0x0000) // Unique Bus ID, optional + + Method(_PRT,0) { + If(PICM) {Return(AR00)} // APIC mode + Return (PR00) // PIC Mode + } // end _PRT + include ("HOST_BUS.ASL") + } // end PCI0 Bridge "Host Bridge" +} // end _SB scope + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PcieRpPxsxWrapper.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PcieRpPxsxWrapper.asl new file mode 100644 index 0000000000..9675f966df --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PcieRpPxsxWrapper.asl @@ -0,0 +1,43 @@ +/** @file + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope (\_SB.PCI0.RP01.PXSX) +{ + Include("Wifi.asl") +} + +Scope (\_SB.PCI0.RP02.PXSX) +{ + Include("Wifi.asl") +} + +Scope (\_SB.PCI0.RP03.PXSX) +{ + Include("Wifi.asl") +} + +Scope (\_SB.PCI0.RP04.PXSX) +{ + Include("Wifi.asl") +} + +Scope (\_SB.PCI0.RP05.PXSX) +{ + Include("Wifi.asl") +} + +Scope (\_SB.PCI0.RP06.PXSX) +{ + Include("Wifi.asl") +} + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Pep/Pep.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Pep/Pep.asl new file mode 100644 index 0000000000..5daf6e941e --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Pep/Pep.asl @@ -0,0 +1,255 @@ +/** @file + ACPI uPEP Support + + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +External(\_PR.NLPC, IntObj) + +//@todo MSFT has NOT implemented uPEP for Non-CS configuration on Win10. Need to uncomment once MSFT fully implements uPEP +If (LOr(LEqual(S0ID, 1),LGreaterEqual(OSYS, 2015))) { + //Comment out the GFX0, since the _DEP is added in NorthCluster/AcpiTables/Sa.asl + Scope(\_SB.PCI0.SATA) { Name(_DEP, Package(){\_SB.PEPD}) } + Scope(\_SB.PCI0.I2C0) { Name(_DEP, Package(){\_SB.PEPD}) } + Scope(\_SB.PCI0.I2C1) { Name(_DEP, Package(){\_SB.PEPD}) } + Scope(\_SB.PCI0.I2C2) { Name(_DEP, Package(){\_SB.PEPD}) } + Scope(\_SB.PCI0.I2C3) { Name(_DEP, Package(){\_SB.PEPD}) } + Scope(\_SB.PCI0.I2C4) { Name(_DEP, Package(){\_SB.PEPD}) } + Scope(\_SB.PCI0.I2C5) { Name(_DEP, Package(){\_SB.PEPD}) } + Scope(\_SB.PCI0.I2C6) { Name(_DEP, Package(){\_SB.PEPD}) } + Scope(\_SB.PCI0.I2C7) { Name(_DEP, Package(){\_SB.PEPD}) } + Scope(\_SB.PCI0.SPI1) { Name(_DEP, Package(){\_SB.PEPD}) } + Scope(\_SB.PCI0.SPI2) { Name(_DEP, Package(){\_SB.PEPD}) } + Scope(\_SB.PCI0.SPI3) { Name(_DEP, Package(){\_SB.PEPD}) } + Scope(\_SB.PCI0.URT1) { Name(_DEP, Package(){\_SB.PEPD}) } + Scope(\_SB.PCI0.URT2) { Name(_DEP, Package(){\_SB.PEPD}) } + Scope(\_SB.PCI0.URT4) { Name(_DEP, Package(){\_SB.PEPD}) } + Scope(\_SB.PCI0.XHC) { Name(_DEP, Package(){\_SB.PEPD}) } + Scope(\_PR.CPU0) { Name(_DEP, Package(){\_SB.PEPD}) } + Scope(\_PR.CPU1) { Name(_DEP, Package(){\_SB.PEPD}) } + Scope(\_PR.CPU2) { Name(_DEP, Package(){\_SB.PEPD}) } + Scope(\_PR.CPU3) { Name(_DEP, Package(){\_SB.PEPD}) } + Scope(\_SB.PCI0.SDIO) { Name(_DEP, Package(){\_SB.PEPD}) } + Scope(\_SB.PCI0.SDHA) { Name(_DEP, Package(){\_SB.PEPD}) } + Scope(\_SB.PCI0.SDC) { Name(_DEP, Package(){\_SB.PEPD}) } + Scope(\_SB.PCI0.RP02.PXSX) { Name(_DEP, Package(){\_SB.PEPD}) } +} + +Scope(\_SB) +{ + Device (PEPD) + { + Name (_HID, "INT33A1") + Name (_CID, EISAID ("PNP0D80")) + Name (_UID, 0x1) + + Name(PEPP, Zero) + Name (DEVS, Package() + { + 1, + Package() {"\\_SB.PCI0.GFX0"}, + //Package() {"\\_SB.PCI0.SAT0.PRT1"} + }) + + Name(DEVY, Package() // uPEP Device List + { + // + // 1: ACPI Device Descriptor: Fully Qualified name-string + // 2: Enabled/Disabled Field + // 0 = This device is disabled and applies no constraints + // 1+ = This device is enabled and applies constraints + // 3: Constraint Package: entry per LPI state in LPIT + // a. Associated LPI State UID + // ID == 0xFF: same constraints apply to all states in LPIT + // b: minimum Dx state as pre-condition + // c: (optional) OEM specific OEM may provide an additional encoding + // which further defines the D-state Constraint + // 0x0-0x7F - Reserved + // 0x80-0xFF - OEM defined + // + Package() {"\\_PR.CPU0", 0x1, Package() {0, Package() {0xFF, 0}}}, + Package() {"\\_PR.CPU1", 0x1, Package() {0, Package() {0xFF, 0}}}, + Package() {"\\_PR.CPU2", 0x1, Package() {0, Package() {0xFF, 0}}}, + Package() {"\\_PR.CPU3", 0x1, Package() {0, Package() {0xFF, 0}}}, + Package() {"\\_SB.PCI0.GFX0", 0x1, Package() {0, Package() {0xFF, 3}}}, + Package() {"\\_SB.PCI0.SATA", 0x1, Package() {0, Package() {0xFF, 0, 0x81}}}, + Package() {"\\_SB.PCI0.URT1", 0x1, Package() {0, Package() {0xFF, 3}}}, + Package() {"\\_SB.PCI0.URT2", 0x1, Package() {0, Package() {0xFF, 3}}}, + Package() {"\\_SB.PCI0.URT3", 0x0, Package() {0, Package() {0xFF, 3}}}, + Package() {"\\_SB.PCI0.URT4", 0x1, Package() {0, Package() {0xFF, 3}}}, + Package() {"\\_SB.PCI0.SPI1", 0x1, Package() {0, Package() {0xFF, 3}}}, + Package() {"\\_SB.PCI0.SPI2", 0x1, Package() {0, Package() {0xFF, 3}}}, + Package() {"\\_SB.PCI0.SPI3", 0x1, Package() {0, Package() {0xFF, 3}}}, + Package() {"\\_SB.PCI0.I2C0", 0x1, Package() {0, Package() {0xFF, 3}}}, + Package() {"\\_SB.PCI0.I2C1", 0x1, Package() {0, Package() {0xFF, 3}}}, + Package() {"\\_SB.PCI0.I2C2", 0x1, Package() {0, Package() {0xFF, 3}}}, + Package() {"\\_SB.PCI0.I2C3", 0x1, Package() {0, Package() {0xFF, 3}}}, + Package() {"\\_SB.PCI0.I2C4", 0x1, Package() {0, Package() {0xFF, 3}}}, + Package() {"\\_SB.PCI0.I2C5", 0x1, Package() {0, Package() {0xFF, 3}}}, + Package() {"\\_SB.PCI0.I2C6", 0x1, Package() {0, Package() {0xFF, 3}}}, + Package() {"\\_SB.PCI0.I2C7", 0x1, Package() {0, Package() {0xFF, 3}}}, + Package() {"\\_SB.PCI0.PWM", 0x0, Package() {0, Package() {0xFF, 3}}}, + Package() {"\\_SB.PCI0.SDIO", 0x1, Package() {0, Package() {0xFF, 3}}}, + Package() {"\\_SB.PCI0.SDHA", 0x1, Package() {0, Package() {0xFF, 3}}}, + Package() {"\\_SB.PCI0.SDC", 0x1, Package() {0, Package() {0xFF, 3}}}, + Package() {"\\_SB.PCI0.XHC", 0x1, Package() {0, Package() {0xFF, 3}}}, + Package() {"INTELAUDIO\\FUNC_01&VEN_8086&DEV_280*", 0x1, Package(){0, Package (){0xFF, 3}}}, + Package() {"\\_SB.PCI0.RP02.PXSX", 0x0, Package() {0, Package() {0xFF, 0}}}, + }) + + Name(BCCD, Package() // Bugcheck Critical Device(s) + { + // + // 1: ACPI Device Descriptor: Fully Qualified name string + // 2: Package of packages: 1 or more specific commands to power up critical device + // 2a: Package: GAS-structure describing location of PEP accessible power control + // Refer to ACPI 5.0 spec section 5.2.3.1 for details + // a: Address Space ID (0 = System Memory) + // NOTE: A GAS Address Space of 0x7F (FFH) indicates remaining package + // elements are Intel defined + // b: Register bit width (32 = DWORD) + // c: Register bit offset + // d: Access size (3 = DWORD Access) + // e: Address (for System Memory = 64-bit physical address) + // 2b: Package containing: + // a: AND mask !V not applicable for all Trigger Types + // b: Value (bits required to power up the critical device) + // c: Trigger Type: + // 0 = Read + // 1 = Write + // 2 = Write followed by Read + // 3 = Read Modify Write + // 4 = Read Modify Write followed by Read + // 2c: Power up delay: Time delay before next operation in uSec + // + Package() {"\\_SB.PCI0.SATA", Package() { + Package() {Package() {1, 8, 0, 1, 0xB2}, // GAS Structure 8-bit IO Port + Package() {0x0, 0xCD, 0x1}, // Write 0xCD + 16000} // Power up delay = 16ms + } + }, + Package() {"\\_SB.PCI0.SATA.PRT0", Package(){ + Package() {Package() {1, 8, 0, 1, 0xB2}, // GAS Structure 8-bit IO Port + Package() {0x0, 0xCD, 0x1}, // Write 0xCD + 16000} // Power up delay = 16ms + } + }, + Package() {"\\_SB.PCI0.SATA.PRT1", Package(){ + Package() {Package() {1, 8, 0, 1, 0xB2}, // GAS Structure 8-bit IO Port + Package() {0x0, 0xCD, 0x1}, // Write 0xCD + 16000} // Power up delay = 16ms + } + }, + }) + + Method(_STA, 0x0, NotSerialized) + { + If (LOr(LGreaterEqual(OSYS,2015), LAnd(LGreaterEqual(OSYS,2012),LEqual(S0ID, 1)))) { + Return(0xf) + } + Return(0) + } + + Method(_DSM, 0x4, Serialized) + { + + If (LEqual(Arg0,ToUUID("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66"))) { + // Number of Functions (including this one) + If (LEqual(Arg2, Zero)) { + Return(Buffer(One){0x07}) + } + + If (LEqual(\_PR.NLPC, 1)) { + Store (0x01, Index (DeRefOf(Index (DEVY, 0)), 1)) // 0 - CPU-0 + Store (0x00, Index (DeRefOf(Index (DEVY, 1)), 1)) // 1 - CPU-1 + Store (0x00, Index (DeRefOf(Index (DEVY, 2)), 1)) // 2 - CPU-2 + Store (0x00, Index (DeRefOf(Index (DEVY, 3)), 1)) // 3 - CPU-3 + } + + If (LEqual(\_PR.NLPC, 2)) { + Store (0x01, Index (DeRefOf(Index (DEVY, 0)), 1)) // 0 - CPU-0 + Store (0x00, Index (DeRefOf(Index (DEVY, 1)), 1)) // 1 - CPU-1 + Store (0x01, Index (DeRefOf(Index (DEVY, 2)), 1)) // 2 - CPU-2 + Store (0x00, Index (DeRefOf(Index (DEVY, 3)), 1)) // 3 - CPU-3 + } + + If (LEqual(\_PR.NLPC, 3)) { + Store (0x01, Index (DeRefOf(Index (DEVY, 0)), 1)) // 0 - CPU-0 + Store (0x01, Index (DeRefOf(Index (DEVY, 1)), 1)) // 1 - CPU-1 + Store (0x01, Index (DeRefOf(Index (DEVY, 2)), 1)) // 2 - CPU-2 + Store (0x00, Index (DeRefOf(Index (DEVY, 3)), 1)) // 3 - CPU-3 + } + + If (LEqual(\_PR.NLPC, 4)) { + Store (0x01, Index (DeRefOf(Index (DEVY, 0)), 1)) // 0 - CPU-0 + Store (0x01, Index (DeRefOf(Index (DEVY, 1)), 1)) // 1 - CPU-1 + Store (0x01, Index (DeRefOf(Index (DEVY, 2)), 1)) // 2 - CPU-2 + Store (0x01, Index (DeRefOf(Index (DEVY, 3)), 1)) // 3 - CPU-3 + } + + If (LEqual(ODBG, 0)) { + Store (0x01, Index (DeRefOf(Index (DEVY, 8)), 1)) // URT-3 + } + + If (LEqual(ODBG, 1)) { + Store (0x00, Index (DeRefOf(Index (DEVY, 8)), 1)) // URT-3 + } + + If (\_SB.PCI0.RP02.PXSX.WIST()) { + Store (3, Index(DeRefOf(Index(DeRefOf(Index (DeRefOf(Index (DEVY, 27)), 2)), 1)), 1)) // 27 - RP02 + Store (0x01, Index (DeRefOf(Index (DEVY, 27)), 1)) // 27 - RP02 + } + + // Device Constraints Enumeration + If (LEqual(Arg2, One)) { + If (LEqual(S0ID, 1)) { + Return(DEVY) + } + Return(Package() {0}) + } + // BCCD + If (LEqual(Arg2, 2)) { + Return(BCCD) + } + // Screen off notification + If (LEqual(Arg2, 0x3)) { + + } + + // Screen on notification + If (LEqual(Arg2, 0x4)) { + + } + + // resiliency phase entry (deep standby entry) + If (LEqual(Arg2, 0x5)) { + If (LEqual(S0ID, 1)) { //S0ID: >=1: CS 0: non-CS + // call method specific to CS platforms when the system is in a + // standby state with very limited SW activities + \GUAM(1) // 0x01 - Power State Standby (CS Entry) + } + } + + // resiliency phase exit (deep standby exit) + If (LEqual(Arg2, 0x6)) { + If (LEqual(S0ID, 1)) { //S0ID: >=1: CS 0: non-CS + // call method specific to CS platforms when the system is in a + // standby state with very limited SW activities + \GUAM(0) // 0x00 - Power State On (CS Exit) + } + } + }// If(LEqual(Arg0,ToUUID("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66"))) + Return(One) + } // Method(_DSM) + } //device (PEPD) +} // End Scope(\_SB) + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Platform.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Platform.asl new file mode 100644 index 0000000000..7847f2f6dc --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Platform.asl @@ -0,0 +1,783 @@ +/** @file + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// Define the following External variables to prevent a WARNING when +// using ASL.EXE and an ERROR when using IASL.EXE. + +External(PDC0) +External(PDC1) +External(PDC2) +External(PDC3) +External(\_PR.CPU0._PPC, IntObj) +External(\_SB.PCI0.LPCB.TPM.PTS, MethodObj) +Name(ECUP, 1) // EC State indicator: 1- Normal Mode 0- Low Power Mode +Mutex(EHLD, 0) // EC Hold indicator: 0- No one accessing the EC Power State 1- Someone else is accessing the EC Power State + +External(\_SB.IETM,DeviceObj) +External(\_SB.IETM.ODVP,MethodObj) +External(\_SB.IETM.ODVX,PkgObj) +External(\_SB.TPM.PTS, MethodObj) +Name (ADW1, 0) + +// +// Create a Global MUTEX. +// +Mutex(MUTX,0) + +// Define Port 80 as an ACPI Operating Region to use for debugging. Please +// note that the Intel CRBs have the ability to ouput an entire DWord to +// Port 80h for debugging purposes, so the model implemented here may not be +// able to be used on OEM Designs. + +OperationRegion(PRT0,SystemIO,0x80,4) +Field(PRT0,DwordAcc,Lock,Preserve) +{ + P80H, 32 +} + +// Port 80h Update: +// Update 8 bits of the 32-bit Port 80h. +// +// Arguments: +// Arg0: 0 = Write Port 80h, Bits 7:0 Only. +// 1 = Write Port 80h, Bits 15:8 Only. +// 2 = Write Port 80h, Bits 23:16 Only. +// 3 = Write Port 80h, Bits 31:24 Only. +// Arg1: 8-bit Value to write +// +// Return Value: +// None + +Method(P8XH,2,Serialized) +{ + If (LEqual(Arg0,0)) // Write Port 80h, Bits 7:0. + { + Store(Or(And(P80D,0xFFFFFF00),Arg1),P80D) + } + + If (LEqual(Arg0,1)) // Write Port 80h, Bits 15:8. + { + Store(Or(And(P80D,0xFFFF00FF),ShiftLeft(Arg1,8)),P80D) + } + + If (LEqual(Arg0,2)) // Write Port 80h, Bits 23:16. + { + Store(Or(And(P80D,0xFF00FFFF),ShiftLeft(Arg1,16)),P80D) + } + + If (LEqual(Arg0,3)) // Write Port 80h, Bits 31:24. + { + Store(Or(And(P80D,0x00FFFFFF),ShiftLeft(Arg1,24)),P80D) + } + + Store(P80D,P80H) +} + +// +// Define SW SMI port as an ACPI Operating Region to use for generate SW SMI. +// +OperationRegion (SPRT, SystemIO, 0xB2, 2) +Field (SPRT, ByteAcc, Lock, Preserve) { + SSMP, 8 +} + +// The _PIC Control Method is optional for ACPI design. It allows the +// OS to inform the ASL code which interrupt controller is being used, +// the 8259 or APIC. The reference code in this document will address +// PCI IRQ Routing and resource allocation for both cases. +// +// The values passed into _PIC are: +// 0 = 8259 +// 1 = IOAPIC + +Method(\_PIC,1) +{ + Store(Arg0,GPIC) + Store(Arg0,PICM) +} + +OperationRegion(SWC0, SystemIO, 0x610, 0x0F) +Field(SWC0, ByteAcc, NoLock, Preserve) +{ + G1S, 8, //SWC GPE1_STS + Offset(0x4), + G1E, 8, + Offset(0xA), + G1S2, 8, //SWC GPE1_STS_2 + G1S3, 8 //SWC GPE1_STS_3 +} + +OperationRegion (SWC1, SystemIO, \PMBS, 0x2C) +Field(SWC1, DWordAcc, NoLock, Preserve) +{ + Offset(0x20), + G0S, 32, //GPE0_STS + Offset(0x28), + G0EN, 32 //GPE0_EN +} + +OperationRegion (PMCM, SystemMemory, Add(DD1A,0x1000), 0x1000) +Field (PMCM, ByteAcc, NoLock, Preserve) +{ + Offset (0x94), + DHPD, 32, // DISPLAY_HPD_CTL +} + +// Prepare to Sleep. The hook is called when the OS is about to +// enter a sleep state. The argument passed is the numeric value of +// the Sx state. + +Method(_PTS,1) +{ + Store(0,P80D) // Zero out the entire Port 80h DWord. + P8XH(0,Arg0) // Output Sleep State to Port 80h, Byte 0. + + //clear the 3 SWC status bits + Store(Ones, G1S3) + Store(Ones, G1S2) + Store(1, G1S) + + //set SWC GPE1_EN + Store(1,G1E) + + //clear GPE0_STS + Store(Ones, G0S) + + // + // Call TPM PTS method + // + \_SB.TPM.PTS (Arg0) + + // + // Set GPIO_116 (SOC_CODEC_IRQ) 20k pull-down for device I2S audio codec INT343A before enter S3/S4 + // + If (LAnd (LEqual (IOBF, 3), LEqual (IS3A, 1))) { + Store (\_SB.GPC1 (NW_GPIO_116), ADW1) + Or (ADW1, 0xFFFFC3FF, ADW1) + And (ADW1, 0x00001000, ADW1) + \_SB.SPC1 (NW_GPIO_116, ADW1) + } +} + +// Wake. This hook is called when the OS is about to wake from a +// sleep state. The argument passed is the numeric value of the +// sleep state the system is waking from. + +Method(_WAK,1,Serialized) +{ + P8XH(1,0xAB) // Beginning of _WAK. + + If (NEXP) { + // Reinitialize the Native PCI Express after resume + If (And(OSCC,0x02)) { + \_SB.PCI0.NHPG() + } + + If (And(OSCC,0x04)) { + // PME control granted? + \_SB.PCI0.NPME() + } + } + + If (LOr(LEqual(Arg0,3), LEqual(Arg0,4))) { // If S3 or S4 Resume + If (LEqual(PFLV,FMBL)) { + // + // if battery has changed from previous state i.e after Hibernate + // then update the PWRS and update the SMM Power state + // + If (LEqual(Arg0,4)) { + // Perform needed ACPI Notifications. + PNOT() + } + } + + + // Windows XP SP2 does not properly restore the P-State + // upon resume from S4 or S3 with degrade modes enabled. + // Use the existing _PPC methods to cycle the available + // P-States such that the processor ends up running at + // the proper P-State. + // + // Note: For S4, another possible W/A is to always boot + // the system in LFM. + // + If (LEqual(OSYS,2002)) { + If (LGreater(\_PR.CPU0._PPC,0)) { + Subtract(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC) + PNOT() + Add(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC) + PNOT() + } Else { + Add(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC) + PNOT() + Subtract(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC) + PNOT() + } + } + + // + // Invoke SD card wake up method + // + \_SB.PCI0.SDC.WAK() + } + Return(Package(){0,0}) +} + + +// Power Notification: +// Perform all needed OS notifications during a +// Power Switch. +// +// Arguments: +// None +// +// Return Value: +// None + +Method(PNOT,0,Serialized) +{ + // + // If MP enabled and driver support is present, notify both + // processors. + // + If (MPEN) { + If (And(PDC0,0x0008)) { + Notify(\_PR.CPU0,0x80) // Eval CPU0 _PPC. + + If (And(PDC0,0x0010)) { + Sleep(100) + Notify(\_PR.CPU0,0x81) // Eval _CST. + } + } + + If (And(PDC1,0x0008)) { + Notify(\_PR.CPU1,0x80) // Eval CPU1 _PPC. + + If (And(PDC1,0x0010)) { + Sleep(100) + Notify(\_PR.CPU1,0x81) // Eval _CST. + } + } + + If (And(PDC2,0x0008)) { + Notify(\_PR.CPU2,0x80) // Eval CPU2 _PPC. + + If (And(PDC2,0x0010)) { + Sleep(100) + Notify(\_PR.CPU2,0x81) // Eval _CST. + } + } + + If (And(PDC3,0x0008)) { + Notify(\_PR.CPU3,0x80) // Eval CPU3 _PPC. + + If (And(PDC3,0x0010)) { + Sleep(100) + Notify(\_PR.CPU3,0x81) // Eval _CST. + } + } + } Else { + Notify(\_PR.CPU0,0x80) // Eval _PPC. + Sleep(100) + Notify(\_PR.CPU0,0x81) // Eval _CST + } + + If (LEqual(\DPTE,1)) { + Notify(\_SB.IETM, 0x86) // Notification sent to DPTF driver (Policy) for PDRT reevaluation after AC/DC transtion has occurred. + } +} //end of PNOT + +Name(CLMP, 0) // save the clamp bit +Name(PLEN, 0) // save the power limit enable bit +Name(PLSV, 0x8000) // save value of PL1 upon entering CS +Name(CSEM, 0) //semaphore to avoid multiple calls to SPL1. SPL1/RPL1 must always be called in pairs, like push/pop off a stack +// +// SPL1 (Set PL1 to 4.5 watts with clamp bit set) +// Per Legacy Thermal management CS requirements, we would like to set the PL1 limit when entering CS to 4.5W with clamp bit set via MMIO. +// This can be done in the ACPI object which gets called by graphics driver during CS Entry. +// Likewise, during CS exit, the BIOS must reset the PL1 value to the previous value prior to CS entry and reset the clamp bit. +// +// Arguments: +// None +// +// Return Value: +// None +Method(SPL1,0,Serialized) +{ + If (LEqual(CSEM, 1)) + { + Return() // we have already been called, must have CS exit before calling again + } + Store(1, CSEM) // record first call +} +// +// RPL1 (Restore the PL1 register to the values prior to CS entry) +// +// Arguments: +// None +// +// Return Value: +// None +Method(RPL1,0,Serialized) +{ + Store(0, CSEM) // restore semaphore +} + +Name(DDPS, 0) // Current Display Power Status. 0= D0; non-zero = Dx state;. Initial value is zero. +Name(UAMS, 0) // User Absent Mode state, Zero - User Present; non-Zero - User not present +// GUAM - Global User Absent Mode +// Run when a change to User Absent mode is made, e.g. screen/display on/off events. +// Any device that needs notifications of these events includes its own UAMN Control Method. +// +// Arguments: +// Power State: +// 00h = On +// 01h = Standby +// 02h = Suspend +// 04h = Off +// 08h = Reduced On +// +// Return Value: +// None +// +Method(GUAM,1,Serialized) +{ + If (LNotEqual(Arg0, DDPS)) { // Display controller D-State changed? + Store(Arg0, DDPS) //Update DDPS to current state + Store(LAnd(Arg0, LNot(PWRS)), UAMS) // UAMS: User Absent Mode state, Zero - User Present; non-Zero - User not present + + //Port 80 code for CS + If (Arg0) { + + + If (PLCS) { + SPL1() // set PL1 to low value upon CS entry + } + } Else { + + } + + P_CS() // Powergating during CS + } +} + +// Power CS Powergated Devices: +// Method to enable/disable power during CS +Method(P_CS,0,Serialized) +{ +} + +// +// System Bus +// +Scope(\_SB) +{ + Scope(PCI0) + { + Method(_INI,0) + { + // Determine the OS and store the value, where: + // + // OSYS = 2000 = WIN2000. + // OSYS = 2001 = WINXP, RTM or SP1. + // OSYS = 2002 = WINXP SP2. + // OSYS = 2006 = Vista. + // OSYS = 2009 = Windows 7 and Windows Server 2008 R2. + // OSYS = 2012 = Windows 8 and Windows Server 2012. + // OSYS = 2013 = Windows Blue. + // OSYS = 2015 = Windows 10. + // + // Assume Windows 2000 at a minimum. + + Store(2000,OSYS) + + // Check for a specific OS which supports _OSI. + + If (CondRefOf(\_OSI)) { + // Linux returns _OSI = TRUE for numerous Windows + // strings so that it is fully compatible with + // BIOSes available in the market today. There are + // currently 2 known exceptions to this model: + // 1) Video Repost - Linux supports S3 without + // requiring a Driver, meaning a Video + // Repost will be required. + // 2) On-Screen Branding - a full CMT Logo + // is limited to the WIN2K and WINXP + // Operating Systems only. + + // Use OSYS for Windows Compatibility. + + If(\_OSI("Windows 2001")) // Windows XP + { + Store(2001,OSYS) + } + + If(\_OSI("Windows 2001 SP1")) // Windows XP SP1 + { + Store(2001,OSYS) + } + + If(\_OSI("Windows 2001 SP2")) // Windows XP SP2 + { + Store(2002,OSYS) + } + + If(\_OSI("Windows 2006")) // Windows Vista + { + Store(2006,OSYS) + } + + If(\_OSI("Windows 2009")) // Windows 7 and Windows Server 2008 R2 + { + Store(2009,OSYS) + } + + If(\_OSI("Windows 2012")) //Windows 8 and Windows Server 2012 + { + Store(2012,OSYS) + } + + If(\_OSI("Windows 2013")) //Windows 8.1 and Windows Server 2012 R2 + { + Store(2013,OSYS) + } + + If(\_OSI("Windows 2015")) //Windows 10 + { + Store(2015,OSYS) + } + // + // If CMP is enabled, enable SMM C-State + // coordination. SMM C-State coordination + // will be disabled in _PDC if driver support + // for independent C-States deeper than C1 + // is indicated. + } + } + + Method(NHPG,0,Serialized) + { + Store(0,^RP01.HPEX) // clear the hot plug SCI enable bit + Store(0,^RP02.HPEX) // clear the hot plug SCI enable bit + Store(0,^RP03.HPEX) // clear the hot plug SCI enable bit + Store(0,^RP04.HPEX) // clear the hot plug SCI enable bit + Store(0,^RP05.HPEX) // clear the hot plug SCI enable bit + Store(0,^RP06.HPEX) // clear the hot plug SCI enable bit + Store(1,^RP01.HPSX) // clear the hot plug SCI status bit + Store(1,^RP02.HPSX) // clear the hot plug SCI status bit + Store(1,^RP03.HPSX) // clear the hot plug SCI status bit + Store(1,^RP04.HPSX) // clear the hot plug SCI status bit + Store(1,^RP05.HPSX) // clear the hot plug SCI status bit + Store(1,^RP06.HPSX) // clear the hot plug SCI status bit + } + + Method(NPME,0,Serialized) + { + Store(0,^RP01.PMEX) // clear the PME SCI enable bit + Store(0,^RP02.PMEX) // clear the PME SCI enable bit + Store(0,^RP03.PMEX) // clear the PME SCI enable bit + Store(0,^RP04.PMEX) // clear the PME SCI enable bit + Store(0,^RP05.PMEX) // clear the PME SCI enable bit + Store(0,^RP06.PMEX) // clear the PME SCI enable bit + Store(1,^RP01.PMSX) // clear the PME SCI status bit + Store(1,^RP02.PMSX) // clear the PME SCI status bit + Store(1,^RP03.PMSX) // clear the PME SCI status bit + Store(1,^RP04.PMSX) // clear the PME SCI status bit + Store(1,^RP05.PMSX) // clear the PME SCI status bit + Store(1,^RP06.PMSX) // clear the PME SCI status bit + } + } // end Scope(PCI0) + + //-------------------- + // GPIO + //-------------------- + + Device (GPO0) // North Community for DFx GPIO, SATA GPIO, PWM, LPSS/ISH UARTs, IUnit GPIO, JTAG, and SVID + { + Name (_ADR, 0) + Name (_HID, "INT3452") + Name (_CID, "INT3452") + Name (_DDN, "General Purpose Input/Output (GPIO) Controller - North" ) + Name (_UID, 1) + Name (LINK, "\\_SB.GPO0") // Support for Windows 7 + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00004000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {14} + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(GP0A, B0BA) + Store(GP0L, B0LN) + Return (RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + Return(0xf) + } + // Track status of GPIO OpRegion availability for this controller + Name(AVBL, 0) + Method(_REG,2) { + If (Lequal(Arg0, 8)) { + Store(Arg1, ^AVBL) + } + } + + OperationRegion(GPOP, SystemMemory, GP0A, GP0L) + Field(\_SB.GPO0.GPOP, ByteAcc, NoLock, Preserve) { + Offset(0x578), //PIN 15:15 * 8 + 0x500 // WiFi Reset + CWLE, 1, + Offset(0x5B0), //PIN 22:22 * 8 + 0x500 // SATA_ODD_PWRGT_R + ODPW, 1 + } + } // Device (GPO0) + + Device (GPO1) // Northwest Community for Display GPIO, PMC, Audio, and SPI + { + Name (_ADR, 0) + Name (_HID, "INT3452") + Name (_CID, "INT3452") + Name (_DDN, "General Purpose Input/Output (GPIO) Controller - Northwest" ) + Name (_UID, 2) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00004000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {14} + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(GP1A, B0BA) + Store(GP1L, B0LN) + Return (RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + If (LLess(OSYS,2012)) { + // Don't report this GPIO for WIN7 + Return (0) + } + Return(0xf) + } + + } //Device (GPO1) + + + Device (GPO2) // West Community for LPSS/ISH I2C, ISH GPIO, iCLK, and PMU + { + Name (_ADR, 0) + Name (_HID, "INT3452") + Name (_CID, "INT3452") + Name (_DDN, "General Purpose Input/Output (GPIO) Controller - West" ) + Name (_UID, 3) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00004000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {14} + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(GP2A, B0BA) + Store(GP2L, B0LN) + Return (RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + If (LLess(OSYS,2012)) { + // Don't report this GPIO for WIN7 + Return (0) + } + Return(0xf) + } + } //Device (GPO2) + + Device (GPO3) // Southwest Community for EMMC, SDIO, SDCARD, SMBUS, and LPC + { + Name (_ADR, 0) + Name (_HID, "INT3452") + Name (_CID, "INT3452") + Name (_DDN, "General Purpose Input/Output (GPIO) Controller - Southwest" ) + Name (_UID, 4) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00004000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {14} + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(GP3A, B0BA) + Store(GP3L, B0LN) + Return (RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + If(LLess(OSYS,2012)) { + // Don't report this GPIO for WIN7 + Return (0) + } + Return(0xf) + } + + // Track status of GPIO OpRegion availability for this controller + Name(AVBL, 0) + Method(_REG,2) { + If (Lequal(Arg0, 8)) { + Store(Arg1, ^AVBL) + } + } + + OperationRegion(GPOP, SystemMemory, GP3A, GP3L) + Field(\_SB.GPO3.GPOP, ByteAcc, NoLock, Preserve) { + Offset(0x5F0), //PIN 30: 30 * 8 + 0x500 // GPIO_183 SD_CARD_PWR_EN_N + SDPC, 1 + } + } //Device (GPO3) + + +} // end Scope(\_SB) + +Scope (\) +{ + // + // Global Name, returns current Interrupt controller mode; + // updated from _PIC control method + // + Name(PICM, 0) + + // + // Procedure: GPRW + // + // Description: Generic Wake up Control Method ("Big brother") + // to detect the Max Sleep State available in ASL Name scope + // and Return the Package compatible with _PRW format. + // Input: Arg0 = bit offset within GPE register space device event will be triggered to. + // Arg1 = Max Sleep state, device can resume the System from. + // If Arg1 = 0, Update Arg1 with Max _Sx state enabled in the System. + // Output: _PRW package + // + Name(PRWP, Package(){Zero, Zero}) // _PRW Package + + Method(GPRW, 2) + { + Store(Arg0, Index(PRWP, 0)) // copy GPE# + // + // SS1-SS4 - enabled in BIOS Setup Sleep states + // + Store(ShiftLeft(SS1,1),Local0) // S1 ? + Or(Local0,ShiftLeft(SS2,2),Local0) // S2 ? + Or(Local0,ShiftLeft(SS3,3),Local0) // S3 ? + Or(Local0,ShiftLeft(SS4,4),Local0) // S4 ? + // + // Local0 has a bit mask of enabled Sx(1 based) + // bit mask of enabled in BIOS Setup Sleep states(1 based) + // + If (And(ShiftLeft(1, Arg1), Local0)) { + // + // Requested wake up value (Arg1) is present in Sx list of available Sleep states + // + Store(Arg1, Index(PRWP, 1)) // copy Sx# + } Else { + // + // Not available -> match Wake up value to the higher Sx state + // + ShiftRight(Local0, 1, Local0) + // If(LOr(LEqual(OSFL, 1), LEqual(OSFL, 2))) { // ??? Win9x + // FindSetLeftBit(Local0, Index(PRWP,1)) // Arg1 == Max Sx + // } Else { // ??? Win2k / XP + FindSetLeftBit(Local0, Index(PRWP,1)) // Arg1 == Min Sx + // } + } + + Return(PRWP) + } +} + +Scope (\_SB) +{ + Name(OSCI, 0) // \_SB._OSC DWORD2 input + Name(OSCO, 0) // \_SB._OSC DWORD2 output + Name(OSCP, 0) // \_SB._OSC CAPABILITIES + // _OSC (Operating System Capabilities) + // _OSC under \_SB scope is used to convey platform wide OSPM capabilities. + // For a complete description of _OSC ACPI Control Method, refer to ACPI 5.0 + // specification, section 6.2.10. + // Arguments: (4) + // Arg0 - A Buffer containing the UUID "0811B06E-4A27-44F9-8D60-3CBBC22E7B48" + // Arg1 - An Integer containing the Revision ID of the buffer format + // Arg2 - An Integer containing a count of entries in Arg3 + // Arg3 - A Buffer containing a list of DWORD capabilities + // Return Value: + // A Buffer containing the list of capabilities + // + Method(_OSC,4,Serialized) + { + // + // Point to Status DWORD in the Arg3 buffer (STATUS) + // + CreateDWordField(Arg3, 0, STS0) + // + // Point to Caps DWORDs of the Arg3 buffer (CAPABILITIES) + // + CreateDwordField(Arg3, 4, CAP0) + + // + // Check UUID + // + If (LEqual(Arg0,ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48"))) { + // + // Check Revision + // + If (LEqual(Arg1,One)) { + Store(CAP0, OSCP) + If (And(CAP0,0x04)) // Check _PR3 Support(BIT2) + { + Store(0x04, OSCO) + If (LEqual(RTD3,0)) // Is RTD3 support disabled in Bios Setup? + { + // RTD3 is disabled via BIOS Setup. + And(CAP0, 0x3B, CAP0) // Clear _PR3 capability + Or(STS0, 0x10, STS0) // Indicate capability bit is cleared + } + } + } Else{ + And(STS0,0xFFFFFF00,STS0) + Or(STS0,0xA, STS0) // Unrecognised Revision and report OSC failure + } + } Else { + And(STS0,0xFFFFFF00,STS0) + Or (STS0,0x6, STS0) // Unrecognised UUID and report OSC failure + } + + Return(Arg3) + } // End _OSC +} + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Audio/AudioCodec_INT343A.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Audio/AudioCodec_INT343A.asl new file mode 100644 index 0000000000..a1756ec6ef --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Audio/AudioCodec_INT343A.asl @@ -0,0 +1,57 @@ +/** @file + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +External(\IOBF, IntObj) // ScHdAudioIoBufferOwnership +External(\IS3A, IntObj) + +Scope(\_SB.PCI0.I2C0) { + //----------------------------------- + // HD Audio I2S Codec device + // ALC 298 + // I2C1 + // GPIO_192:SOC_CODEC_PD_N North West Community number 5 + // GPIO_116:SOC_CODEC_IRQ North West Community, direct IRQ, IRQ number 0x5B. + //----------------------------------- + Device (HDAC) + { + Name (_HID, "INT343A") + Name (_CID, "INT343A") + Name (_DDN, "Intel(R) Smart Sound Technology Audio Codec") + Name (_UID, 1) + Name (CADR, 0) // Codec I2C address + + Method(_INI) { + } + + Method (_CRS, 0, Serialized) { + Name (SBFB, ResourceTemplate () { + I2cSerialBus (0x1C, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.PCI0.I2C0",,,) + }) + + Name (SBFI, ResourceTemplate () { + Interrupt (ResourceConsumer, Level, ActiveLow, ExclusiveAndWake,,,) {0x5B} + }) + + Return (ConcatenateResTemplate(SBFB, SBFI)) + } + + Method (_STA, 0, NotSerialized) + { + If (LAnd (LEqual (IOBF, 3), LEqual(IS3A, 1))) { + Return (0xF) // I2S Codec Enabled + } + Return (0) + } + } // Device (HDAC) +} + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Audio/AudioCodec_INT34C1.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Audio/AudioCodec_INT34C1.asl new file mode 100644 index 0000000000..562f3bd0f2 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Audio/AudioCodec_INT34C1.asl @@ -0,0 +1,57 @@ +/** @file + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +External(\ISC1, IntObj) + +Scope(\_SB.PCI0.I2C1) +{ + Device (ACD0) // Audio Codec driver I2C + { + Name (_ADR, 0x38) + Name (_HID, "INT34C1") + Name (_CID, "INT34C1") + Name (_DDN, "Intel(R) Smart Sound Technology Audio Codec" ) + Name (_UID, 1) + + Method(_CRS, 0x0, Serialized) + { + Name(SBUF,ResourceTemplate () + { + I2CSerialBus( + 0x38, // SlaveAddress: bus address + , // SlaveMode: default to ControllerInitiated + 400000, // ConnectionSpeed: in Hz + , // Addressing Mode: default to 7 bit + "\\_SB.PCI0.I2C1", // ResourceSource: I2C bus controller name + , // Descriptor Name: creates name for offset of resource descriptor + ) // VendorData + GpioInt(Level, ActiveLow, ExclusiveAndWake, PullUp, 0,"\\_SB.GPO1") {69} // SOC_CODEC_IRQ + }) + Return (SBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + If (LEqual (ISC1, 1)) { + Return (0xF) // I2S Codec Enabled + } + Return (0) + } + + Method (_DIS, 0x0, NotSerialized) + { + } + + } // Device (ACD0) +} + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Bluetooth/Bluetooth_BCM2E40.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Bluetooth/Bluetooth_BCM2E40.asl new file mode 100644 index 0000000000..a001d67357 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Bluetooth/Bluetooth_BCM2E40.asl @@ -0,0 +1,55 @@ +/** @file + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(\_SB.PCI0.URT1) +{ + Device(BTH0) { + Method(_HID) { + // Return HID based on BIOS Setup + Return("BCM2EA8") + } + + Method(_INI) { + } + + Method(_CRS, 0x0, Serialized) { + Name(SBFG, ResourceTemplate (){ + UARTSerialBus(115200,,,0xc0,,,FlowControlHardware,32,32,"\\_SB.PCI0.URT1" ) + GpioIo(Exclusive, PullDown, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {27} // North-west(27):GPIO_214 NGFF_BT_DEV_WAKE_N + GpioIo(Exclusive, PullDown, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO2", ) {24} // West(24):GPIO_154, BT_DISABLE2_1P8_N + GpioInt (Level, ActiveLow, Exclusive, PullDefault, 0x0000, "\\_SB.GPO1", 0x00, ResourceConsumer, ) {35} + }) + + Name(SBFI, ResourceTemplate () { + UARTSerialBus(115200,,,0xc0,,,FlowControlHardware,32,32,"\\_SB.PCI0.URT1" ) + GpioIo(Exclusive, PullDown, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {27} // North-west(27):GPIO_214 NGFF_BT_DEV_WAKE_N + GpioIo(Exclusive, PullDown, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO2", ) {24} // West(24):GPIO_154, BT_DISABLE2_1P8_N + Interrupt(ResourceConsumer, Level, ActiveLow, Exclusive, ) {0x34} + }) + + If(LLess(OSYS,2012)) { return (SBFI) } // For Windows 7 only report Interrupt; it doesn't support ACPI5.0 and wouldn't understand GpioInt nor I2cBus + Return (SBFG) + } + + Method (_STA, 0x0, NotSerialized) { + If (LEqual (SBTD, 1)) { + Return (0xF) + } + Return (0) + } + + Name (_S0W, 2) // required to put the device to D2 during S0 idle + } // Device BTH0 + +} // end Scope(\_SB.PCI0.URT1) + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Bluetooth/Bluetooth_BCM2EA1.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Bluetooth/Bluetooth_BCM2EA1.asl new file mode 100644 index 0000000000..815c6d3a98 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Bluetooth/Bluetooth_BCM2EA1.asl @@ -0,0 +1,55 @@ +/** @file + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(\_SB.PCI0.URT1) +{ + Device(BTH0) { + Method(_HID) { + // Return HID based on BIOS Setup + Return("BCM2EA1") + } + + Method(_INI) { + } + + Method(_CRS, 0x0, Serialized) { + Name(SBFG, ResourceTemplate (){ + UARTSerialBus(115200,,,0xc0,,,FlowControlHardware,32,32,"\\_SB.PCI0.URT1" ) + GpioIo(Exclusive, PullDown, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {27} // North-west(27):GPIO_214 NGFF_BT_DEV_WAKE_N + GpioIo(Exclusive, PullDown, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO2", ) {24} // West(24):GPIO_154, BT_DISABLE2_1P8_N + GpioInt (Level, ActiveLow, Exclusive, PullDefault, 0x0000, "\\_SB.GPO1", 0x00, ResourceConsumer, ) {35} + }) + + Name(SBFI, ResourceTemplate () { + UARTSerialBus(115200,,,0xc0,,,FlowControlHardware,32,32,"\\_SB.PCI0.URT1" ) + GpioIo(Exclusive, PullDown, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {27} // North-west(27):GPIO_214 NGFF_BT_DEV_WAKE_N + GpioIo(Exclusive, PullDown, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO2", ) {24} // West(24):GPIO_154, BT_DISABLE2_1P8_N + Interrupt(ResourceConsumer, Level, ActiveLow, Exclusive, ) {0x34} + }) + + If(LLess(OSYS,2012)) { return (SBFI) } // For Windows 7 only report Interrupt; it doesn't support ACPI5.0 and wouldn't understand GpioInt nor I2cBus + Return (SBFG) + } + + Method (_STA, 0x0, NotSerialized) { + If (LEqual (SBTD, 2)) { + Return (0xF) + } + Return (0) + } + + Name (_S0W, 2) // required to put the device to D2 during S0 idle + } // Device BTH0 + +} // end Scope(\_SB.PCI0.URT1) + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Camera/Camera_INT3471.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Camera/Camera_INT3471.asl new file mode 100644 index 0000000000..585e49d1fd --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Camera/Camera_INT3471.asl @@ -0,0 +1,187 @@ +/** @file + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(\_SB.PCI0.I2C2) +{ + Device (PMC1) { + Name (_ADR, Zero) + Name (_HID, "INT3472") + Name (_CID, "INT3472") + Name (_DDN, "INCL-CRDD") + Name (_UID, "0") + + Method (_CRS, 0x0, Serialized) { + Name (SBUF, ResourceTemplate() { + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, + "\\_SB.GPO0", 0x00, ResourceConsumer, ,) { + 0x37 // GPIO_67 + } + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, + "\\_SB.GPO0", 0x00, ResourceConsumer, ,) { + 0x3C // GPIO_72 + } + }) + + Return (SBUF) + } + + Method (_STA, 0, NotSerialized) { + If (LEqual (WCAS, 2)) { // 2-IMX135 + Return (0x0F) + } + Return (0x0) + } + + Method (CLDB, 0, Serialized) { + Name (PAR, Buffer(0x20) { + 0x00, //Version + 0x01, //Control logic Type 0: UNKNOWN 1: DISCRETE 2: PMIC TPS68470 3: PMIC uP6641 + 0x00, //Control logic ID: Control Logic 0 + 0x70, //CRD board Type, 0: UNKNOWN 0x20: CRD-D 0x30: CRD-G 0x40: PPV 0x50: CRD-G2 0x70: CRD_G_BXT + 0x00, 0x00, 0x00, 0x00, // Reserved + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Reserved + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Reserved + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Reserved + }) + Return (PAR) + } + + Method (_DSM, 4, NotSerialized) { + If (LEqual (Arg0, ToUUID("79234640-9E10-4FEA-A5C1-B5AA8B19756F"))) { + If (LEqual (Arg2, One)) { + Return (0x02) // number + } + If (LEqual (Arg2, 0x02)) { + Return (0x01004300) // RESET + } + If (LEqual (Arg2, 0x03)) { + Return (0x01004801) // POWER DOWN + } + } + Return (Zero) + } + } + + // + // Rear Camera IMX135 + // + Device (CAM1) { + Name (_ADR, Zero) + Name (_HID, "INT3471") + Name (_CID, "INT3471") + Name (_SUB, "INTL0000") + Name (_DDN, "SONY IMX135") + Name (_UID, One) + Name (_DEP, Package () { + \_SB.PCI0.I2C2.PMC1 + }) + Name (PLDB, Package(1) { + Buffer(0x14) + { + 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x69, 0x0C, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + 0xFF, 0xFF, 0xFF, 0xFF + } + }) + Method (_PLD, 0, Serialized) { + CreateField(DerefOf(Index(PLDB,0)), 115, 4, RPOS) // Rotation field + Store(CROT, RPOS) + + Return(PLDB) + } + + Method (_STA, 0, NotSerialized) { + If(LEqual (WCAS, 2)) { // 2-IMX135 + Return (0x0F) + } + Return (0x0) + } + + Method (SSDB, 0, Serialized) { + Name (PAR, Buffer(0x6C) { + 0x00, //Version + 0x70, //SKU: CRD_G_BXT + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //GUID for CSI2 host controller + 0x00, //DevFunction + 0x00, //Bus + 0x00, 0x00, 0x00, 0x00, //DphyLinkEnFuses + 0x00, 0x00, 0x00, 0x00, //ClockDiv + 0x06, //LinkUsed + 0x04, //LaneUsed + 0x00, 0x00, 0x00, 0x00, //CSI_RX_DLY_CNT_TERMEN_CLANE + 0x00, 0x00, 0x00, 0x00, //CSI_RX_DLY_CNT_SETTLE_CLANE + 0x00, 0x00, 0x00, 0x00, //CSI_RX_DLY_CNT_TERMEN_DLANE0 + 0x00, 0x00, 0x00, 0x00, //CSI_RX_DLY_CNT_SETTLE_DLANE0 + 0x00, 0x00, 0x00, 0x00, //CSI_RX_DLY_CNT_TERMEN_DLANE1 + 0x00, 0x00, 0x00, 0x00, //CSI_RX_DLY_CNT_SETTLE_DLANE1 + 0x00, 0x00, 0x00, 0x00, //CSI_RX_DLY_CNT_TERMEN_DLANE2 + 0x00, 0x00, 0x00, 0x00, //CSI_RX_DLY_CNT_SETTLE_DLANE2 + 0x00, 0x00, 0x00, 0x00, //CSI_RX_DLY_CNT_TERMEN_DLANE3 + 0x00, 0x00, 0x00, 0x00, //CSI_RX_DLY_CNT_SETTLE_DLANE3 + 0x00, 0x00, 0x00, 0x00, //MaxLaneSpeed + 0x00, //SensorCalibrationFileIdx + 0x00, 0x00, 0x00, //SensorCalibrationFileIdxInMBZ + 0x00, //RomType: NONE + 0x03, //VcmType: AD5816 + 0x08, //Platform info BXT + 0x00, //Platform sub info + 0x03, //Flash ENABLED + 0x00, //Privacy LED not supported + 0x00, //0 degree + 0x01, //MIPI link/lane defined in ACPI + 0x00, 0xF8, 0x24, 0x01, // MCLK: 19200000Hz + 0x00, //Control logic ID + 0x00, 0x00, 0x00, + 0x02, // M_CLK Port + 0x00, 0x00, 0x00, //Reserved + 0x00, 0x00, 0x00, 0x00, 0x00, //Reserved + 0x00, 0x00, 0x00, 0x00, 0x00, //Reserved + }) + Return (PAR) + } + + Method (_CRS, 0, Serialized) { + Name (SBUF, ResourceTemplate() { + I2CSerialBus(0x0010, ControllerInitiated, 0x00061A80, AddressingMode7Bit, + "\\_SB.PCI0.I2C2", 0x00, ResourceConsumer,,) + I2CSerialBus(0x000E, ControllerInitiated, 0x00061A80, AddressingMode7Bit, + "\\_SB.PCI0.I2C2", 0x00, ResourceConsumer,,) + }) + Return(SBUF) + } + + Method (_DSM, 4, NotSerialized) + { + If (LEqual (Arg0, ToUUID ("822ACE8F-2814-4174-A56B-5F029FE079EE"))) { + Return("13P2BAD33") + } + + If (LEqual (Arg0, ToUUID ("26257549-9271-4CA4-BB43-C4899D5A4881"))) { + If (LEqual (Arg2, One)) { + Return (0x02) + } + If (LEqual (Arg2, 0x02)) { + // I2C 0:bit31-24:BUS. 23-16:Speed.15-8:Addr. 0-7:Function + Return (0x02001000) // SENSOR + } + If (LEqual (Arg2, 0x03)) { + // I2C 0:bit31-24:BUS. 23-16:Speed.15-8:Addr. 0-7:Function + Return (0x02000E01) // VCM + } + } + + Return(Zero) + } + } +} // Scope(\_SB.PCI0.I2C2) + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Camera/Camera_INT3474.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Camera/Camera_INT3474.asl new file mode 100644 index 0000000000..b3c6be7a24 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Camera/Camera_INT3474.asl @@ -0,0 +1,196 @@ +/** @file + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(\_SB.PCI0.I2C0) +{ + Device(PMC0) + { + Name(_ADR, Zero) + Name(_HID, "INT3472") + Name(_CID, "INT3472") + Name(_DDN, "INCL-CRDD") + Name(_UID, "1") + + Method(_CRS, 0x0, Serialized) + { + Name(SBUF, ResourceTemplate() + { + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, + "\\_SB.GPO0", 0x00, ResourceConsumer, ,) + { // Pin list + 0x35 // GPIO_65 + } + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, + "\\_SB.GPO0", 0x00, ResourceConsumer, ,) + { // Pin list + 0x3B // GPIO_71 + } + }) + Return (SBUF) + } + + Method(_STA, 0, NotSerialized) // _STA: Status + { + If (LEqual (UCAS, 1)) { // 1-OV2740 + Return (0x0F) + } else { + Return (0x0) + } + } + Method(CLDB, 0, Serialized) + { + Name(PAR, Buffer(0x20) + { + 0x00, //Version + 0x01, //Control logic Type 0: UNKNOWN 1: DISCRETE 2: PMIC TPS68470 3: PMIC uP6641 + 0x01, //Control logic ID: Control Logic 1 + 0x70, //CRD board Type, 0: UNKNOWN 0x20: CRD-D 0x30: CRD-G 0x40: PPV 0x50: CRD-G2 0x70: CRD_G_BXT + 0x00, 0x00, 0x00, 0x00, // Reserved + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Reserved + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Reserved + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Reserved + }) + Return (PAR) + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + If (LEqual (Arg0, ToUUID("79234640-9E10-4FEA-A5C1-B5AA8B19756F"))) { + If (LEqual (Arg2, One)) { + Return (0x02) // number + } + If (LEqual (Arg2, 0x02)) { + Return (0x01004100) // RESET + } + If (LEqual (Arg2, 0x03)) { + Return (0x01004701) // POWER DOWN + } + } + Return (Zero) + } + } + + Device(CAM0) + { + Name(_ADR, Zero) + Name(_HID, "INT3474") + Name(_CID, "INT3474") + Name(_SUB, "INTL0000") + Name(_DDN, "OV2740") + Name(_UID, One) + + Name (_DEP, Package () // _DEP: Dependencies + { + \_SB.PCI0.I2C0.PMC0 + }) + + Name(PLDB, Package(1) + { + Buffer(0x14) + { + 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x61, 0x0C, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + 0xFF, 0xFF, 0xFF, 0xFF + } + }) + + Method(_PLD, 0, Serialized) + { + CreateField(DerefOf(Index(PLDB,0)), 115, 4, RPOS) // Rotation field + Store(CROT, RPOS) + + Return(PLDB) + } + + Method(_STA, 0, NotSerialized) + { + If (LEqual (UCAS, 1)) { // 1-OV2740 + Return (0x0F) + } else { + Return (0x0) + } + } + Method(SSDB, 0, Serialized) + { + Name(PAR, Buffer(0x6C) + { + 0x00, //Version + 0x70, //SKU: CRD_G_BXT + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //GUID for CSI2 host controller + 0x00, //DevFunction + 0x00, //Bus + 0x00, 0x00, 0x00, 0x00, //DphyLinkEnFuses + 0x00, 0x00, 0x00, 0x00, //ClockDiv + 0x02, //LinkUsed + 0x02, //LaneUsed + 0x00, 0x00, 0x00, 0x00, //CSI_RX_DLY_CNT_TERMEN_CLANE + 0x00, 0x00, 0x00, 0x00, //CSI_RX_DLY_CNT_SETTLE_CLANE + 0x00, 0x00, 0x00, 0x00, //CSI_RX_DLY_CNT_TERMEN_DLANE0 + 0x00, 0x00, 0x00, 0x00, //CSI_RX_DLY_CNT_SETTLE_DLANE0 + 0x00, 0x00, 0x00, 0x00, //CSI_RX_DLY_CNT_TERMEN_DLANE1 + 0x00, 0x00, 0x00, 0x00, //CSI_RX_DLY_CNT_SETTLE_DLANE1 + 0x00, 0x00, 0x00, 0x00, //CSI_RX_DLY_CNT_TERMEN_DLANE2 + 0x00, 0x00, 0x00, 0x00, //CSI_RX_DLY_CNT_SETTLE_DLANE2 + 0x00, 0x00, 0x00, 0x00, //CSI_RX_DLY_CNT_TERMEN_DLANE3 + 0x00, 0x00, 0x00, 0x00, //CSI_RX_DLY_CNT_SETTLE_DLANE3 + 0x00, 0x00, 0x00, 0x00, //MaxLaneSpeed + 0x00, //SensorCalibrationFileIdx + 0x00, 0x00, 0x00, //SensorCalibrationFileIdxInMBZ + 0x00, //RomType: NONE + 0x00, //VcmType: none + 0x08, //Platform info BXT + 0x00, //Platform sub info + 0x02, //Flash none + 0x00, //Privacy LED not supported + 0x00, //0 degree + 0x01, //MIPI link/lane defined in ACPI + 0x00, 0xF8, 0x24, 0x01, // MCLK: 19200000Hz + 0x01, //Control logic ID + 0x00, 0x00, 0x00, + 0x01, // M_CLK + 0x00, 0x00, 0x00, //Reserved + 0x00, 0x00, 0x00, 0x00, 0x00, //Reserved + 0x00, 0x00, 0x00, 0x00, 0x00, //Reserved + }) + Return (PAR) + } + + Method(_CRS, 0, Serialized) + { + Name(SBUF, ResourceTemplate() + { + I2CSerialBus(0x0036, ControllerInitiated, 0x00061A80, AddressingMode7Bit, + "\\_SB.PCI0.I2C0", 0x00, ResourceConsumer,,) + }) + Return(SBUF) + } + + Method(_DSM, 4, NotSerialized) + { + If (LEqual(Arg0, ToUUID("822ACE8F-2814-4174-A56B-5F029FE079EE"))) { + Return("4SF259T2") + } + If (LEqual(Arg0, ToUUID("26257549-9271-4CA4-BB43-C4899D5A4881"))) { + If (LEqual(Arg2, One)) { + Return(One) + } + If (LEqual(Arg2, 0x02)) { + // I2C 0:bit31-24:BUS. 23-16:Speed.15-8:Addr. 0-7:Function + Return(0x00003600) // SENSOR + } + } + Return(Zero) + } + } +} + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Camera/Camera_Sony214A.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Camera/Camera_Sony214A.asl new file mode 100644 index 0000000000..721e867b8b --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Camera/Camera_Sony214A.asl @@ -0,0 +1,188 @@ +/** @file + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(\_SB.PCI0.I2C2) +{ + Device (PMC2) { + Name (_ADR, Zero) + Name (_HID, "INT3472") + Name (_CID, "INT3472") + Name (_DDN, "INCL-CRDD") + Name (_UID, "0") + + Method (_CRS, 0x0, Serialized) { + Name (SBUF, ResourceTemplate() { + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, + "\\_SB.GPO0", 0x00, ResourceConsumer, ,) { + 0x37 // GPIO_67 + } + + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, + "\\_SB.GPO0", 0x00, ResourceConsumer, ,) { + 0x3C // GPIO_72 + } + }) + Return (SBUF) + } + + Method (_STA, 0, NotSerialized) { + If (LEqual (WCAS, 1)) { // 1-IMX214 + Return (0x0F) + } + Return (0x0) + } + + Method (CLDB, 0, Serialized) { + Name (PAR, Buffer(0x20) { + 0x00, //Version + 0x01, //Control logic Type 0: UNKNOWN 1: DISCRETE 2: PMIC TPS68470 3: PMIC uP6641 + 0x00, //Control logic ID: Control Logic 0 + 0x70, //CRD board Type, 0: UNKNOWN 0x20: CRD-D 0x30: CRD-G 0x40: PPV 0x50: CRD-G2 0x70: CRD_G_BXT + 0x00, 0x00, 0x00, 0x00, // Reserved + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Reserved + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Reserved + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Reserved + }) + Return (PAR) + } + + Method (_DSM, 4, NotSerialized) { + If (LEqual (Arg0, ToUUID("79234640-9E10-4FEA-A5C1-B5AA8B19756F"))) { + If (LEqual (Arg2, One)) { + Return (0x02) // number + } + If (LEqual (Arg2, 0x02)) { + Return (0x01004300) // RESET + } + If (LEqual (Arg2, 0x03)) { + Return (0x01004801) // POWER DOWN + } + } + Return (Zero) + } + } + + // + // Rear Camera IMX214A + // + Device (CAM2) { + Name (_ADR, Zero) + Name (_HID, "SONY214A") + Name (_CID, "SONY214A") + Name (_SUB, "INTL0000") + Name (_DDN, "SONY IMX214") + Name (_UID, One) + + Name (_DEP, Package () { + \_SB.PCI0.I2C2.PMC2 + }) + + Name (PLDB, Package(1) { + Buffer(0x14) + { + 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x69, 0x0C, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + 0xFF, 0xFF, 0xFF, 0xFF + } + }) + Method (_PLD, 0, Serialized) { + CreateField(DerefOf(Index(PLDB,0)), 115, 4, RPOS) // Rotation field + Store(CROT, RPOS) + + Return(PLDB) + } + + Method (_STA, 0, NotSerialized) { + If (LEqual (WCAS, 1)) { // 1-IMX214 + Return (0x0F) + } + Return (0x0) + } + + Method (SSDB, 0, Serialized) { + Name (PAR, Buffer(0x6C) { + 0x00, //Version + 0x70, //SKU: CRD_G_BXT + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //GUID for CSI2 host controller + 0x00, //DevFunction + 0x00, //Bus + 0x00, 0x00, 0x00, 0x00, //DphyLinkEnFuses + 0x00, 0x00, 0x00, 0x00, //ClockDiv + 0x06, //LinkUsed + 0x04, //LaneUsed + 0x00, 0x00, 0x00, 0x00, //CSI_RX_DLY_CNT_TERMEN_CLANE + 0x00, 0x00, 0x00, 0x00, //CSI_RX_DLY_CNT_SETTLE_CLANE + 0x00, 0x00, 0x00, 0x00, //CSI_RX_DLY_CNT_TERMEN_DLANE0 + 0x00, 0x00, 0x00, 0x00, //CSI_RX_DLY_CNT_SETTLE_DLANE0 + 0x00, 0x00, 0x00, 0x00, //CSI_RX_DLY_CNT_TERMEN_DLANE1 + 0x00, 0x00, 0x00, 0x00, //CSI_RX_DLY_CNT_SETTLE_DLANE1 + 0x00, 0x00, 0x00, 0x00, //CSI_RX_DLY_CNT_TERMEN_DLANE2 + 0x00, 0x00, 0x00, 0x00, //CSI_RX_DLY_CNT_SETTLE_DLANE2 + 0x00, 0x00, 0x00, 0x00, //CSI_RX_DLY_CNT_TERMEN_DLANE3 + 0x00, 0x00, 0x00, 0x00, //CSI_RX_DLY_CNT_SETTLE_DLANE3 + 0x00, 0x00, 0x00, 0x00, //MaxLaneSpeed + 0x00, //SensorCalibrationFileIdx + 0x00, 0x00, 0x00, //SensorCalibrationFileIdxInMBZ + 0x00, //RomType: NONE + 0x02, //VcmType: DW9714A + 0x08, //Platform info BXT + 0x00, //Platform sub info + 0x03, //Flash ENABLED + 0x00, //Privacy LED not supported + 0x00, //0 degree + 0x01, //MIPI link/lane defined in ACPI + 0x00, 0xF8, 0x24, 0x01, // MCLK: 19200000Hz + 0x00, //Control logic ID + 0x00, 0x00, 0x00, + 0x02, // M_CLK Port + 0x00, 0x00, 0x00, //Reserved + 0x00, 0x00, 0x00, 0x00, 0x00, //Reserved + 0x00, 0x00, 0x00, 0x00, 0x00, //Reserved + }) + Return (PAR) + } + + Method (_CRS, 0, Serialized) { + Name (SBUF, ResourceTemplate() { + I2CSerialBus(0x001A, ControllerInitiated, 0x00061A80, AddressingMode7Bit, + "\\_SB.PCI0.I2C2", 0x00, ResourceConsumer,,) + I2CSerialBus(0x000C, ControllerInitiated, 0x00061A80, AddressingMode7Bit, + "\\_SB.PCI0.I2C2", 0x00, ResourceConsumer,,) + }) + Return(SBUF) + } + + Method (_DSM, 4, NotSerialized) + { + If (LEqual (Arg0, ToUUID ("822ACE8F-2814-4174-A56B-5F029FE079EE"))) { + Return("P13N05BA") + } + + If (LEqual (Arg0, ToUUID ("26257549-9271-4CA4-BB43-C4899D5A4881"))) { + If (LEqual (Arg2, One)) { + Return (0x02) + } + If (LEqual (Arg2, 0x02)) { + // I2C 0:bit31-24:BUS. 23-16:Speed.15-8:Addr. 0-7:Function + Return (0x02001A00) // SENSOR + } + If (LEqual (Arg2, 0x03)) { + // I2C 0:bit31-24:BUS. 23-16:Speed.15-8:Addr. 0-7:Function + Return (0x02000C01) // VCM + } + } + Return(Zero) + } + } +} // Scope(\_SB.PCI0.I2C2) + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Camera/Flash_TPS61311.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Camera/Flash_TPS61311.asl new file mode 100644 index 0000000000..b16fff32ab --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Camera/Flash_TPS61311.asl @@ -0,0 +1,93 @@ +/** @file + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope (\_SB.PCI0.I2C2) +{ + Device (STRB) + { + Name (_ADR, Zero) // _ADR: Address + Name (_HID, "INT3481") // _HID: Hardware ID + Name (_CID, "INT3481") // _CID: Compatible ID + Name (_SUB, "INTL0000") // _SUB: Subsystem ID + Name (_DDN, "Flash TPS61311") // _DDN: DOS Device Name + Name (_UID, Zero) // _UID: Unique ID + Name (PLDB, Package (0x01) + { + Buffer (0x14) + { + /* 0000 */ 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ........ */ + /* 0008 */ 0x69, 0x0C, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, /* i....... */ + /* 0010 */ 0xFF, 0xFF, 0xFF, 0xFF /* .... */ + } + }) + + Method (_PLD, 0, Serialized) // _PLD: Physical Location of Device + { + Return (PLDB) /* \_SB_.PCI0.I2C2.STRB.PLDB */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + Name (SBUF, ResourceTemplate () + { + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, + "\\_SB.GPO0", 0x00, ResourceConsumer, , + ) + { // Pin list + 0x0036 + } + I2cSerialBus (0x0033, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C2", + 0x00, ResourceConsumer, , + ) + }) + Return (SBUF) /* \_SB_.PCI0.I2C2.STRB._CRS.SBUF */ + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + If (LEqual(Arg0,ToUUID ("377ba76a-f390-4aff-ab38-9b1bf33a3015"))) { + Return ("INT3481") + } + If (LEqual(Arg0,ToUUID ("3c62aaaa-d8e0-401a-84c3-fc05656fa28c"))) { + Return ("TPS61311") + } + If (LEqual(Arg0,ToUUID ("2959512a-028c-4646-b73d-4d1b5672fad8"))) { + Return ("BXT") + } + If (LEqual(Arg0,ToUUID ("26257549-9271-4ca4-bb43-c4899d5a4881"))) { + If (LEqual(Arg2,One)) { + Return (One) + } + If (LEqual(Arg2,0x02)) { + Return (0x02003300) + } + } + If (LEqual(Arg0,ToUUID ("79234640-9e10-4fea-a5c1-b5aa8b19756f"))) { + If (LEqual(Arg2,One)) { + Return (One) + } + If (LEqual(Arg2,0x02)) { + Return (0x01003604) + } + } + Return (Zero) + } + } +} + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Fingerprint/Fingerprint_FPC.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Fingerprint/Fingerprint_FPC.asl new file mode 100644 index 0000000000..03d73f2d9c --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Fingerprint/Fingerprint_FPC.asl @@ -0,0 +1,50 @@ +/** @file + Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +External(\SDS1, IntObj) + +//----------------------------- +// Serial IO SPI1 Controller +//----------------------------- +Scope(\_SB.PCI0.SPI1) +{ + Device(FPNT) { + Method(_HID) { + // + // Return FPS HID based on BIOS Setup + // + if (LEqual(SDS1, 1)) {Return ("FPC1020")} + if (LEqual(SDS1, 2)) {Return ("FPC1021")} + Return ("FPNT_DIS") + } + + Method(_STA) { + // + // Is SerialIo SPI1 FPS enabled in BIOS Setup? + // + If (LNotEqual(SDS1, 0)) { + Return (0x0F) + } + Return (0x00) + } + Method(_CRS, 0x0, Serialized) { + Name(BBUF,ResourceTemplate () { + SPISerialBus(0x00,PolarityLow,FourWireMode,8,ControllerInitiated,3000000,ClockPolarityLow,ClockPhaseFirst,"\\_SB.PCI0.SPI1",,,SPIR) + GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1",,,GSLP) {67} //North-west(67):GPIO_112 FGR_RESET_N + GpioInt (Edge, ActiveHigh, ExclusiveAndWake, PullDefault, 0x0000, "\\_SB.GPO0", 0x00, ResourceConsumer,GINT ) {14} //North(14):GPIO_14 : FGR_INT + }) + Return (BBUF) + } + } // Device (FPNT) +} // end Scope(\_SB.PCI0.SPI1) + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Gps/Gps.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Gps/Gps.asl new file mode 100644 index 0000000000..f011d8e016 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Gps/Gps.asl @@ -0,0 +1,56 @@ +/** @file + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +External(\GSBC, IntObj) + +Scope(\_SB.PCI0.URT2) +{ + Device(GPS1)//GPS for Windows OS. + { + Name(_HID, "BCM4752") //Vendor: test GPS device for BYT + Name(_HRV, 0x0001) + + Method(_STA, 0x0, NotSerialized) + { + If (LEqual (GSBC, 1)) { + Return (0xF) + } + Return (0) + } + + Method(_CRS, 0x0, Serialized) + { + // UARTSerial Bus Connection Descriptor + Name(BBUF, ResourceTemplate () { + UARTSerialBus( + 115200, // InitialBaudRate: in bits ber second + , // BitsPerByte: default to 8 bits + , // StopBits: Defaults to one bit + 0xfc, // LinesInUse: 8 1-bit flags to declare line enabled + , // IsBigEndian: default to LittleEndian + , // Parity: Defaults to no parity + FlowControlHardware, // FlowControl: Defaults to no flow control + 32, // ReceiveBufferSize + 32, // TransmitBufferSize + "\\_SB.PCI0.URT2", // ResourceSource: UART bus controller name + ,) // DescriptorName: creates name for offset of resource descriptor + // + //Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {62} // GPS_HOSTREQ IRQ - 62 + GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO1", ) {36} // GNSS_UART_WAKE_N + }) + Return (BBUF) + } + + } // Device GPS1 +} + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Irmt.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Irmt.asl new file mode 100644 index 0000000000..c68e66467c --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Irmt.asl @@ -0,0 +1,99 @@ +/** @file + ACPI interface for Intel Ready Mode Technology(IRMT) + + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +DefinitionBlock ( + "IrmtAcpi.aml", + "SSDT", + 2, + "Intel_", + "IrmtTabl", + 0x1000 + ) +{ + External(IRMC) // Irmt Configuration + External(\_SB.PCI0.GFX0.TCHE) // Technology enabled indicator + External(\_SB.PCI0.GFX0.STAT) // State Indicator + + Scope (\_SB) { + Device (AOAA) { + Name (_HID, "INT3398") + + Name (NSMD, 0x00) // Used to store mode settings: + /** + Bits Description + - (1:0) 00: Leave Never Sleep Mode; + 01: Enter Never Sleep Mode. + 10: Power Reduction Mode + 11: Enter Do Not Disturb mode. + - (7:2) Reserved: Set to 0. + **/ + + Method (_STA, 0) + { + // + //The Intel RMT ACPI device is a hidden device and + //listed under system devices on Device Manager. + // + Return (0x0B) + } + + /** + GNSC - Get Never Sleep Configuration + Input: None + Return: + Bits Description + - 0 State(Never Sleep Enabling Status in BIOS): 0 = Disabled, 1 = Enabled + - 1 Notification(Hardware notification enabling status): 0 = Unsupported, 1 = Supported + - (7:2) Reserved: Set to 0. + **/ + Method (GNSC, 0, NotSerialized, 0, IntObj) { + Return (IRMC) + } + + /** + GNSM - Get Never Sleep Mode + Input: None + Return: + Bits Description + - (1:0) 00: Leave Never Sleep Mode; + 01: Enter Never Sleep Mode. + 10: Power Reduction Mode + 11: Enter Do Not Disturb mode. + - (7:2) Reserved: Set to 0. + **/ + Method (GNSM, 0, NotSerialized, 0, IntObj) { + Return (NSMD) + } + + /** + SNSM - Set Never Sleep Mode + Input: + Bits Description + - (1:0) 00: Leave Never Sleep Mode; + 01: Enter Never Sleep Mode. + 10: Power Reduction Mode + 11: Enter Do Not Disturb mode. + - (7:2) Reserved: Set to 0. + Return: + **/ + Method (SNSM, 1, NotSerialized, 0, UnknownObj, IntObj) { + And(Arg0, 0x3, NSMD) + } + + } // Device (AOAA) + } // Scope (\_SB) +} // End SSDT + + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Nfc/Nfc.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Nfc/Nfc.asl new file mode 100644 index 0000000000..cd0f383da8 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Nfc/Nfc.asl @@ -0,0 +1,70 @@ +/** @file + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +/* +NXP NPC100 non-secure NFC +* I2C 1(0 based) +* Slave address: 0x29 +* IRQ : GPIO_20, direct IRQ, level high +* Reset : GPIO_150, output +* Fw update : GPIO_27, output +*/ +External(\NFCN, IntObj) + +Scope (\_SB.PCI0.I2C1) +{ + Device (NFC1) + { + Name (_ADR, Zero) // _ADR: Address + Name (_HID, EISAID("NXP1001")) // _HID: Hardware ID + Name (_DDN, "NXP NPC100") // _DDN: DOS Device Name + Name (_UID, One) // _UID: Unique ID + + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + Name (SBUF, ResourceTemplate () + { + I2cSerialBus (0x29, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C1", + 0x00, ResourceConsumer, , + ) + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + 0x00000077, // GPIO_20 + } + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, + "\\_SB.GPO0", 0x00, ResourceConsumer, , + ) + { // Pin list, GPIO_27 + 0x001B + } + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, + "\\_SB.GPO2", 0x00, ResourceConsumer, , + ) + { // Pin list, GPIO_150 + 0x0014 + } + }) + Return (SBUF) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (LEqual (NFCN, 1)) { + Return (0xF) + } + Return (0) + } + } // Device (NFC1) +} // Scope (\_SB.PCI0.I2C1) + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/PSS/MonzaX2K_IMPJ0003.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/PSS/MonzaX2K_IMPJ0003.asl new file mode 100644 index 0000000000..c821139205 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/PSS/MonzaX2K_IMPJ0003.asl @@ -0,0 +1,51 @@ +/** @file + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +External(\PSSI, IntObj) + +Scope(\_SB.PCI0.I2C7){ +//------------------------ +// PSS on I2C7 +//------------------------ +/* +PSS: Monza_X-2K_Dura +* GPIO: None +* I2C bus: I2C 7 (0 based) +* I2C slave address: 0x6E +* I2C frequency: 400K +* ACPI ID: IMPJ0003 +*/ + Device (IMP3) + { + Name (_ADR, Zero) // _ADR: Address + Name (_HID, "IMPJ0003") // _HID: Hardware ID + Name (_CID, "IMPJ0003") // _CID: Compatible ID + Name (_UID, One) // _UID: Unique ID + + Method(_STA, 0x0, NotSerialized) { + If (LEqual (PSSI, 1)) { + Return (0xF) + } + Return (0) + } + + Method (_CRS, 0, Serialized) { + Name (SBUF, ResourceTemplate () { + I2cSerialBus (0x6E,ControllerInitiated,400000,AddressingMode7Bit,"\\_SB.PCI0.I2C7",0x00,ResourceConsumer,,) + }) + Return (SBUF) + } + + } // Device (IMP3) +} //Scope(\_SB.PCI0.I2C7) + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/PlatformSsdt.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/PlatformSsdt.asl new file mode 100644 index 0000000000..fd7feddf75 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/PlatformSsdt.asl @@ -0,0 +1,71 @@ +/** @file + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +DefinitionBlock ( + "PlatformSsdt.aml", + "SSDT", + 1, + "Intel_", + "PlatformTable", + 0x1000 + ) +{ + External(\_SB.PCI0.I2C0, DeviceObj) + External(\_SB.PCI0.I2C1, DeviceObj) + External(\_SB.PCI0.I2C2, DeviceObj) + External(\_SB.PCI0.I2C3, DeviceObj) + External(\_SB.PCI0.I2C4, DeviceObj) + External(\_SB.PCI0.I2C7, DeviceObj) + External(\_SB.PCI0.URT1, DeviceObj) + External(\_SB.PCI0.URT2, DeviceObj) + External(\_SB.PCI0.SDIO, DeviceObj) + External(\_SB.PCI0.SPI1, DeviceObj) + External(\_SB.GPO0.CWLE, IntObj) + External(\_SB.GPO0.AVBL, IntObj) + External(\_SB.PCI0.SDIO.PSTS, IntObj) + External(HIDG, MethodObj) + External(OSYS, IntObj) + External(SBTD, IntObj) + External(WCAS, IntObj) + External(UCAS, IntObj) + External(CROT, IntObj) + External(TP7G) + External(IPUD) + + include ("Audio/AudioCodec_INT34C1.asl") + include ("Audio/AudioCodec_INT343A.asl") + + If (LEqual(IPUD, 1)) { + include ("Camera/Camera_INT3471.asl") + include ("Camera/Camera_INT3474.asl") + include ("Camera/Camera_Sony214A.asl") + include ("Camera/Flash_TPS61311.asl") + } + + include ("Touch/TouchPanel_I2C3.asl") + include ("Touch/TouchPads_I2C4.asl") + + include ("PSS/MonzaX2K_IMPJ0003.asl") + + include ("Bluetooth/Bluetooth_BCM2E40.asl") + + include ("Wifi/WIFI_Broadcom1.asl") + include ("Wifi/WIFI_Broadcom2.asl") + + include ("Gps/Gps.asl") + + include ("Nfc/Nfc.asl") + + include ("Fingerprint/Fingerprint_FPC.asl") +} + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/PlatformSsdt.inf b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/PlatformSsdt.inf new file mode 100644 index 0000000000..96a8ded34e --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/PlatformSsdt.inf @@ -0,0 +1,31 @@ +## @file +# Component description file for PlatformAcpiTable module. +# +# Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformSsdt + FILE_GUID = 8041F38B-0A34-49D7-A905-03AEEF4826F7 + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + EDK_RELEASE_VERSION = 0x00020000 + EFI_SPECIFICATION_VERSION = 0x00020000 + +[sources] + Irmt.asl + PlatformSsdt.asl + +[Packages] + MdePkg/MdePkg.dec + BroxtonSiPkg/BroxtonSiPkg.dec diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Touch/TouchPads_I2C4.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Touch/TouchPads_I2C4.asl new file mode 100644 index 0000000000..9094e3ab7b --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Touch/TouchPads_I2C4.asl @@ -0,0 +1,115 @@ +/** @file + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +External(\TCPD, IntObj) + +Scope(\_SB.PCI0.I2C4) { +//------------------------ +// Touch Pads on I2C4 +// Note: instead of adding more touch devices, parametrize this one with appropriate _HID value and GPIO numbers +// GPIO_18:TCHPAD_INT_N North West Community, IRQ number 0x75. +//------------------------ + + Device(TPD0) + { + Name(_ADR, One) + Name(_HID, "ALPS0001") + Name(_CID, "PNP0C50") + Name(_UID, One) + Name(_S0W, 4) // required to put the device to D3 Cold during S0 idle + Name (SBFB, ResourceTemplate () { + I2cSerialBus ( + 0x2C, + ControllerInitiated, + 400000, + AddressingMode7Bit, + "\\_SB.PCI0.I2C4", + 0x00, + ResourceConsumer, + , + ) + }) + Name (SBFG, ResourceTemplate () { + GpioInt (Level, ActiveLow, Exclusive, PullDefault, 0x0000, "\\_SB.GPO0", 0x00, ResourceConsumer, ,) + { // Pin list + 0x0012 + } + }) + Name (SBFI, ResourceTemplate () { + Interrupt(ResourceConsumer, Level, ActiveLow, ExclusiveAndWake,,,) + { + 0x75, + } + }) + Method (_INI, 0, NotSerialized) + { + } + Method (_STA, 0, NotSerialized) + { + If (LEqual (TCPD, 1)) { + Return (0x0F) + } + Return (0x00) + } + Method (_CRS, 0, NotSerialized) + { + If (LLess (OSYS, 2012)) { + Return (SBFI) + } + Return (ConcatenateResTemplate (SBFB, SBFI)) + } + Method(_DSM, 0x4, NotSerialized) + { + // DSM UUID for HIDI2C. Do Not change. + If (LEqual(Arg0, ToUUID("3CDFF6F7-4267-4555-AD05-B30A3D8938DE"))) { + // Function 0 : Query Function + If (LEqual(Arg2, Zero)) { + // Revision 1 + If (LEqual(Arg1, One)) { + Return (Buffer (One) {0x03}) + } + Else + { + Return (Buffer (One) {0x00}) + } + } ElseIf (LEqual(Arg2, One)) { // Function 1 : HID Function + // HID Descriptor Address (IHV Specific) + Return(0x0020) + } Else { + Return (Buffer (One) {0x00}) + } + } + Else + { + If (LEqual(Arg0, ToUUID("EF87EB82-F951-46DA-84EC-14871AC6F84B"))) { + If (LEqual (Arg2, Zero)) { + If (LEqual (Arg1, One)) { + Return (Buffer (One) {0x03}) + } + } + + If (LEqual (Arg2, One)) { + Return (ConcatenateResTemplate (SBFB, SBFG)) + } + + Return (Buffer (One) {0x00}) + } + Else + { + Return (Buffer (One) {0x00}) + } + } + } + } +} //Scope(\_SB.PCI0.I2C4) + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Touch/TouchPanel_I2C3.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Touch/TouchPanel_I2C3.asl new file mode 100644 index 0000000000..07196c0606 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Touch/TouchPanel_I2C3.asl @@ -0,0 +1,142 @@ +/** @file + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +External(\TCPL, IntObj) + +Scope(\_SB.PCI0.I2C3) { +//------------------------ +// Touch Panels on I2C3 +// Note: instead of adding more touch panels, parametrize this one with appropriate _HID value and GPIO numbers +// GPIO_21:TCH_PNL_INTR_LS_N North Community, IRQ number 0x32. +//------------------------ + Device (TPL1) { + Name (HID2, Zero) + Name (_HID, "ELAN221D") // _HID: Hardware ID + Name (_CID, "PNP0C50") // _CID: Compatible ID + Name (_S0W, 0x04) // _S0W: S0 Device Wake State + Name (SBFB, ResourceTemplate () { + I2cSerialBus ( + 0x0010, + ControllerInitiated, + 400000, + AddressingMode7Bit, + "\\_SB.PCI0.I2C3", + 0x00, + ResourceConsumer, + , + ) + }) + Name (SBFG, ResourceTemplate () { + GpioInt (Level, ActiveLow, Exclusive, PullDefault, 0x0000, + "\\_SB.GPO0", 0x00, ResourceConsumer, , + ) + { // Pin list + 0x0015 + } + }) + Name (SBFI, ResourceTemplate () { + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, ,, ) + { + 0x32, + } + }) + + Method (_INI, 0, NotSerialized) // _INI: Initialize + { + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (LEqual (TCPL, 1)) { + Return (0x0F) + } + Return (0x00) + } + + Method (_CRS, 0, NotSerialized) { + If (LLess (OSYS,2012)) { + // For Windows 7 only report Interrupt; it doesn't support ACPI5.0 and wouldn't understand GpioInt nor I2cBus + return (SBFI) + } + Return (ConcatenateResTemplate(SBFB, SBFI)) + } + + Method(_DSM, 0x4, Serialized){ + Store ("Method _DSM begin", Debug) + If (LEqual(Arg0, ToUUID("3CDFF6F7-4267-4555-AD05-B30A3D8938DE"))) { + // DSM Function + switch(ToInteger(Arg2)) + { + // Function 0: Query function, return based on revision + case(0) + { + // DSM Revision + switch(ToInteger(Arg1)) + { + // Revision 1: Function 1 supported + case(1) + { + Store ("Method _DSM Function Query", Debug) + Return(Buffer(One) { 0x03 }) + } + + default + { + // Revision 2+: no functions supported + Return(Buffer(One) { 0x00 }) + } + } + } + + // Function 1 : HID Function + case(1) + { + Store ("Method _DSM Function HID", Debug) + // HID Descriptor Address + Return(0x0001) + } + + default + { + // Functions 2+: not supported + Return(0x0000) + } + } + } + Elseif(LEqual(Arg0, ToUUID("EF87EB82-F951-46DA-84EC-14871AC6F84B"))) + { // Windows 7 Resources DSM (Intel specific) + + // Function 0 : Query Function + If (LEqual(Arg2, Zero)) { + // Revision 1 + If (LEqual(Arg1, One)) { + Return(Buffer(One) { 0x03 }) + } + } + // Function 1 : I2CSerialBus(...) and GpioInt(...) resources + If (LEqual(Arg2, One)) { + Return (ConcatenateResTemplate(SBFB, SBFG)) + } + + Return(Buffer(One) { 0x00 }) + } + else + { + // No other GUIDs supported + Return(Buffer(One) { 0x00 }) + } + } + + } // Device (TPL0) +} //Scope(\_SB.PCI0.I2C3) + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Wifi/WIFI_Broadcom1.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Wifi/WIFI_Broadcom1.asl new file mode 100644 index 0000000000..8a48108e36 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Wifi/WIFI_Broadcom1.asl @@ -0,0 +1,68 @@ +/** @file + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +/* + GPIO_10 for Wi-Fi direct IRQ 0x6D. + GPIO_15 for Wi-Fi reset + PMIC_STDBY for Wi-Fi disable, NW index 30 +*/ + + +Scope(\_SB.PCI0.SDIO) +{ + Device (BRCM) + { + Name (_ADR, One) // _ADR: Address + Name (_DEP, Package() {\_SB.GPO0}) + Name (_S4W, 2) + Name (_S0W, 2) + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } + + Method (_RMV, 0, NotSerialized) + { + Return (Zero) + } + + Name (_PRW, Package (0x02) + { + Zero, + Zero + }) + + Method (_CRS, 0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Interrupt (ResourceConsumer, Edge, ActiveHigh, ExclusiveAndWake, , , ) {0x6D} // GPIO_10 to IOAPIC IRQ 0x6D + }) + Return (RBUF) + } + + Method (_PS3, 0, NotSerialized) + { + Store( 0x00, \_SB.GPO0.CWLE ) // Put WiFi chip in Reset + Sleep(150) + } + + Method (_PS0, 0, NotSerialized) + { + Store( 0x01, \_SB.GPO0.CWLE ) // Take WiFi chip out in Reset + Sleep(150) + } + } +} + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Wifi/WIFI_Broadcom2.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Wifi/WIFI_Broadcom2.asl new file mode 100644 index 0000000000..52db361659 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Wifi/WIFI_Broadcom2.asl @@ -0,0 +1,49 @@ +/** @file + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(\_SB.PCI0.SDIO) +{ + Device (BRC2) + { + Name (_ADR, 0x02) + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } + + Method (_RMV, 0, NotSerialized) + { + Return (Zero) + } + + Method (_CRS, 0, Serialized) + { + Name (NAM, Buffer () + { // 20 + "\\_SB.PCI0.SDIO.BRCM" + }) + Name (SPB, Buffer () + { + /* 0000 */ 0x8E, 0x1D, 0x00, 0x01, 0x00, 0xC0, 0x02, 0x00, + /* 0008 */ 0x00, 0x01, 0x00, 0x00 + }) + Name(END, Buffer() {0x79, 0x00}) + + Concatenate (SPB, NAM, Local0) + Concatenate (Local0, END, Local1) + Return (Local1) + } + } +} + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Pram/Pram.aslc b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Pram/Pram.aslc new file mode 100644 index 0000000000..2d1425a636 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Pram/Pram.aslc @@ -0,0 +1,61 @@ +/** @file + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// +// Statements that include other files +// +#include + +// +// MCFG Table definition +// +EFI_ACPI_PRAM_BASE_ADDRESS_TABLE PRAM = { + EFI_ACPI_PRAM_BASE_ADDRESS_TABLE_SIGNATURE, + sizeof (EFI_ACPI_PRAM_BASE_ADDRESS_TABLE), + EFI_ACPI_PRAM_BASE_ADDRESS_TABLE_REVISION, + // + // Checksum will be updated at runtime + // + 0x00, + // + // It is expected that these values will be programmed at runtime + // + ' ', + ' ', + ' ', + ' ', + ' ', + ' ', + + 0, + EFI_ACPI_OEM_PRAM_REVISION, + 0, + 0, + // + // Beginning of PRAM specific fields + // + 0, //address + 0, //size +}; + +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from + // removing the data structure from the executable + // + return (VOID*)&PRAM; +} diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Sc.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Sc.asl new file mode 100644 index 0000000000..fed50b37bc --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Sc.asl @@ -0,0 +1,292 @@ +/** @file + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Include ("GpioLib.asl") +Scope(\) +{ + // + // Define ABASE I/O as an ACPI operating region. The base address + // can be found in Device 31, Registers 40-43h. + // + OperationRegion(PMIO, SystemIo, \PMBS, 0x46) + Field(PMIO, ByteAcc, NoLock, Preserve) { + , 8, + PWBS, 1, // Power Button Status + Offset(0x20), + , 13, + PMEB, 1, // PME_B0_STS + Offset(0x42), // General Purpose Control + , 1, + GPEC, 1 + } + Field(PMIO, ByteAcc, NoLock, WriteAsZeros) { + Offset(0x20), // GPE0 Status + , 4, + PSCI, 1, // PUNIT SCI Status + SCIS, 1 // GUNIT SCI Status + } + + // + // Define a Memory Region that will allow access to the PMC + // Register Block. Note that in the Intel Reference Solution, the PMC + // will get fixed up dynamically during POST. + // + OperationRegion(PMCR, SystemMemory, Add(DD1A,0x1000), 0x80) // PMC Space + Field(PMCR,DWordAcc,Lock,Preserve) { + Offset(0x34), // Function Disable Register + , 22, + RP2D, 1, // (22) Root Port 2 Disable + RP1D, 1, // (23) Root Port 1 Disable + Offset(0x38), // Function Disable Register 1 + , 3, + RP3D, 1, // (03) Root Port 3 Disable + RP4D, 1, // (04) Root Port 4 Disable + RP5D, 1, // (05) Root Port 5 Disable + RP6D, 1, // (06) Root Port 6 Disable + } + + // + // Support S0, S3, S4, and S5. The proper bits to be set when + // entering a given sleep state are found in the Power Management + // 1 Control ( PM1_CNT ) register, located at ACPIBASE + 04h, + // bits 10d - 12d. + // + +} //end Scope(\) + +scope (\_SB.PCI0) { + Name(LTRN, 0) + Name(OBFN, 0) + + Name(LMSL, 0) + Name(LNSL, 0) + + // + // LPC Bridge - Device 31, Function 0, this is only for PCH register Memory Region declare, + // it's better to be declared as early as possible since it's widely used in whole ACPI name space. + // Please add any code which needs to reference any register of it after this + // + Device(LPCB) { + Name(_ADR, 0x001F0000) + + OperationRegion(LPC, PCI_Config, 0x00, 0x100) + Field(LPC, AnyAcc, NoLock, Preserve) + { + Offset(0x02), + CDID, 16, + Offset(0x08), + CRID, 8, + Offset(0x80), + IOD0, 8, + IOD1, 8, + Offset(0xA0), + , 9, + PRBL, 1, + Offset(0xAC), + , 8, + , 8, + XUSB, 1, + Offset(0xB8), + , 22, + GR0B, 2, + , 8, + Offset(0xBC), + , 2, + GR19, 2, + , 28, + } + } + + // + // PCIE Root Port #01 + // + Device(RP01) { + Method (_ADR, 0) { + If (LNotEqual(RPA1,0)) { + Return (RPA1) + } Else { + Return (0x00140000) + } + } + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR1, LTRN) + Store (PML1, LMSL) + Store (PNL1, LNSL) + Store (OBF1, OBFN) + } + Include("ScPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + Method(_PRT, 0) { + If (PICM) { Return(AR04) }// APIC mode + Return (PR04) // PIC Mode + } // end _PRT + } // end "PCIE Root Port #01" + + // + // PCIE Root Port #02 + // + Device(RP02) { + Method (_ADR, 0) { + If (LNotEqual(RPA2,0)) { + Return (RPA2) + } Else { + Return (0x00140001) + } + } + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR2, LTRN) + Store (PML2, LMSL) + Store (PNL2, LNSL) + Store (OBF2, OBFN) + } + Include("ScPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x08, 4)) } //GPE enable bit for RP2 is 8, can wake up from S4 state + Method(_PRT, 0) { + If (PICM) { Return(AR05) }// APIC mode + Return (PR05) // PIC Mode + } // end _PRT + } // end "PCIE Root Port #02" + + // + // PCIE Root Port #03 + // + Device(RP03) { + Method (_ADR, 0) { + If (LNotEqual(RPA3,0)) { + Return (RPA3) + } Else { + Return (0x00130000) + } + } + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR3, LTRN) + Store (PML3, LMSL) + Store (PNL3, LNSL) + Store (OBF3, OBFN) + } + Include("ScPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + Method(_PRT, 0) { + If (PICM) { Return(AR04) }// APIC mode + Return (PR04) // PIC Mode + } // end _PRT + } // end "PCIE Root Port #03" + + // + // PCIE Root Port #04 + // + Device(RP04) { + Method (_ADR, 0) { + If (LNotEqual(RPA4,0)) { + Return (RPA4) + } Else { + Return (0x00130001) + } + } + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR4, LTRN) + Store (PML4, LMSL) + Store (PNL4, LNSL) + Store (OBF4, OBFN) + } + Include("ScPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + Method(_PRT, 0) { + If(PICM) { Return(AR05) }// APIC mode + Return (PR05) // PIC Mode + } // end _PRT + } // end "PCIE Root Port #04" + + // + // PCIE Root Port #05 + // + Device(RP05) { + Method (_ADR, 0) { + If (LNotEqual(RPA5,0)) { + Return (RPA5) + } Else { + Return (0x00130002) + } + } + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR5, LTRN) + Store (PML5, LMSL) + Store (PNL5, LNSL) + Store (OBF5, OBFN) + } + Include("ScPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + Method(_PRT, 0) { + If (PICM) { Return(AR06) }// APIC mode + Return (PR06) // PIC Mode + } // end _PRT + } // end "PCIE Root Port #05" + + // + // PCIE Root Port #06 + // + Device(RP06) { + Method (_ADR, 0) { + If (LNotEqual(RPA6,0)) { + Return (RPA6) + } Else { + Return (0x00130003) + } + } + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR6, LTRN) + Store (PML6, LMSL) + Store (PNL6, LNSL) + Store (OBF6, OBFN) + } + Include("ScPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + Method(_PRT, 0) { + If (PICM) { Return(AR07) }// APIC mode + Return (PR07) // PIC Mode + } // end _PRT + } // end "PCIE Root Port #06" + + include ("ScSata.asl") + // xHCI Controller - Device 20, Function 0 + include ("ScXhci.asl") + include ("ScXdci.asl") + include ("ScScc.asl") + include ("ScLpss.asl") + include ("ScAudio.asl") +} + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScAudio.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScAudio.asl new file mode 100644 index 0000000000..80da490ce5 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScAudio.asl @@ -0,0 +1,248 @@ +/** @file + Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + // + // High Definition Audio - Device 14, Function 0 + // + Device(HDAS) { + Name(_ADR, 0x000E0000) + + OperationRegion(HDAR, PCI_Config, 0x00,0x100) + Field(HDAR,ByteAcc,NoLock,Preserve) { + VDID, 32, // 0x00, VID DID + Offset(0x48), // 0x48, CGCTL - Clock Gating Control + , 6, + MBCG, 1, // MISCBDCGE [BIT6] + Offset(0x54), // 0x54, Power Management Control and Status Register + , 8, + PMEE, 1, // PME_EN + , 6, + PMES, 1 // PME Status + } + + // NHLT Table memory descriptor, returned from _DSM + Name(NBUF, ResourceTemplate () { + // NHLT table address (_MIN = NHLT 64bit pointer, _MAX = _MIN + _LEN - 1) and length (_LEN) + // Move to 64 bit mode from 32 bit + QWordMemory (ResourceConsumer, , MinNotFixed, MaxNotFixed, NonCacheable, ReadOnly, + 0x1, // AddressGranularity + 0x0000000000000000, // AddressMinimum _MIN + 0x0000000000000000, // AddressMaximum _MAX + 0x0, + 0x0, // RangeLength _LEN + , , NHLT, AddressRangeACPI,) + }) + + Name(_S0W, 3) // Device can wake itself from D3 in S0 + + Method(_DSW, 3) { Store(Arg0, PMEE) } // Device wake enable + + Name (_PRW, Package() {0x0E, 3}) // can wakeup from S3 state + + Method(_PS0,0,Serialized) /// D0 Method for HD-A Controller + { + + } + Method(_PS3,0,Serialized) /// D3 Method for HD-A Controller(Dummy routine to support D3 state) + { + + } + + Method(_INI, 0, NotSerialized) // _INI: Initialize + { + // Update resource according to NVS + + + // Set NHLT base address and length + CreateQWordField(NBUF, ^NHLT._MIN, NBAS) + CreateQWordField(NBUF, ^NHLT._MAX, NMAS) + CreateQWordField(NBUF, ^NHLT._LEN, NLEN) + Store(NHLA, NBAS) + Add(NHLA, Subtract(NHLL, 1), NMAS) + Store(NHLL, NLEN) + } + + Method(_DSM, 0x4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) { + // Arg0 - UUID: A69F886E-6CEB-4594-A41F-7B5DCE24C553 (Buffer) + // Arg1 - Revision ID: 0x01 (Integer) + // Arg2 - Function Index: 0x0 - 0x3 (Integer) - See below for details. + // Arg3 - Depends on Function Index - See below for details. + // Return - Depends on Function Index - See below for details. + + + // Verify UUID + If (LEqual(Arg0, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553"))){ + + Switch(ToInteger(Arg2)) { + + // Function 0: Function Support Query + // Arg2 - Function Index: 0x00 (Integer) + // Arg3: Unused + // Return: Bitmask of functions supported. (Buffer) + Case(0) { + // Supports function 0 - 3 + Return(Buffer(One) { 0x0F }) + } + + // Function 1: Query Non HD Audio Descriptor Table + // Used by the Intel Offload Engine Driver to discover the + // non HD Audio devices supported by the Audio DSP. + // Arg2 - Function Index: 0x01 (Integer) + // Arg3 - Unused + // Return - ACPI Table describing the non HD Audio links and devices supported by the ADSP (ResourceBuffer) + Case(1) { + + // NBUF - Memory Resource Descriptor buffer with address and length of NHLT + Return(NBUF) + } + + // Function 2: Query Feature Mask + // Used by the Intel Offload Engine Driver to retrieve a bitmask + // of features allowable on this platform. + // Arg2 - Function Index: 0x02 (Integer) + // Arg3: Unused + // Return: Bitmask of supported features. + Case (2) { + + // + // Bit 0 == '1', WoV is supported, Bit 0 == '0', WoV not supported + // Bit 1 == '1', BT Sideband is supported, Bit 1 == '0', BT not supported + // Bit 2 == '1', codec based VAD support allowable + // Bit 3 == '1', SramReclaim Feature enabled + // Bit 4 Reserved + // Bit 5 == '1', BT Intel HFP SCO is supported + // Bit 6 == '1', BT Intel A2DP is supported + // Bit 7 == '1', DSP based speech pre-processing disabled + // Bit 8 == '1', Windows Voice Activation, Bit 8 == '0', Intel Wake on Voice + // Bit 9 == '1' Context Aware Feature enabled + // Bit 10 - 31 Reserved, shall be set to '0' + // ADFM - NVS AudioDSP Feature Bit Mask updated from PchPolicy + // + Return(ADFM) + } + // Function 3: Query Pre/Post Processing Module Support + // Used by the Intel Offload Engine Driver to determine if a + // specified PP Module is allowed to be supported on this platform + // Arg2 - Function Index: 0x03 (Integer) + // Arg3 - UUID: Specifies the UUID of the PP module to check (Buffer) + // Return - TRUE if PP Module supported, else FALSE. + Case (3) { + + // ADPM - NVS AudioDSP Post-Processing Module Bit Mask updated from PchPolicy: HdaConfig->DspPpModuleMask + + // + // Example (to be updated with real GUIDs of supported 3rd party IP): + // + // 3rd Party DSP Processing Module 1 placeholder (enabled by policy HdaConfig->DspPpModuleMask |= BIT0) + // Check PP module with GUID AABBCCDD-EEFF-1122-3344-556677889900 + // If (LEqual(Arg3, ToUUID ("AABBCCDD-EEFF-1122-3344-556677889900"))){ + // Return(And(ADPM, 0x1)) // DspPpModuleMask[BIT0] / ADPM[BIT0] set - supported 3rd Party Processing Module 1(return true) + // } + // + // 3rd Party DSP Processing Module 5 placeholder (enabled by policy HdaConfig->DspPpModuleMask |= BIT5) + // Check PP module with GUID 11111111-2222-3333-4444-AABBCCDDEEFF + // If (LEqual(Arg3, ToUUID ("11111111-2222-3333-4444-AABBCCDDEEFF"))){ + // Return(And(ADPM, 0x20)) // DspPpModuleMask[BIT5] / ADPM[BIT5] set - supported 3rd Party Processing Module 5(return true) + // } + // + // Implement for all supported PP modules + // + + // PP Module Waves (module XAMAXXAU) + // Check PP module with GUID B489C2DE-0F96-42E1-8A2D-C25B5091EE49 + If (LEqual(Arg3, ToUUID ("B489C2DE-0F96-42E1-8A2D-C25B5091EE49"))) { + Return(And(ADPM, BIT0)) // ADPM[BIT0] set - supported (return true) + } + + // PP Module DTS (module PRMSND) + // Check PP module with GUID E1284052-8664-4FE4-A353-3878F72704C3 + If (LEqual(Arg3, ToUUID ("E1284052-8664-4FE4-A353-3878F72704C3"))) { + Return(And(ADPM, BIT1)) // ADPM[BIT1] set - supported (return true) + } + + // PP Module IntelSst Speech + // Check PP module with GUID 7C708106-3AFF-40FE-88BE-8C999B3F7445 + If (LEqual(Arg3, ToUUID ("7C708106-3AFF-40FE-88BE-8C999B3F7445"))) { + Return(And(ADPM, BIT2)) // ADPM[BIT2] set - supported (return true) + } + + // PP Module Dolby + // Check PP module with GUID E0E018A8-3550-4B54-A8D0-A8E05D0FCBA2 + If (LEqual(Arg3, ToUUID ("E0E018A8-3550-4B54-A8D0-A8E05D0FCBA2"))) { + Return(And(ADPM, BIT3)) // ADPM[BIT3] set - supported (return true) + } + + // PP Module Samsung SoundAlive + // Check PP module with GUID 202BADB5-8870-4290-B536-F2380C63F55D + If (LEqual(Arg3, ToUUID ("202BADB5-8870-4290-B536-F2380C63F55D"))) { + Return(And(ADPM, BIT4)) // ADPM[BIT4] set - supported (return true) + } + + // PP Module Samsung SoundBooster + // Check PP module with GUID EB3FEA76-394B-495D-A14D-8425092D5CB7 + If (LEqual(Arg3, ToUUID ("EB3FEA76-394B-495D-A14D-8425092D5CB7"))) { + Return(And(ADPM, BIT5)) // ADPM[BIT5] set - supported (return true) + } + + // PP Module Samsung EQ/DRC + // Check PP module with GUID F1C69181-329A-45F0-8EEF-D8BDDF81E036 + If (LEqual(Arg3, ToUUID ("F1C69181-329A-45F0-8EEF-D8BDDF81E036"))) { + Return(And(ADPM, BIT6)) // ADPM[BIT6] set - supported (return true) + } + + // PP Module ForteMedia SAMSoft + // Check PP module with GUID B3573EFF-6441-4A75-91F7-4281EEC4597D + If (LEqual(Arg3, ToUUID ("B3573EFF-6441-4A75-91F7-4281EEC4597D"))) { + Return(And(ADPM, BIT7)) // ADPM[BIT7] set - supported (return true) + } + + // PP Module WoV Intel + // Check PP module with GUID EC774FA9-28D3-424A-90E4-69F984F1EEB7 + If (LEqual(Arg3, ToUUID ("EC774FA9-28D3-424A-90E4-69F984F1EEB7"))) { + Return(And(ADPM, BIT8)) // ADPM[BIT8] set - supported (return true) + } + + // PP Module WoV Sensory + // Check PP module with GUID F101FEF0-FF5A-4AD4-8710-43592A6F7948 + If (LEqual(Arg3, ToUUID ("F101FEF0-FF5A-4AD4-8710-43592A6F7948"))) { + Return(And(ADPM, BIT9)) // ADPM[BIT9] set - supported (return true) + } + + // PP Module Conexant + // Check PP module with GUID F3578986-4400-4ADF-AE7E-CD433CD3F26E + If (LEqual(Arg3, ToUUID ("F3578986-4400-4ADF-AE7E-CD433CD3F26E"))) { + Return(And(ADPM, BIT10)) // ADPM[BIT10] set - supported (return true) + } + + // PP Module Aware + // Check PP module with GUID 13B5E4D7-A91A-4059-8290-605B01CCB650 + If (LEqual(Arg3, ToUUID ("13B5E4D7-A91A-4059-8290-605B01CCB650"))) { + Return(And(ADPM, BIT11)) // ADPM[BIT11] set - supported (return true) + } + + Return(0) // Is not supported + } // Case 3 end + + Default { + // Function not supported (Arg2) + + Return(Buffer(One) { 0x00 }) + } + } // Switch(Arg2) End + } // If(Arg0, UUID) End + // UUID not supported (Arg0) + + Return(Buffer(One) { 0x00 }) //Will never hit this but compiler is not happy without it + } // _DSM End +} // end "High Definition Audio Controller" + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScLpss.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScLpss.asl new file mode 100644 index 0000000000..9ad39c8296 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScLpss.asl @@ -0,0 +1,579 @@ +/** @file + ACPI DSDT table + + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +scope (\_SB.PCI0) { + // + // LPIO1 PWM + // + Device(PWM) { + Name (_ADR, 0x001A0000) + Name (_DDN, "Intel(R) PWM Controller") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate () + { + }) + Method (_CRS, 0x0, NotSerialized) + { + Return (RBUF) + } + } + + // + // LPIO1 HS-UART #1 + // + Device(URT1) { + Name (_ADR, 0x00180000) + Name (_DDN, "Intel(R) HS-UART Controller #1") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate () + { + }) + Method (_CRS, 0x0, NotSerialized) + { + Return (RBUF) + } + + Device (VUT0) { + Name (_HID, "INT3511") + Method (_STA, 0x0, NotSerialized) + { + If(LEqual(OSYS,2015)) { + Return(0xf) + } + else { + Return(0) + } + } + Method(_CRS, 0x0, NotSerialized){ + Name(SBUF, ResourceTemplate (){ + UARTSerialBus(115200,,,0xfc,,,,32,32,"\\_SB.PCI0.URT1" ) + }) + Return (SBUF) + } + } //Device (VUT0) + + } // Device (URT1) + + // + // LPIO1 HS-UART #2 + // + Device(URT2) { + Name (_ADR, 0x00180001) + Name (_DDN, "Intel(R) HS-UART Controller #2") + Name (_UID, 2) + + Name (RBUF, ResourceTemplate () + { + }) + Method (_CRS, 0x0, NotSerialized) + { + Return (RBUF) + } + + OperationRegion (KEYS, SystemMemory, U21A, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32 + } + + Device (VUT1) { + Name (_HID, "INT3512") + Method (_STA, 0x0, NotSerialized) + { + If(LEqual(OSYS,2015)) { + Return(0xf) + } + else { + Return(0) + } + } + Method(_CRS, 0x0, NotSerialized){ + Name(SBUF, ResourceTemplate (){ + UARTSerialBus(115200,,,0xfc,,,,32,32,"\\_SB.PCI0.URT2" ) + }) + Return (SBUF) + } + } // Device(VUT1) + } // Device (URT2) + + // + // LPIO1 HS-UART #3 + // + Device(URT3) { + Name (_ADR, 0x00180002) + Name (_DDN, "Intel(R) HS-UART Controller #3") + Name (_UID, 3) + + Name (RBUF, ResourceTemplate () + { + }) + Method (_CRS, 0x0, NotSerialized) + { + Return (RBUF) + } + } // Device (URT3) + + // + // LPIO1 HS-UART #4 + // + Device(URT4) { + Name (_ADR, 0x00180003) + Name (_DDN, "Intel(R) HS-UART Controller #4") + Name (_UID, 4) + + Name (RBUF, ResourceTemplate () + { + }) + Method (_CRS, 0x0, NotSerialized) + { + Return (RBUF) + } + } // Device (URT4) + + // + // LPIO1 SPI + // + Device(SPI1) { + Name (_ADR, 0x00190000) + Name (_DDN, "Intel(R) SPI Controller #1") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate () + { + }) + Method (_CRS, 0x0, NotSerialized) + { + Return (RBUF) + } + } // Device (SPI1) + + // + // LPIO1 SPI #2 + // + Device(SPI2) { + Name (_ADR, 0x00190001) + Name (_DDN, "Intel(R) SPI Controller #2") + Name (_UID, 2) + + Name (RBUF, ResourceTemplate () + { + }) + Method (_CRS, 0x0, NotSerialized) + { + Return (RBUF) + } + } // Device (SPI2) + + // + // LPIO1 SPI #3 + // + Device(SPI3) { + Name (_ADR, 0x00190002) + Name (_DDN, "Intel(R) SPI Controller #3") + Name (_UID, 3) + + Name (RBUF, ResourceTemplate () + { + //FixedDMA(0x8, 0x8, Width32Bit, ) + //FixedDMA(0x9, 0x9, Width32Bit, ) + }) + Method (_CRS, 0x0, NotSerialized) + { + Return (RBUF) + } + } // Device (SPI3) + + + // + // LPIO2 I2C #0 + // Connect to AUDIO CODEC, MCSI CAM + // + Device(I2C0) { + Name (_ADR, 0x00160000) + Name (_DDN, "Intel(R) I2C Controller #0") + Name (_UID, 1) + Name (LINK,"\\_SB.PCI0.I2C0") // Support for Windows 7 + + Name (RBUF, ResourceTemplate () + { + //FixedDMA(0x10, 0x0, Width32Bit, ) + //FixedDMA(0x11, 0x1, Width32Bit, ) + }) + + Method (FREQ, 0x0, Serialized) + { + Return(IC0S) + } + Method (FMCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 100, 214, 28 }) + Return (PKG) + } + Method (FPCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 38, 80, 12 }) + Return (PKG) + } + Method (HSCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 5, 24, 12 }) + Return (PKG) + } + Method (SSCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 580,730, 28}) + Return (PKG) + } + + Method (_CRS, 0x0, NotSerialized) + { + Return (RBUF) + } + } // Device(I2C0) + + // + // LPIO2 I2C #1 + // Connect to NFC + // + Device(I2C1) { + Name (_ADR, 0x00160001) + Name (_DDN, "Intel(R) I2C Controller #1") + Name (_UID, 2) + Name (LINK,"\\_SB.PCI0.I2C1") // Support for Windows 7 + + Name (RBUF, ResourceTemplate () + { + }) + + Method (FREQ, 0x0, Serialized) + { + Return(IC1S) + } + Method (FMCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 100, 214, 28 }) + Return (PKG) + } + + Method (FPCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 38, 80, 12 }) + Return (PKG) + } + Method (HSCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 5, 24, 12 }) + Return (PKG) + } + Method (SSCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 580,730, 28}) + Return (PKG) + } + + Method (_CRS, 0x0, NotSerialized) + { + Return (RBUF) + } + } // Device (I2C1) + + // + // LPIO2 I2C #2 + // Connect to MCSI CAMERA + // + Device(I2C2) { + Name (_ADR, 0x00160002) + Name (_DDN, "Intel(R) I2C Controller #2") + Name (_UID, 3) + Name (LINK,"\\_SB.PCI0.I2C2") // Support for Windows 7 + + Name (RBUF, ResourceTemplate () + { + //FixedDMA(0x14, 0x4, Width32Bit, ) + //FixedDMA(0x15, 0x5, Width32Bit, ) + }) + + Method (FREQ, 0x0, Serialized) + { + Return(IC2S) + } + Method (FMCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 100, 214, 28 }) + Return (PKG) + } + Method (FPCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 38, 80, 12 }) + Return (PKG) + } + Method (HSCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 5, 24, 12 }) + Return (PKG) + } + Method (SSCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 580,730, 28}) + Return (PKG) + } + + Method (_CRS, 0x0, NotSerialized) + { + Return (RBUF) + } + } // Device(I2C2) + + // + // LPIO2 I2C #3 + // Connect to TOUCH PANEL + // + Device(I2C3) { + Name (_ADR, 0x00160003) + Name (_DDN, "Intel(R) I2C Controller #3") + Name (_UID, 4) + Name (LINK,"\\_SB.PCI0.I2C3") // Support for Windows 7 + + Name (RBUF, ResourceTemplate () + { + //FixedDMA(0x16, 0x6, Width32Bit, ) + //FixedDMA(0x17, 0x7, Width32Bit, ) + }) + + Method (FREQ, 0x0, Serialized) + { + Return(IC3S) + } + Method (FMCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 100, 214, 28 }) + Return (PKG) + } + Method (FPCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 38, 80, 12 }) + Return (PKG) + } + Method (HSCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 5, 24, 12 }) + Return (PKG) + } + Method (SSCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 580,730, 28}) + Return (PKG) + } + + Method (_CRS, 0x0, NotSerialized) + { + Return (RBUF) + } + } // Device(I2C3) + + // + // LPIO2 I2C #4 + // Connect to TOUCH PAD + // + Device(I2C4) { + Name (_ADR, 0x00170000) + Name (_DDN, "Intel(R) I2C Controller #4") + Name (_UID, 1) + Name (LINK,"\\_SB.PCI0.I2C4") // Support for Windows 7 + + Name (RBUF, ResourceTemplate () + { + //FixedDMA(0x18, 0x0, Width32Bit, ) + //FixedDMA(0x19, 0x1, Width32Bit, ) + }) + + Method (FREQ, 0x0, Serialized) + { + Return(IC4S) + } + Method (FMCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 100, 214, 28 }) + Return (PKG) + } + Method (FPCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 38, 80, 12 }) + Return (PKG) + } + Method (HSCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 5, 24, 12 }) + Return (PKG) + } + Method (SSCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 580,730, 28}) + Return (PKG) + } + + Method (_CRS, 0x0, NotSerialized) + { + Return (RBUF) + } + } // Device(I2C4) + + + // + // LPIO2 I2C #5 + // Connect to SENSOR AIC + // + Device(I2C5) { + Name (_ADR, 0x00170001) + Name (_DDN, "Intel(R) I2C Controller #5") + Name (_UID, 2) + Name (LINK,"\\_SB.PCI0.I2C5") // Support for Windows 7 + + Name (RBUF, ResourceTemplate () + { + //FixedDMA(0x1A, 0x02, Width32Bit, ) + //FixedDMA(0x1B, 0x03, Width32Bit, ) + }) + + Method (FREQ, 0x0, Serialized) + { + Return(IC5S) + } + Method (FMCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 100, 214, 28 }) + Return (PKG) + } + Method (FPCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 38, 80, 12 }) + Return (PKG) + } + Method (HSCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 5, 24, 12 }) + Return (PKG) + } + Method (SSCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 580,730, 28}) + Return (PKG) + } + + Method (_CRS, 0x0, NotSerialized) + { + Return (RBUF) + } + } // Device(I2C5) + + + // + // LPIO2 I2C #6 + // Connect to SENSOR AIC + // + Device(I2C6) { + Name (_ADR, 0x00170002) + Name (_DDN, "Intel(R) I2C Controller #6") + Name (_UID, 3) + Name (LINK,"\\_SB.PCI0.I2C6") // Support for Windows 7 + + Name (RBUF, ResourceTemplate () + { + //FixedDMA(0x1C, 0x4, Width32Bit, ) + //FixedDMA(0x1D, 0x5, Width32Bit, ) + }) + + Method (FREQ, 0x0, Serialized) + { + Return(IC6S) + } + Method (FMCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 100, 214, 28 }) + Return (PKG) + } + Method (FPCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 38, 80, 12 }) + Return (PKG) + } + Method (HSCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 5, 24, 12 }) + Return (PKG) + } + Method (SSCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 580,730, 28}) + Return (PKG) + } + + Method (_CRS, 0x0, NotSerialized) + { + Return (RBUF) + } + } // Device(I2C6) + + // + // LPIO2 I2C #7 + // Connect to PSS RFID / INA DEVICESx16 + // + Device(I2C7) { + Name (_ADR, 0x00170003) + Name (_DDN, "Intel(R) I2C Controller #7") + Name (_UID, 4) + Name (LINK,"\\_SB.PCI0.I2C7") // Support for Windows 7 + + Name (RBUF, ResourceTemplate () + { + //FixedDMA(0x1C, 0x4, Width32Bit, ) + //FixedDMA(0x1D, 0x5, Width32Bit, ) + }) + + Method (FREQ, 0x0, Serialized) + { + Return(IC7S) + } + Method (FMCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 100, 214, 28 }) + Return (PKG) + } + Method (FPCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 38, 80, 12 }) + Return (PKG) + } + Method (HSCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 5, 24, 12 }) + Return (PKG) + } + Method (SSCN, 0x0, Serialized) + { + Name (PKG, Package(3) { 580,730, 28}) + Return (PKG) + } + + Method (_CRS, 0x0, NotSerialized) + { + Return (RBUF) + } + } // Device(I2C7) +}// PCI0 + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScPcie.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScPcie.asl new file mode 100644 index 0000000000..7d281ecc20 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScPcie.asl @@ -0,0 +1,88 @@ +/** @file + Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + OperationRegion(PXCS,PCI_Config,0x00,0x380) + Field(PXCS,AnyAcc, NoLock, Preserve) + { + Offset(0), + VDID, 32, + Offset(0x5A), // SLSTS[7:0] - Slot Status Register + ABPX, 1, // 0, Attention Button Pressed + , 2, + PDCX, 1, // 3, Presence Detect Changed + , 2, + PDSX, 1, // 6, Presence Detect State + , 1, + Offset(0x60), // RSTS - Root Status Register + , 16, + PSPX, 1, // 16, PME Status + Offset(0xA4), + D3HT, 2, // Power State + Offset(0xD8), // MPC - Miscellaneous Port Configuration Register + , 30, + HPEX, 1, // 30, Hot Plug SCI Enable + PMEX, 1, // 31, Power Management SCI Enable + } + + Field(PXCS,AnyAcc, NoLock, WriteAsZeros) + { + Offset(0xDC), // SMSCS - SMI/SCI Status Register + , 30, + HPSX, 1, // 30, Hot Plug SCI Status + PMSX, 1 // 31, Power Management SCI Status + } + + Device(PXSX) + { + Name(_ADR, 0x00000000) + + // NOTE: Any PCIE Hot-Plug dependency for this port is + // specific to the CRB. Please modify the code based on + // your platform requirements. + + Name(_PRW, Package(){8,4}) //Wake bit for WiFi is 8 + } + + // + // PCI_EXP_STS Handler for PCIE Root Port + // + Method(HPME,0,Serialized) + { + If (PMSX) { + // + // Clear the PME SCI status bit with timeout + // + Store(200,Local0) + While(Local0) { + // + // Clear PME SCI Status + // + Store(1, PMSX) + // + // If PME SCI Status is still set, keep clearing it. + // Otherwise, break the while loop. + // + If (PMSX) { + Decrement(Local0) + } else { + Store(0,Local0) + } + } + + // + // Notify PCIE Endpoint Devices + // + Notify(PXSX, 0x02) + } + } + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScSata.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScSata.asl new file mode 100644 index 0000000000..a19be44eb1 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScSata.asl @@ -0,0 +1,66 @@ +/** @file + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(\_SB.PCI0) +{ + // + // Serial ATA Host Controller - Device 18, Function 0 + // + Device(SATA) { + Name(_ADR,0x00120000) + + Device(PRT0) + { + Name(_ADR,0x0000FFFF) // Port 0 + } + Device(PRT1) + { + Name(_ADR,0x0001FFFF) // Port 1 + } + // + // SATA Methods pulled in via SSDT. + // + OperationRegion(SATR, PCI_Config, 0x74,0x4) + Field(SATR,WordAcc,NoLock,Preserve) { + Offset(0x00), // 0x74, PMCR + , 8, + PMEE, 1, //PME_EN + , 6, + PMES, 1 //PME_STS + } + + Method (_STA, 0x0, NotSerialized) + { + //Enable SATA controller PME_EN bit + Store (1, \_SB.PCI0.SATA.PMEE) + Return(0xf) + } + + Method(_DSW, 3) + { + If (Arg1) { // Entering Sx, need to disable WAKE# from generating runtime PME + Store(0, \_SB.PCI0.SATA.PMEE) + } Else { // Staying in S0 + If (LAnd(Arg0, Arg2)) { + // Exiting D0 and arming for wake + // Set PME + Store(1, \_SB.PCI0.SATA.PMEE) + } Else { // Disable runtime PME, either because staying in D0 or disabling wake + Store(0, \_SB.PCI0.SATA.PMEE) + } + } + } // End _DSW + } +} + + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScScc.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScScc.asl new file mode 100644 index 0000000000..9432a25626 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScScc.asl @@ -0,0 +1,719 @@ +/** @file + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +External(EEPI, IntObj) + +scope (\_SB.PCI0) { + + // + // Access P2SB CFG Space + // + // P2SB PCI MMCFG Space: 0xE0000000 + // P2SB Device: 0xD, Function: 0x0 + // P2SB MM CFG Interface Access Registers: 0xD0 - 0xDC + // + OperationRegion(P2CG, SystemMemory, OR( OR (0xE0000000, ShiftLeft(0xD, 15)), 0xD0), 0x20) // P2SB PCI CFG SB Interface Registers + Field(P2CG, DWordAcc, NoLock, Preserve) + { + Offset (0x00), // SBI Addr (0xD0) + SBAD, 32, + Offset (0x04), // SBI Data (0xD4) + SBDA, 32, + Offset (0x08), // SBI Stat (0xD8) + IRDY, 1, + , 6, + POST, 1, + OPCD, 8, + Offset (0x0A), // SBI RID (0xDA) + SBID, 16, + Offset (0x0C), // SBI Ext Addr (0xDC) + SBEA, 32, + Offset (0x10), // P2SBC - P2SB Control (0xE0) + , 8, + P2HD, 8 // P2SB HIDE bit [8:8] (use the byte which is reserved) + } + + // + // SBI Method: + // SBI message execution + // + // Arguments: (4) + // Arg0: Addr + // Arg1: WriteData + // Arg2: OpCode + // Arg3: RID + // + // Return Value: + // ReadData + // + Method (SBIM, 4, Serialized) + { + Store (0x0, Local0) + // + // Acquire the ACPI Global Lock to Ensure Exclusive Access to the P2SB Interface + // + Store(Acquire (\_GL, 0x1F40), Local1) + If (LEqual(Local1, 0)) { + // Unhide P2SB CFG Space + Store (0, P2HD) + + // Wait Until InitRdy == 0 (Transaction Complete) + While (IRDY) + { + Sleep (1) + } + + // SBIADDR + And (SBAD, 0x00F00000, SBAD) + Or (SBAD, Arg0, SBAD) + + // SBIEXTADDR + Store (0, SBEA) + + // SBIDATA + Store (Arg1, SBDA) + + // SBIRID + And (SBID, 0x0800, SBID) + Or (SBID, Arg3, SBID) + + // SBISTAT + Store (0, POST) // set non-posted access + Store (Arg2, OPCD) + Store (1, IRDY) + + // Wait Until InitRdy == 0 (Transaction Complete) + While (IRDY) + { + Sleep (1) + } + Store (SBDA, local0) + + // Hide P2SB CFG Space + Store (1, P2HD) + } + Release (\_GL) + Return (local0) + } + + OperationRegion (SBMM, SystemMemory, OR( OR (P2BA, ShiftLeft(0xD6, 16)), 0x0600), 0x18) + Field (SBMM, DWordAcc, NoLock, Preserve) + { + Offset (0x00), + GENR, 32, + Offset (0x08), + , 5, + GRR3, 1, + } + + // + // SCC power gate control method, this method must be serialized as multiple device will control the GENR register + // + // Arguments: (2) + // Arg0: 0-AND 1-OR + // Arg1: Value + Method (SCPG, 2, Serialized) + { + Name (TMP, 0x0) + if (LEqual(Arg0, 0x1)) { + Store (\_SB.PCI0.GENR, TMP) + Or (TMP, Arg1, \_SB.PCI0.GENR) + + } ElseIf(LEqual(Arg0, 0x0)) { + Store (\_SB.PCI0.GENR, TMP) + And (TMP, Arg1, \_SB.PCI0.GENR) + } + } + + // + // eMMC + // + Device(SDHA) { + Name (_ADR, 0x001C0000) + Name (_DDN, "Intel(R) eMMC Controller - 80865ACC") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate () + { + }) + + OperationRegion (PMCS, PCI_Config, 0x84, 0x4) + Field (PMCS, WordAcc, NoLock, Preserve) { + PMSR, 32, // 0x84, PMCSR - Power Management Control and Status + } + + OperationRegion (SCPC, PCI_Config, 0xA0, 4) + Field (SCPC, WordAcc, NoLock, Preserve) + { + Offset (0x00), // 0xA0 D0i3 Max Power Latency Powergating Config + , 17, + I3EN, 1, + DPGE, 1 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (RBUF) + } + + Method (_PS0, 0, NotSerialized) // _PS0: Power State 0 + { + // + // Disable power gate + // + Store (0, \_SB.PCI0.SDHA.DPGE) + Store (0, \_SB.PCI0.SDHA.I3EN) + // + // Clear clock gate + // + \_SB.PCI0.SCPG(0,0xFFFFFFBE) // Clear bit 6 and 0 + Sleep (2) // Sleep 2 ms + + } + + Method (_PS3, 0, NotSerialized) // _PS3: Power State 3 + { + Store (SBIM (0xD600003C, 0, 0x0, 0x30E0), local0) + Store (SBIM (0xD6000834, 0, 0x0, 0x30E0), local1) + Store (SBIM (0xD6000840, 0, 0x0, 0x30E0), local2) + + If (And (Local0, 0x00800000)) { + Add (Multiply (And (local2, 0x1F), 2), ShiftRight(And (Local1, 0x3F00), 8), local3) + Or (And (local1, 0xFFFFFF80), And (local3, 0x7F), local1) + SBIM (0xD6000834, local1, 0x1, 0x30E0) + } + // + // Enable power gate + // + Store (1, \_SB.PCI0.SDHA.DPGE) + Store (1, \_SB.PCI0.SDHA.I3EN) + // + // Restore clock gate + // + \_SB.PCI0.SCPG(1,0x00000041) // restore bit 6 and 0 + + // + // Dummy read PMCSR + // + + Store (PMSR, Local0) + And (Local0, 1, Local0) // Dummy operation on Local0 + } + + Method(_DSM, 0x4, Serialized) + { + //check the UUID + if (LEqual(Arg0, ToUUID("f6c13ea5-65cd-461f-ab7a-29f7e8d5bd61"))) { + //check the revision + If (LEqual(Arg1, Zero)) { + //Switch statement based on the function index. + switch (ToInteger(Arg2)) { + // + // Function Index 0 the return value is a buffer containing + // one bit for each function index, starting with zero. + // Bit 0 - Indicates whether there is support for any functions other than function 0. + // Bit 1 - Indicates support to clear power control register + // Bit 2 - Indicates support to set power control register + // Bit 3 - Indicates support to set 1.8V signalling + // Bit 4 - Indicates support to set 3.3V signalling + // Bit 5 - Indicates support for HS200 mode + // Bit 6 - Indicates support for HS400 mode + // + // On SPT, for eMMC we have to support functions for + // HS200 and HS400 + // + + case(0) + { + Return(Buffer() {0x61}) + } + + // + // Function index 5 - corresponds to HS200 mode + // Return value from this function is used to program + // the UHS Mode Select bits in Host Control 2. + // 011b - corresponds to SDR104 and according to the + // SD Host Controller Spec and this value is overloaded + // to program the controller to select HS200 mode for eMMC. + // + + case(5) + { + Return(Buffer() {0x3}) + } + + // + // Function index 6 - corresponds to HS400 mode + // Return value from this function is used to program + // the UHS Mode Select bits in Host Control 2. + // 101b is a reserved value according to the SD Host + // Controller Spec and we use this value for HS400 mode + // selection. + // + + case(6) + { + Return(Buffer() {0x5}) + } + } // End - Switch(Arg2) + + Return(Buffer() {0x0}) + } Else { + Return(Buffer() {0x0}) + } //End - If else statement for revision check + } Else { + Return(Buffer() {0x0}) + } //End - If else statement for UUID check + } + + Device (EMMD) + { + Name (_ADR, 0x00000008) // Slot 0, Function 8 + Method (_RMV, 0, NotSerialized) + { + Return (0x0) + } + } + } // Device(SDHA) + + // + // UFS + // + Device(UFSH) { + Name (_ADR, 0x001D0000) + Name (_DDN, "Intel(R) UFS Controller - 80865ACE") + Name (_UID, 1) + + OperationRegion (PMCS, PCI_Config, 0x84, 0x4) + Field (PMCS, WordAcc, NoLock, Preserve) { + PMSR, 32, // 0x84, PMCSR - Power Management Control and Status + } + + Method (_PS0, 0, NotSerialized) { // _PS0: Power State 0 + } + + Method (_PS3, 0, NotSerialized) { // _PS3: Power State 3 + // + // Dummy read PMCSR + // + + Store (PMSR, Local0) + And (Local0, 1, Local0) // Dummy operation on Local0 + } + + Name (RBUF, ResourceTemplate () + { + }) + Method (_CRS, 0x0, NotSerialized) + { + Return (RBUF) + } + + Device (UFSD) + { + Name (_ADR, 0x00000008) // Slot 0, Function 8 + Method (_RMV, 0, NotSerialized) + { + Return (0x0) + } + } + } // Device(UFSH) + + // + // SDIO + // + Device(SDIO) { + Name (_ADR, 0x001E0000) + Name (_DDN, "Intel(R) SDIO Controller - 80865AD0") + Name (_UID, 1) + Name (_S0W, 0x03) // _S0W: S0 Device Wake State + + Name (RBUF, ResourceTemplate () + { + }) + + Name (PSTS, 0x0) + + OperationRegion (SCPC, PCI_Config, 0xA0, 4) + Field (SCPC, WordAcc, NoLock, Preserve) + { + Offset (0x00), // 0xA0 D0i3 Max Power Latency Powergating Config + , 17, + I3EN, 1, + DPGE, 1 + } + + OperationRegion (PMCS, PCI_Config, 0x84, 0x4) + Field (PMCS, WordAcc, NoLock, Preserve) { + PMSR, 32, // 0x84, PMCSR - Power Management Control and Status + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (RBUF) + } + + Method (_PS0, 0, NotSerialized) // _PS0: Power State 0 + { + If (LEqual(\_SB.PCI0.SDIO.PSTS,0x0)) { + // + // Disable power gate + // + Store (0, \_SB.PCI0.SDIO.DPGE) + Store (0, \_SB.PCI0.SDIO.I3EN) + // + // Enable clock gate + // + \_SB.PCI0.SCPG(0,0xFFFFFEFE) // Clear bit 8 and 0 + Sleep (2) // Sleep 2 ms + + Store( 0x1, \_SB.PCI0.SDIO.PSTS) // Indicates that the device is powered ON + } + } + + Method (_PS3, 0, NotSerialized) // _PS3: Power State 3 + { + If (LEqual(\_SB.PCI0.SDIO.PSTS,0x1)) { + // + // Enable power gate + // + Store (1, \_SB.PCI0.SDIO.DPGE) + Store (1, \_SB.PCI0.SDIO.I3EN) + + // + // Restore clock gate + // + \_SB.PCI0.SCPG(1,0x00000101) // restore bit 8 and 0 + + // + // Dummy read PMCSR + // + + Store (PMSR, Local0) + And (Local0, 1, Local0) // Dummy operation on Local0 + Store( 0x0, \_SB.PCI0.SDIO.PSTS) // Indicates that the device is powered OFF + } + } + + Method (_DSW, 3, NotSerialized) // _DSW: Device Sleep Wake + { + } + } // Device(SDIO) + + // + // SD Card + // + Device (SDC) { + Name (_ADR, 0x001B0000) // _ADR: Address + Name (_DDN, "Intel(R) SD Card Controller - 80865ACA") // _DDN: DOS Device Name + Name (_S0W, 0x03) // _S0W: S0 Device Wake State + Name (GDW0, 0x00000000) + Name (GDW1, 0x00000000) + + Method (_CRS, 0x0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + // + // Don't align with BoardGpio setting. If do, system can't enter S3 with SD card in slot. + // + GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0, "\\_SB.GPO3", 0, ResourceConsumer, , ) {26} // GPIO_177(SW pin 26):SDCARD_CD_B (SDMMC3_CD_N) + GpioIo(Shared, PullDefault, 0, 0, IoRestrictionInputOnly, "\\_SB.GPO3", 0, ResourceConsumer, , ) {26} // GPIO_177(SW pin 26):SDCARD_CD_B (SDMMC3_CD_N) + }) + + Return (RBUF) + } + + // + // The EPI tool uses the SD Card slot. If the EPI tool is inserted in the SD Card slot, we need to make sure that the slot + // remains powered after OS boot. In order to prevent SD Card enumeration and power down of the slot, we disable the device when EPI + // is enabled in setup. + // + Method (_STA, 0x0, NotSerialized) + { + If (Lequal(EEPI, 1)) { + Return(0x0) + } Else { + Return(0xF) + } + } + + OperationRegion (SCPC, PCI_Config, 0xA0, 4) + Field (SCPC, WordAcc, NoLock, Preserve) + { + Offset (0x00), // 0xA0 D0i3 Max Power Latency Powergating Config + , 17, + I3EN, 1, + DPGE, 1 + } + + OperationRegion(PCCS, PCI_Config, 0x84, 0x04) + Field(PCCS, WordAcc, NoLock, Preserve) { + PMSR, 32 // 84h: Power Gating Control + } + + + + OperationRegion (SCGI, SystemMemory, Or(GP3A, 0x100), 0x10) + Field (SCGI, DWordAcc, NoLock, Preserve) + { + Offset (0x00), + GPIS, 32, // GPI Interrupt Status + } + + OperationRegion (SCGP, SystemMemory, Or(GP3A, 0x5D0), 0x2C) + Field (SCGP, DWordAcc, NoLock, Preserve) + { + Offset (0x00), // SDCARD_CD (177-26) Pad Cfg DW0 + , 1, + RXST, 1, // GPIO RX State + , 23, + RXEV, 2, // RX Level/Edge Configuration + Offset (0x20), // SDCARD_PWR_DOWN_B (183-30) Pad Cfg DW0 + GPOV, 1 // GPO Value + } + + // + // Update GPIO Interrupt status and value used by SD card. + // + Method (WAK, 0x0, Serialized) { + // + // Write clear GPIO_177 Interrupt status (bit26) + // + If (LEqual (\_SB.PCI0.SDC.GPIS, 0x04000000)) { + Store (0x04000000, \_SB.PCI0.SDC.GPIS) + } + \_SB.SPC0 (SW_GPIO_177, GDW0) + \_SB.SPC1 (SW_GPIO_177, GDW1) + } + + Method(_INI, 0) + { + Not(\_SB.PCI0.SDC.RXST, \_SB.PCI0.GRR3) // Set Card Presence in host controller to inverse of RX State in GPIO pad + } + + Method (_PS0, 0, NotSerialized) // _PS0: Power State 0 + { + // + // Set Card Presence in Host Controller to Inverse of RX State in GPIO Pad + // + Not(\_SB.PCI0.SDC.RXST, \_SB.PCI0.GRR3) + + // + // Disable power gate + // + Store (0, \_SB.PCI0.SDC.DPGE) + Store (0, \_SB.PCI0.SDC.I3EN) + + // + // Clear clock gate + // + \_SB.PCI0.SCPG(0, 0xFFFFFBFE) // Clear bit 10 and 0 + + Sleep (2) // Sleep 2 ms + + // + // Restore clock gate + // + \_SB.PCI0.SCPG(1, 0x00000401) // restore bit 10 and 0 + + // + // Turn Card Power On + // + // GPIO 183: Set GPIOTXState = 0 + // + + If (LEqual(BDID,GRBM)) { + Store (1, \_SB.PCI0.SDC.GPOV) + } Else { + Store (0, \_SB.PCI0.SDC.GPOV) + } + + // + // Save GPIO_177 DW0 and DW1 + // + If (LAnd (LEqual (GDW0, 0), LEqual (\_SB.PCI0.SDC.RXEV, 0))) { + Store (\_SB.GPC0 (SW_GPIO_177), GDW0) + Store (\_SB.GPC1 (SW_GPIO_177), GDW1) + } + } + + Method (_PS3, 0, NotSerialized) // _PS3: Power State 3 + { + Store (PMSR, Local0) + + // + // Turn Card Power Off + // + // GPIO 183: Set GPIOTXState = 1 + // + + If (LEqual(BDID,GRBM)) { + Store (0, \_SB.PCI0.SDC.GPOV) + } Else { + Store (1, \_SB.PCI0.SDC.GPOV) + } + + // + // Clear Normal Interrupt Status Enable Bit 6 & 7 + // Clear Normal Interrupt Signal Enable Bit 6 & 7 + // + // Note: SB Port = 0xD6 (SCC), Reg Offset = 0x34 and Reg Offset = 0x38, OpCode = MRd (0) + + // Only Perform the WA If the Card is Already Inserted + If (LEqual(\_SB.PCI0.GRR3, 1)) { + If (LEqual(Local0, 0)) { + SBIM (0xD6000034, 0, 0x1, 0x30D8) + SBIM (0xD6000038, 0, 0x1, 0x30D8) + } + } + + // + // Clear Present Bit (S0ix Fix) + // + Store (0, \_SB.PCI0.GRR3) + + // + // Restore clock gate + // + \_SB.PCI0.SCPG(1, 0x00000401) // restore bit 10 and 0 + + // + // Enable power gate + // + Store (1, \_SB.PCI0.SDC.DPGE) + Store (1, \_SB.PCI0.SDC.I3EN) + + // + // Dummy read PMCSR (SCC D3 WA) + // + + Store (PMSR, Local0) + + } + + Method(_DSM, 0x4, Serialized) + { + // + // Switch based on which unique function identifier was passed in Arg3. + // + If (LEqual(Arg0, ToUUID("f6c13ea5-65cd-461f-ab7a-29f7e8d5bd61"))) { + Switch (ToInteger(Arg2)) + { + // + // Function 0: Return supported functions. + // Currently, we only support: Query, 1.8v & 3.3v switch support functions. + // + Case (0) + { + Switch (ToInteger(Arg1)) + { + // + // REVISION 0: DSM has 6 Supported SUB functions + // + Case (0) {Return (Buffer() {0x19})} + } + // Default Case: Report no functions supported + Return (Buffer() {0x00}) + } + // + // Function 1: Clear Power Control Register + // + Case (1) + { + //Store (Zero, DL13) + Return (Zero) + } + // + // Function 2: Set power control register + // + Case (2) + { + // + // Set Power Control Code + // + + Return (Buffer(){0x00}) + } + // Function 3: Set 1.8v Signalling + Case (3) + { + // + // 1.8v Signalling Code + // + // BXT-P: Nothing to be done here. + // + + Return (Buffer(){0x00}) + } + // Function 4: Set 3.3v Signalling + Case (4) + { + // + // 3.3v Signalling Code + // + // Power Off SD Card: + // GPIO 183: + // Set gpiotxstate =1 + // + + // GPIO 183: Set GPIOTXState = 1 + + If (LEqual(BDID,GRBM)) { + Store (0, \_SB.PCI0.SDC.GPOV) + } Else { + Store (1, \_SB.PCI0.SDC.GPOV) + } + // Sleep for 50ms Between Powering Off / Powering On + Sleep (50) + + // Power On SD Card: + // GPIO 183: + // Set gpiotxstate = 0 + + // GPIO 183: Set GPIOTXState = 0 + + If (LEqual(BDID,GRBM)) { + Store (1, \_SB.PCI0.SDC.GPOV) + } Else { + Store (0, \_SB.PCI0.SDC.GPOV) + } + + Return (Buffer(){0x00}) + } + // Function 5: Enable HS200 capability + Case (5) + { + Return (Buffer(){0x00}) + } + // Function 6: Enable HS400 capability + Case (6) + { + Return (Buffer(){0x00}) + } + // Function 7 (Reserved): Enable Platform Speed Register + } + // + // If not one of the function identifiers we recognize, then return a buffer + // with bit 0 set to 1 indicating no functions supported. + // + Return (Buffer(){0x01}) + } + Else + { + Return (Buffer(One){0x0}) + } + } + } // Device(SDC) +} + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScSmb.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScSmb.asl new file mode 100644 index 0000000000..1cf8b83c31 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScSmb.asl @@ -0,0 +1,558 @@ +/** @file + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + +// Define various SMBus PCI Configuration Space Registers. + +OperationRegion(SMBP,PCI_Config,0x40,0xC0) +Field(SMBP,DWordAcc,NoLock,Preserve) +{ + , 2, + I2CE, 1 +} + +OperationRegion(SMPB,PCI_Config,0x20,4) +Field(SMPB,DWordAcc,NoLock,Preserve) +{ + , 5, + SBAR, 11 +} + +// Define various SMBus IO Mapped Registers. + +OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10) +Field(SMBI,ByteAcc,NoLock,Preserve) +{ + HSTS, 8, // 0 - Host Status Register + Offset(0x02), + HCON, 8, // 2 - Host Control + HCOM, 8, // 3 - Host Command + TXSA, 8, // 4 - Transmit Slave Address + DAT0, 8, // 5 - Host Data 0 + DAT1, 8, // 6 - Host Data 1 + HBDR, 8, // 7 - Host Block Data + PECR, 8, // 8 - Packer Error Check + RXSA, 8, // 9 - Receive Slave Address + SDAT, 16, // A - Slave Data +} + +// SMBus Send Byte - This function will write a single byte of +// data to a specific Slave Device per SMBus Send Byte Protocol. +// Arg0 = Address +// Arg1 = Data +// Return: Success = 1 +// Failure = 0 + +Method(SSXB,2,Serialized) +{ + // Step 1: Confirm the ICHx SMBus is ready to perform + // communication. + + If (STRT()) { + Return(0) + } + + // Step 2: Initiate a Send Byte. + + Store(0,I2CE) // Ensure SMbus Mode. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Arg0,TXSA) // Write Address in TXSA. + Store(Arg1,HCOM) // Data in HCOM. + + // Set the SMBus Host control register to 0x48. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 001 = Byte Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x48,HCON) + + // Step 3: Exit the Method correctly. + + If (COMP) { + Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others.. + Return(1) // Return Success. + } + Return(0) +} + +// SMBus Receive Byte - This function will write a single byte +// of data to a specific Slave Device per SMBus Receive Byte +// Protocol. +// Arg0 = Address +// Return: Success = Byte-Size Value +// Failure = Word-Size Value = FFFFh. + +Method(SRXB,1,Serialized) +{ + // Step 1: Confirm the ICHx SMBus is ready to perform + // communication. + + If (STRT()) { + Return(0xFFFF) + } + + // Step 2: Initiate a Receive Byte. + + Store(0,I2CE) // Ensure SMbus Mode. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Or(Arg0,1),TXSA) // Read Address in TXSA. + + // Set the SMBus Host control register to 0x48. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 001 = Byte Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x44,HCON) + + // Step 3: Exit the Method correctly. + + If (COMP) { + Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others.. + Return(DAT0) // Return Success. + } + Return(0xFFFF) // Return Failure. +} + +// SMBus Write Byte - This function will write a single byte +// of data to a specific Slave Device per SMBus Write Byte +// Protocol. +// Arg0 = Address +// Arg1 = Command +// Arg2 = Data +// Return: Success = 1 +// Failure = 0 + +Method(SWRB,3,Serialized) +{ + // Step 1: Confirm the ICHx SMBus is ready to perform communication. + + If (STRT()) { + Return(0) + } + + // Step 2: Initiate a Write Byte. + + Store(0,I2CE) // Ensure SMbus Mode. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Arg0,TXSA) // Write Address in TXSA. + Store(Arg1,HCOM) // Command in HCOM. + Store(Arg2,DAT0) // Data in DAT0. + + // Set the SMBus Host control register to 0x48. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 010 = Byte Data Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x48,HCON) + + // Step 3: Exit the Method correctly. + + If (COMP) { + Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others.. + Return(1) // Return Success. + } + + Return(0) // Return Failure. +} + +// SMBus Read Byte - This function will read a single byte of data +// from a specific slave device per SMBus Read Byte Protocol. +// Arg0 = Address +// Arg1 = Command +// Return: Success = Byte-Size Value +// Failure = Word-Size Value + +Method(SRDB,2,Serialized) +{ + // Step 1: Confirm the ICHx SMBus is ready to perform communication. + + If (STRT()) { + Return(0xFFFF) + } + + // Step 2: Initiate a Read Byte. + + Store(0,I2CE) // Ensure SMbus Mode. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Or(Arg0,1),TXSA) // Read Address in TXSA. + Store(Arg1,HCOM) // Command in HCOM. + + // Set the SMBus Host control register to 0x48. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 010 = Byte Data Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x48,HCON) + + // Step 3: Exit the Method correctly. + + If (COMP) { + Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others.. + Return(DAT0) // Return Success. + } + + Return(0xFFFF) // Return Failure. +} + +// SMBus Write Word - This function will write a single word +// of data to a specific Slave Device per SMBus Write Word +// Protocol. +// Arg0 = Address +// Arg1 = Command +// Arg2 = Data (16 bits in size) +// Return: Success = 1 +// Failure = 0 + +Method(SWRW,3,Serialized) +{ + // Step 1: Confirm the ICHx SMBus is ready to perform communication. + + If (STRT()) { + Return(0) + } + + // Step 2: Initiate a Write Word. + + Store(0,I2CE) // Ensure SMbus Mode. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Arg0,TXSA) // Write Address in TXSA. + Store(Arg1,HCOM) // Command in HCOM. + And(Arg2,0xFF,DAT1) // Low byte Data in DAT1. + And(ShiftRight(Arg2,8),0xFF,DAT0) // High byte Data in DAT0. + + // Set the SMBus Host control register to 0x4C. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 011 = Word Data Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x4C,HCON) + + // Step 3: Exit the Method correctly. + + If (COMP()) { + Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others. + Return(1) // Return Success. + } + + Return(0) // Return Failure. +} + +// SMBus Read Word - This function will read a single byte of data +// from a specific slave device per SMBus Read Word Protocol. +// Arg0 = Address +// Arg1 = Command +// Return: Success = Word-Size Value +// Failure = Dword-Size Value + +Method(SRDW,2,Serialized) +{ + // Step 1: Confirm the ICHx SMBus is ready to perform communication. + + If (STRT()) { + Return(0xFFFF) + } + + // Step 2: Initiate a Read Word. + + Store(0,I2CE) // Ensure SMbus Mode. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Or(Arg0,1),TXSA) // Read Address in TXSA. + Store(Arg1,HCOM) // Command in HCOM. + + // Set the SMBus Host control register to 0x4C. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 011 = Word Data Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x4C,HCON) + + // Step 3: Exit the Method correctly. + + If (COMP()) { + Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others. + Return(Or(ShiftLeft(DAT0,8),DAT1)) // Return Success. + } + + Return(0xFFFFFFFF) // Return Failure. +} + +// SMBus Block Write - This function will write an entire block of data +// to a specific slave device per SMBus Block Write Protocol. +// Arg0 = Address +// Arg1 = Command +// Arg2 = Buffer of Data to Write +// Arg3 = 1 = I2C Block Write, 0 = SMBus Block Write +// Return: Success = 1 +// Failure = 0 + +Method(SBLW,4,Serialized) +{ + // Step 1: Confirm the ICHx SMBus is ready to perform communication. + + If (STRT()) { + Return(0) + } + + // Step 2: Initiate a Block Write. + + Store(Arg3,I2CE) // Select the proper protocol. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Arg0,TXSA) // Write Address in TXSA. + Store(Arg1,HCOM) // Command in HCOM. + Store(Sizeof(Arg2),DAT0) // Count in DAT0. + Store(0,Local1) // Init Pointer to Buffer. + Store(DerefOf(Index(Arg2,0)),HBDR) // First Byte in HBD Register. + + // Set the SMBus Host control register to 0x48. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 101 = Block Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x54,HCON) + + // Step 3: Send the entire Block of Data. + + While(LGreater(Sizeof(Arg2),Local1)) + { + // Wait up to 200ms for Host Status to get set. + + Store(4000,Local0) // 4000 * 50us = 200ms. + + While(LAnd(LNot(And(HSTS,0x80)),Local0)) + { + Decrement(Local0) // Decrement Count. + Stall(50) // Delay = 50us. + } + + If (LNot(Local0)) { // Timeout? + KILL() // Yes. Kill Communication. + Return(0) // Return failure. + } + + Store(0x80,HSTS) // Clear Host Status. + Increment(Local1) // Point to Next Byte. + + // Place next byte in HBDR if last byte has not been sent. + + If (LGreater(Sizeof(Arg2),Local1)) { + Store(DerefOf(Index(Arg2,Local1)),HBDR) + } + } + + // Step 4: Exit the Method correctly. + + If (COMP()) { + Or(HSTS,0xFF,HSTS) // Clear all status bits. + Return(1) // Return Success. + } + + Return(0) // Return Failure. +} + +// SMBus Block Read - This function will read a block of data from +// a specific slave device per SMBus Block Read Protocol. +// Arg0 = Address +// Arg1 = Command +// Arg2 = 1 = I2C Block Write, 0 = SMBus Block Write +// Return: Success = Data Buffer (First Byte = length) +// Failure = 0 + +Method(SBLR,3,Serialized) +{ + Name(TBUF, Buffer(256) {}) + + // Step 1: Confirm the ICHx SMBus is ready to perform communication. + + If (STRT()) { + Return(0) + } + + // Step 2: Initiate a Block Read. + + Store(Arg2,I2CE) // Select the proper protocol. + Store(0xBF,HSTS) // Clear all but INUSE_STS. + Store(Or(Arg0,1),TXSA) // Read Address in TXSA. + Store(Arg1,HCOM) // Command in HCOM. + + // Set the SMBus Host control register to 0x48. + // Bit 7: = 0 = reserved + // Bit 6: = 1 = start + // Bit 5: = 0 = disregard, I2C related bit + // Bits 4:2: = 101 = Block Protocol + // Bit 1: = 0 = Normal Function + // Bit 0: = 0 = Disable interrupt generation + + Store(0x54,HCON) + + // Step 3: Wait up to 200ms to get the Data Count. + + Store(4000,Local0) // 4000 * 50us = 200ms. + + While(LAnd(LNot(And(HSTS,0x80)),Local0)) + { + Decrement(Local0) // Decrement Count. + Stall(50) // Delay = 50us. + } + + If (LNot(Local0)) { // Timeout? + KILL() // Yes. Kill Communication. + Return(0) // Return failure. + } + + Store(DAT0,Index(TBUF,0)) // Get the Data Count. + Store(0x80,HSTS) // Clear Host Status. + Store(1,Local1) // Local1 = Buffer Pointer. + + // Step 4: Get the Block Data and store it. + + While(LLess(Local1,DerefOf(Index(TBUF,0)))) + { + // Wait up to 200ms for Host Status to get set. + + Store(4000,Local0) // 4000 * 50us = 200ms. + + While(LAnd(LNot(And(HSTS,0x80)),Local0)) + { + Decrement(Local0) // Decrement Count. + Stall(50) // Delay = 50us. + } + + If (LNot(Local0)) { // Timeout? + KILL() // Yes. Kill Communication. + Return(0) // Return failure. + } + + Store(HBDR,Index(TBUF,Local1)) // Place into Buffer. + Store(0x80,HSTS) // Clear Host Status. + Increment(Local1) + } + + // Step 5: Exit the Method correctly. + + If (COMP()) { + Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others. + Return(TBUF) // Return Success. + } + + Return(0) // Return Failure. +} + + +// SMBus Start Check +// Return: Success = 0 +// Failure = 1 + +Method(STRT,0,Serialized) +{ + // Wait up to 200ms to confirm the SMBus Semaphore has been + // released (In Use Status = 0). Note that the Sleep time may take + // longer as the This function will yield the Processor such that it + // may perform different tasks during the delay. + + Store(200,Local0) // 200 * 1ms = 200ms. + + While(Local0) + { + If (And(HSTS,0x40)) { // In Use Set? + Decrement(Local0) // Yes. Decrement Count. + Sleep(1) // Delay = 1ms. + If (LEqual(Local0,0)) { // Count = 0? + Return(1) // Return failure. + } + } Else { + Store(0,Local0) // In Use Clear. Continue. + } + } + + // In Use Status = 0 during last read, which will make subsequent + // reads return In Use Status = 1 until software clears it. All + // software using ICHx SMBus should check this bit before initiating + // any SMBus communication. + + // Wait up to 200ms to confirm the Host Interface is + // not processing a command. + + Store(4000,Local0) // 4000 * 50us = 200ms. + + While(Local0) + { + If (And(HSTS,0x01)) { // Host Busy Set? + Decrement(Local0) // Decrement Count. + Stall(50) // Delay = 50us. + If (LEqual(Local0,0)) { // Count = 0? + KILL() // Yes. Kill Communication. + } + } Else { + Return(0) + } + } + + Return(1) // Timeout. Return failure. +} + +// SMBus Completion Check +// Return: Success = 1 +// Failure = 0 + +Method(COMP,0,Serialized) +{ + // Wait for up to 200ms for the Completion Command + // Status to get set. + + Store(4000,Local0) // 4000 * 50us = 200ms. + + While(Local0) + { + If (And(HSTS,0x02)) { // Completion Status Set? + Return(1) // Yes. We are done. + } Else { + Decrement(Local0) // Decrement Count. + Stall(50) // Delay 50us. + If (LEqual(Local0,0)) { // Count = 0? + KILL() // Yes. Kill Communication. + } + } + } + + Return(0) // Timeout. Return Failure. +} + +// SMBus Kill Command + +Method(KILL,0,Serialized) +{ + Or(HCON,0x02,HCON) // Yes. Send Kill command. + Or(HSTS,0xFF,HSTS) // Clear all status. +} + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScXdci.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScXdci.asl new file mode 100644 index 0000000000..8a6eb782e9 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScXdci.asl @@ -0,0 +1,300 @@ +/** @file + Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +External(XDCE, IntObj) +External(XDAT, MethodObj) + +Scope(\_SB.PCI0) +{ + Device(XDCI) + { + Name (_ADR, 0x00150001) // _ADR: Address Device 21, Function 1 + OperationRegion (OTGD, PCI_Config, 0x0, 0x100) + Field (OTGD, DWordAcc, NoLock, Preserve) + { + Offset(0x0), + DVID, 16, + Offset(0x10), + XDCB, 64 + } + // + // Byte access for PMCS field to avoid race condition on device D-state. + // + Field (OTGD, ByteAcc, NoLock, Preserve) + { + Offset(0x74), // PM_CS - Power Management Control/Status + D0I3, 2, // PM_CS[1:0] PowerState + , 6, + PMEE, 1, // bit 8, PME Enable + , 6, + PMES, 1 // bit 15, PME Status + } + + Name (_DDN, "Broxton XDCI controller") // _DDN: DOS Device Name + Name (_STR, Unicode ("Broxton XDCI controller")) // _STR: Description String + + Method(_S0W, 0) + { + Return (3) + } + + Method (_DSW, 3) // _DSW: Device Sleep Wake + { + Return (Zero) + } + + Name (_PRW, Package() {0x0C, 4}) // Declare xDCI GPE status and enable bits are bit 12. + + Method(XDBA, 0) + { + Return(And(^XDCB, 0xFFFFFFFFFFFFFF00)) + } + + // + // Arg0: UUID = {732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511} + // Arg1: Revision ID = 1 + // Arg2: Function Index + // Arg3: Argument + // + Method(_DSM,4,Serialized) + { + If (PCIC(Arg0)) { Return(PCID(Arg0,Arg1,Arg2,Arg3)) } + + + If (LEqual(Arg0, ToUUID("732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"))) { + If (Lequal(Arg1, 1)) { + // + // Set PMU Power State + // Arg0: 0x00 PMU should enter the D0 power state. + // 0x03 PMU should enter the D3 power state. + // Arg1: 0x03 Enable PMU PME + // 0x00 Clear PMU PME + // + Method (SPPS,2,Serialized) { + OperationRegion(XDBW, SystemMemory, XDBA(), 0x110000) + Field(XDBW, WordAcc, NoLock, Preserve) + { + Offset(0x10f810), + , 8, + U2CP, 2, // USB2 core power state + U3CP, 2, // USB3 core power state + Offset(0x10f818), + PUPS, 2, // PMU power state + , 1, + PURC, 1, // Reset PMU core + , 12, + Offset(0x10f81c), + , 3, + UXPE, 2, // U2 PME EN / U3 PME EN + , 11, + } + + // Local 1 is power state D0 or D3 + Store(Arg0, Local1) + // Local 2 is Enable/Clear PMU PME + Store(Arg1, Local2) + + If (LEqual(Local1, 0)) { + + // Clear PMU PME + // 0x10F81C BIT3: USB3 PME + // 0x10F81C BIT4: USB2 PME + Store(0, UXPE) + // Wait for at least 100us, currently configured to 1000us + Store(0, Local0) + While (LLess(Local0, 10)) { + Stall(100) + Increment(Local0) + } + // Set PMU to D0 by writing 0 to 0x10f818 Bit 1:0 + Store(0, PUPS) + // Wait 200ms for PMU to enter D0 + // Confirm PMU being in D0 by checking 0x10f810 Bit 11:8 to be clear + // 0x10f810 Bit 11:10 - Current power state of USB3 core + // 0x10f810 Bit 9:8 - Current power state of USB2 core + // both should be clear + Store(0,Local0) + While (LLess(Local0,2000)) { + Stall(100) + If (LAnd(LEqual(U2CP,0),LEqual(U3CP,0))) { + break + } + Increment(Local0) + } + If (LNotEqual(U2CP, 0)) { + // Show warning message + + } + If (LNotEqual(U3CP, 0)) { + // Show warning message + + } + Return(0) + } + + If (LEqual(Local1, 3)) { + + // PMU should be in D0 at this point + // 0x10f810 Bit 11:10 - current power state of USB3 core + // 0x10f810 Bit 9:8 - current power state of USB2 core + // both should be clear + If (LNotEqual(U2CP, 0)) { + // Show warning message + + } + If (LNotEqual(U3CP, 0)) { + // Show warning message + + } + // Set PMU to D3 by writing 3 to 0x10f818 bit 1:0 + Store(3, PUPS) + // Wait 200ms for PMU to enter D3 + // Confirm PMU being in D3 by checking 0x10f810 Bit 11:8 to be set + // 0x10f810 Bit 11:10 - Current power state of USB3 core + // 0x10f810 Bit 9:8 - Current power state of USB2 core + // both should be set + Store(0,Local0) + While (LLess(Local0,2000)) { + Stall(100) + If (LAnd(LEqual(U2CP,3),LEqual(U3CP,3))) { + break + } + Increment(Local0) + } + If (LNotEqual(U2CP, 3)) { + // Show warning message + + } + If (LNotEqual(U3CP, 3)) { + // Show warning message + + } + // Set/Clear PMU PME + // 0x10F81C BIT3: USB3 PME + // 0x10F81C BIT4: USB2 PME + Store(Local2, UXPE) + Return(0) + } + Return(0) + } + + Switch(ToInteger(Arg2)){ + Case(0){ + // Function 0: return Bit map to indicate Function 0,1,3,4,5,6,7 supported + + Return(Buffer(){0xfb}) + } + Case(1){ + // Function 1: Attach/Detach and Port Detection Properties Method + // This method is called by the USB function stack to set the power state of the PMU. + // Bit 0 as 1: to indicate Platform support for Attach/detach notify + // Bit 1 as 0:HW based charging indication + + Return(0x1) + } + Case(3){ + // Function 3: Check xDCI status + // Return (0x0), xDCI disabled + // Return (0x1), xDCI enabled + + Return(XDCE) + } + Case(4){ + // Function 4: Set PMU Power State Method, clear PMU PME + // Arg3: A package consisting of 1 ULONG value + // 0x00 PMU should enter the D0 power state. + // 0x03 PMU should enter the D3 power state. + + + // Local 1 is power state D0 or D3 + Store(DerefOf(Index(Arg3,0)), Local1) + + + // Set PMU to Dx state and clear PMU PME + SPPS(Local1, 0) + } + Case(5){ + // Function 5: Attach Notification Enabled Method + // This method is called by the USB function stack to indicate that it has enabled ACPI attach detach notifications. + // In response the platform may issue an notification indicating the current attach/detach state of the controller. + + // If device is attached, notify XDCI with 0x80 + // If device is detached, notify XDCI with 0x81 + + + + Return(0) + } + Case(6){ + // Function 6: XDCI Soft Reset Workaround + // Return value indicate to OS softreset should be done by OS or not + // Return value == 1: OS does softreset + // Return value == 0: platform does softreset + + + + OperationRegion(XDBD, SystemMemory, XDBA(), 0x110000) + Field(XDBD, DwordAcc, NoLock, Preserve) + { + Offset(0xC704), + , 30, + CSFR, 1, + , 1, + } + OperationRegion(XDW2, SystemMemory, XDBA(), 0x110000) + Field(XDW2, WordAcc, NoLock, Preserve) + { + Offset(0x10f820), + , 13, + OTHC, 1, // OTG switched to host complete + } + + If (LEqual(OTHC, 0)) { + Store(1, CSFR) + // timeout is 100ms + Store(0, Local0) + While (LLess(Local0, 100)) { + If (LEqual(CSFR, 0)) { + Break + } + Sleep(1) + } + } + Return(0) + } + Case(7){ + // Function 7: Get PMU Power State Method + // Return: + // 0: PMU is in D0 state + // 3: PMU is in D3 state + + + + OperationRegion(XD22, SystemMemory, XDBA(), 0x110000) + Field(XD22, WordAcc, NoLock, Preserve) + { + Offset(0x10f818), + P2PS, 2, // PMU power state + , 14, + } + Store(P2PS, Local0) + Return(Local0) + } + } // Switch Arg2 + } // if Rev == 1 + } // if UUID match + Return(0) + } // _DSM + } // XDCI +} + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScXhci.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScXhci.asl new file mode 100644 index 0000000000..34a93fc9ad --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/ScXhci.asl @@ -0,0 +1,611 @@ +/** @file + Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +//scope is \_SB.PCI0.XHC +Device(XHC) { + Name(_ADR, 0x00150000) //Device 21, Function 0 + + Name (_DDN, "Broxton XHCI controller (Host only)" ) + Name (_STR, Unicode ("Broxton XHCI controller (Host only)")) + + Method(_S0W, 0x0, NotSerialized) // _S0W: S0 Device Wake State + { + Return(0x3) + } + Name (_PRW, Package() {0x0D, 4}) // Declare XHCI GPE status and enable bits are bit 13. + + OperationRegion (USBR, PCI_Config, 0x74, 0x04) + Field (USBR, WordAcc, NoLock, Preserve) + { + Offset (0x01), + PMEE, 1, + , 6, + PMES, 1 + } + + Method (_DSW, 3, NotSerialized) // _DSW: Device Sleep Wake + { + Store (Arg0, PMEE) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + Return (Zero) + } + //_PS3 is removed as requested (SV D3 verified) + + Method(_STA, 0) + { + Return (0xF) + } + + Device(RHUB) + { + Name(_ADR, Zero) + + Method(TPLD, 2, Serialized) { // For the port related with USB Tyep C. copied and modifined from GPLD + // Arg0: Visiable + // Arg1: Group position + Name(PCKG, Package() { Buffer(0x14) {} } ) + CreateField(DerefOf(Index(PCKG,0)), 0, 7, REV) + Store(1,REV) + CreateField(DerefOf(Index(PCKG,0)), 64, 1, VISI) + Store(Arg0, VISI) + CreateField(DerefOf(Index(PCKG,0)), 87, 8, GPOS) + Store(Arg1, GPOS) + CreateField(DerefOf(Index(PCKG,0)), 128, 32,VHOS) + Store(0xFFFFFFFF, VHOS) + + // Following add for USB type C + CreateField(DerefOf(Index(PCKG,0)), 74, 4, SHAP) // Shape set to Oval + Store(1, SHAP) + CreateField(DerefOf(Index(PCKG,0)), 32, 16, WID) // Width of the connector, 8.34mm + Store(8, WID) + CreateField(DerefOf(Index(PCKG,0)), 48, 16, HGT) // Height of the connector, 2.56mm + Store(3, HGT) + return (PCKG) + } + Method(TUPC, 1, Serialized) { // For the port related with USB Tyep C. copied and modifined from GUPC + // Arg0: Type + // Type: + // 0x08: Type-C connector - USB2-only + // 0x09: Type-C connector - USB2 and SS with Switch + // 0x0A: Type-C connector - USB2 and SS without Switch + Name(PCKG, Package(4) { 1, 0x00, 0, 0 } ) + Store(Arg0,Index(PCKG,1)) + return (PCKG) + } + + // + // High Speed Ports + // It would be USB2.0 port if SS termination is disabled + + // The UPC declarations for LS/FS/HS and SS ports that are paired to form a USB3.0 compatible connector. + // A "pair" is defined by two ports that declare _PLDs with identical Panel, Vertical Position, Horizontal Postion, Shape, Group Orientation + // and Group Token + + Device(HS01) // Pair with SS01: OTG(Dual Role) Port + { + Name(_ADR, 0x01) + Method(_UPC,0,Serialized) { + Return (TUPC(9)) + } + + Method(_PLD,0,Serialized) { + Return (TPLD(1,1)) + } + }//end of HS01 + + Device(HS02) + { + Name(_ADR, 0x02) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { 0xFF,0x00,0x00,0x00 }) + Return(UPCP) + } + + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x14) + { + //31:0 - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored + 0x82, 0x00, 0x00, 0x00, + //63:32 - Bit[47:32]=0 width: 0x0000 Bit[63:48]=0 Height:0x0000 + 0x00, 0x00, 0x00, 0x00, + //95:64 - bit[66:64]=b'011 visiable/docking/no lid bit[69:67]=b'001 bottom panel bit[71:70]=b'01 Center bit[73:72]=b'01 Center + // bit[77:74]=6 Horizontal Trapezoid bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay + //[71:64][79:72][87:80][95:88] + 0x41, 0x08, 0x02, 0x00, + //127:96 -bit[96]=1 Ejectable bit[97]=1 OSPM Ejection required Bit[105:98]=0 no Cabinet Number + // bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order + 0x00, 0x00, 0x00, 0x00, + //159:128 Vert. and Horiz. Offsets not supplied + 0xFF, 0xFF, 0xFF, 0xFF + } + }) + + Return (PLDP) + } + }//end of HS02 + + Device(HS03) + { + Name(_ADR, 0x03) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { 0xFF,0xFF,0x00,0x00 }) + Return(UPCP) + } + + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x14) + { + //31:0 - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored + 0x82, 0x00, 0x00, 0x00, + //63:32 - Bit[47:32]=0 width: 0x0000 Bit[63:48]=0 Height:0x0000 + 0x00, 0x00, 0x00, 0x00, + //95:64 - bit[66:64]=b'011 visiable/docking/no lid bit[69:67]=b'001 bottom panel bit[71:70]=b'01 Center bit[73:72]=b'01 Center + // bit[77:74]=6 Horizontal Trapezoid bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay + //[71:64][79:72][87:80][95:88] + 0x40, 0x08, 0x03, 0x00, + //127:96 -bit[96]=1 Ejectable bit[97]=1 OSPM Ejection required Bit[105:98]=0 no Cabinet Number + // bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order + 0x00, 0x00, 0x00, 0x00, + //159:128 Vert. and Horiz. Offsets not supplied + 0xFF, 0xFF, 0xFF, 0xFF + } + }) + + Return (PLDP) + } + }//end of HS03 + + Device(HS04) + { + Name(_ADR, 0x04) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { 0xFF,0x00,0x00,0x00 }) + Return(UPCP) + } + + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x14) + { + //31:0 - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored + 0x82, 0x00, 0x00, 0x00, + //63:32 - Bit[47:32]=0 width: 0x0000 Bit[63:48]=0 Height:0x0000 + 0x00, 0x00, 0x00, 0x00, + //95:64 - bit[66:64]=b'011 visiable/docking/no lid bit[69:67]=b'001 bottom panel bit[71:70]=b'01 Center bit[73:72]=b'01 Center + // bit[77:74]=6 Horizontal Trapezoid bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay + //[71:64][79:72][87:80][95:88] + 0x41, 0x08, 0x04, 0x00, + //127:96 -bit[96]=1 Ejectable bit[97]=1 OSPM Ejection required Bit[105:98]=0 no Cabinet Number + // bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order + 0x00, 0x00, 0x00, 0x00, + //159:128 Vert. and Horiz. Offsets not supplied + 0xFF, 0xFF, 0xFF, 0xFF + } + }) + + Return (PLDP) + } + }//end of HS04 + + Device(HS05) + { + Name(_ADR, 0x05) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { 0xFF,0x00,0x00,0x00 }) + Return(UPCP) + } + + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x14) + { + //31:0 - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored + 0x82, 0x00, 0x00, 0x00, + //63:32 - Bit[47:32]=0 width: 0x0000 Bit[63:48]=0 Height:0x0000 + 0x00, 0x00, 0x00, 0x00, + //95:64 - bit[66:64]=b'011 visiable/docking/no lid bit[69:67]=b'001 bottom panel bit[71:70]=b'01 Center bit[73:72]=b'01 Center + // bit[77:74]=6 Horizontal Trapezoid bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay + //[71:64][79:72][87:80][95:88] + 0x41, 0x08, 0x05, 0x00, + //127:96 -bit[96]=1 Ejectable bit[97]=1 OSPM Ejection required Bit[105:98]=0 no Cabinet Number + // bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order + 0x00, 0x00, 0x00, 0x00, + //159:128 Vert. and Horiz. Offsets not supplied + 0xFF, 0xFF, 0xFF, 0xFF + } + }) + + Return (PLDP) + } + }//end of HS05 + + Device(HS06) + { + Name(_ADR, 0x06) + Method(_UPC,0,Serialized) { + // No connect + Name(UPCP, Package() { 0x00,0xFF,0x00,0x00 }) + Return(UPCP) + } + + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x14) + { + //31:0 - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored + 0x82, 0x00, 0x00, 0x00, + //63:32 - Bit[47:32]=0 width: 0x0000 Bit[63:48]=0 Height:0x0000 + 0x00, 0x00, 0x00, 0x00, + //95:64 - bit[66:64]=b'011 visiable/docking/no lid bit[69:67]=b'001 bottom panel bit[71:70]=b'01 Center bit[73:72]=b'01 Center + // bit[77:74]=6 Horizontal Trapezoid bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay + //[71:64][79:72][87:80][95:88] + 0x40, 0x08, 0x06, 0x00, + //127:96 -bit[96]=1 Ejectable bit[97]=1 OSPM Ejection required Bit[105:98]=0 no Cabinet Number + // bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order + 0x00, 0x00, 0x00, 0x00, + //159:128 Vert. and Horiz. Offsets not supplied + 0xFF, 0xFF, 0xFF, 0xFF + } + }) + + Return (PLDP) + } + }//end of HS06 + + Device(HS07) + { + Name(_ADR, 0x07) + Method(_UPC,0,Serialized) { + // No connect + Name(UPCP, Package() { 0xFF,0xFF,0x00,0x00 }) + Return(UPCP) + } + + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x14) + { + //31:0 - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored + 0x82, 0x00, 0x00, 0x00, + //63:32 - Bit[47:32]=0 width: 0x0000 Bit[63:48]=0 Height:0x0000 + 0x00, 0x00, 0x00, 0x00, + //95:64 - bit[66:64]=b'011 visiable/docking/no lid bit[69:67]=b'001 bottom panel bit[71:70]=b'01 Center bit[73:72]=b'01 Center + // bit[77:74]=6 Horizontal Trapezoid bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay + //[71:64][79:72][87:80][95:88] + 0x40, 0x08, 0x07, 0x00, + //127:96 -bit[96]=1 Ejectable bit[97]=1 OSPM Ejection required Bit[105:98]=0 no Cabinet Number + // bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order + 0x00, 0x00, 0x00, 0x00, + //159:128 Vert. and Horiz. Offsets not supplied + 0xFF, 0xFF, 0xFF, 0xFF + } + }) + + Return (PLDP) + } + }//end of HS07 + + Device(HS08) + { + Name(_ADR, 0x08) + Method(_UPC,0,Serialized) { + // No connect + Name(UPCP, Package() { 0xFF,0xFF,0x00,0x00 }) + Return(UPCP) + } + + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x14) + { + //31:0 - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored + 0x82, 0x00, 0x00, 0x00, + //63:32 - Bit[47:32]=0 width: 0x0000 Bit[63:48]=0 Height:0x0000 + 0x00, 0x00, 0x00, 0x00, + //95:64 - bit[66:64]=b'011 visiable/docking/no lid bit[69:67]=b'001 bottom panel bit[71:70]=b'01 Center bit[73:72]=b'01 Center + // bit[77:74]=6 Horizontal Trapezoid bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay + //[71:64][79:72][87:80][95:88] + 0x40, 0x08, 0x08, 0x00, + //127:96 -bit[96]=1 Ejectable bit[97]=1 OSPM Ejection required Bit[105:98]=0 no Cabinet Number + // bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order + 0x00, 0x00, 0x00, 0x00, + //159:128 Vert. and Horiz. Offsets not supplied + 0xFF, 0xFF, 0xFF, 0xFF + } + }) + + Return (PLDP) + } + + // Add Camera built in Device + Device (FCAM) + { + Name(_ADR, 0x08) + + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { 0xFF,0xFF,0x00,0x00 }) // Connectable, Proprietary connector + Return(UPCP) + } + + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { + Buffer(0x14) + { + //31:0 - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored + 0x82, 0x00, 0x00, 0x00, + //63:32 - Bit[47:32]=0 width: 0x0000 Bit[63:48]=0 Height:0x0000 + 0x00, 0x00, 0x00, 0x00, + //95:64 - bit[66:64]=b'000 in-visiable/ no docking/no lid bit[69:67]=b'100 front panel bit[71:70]=b'01 Center bit[73:72]=b'01 Center + // bit[77:74]=6 Horizontal Trapezoid bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay + //[71:64][79:72][87:80][95:88] + 0x60, 0x08, 0x08, 0x00, + //127:96 -bit[96]=1 Ejectable bit[97]=1 OSPM Ejection required Bit[105:98]=0 no Cabinet Number + // bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order + 0x00, 0x00, 0x00, 0x00, + //159:128 Vert. and Horiz. Offsets not supplied + 0xFF, 0xFF, 0xFF, 0xFF + } + }) + + Return (PLDP) + } + } + }//end of HS08 + + // + // Super Speed Ports - must match _UPC declarations of the corresponding Full Speed Ports. + // + Device(SSP1) //Pair with HS01: OTG(Dual Role) Port + { + Name(_ADR, 0x09) + Method(_UPC,0,Serialized) { + Return (TUPC(9)) + } + + Method(_PLD,0,Serialized) { + Return (TPLD(1,1)) + } + }//end of SSP1 + + Device(SSP2) + { + Name(_ADR, 0x0A) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { + 0xFF, //port is connectable if non-zero + 0x03, //USB3 Type A connector + 0x00, + 0x00 }) + + Return(UPCP) + } + + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { //pls check ACPI 5.0 section 6.1.8 + Buffer(0x14) + { + //31:0 - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored + 0x82, 0x00, 0x00, 0x00, + //63:32 - Bit[47:32]=0 width: 0x0000 Bit[63:48]=0 Height:0x0000 + 0x00, 0x00, 0x00, 0x00, + //95:64 - bit[66:64]=b'011 visiable/docking/no lid bit[69:67]=b'001 bottom panel bit[71:70]=b'01 Center bit[73:72]=b'01 Center + // bit[77:74]=6 Horizontal Trapezoid bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay + //[71:64][79:72][87:80][95:88] + 0x41, 0x08, 0x02, 0x00, + //127:96 -bit[96]=1 Ejectable bit[97]=1 OSPM Ejection required Bit[105:98]=0 no Cabinet Number + // bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order + 0x00, 0x00, 0x00, 0x00, + //159:128 Vert. and Horiz. Offsets not supplied + 0xFF, 0xFF, 0xFF, 0xFF + } + }) + + Return (PLDP) + } + }//end of SSP2 + + Device(SSP3) + { + Name(_ADR, 0x0B) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { + 0xFF, //port is connectable if non-zero + 0xFF, + 0x00, + 0x00 }) + + Return(UPCP) + } + + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { //pls check ACPI 5.0 section 6.1.8 + Buffer(0x14) + { + //31:0 - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored + 0x82, 0x00, 0x00, 0x00, + //63:32 - Bit[47:32]=0 width: 0x0000 Bit[63:48]=0 Height:0x0000 + 0x00, 0x00, 0x00, 0x00, + //95:64 - bit[66:64]=b'011 visiable/docking/no lid bit[69:67]=b'001 bottom panel bit[71:70]=b'01 Center bit[73:72]=b'01 Center + // bit[77:74]=6 Horizontal Trapezoid bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay + //[71:64][79:72][87:80][95:88] + 0x40, 0x08, 0x03, 0x00, + //127:96 -bit[96]=1 Ejectable bit[97]=1 OSPM Ejection required Bit[105:98]=0 no Cabinet Number + // bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order + 0x00, 0x00, 0x00, 0x00, + //159:128 Vert. and Horiz. Offsets not supplied + 0xFF, 0xFF, 0xFF, 0xFF + } + }) + + Return (PLDP) + } + }//end of SSP3 + + Device(SSP4) + { + Name(_ADR, 0x0C) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { + 0x00, //port is not-connectable + 0xFF, //proprietary connector going to PCIe port + 0x00, + 0x00 }) + + Return(UPCP) + } + + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { //pls check ACPI 5.0 section 6.1.8 + Buffer(0x14) + { + //31:0 - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored + 0x82, 0x00, 0x00, 0x00, + //63:32 - Bit[47:32]=0 width: 0x0000 Bit[63:48]=0 Height:0x0000 + 0x00, 0x00, 0x00, 0x00, + //95:64 - bit[66:64]=b'011 visiable/docking/no lid bit[69:67]=b'001 bottom panel bit[71:70]=b'01 Center bit[73:72]=b'01 Center + // bit[77:74]=6 Horizontal Trapezoid bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay + //[71:64][79:72][87:80][95:88] + 0x40, 0x08, 0x04, 0x00, + //127:96 -bit[96]=1 Ejectable bit[97]=1 OSPM Ejection required Bit[105:98]=0 no Cabinet Number + // bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order + 0x00, 0x00, 0x00, 0x00, + //159:128 Vert. and Horiz. Offsets not supplied + 0xFF, 0xFF, 0xFF, 0xFF + } + }) + + Return (PLDP) + } + }//end of SSP4 + + Device(SSP5) + { + Name(_ADR, 0x0D) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { + 0xFF, //port is connectable if non-zero + 0x03, //USB3 Type A connector + 0x00, + 0x00 }) + + Return(UPCP) + } + + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { //pls check ACPI 5.0 section 6.1.8 + Buffer(0x14) + { + //31:0 - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored + 0x82, 0x00, 0x00, 0x00, + //63:32 - Bit[47:32]=0 width: 0x0000 Bit[63:48]=0 Height:0x0000 + 0x00, 0x00, 0x00, 0x00, + //95:64 - bit[66:64]=b'011 visiable/docking/no lid bit[69:67]=b'001 bottom panel bit[71:70]=b'01 Center bit[73:72]=b'01 Center + // bit[77:74]=6 Horizontal Trapezoid bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay + //[71:64][79:72][87:80][95:88] + 0x41, 0x08, 0x05, 0x00, + //127:96 -bit[96]=1 Ejectable bit[97]=1 OSPM Ejection required Bit[105:98]=0 no Cabinet Number + // bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order + 0x00, 0x00, 0x00, 0x00, + //159:128 Vert. and Horiz. Offsets not supplied + 0xFF, 0xFF, 0xFF, 0xFF + } + }) + + Return (PLDP) + } + }//end of SSP5 + + Device(SSP6) + { + Name(_ADR, 0x0E) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { + 0x00, //port is connectable if non-zero + 0xFF, + 0x00, + 0x00 }) + + Return(UPCP) + } + + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { //pls check ACPI 5.0 section 6.1.8 + Buffer(0x14) + { + //31:0 - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored + 0x82, 0x00, 0x00, 0x00, + //63:32 - Bit[47:32]=0 width: 0x0000 Bit[63:48]=0 Height:0x0000 + 0x00, 0x00, 0x00, 0x00, + //95:64 - bit[66:64]=b'011 visiable/docking/no lid bit[69:67]=b'001 bottom panel bit[71:70]=b'01 Center bit[73:72]=b'01 Center + // bit[77:74]=6 Horizontal Trapezoid bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay + //[71:64][79:72][87:80][95:88] + 0x40, 0x08, 0x06, 0x00, + //127:96 -bit[96]=1 Ejectable bit[97]=1 OSPM Ejection required Bit[105:98]=0 no Cabinet Number + // bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order + 0x00, 0x00, 0x00, 0x00, + //159:128 Vert. and Horiz. Offsets not supplied + 0xFF, 0xFF, 0xFF, 0xFF + } + }) + + Return (PLDP) + } + }//end of SSP6 + + // + // SSIC PORT + // + Device(SSP7) + { + Name(_ADR, 0x0F) + Method(_UPC,0,Serialized) { + Name(UPCP, Package() { + 0x00, //port is connectable if non-zero + 0xFF, //proprietary connector + 0x00, + 0x00 }) + + Return(UPCP) + } + + Method(_PLD,0,Serialized) { + Name(PLDP, Package() { //pls check ACPI 5.0 section 6.1.8 + Buffer(0x14) + { + //31:0 - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored + 0x82, 0x00, 0x00, 0x00, + //63:32 - Bit[47:32]=0 width: 0x0000 Bit[63:48]=0 Height:0x0000 + 0x00, 0x00, 0x00, 0x00, + //95:64 - bit[66:64]=b'011 visiable/docking/no lid bit[69:67]=b'001 bottom panel bit[71:70]=b'01 Center bit[73:72]=b'01 Center + // bit[77:74]=6 Horizontal Trapezoid bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay + //[71:64][79:72][87:80][95:88] + 0x40, 0x08, 0x07, 0x00, + //127:96 -bit[96]=1 Ejectable bit[97]=1 OSPM Ejection required Bit[105:98]=0 no Cabinet Number + // bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order + 0x00, 0x00, 0x00, 0x00, + //159:128 Vert. and Horiz. Offsets not supplied + 0xFF, 0xFF, 0xFF, 0xFF + } + }) + + Return (PLDP) + } + }//end of SSP7 + } //end of root hub +} // end of XHC1 + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtPcie.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtPcie.asl new file mode 100644 index 0000000000..82465f0a59 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtPcie.asl @@ -0,0 +1,312 @@ +/** @file + ACPI RTD3 SSDT table for BXT PCIe + + Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Name(WKEN, 0) + + Method(_S0W, 0) + { + /// This method returns the lowest D-state supported by PCIe root port during S0 state + + ///- PMEs can be generated from D3Cold for ULT + Return(4) + + /** @defgroup pcie_s0W PCIE _S0W **/ + } // End _S0W + + + Method(_DSW, 3) + { + /// This method is used to enable/disable wake from PCIe (WKEN) + If (Arg1) { /// If entering Sx, need to disable WAKE# from generating runtime PME + Store(0, WKEN) + } Else { /// If Staying in S0 + If (LAnd(Arg0, Arg2)) { + ///- Check if Exiting D0 and arming for wake + ///- Set PME + Store(1, WKEN) + } Else { ///- Disable runtime PME, either because staying in D0 or disabling wake + Store(0, WKEN) + } + } + + /** @defgroup pcie_dsw PCIE _DSW **/ + } // End _DSW + + + PowerResource(PXP, 0, 0) + { + /// Define the PowerResource for PCIe slot + /// Method: _STA(), _ON(), _OFF() + /** @defgroup pcie_pxp PCIE Power Resource **/ + + Method(_STA, 0) + { + /// Returns the status of PCIe slot core power + + // detect power pin status + if (LNotEqual(DeRefOf(Index(PWRG, 0)),0)) { + if (LEqual(DeRefOf(Index(PWRG, 0)),1)) { // GPIO mode + if (LEqual(\_SB.GGOV(DeRefOf(Index(PWRG, 2))),DeRefOf(Index(PWRG, 3)))) { + Return (1) + } Else { + Return (0) + } + } // GPIO mode + } + // detect reset pin status + if (LNotEqual(DeRefOf(Index(RSTG, 0)),0)) { + if (LEqual(DeRefOf(Index(RSTG, 0)),1)) { // GPIO mode + if (LEqual(\_SB.GGOV(DeRefOf(Index(RSTG, 2))),DeRefOf(Index(RSTG, 3)))) { + Return (1) + } Else { + Return (0) + } + } // GPIO mode + } + Return (0) + } /** @defgroup pcie_sta PCIE _STA method **/ + + Method(_ON,0,Serialized) /// Turn on core power to PCIe Slot + { + Name(PCIA, 0) + // + // Windows will call _ON for all devices,regardless + // of the device enable state. + // We need to exit when the device is not present + // to prevent driving power to the device. + // + if (LEqual(SLOT, 1)) { + ShiftRight(RPA1, 1, PCIA) + Or(0xE0000000, PCIA, PCIA) + PON(PCIA) + } elseif(LEqual(SLOT, 2)) { + ShiftRight(RPA2, 1, PCIA) + Or(0xE0000000, PCIA, PCIA) + PON(PCIA) + } elseif(LEqual(SLOT, 3)) { + ShiftRight(RPA3, 1, PCIA) + Or(0xE0000000, PCIA, PCIA) + PON(PCIA) + } elseif(LEqual(SLOT, 4)) { + ShiftRight(RPA4, 1, PCIA) + Or(0xE0000000, PCIA, PCIA) + PON(PCIA) + } elseif(LEqual(SLOT, 5)) { + ShiftRight(RPA5, 1, PCIA) + Or(0xE0000000, PCIA, PCIA) + PON(PCIA) + } elseif(LEqual(SLOT, 6)) { + ShiftRight(RPA6, 1, PCIA) + Or(0xE0000000, PCIA, PCIA) + PON(PCIA) + } + } + + Method(PON, 1, Serialized) { + OperationRegion(PX02,SystemMemory, Arg0,0x380) + Field(PX02,AnyAcc, NoLock, Preserve) + { + Offset(0), + VD02, 32, + Offset(0x50), // LCTL - Link Control Register + L0SE, 1, // 0, L0s Entry Enabled + , 3, + LDIS, 1, + Offset(0x52), // LSTS - Link Status Register + , 13, + LASX, 1, // 0, Link Active Status + Offset(0xE2), // RPPGEN - Root Port Power Gating Enable + , 2, + L23E, 1, // 2, L23_Rdy Entry Request (L23ER) + L23R, 1, // 3, L23_Rdy to Detect Transition (L23R2DT) + Offset(0xF4), // BLKPLLEN + , 10, + BPLL, 1, + Offset(0x324), + , 3, + LEDM, 1, // PCIEDBG.DMIL1EDM + Offset(0x338), + , 26, + BDQA, 1 // BLKDQDA + } + /// Turn ON Power for PCIe Slot + if (LNotEqual(DeRefOf(Index(WAKG, 0)),0)) { // if power gating enabled + if (LEqual(DeRefOf(Index(WAKG, 0)),1)) { // GPIO mode + \_SB.SGOV(DeRefOf(Index(WAKG, 2)),DeRefOf(Index(WAKG, 3))) + // \_SB.SHPO(DeRefOf(Index(WAKG, 2)), 0) // set gpio ownership to ACPI(0=ACPI mode, 1=GPIO mode) + Store(\_SB.GPC0(DeRefOf(Index(WAKG, 2))), Local1) + Or(Local1, 0x400000, Local1) + And(Local1, 0xFFFFFBFF, Local1) + \_SB.SPC0(DeRefOf(Index(WAKG, 2)), Local1) + } + } + + If (LEqual(DeRefOf(Index(SCLK,0)), 1)) { + Store(\_SB.GPC0(DeRefOf(Index(SCLK,1))), Local1) + And(Local1, 0xFFBFFFFF, Local1) + \_SB.SPC0(DeRefOf(Index(SCLK,1)), Local1) + } + + \_SB.SGOV(DeRefOf(Index(RSTG, 2)),DeRefOf(Index(RSTG, 3))) + + Store(0, BDQA) // Set BLKDQDA to 0 + Store(0, BPLL) // Set BLKPLLEN to 0 + + /// Set L23_Rdy to Detect Transition (L23R2DT) + Store(1, L23R) + Sleep(16) + Store(0, Local0) + /// Wait up to 12 ms for transition to Detect + While(L23R) { + If(Lgreater(Local0, 4)) // Debug - Wait for 5 ms + { + Break + } + Sleep(16) + Increment(Local0) + } + } + + Method(_OFF,0,Serialized) /// Turn off core power to PCIe Slot + { + Name(PCIA, 0) + + Switch(ToInteger(SLOT)) { + Case(1) { + ShiftRight(RPA1, 1, PCIA) + Or(0xE0000000, PCIA, PCIA) + } + Case(2) { + ShiftRight(RPA2, 1, PCIA) + Or(0xE0000000, PCIA, PCIA) + } + Case(3) { + ShiftRight(RPA3, 1, PCIA) + Or(0xE0000000, PCIA, PCIA) + } + Case(4) { + ShiftRight(RPA4, 1, PCIA) + Or(0xE0000000, PCIA, PCIA) + } + Case(5) { + ShiftRight(RPA5, 1, PCIA) + Or(0xE0000000, PCIA, PCIA) + } + Case(6) { + ShiftRight(RPA6, 1, PCIA) + Or(0xE0000000, PCIA, PCIA) + } + Default { + } + } + + // Dynamic Opregion needed to access registers when the controller is in D3 cold + OperationRegion(PX02,SystemMemory,PCIA,0x380) + Field(PX02,AnyAcc, NoLock, Preserve) + { + Offset(0x50), // LCTL - Link Control Register + L0SE, 1, // 0, L0s Entry Enabled + , 3, + LDIS, 1, + Offset(0xE2), // RPPGEN - Root Port Power Gating Enable + , 2, + L23E, 1, // 2, L23_Rdy Entry Request (L23ER) + L23R, 1, // 3, L23_Rdy to Detect Transition (L23R2DT) + Offset(0xF4), // BLKPLLEN + , 10, + BPLL, 1, + Offset(0x324), + , 3, + LEDM, 1, // PCIEDBG.DMIL1EDM + Offset(0x338), + , 26, + BDQA, 1 // BLKDQDA + } + /// Set L23_Rdy Entry Request (L23ER) + Store(1, L23E) + Sleep(16) + Store(0, Local0) + While(L23E) { + If (Lgreater(Local0, 4)) { + /// Debug - Wait for 5 ms + Break + } + Sleep(16) + Increment(Local0) + } + + Store(1, BDQA) // Set BLKDQDA to 1 + Store(1, BPLL) // Set BLKPLLEN to 1 + + if (LNotEqual(DeRefOf(Index(WAKG, 0)),0)) { + // if power gating enabled + if (LEqual(DeRefOf(Index(WAKG, 0)),1)) { + // GPIO mode + Store(\_SB.GPC0(DeRefOf(Index(WAKG, 2))), Local1) + Or(Local1, 0x400, Local1) + And(Local1, 0xFFBFFFFF, Local1) + \_SB.SPC0(DeRefOf(Index(WAKG, 2)), Local1) + } + } + + /// Assert Reset Pin + if (LNotEqual(DeRefOf(Index(RSTG, 0)),0)) { + // if reset pin enabled + if (LEqual(DeRefOf(Index(RSTG, 0)),1)) { + // GPIO mode + \_SB.SGOV(DeRefOf(Index(RSTG, 2)),Xor(DeRefOf(Index(RSTG, 3)),1)) + } + } + + + /// assert CLK_REQ MSK + if (LEqual(DeRefOf(Index(SCLK, 0)),1)) { + // if power gating enabled + Store(\_SB.GPC0(DeRefOf(Index(SCLK, 1))), Local1) + Or(Local1, 0x400000, Local1) + \_SB.SPC0(DeRefOf(Index(SCLK, 1)), Local1) + } + + /** @defgroup pcie_off PCIE _OFF method **/ + } // End of Method_OFF + } // End PXP + + Name(_PR0, Package(){PXP}) + Name(_PR3, Package(){PXP}) + + // + // _SxW, in Sx, the lowest power state supported to wake up the system + // _SxD, in Sx, the highest power state supported by the device + // If OSPM supports _PR3 (_OSC, Arg3[2]), 3 represents D3hot; 4 represents D3cold, otherwise 3 represents D3. + // + + Method (_S3D, 0, Serialized) + { + Return (0x2) + } + Method (_S3W, 0, Serialized) + { + Return (0x3) + } + Method (_S4D, 0, Serialized) + { + Return (0x2) + } + Method (_S4W, 0, Serialized) + { + Return (0x3) + } + + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtSata.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtSata.asl new file mode 100644 index 0000000000..f6b6f15659 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtSata.asl @@ -0,0 +1,216 @@ +/** @file + ACPI RTD3 SSDT table for BXT SATA + + Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + Method(_DSW, 3, Serialized) + { + } + + /// _S0W method returns the lowest D-state can be supported in state S0. + Method(_S0W, 0) + { + Return(4) // return 4 (D3cold) + } // End _S0W + + Method(_PR0) { + If (LAnd(LAnd(LAnd(And(RCG0, 0x01), 0x01), LGreaterEqual(\OSYS, 2012)), LEqual(PORT, 0))) { + // Return ODPR for ZPODD + Return(Package(){ODPR}) + } ElseIf (LAnd(LGreaterEqual(\OSYS, 2015), LEqual(\EMOD, 1))) { + If (CondRefOf(\_SB.MODS)) { + Return(Package(){\_SB.MODS}) + } + } Else { + If (CondRefOf(SPPR)) { + Return(Package(){SPPR}) + } + } + Return(Package() {}) + } + Method(_PR3) { + If (LAnd(LAnd(LAnd(And(RCG0, 0x01), 0x01), LGreaterEqual(\OSYS, 2012)), LEqual(PORT, 0))) { + // Return ODPR for ZPODD + Return(Package(){ODPR}) + } ElseIf (LAnd(LGreaterEqual(\OSYS, 2015), LEqual(\EMOD, 1))) { + If (CondRefOf(\_SB.MODS)) { + Return(Package(){\_SB.MODS}) + } + } Else { + If (CondRefOf(SPPR)) { + Return(Package(){SPPR}) + } + } + Return(Package() {}) + } + + PowerResource(SPPR, 0, 0) + { + Method(_STA) + { + If (LEqual(\EMOD, 1)) { + Return(0x01) + } Else { + Return(SPSA()) + } + } + + Method(_ON) { + If (LEqual(\EMOD, 1)) { + // Do nothing + } Else { + SPON() // _ON Method + Sleep(16) // Delay for power ramp. + } + } + + Method(_OFF) { + If (LEqual(\EMOD, 1)) { + // Do nothing + } Else { + SPOF() + } + } + } // end SPPR + + Name(OFTM, Zero) /// OFTM: Time returned by Timer() when the Power resource was turned OFF + Method(SPSA) { + + // check power control enable + If (LNotEqual(DeRefOf(Index(PWRG, 0)), 0)) { + // read power pin status + If (LEqual(DeRefOf(Index(PWRG, 0)),1)) { // GPIO mode + if (LEqual(\_SB.GGOV(DeRefOf(Index(PWRG, 2))), DeRefOf(Index(PWRG, 3)))) { + Return(0x01) + } Else { + Return(0x00) + } + } + } + Return(0x00) // disabled + } /// @defgroup sata_prt1_sta SATA Port 1 PowerResource _STA Method + + Method(SPON, 0) { + If (LNotEqual(^OFTM, Zero)) { /// if OFTM != 0 => Disk was turned OFF by asl + Divide(Subtract(Timer(), ^OFTM), 10000, , Local0) ///- Store Elapsed time in ms + Store(Zero, ^OFTM) ///- Reset OFTM to zero to indicate minimum 50ms requirement does not apply when _ON called next time + If (LLess(Local0, 50)) ///- Do not sleep if already past the delay requirement + { + Sleep(Subtract(50, Local0)) ///- Sleep 50ms - time elapsed + } + } + // drive power pin "ON" + if (LNotEqual(DeRefOf(Index(PWRG, 0)),0)) { // if power gating enabled + if (LEqual(DeRefOf(Index(PWRG, 0)),1)) { // GPIO mode + \_SB.SGOV(DeRefOf(Index(PWRG, 2)),DeRefOf(Index(PWRG, 3))) + } + } + } + + Method(SPOF, 0) { + + Add(\_SB.PCI0.SATA.MBR6, PBAR, Local0) + /// if S0Ix enabled + If (LEqual(S0ID, 1)) { + OperationRegion(PSTS, SystemMemory, Local0, 0x18) + Field(PSTS, DWordAcc, NoLock, Preserve) + { + Offset(0x0), + CMST, 1, //PxCMD.ST + CSUD, 1, //PxCMD.SUD + , 2, + CFRE, 1, //PxCMD.FRE + Offset(0x10), + SDET, 4, //PxSSTS.DET + Offset(0x14), + CDET, 4 //PxSCTL.DET + } + + // Execute offline flow only if Device detected and Phy not offline + If (LOr(LEqual(SDET, 1), LEqual(SDET, 3))) { + + ///- Clear ST (PxCMD.ST) + Store(0, CMST) // PBAR[0] + ///- Clear FRE + Store(0, CFRE) // PBAR[4] + ///- Clear SUD (PxCMD.SUD) + Store(0, CSUD) // PBAR[1] + ///- Set DET to 4 (PxSCTL.DET) + Store(4, CDET) // PBAR+0x14[3:0] + Sleep(16) + ///- Wait until PxSSTS.DET == 4 + While(LNotEqual(SDET, 4)){ + Sleep(16) + } + } + } // if S0Ix enabled + // drive power pin "OFF" + If (LNotEqual(DeRefOf(Index(PWRG, 0)),0)) { // if power gating enabled + if (LEqual(DeRefOf(Index(PWRG, 0)),1)) { // GPIO mode + \_SB.SGOV(DeRefOf(Index(PWRG, 2)),Xor(DeRefOf(Index(PWRG, 3)),1)) + } + } + + Store(Timer(), ^OFTM) /// Store time when Disk turned OFF(non-zero OFTM indicate minimum 50ms requirement does apply when _ON called next time) + } // end _OFF + + // + // Power Resource for RTD3 ZPODD + // + PowerResource(ODPR, 0, 0) + { + Method(_STA) + { + Return(ODSA()) + } + + Method(_ON) + { + ODON() // _ON Method + Sleep(800) // Delay for power ramp. + } + + Method(_OFF) + { + ODOF() // _OFF Method + } + + } // end PZPR + + Method(ODSA) + { + // check power control enable + // read power pin status + If (LEqual(\_SB.GGOV(N_GPIO_22), 0x01)) { + Return(0x01) + } Else { + Return(0x00) + } + } + + Method(ODON, 0) + { + // drive power pin "ON" + If (LAnd(LAnd(LAnd(And(RCG0, 0x01), 0x01), LGreaterEqual(\OSYS, 2012)), LEqual(PORT, 0))) { + Store (1, \_SB.GPO0.ODPW) + } + } + + Method(ODOF, 0) + { + // drive power pin "OFF" + If (LAnd(LAnd(LAnd(And(RCG0, 0x01), 0x01), LGreaterEqual(\OSYS, 2012)), LEqual(PORT, 0))) { + Store (0, \_SB.GPO0.ODPW) + } + } + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtUsb.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtUsb.asl new file mode 100644 index 0000000000..f4e168f6b3 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtUsb.asl @@ -0,0 +1,63 @@ +/** @file + Power resource and wake capability for USB ports + + Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + // + // Define _PR0, _PR3 PowerResource Package + // + Name (_PR0, Package(){UPPR}) + Name (_PR3, Package(){UPPR}) + + PowerResource(UPPR, 0, 0) + { + Method(_STA) + { + Return(0x01) + } + + Method(_ON) + { + } + + Method(_OFF) + { + } + } + + // + // _SxW, in Sx, the lowest power state supported to wake up the system + // _SxD, in Sx, the highest power state supported by the device + // If OSPM supports _PR3 (_OSC, Arg3[2]), 3 represents D3hot; 4 represents D3cold, otherwise 3 represents D3. + // + Method(_S0W, 0, Serialized) + { + Return(0x3) // return 3 (D3hot) + } + Method (_S3D, 0, Serialized) + { + Return (0x2) + } + Method (_S3W, 0, Serialized) + { + Return (0x3) + } + Method (_S4D, 0, Serialized) + { + Return (0x2) + } + Method (_S4W, 0, Serialized) + { + Return (0x3) + } + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtUsbWwan.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtUsbWwan.asl new file mode 100644 index 0000000000..787d7cd704 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3BxtUsbWwan.asl @@ -0,0 +1,90 @@ +/** @file + Power resource and wake capability for USB ports hosting WWAN module + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + // USB Port 3 power resource + + PowerResource(PX03, 0, 0) { + Name(WOFF, 0) // Last OFF Time stamp (WOFF): The time stamp of the last power resource _OFF method evaluation + + Method(_STA) + { + If (LEqual(\_SB.GGOV(NW_GPIO_78), 1)) { + Return(0x01) + } Else { + Return(0x00) + } + } + + Method(_ON, 0) /// _ON Method + { + If (LNotEqual(^WOFF, Zero)) { + Divide(Subtract(Timer(), ^WOFF), 10000, , Local0) // Store Elapsed time in ms, ignore remainder + If (LLess(Local0,100)) { // If Elapsed time is less than 100ms + Sleep(Subtract(100,Local0)) // Sleep for the remaining time + } + } + \_SB.SGOV(NW_GPIO_78,1) // set power pin to high + \_SB.SGOV(NW_GPIO_117,1) // set reset pin to high + } + + Method(_OFF, 0) /// _OFF Method + { + \_SB.SGOV(NW_GPIO_117,0) // set reset pin to low + \_SB.SGOV(NW_GPIO_78,0) // set power pin to low + + Store(Timer(), ^WOFF) // Start OFF timer here. + } + } // End PX03 + + Name(_PR0,Package(){PX03}) // Power Resource required to support D0 + Name(_PR2,Package(){PX03}) // Power Resource required to support D2 + Name(_PR3,Package(){PX03}) // Power Resource required to support D3 + + // + // WWAN Modem device with the same power resource as its composite parent device + // + Device (MODM) { + Name(_ADR, 0x3) + Name(_PR0,Package(){PX03}) // Power Resource required to support D0 + Name(_PR2,Package(){PX03}) // Power Resource required to support D2 + Name(_PR3,Package(){PX03}) // Power Resource required to support D3 + } + + // + // _SxW, in Sx, the lowest power state supported to wake up the system + // _SxD, in Sx, the highest power state supported by the device + // If OSPM supports _PR3 (_OSC, Arg3[2]), 3 represents D3hot; 4 represents D3cold, otherwise 3 represents D3. + // + Method(_S0W, 0, Serialized) + { + Return(0x3) // return 3 (D3hot) + } + Method (_S3D, 0, Serialized) + { + Return (0x2) + } + Method (_S3W, 0, Serialized) + { + Return (0x3) + } + Method (_S4D, 0, Serialized) + { + Return (0x2) + } + Method (_S4W, 0, Serialized) + { + Return (0x3) + } + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3Common.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3Common.asl new file mode 100644 index 0000000000..0e95dd8774 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/Rtd3Common.asl @@ -0,0 +1,91 @@ +/** @file + ACPI RTD3 SSDT table + + Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +External(\_SB.OSCO) +External(\_SB.PCI0, DeviceObj) + +External(\_SB.PCI0.RP01, DeviceObj) +External(\_SB.PCI0.RP02, DeviceObj) +External(\_SB.PCI0.RP03, DeviceObj) +External(\_SB.PCI0.RP04, DeviceObj) +External(\_SB.PCI0.RP05, DeviceObj) +External(\_SB.PCI0.RP06, DeviceObj) +External(\_SB.PCI0.RP01.VDID) +External(\_SB.PCI0.RP02.VDID) +External(\_SB.PCI0.RP03.VDID) +External(\_SB.PCI0.RP04.VDID) +External(\_SB.PCI0.RP05.VDID) +External(\_SB.PCI0.RP06.VDID) +External(\_SB.PCI0.SATA, DeviceObj) +External(\_SB.PCI0.SATA.PRT0, DeviceObj) +External(\_SB.PCI0.SATA.PRT1, DeviceObj) + +External(\_SB.PCI0.XHC, DeviceObj) +External(\_SB.PCI0.XHC.RHUB, DeviceObj) + +External(\_SB.PCI0.XHC.RHUB.HS01, DeviceObj) +External(\_SB.PCI0.XHC.RHUB.HS02, DeviceObj) +External(\_SB.PCI0.XHC.RHUB.HS03, DeviceObj) +External(\_SB.PCI0.XHC.RHUB.HS04, DeviceObj) +External(\_SB.PCI0.XHC.RHUB.HS05, DeviceObj) +External(\_SB.PCI0.XHC.RHUB.HS06, DeviceObj) +External(\_SB.PCI0.XHC.RHUB.HS07, DeviceObj) +External(\_SB.PCI0.XHC.RHUB.HS08, DeviceObj) + +External(\_SB.PCI0.XHC.RHUB.SSP1, DeviceObj) +External(\_SB.PCI0.XHC.RHUB.SSP2, DeviceObj) +External(\_SB.PCI0.XHC.RHUB.SSP3, DeviceObj) +External(\_SB.PCI0.XHC.RHUB.SSP4, DeviceObj) +External(\_SB.PCI0.XHC.RHUB.SSP5, DeviceObj) +External(\_SB.PCI0.XHC.RHUB.SSP6, DeviceObj) +External(\_SB.PCI0.XHC.RHUB.SSP7, DeviceObj) + +External(\_SB.PCI0.XDCI, DeviceObj) + +External(\_SB.PCI0.SDHA, DeviceObj) +External(\_SB.PCI0.SDIO, DeviceObj) + +External(\_SB.PCI0.PWM, DeviceObj) +External(\_SB.PCI0.I2C0, DeviceObj) +External(\_SB.PCI0.I2C1, DeviceObj) +External(\_SB.PCI0.I2C2, DeviceObj) +External(\_SB.PCI0.I2C3, DeviceObj) +External(\_SB.PCI0.I2C4, DeviceObj) +External(\_SB.PCI0.I2C5, DeviceObj) +External(\_SB.PCI0.I2C6, DeviceObj) +External(\_SB.PCI0.I2C7, DeviceObj) +External(\_SB.PCI0.SPI1, DeviceObj) +External(\_SB.PCI0.SPI2, DeviceObj) +External(\_SB.PCI0.SPI3, DeviceObj) +External(\_SB.PCI0.URT1, DeviceObj) +External(\_SB.PCI0.URT2, DeviceObj) +External(\_SB.PCI0.URT3, DeviceObj) +External(\_SB.PCI0.URT4, DeviceObj) + +External(\GPRW, MethodObj) +External(P8XH, MethodObj) +External(XDST, IntObj) + +// +// Externs common to ULT0RTD3.asl and FFRDRTD3.asl and exclude for BRRTD3.asl +// + +// GPIO methods +External(\_SB.GPC0, MethodObj) +External(\_SB.SPC0, MethodObj) + +// IO expander methods +// RTD3 devices and variables + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/RvpRtd3.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/RvpRtd3.asl new file mode 100644 index 0000000000..6ce5b22afa --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/SsdtRtd3/RvpRtd3.asl @@ -0,0 +1,841 @@ +/** @file + ACPI RTD3 SSDT table for APLK + + Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +DefinitionBlock ( + "Rtd3.aml", + "SSDT", + 2, + "AcpiRef", + "RVPRtd3", + 0x1000 + ) +{ +External(RTD3, IntObj) +External(EMOD, IntObj) +External(RCG0, IntObj) +External(RPA1, IntObj) +External(RPA2, IntObj) +External(RPA3, IntObj) +External(RPA4, IntObj) +External(RPA5, IntObj) +External(RPA6, IntObj) +External(\_SB.GPO0.AVBL, IntObj) +External(\_SB.GPO0.ODPW, IntObj) +External(\_SB.GGOV, MethodObj) +External(\_SB.SGOV, MethodObj) +External(OSYS) +External(HGEN) +External(S0ID) + +Include ("BxtPGpioDefine.asl") +Include ("Rtd3Common.asl") + +// +// PCIe root ports - START +// + /// + /// PCIe RTD3 - SLOT#1 + /// + Scope(\_SB.PCI0.RP01) + { + // reset pin = N_GPIO_13 + // power pin = N_GPIO_17 + // wake pin = SW_GPIO_207 + // CLK_REQ = Mask Enable of Mapped CLKREQ# for CLKOUT_SRC2 (MSKCRQSRC2): + Name(SLOT, 1) // port #1 + + Name(RSTG, Package() { + 0, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander) + 0, // IOEX # + N_GPIO_13, // GPIO pad #/IOEX pin # + 1 // reset pin de-assert polarity + }) + Name(PWRG, Package() { + 0, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander) + 0, // IOEX # + N_GPIO_17, // GPIO pad #/IOEX pin # + 1 // power on polarity + }) + Name(WAKG, Package() { + 0, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander) + 0, // IOEX # + SW_GPIO_207, // MSKCRQSRC2 + 0 // wake en polarity + }) + Name(SCLK, Package() { + 0, // 0-disable, 1-enable + W_GPIO_211, // MSKCRQSRC2 + 0 // assert polarity, ICC should be LOW-activated + }) + + Include("Rtd3BxtPcie.asl") + } + + /// + /// PCIe RTD3 - SLOT#2 + /// + Scope(\_SB.PCI0.RP02) + { + Name (PCA2, 0) + // reset pin = N_GPIO_15 + // power pin = N_GPIO_17 + // wake pin = SW_GPIO_208 + // CLK_REQ = Mask Enable of Mapped CLKREQ# for CLKOUT_SRC1 (MSKCRQSRC1): + Name(SLOT, 2) // port #2 + + Name(RSTG, Package() { + 1, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander) + 0, // IOEX # + N_GPIO_15, // GPIO pad #/IOEX pin # + 1 // reset pin de-assert polarity + }) + Name(PWRG, Package() { + 0, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander) + 0, // IOEX # + N_GPIO_17, // GPIO pad #/IOEX pin # + 1 // power on polarity + }) + Name(WAKG, Package() { + 0, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander) + 0, // IOEX # + SW_GPIO_208, // GPIO pad #/IOEX pin # + 1 // wake en polarity + }) + Name(SCLK, Package() { + 1, // 0-disable, 1-enable + W_GPIO_212, // MSKCRQSRC1 + 0 // assert polarity, ICC should be LOW-activated + }) + + Include("Rtd3BxtPcie.asl") + } + + /// + /// PCIe RTD3 - SLOT#3 + /// + If (LEqual (HGEN, 0)) { + Scope(\_SB.PCI0.RP03) + { + Name (PCA3, 0) + // reset pin = W_GPIO_152 + // power pin = N_GPIO_19 + // wake pin = SW_GPIO_205 + // CLK_REQ = W_GPIO_209 + Name(SLOT, 3) // port #3 + + Name(RSTG, Package() { + 1, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander) + 0, // IOEX # + W_GPIO_152, // GPIO pad #/IOEX pin # + 1 // reset pin de-assert polarity + }) + Name(PWRG, Package() { + 1, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander) + 0, // IOEX # + N_GPIO_19, // GPIO pad #/IOEX pin # + 1 // power on polarity + }) + Name(WAKG, Package() { + 1, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander) + 0, // IOEX # + SW_GPIO_205, // GPIO pad #/IOEX pin # + 1 // wake en polarity + }) + Name(SCLK, Package() { + 1, // 0-disable, 1-enable + W_GPIO_209, // MSKCRQSRCx + 0 // assert polarity, ICC should be LOW-activated + }) + Include("Rtd3BxtPcie.asl") + } + } + + /// + /// PCIe RTD3 - SLOT#4 + /// + Scope(\_SB.PCI0.RP04) + { + Name (PCA4, 0) + // reset pin = none + // power pin = none + // wake pin = none + // CLK_REQ = Mask Enable of Mapped CLKREQ# for CLKOUT_SRC5 (MSKCRQSRC5) + Name(SLOT, 4) ///- Slot #4 + + Name(RSTG, Package() { + 0, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander) + 0, // IOEX # + 0, // GPIO pad #/IOEX pin # + 0 // reset pin de-assert polarity + }) + Name(PWRG, Package() { + 0, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander) + 0, // IOEX # + 0, // GPIO pad #/IOEX pin # + 0 // power on polarity + }) + Name(WAKG, Package() { + 0, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander) + 0, // IOEX # + 0, // GPIO pad #/IOEX pin # + 0 // wake en polarity + }) + Name(SCLK, Package() { + 0, // 0-disable, 1-enable + 0, // MSKCRQSRC5 + 0 // assert polarity, ICC should be LOW-activated + }) + + Include("Rtd3BxtPcie.asl") + } + + /// + /// PCIe RTD3 - SLOT#5 + /// + Scope(\_SB.PCI0.RP05) + { + Name (PCA5, 0) + // reset pin = none + // power pin = none + // wake pin = none + // CLK_REQ = Mask Enable of Mapped CLKREQ# for CLKOUT_SRC4 (MSKCRQSRC4) + Name(SLOT, 5) ///- port #5 + + Name(RSTG, Package() { + 0, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander) + 0, // IOEX # + 0, // GPIO pad #/IOEX pin # + 0 // reset pin de-assert polarity + }) + Name(PWRG, Package() { + 0, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander) + 0, // IOEX # + 0, // GPIO pad #/IOEX pin # + 0 // power on polarity + }) + Name(WAKG, Package() { + 0, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander) + 0, // IOEX # + 0, // GPIO pad #/IOEX pin # + 0 // wake en polarity + }) + Name(SCLK, Package() { + 0, // 0-disable, 1-enable + 0, // MSKCRQSRC4 + 0 // assert polarity, ICC should be LOW-activated + }) + + Include("Rtd3BxtPcie.asl") + } + + /// + /// PCIe RTD3 - SLOT#6 + /// + Scope(\_SB.PCI0.RP06) + { + Name (PCA6, 0) + // reset pin = none + // power pin = none + // wake pin = none + // CLK_REQ = Mask Enable of Mapped CLKREQ# for CLKOUT_SRC4 (MSKCRQSRC4) + Name(SLOT, 6) ///- port #6 + + Name(RSTG, Package() { + 0, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander) + 0, // IOEX # + 0, // GPIO pad #/IOEX pin # + 0 // reset pin de-assert polarity + }) + Name(PWRG, Package() { + 0, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander) + 0, // IOEX # + 0, // GPIO pad #/IOEX pin # + 0 // power on polarity + }) + Name(WAKG, Package() { + 0, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander) + 0, // IOEX # + 0, // GPIO pad #/IOEX pin # + 0 // wake en polarity + }) + Name(SCLK, Package() { + 0, // 0-disable, 1-enable + 0, // MSKCRQSRC4 + 0 // assert polarity, ICC should be LOW-activated + }) + + Include("Rtd3BxtPcie.asl") + } +// +// PCIe root ports - END +// + +// +// SATA - START +// + + Scope(\_SB.PCI0.SATA) { + + OperationRegion (PMCS, PCI_Config, 0x74, 0x4) + Field (PMCS, WordAcc, NoLock, Preserve) { + PMSR, 32, // 0x74, PMCSR - Power Management Control and Status + } + + /// _PS0 Method for SATA HBA + Method(_PS0,0,Serialized) + { + + } + + /// _PS3 Method for SATA HBA + Method(_PS3,0,Serialized) + { + } + + /// Define SATA PCI Config OperationRegion + OperationRegion(SMIO,PCI_Config,0x24,4) + Field(SMIO,AnyAcc, NoLock, Preserve) { + Offset(0x00), ///- SATA MABR6 + MBR6, 32, ///- SATA ABAR + } + + Scope(PRT0) { + // Define _PR0, _PR3 PowerResource Package + // P0 command port = ABAR + 0x118 + // power pin = N_GPIO_22 + Name(PORT, 0) + Name(PBAR, 0x118) // port0 command port address + Name(PWRG, Package() { + 1, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander) + 0, // GPIO group #/IOEX # + N_GPIO_22, // GPIO pad #/IOEX pin # + 1 // power on polarity + }) + Include("Rtd3BxtSata.asl") + } // end device(PRT0) + + Scope(PRT1) { + // Define _PR0, _PR3 PowerResource Package + // P1 command port = ABAR + 0x198 + // power pin = none + Name(PORT, 1) + Name(PBAR, 0x198) // port1 command port address + Name(PWRG, Package() { + 0, // 0-disable, 1-enable GPIO, 2-enable IOEX(IO Expander) + 0, // GPIO group #/IOEX # + 0, // GPIO pad #/IOEX pin # + 0 // power on polarity + }) + Include("Rtd3BxtSata.asl") + } // end device(PRT1) + + /// + /// _DSM Device Specific Method supporting AHCI DEVSLP + /// + /// Arg0: UUID Unique function identifier \n + /// Arg1: Integer Revision Level \n + /// Arg2: Integer Function Index \n + /// Arg3: Package Parameters \n + /// + /// Variables: + Name(DRV, 0) /// Storage for _DSM Arg3 parameter 0 + Name(PWR, 0) /// Storage for _DSM Arg3 parameter 1 + + Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) { + + /// Check UUID of _DSM defined by Microsoft + If (LEqual(Arg0, ToUUID ("E4DB149B-FCFE-425b-A6D8-92357D78FC7F"))) { + /// + /// Switch by function index + /// + Switch (ToInteger(Arg2)) { + Case (0) { /// case 0: + ///- Standard query - A bitmask of functions supported + ///- Supports function 0-3 + Return(0x0f) + } + Case (1) { /// case 1: + ///- Query Device IDs (Addresses) of children where drive power and/or DevSleep are supported. + ///- SATA HBA provides autonomous link (DevSleep) support, return a package of 0 elements + Return( Package(){}) ///- SATA HBA provides native DevSleep + } + Case (2) { /// Case 2: Control power to device. + Store(ToInteger(DerefOf(Index(Arg3, Zero))), DRV) + Store(ToInteger(DerefOf(Index(Arg3, One))), PWR) + + Switch(ToInteger(DRV)){ + Case (0x0000FFFF){ + If (LAnd(LAnd(And(RCG0, 0x01), 0x01), LGreaterEqual(\OSYS, 2012))) { + ///- Turn on drive and link power to all drives. Note that even though + If(PWR){ // Applying Power + \_SB.PCI0.SATA.PRT0.ODPR._ON() ///- apply power to port 0 + } + } Else { + If(PWR){ // Applying Power + \_SB.PCI0.SATA.PRT0.SPPR._ON() ///- apply power to port 0 + } + } + } + } //Switch(DRV) + Return (0) + } //Case (2) + Case (3){ /// Case 3: Current status of Device/Link of Port + Store(ToInteger(DerefOf(Index(Arg3, Zero))), DRV) + Switch(ToInteger(DRV)){ /// Check for SATA port + Case (0x0000FFFF) { ///- SATA Port 0 + ///- Bit0 => Device power state + If (LAnd(LAnd(And(RCG0, 0x01), 0x01), LGreaterEqual(\OSYS, 2012))) { + If(LEqual(\_SB.PCI0.SATA.PRT0.ODPR._STA(), 0)){ + Store(0, Local0) + }Else{ + Store(1, Local0) + } + } Else { + ///- Bit0 => Device power state + If (LEqual(\_SB.PCI0.SATA.PRT0.SPPR._STA(), 0)){ + Store(0, Local0) + } Else { + Store(1, Local0) + } + } + Return (Local0) + } + Case (0x0001FFFF){ ///- SATA Port 1 + ///- Bit0 => Device power state + If (LEqual(\_SB.PCI0.SATA.PRT1.SPPR._STA(), 0)) { + Store(0, Local0) + } Else { + Store(1, Local0) + } + Return (Local0) + } + Default { ///- Invalid SATA Port - error + Return (Ones) + } + } + } + Default { + Return (0) + } + } + } Else { // UUID does not match + Return (0) + } + } /// @defgroup sata_dsm SATA _DSM Method + + } //Scope(\_SB.PCI0.SATA) +// +// SATA - END +// + + Scope(\_SB.PCI0.XHC.RHUB) { //USB XHCI RHUB + // + // No specific power control (GPIO) to USB connectors (p2/p4/p5), + // declare power resource with null functions and specify its wake ability + // Please refer to ACPI 5.0 spec CH7.2 + // + Scope (HS02) { + Name(PORT, 2) + Include ("Rtd3BxtUsb.asl") + } + Scope (SSP2) { + Name(PORT, 10) + Include ("Rtd3BxtUsb.asl") + } + + Scope (HS04) { + Name(PORT, 4) + Include ("Rtd3BxtUsb.asl") + } + Scope (SSP4) { + Name(PORT, 12) + Include ("Rtd3BxtUsb.asl") + } + + Scope (HS05) { + Name(PORT, 5) + Include ("Rtd3BxtUsb.asl") + } + Scope (SSP5) { + Name(PORT, 13) + Include ("Rtd3BxtUsb.asl") + } + + /// + /// WWAN RTD3 support, associate _PR0, PR2, PR3 for USB High speed Port 3 + Scope (HS03) { + Name(PORT, 3) + Include ("Rtd3BxtUsbWwan.asl") + } + + } // RHUB + + Scope(\_SB){ + PowerResource(SDPR, 0, 0) { + Name(_STA, One) + Method(_ON, 0, Serialized) { + + } + + Method(_OFF, 0, Serialized) { + + } + + } //End of PowerResource(SDPR, 0, 0) + } //End of Scope(\_SB) + + Scope(\_SB.PCI0.SDHA) + { + + Name(_PR0, Package(){SDPR}) // TBD + Name(_PR3, Package(){SDPR}) // TBD + } //Scope(\_SB.PCI0.SDHA) + + Scope(\_SB.PCI0.SDIO) + { + + Name(_PR0, Package(){SDPR}) // TBD + Name(_PR3, Package(){SDPR}) // TBD + } //Scope(\_SB.PCI0.SDIO) + + Scope(\_SB) + { + // + // Dummy power resource for USB D3 cold support + // + PowerResource(USBC, 0, 0) + { + Method(_STA) { Return (0x1) } + Method(_ON) {} + Method(_OFF) {} + } + } + + Scope(\_SB.PCI0.XDCI) + { + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + Return (Zero) + } + + Method (_PR3, 0, NotSerialized) // _PR3: Power Resources for D3hot + { + Return (Package (0x01) + { + USBC // return dummy package + }) + } + + OperationRegion (PMCS, PCI_Config, 0x74, 0x4) + Field (PMCS, WordAcc, NoLock, Preserve) { + PMSR, 32, // 0x74, PMCSR - Power Management Control and Status + } + + Method (_PS0, 0, NotSerialized) { // _PS0: Power State 0 + } + + Method (_PS3, 0, NotSerialized) { // _PS3: Power State 3 + // + // dummy read PMCSR + // + + Store (PMSR, Local0) + And (Local0, 1, Local0) // Dummy operation on Local0 + } + } // Scope(\_SB.PCI0.XDCI) + +// +// XDCI - end +// + +//Power Resource for Audio Codec + Scope(\_SB.PCI0) + { + PowerResource(PAUD, 0, 0) { + + /// Namespace variable used: + Name(PSTA, One) /// PSTA: Physical Power Status of Codec 0 - OFF; 1-ON + Name(ONTM, Zero) /// ONTM: 0 - Not in Speculative ON ; Non-Zero - elapsed time in Nanosecs after Physical ON + + Name(_STA, One) /// _STA: PowerResource Logical Status 0 - OFF; 1-ON + + ///@defgroup pr_paud Power Resource for onboard Audio CODEC + + Method(_ON, 0){ /// _ON method \n + + Store(One, _STA) ///- Set Logocal power state + PUAM() ///- Call PUAM() to tansition Physical state to match current logical state + ///@addtogroup pr_paud + } // End _ON + + Method(_OFF, 0){ /// _OFF method \n + + Store(Zero, _STA) ///- Set the current power state + PUAM() ///- Call PUAM() to tansition Physical state to match current logical state + ///@addtogroup pr_paud + } // End _OFF + + /// PUAM - Power Resource User Absent Mode for onboard Audio CODEC + /// Arguments: + /// + /// Uses: + /// _STA - Variable updated by Power Resource _ON/_OFF methods \n + /// \\UAMS - Variable updated by GUAM method to show User absent present \n + /// ONTM - Local variable to store ON time during Speculative ON \n + /// ______________________________ + // | Inputs | Outputs | + // ______________________________ + // | _STA | \UAMS | GPIO | ONTM | + // ______________________________ + // | 1 | 0 | ON | !0 | + // | 1 | !0 | ON | !0 | + // | 0 | 0 | ON | !0 | + // | 0 | !0 | OFF | 0 | + // ______________________________ + /** + +
Inputs Output +
_STA \\UAMS GPIO ONTM +
1 0 ON !0 +
1 !0ON !0 +
0 0 ON !0 +
0 !0OFF 0 +
+ **/ + ///@addtogroup pr_paud_puam + Method(PUAM, 0, Serialized) + { + If (LEqual(^_STA, Zero)) { + } Else { /// New state = ON (_STA=1) or (_STA=0 and \UAMS=0) + } + } //PUAM + } //PAUD + } //Scope(\_SB.PCI0) +//Power Resource for Audio Codec End + +// I2C1 - TouchPanel Power control + +//Serial IO End + + // Modern Standby N:1 Power Resource definition. Place Holder. + If (LEqual(\EMOD, 1)) { + Scope(\_SB){ + Name(GBPS, 0) // Power state flag for Modern Standby. Initial value = 1 (On). + PowerResource(MODS, 0, 0){ /// Modern Standby Power Resource + + Method(_STA) { /// _STA method + If (LGreaterEqual(OSYS, 2015)) { + Return(GBPS) + } + Return(0) + } + + Method(_ON, 0) { /// _ON Method + If (LGreaterEqual(OSYS, 2015)) { + \_SB.PCI0.SATA.PRT0.SPON() + Store(1, GBPS) // Indicate devices are ON + } + } + + Method(_OFF, 0) { /// _OFF Method + If (LGreaterEqual(OSYS, 2015)) { + \_SB.PCI0.SATA.PRT0.SPOF() + Store(0, GBPS) + } + } + } // End MODS + } // \_SB + } // End If ((LEqual(EMOD, 1)) + + Scope(\_SB.PCI0) { + Method(LPD3, 0, Serialized) { + // + // Memory Region to access to the PCI Configuration Space + // and dummy read PMCSR + // + OperationRegion (PMCS, PCI_Config, 0x84, 0x4) + Field (PMCS, WordAcc, NoLock, Preserve) { + PMSR, 32, // 0x84, PMCSR - Power Management Control and Status + } + // + // Dummy PMCSR read + // + Store (PMSR, Local0) + And (Local0, 1, Local0) // Dummy operation on Local0 + } + + PowerResource (LSPR, 0, 0) { + // + // LPSS Power Resource + // + Name (_STA, One) + Method (_ON, 0, Serialized) { + + } + + Method (_OFF, 0, Serialized) { + + } + } //End of PowerResource(SDPR, 0, 0) + } + + Scope(\_SB.PCI0.PWM) + { + // + // Dummy Power Resource declaration + // + Name(_PR0, Package(){LSPR}) // TBD + Name(_PR3, Package(){LSPR}) // TBD + Method (_PS0) { } + Method (_PS3) {LPD3 ()} + } //Scope(\_SB.PCI0.PWM) + + Scope(\_SB.PCI0.I2C0) + { + Name(_PR0, Package(){LSPR}) // TBD + Name(_PR3, Package(){LSPR}) // TBD + Method (_PS0) { } + Method (_PS3) {LPD3 ()} + } //Scope(\_SB.PCI0.I2C0) + + Scope(\_SB.PCI0.I2C1) + { + // + // Dummy Power Resource declaration + // + Name(_PR0, Package(){LSPR}) // TBD + Name(_PR3, Package(){LSPR}) // TBD + Method (_PS0) { } + Method (_PS3) {LPD3 ()} + } //Scope(\_SB.PCI0.I2C1) + + Scope(\_SB.PCI0.I2C2) + { + Name(_PR0, Package(){LSPR}) // TBD + Name(_PR3, Package(){LSPR}) // TBD + Method (_PS0) { } + Method (_PS3) {LPD3 ()} + } //Scope(\_SB.PCI0.I2C2) + + Scope(\_SB.PCI0.I2C3) + { + // + // Dummy Power Resource declaration + // + Name(_PR0, Package(){LSPR}) // TBD + Name(_PR3, Package(){LSPR}) // TBD + Method (_PS0) { } + Method (_PS3) {LPD3 ()} + } //Scope(\_SB.PCI0.I2C3) + + Scope(\_SB.PCI0.I2C4) + { + Name(_PR0, Package(){LSPR}) // TBD + Name(_PR3, Package(){LSPR}) // TBD + Method (_PS0) { } + Method (_PS3) {LPD3 ()} + } //Scope(\_SB.PCI0.I2C4) + + Scope(\_SB.PCI0.I2C5) + { + // + // Dummy Power Resource declaration + // + Name(_PR0, Package(){LSPR}) // TBD + Name(_PR3, Package(){LSPR}) // TBD + Method (_PS0) { } + Method (_PS3) {LPD3 ()} + } //Scope(\_SB.PCI0.I2C5) + + Scope(\_SB.PCI0.I2C6) + { + Name(_PR0, Package(){LSPR}) // TBD + Name(_PR3, Package(){LSPR}) // TBD + Method (_PS0) { } + Method (_PS3) {LPD3 ()} + } //Scope(\_SB.PCI0.I2C6) + + Scope(\_SB.PCI0.I2C7) + { + // + // Dummy Power Resource declaration + // + Name(_PR0, Package(){LSPR}) // TBD + Name(_PR3, Package(){LSPR}) // TBD + Method (_PS0) { } + Method (_PS3) {LPD3 ()} + } //Scope(\_SB.PCI0.I2C7) + + Scope(\_SB.PCI0.SPI1) + { + Name(_PR0, Package(){LSPR}) // TBD + Name(_PR3, Package(){LSPR}) // TBD + Method (_PS0) { } + Method (_PS3) {LPD3 ()} + } //Scope(\_SB.PCI0.SPI1) + + Scope(\_SB.PCI0.SPI2) + { + // + // Dummy Power Resource declaration + // + Name(_PR0, Package(){LSPR}) // TBD + Name(_PR3, Package(){LSPR}) // TBD + Method (_PS0) { } + Method (_PS3) {LPD3 ()} + } //Scope(\_SB.PCI0.SPI2) + + Scope(\_SB.PCI0.SPI3) + { + Name(_PR0, Package(){LSPR}) // TBD + Name(_PR3, Package(){LSPR}) // TBD + Method (_PS0) { } + Method (_PS3) {LPD3 ()} + } //Scope(\_SB.PCI0.SPI3) + + Scope(\_SB.PCI0.URT1) + { + Name(_PR0, Package(){LSPR}) // TBD + Name(_PR3, Package(){LSPR}) // TBD + Method (_PS0) { } + Method (_PS3) {LPD3 ()} + } //Scope(\_SB.PCI0.URT1) + + Scope(\_SB.PCI0.URT2) + { + Name(_PR0, Package(){LSPR}) // TBD + Name(_PR3, Package(){LSPR}) // TBD + Method (_PS0) { } + Method (_PS3) { LPD3 () } + } //Scope(\_SB.PCI0.URT2) + + Scope(\_SB.PCI0.URT3) + { + Name(_PR0, Package(){LSPR}) // TBD + Name(_PR3, Package(){LSPR}) // TBD + Method (_PS0) { } + Method (_PS3) {LPD3 ()} + } //Scope(\_SB.PCI0.URT3) + + Scope(\_SB.PCI0.URT4) + { + Name(_PR0, Package(){LSPR}) // TBD + Name(_PR3, Package(){LSPR}) // TBD + Method (_PS0) { } + Method (_PS3) {LPD3 ()} + } //Scope(\_SB.PCI0.URT4) + +} // End SSDT + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/THERMAL.ASL b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/THERMAL.ASL new file mode 100644 index 0000000000..fcba18c153 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/THERMAL.ASL @@ -0,0 +1,201 @@ +/** @file + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(\_TZ) +{ + // + // Memory window to MCHBAR+7000h. + // + OperationRegion (MBAR, SystemMemory, Add(ShiftLeft(\_SB.PCI0.VLVC.MHBR,15),0x7000), 0x100) + Field (MBAR, ByteAcc, NoLock, Preserve) + { + Offset (0x1C), // P_CR_PKG_THERM_STATUS_0_0_0_MCHBAR (MCHBAR+0x701C) + , 1, // THRESHOLD1_STATUS[0] + , 1, // THRESHOLD1_LOG[1] + , 1, // THRESHOLD2_STATUS[2] + , 1, // THRESHOLD2_LOG[3] + , 1, // CRITICAL_THERMAL_EVENT_STATUS[4] + , 1, // CRITICAL_THERMAL_EVENT_LOG[5] + , 10, // RESERVED[15:6] + PKGT, 8, // TEMPERATURE[23:16] + } + + // Notes: + // 1) WIN2K strictly uses interrupt driven thermal events. + // 2) Temperature values are stored in tenths of Kelvin to eliminate the decimal place. + // 3) Kelvin = Celsius + 273.2. + // 4) All temperature must be >= 289K. + + // Flag to indicate Legacy thermal control. + // 1 = Legacy thermal control + // 0 = other thermal control, like DPTF + Name(LEGA, 1) // for Active Policy + Name(LEGP, 1) // for Passive Policy + Name(LEGC, 1) // for Critical Policy + + // Fan 0 = Package Processor Fan. + + PowerResource(FN00,0,0) + { + // Return Virtual Fan 0 status. + // + Method(_STA,0,Serialized) + { + Return(0x0F) + } + + Name(FANS,0) // Fan State: 1=ON, 0=OFF + + Method(FCTL,1,Serialized) + { + + } + + Method(_ON,0,Serialized) + { + // If EC access is enabled. + If (\_TZ.LEGA) { + Store(1,FANS) // save fan state as on + FCTL(100) + } + } + + Method(_OFF,0,Serialized) + { + // If EC access is enabled. + If (\_TZ.LEGA) { + Store(0,FANS) // save fan state as off + FCTL(0) + } + } + } + + // Associate Virtual Fan 0 Power Resource with the FAN0 Device. + // + Device(FAN0) + { + Name(_HID, EISAID("PNP0C0B")) + Name(_UID,0) + Name(_PR0, Package(1){FN00}) + } + + // Thermal Zone 1 = DTS Thermal Zone. + // + ThermalZone(TZ01) + { + // Return the temperature at which the OS initiates Active Cooling. + // + Method(_AC0,0,Serialized) + { + If (LEqual(\_TZ.LEGA,0)) { Return(Add(2732,Multiply(210,10)))} // 210 degree C + Return(Add(2732,Multiply(ACTT,10))) + } + + // Returns the Device to turn on when _ACx is exceeded. + // + Name(_AL0, Package(1){FAN0}) + + // Return the temperature at which the OS must perform a Critcal Shutdown. + // + Method(_CRT,0,Serialized) + { + If (LEqual(\_TZ.LEGC,0)) { Return(Add(2732,Multiply(210,10)))} // 210 degree C + Return(Add(2732,Multiply(\CRTT,10))) + } + + // Notifies ASL Code the current cooling mode. + // 0 - Active cooling + // 1 - Passive cooling + // + Method(_SCP,1,Serialized) + { + Store(Arg0,\CTYP) + } + + // _TMP (Temperature) + // + // Return the highest of the CPU temperatures to the OS. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the current temperature of the thermal zone (in tenths of degrees Kelvin) + // + Method(_TMP,0,Serialized) + { + // + // DTS Enabled Case + // + If (DTSE) { + // + // If DTS support is enabled, simply return the + // higher of the two DTS Temperatures. + If (LGreaterEqual(DTS1, DTS2)) { + Return(Add(2732, Multiply(DTS1, 10))) + } + Return(Add(2732, Multiply(DTS2, 10))) + } + // + // Max Platform temperature returned by EC + // + Else{ + Return (Add(2732,Multiply(PKGT,10))) // this depends on EC sending a SCI every second to simulate polling. + } + } // End of _TMP + + // Return the Processor(s) used for Passive Cooling. + // + Method(_PSL,0,Serialized) + { + If (LEqual(MPEN, 4)) { + // CMP - Throttling controls all four logical CPUs. + Return(Package(){\_PR.CPU0,\_PR.CPU1,\_PR.CPU2,\_PR.CPU3}) + } + If (MPEN) { + // CMP - Throttling controls both CPUs. + Return(Package(){\_PR.CPU0,\_PR.CPU1}) + } + Return(Package(){\_PR.CPU0}) + } + + // Returns the temperature at which the OS initiates CPU throttling. + // + Method(_PSV,0,Serialized) + { + If (LEqual(\_TZ.LEGP,0)){ Return(Add(2732,Multiply(110,10)))} // 110 degree C + Return(Add(2732,Multiply(\PSVT,10))) + } + + // Returns TC1 value used in the passive cooling formula. + // + Method(_TC1,0,Serialized) + { + Return(\TC1V) + } + + // Returns TC2 value used in the passive cooling formula. + // + Method(_TC2,0,Serialized) + { + Return(\TC2V) + } + + // Returns the sampling period used in the passive cooling formula. + // + Method(_TSP,0,Serialized) + { + Return(\TSPV) + } + + }// end ThermalZone(TZ01) +} // end Scope(\_TZ) diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/UsbSbd.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/UsbSbd.asl new file mode 100644 index 0000000000..eb18763a90 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/UsbSbd.asl @@ -0,0 +1,68 @@ +/** @file + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// +// _DSM : Device Specific Method supporting USB Sideband Deferring function +// +// Arg0: UUID Unique function identifier +// Arg1: Integer Revision Level +// Arg2: Integer Function Index +// Arg3: Package Parameters +// +Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) +{ + If (LEqual(Arg0, ToUUID ("A5FC708F-8775-4BA6-BD0C-BA90A1EC72F8"))) { + // + // Switch by function index + // + Switch (ToInteger(Arg2)) + { + // + // Standard query - A bitmask of functions supported + // Supports function 0-2 + // + Case (0) + { + if (LEqual(Arg1, 1)) { // test Arg1 for the revision + Return (Buffer () {0x07}) + } else { + Return (Buffer () {0}) + } + } + // + // USB Sideband Deferring Support + // 0: USB Sideband Deferring not supported on this device + // 1: USB Sideband Deferring supported + // + Case (1) + { + if (LEqual(SDGV,0xFF)) { // check for valid GPE vector + Return (0) + } else { + Return (1) + } + } + // + // GPE Vector + // Return the bit offset within the GPE block of the GPIO (HOST_ALERT) driven by this device + // + Case (2) + { + Return (SDGV) + } + } + } + + Return (0) +} + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/UsbTypeC/UsbTypeC.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/UsbTypeC/UsbTypeC.asl new file mode 100644 index 0000000000..c7bce84bd5 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/UsbTypeC/UsbTypeC.asl @@ -0,0 +1,148 @@ +/** @file + ACPI DSDT table for USB Type C. + + Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +DefinitionBlock ( + "UsbC.aml", + "SSDT", + 2, + "Intel_", + "UsbCTabl", + 0x1000 + ) +{ + + External(UBCB) + External(P8XH, MethodObj) + External(BID, IntObj) // BoardId + External(\_SB.PCI0.XHC.RHUB, DeviceObj) + External(\_SB.PCI0.XHC.RHUB.TPLD, MethodObj) + External(\_SB.PCI0.XHC.RHUB.TUPC, MethodObj) + External(ETYC, IntObj) + + Scope (\_SB) + { + Device(UBTC) // USB type C device + { + Name (_HID, EISAID("USBC000")) + Name (_CID, EISAID("PNP0CA0")) + Name (_UID, 0) + Name (_DDN, "USB Type C") + Name (_ADR, 0x0) + + + Name (CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x00000000, 0x1000, USBR) + }) + + Device (CR01) // USB Type C Connector + { + Name (_ADR, 0x0) + Method (_PLD) { Return ( \_SB.PCI0.XHC.RHUB.TPLD(1,1) ) } + } + + Method(_CRS,0, Serialized) + { + CreateDWordField (CRS, \_SB.UBTC.USBR._BAS, CBAS) + Store (UBCB, CBAS) + Return(CRS) + } + + Method(_STA,0) + { + If (LEqual (ETYC, 1)) { + Return(0xF) + } + Return(0x0) + } + + OperationRegion (USBC, SystemMemory, UBCB, 0x38) // 56 bytes Opm Buffer + Field(USBC,ByteAcc,Lock,Preserve) + { + VER1, 8, + VER2, 8, + RSV1, 8, + RSV2, 8, + Offset(4), + CCI0, 8, // PPM->OPM CCI indicator + CCI1, 8, + CCI2, 8, + CCI3, 8, + + CTL0, 8, // OPM->PPM Control message + CTL1, 8, + CTL2, 8, + CTL3, 8, + CTL4, 8, + CTL5, 8, + CTL6, 8, + CTL7, 8, + + // USB Type C Mailbox Interface + MGI0, 8, // PPM->OPM Message In + MGI1, 8, + MGI2, 8, + MGI3, 8, + MGI4, 8, + MGI5, 8, + MGI6, 8, + MGI7, 8, + MGI8, 8, + MGI9, 8, + MGIA, 8, + MGIB, 8, + MGIC, 8, + MGID, 8, + MGIE, 8, + MGIF, 8, + + MGO0, 8, // OPM->PPM Message Out + MGO1, 8, + MGO2, 8, + MGO3, 8, + MGO4, 8, + MGO5, 8, + MGO6, 8, + MGO7, 8, + MGO8, 8, + MGO9, 8, + MGOA, 8, + MGOB, 8, + MGOC, 8, + MGOD, 8, + MGOE, 8, + MGOF, 8, + + } // end of Field + + Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj} ) + { + // Compare passed in UUID with supported UUID. + If (LEqual(Arg0, ToUUID ("6f8398c2-7ca4-11e4-ad36-631042b5008f"))) { + // UUID for USB type C + Switch (ToInteger(Arg2)) // Arg2: 0 for query, 1 for write and 2 for read + { + Case (0) + { + Return (Buffer() {0x07}) // 2 functions defined other than Query. + } + + } // End switch + } // End UUID check + Return (0) + } // End _DSM Method + } // end of Device + } // end \_SB scope +} // end SSDT + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Video.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Video.asl new file mode 100644 index 0000000000..d9151b89d3 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Video.asl @@ -0,0 +1,32 @@ +/** @file + Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +External(\_SB.PCI0.GFX0.DD1F) + +// Brightness Notification: +// Generate a brightness related notification +// to the LFP if its populated. +// +// Arguments: +// Arg0: Notification value. +// +// Return Value: +// None + +Method(BRTN,1,Serialized) +{ + If (LEqual(And(DIDX,0x0F00),0x400)) { + Notify(\_SB.PCI0.GFX0.DD1F,Arg0) + } +} + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Wifi.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Wifi.asl new file mode 100644 index 0000000000..3a2e444f4d --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Wifi.asl @@ -0,0 +1,57 @@ +/** @file + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + OperationRegion(RPXX, PCI_Config, 0x00, 0x10) + Field(RPXX, AnyAcc, NoLock, Preserve) + { + Offset(0), // Vendor-Device ID + VDID, 32, + } + + // WIST (WiFi Device Presence Status) + // + // Check if a WiFi Device is present on the RootPort. + // + // Arguments: (0) + // None + // Return Value: + // 0 - if a device is not present. + // 1 - if a device is present. + // + Method(WIST,0,Serialized) + { + // check Vendor-Device ID for supported devices + If (CondRefOf(VDID)) { + Switch (ToInteger(VDID)) { + // Wifi devices + Case(0x095A8086){Return(1)} // StonePeak + Case(0x095B8086){Return(1)} // StonePeak + Case(0x31658086){Return(1)} // StonePeak 1x1 + Case(0x31668086){Return(1)} // StonePeak 1x1 + Case(0x08B18086){Return(1)} // WilkinsPeak + Case(0x08B28086){Return(1)} // WilkinsPeak + Case(0x08B38086){Return(1)} // WilkinsPeak + Case(0x08B48086){Return(1)} // WilkinsPeak + Case(0x24F38086){Return(1)} // SnowfieldPeak + Case(0x24F48086){Return(1)} // SnowfieldPeak + Case(0x24F58086){Return(1)} // SnF/LnP/DgP SKUs + Case(0x24F68086){Return(1)} // SnF/LnP/DgP SKUs + Case(0x24FD8086){Return(1)} // Windstorm Peak + Case(0x24FB8086){Return(1)} // Sandy Peak + Default{Return(0)} // no supported device + } + } Else { + Return(0) + } + } + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Wsmt/WSMT.h b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Wsmt/WSMT.h new file mode 100644 index 0000000000..5c45a1a7b9 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Wsmt/WSMT.h @@ -0,0 +1,57 @@ +/** @file + This file describes WSMT table. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +typedef struct { + UINT32 Signature; //0 + UINT32 Length; //4 + UINT8 Revision; //8 + UINT8 Checksum; //9 + UINT8 OEMID[6]; //10 + UINT8 OEMTableID[8]; //16 + UINT32 OEMRevision; //24 + UINT32 CreatorID; //28 + UINT32 CreatorRevision; //32 + UINT32 ProtectionFlags; //36 +} ACPI_WINDOWS_SMM_SECURITY_MITIGATIONS_STRUCTURE; + +#define ACPI_WINDOWS_SMM_SECURITY_MITIGATIONS_STRUCTURE_SIGNATURE SIGNATURE_32('W', 'S', 'M', 'T') + +// +//note: ProtectionFlags , BIT0=FIXED_COMM_BUFFERS , BIT1=COMM_BUFFER_NESTED_PTR_PROTECTION , BIT2=SYSTEM_RESOURCE_PROTECTION +// + +/* +FIXED_COMM_BUFFERS - Firmware setting this bit should refer to the SMM Communication ACPI Table defined in the UEFI 2.6 specification. + Firmware should also consider all other possible data exchanges between SMM and non-SMM, + including but not limited to EFI_SMM_COMMUNICATION_PROTOCOL, ACPINVS in ASL code, + general purpose registers as buffer pointers, etc. + +COMM_BUFFER_NESTED_PTR_PROTECTION - Firmware setting this bit must also set the FIXED_COMM_BUFFERS bit. + +SYSTEM_RESOURCE_PROTECTION - After ExitBootServices(), firmware setting this bit shall not allow any software to make changes + to the locations of IOMMU's, interrupt controllers, PCI Configuration Space, + the Firmware ACPI Control Structure (FACS), or any registers reported through ACPI fixed tables + (e.g. PMx Control registers, reset register, etc.). + This also includes disallowing changes to RAM layout and ensuring that decodes to RAM + and any system resources as described above take priority over software configurable registers. + For example, if software configures a PCI Express BAR to overlay RAM, + accesses by the CPU to the affected system physical addresses must decode to RAM. +*/ + +#define ACPI_WINDOWS_SMM_SECURITY_MITIGATIONS_PROTECTION_FLAGS 0x00000000 +#define FIXED_COMM_BUFFERS BIT0 +#define COMM_BUFFER_NESTED_PTR_PROTECTION BIT1 +#define SYSTEM_RESOURCE_PROTECTION BIT2 + diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Wsmt/Wsmt.act b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Wsmt/Wsmt.act new file mode 100644 index 0000000000..334c58df38 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Wsmt/Wsmt.act @@ -0,0 +1,82 @@ +/** @file + ACPI WSMT table + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "WSMT.h" + + +ACPI_WINDOWS_SMM_SECURITY_MITIGATIONS_STRUCTURE Wsmt = { + ACPI_WINDOWS_SMM_SECURITY_MITIGATIONS_STRUCTURE_SIGNATURE, + sizeof (ACPI_WINDOWS_SMM_SECURITY_MITIGATIONS_STRUCTURE), + + //Revision + 0x00, + + //Checksum + 0x00, + + //OEMID + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + + //OEMTableID + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + + //OEMRevision + 0x00000000, + + //CreatorID + 0x00000000, + + //CreatorRevision + 0x00000000, + + //ProtectionFlags + ACPI_WINDOWS_SMM_SECURITY_MITIGATIONS_PROTECTION_FLAGS, + +}; + + +#ifdef __GNUC__ +VOID* +ReferenceAcpiTable ( + VOID + ) +{ + // + // Reference the table being generated to prevent the optimizer from removing the + // data structure from the exeutable + // + return (VOID*)&Wsmt; +} +#else +VOID +main ( + VOID + ) + +{ +} +#endif \ No newline at end of file diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/token.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/token.asl new file mode 100644 index 0000000000..3716dc28d3 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/token.asl @@ -0,0 +1,55 @@ +/** @file + Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Name(SP3O, 0x2e) // Super I/O (Winbond 3xx) Index/Data configuration port for ASL. +Name(IO4B, 0xa20) // Super I/O (Winbond 3xx) GPIO base address +Name(IO4L, 0x20) // Super I/O (Winbond 3xx) GPIO base address length +Name(SP1O, 0x4e) // Super IO Index/Data configuration port for ASL. +Name(PMBS, 0x400) // ASL alias for ACPI I/O base address. +Name(SMIP, 0xb2) // I/O port to trigger SMI +Name(APCB, 0xfec00000) // Default I/O APIC(s) memory start address, 0x0FEC00000 - default, 0 - I/O APIC's disabled +Name(APCL, 0x1000) // I/O APIC(s) memory decoded range, 0x1000 - default, 0 - I/O APIC's not decoded +Name(PMCB, 0xfed03000) // PMC Base Address +Name(IBAS, 0xfed08000) // ILB Base Address +Name(SRCB, 0xfed1c000) // RCBA (Root Complex Base Address) +Name(HPTB, 0xfed00000) // Same as HPET_BASE_ADDRESS for ASL use +Name(PEBS, 0xe0000000) // +Name(PELN, 0x10000000) // +Name(FMBL, 0x1) // Platform Flavor - Mobile flavor for ASL code. +Name(FDTP, 0x2) // Platform Flavor - Desktop flavor for ASL code. +Name(GCDD, 0x1) // GET_CURRENT_DISPLAY_DEVICE_SMI +Name(DSTA, 0xa) // DISPLAY_SWITCH_TOGGLE_ACPI_SMI +Name(DSLO, 0x2) // DISPLAY_SWITCH_LID_OPEN_ACPI_SMI +Name(DSLC, 0x3) // DISPLAY_SWITCH_LID_CLOSE_ACPI_SMI +Name(PITS, 0x10) // POPUP_ICON_TOGGLE_SMI +Name(SBCS, 0x12) // SET_BACKLIGHT_CONTROL_SMI +Name(SALS, 0x13) // SET_ALI_LEVEL_SMI +Name(LSSS, 0x2a) // LID_STATE_SWITCH_SMI +Name(PSSS, 0x2b) // POWER_STATE_SWITCH_SMI +Name(SOOT, 0x35) // SAVE_OSB_OS_TYPE_SMI +Name(ESCS, 0x48) // ENABLE_SMI_C_STATE_COORDINATION_SMI +Name(SDGV, 0x1c) // UHCI Controller HOST_ALERT's bit offset within the GPE block. GPIO[0:15] corresponding to GPE[16:31] +Name(ACPH, 0xde) // North Bridge Scratchpad Data Register for patch ACPI. +Name(ASSB, 0x0) // ACPI Sleep State Buffer for BIOS Usage. +Name(AOTB, 0x0) // ACPI OS Type Buffer for BIOS Usage. +Name(AAXB, 0x0) // ACPI Auxiliary Buffer for BIOS Usage. +Name(PEHP, 0x1) // _OSC: Pci Express Native Hot Plug Control +Name(SHPC, 0x0) // _OSC: Standard Hot Plug Controller (SHPC) Native Hot Plug control +Name(PEPM, 0x1) // _OSC: Pci Express Native Power Management Events control +Name(PEER, 0x1) // _OSC: Pci Express Advanced Error Reporting control +Name(PECS, 0x1) // _OSC: Pci Express Capability Structure control +Name(ITKE, 0x0) // This will be overridden by the ITK module. +Name(FTBL, 0x4) // Platform Flavor - Tablet flavor for ASL code. +Name(GRBM, 0xF) // Board id for Gordon Ridge BMP MRB +Name(MNHL, 0x5) // Board id for Mineral Hill + -- cgit v1.2.3