From 600081b52debde8d06585fdaf09fac16d323670f Mon Sep 17 00:00:00 2001 From: Leif Lindholm Date: Thu, 3 Aug 2017 12:24:30 +0100 Subject: Platform,Silicon: Import Hisilicon D02,D03,D05 and HiKey Imported from commit efd798c1eb of https://git.linaro.org/uefi/OpenPlatformPkg.git Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm --- .../D02/EarlyConfigPeim/EarlyConfigPeim.c | 94 +++ .../D02/EarlyConfigPeim/EarlyConfigPeim.inf | 53 ++ .../Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.c | 341 +++++++++++ .../Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf | 43 ++ Platform/Hisilicon/D02/Include/Library/CpldD02.h | 34 ++ .../D02/Library/OemMiscLibD02/BoardFeatureD02.c | 105 ++++ .../OemMiscLibD02/BoardFeatureD02Strings.uni | Bin 0 -> 1796 bytes .../D02/Library/OemMiscLibD02/OemMiscLibD02.c | 77 +++ .../D02/Library/OemMiscLibD02/OemMiscLibD02.inf | 45 ++ .../D02/Library/PlatformPciLib/PlatformPciLib.c | 147 +++++ .../D02/Library/PlatformPciLib/PlatformPciLib.inf | 182 ++++++ .../Hisilicon/D02/OemNicConfigD02/OemNicConfig.h | 31 + .../D02/OemNicConfigD02/OemNicConfigD02.c | 173 ++++++ .../D02/OemNicConfigD02/OemNicConfigD02.inf | 50 ++ Platform/Hisilicon/D02/Pv660D02.dec | 44 ++ Platform/Hisilicon/D02/Pv660D02.dsc | 453 ++++++++++++++ Platform/Hisilicon/D02/Pv660D02.fdf | 317 ++++++++++ Platform/Hisilicon/D03/D03.dec | 44 ++ Platform/Hisilicon/D03/D03.dsc | 525 ++++++++++++++++ Platform/Hisilicon/D03/D03.fdf | 334 +++++++++++ .../Drivers/OemNicConfig2PHi1610/OemNicConfig.h | 40 ++ .../Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c | 362 +++++++++++ .../OemNicConfig2PHi1610/OemNicConfig2P.inf | 52 ++ .../D03/Drivers/PciPlatform/PciPlatform.c | 437 ++++++++++++++ .../D03/Drivers/PciPlatform/PciPlatform.h | 180 ++++++ .../D03/Drivers/PciPlatform/PciPlatform.inf | 53 ++ .../D03/EarlyConfigPeim/EarlyConfigPeimD03.c | 180 ++++++ .../D03/EarlyConfigPeim/EarlyConfigPeimD03.inf | 55 ++ Platform/Hisilicon/D03/Include/Library/CpldD03.h | 25 + .../DS3231RealTimeClockLib/DS3231RealTimeClock.h | 178 ++++++ .../DS3231RealTimeClockLib.c | 504 ++++++++++++++++ .../DS3231RealTimeClockLib.inf | 48 ++ .../D03/Library/FdtUpdateLib/FdtUpdateLib.c | 487 +++++++++++++++ .../D03/Library/FdtUpdateLib/FdtUpdateLib.inf | 50 ++ .../Library/OemMiscLib2P/BoardFeature2PHi1610.c | 197 ++++++ .../OemMiscLib2P/BoardFeature2PHi1610Strings.uni | Bin 0 -> 4292 bytes .../D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c | 141 +++++ .../Library/OemMiscLib2P/OemMiscLib2PHi1610.inf | 54 ++ .../D03/Library/PlatformPciLib/PlatformPciLib.c | 156 +++++ .../D03/Library/PlatformPciLib/PlatformPciLib.inf | 182 ++++++ Platform/Hisilicon/D05/D05.dsc | 663 +++++++++++++++++++++ Platform/Hisilicon/D05/D05.fdf | 358 +++++++++++ .../D05/EarlyConfigPeim/EarlyConfigPeimD05.c | 64 ++ .../D05/EarlyConfigPeim/EarlyConfigPeimD05.inf | 53 ++ .../D05/Library/OemMiscLibD05/BoardFeatureD05.c | 225 +++++++ .../OemMiscLibD05/BoardFeatureD05Strings.uni | 56 ++ .../D05/Library/OemMiscLibD05/OemMiscLibD05.c | 107 ++++ .../D05/Library/OemMiscLibD05/OemMiscLibD05.inf | 55 ++ .../D05/Library/PlatformPciLib/PlatformPciLib.c | 279 +++++++++ .../D05/Library/PlatformPciLib/PlatformPciLib.inf | 183 ++++++ Platform/Hisilicon/HiKey/HiKey.dec | 36 ++ Platform/Hisilicon/HiKey/HiKey.dsc | 482 +++++++++++++++ Platform/Hisilicon/HiKey/HiKey.fdf | 351 +++++++++++ Platform/Hisilicon/HiKey/Include/ArmPlatform.h | 26 + Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKey.c | 159 +++++ .../Hisilicon/HiKey/Library/HiKeyLib/HiKeyHelper.S | 49 ++ .../Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf | 51 ++ .../Hisilicon/HiKey/Library/HiKeyLib/HiKeyMem.c | 204 +++++++ 58 files changed, 9874 insertions(+) create mode 100644 Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.c create mode 100644 Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf create mode 100644 Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.c create mode 100644 Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf create mode 100644 Platform/Hisilicon/D02/Include/Library/CpldD02.h create mode 100644 Platform/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c create mode 100644 Platform/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02Strings.uni create mode 100644 Platform/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.c create mode 100644 Platform/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.inf create mode 100644 Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c create mode 100644 Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf create mode 100644 Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfig.h create mode 100644 Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.c create mode 100644 Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf create mode 100644 Platform/Hisilicon/D02/Pv660D02.dec create mode 100644 Platform/Hisilicon/D02/Pv660D02.dsc create mode 100644 Platform/Hisilicon/D02/Pv660D02.fdf create mode 100644 Platform/Hisilicon/D03/D03.dec create mode 100644 Platform/Hisilicon/D03/D03.dsc create mode 100644 Platform/Hisilicon/D03/D03.fdf create mode 100644 Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig.h create mode 100644 Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c create mode 100644 Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf create mode 100644 Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.c create mode 100644 Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.h create mode 100644 Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf create mode 100644 Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c create mode 100644 Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf create mode 100644 Platform/Hisilicon/D03/Include/Library/CpldD03.h create mode 100644 Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClock.h create mode 100644 Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c create mode 100644 Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf create mode 100755 Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.c create mode 100755 Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf create mode 100644 Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c create mode 100644 Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610Strings.uni create mode 100644 Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c create mode 100644 Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf create mode 100644 Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c create mode 100644 Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf create mode 100644 Platform/Hisilicon/D05/D05.dsc create mode 100644 Platform/Hisilicon/D05/D05.fdf create mode 100644 Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c create mode 100644 Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf create mode 100644 Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c create mode 100644 Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni create mode 100644 Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c create mode 100644 Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf create mode 100644 Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c create mode 100644 Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf create mode 100644 Platform/Hisilicon/HiKey/HiKey.dec create mode 100644 Platform/Hisilicon/HiKey/HiKey.dsc create mode 100644 Platform/Hisilicon/HiKey/HiKey.fdf create mode 100644 Platform/Hisilicon/HiKey/Include/ArmPlatform.h create mode 100644 Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKey.c create mode 100644 Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyHelper.S create mode 100644 Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf create mode 100644 Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyMem.c (limited to 'Platform/Hisilicon') diff --git a/Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.c b/Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.c new file mode 100644 index 0000000000..1d011fb686 --- /dev/null +++ b/Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.c @@ -0,0 +1,94 @@ +/** @file +* +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#define TIMER_SUBCTRL_BASE PcdGet64(PcdPeriSubctrlAddress) +#define ALG_BASE (0xA0000000) +#define PERI_SUB_CTRL_BASE (0x80000000) +#define SC_TM_CLKEN0_REG (0x2050) +#define SYS_APB_IF_BASE (0x10000) +#define TSENSOR_REG (0x5000) +#define SC_ITS_M3_INT_MUX_SEL_REG (0x21F0) +#define SC_HLLC_RESET_DREQ_REG (0xA8C) +#define SC_ITS_M3_INT_MUX_SEL_VALUE (0xF) +#define SC_HLLC_RESET_DREQ_VALUE (0x1f) +#define TSENSOR_CONFIG_VALUE (0x1) + +VOID PlatformTimerStart (VOID) +{ + // Timer0 clock enable + MmioWrite32 (TIMER_SUBCTRL_BASE + SC_TM_CLKEN0_REG, 0x3); +} + +EFI_STATUS +EFIAPI +EarlyConfigEntry ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + DEBUG((EFI_D_INFO,"SMMU CONFIG.........")); + SmmuConfigForOS(); + DEBUG((EFI_D_INFO,"Done\n")); + + DEBUG((EFI_D_INFO,"ITS CONFIG.........")); + ITSCONFIG(); + DEBUG((EFI_D_INFO,"Done\n")); + + DEBUG((EFI_D_INFO,"AP CONFIG.........")); + MmioWrite64(FixedPcdGet64(PcdMailBoxAddress), 0x0); + (void)WriteBackInvalidateDataCacheRange((VOID *) FixedPcdGet64(PcdMailBoxAddress), 8); + ArmDataSynchronizationBarrier (); + ArmInstructionSynchronizationBarrier (); + + CoreSelectBoot(); + + DEBUG((EFI_D_INFO,"Done\n")); + + DEBUG((EFI_D_INFO,"MN CONFIG.........")); + MN_CONFIG (); + DEBUG((EFI_D_INFO,"Done\n")); + + DEBUG((EFI_D_INFO,"RTC CONFIG.........")); + + MmioWrite32(ALG_BASE + SC_ITS_M3_INT_MUX_SEL_REG, SC_ITS_M3_INT_MUX_SEL_VALUE); + + DEBUG((EFI_D_INFO,"Done\n")); + + DEBUG((EFI_D_INFO,"Tsensor CONFIG.........")); + + MmioWrite32(PERI_SUB_CTRL_BASE + SYS_APB_IF_BASE + TSENSOR_REG, TSENSOR_CONFIG_VALUE); + MmioWrite32(ALG_BASE + SC_HLLC_RESET_DREQ_REG, SC_HLLC_RESET_DREQ_VALUE); + + DEBUG((EFI_D_INFO,"Done\n")); + + DEBUG((EFI_D_INFO,"Timer CONFIG.........")); + PlatformTimerStart (); + DEBUG((EFI_D_INFO,"Done\n")); + + return EFI_SUCCESS; +} diff --git a/Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf b/Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf new file mode 100644 index 0000000000..5506a586ae --- /dev/null +++ b/Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf @@ -0,0 +1,53 @@ +#/** @file +# +# Copyright (c) 2015, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = EarlyConfigPeim + FILE_GUID = A181AD33-E64A-4084-A54A-A69DF1FB0ABF + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = EarlyConfigEntry + +[Sources.common] + EarlyConfigPeim.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + ArmPkg/ArmPkg.dec + + Silicon/Hisilicon/HisiPkg.dec + +[LibraryClasses] + PeimEntryPoint + PcdLib + DebugLib + IoLib + CacheMaintenanceLib + ArmLib + + PlatformSysCtrlLib + +[Pcd] + gHisiTokenSpaceGuid.PcdMailBoxAddress + gHisiTokenSpaceGuid.PcdPeriSubctrlAddress + +[Depex] +## As we will clean mailbox in this module, need to wait memory init complete + gEfiPeiMemoryDiscoveredPpiGuid + +[BuildOptions] + diff --git a/Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.c b/Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.c new file mode 100644 index 0000000000..429306bb03 --- /dev/null +++ b/Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.c @@ -0,0 +1,341 @@ +/** @file +* +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +MAC_ADDRESS gMacAddress[1]; + +CHAR8 *EthName[8]= +{ + "ethernet@0","ethernet@1", + "ethernet@2","ethernet@3", + "ethernet@4","ethernet@5", + "ethernet@6","ethernet@7" +}; + +CHAR8 *MacName[4]= +{ + "ethernet-mac@c7040000", + "ethernet-mac@c7044000", + "ethernet-mac@c7048000", + "ethernet-mac@c704c000" +}; + +STATIC +BOOLEAN +IsMemMapRegion ( + IN EFI_MEMORY_TYPE MemoryType + ) +{ + switch(MemoryType) + { + case EfiRuntimeServicesCode: + case EfiRuntimeServicesData: + case EfiConventionalMemory: + case EfiACPIReclaimMemory: + case EfiACPIMemoryNVS: + case EfiLoaderCode: + case EfiLoaderData: + case EfiBootServicesCode: + case EfiBootServicesData: + case EfiPalCode: + return TRUE; + default: + return FALSE; + } +} + +EFI_STATUS +GetMacAddress (UINT32 Port) +{ + EFI_MAC_ADDRESS Mac; + EFI_STATUS Status; + HISI_BOARD_NIC_PROTOCOL *OemNic = NULL; + + Status = gBS->LocateProtocol(&gHisiBoardNicProtocolGuid, NULL, (VOID **)&OemNic); + if(EFI_ERROR(Status)) + { + DEBUG((EFI_D_ERROR, "[%a]:[%dL] LocateProtocol failed %r\n", __FUNCTION__, __LINE__, Status)); + return Status; + } + + Status = OemNic->GetMac(&Mac, Port); + if(EFI_ERROR(Status)) + { + DEBUG((EFI_D_ERROR, "[%a]:[%dL] GetMac failed %r\n", __FUNCTION__, __LINE__, Status)); + return Status; + } + + gMacAddress[0].data0=Mac.Addr[0]; + gMacAddress[0].data1=Mac.Addr[1]; + gMacAddress[0].data2=Mac.Addr[2]; + gMacAddress[0].data3=Mac.Addr[3]; + gMacAddress[0].data4=Mac.Addr[4]; + gMacAddress[0].data5=Mac.Addr[5]; + DEBUG((EFI_D_ERROR, "Port%d:0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", + Port,gMacAddress[0].data0,gMacAddress[0].data1,gMacAddress[0].data2, + gMacAddress[0].data3,gMacAddress[0].data4,gMacAddress[0].data5)); + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +DelPhyhandleUpdateMacAddress(IN VOID* Fdt) +{ + UINT8 port; + INTN ethernetnode; + INTN node; + INTN Error; + struct fdt_property *m_prop; + int m_oldlen; + EFI_STATUS Status = EFI_SUCCESS; + + node = fdt_subnode_offset(Fdt, 0, "soc"); + if (node < 0) + { + DEBUG ((EFI_D_ERROR, "can not find soc root node\n")); + return EFI_INVALID_PARAMETER; + } + else + { + for( port=0; port<8; port++ ) + { + (VOID) GetMacAddress(port); + ethernetnode=fdt_subnode_offset(Fdt, node,EthName[port]); + if (ethernetnode < 0) + { + DEBUG ((EFI_D_ERROR, "can not find ethernet@ %d node\n",port)); + } + m_prop = fdt_get_property_w(Fdt, ethernetnode, "local-mac-address", &m_oldlen); + if(m_prop) + { + Error = fdt_delprop(Fdt, ethernetnode, "local-mac-address"); + if (Error) + { + DEBUG ((EFI_D_ERROR, "ERROR:fdt_delprop() Local-mac-address: %a\n", fdt_strerror (Error))); + Status = EFI_INVALID_PARAMETER; + } + Error = fdt_setprop(Fdt, ethernetnode, "local-mac-address",gMacAddress,sizeof(MAC_ADDRESS)); + if (Error) + { + DEBUG ((EFI_D_ERROR, "ERROR:fdt_setprop():local-mac-address %a\n", fdt_strerror (Error))); + Status = EFI_INVALID_PARAMETER; + } + } + } + } + return Status; +} + +EFI_STATUS UpdateMemoryNode(VOID* Fdt) +{ + INTN Error = 0; + EFI_STATUS Status = EFI_SUCCESS; + UINT32 Index = 0; + UINT32 MemIndex; + INTN node; + struct fdt_property *m_prop; + int m_oldlen; + EFI_MEMORY_DESCRIPTOR *MemoryMap; + EFI_MEMORY_DESCRIPTOR *MemoryMapPtr; + EFI_MEMORY_DESCRIPTOR *MemoryMapPtrCurrent; + UINTN MemoryMapSize; + UINTN Pages0 = 0; + UINTN Pages1 = 0; + UINTN MapKey; + UINTN DescriptorSize; + UINT32 DescriptorVersion; + PHY_MEM_REGION *mRegion; + UINTN MemoryMapLastEndAddress ; + UINTN MemoryMapcontinuousStartAddress ; + UINTN MemoryMapCurrentStartAddress; + BOOLEAN FindMemoryRegionFlag = FALSE; + node = fdt_subnode_offset(Fdt, 0, "memory"); + if (node < 0) + { + // Create the memory node + node = fdt_add_subnode(Fdt, 0, "memory"); + if(node < 0) + { + DEBUG((EFI_D_INFO, "[%a]:[%dL] fdt add subnode error\n", __FUNCTION__, __LINE__)); + } + } + //find the memory node property + m_prop = fdt_get_property_w(Fdt, node, "memory", &m_oldlen); + if(m_prop) + Error=fdt_delprop(Fdt, node, "reg"); + if (Error) + { + DEBUG ((EFI_D_ERROR, "ERROR:fdt_delprop(): %a\n", fdt_strerror (Error))); + Status = EFI_INVALID_PARAMETER; + return Status; + } + + MemoryMap = NULL; + MemoryMapSize = 0; + MemIndex = 0; + + Status = gBS->GetMemoryMap (&MemoryMapSize, MemoryMap, &MapKey, &DescriptorSize, &DescriptorVersion); + if (Status == EFI_BUFFER_TOO_SMALL) + { + // The UEFI specification advises to allocate more memory for the MemoryMap buffer between successive + // calls to GetMemoryMap(), since allocation of the new buffer may potentially increase memory map size. + //DEBUG ((EFI_D_ERROR, "MemoryMapsize: 0x%lx\n",MemoryMapSize)); + Pages0 = EFI_SIZE_TO_PAGES (MemoryMapSize) + 1; + MemoryMap = AllocatePages (Pages0); + if (MemoryMap == NULL) + { + Status = EFI_OUT_OF_RESOURCES; + return Status; + } + Status = gBS->GetMemoryMap (&MemoryMapSize, MemoryMap, &MapKey, &DescriptorSize, &DescriptorVersion); + } + + if(MemoryMap == NULL) + { + Status = EFI_OUT_OF_RESOURCES; + //goto EXIT; + return Status; + } + + mRegion = NULL; + Pages1 = EFI_SIZE_TO_PAGES (sizeof(PHY_MEM_REGION) *( MemoryMapSize / DescriptorSize)); + mRegion = (PHY_MEM_REGION*)AllocatePages(Pages1); + if (mRegion == NULL) + { + Status = EFI_OUT_OF_RESOURCES; + return Status; + } + + if (!EFI_ERROR(Status)) + { + MemoryMapPtr = MemoryMap; + MemoryMapPtrCurrent = MemoryMapPtr; + MemoryMapLastEndAddress = 0; + MemoryMapcontinuousStartAddress = 0; + MemoryMapCurrentStartAddress = 0; + for ( Index = 0; Index < (MemoryMapSize / DescriptorSize); Index++) + { + MemoryMapPtrCurrent = (EFI_MEMORY_DESCRIPTOR*)((UINTN)MemoryMapPtr + Index*DescriptorSize); + MemoryMapCurrentStartAddress = (UINTN)MemoryMapPtrCurrent->PhysicalStart; + + if (!IsMemMapRegion ((EFI_MEMORY_TYPE)MemoryMapPtrCurrent->Type)) + { + continue; + } + else + { + FindMemoryRegionFlag = TRUE; + if(MemoryMapCurrentStartAddress != MemoryMapLastEndAddress) + { + mRegion[MemIndex].BaseHigh= cpu_to_fdt32(MemoryMapcontinuousStartAddress>>32); + mRegion[MemIndex].BaseLow=cpu_to_fdt32(MemoryMapcontinuousStartAddress); + mRegion[MemIndex].LengthHigh= cpu_to_fdt32((MemoryMapLastEndAddress-MemoryMapcontinuousStartAddress)>>32); + mRegion[MemIndex].LengthLow=cpu_to_fdt32(MemoryMapLastEndAddress-MemoryMapcontinuousStartAddress); + MemIndex+=1; + MemoryMapcontinuousStartAddress=MemoryMapCurrentStartAddress; + } + } + MemoryMapLastEndAddress = (UINTN)(MemoryMapPtrCurrent->PhysicalStart + MemoryMapPtrCurrent->NumberOfPages * EFI_PAGE_SIZE); + } + if (FindMemoryRegionFlag) + { + mRegion[MemIndex].BaseHigh = cpu_to_fdt32(MemoryMapcontinuousStartAddress>>32); + mRegion[MemIndex].BaseLow = cpu_to_fdt32(MemoryMapcontinuousStartAddress); + mRegion[MemIndex].LengthHigh = cpu_to_fdt32((MemoryMapLastEndAddress-MemoryMapcontinuousStartAddress)>>32); + mRegion[MemIndex].LengthLow = cpu_to_fdt32(MemoryMapLastEndAddress-MemoryMapcontinuousStartAddress); + } + } + Error = fdt_setprop(Fdt, node, "reg",mRegion,sizeof(PHY_MEM_REGION) *(MemIndex+1)); + FreePages (mRegion, Pages1); + FreePages (MemoryMap, Pages0); + if (Error) + { + DEBUG ((EFI_D_ERROR, "ERROR:fdt_setprop(): %a\n", fdt_strerror (Error))); + Status = EFI_INVALID_PARAMETER; + return Status; + } + return Status; +} + +/* + * Entry point for fdtupdate lib. + */ + +EFI_STATUS EFIFdtUpdate(UINTN FdtFileAddr) +{ + INTN Error; + VOID* Fdt; + UINT32 Size; + UINTN NewFdtBlobSize; + UINTN NewFdtBlobBase; + EFI_STATUS Status = EFI_SUCCESS; + + Error = fdt_check_header ((VOID*)(UINTN)(FdtFileAddr)); + if (Error != 0) + { + DEBUG ((EFI_D_ERROR,"ERROR: Device Tree header not valid (%a)\n", fdt_strerror(Error))); + return EFI_INVALID_PARAMETER; + } + + Size = (UINTN)fdt_totalsize ((VOID*)(UINTN)(FdtFileAddr)); + NewFdtBlobSize = Size + ADD_FILE_LENGTH; + Fdt = (VOID*)(UINTN)FdtFileAddr; + + Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, EFI_SIZE_TO_PAGES(NewFdtBlobSize), &NewFdtBlobBase); + if (EFI_ERROR (Status)) + { + return EFI_OUT_OF_RESOURCES; + } + + + Error = fdt_open_into(Fdt,(VOID*)(UINTN)(NewFdtBlobBase), (NewFdtBlobSize)); + if (Error) { + DEBUG ((EFI_D_ERROR, "ERROR:fdt_open_into(): %a\n", fdt_strerror (Error))); + Status = EFI_INVALID_PARAMETER; + goto EXIT; + } + + Fdt = (VOID*)(UINTN)NewFdtBlobBase; + + Status = DelPhyhandleUpdateMacAddress(Fdt); + if (EFI_ERROR (Status)) + { + DEBUG ((EFI_D_ERROR, "DelPhyhandleUpdateMacAddress fail:\n")); + Status = EFI_SUCCESS; + } + + Status = UpdateMemoryNode(Fdt); + if (EFI_ERROR (Status)) + { + goto EXIT; + } + + gBS->CopyMem(((VOID*)(UINTN)(FdtFileAddr)),((VOID*)(UINTN)(NewFdtBlobBase)),NewFdtBlobSize); + +EXIT: + gBS->FreePages(NewFdtBlobBase,EFI_SIZE_TO_PAGES(NewFdtBlobSize)); + + return Status; +} diff --git a/Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf b/Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf new file mode 100644 index 0000000000..c952414350 --- /dev/null +++ b/Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf @@ -0,0 +1,43 @@ +#/** @file +# +# Copyright (c) 2015, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = FdtUpdateLib + FILE_GUID = 02CF1727-E697-47fc-8CC2-5DCB81B26DD9 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = FdtUpdateLib + + +[Sources.common] + FdtUpdateLib.c + + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec + +[LibraryClasses] + FdtLib + OemAddressMapLib + +[Protocols] + gHisiBoardNicProtocolGuid + +[Pcd] + diff --git a/Platform/Hisilicon/D02/Include/Library/CpldD02.h b/Platform/Hisilicon/D02/Include/Library/CpldD02.h new file mode 100644 index 0000000000..b899dbb377 --- /dev/null +++ b/Platform/Hisilicon/D02/Include/Library/CpldD02.h @@ -0,0 +1,34 @@ +/** @file +* +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __CPLDD02_H__ +#define __CPLDD02_H__ +#define CPLD_LOGIC_VERSION (0x52) +#define PRODUCT_VERSION (0x53) +#define CPLD_LOGIC_COMPLIER_YEAR (0x54) +#define CPLD_LOGIC_COMPLIER_MONTH (0x55) +#define CPLD_LOGIC_COMPLIER_DAY (0x56) +#define CPLD_LOGIC_COMPLIER_HOUR (0x57) +#define CPLD_LOGIC_COMPLIER_MINUTE (0x58) +#define BOARD_ID (0x59) +#define BOM_VERSION (0x5A) +#define CPLD_BIOS_CURRENT_CHANNEL_REG_D02 (0x5B) + +#define CPU0_PCIE1_RESET_REG (0x12) +#define CPU0_PCIE2_RESET_REG (0x13) +#define CPU1_PCIE1_RESET_REG (0x14) +#define CPU1_PCIE2_RESET_REG (0x15) + +#endif /* __CPLDD02_H__ */ diff --git a/Platform/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c b/Platform/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c new file mode 100644 index 0000000000..49942e5151 --- /dev/null +++ b/Platform/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c @@ -0,0 +1,105 @@ +/** @file +* +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +I2C_DEVICE gDS3231RtcDevice = { + .Socket = 0, + .Port = 7, + .DeviceType = DEVICE_TYPE_SPD, + .SlaveDeviceAddress = 0x68 +}; + +// Set Tx output polarity. Not inverting data is default. For Phosphor660 D02 Board +//if((1 == ulMacroId) && ((7 == ulDsNum)||(0 == ulDsNum))) +SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[] = +{ + {1, 7}, + {1, 0}, + {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM} +}; + +// Set Rx data polarity. Not inverting data is default. For Phosphor660 D02 Board +//if((1 == ulMacroId) && ((0 == ulDsNum) || (1 == ulDsNum))) +SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[] = +{ + {1, 0}, + {1, 1}, + {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM} +}; + +SERDES_PARAM gSerdesParam = { + .Hilink0Mode = EmHilink0Pcie1X8, + .Hilink1Mode = EmHilink1Pcie0X8, + .Hilink2Mode = EmHilink2Pcie2X8, + .Hilink3Mode = EmHilink3GeX4, + .Hilink4Mode = EmHilink4XgeX4, + .Hilink5Mode = EmHilink5Sas1X4, +}; + +EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId) +{ + if (ParamA == NULL) { + DEBUG((DEBUG_ERROR, "[%a]:[%dL] ParamA == NULL!\n", __FUNCTION__, __LINE__)); + return EFI_INVALID_PARAMETER; + } + + (VOID) CopyMem(ParamA, &gSerdesParam, sizeof(*ParamA)); + return EFI_SUCCESS; +} + + +VOID OemPcieResetAndOffReset(void) + { + WriteCpldReg(CPU0_PCIE1_RESET_REG,0x0); + WriteCpldReg(CPU0_PCIE2_RESET_REG,0x0); + WriteCpldReg(CPU1_PCIE1_RESET_REG,0x0); + WriteCpldReg(CPU1_PCIE2_RESET_REG,0x0); + MicroSecondDelay(100000); + WriteCpldReg(CPU0_PCIE1_RESET_REG,0x55); + WriteCpldReg(CPU0_PCIE2_RESET_REG,0x55); + WriteCpldReg(CPU1_PCIE1_RESET_REG,0x55); + WriteCpldReg(CPU1_PCIE2_RESET_REG,0x55); + return; + } + +EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM] = { + {{STRING_TOKEN(STR_D02_DIMM_000), STRING_TOKEN(STR_D02_DIMM_001), 0xFFFF}, + {STRING_TOKEN(STR_D02_DIMM_010), STRING_TOKEN(STR_D02_DIMM_011), 0xFFFF}} +}; + +EFI_HII_HANDLE +EFIAPI +OemGetPackages ( + ) +{ + return HiiAddPackages ( + &gEfiCallerIdGuid, + NULL, + OemMiscLibD02Strings, + NULL, + NULL + ); +} diff --git a/Platform/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02Strings.uni b/Platform/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02Strings.uni new file mode 100644 index 0000000000..dcd79eb3d5 Binary files /dev/null and b/Platform/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02Strings.uni differ diff --git a/Platform/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.c b/Platform/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.c new file mode 100644 index 0000000000..df7d158c2d --- /dev/null +++ b/Platform/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.c @@ -0,0 +1,77 @@ +/** @file +* +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// Right now we only support 1P +BOOLEAN OemIsSocketPresent (UINTN Socket) +{ + if (0 == Socket) + { + return TRUE; + } + + return FALSE; +} + +UINTN OemGetSocketNumber (VOID) +{ + return 1; +} + +UINTN OemGetDimmSlot(UINTN Socket, UINTN Channel) +{ + return 2; +} + +UINTN OemGetDdrChannel (VOID) +{ + return 2; +} + +VOID CoreSelectBoot(VOID) +{ + if (!PcdGet64 (PcdTrustedFirmwareEnable)) + { + StartupAp (); + } + + return; +} + +BOOLEAN OemIsMpBoot() +{ + return FALSE; +} + +VOID OemBiosSwitch(UINT32 Master) +{ + return; +} + +UINT32 OemIsWarmBoot(VOID) +{ + return 0; +} diff --git a/Platform/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.inf b/Platform/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.inf new file mode 100644 index 0000000000..3b50ddf9bc --- /dev/null +++ b/Platform/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.inf @@ -0,0 +1,45 @@ +#/** @file +# +# Copyright (c) 2015, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = OemMiscLibD02 + FILE_GUID = 1DCE7EC8-3DB6-47cf-A2B5-717FD9AB2570 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = OemMiscLib + +[Sources.common] + BoardFeatureD02.c + OemMiscLibD02.c + BoardFeatureD02Strings.uni + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + ArmPkg/ArmPkg.dec + + Platform/Hisilicon/D02/Pv660D02.dec + Silicon/Hisilicon/HisiPkg.dec + +[LibraryClasses] + SerialPortLib + CpldIoLib + +[BuildOptions] + +[Pcd] + gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable + diff --git a/Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c b/Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c new file mode 100644 index 0000000000..797163a5fc --- /dev/null +++ b/Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.c @@ -0,0 +1,147 @@ +/** @file + + Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2016, Linaro Limited. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include + +PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = { + {// HostBridge 0 + /* Port 0 */ + { + PCI_HB0RB0_ECAM_BASE, + 0, //BusBase + 63, //BusLimit + (PCI_HB0RB0_ECAM_BASE + SIZE_64MB), //MemBase + (PCI_HB0RB0_ECAM_BASE + PCI_HB0RB0_ECAM_SIZE - 1), //MemLimit + (0), //IoBase + (0), //IoLimit + 0, + 0, + (PCI_HB0RB0_PCI_BASE), //RbPciBar + 0, + 0 + }, + /* Port 1 */ + { + PCI_HB0RB1_ECAM_BASE, + 64, //BusBase + 127, //BusLimit + PCI_HB0RB1_PCIREGION_BASE, + PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1, + PCI_HB0RB1_IO_BASE, //IoBase + PCI_HB0RB1_IO_BASE + PCI_HB0RB1_IO_SIZE - 1, //IoLimit + PCI_HB0RB1_CPUMEMREGIONBASE, + PCI_HB0RB2_CPUIOREGIONBASE, + (PCI_HB0RB1_PCI_BASE), //RbPciBar + PCI_HB0RB1_PCIREGION_BASE, + PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1 + }, + /* Port 2 */ + { + PCI_HB0RB2_ECAM_BASE, + 128, //BusBase + 191, //BusLimit + PCI_HB0RB2_PCIREGION_BASE , + PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1, + PCI_HB0RB2_IO_BASE, //IoBase + PCI_HB0RB2_IO_BASE + PCI_HB0RB2_IO_SIZE - 1, //IoLimit + PCI_HB0RB2_CPUMEMREGIONBASE, + PCI_HB0RB2_CPUIOREGIONBASE, + (PCI_HB0RB2_PCI_BASE), //RbPciBar + PCI_HB0RB2_PCIREGION_BASE , + PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1 + }, + + /* Port 3 */ + { + PCI_HB0RB3_ECAM_BASE, + 192, //BusBase + 255, //BusLimit + (PCI_HB0RB3_ECAM_BASE), //MemBase + (PCI_HB0RB3_ECAM_BASE + PCI_HB0RB3_ECAM_SIZE - 1), //MemLimit + (0), //IoBase + (0), //IoLimit + 0, + 0, + (PCI_HB0RB3_PCI_BASE), //RbPciBar + 0, + 0 + } + }, +{// HostBridge 1 + /* Port 0 */ + { + PCI_HB1RB0_ECAM_BASE, + 0, //BusBase + 0x1, //BusLimit + (PCI_HB1RB0_ECAM_BASE), //MemBase + (PCI_HB1RB0_ECAM_BASE + PCI_HB1RB0_ECAM_SIZE - 1), //MemLimit + (0), //IoBase + (0), //IoLimit + 0, + 0, + (PCI_HB1RB0_PCI_BASE), //RbPciBar + 0, + 0 + }, + /* Port 1 */ + { + PCI_HB1RB1_ECAM_BASE, + 0x2, //BusBase + 0x3, //BusLimit + (PCI_HB1RB1_ECAM_BASE), //MemBase + (PCI_HB1RB1_ECAM_BASE + PCI_HB1RB1_ECAM_SIZE - 1), //MemLimit + (0), //IoBase + (0), //IoLimit + 0, + 0, + (PCI_HB1RB1_PCI_BASE), //RbPciBar + 0, + 0 + }, + /* Port 2 */ + { + PCI_HB1RB2_ECAM_BASE, + 0x4, //BusBase + 0x5, //BusLimit + (PCI_HB1RB2_ECAM_BASE), //MemBase + (PCI_HB1RB2_ECAM_BASE + PCI_HB1RB2_ECAM_SIZE - 1), //MemLimit + (0), //IoBase + (0), //IoLimit + 0, + 0, + (PCI_HB1RB2_PCI_BASE), //RbPciBar + 0, + 0 + }, + + /* Port 3 */ + { + PCI_HB1RB3_ECAM_BASE, + 0x6, //BusBase + 0x7, //BusLimit + (PCI_HB1RB3_ECAM_BASE), //MemBase + (PCI_HB1RB3_ECAM_BASE + PCI_HB1RB3_ECAM_SIZE - 1), //MemLimit + (0), //IoBase + (0), //IoLimit + 0, + 0, + (PCI_HB1RB3_PCI_BASE), //RbPciBar + 0, + 0 + } + } +}; + diff --git a/Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf b/Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf new file mode 100644 index 0000000000..4d2dbbaf0d --- /dev/null +++ b/Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf @@ -0,0 +1,182 @@ +## @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformPciLib + FILE_GUID = 61b7276a-fc67-11e5-82fd-47ea9896dd5d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + +[Sources] + PlatformPciLib.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/Hisilicon/HisiPkg.dec + +[LibraryClasses] + PcdLib + +[FixedPcd] + gHisiTokenSpaceGuid.PcdHb1BaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PciHb0Rb0Base + gHisiTokenSpaceGuid.PciHb0Rb1Base + gHisiTokenSpaceGuid.PciHb0Rb2Base + gHisiTokenSpaceGuid.PciHb0Rb3Base + gHisiTokenSpaceGuid.PciHb0Rb4Base + gHisiTokenSpaceGuid.PciHb0Rb5Base + gHisiTokenSpaceGuid.PciHb0Rb6Base + gHisiTokenSpaceGuid.PciHb0Rb7Base + gHisiTokenSpaceGuid.PciHb1Rb0Base + gHisiTokenSpaceGuid.PciHb1Rb1Base + gHisiTokenSpaceGuid.PciHb1Rb2Base + gHisiTokenSpaceGuid.PciHb1Rb3Base + gHisiTokenSpaceGuid.PciHb1Rb4Base + gHisiTokenSpaceGuid.PciHb1Rb5Base + gHisiTokenSpaceGuid.PciHb1Rb6Base + gHisiTokenSpaceGuid.PciHb1Rb7Base + gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress + + gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize + + gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase + + gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase + + gHisiTokenSpaceGuid.PcdHb0Rb0IoBase + gHisiTokenSpaceGuid.PcdHb0Rb0IoSize + gHisiTokenSpaceGuid.PcdHb0Rb1IoBase + gHisiTokenSpaceGuid.PcdHb0Rb1IoSize + gHisiTokenSpaceGuid.PcdHb0Rb2IoBase + gHisiTokenSpaceGuid.PcdHb0Rb2IoSize + gHisiTokenSpaceGuid.PcdHb0Rb3IoBase + gHisiTokenSpaceGuid.PcdHb0Rb3IoSize + gHisiTokenSpaceGuid.PcdHb0Rb4IoBase + gHisiTokenSpaceGuid.PcdHb0Rb4IoSize + gHisiTokenSpaceGuid.PcdHb0Rb5IoBase + gHisiTokenSpaceGuid.PcdHb0Rb5IoSize + gHisiTokenSpaceGuid.PcdHb0Rb6IoBase + gHisiTokenSpaceGuid.PcdHb0Rb6IoSize + gHisiTokenSpaceGuid.PcdHb0Rb7IoBase + gHisiTokenSpaceGuid.PcdHb0Rb7IoSize + gHisiTokenSpaceGuid.PcdHb1Rb0IoBase + gHisiTokenSpaceGuid.PcdHb1Rb0IoSize + gHisiTokenSpaceGuid.PcdHb1Rb1IoBase + gHisiTokenSpaceGuid.PcdHb1Rb1IoSize + gHisiTokenSpaceGuid.PcdHb1Rb2IoBase + gHisiTokenSpaceGuid.PcdHb1Rb2IoSize + gHisiTokenSpaceGuid.PcdHb1Rb3IoBase + gHisiTokenSpaceGuid.PcdHb1Rb3IoSize + gHisiTokenSpaceGuid.PcdHb1Rb4IoBase + gHisiTokenSpaceGuid.PcdHb1Rb4IoSize + gHisiTokenSpaceGuid.PcdHb1Rb5IoBase + gHisiTokenSpaceGuid.PcdHb1Rb5IoSize + gHisiTokenSpaceGuid.PcdHb1Rb6IoBase + gHisiTokenSpaceGuid.PcdHb1Rb6IoSize + gHisiTokenSpaceGuid.PcdHb1Rb7IoBase + gHisiTokenSpaceGuid.PcdHb1Rb7IoSize diff --git a/Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfig.h b/Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfig.h new file mode 100644 index 0000000000..5f07116426 --- /dev/null +++ b/Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfig.h @@ -0,0 +1,31 @@ +/** @file +* +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __OEM_NIC_CONFIG_H__ +#define __OEM_NIC_CONFIG_H__ + +#define I2C_SLAVEADDR_EEPROM (0x52) + +#define I2C_OFFSET_EEPROM_ETH0 (0xc00) +#define I2C_OFFSET_EEPROM_ETH1 (I2C_OFFSET_EEPROM_ETH0 + 6) +#define I2C_OFFSET_EEPROM_ETH2 (I2C_OFFSET_EEPROM_ETH1 + 6) +#define I2C_OFFSET_EEPROM_ETH3 (I2C_OFFSET_EEPROM_ETH2 + 6) +#define I2C_OFFSET_EEPROM_ETH4 (I2C_OFFSET_EEPROM_ETH3 + 6) +#define I2C_OFFSET_EEPROM_ETH5 (I2C_OFFSET_EEPROM_ETH4 + 6) +#define I2C_OFFSET_EEPROM_ETH6 (I2C_OFFSET_EEPROM_ETH5 + 6) +#define I2C_OFFSET_EEPROM_ETH7 (I2C_OFFSET_EEPROM_ETH6 + 6) + + +#endif diff --git a/Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.c b/Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.c new file mode 100644 index 0000000000..d327fa4343 --- /dev/null +++ b/Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.c @@ -0,0 +1,173 @@ +/** @file +* +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include +#include +#include + +#include +#include +#include + +#define EEPROM_I2C_PORT 7 + +EFI_STATUS +EFIAPI OemGetMac (IN OUT EFI_MAC_ADDRESS *Mac, IN UINTN Port); + +EFI_STATUS +EFIAPI OemSetMac (IN EFI_MAC_ADDRESS *Mac, IN UINTN Port); + +HISI_BOARD_NIC_PROTOCOL mOemNicProtocol = { + .GetMac = OemGetMac, + .SetMac = OemSetMac, +}; + + +EFI_STATUS OemGetMacE2prom(IN UINT32 Port, OUT UINT8 *pucAddr) +{ + I2C_DEVICE stI2cDev = {0}; + EFI_STATUS Status; + UINT16 I2cOffset; + + Status = I2CInit(0, EEPROM_I2C_PORT, Normal); + if (EFI_ERROR(Status)) + { + DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2CInit failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status)); + return Status; + } + + I2cOffset = I2C_OFFSET_EEPROM_ETH0 + (Port * 6); + + stI2cDev.DeviceType = DEVICE_TYPE_E2PROM; + stI2cDev.Port = EEPROM_I2C_PORT; + stI2cDev.SlaveDeviceAddress = I2C_SLAVEADDR_EEPROM; + stI2cDev.Socket = 0; + Status = I2CRead(&stI2cDev, I2cOffset, 6, pucAddr); + if (EFI_ERROR(Status)) + { + DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2cRead failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status)); + return Status; + } + + return EFI_SUCCESS; +} + + +EFI_STATUS OemSetMacE2prom(IN UINT32 Port, IN UINT8 *pucAddr) +{ + I2C_DEVICE stI2cDev = {0}; + EFI_STATUS Status; + UINT16 I2cOffset; + + Status = I2CInit(0, EEPROM_I2C_PORT, Normal); + if (EFI_ERROR(Status)) + { + DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2CInit failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status)); + return Status; + } + + I2cOffset = I2C_OFFSET_EEPROM_ETH0 + (Port * 6); + + stI2cDev.DeviceType = DEVICE_TYPE_E2PROM; + stI2cDev.Port = EEPROM_I2C_PORT; + stI2cDev.SlaveDeviceAddress = I2C_SLAVEADDR_EEPROM; + stI2cDev.Socket = 0; + Status = I2CWrite(&stI2cDev, I2cOffset, 6, pucAddr); + if (EFI_ERROR(Status)) + { + DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2cWrite failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status)); + return Status; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI OemGetMac ( + IN OUT EFI_MAC_ADDRESS *Mac, + IN UINTN Port + ) +{ + EFI_STATUS Status; + + if (NULL == Mac) + { + DEBUG((EFI_D_ERROR, "[%a]:[%dL] Mac buffer is null!\n", __FUNCTION__, __LINE__)); + return EFI_INVALID_PARAMETER; + } + + //TODO: discard port number, only support one port + // Only 6 bytes are used + Status = OemGetMacE2prom(Port, Mac->Addr); + if ((EFI_ERROR(Status))) + { + DEBUG((EFI_D_ERROR, "[%a]:[%dL] Get mac failed!\n", __FUNCTION__, __LINE__)); + return Status; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI OemSetMac ( + IN EFI_MAC_ADDRESS *Mac, + IN UINTN Port + ) +{ + EFI_STATUS Status; + + if (NULL == Mac) + { + DEBUG((EFI_D_ERROR, "[%a]:[%dL] Mac buffer is null!\n", __FUNCTION__, __LINE__)); + return EFI_INVALID_PARAMETER; + } + + Status = OemSetMacE2prom(Port, Mac->Addr); + if ((EFI_ERROR(Status))) + { + DEBUG((EFI_D_ERROR, "[%a]:[%dL] Set mac failed!\n", __FUNCTION__, __LINE__)); + return Status; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +OemNicConfigEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + Status = gBS->InstallProtocolInterface( + &ImageHandle, + &gHisiBoardNicProtocolGuid, + EFI_NATIVE_INTERFACE, + &mOemNicProtocol + ); + + if(EFI_ERROR(Status)) + { + DEBUG((EFI_D_ERROR, "[%a]:[%dL] Install Protocol failed %r\n", __FUNCTION__, __LINE__, Status)); + return Status; + } + + return EFI_SUCCESS; +} + diff --git a/Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf b/Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf new file mode 100644 index 0000000000..df5adf17ca --- /dev/null +++ b/Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf @@ -0,0 +1,50 @@ +#/** @file +# +# Copyright (c) 2015, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = OemNicConfig + FILE_GUID = 3A23A929-1F38-4d04-8A01-38AD993EB2CE + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = OemNicConfigEntry + +[Sources.common] + OemNicConfigD02.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + + Silicon/Hisilicon/HisiPkg.dec + +[Protocols] + gHisiBoardNicProtocolGuid ##Produce + +[LibraryClasses] + UefiDriverEntryPoint + UefiBootServicesTableLib + DebugLib + IoLib + TimerLib + I2CLib + +[FixedPcd] + +[Depex] + TRUE + +[BuildOptions] + diff --git a/Platform/Hisilicon/D02/Pv660D02.dec b/Platform/Hisilicon/D02/Pv660D02.dec new file mode 100644 index 0000000000..5c34c2e537 --- /dev/null +++ b/Platform/Hisilicon/D02/Pv660D02.dec @@ -0,0 +1,44 @@ +#/** @file +# +# Copyright (c) 2015, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +# +# PV660 D02 Package +# +# +# + +[Defines] + DEC_SPECIFICATION = 0x00010005 + PACKAGE_NAME = Pv660D02Pkg + PACKAGE_GUID = 54392E0D-972B-459D-8CBE-DB381E7D1B98 + PACKAGE_VERSION = 0.1 + +[Includes] + Include + +[Ppis] + +[Protocols] + +[Guids] + + +[LibraryClasses] + +[PcdsFixedAtBuild] + +[PcdsFeatureFlag] + + diff --git a/Platform/Hisilicon/D02/Pv660D02.dsc b/Platform/Hisilicon/D02/Pv660D02.dsc new file mode 100644 index 0000000000..99d6972c75 --- /dev/null +++ b/Platform/Hisilicon/D02/Pv660D02.dsc @@ -0,0 +1,453 @@ +# +# Copyright (c) 2011-2012, ARM Limited. All rights reserved. +# Copyright (c) 2015, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = Pv660D02 + PLATFORM_GUID = E1AB8AC3-3EF1-4c6f-8D9F-ABE3EC67188E + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010005 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/Hisilicon/D02/$(PLATFORM_NAME).fdf + DEFINE INCLUDE_TFTP_COMMAND=1 + +!include Silicon/Hisilicon/Hisilicon.dsc.inc + +[LibraryClasses.common] + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf + ArmPlatformLib|Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf + + ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf + NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf + LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf + I2CLib|Silicon/Hisilicon/Library/I2CLib/I2CLib.inf + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf + + IpmiCmdLib|Silicon/Hisilicon/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.inf + + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf + DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf + UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf + IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf + +!ifdef $(FDT_ENABLE) + #FDTUpdateLib + FdtUpdateLib|Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf +!endif #$(FDT_ENABLE) + + CpldIoLib|Silicon/Hisilicon/Library/CpldIoLib/CpldIoLib.inf + + SerdesLib|Silicon/Hisilicon/Pv660/Library/Pv660Serdes/Pv660SerdesLib.inf + + TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf + RealTimeClockLib|Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf + OemMiscLib|Platform/Hisilicon/D02/Library/OemMiscLibD02/OemMiscLibD02.inf + OemAddressMapLib|Platform/Hisilicon/D02/Library/AddressMapPv660D02/OemAddressMapPv660D02.inf + PlatformSysCtrlLib|Silicon/Hisilicon/Pv660/Library/PlatformSysCtrlLibPv660/PlatformSysCtrlLibPv660.inf + + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf + PlatformBdsLib|Silicon/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf + +## GIC on D02/D03 is not fully ARM GIC compatible: IRQ cannot be cancelled when +## input signal is de-asserted, except for virtual timer interrupt IRQ #27. +## So we choose to use virtual timer instead of physical one as a workaround. +## This library instance is to override the original define in LibraryClasses.AARCH64 in Hisilicon.dsc.inc. +[LibraryClasses.AARCH64] + ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.inf + +[LibraryClasses.common.SEC] + ArmPlatformLib|Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + I2CLib|Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf + +[BuildOptions] + GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/Silicon/Hisilicon/Pv660/Include + + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + +[PcdsFeatureFlag.common] + + ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. + # It could be set FALSE to save size. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|FALSE + +[PcdsFixedAtBuild.common] + gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"D02" + + gArmPlatformTokenSpaceGuid.PcdCoreCount|8 + + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 + + # Stacks for MPCores in Secure World + gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0xE1000000 + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000 + + # Stacks for MPCores in Monitor Mode + gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0xE100FF00 + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100 + + # Stacks for MPCores in Normal World + gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0xE1000000 + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0xFF00 + + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x3FC00000 + + # Size of the region used by UEFI in permanent memory (Reserved 64MB) + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x10000000 + + ## SP805 Watchdog - Motherboard Watchdog + gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x801e0000 + + ## Serial Terminal + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x80300000 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + + gHisiTokenSpaceGuid.PcdUartClkInHz|200000000 + + gHisiTokenSpaceGuid.PcdSerialPortSendDelay|10000000 + + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1 + + gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0xa0040000 + gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000 + gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000 + gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D02 UEFI 16.08 RC1" + + gHisiTokenSpaceGuid.PcdSystemProductName|L"D02" + gHisiTokenSpaceGuid.PcdSystemVersion|L"Estuary" + gHisiTokenSpaceGuid.PcdBaseBoardProductName|L"D02" + gHisiTokenSpaceGuid.PcdBaseBoardVersion|L"Estuary" + + gHisiTokenSpaceGuid.PcdSlotPerChannelNum|0x2 + + # + # ARM PL390 General Interrupt Controller + # + gArmTokenSpaceGuid.PcdGicDistributorBase|0x8D000000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xFE000000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x8D100000 + + ## DTB address at spi flash + gHisiTokenSpaceGuid.FdtFileAddress|0xA4B00000 + + gHisiTokenSpaceGuid.PcdNORFlashBase|0x90000000 + gHisiTokenSpaceGuid.PcdNORFlashCachableSize|0x8000000 + + # + # ARM OS Loader + # + # Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux: + gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from SATA" + gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"EFI\GRUB2\grubaa64.efi" + gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"" + + # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut) + gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)" + gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()" + + # + # ARM Architectual Timer Frequency + # + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|50000000 + + gHisiTokenSpaceGuid.PcdSysControlBaseAddress|0x80010000 + gHisiTokenSpaceGuid.PcdMailBoxAddress|0x0000FFF8 + gHisiTokenSpaceGuid.PcdCpldBaseAddress|0x98000000 + gHisiTokenSpaceGuid.PcdSFCCFGBaseAddress|0xA6000000 + gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress|0xA4000000 + + gHisiTokenSpaceGuid.PcdPeriSubctrlAddress|0x80000000 + + gHisiTokenSpaceGuid.PcdMdioSubctrlAddress|0x80000000 + + ## 1 SCCL + 1 SICL + gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType|0x0 + gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x80020000 + gHisiTokenSpaceGuid.PcdTopOfLowMemory|0x80000000 + gHisiTokenSpaceGuid.PcdBottomOfHighMemory|0x1000000000 + gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x1 + + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 } + + ## SP804 DualTimer + gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|200 + gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|304 + gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0x80060000 + ## TODO: need to confirm the base for Performance and Metronome base for PV660 + gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0x80060000 + gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0x80060000 + + gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0x6 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB1RB0,bit5:HB1RB1,bit6:HB1RB2,bit7:HB1RB3 + gHisiTokenSpaceGuid.PcdHb1BaseAddress|0x400000000000 # 4T + + gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress|0x30000000000 + gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize|0x10000000000 + + gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress|0x22000000000 + gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize|0x10000000 + + gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress|0x24000000000 + gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize|0x10000000 + + gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress|0x26000000000 + gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize|0x10000000 + + gHisiTokenSpaceGuid.PciHb0Rb0Base|0xb0070000 + gHisiTokenSpaceGuid.PciHb0Rb1Base|0xb0080000 + gHisiTokenSpaceGuid.PciHb0Rb2Base|0xb0090000 + gHisiTokenSpaceGuid.PciHb0Rb3Base|0xb00a0000 + + gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xb0000000 + gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0x7feffff + + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xc0000000 + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x3feffff + + gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0x22008000000 + gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0x2400c000000 + + gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0x2200fff0000 + gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0x2400fff0000 + + gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0 + gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0 + gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0xffff #64K + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ +[Components.common] + # + # PEI Phase modules + # + ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + MdeModulePkg/Core/Pei/PeiMain.inf + MdeModulePkg/Universal/PCD/Pei/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + ArmPlatformPkg/PlatformPei/PlatformPeim.inf + Platform/Hisilicon/D02/MemoryInitPei/MemoryInitPeim.inf + ArmPkg/Drivers/CpuPei/CpuPei.inf + IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf + MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf + Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf + + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { + + NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf + } + + # + # DXE + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf + } + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + + Silicon/Hisilicon/Pv660/Drivers/IoInitDxe/IoInitDxe.inf + + # + # Architectural Protocols + # + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + + Silicon/Hisilicon/Drivers/NorFlashDxe/NorFlashDxe.inf + + + Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf + + Platform/Hisilicon/D02/Drivers/SFC/SfcDxeDriver.inf + + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf + Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + } + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + # Simple TextIn/TextOut for UEFI Terminal + EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf + + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + + ArmPkg/Drivers/TimerDxe/TimerDxe.inf + ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf + + IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf + # + #ACPI + # + MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + + Silicon/Hisilicon/Pv660/Pv660AcpiTables/AcpiTables.inf + Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf + Silicon/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.inf + + #Pci Express + Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitDxe.inf + Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf { + + NULL|Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf + } + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + + # + #network + # + Platform/Hisilicon/D02/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.inf + MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf + MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf + MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf + MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf + MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf + MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf + MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf + MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf + MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.inf + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + Silicon/Hisilicon/Pv660/Drivers/SasInitDxe/SasV1Init.inf + + MdeModulePkg/Application/HelloWorld/HelloWorld.inf + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + + Platform/Hisilicon/D02/Drivers/AtaAtapiPassThru/AtaAtapiPassThru.inf + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + + # + # USB Support + # + Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf + Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf + Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf + +!ifdef $(FDT_ENABLE) + Silicon/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf { + + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + } +!endif #$(FDT_ENABLE) + + # + # Memory test + # + MdeModulePkg/Universal/MemoryTest/GenericMemoryTestDxe/GenericMemoryTestDxe.inf + + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf + + # + # UEFI application (Shell Embedded Boot Loader) + # + ShellPkg/Application/Shell/Shell.inf { + + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf +!ifdef $(INCLUDE_DP) + NULL|ShellPkg/Library/UefiDpLib/UefiDpLib.inf +!endif #$(INCLUDE_DP) +!ifdef $(INCLUDE_TFTP_COMMAND) + NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf +!endif #$(INCLUDE_TFTP_COMMAND) + + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 + } diff --git a/Platform/Hisilicon/D02/Pv660D02.fdf b/Platform/Hisilicon/D02/Pv660D02.fdf new file mode 100644 index 0000000000..2d6cdcd9f6 --- /dev/null +++ b/Platform/Hisilicon/D02/Pv660D02.fdf @@ -0,0 +1,317 @@ +# +# Copyright (c) 2011, 2012, ARM Limited. All rights reserved. +# Copyright (c) 2015, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[DEFINES] + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ + +[FD.PV660D02] +BaseAddress = 0xA4800000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. + +Size = 0x00300000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +ErasePolarity = 1 + +# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x00010000 +NumBlocks = 0x30 + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +################################################################################ + +0x00000000|0x00040000 +gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize +FILE = Platform/Hisilicon/D02/Sec/FVMAIN_SEC.Fv + +0x00040000|0x00240000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT + +## Place for Trusted Firmware +0x00280000|0x00020000 +gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base +FILE = Platform/Hisilicon/D02/bl1.bin +0x002a0000|0x00020000 +FILE = Platform/Hisilicon/D02/fip.bin + +0x002e0000|0x0000e000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +DATA = { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid = + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0x20000 + 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + #Signature "_FVH" #Attributes + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, + #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0x36, 0x09, 0x00, 0x00, 0x00, 0x02, + #Blockmap[0]: 2 Blocks * 0x10000 Bytes / Block + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, + #Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER gEfiVariableGuid + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, + #Size: 0xe000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xdFB8 + 0xB8, 0xdF, 0x00, 0x00, + #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +0x002ee000|0x00002000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +#NV_FTW_WORKING +DATA = { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid = + 0x2B, 0x29, 0x58, 0x9E, 0x68, 0x7C, 0x7D, 0x49, + 0xA0, 0xCE, 0x65, 0x0 , 0xFD, 0x9F, 0x1B, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved + 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0 + 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +0x002f0000|0x00010000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +[FV.FvMain] +BlockSize = 0x40 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 16 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + INF Silicon/Hisilicon/Pv660/Drivers/IoInitDxe/IoInitDxe.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF Silicon/Hisilicon/Drivers/NorFlashDxe/NorFlashDxe.inf + INF Platform/Hisilicon/D02/Drivers/SFC/SfcDxeDriver.inf + + INF Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf + + # PCI Express + INF Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitDxe.inf + INF Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + + INF Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + ## Sometimes we need to switch to emulated variable store for debug reason + #INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf + + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + # Simple TextIn/TextOut for UEFI Terminal + # This is simpler than generic serial console and may be used for debug + #INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf + + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatBinPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + INF IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf + + INF Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.inf + INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + INF Silicon/Hisilicon/Pv660/Drivers/SasInitDxe/SasV1Init.inf + + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + INF Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf + INF Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf + INF Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf + + # + #ACPI + # + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf + + INF RuleOverride=ACPITABLE Silicon/Hisilicon/Pv660/Pv660AcpiTables/AcpiTables.inf + INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf + + # + #Network + # + INF Platform/Hisilicon/D02/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.inf + + INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf + INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf + INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf + INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf + INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf + INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf + INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf + INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf + INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf + +!ifdef $(FDT_ENABLE) + INF Silicon/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf +!endif #$(FDT_ENABLE) + + INF Silicon/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.inf + + # + #Sata + # + INF Platform/Hisilicon/D02/Drivers/AtaAtapiPassThru/AtaAtapiPassThru.inf + INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + + # + # USB Support + # + INF Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf + INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # + # Build Shell from latest source code instead of prebuilt binary + # + INF ShellPkg/Application/Shell/Shell.inf + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + + INF MdeModulePkg/Universal/MemoryTest/GenericMemoryTestDxe/GenericMemoryTestDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf + +[FV.FVMAIN_COMPACT] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + INF MdeModulePkg/Core/Pei/PeiMain.inf + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf + INF Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf + INF Platform/Hisilicon/D02/MemoryInitPei/MemoryInitPeim.inf + INF ArmPkg/Drivers/CpuPei/CpuPei.inf + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf + + INF Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } + } + + +!include Silicon/Hisilicon/Hisilicon.fdf.inc + diff --git a/Platform/Hisilicon/D03/D03.dec b/Platform/Hisilicon/D03/D03.dec new file mode 100644 index 0000000000..8b08a32773 --- /dev/null +++ b/Platform/Hisilicon/D03/D03.dec @@ -0,0 +1,44 @@ +#/** @file +# +# Copyright (c) 2015, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +# +# D03 Package +# +# +# + +[Defines] + DEC_SPECIFICATION = 0x00010005 + PACKAGE_NAME = D03Pkg + PACKAGE_GUID = D42C5D53-63FA-4FBA-9FD4-E8EA684FD3BE + PACKAGE_VERSION = 0.1 + +[Includes] + Include + +[Ppis] + +[Protocols] + +[Guids] + + +[LibraryClasses] + +[PcdsFixedAtBuild] + +[PcdsFeatureFlag] + + diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc new file mode 100644 index 0000000000..fc675c17ec --- /dev/null +++ b/Platform/Hisilicon/D03/D03.dsc @@ -0,0 +1,525 @@ +# +# Copyright (c) 2011-2012, ARM Limited. All rights reserved. +# Copyright (c) 2015, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = D03 + PLATFORM_GUID = e5003abd-8809-6194-ac3d-a6a99ff52478 + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010005 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/Hisilicon/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf + DEFINE INCLUDE_TFTP_COMMAND=1 + +!include Silicon/Hisilicon/Hisilicon.dsc.inc + +[LibraryClasses.common] + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf + ArmPlatformLib|Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf + + ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf + NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf + LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf + + + I2CLib|Silicon/Hisilicon/Library/I2CLib/I2CLib.inf + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf + + IpmiCmdLib|Silicon/Hisilicon/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.inf + + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf + DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf + UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf + IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf + + + +!ifdef $(FDT_ENABLE) + #FDTUpdateLib + FdtUpdateLib|Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf +!endif #$(FDT_ENABLE) + + CpldIoLib|Silicon/Hisilicon/Library/CpldIoLib/CpldIoLib.inf + + SerdesLib|Silicon/Hisilicon/Hi1610/Library/Hi1610Serdes/Hi1610SerdesLib.inf + + TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf + RealTimeClockLib|Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf + + OemMiscLib|Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf + OemAddressMapLib|Platform/Hisilicon/D03/Library/OemAddressMap2P/OemAddressMap2PHi1610.inf + PlatformSysCtrlLib|Silicon/Hisilicon/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.inf + + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf + PlatformBdsLib|Silicon/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf + + # USB Requirements + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + + LpcLib|Silicon/Hisilicon/Hi1610/Library/LpcLib/LpcLib.inf + SerialPortLib|Silicon/Hisilicon/Hi1610/Library/Uart/LpcSerialPortLib/LpcSerialPortLib.inf + +## GIC on D02/D03 is not fully ARM GIC compatible: IRQ cannot be cancelled when +## input signal is de-asserted, except for virtual timer interrupt IRQ #27. +## So we choose to use virtual timer instead of physical one as a workaround. +## This library instance is to override the original define in LibraryClasses.AARCH64 in Hisilicon.dsc.inc. +[LibraryClasses.AARCH64] + ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.inf + +[LibraryClasses.common.SEC] + ArmPlatformLib|Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf + + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + I2CLib|Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf + SerialPortLib|Silicon/Hisilicon/Hi1610/Library/Uart/LpcSerialPortLib/LpcSerialPortLib.inf + +[BuildOptions] + GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/Silicon/Hisilicon/Hi1610/Include + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + +[PcdsFeatureFlag.common] + + ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. + # It could be set FALSE to save size. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE + gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable|TRUE + +[PcdsFixedAtBuild.common] + gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"D03" + + gArmPlatformTokenSpaceGuid.PcdCoreCount|8 + + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 + + # Stacks for MPCores in Secure World + gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x81000000 + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000 + + # Stacks for MPCores in Monitor Mode + gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0x8100FF00 + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100 + + # Stacks for MPCores in Normal World + gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x81000000 + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0xFF00 + + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000 + + + gArmTokenSpaceGuid.PcdSystemMemorySize|0x3FC00000 + + + # Size of the region used by UEFI in permanent memory (Reserved 64MB) + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x10000000 + + gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|1 + gHisiTokenSpaceGuid.PcdSlotPerChannelNum|0x2 + + + gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0x7 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB1RB0,bit5:HB1RB1,bit6:HB1RB2,bit7:HB1RB3 + + ## SP805 Watchdog - Motherboard Watchdog + gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x601e0000 + + ## Serial Terminal + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x2F8 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + + gHisiTokenSpaceGuid.PcdUartClkInHz|1846100 + + gHisiTokenSpaceGuid.PcdSerialPortSendDelay|10000000 + + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1 + + + gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0xa0040000 + gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000 + gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000 + gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000 + + + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D03 UEFI 16.12 Release" + + gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18" + + gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L"1.12" + + gHisiTokenSpaceGuid.PcdSystemProductName|L"D03" + gHisiTokenSpaceGuid.PcdSystemVersion|L"Estuary" + gHisiTokenSpaceGuid.PcdBaseBoardProductName|L"D03" + gHisiTokenSpaceGuid.PcdBaseBoardVersion|L"Estuary" + + gHisiTokenSpaceGuid.PcdCPUInfo|L"Hi1612" + + # + # ARM PL390 General Interrupt Controller + # + + gArmTokenSpaceGuid.PcdGicDistributorBase|0x4D000000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xFE000000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x4D100000 + + # + # ARM OS Loader + # + # Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux: + gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from SATA" + gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"EFI\GRUB2\grubaa64.efi" + gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"" + + # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut) + gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)" + gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()" + + # + # ARM Architectual Timer Frequency + # + # Set it to 0 so that the code will read frequence from register and be + # adapted to 66M and 50M boards + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0 + + + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 } + + gHisiTokenSpaceGuid.PcdSysControlBaseAddress|0x40010000 + gHisiTokenSpaceGuid.PcdMailBoxAddress|0x0000FFF8 + + gHisiTokenSpaceGuid.PcdCpldBaseAddress|0x78000000 + + gHisiTokenSpaceGuid.PcdSFCCFGBaseAddress|0xA6000000 + gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress|0xA4000000 + + + gHisiTokenSpaceGuid.PcdPeriSubctrlAddress|0x40000000 + + + gHisiTokenSpaceGuid.PcdMdioSubctrlAddress|0x60000000 + + gHisiTokenSpaceGuid.FdtFileAddress|0xA47C0000 + + gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType|0x1 + + gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x80010000 + + gHisiTokenSpaceGuid.PcdTopOfLowMemory|0x40000000 + + gHisiTokenSpaceGuid.PcdBottomOfHighMemory|0x2000000000 + + gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x1 + gHisiTokenSpaceGuid.PcdNumaEnable|0 + + gHisiTokenSpaceGuid.PcdHb1BaseAddress|0x40000000000 + + + gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress|0xB0000000 + gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize|0x8000000 + + gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress|0xB0000000 + gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize|0x10000000 + + gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress|0xA0000000 + gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize|0x10000000 + + gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress|0xAC000000 + gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize|0x4000000 + + gHisiTokenSpaceGuid.PciHb0Rb0Base|0xa0090000 + gHisiTokenSpaceGuid.PciHb0Rb1Base|0xa0200000 + gHisiTokenSpaceGuid.PciHb0Rb2Base|0xa00a0000 + gHisiTokenSpaceGuid.PciHb0Rb3Base|0xa00b0000 + + gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress|0xb2000000 + gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0x5feffff + + gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xb8000000 + gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0x5feffff + + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xaa000000 + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x5feffff + + gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xB2000000 + gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xB8000000 + gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xAA000000 + + gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0xb7ff0000 + gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0xbdff0000 + gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xAfff0000 + + gHisiTokenSpaceGuid.PcdHb0Rb0IoBase|0 + gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0 + gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0 + gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0xffff #64K + + gHisiTokenSpaceGuid.Pcdsoctype|0x1610 + ## SP804 DualTimer + gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|200 + gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|0xb0 + gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0x40060000 + ## TODO: need to confirm the base for Performance and Metronome base for PV660 + gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0x40060000 + gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0x40060000 + + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ +[Components.common] + + # + # SEC + # + + # + # PEI Phase modules + # + ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + MdeModulePkg/Core/Pei/PeiMain.inf + MdeModulePkg/Universal/PCD/Pei/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + Platform/Hisilicon/D03/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf + + ArmPlatformPkg/PlatformPei/PlatformPeim.inf + + Platform/Hisilicon/D03/MemoryInitPei/MemoryInitPeim.inf + ArmPkg/Drivers/CpuPei/CpuPei.inf + IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf + MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + + Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf + Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf + + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { + + NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf + } + + # + # DXE + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf + } + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + + Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf + + # + # Architectural Protocols + # + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + + Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf + + Platform/Hisilicon/D03/Drivers/SFC/SfcDxeDriver.inf + + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf + Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + } + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf { + + CpldIoLib|Silicon/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.inf + } + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + # Simple TextIn/TextOut for UEFI Terminal + EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf + + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + + ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf + IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf + # + #ACPI + # + MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + + Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf + Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf + + # + # Usb Support + # + Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + Platform/Hisilicon/D03/Drivers/OhciDxe/OhciDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + Platform/Hisilicon/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.inf + + # + #network + # + Platform/Hisilicon/D03/Drivers/Net/SnpPV660Dxe/SnpPV600Dxe.inf + + MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf + MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf + MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf + MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf + MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf + MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf + MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf + MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf + MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf + + Platform/Hisilicon/D03/Drivers/Sas/SasDxeDriver.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + MdeModulePkg/Application/HelloWorld/HelloWorld.inf + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + + Platform/Hisilicon/D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf + Platform/Hisilicon/D03/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf + Platform/Hisilicon/D03/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf + + Platform/Hisilicon/D03/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf + + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf + +!ifdef $(FDT_ENABLE) + Silicon/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf { + + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + } +!endif #$(FDT_ENABLE) + + #PCIe Support + Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf { + + NULL|Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf + } + Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf + Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf { + + NULL|Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf + } + + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + + Platform/Hisilicon/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf + Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf + Platform/Hisilicon/D03/Drivers/Sm750Dxe/UefiSmi.inf + + Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf + + + Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf + + # + # Memory test + # + MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf + + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf + + # + # UEFI application (Shell Embedded Boot Loader) + # + ShellPkg/Application/Shell/Shell.inf { + + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf +!ifdef $(INCLUDE_DP) + NULL|ShellPkg/Library/UefiDpLib/UefiDpLib.inf +!endif #$(INCLUDE_DP) +!ifdef $(INCLUDE_TFTP_COMMAND) + NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf +!endif #$(INCLUDE_TFTP_COMMAND) + + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 + } diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf new file mode 100644 index 0000000000..d831b42a1a --- /dev/null +++ b/Platform/Hisilicon/D03/D03.fdf @@ -0,0 +1,334 @@ +# +# Copyright (c) 2011, 2012, ARM Limited. All rights reserved. +# Copyright (c) 2015, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[DEFINES] + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ + +[FD.D03] +BaseAddress = 0xA4800000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. + +Size = 0x00300000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +ErasePolarity = 1 + +# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x00010000 +NumBlocks = 0x30 + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +################################################################################ + +0x00000000|0x00040000 +gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize +FILE = Platform/Hisilicon/D03/Sec/FVMAIN_SEC.Fv + +0x00040000|0x00240000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT + +0x00280000|0x00020000 +gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base +FILE = Platform/Hisilicon/D03/bl1.bin +0x002A0000|0x00020000 +FILE = Platform/Hisilicon/D03/fip.bin + +0x002D0000|0x0000E000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +DATA = { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid = + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0x20000 + 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + #Signature "_FVH" #Attributes + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, + #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0x36, 0x09, 0x00, 0x00, 0x00, 0x02, + #Blockmap[0]: 2 Blocks * 0x10000 Bytes / Block + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, + #Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER gEfiVariableGuid + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, + #Size: 0xe000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xdFB8 + 0xB8, 0xdF, 0x00, 0x00, + #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +0x002DE000|0x00002000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +#NV_FTW_WORKING +DATA = { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid = + 0x2B, 0x29, 0x58, 0x9E, 0x68, 0x7C, 0x7D, 0x49, + 0xA0, 0xCE, 0x65, 0x0 , 0xFD, 0x9F, 0x1B, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved + 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0 + 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +0x002E0000|0x00010000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + +0x002F0000|0x00010000 +FILE = Platform/Hisilicon/D03/CustomData.Fv + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +[FV.FvMain] +BlockSize = 0x40 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 16 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + INF Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF Platform/Hisilicon/D03/Drivers/SFC/SfcDxeDriver.inf + + INF Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf + + + INF Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + # Simple TextIn/TextOut for UEFI Terminal + + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatBinPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + INF IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf + + # + # Usb Support + # + + INF Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf + INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + INF Platform/Hisilicon/D03/Drivers/OhciDxe/OhciDxe.inf + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + INF Platform/Hisilicon/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.inf + INF Platform/Hisilicon/D03/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + INF Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf + + INF Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf + INF Platform/Hisilicon/D03/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf + INF Platform/Hisilicon/D03/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf + + INF Platform/Hisilicon/D03/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf + + + INF Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf + + INF Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf + + # + #ACPI + # + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf + + INF RuleOverride=ACPITABLE Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/AcpiTablesHi1610.inf + INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf + + # + #Network + # + + INF Platform/Hisilicon/D03/Drivers/Net/SnpPV660Dxe/SnpPV600Dxe.inf + + INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf + INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf + INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf + INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf + INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf + INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf + INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf + INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf + INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf + +!ifdef $(FDT_ENABLE) + INF Silicon/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf +!endif #$(FDT_ENABLE) + + # + # PCI Support + # + INF Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf + INF Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf + INF Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + + INF Platform/Hisilicon/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf + # VGA Driver + # + INF Platform/Hisilicon/D03/Drivers/Sm750Dxe/UefiSmi.inf + + INF Platform/Hisilicon/D03/Drivers/Sas/SasDxeDriver.inf + + # + # Build Shell from latest source code instead of prebuilt binary + # + INF ShellPkg/Application/Shell/Shell.inf + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + + INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf + +[FV.FVMAIN_COMPACT] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + INF MdeModulePkg/Core/Pei/PeiMain.inf + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf + + INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + + INF Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf + + INF Platform/Hisilicon/D03/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf + INF Platform/Hisilicon/D03/MemoryInitPei/MemoryInitPeim.inf + INF ArmPkg/Drivers/CpuPei/CpuPei.inf + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf + INF Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf + + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } + } + + +!include Silicon/Hisilicon/Hisilicon.fdf.inc + diff --git a/Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig.h b/Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig.h new file mode 100644 index 0000000000..46c77d3061 --- /dev/null +++ b/Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig.h @@ -0,0 +1,40 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __OEM_NIC_CONFIG_H__ +#define __OEM_NIC_CONFIG_H__ + +#define I2C_SLAVEADDR_EEPROM (0x52) + +#define I2C_OFFSET_EEPROM_ETH0 (0xc00) +#define I2C_OFFSET_EEPROM_ETH1 (I2C_OFFSET_EEPROM_ETH0 + 6) +#define I2C_OFFSET_EEPROM_ETH2 (I2C_OFFSET_EEPROM_ETH1 + 6) +#define I2C_OFFSET_EEPROM_ETH3 (I2C_OFFSET_EEPROM_ETH2 + 6) +#define I2C_OFFSET_EEPROM_ETH4 (I2C_OFFSET_EEPROM_ETH3 + 6) +#define I2C_OFFSET_EEPROM_ETH5 (I2C_OFFSET_EEPROM_ETH4 + 6) +#define I2C_OFFSET_EEPROM_ETH6 (I2C_OFFSET_EEPROM_ETH5 + 6) +#define I2C_OFFSET_EEPROM_ETH7 (I2C_OFFSET_EEPROM_ETH6 + 6) + +#define MAC_ADDR_LEN 6 + +#pragma pack(1) +typedef struct { + UINT16 Crc16; + UINT16 MacLen; + UINT8 Mac[MAC_ADDR_LEN]; +} NIC_MAC_ADDRESS; +#pragma pack() + +#endif diff --git a/Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c b/Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c new file mode 100644 index 0000000000..dcaf3aa827 --- /dev/null +++ b/Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.c @@ -0,0 +1,362 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define EEPROM_I2C_PORT 6 +#define EEPROM_PAGE_SIZE 0x40 + +EFI_STATUS +EFIAPI OemGetMac2P (IN OUT EFI_MAC_ADDRESS *Mac, IN UINTN Port); + +EFI_STATUS +EFIAPI OemSetMac2P (IN EFI_MAC_ADDRESS *Mac, IN UINTN Port); + +EFI_STATUS OemGetMacE2prom(IN UINT32 Port, OUT UINT8 *pucAddr); +EFI_STATUS OemSetMacE2prom(IN UINT32 Port, IN UINT8 *pucAddr); + +volatile unsigned char g_2pserveraddr[4][6] = +{ + {0x00, 0x18, 0x16, 0x29, 0x11, 0x00}, + {0x00, 0x18, 0x16, 0x29, 0x11, 0x01}, + {0x00, 0x18, 0x16, 0x29, 0x11, 0x02}, + {0x00, 0x18, 0x16, 0x29, 0x11, 0x03} +}; + +UINT16 crc_tab[256] = { + 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50A5, 0x60C6, 0x70E7, + 0x8108, 0x9129, 0xA14A, 0xB16B, 0xC18C, 0xD1AD, 0xE1CE, 0xF1EF, + 0x1231, 0x0210, 0x3273, 0x2252, 0x52B5, 0x4294, 0x72F7, 0x62D6, + 0x9339, 0x8318, 0xB37B, 0xA35A, 0xD3BD, 0xC39C, 0xF3FF, 0xE3DE, + 0x2462, 0x3443, 0x0420, 0x1401, 0x64E6, 0x74C7, 0x44A4, 0x5485, + 0xA56A, 0xB54B, 0x8528, 0x9509, 0xE5EE, 0xF5CF, 0xC5AC, 0xD58D, + 0x3653, 0x2672, 0x1611, 0x0630, 0x76D7, 0x66F6, 0x5695, 0x46B4, + 0xB75B, 0xA77A, 0x9719, 0x8738, 0xF7DF, 0xE7FE, 0xD79D, 0xC7BC, + 0x48C4, 0x58E5, 0x6886, 0x78A7, 0x0840, 0x1861, 0x2802, 0x3823, + 0xC9CC, 0xD9ED, 0xE98E, 0xF9AF, 0x8948, 0x9969, 0xA90A, 0xB92B, + 0x5AF5, 0x4AD4, 0x7AB7, 0x6A96, 0x1A71, 0x0A50, 0x3A33, 0x2A12, + 0xDBFD, 0xCBDC, 0xFBBF, 0xEB9E, 0x9B79, 0x8B58, 0xBB3B, 0xAB1A, + 0x6CA6, 0x7C87, 0x4CE4, 0x5CC5, 0x2C22, 0x3C03, 0x0C60, 0x1C41, + 0xEDAE, 0xFD8F, 0xCDEC, 0xDDCD, 0xAD2A, 0xBD0B, 0x8D68, 0x9D49, + 0x7E97, 0x6EB6, 0x5ED5, 0x4EF4, 0x3E13, 0x2E32, 0x1E51, 0x0E70, + 0xFF9F, 0xEFBE, 0xDFDD, 0xCFFC, 0xBF1B, 0xAF3A, 0x9F59, 0x8F78, + 0x9188, 0x81A9, 0xB1CA, 0xA1EB, 0xD10C, 0xC12D, 0xF14E, 0xE16F, + 0x1080, 0x00A1, 0x30C2, 0x20E3, 0x5004, 0x4025, 0x7046, 0x6067, + 0x83B9, 0x9398, 0xA3FB, 0xB3DA, 0xC33D, 0xD31C, 0xE37F, 0xF35E, + 0x02B1, 0x1290, 0x22F3, 0x32D2, 0x4235, 0x5214, 0x6277, 0x7256, + 0xB5EA, 0xA5CB, 0x95A8, 0x8589, 0xF56E, 0xE54F, 0xD52C, 0xC50D, + 0x34E2, 0x24C3, 0x14A0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, + 0xA7DB, 0xB7FA, 0x8799, 0x97B8, 0xE75F, 0xF77E, 0xC71D, 0xD73C, + 0x26D3, 0x36F2, 0x0691, 0x16B0, 0x6657, 0x7676, 0x4615, 0x5634, + 0xD94C, 0xC96D, 0xF90E, 0xE92F, 0x99C8, 0x89E9, 0xB98A, 0xA9AB, + 0x5844, 0x4865, 0x7806, 0x6827, 0x18C0, 0x08E1, 0x3882, 0x28A3, + 0xCB7D, 0xDB5C, 0xEB3F, 0xFB1E, 0x8BF9, 0x9BD8, 0xABBB, 0xBB9A, + 0x4A75, 0x5A54, 0x6A37, 0x7A16, 0x0AF1, 0x1AD0, 0x2AB3, 0x3A92, + 0xFD2E, 0xED0F, 0xDD6C, 0xCD4D, 0xBDAA, 0xAD8B, 0x9DE8, 0x8DC9, + 0x7C26, 0x6C07, 0x5C64, 0x4C45, 0x3CA2, 0x2C83, 0x1CE0, 0x0CC1, + 0xEF1F, 0xFF3E, 0xCF5D, 0xDF7C, 0xAF9B, 0xBFBA, 0x8FD9, 0x9FF8, + 0x6E17, 0x7E36, 0x4E55, 0x5E74, 0x2E93, 0x3EB2, 0x0ED1, 0x1EF0, +}; + +UINT16 make_crc_checksum(UINT8 *buf, UINT32 len) +{ + UINT16 StartCRC = 0; + + if (len > (512 * 1024)) + { + return 0; + } + + if (NULL == buf) + { + return 0; + } + + while (len) + { + StartCRC = crc_tab[((UINT8)((StartCRC >> 8) & 0xff)) ^ *(buf++)] ^ ((UINT16)(StartCRC << 8)); + len--; + } + + return StartCRC; +} + + +EFI_STATUS OemGetMacE2prom(IN UINT32 Port, OUT UINT8 *pucAddr) +{ + I2C_DEVICE stI2cDev = {0}; + EFI_STATUS Status; + UINT16 I2cOffset; + UINT16 crc16; + NIC_MAC_ADDRESS stMacDesc = {0}; + UINT16 RemainderMacOffset; + UINT16 LessSizeOfPage; + + Status = I2CInit(0, EEPROM_I2C_PORT, Normal); + if (EFI_ERROR(Status)) + { + DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2CInit failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status)); + return Status; + } + + I2cOffset = I2C_OFFSET_EEPROM_ETH0 + (Port * sizeof(NIC_MAC_ADDRESS)); + + stI2cDev.DeviceType = DEVICE_TYPE_E2PROM; + stI2cDev.Port = EEPROM_I2C_PORT; + stI2cDev.SlaveDeviceAddress = I2C_SLAVEADDR_EEPROM; + stI2cDev.Socket = 0; + RemainderMacOffset = I2cOffset % EEPROM_PAGE_SIZE; + LessSizeOfPage = EEPROM_PAGE_SIZE - RemainderMacOffset; + //The length of NIC_MAC_ADDRESS is 10 bytes long, + //It surly less than EEPROM page size, so we could + //code as bellow, check the address whether across the page boundary, + //and split the data when across page boundary. + if (sizeof(NIC_MAC_ADDRESS) <= LessSizeOfPage) { + Status = I2CRead(&stI2cDev, I2cOffset, sizeof(NIC_MAC_ADDRESS), (UINT8 *)&stMacDesc); + } else { + Status = I2CRead(&stI2cDev, I2cOffset, LessSizeOfPage, (UINT8 *)&stMacDesc); + if (!(EFI_ERROR(Status))) { + Status |= I2CRead( + &stI2cDev, + I2cOffset + LessSizeOfPage, + sizeof(NIC_MAC_ADDRESS) - LessSizeOfPage, + (UINT8 *)&stMacDesc + LessSizeOfPage + ); + } + } + if (EFI_ERROR(Status)) + { + DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2cRead failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status)); + return Status; + } + + crc16 = make_crc_checksum((UINT8 *)&(stMacDesc.MacLen), sizeof(stMacDesc.MacLen) + sizeof(stMacDesc.Mac)); + if ((crc16 != stMacDesc.Crc16) || (0 == crc16)) + { + return EFI_NOT_FOUND; + } + + gBS->CopyMem((VOID *)(pucAddr), (VOID *)(stMacDesc.Mac), MAC_ADDR_LEN); + + + return EFI_SUCCESS; +} + + +EFI_STATUS OemSetMacE2prom(IN UINT32 Port, IN UINT8 *pucAddr) +{ + I2C_DEVICE stI2cDev = {0}; + EFI_STATUS Status; + UINT16 I2cOffset; + NIC_MAC_ADDRESS stMacDesc = {0}; + + + stMacDesc.MacLen = MAC_ADDR_LEN; + UINT16 RemainderMacOffset; + UINT16 LessSizeOfPage; + gBS->CopyMem((VOID *)(stMacDesc.Mac), (VOID *)pucAddr, MAC_ADDR_LEN); + + stMacDesc.Crc16 = make_crc_checksum((UINT8 *)&(stMacDesc.MacLen), sizeof(stMacDesc.MacLen) + MAC_ADDR_LEN); + + Status = I2CInit(0, EEPROM_I2C_PORT, Normal); + if (EFI_ERROR(Status)) + { + DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2CInit failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status)); + return Status; + } + + I2cOffset = I2C_OFFSET_EEPROM_ETH0 + (Port * sizeof(NIC_MAC_ADDRESS)); + + stI2cDev.DeviceType = DEVICE_TYPE_E2PROM; + stI2cDev.Port = EEPROM_I2C_PORT; + stI2cDev.SlaveDeviceAddress = I2C_SLAVEADDR_EEPROM; + stI2cDev.Socket = 0; + RemainderMacOffset = I2cOffset % EEPROM_PAGE_SIZE; + LessSizeOfPage = EEPROM_PAGE_SIZE - RemainderMacOffset; + //The length of NIC_MAC_ADDRESS is 10 bytes long, + //It surly less than EEPROM page size, so we could + //code as bellow, check the address whether across the page boundary, + //and split the data when across page boundary. + if (sizeof(NIC_MAC_ADDRESS) <= LessSizeOfPage) { + Status = I2CWrite(&stI2cDev, I2cOffset, sizeof(NIC_MAC_ADDRESS), (UINT8 *)&stMacDesc); + } else { + Status = I2CWrite(&stI2cDev, I2cOffset, LessSizeOfPage, (UINT8 *)&stMacDesc); + if (!(EFI_ERROR(Status))) { + Status |= I2CWrite( + &stI2cDev, + I2cOffset + LessSizeOfPage, + sizeof(NIC_MAC_ADDRESS) - LessSizeOfPage, + (UINT8 *)&stMacDesc + LessSizeOfPage + ); + } + } + if (EFI_ERROR(Status)) + { + DEBUG((EFI_D_ERROR, "[%a]:[%dL] Call I2cWrite failed! p1=0x%x.\n", __FUNCTION__, __LINE__, Status)); + return Status; + } + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI OemGetMac2P ( + IN OUT EFI_MAC_ADDRESS *Mac, + IN UINTN Port + ) +{ + EFI_STATUS Status; + + if (NULL == Mac) + { + DEBUG((EFI_D_ERROR, "[%a]:[%dL] Mac buffer is null!\n", __FUNCTION__, __LINE__)); + return EFI_INVALID_PARAMETER; + } + + Status = OemGetMacE2prom(Port, Mac->Addr); + if ((EFI_ERROR(Status))) + { + DEBUG((EFI_D_ERROR, "[%a]:[%dL] Get mac failed!\n", __FUNCTION__, __LINE__)); + + Mac->Addr[0] = 0x00; + Mac->Addr[1] = 0x18; + Mac->Addr[2] = 0x82; + Mac->Addr[3] = 0x2F; + Mac->Addr[4] = 0x02; + Mac->Addr[5] = Port; + return Status; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI OemSetMac2P ( + IN EFI_MAC_ADDRESS *Mac, + IN UINTN Port + ) +{ + EFI_STATUS Status; + + if (NULL == Mac) + { + DEBUG((EFI_D_ERROR, "[%a]:[%dL] Mac buffer is null!\n", __FUNCTION__, __LINE__)); + return EFI_INVALID_PARAMETER; + } + + Status = OemSetMacE2prom(Port, Mac->Addr); + if ((EFI_ERROR(Status))) + { + DEBUG((EFI_D_ERROR, "[%a]:[%dL] Set mac failed!\n", __FUNCTION__, __LINE__)); + return Status; + } + + return EFI_SUCCESS; +} + +HISI_BOARD_NIC_PROTOCOL mHisiBoardNicProtocol2P = { + .GetMac = OemGetMac2P, + .SetMac = OemSetMac2P, +}; + +VOID OemFeedbackXGeStatus(BOOLEAN IsLinkup, BOOLEAN IsActOK, UINT32 port) +{ + UINT8 CpldValue = 0; + UINTN RegOffset = 0x10 + (UINTN)port * 4; + + if (port > 2) + { + return; + } + + if (IsLinkup) + { + CpldValue = ReadCpldReg(RegOffset); + CpldValue |= BIT2; + WriteCpldReg(RegOffset, CpldValue); + } + else + { + CpldValue = ReadCpldReg(RegOffset); + CpldValue &= ~((UINT8)BIT2); + WriteCpldReg(RegOffset, CpldValue); + } + + if (IsActOK) + { + CpldValue = ReadCpldReg(RegOffset); + CpldValue |= BIT4; + WriteCpldReg(RegOffset, CpldValue); + } + else + { + CpldValue = ReadCpldReg(RegOffset); + CpldValue &= ~((UINT8)BIT4); + WriteCpldReg(RegOffset, CpldValue); + } +} + +HISI_BOARD_XGE_STATUS_PROTOCOL mHisiBoardXgeStatusProtocol2p = { + .FeedbackXgeStatus = OemFeedbackXGeStatus, +}; + + +EFI_STATUS +EFIAPI +OemNicConfigEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + Status = gBS->InstallProtocolInterface( + &ImageHandle, + &gHisiBoardNicProtocolGuid, + EFI_NATIVE_INTERFACE, + &mHisiBoardNicProtocol2P + ); + + if(EFI_ERROR(Status)) + { + DEBUG((EFI_D_ERROR, "[%a]:[%dL] Install Protocol failed %r\n", __FUNCTION__, __LINE__, Status)); + return Status; + } + + Status = gBS->InstallProtocolInterface( + &ImageHandle, + &gHisiBoardXgeStatusProtocolGuid, + EFI_NATIVE_INTERFACE, + &mHisiBoardXgeStatusProtocol2p + ); + + if(EFI_ERROR(Status)) + { + DEBUG((EFI_D_ERROR, "[%a]:[%dL] Install Protocol failed %r\n", __FUNCTION__, __LINE__, Status)); + return Status; + } + + return EFI_SUCCESS; +} + diff --git a/Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf b/Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf new file mode 100644 index 0000000000..ee5596a4ce --- /dev/null +++ b/Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf @@ -0,0 +1,52 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = OemNicConfigPangea + FILE_GUID = 3A23A929-1F38-4d04-8A01-38AD993EB2CE + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = OemNicConfigEntry + +[Sources.common] + OemNicConfig2P.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Hisilicon/HisiPkg.dec + +[Protocols] + gHisiBoardNicProtocolGuid ##Produce + gHisiBoardXgeStatusProtocolGuid + +[LibraryClasses] + CpldIoLib + UefiDriverEntryPoint + UefiBootServicesTableLib + DebugLib + IoLib + TimerLib + I2CLib + PcdLib + +[FixedPcd] + +[Depex] + TRUE + +[BuildOptions] + diff --git a/Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.c b/Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.c new file mode 100644 index 0000000000..8bfac2d99f --- /dev/null +++ b/Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.c @@ -0,0 +1,437 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// +// Global variables for Option ROMs +// +#define NULL_ROM_FILE_GUID \ + { \ + 0x00000000, 0x0000, 0x0000, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} \ + } + +#define SAS_OPTION_ROM_FILE_GUID \ +{ 0xb47533c7, 0xcc78, 0x4e5e, {0x94, 0x33, 0xf2, 0x8b, 0x16, 0xcd, 0x66, 0xdb}} + +#define SAS3108_OPTION_ROM_FILE_GUID \ +{ 0xb47533c8, 0xcc78, 0x4e5e, {0x94, 0x33, 0xf2, 0x8b, 0x16, 0xcd, 0x66, 0xd8}} + +#define INVALID 0xBD + + +typedef struct { + EFI_HANDLE PciPlatformHandle; + EFI_PCI_PLATFORM_PROTOCOL PciPlatform; +} PCI_PLATFORM_PRIVATE_DATA; + + +#define MAX_ROM_NUMBER 2 + + +typedef struct { + EFI_GUID FileName; + UINTN Segment; + UINTN Bus; + UINTN Device; + UINTN Function; + UINT16 VendorId; + UINT16 DeviceId; +} PCI_OPTION_ROM_TABLE; + +typedef struct { + UINTN RomSize; + VOID *RomBase; +} OPTION_ROM_INFO; + +PCI_PLATFORM_PRIVATE_DATA *mPciPrivateData = NULL; + +PCI_OPTION_ROM_TABLE mPciOptionRomTable[] = { + { + SAS_OPTION_ROM_FILE_GUID, + 0, + 2, + 0, + 0, + 0x1000, + 0x0097 + }, + { + SAS3108_OPTION_ROM_FILE_GUID, + 0, + 1, + 0, + 0, + 0x1000, + 0x005D + }, + + // + // End of OptionROM Entries + // + { + NULL_ROM_FILE_GUID, // Guid + 0, // Segment + 0, // Bus Number + 0, // Device Number + 0, // Function Number + 0xffff, // Vendor ID + 0xffff // Device ID + } +}; + +EFI_STATUS +EFIAPI +GetPlatformPolicy ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + OUT EFI_PCI_PLATFORM_POLICY *PciPolicy + ) +/*++ + +Routine Description: + + Set the PciPolicy as EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_NO_ALIAS. + +Arguments: + + This - The pointer to the Protocol itself. + PciPolicy - the returned Policy. + +Returns: + + EFI_UNSUPPORTED - Function not supported. + EFI_INVALID_PARAMETER - Invalid PciPolicy value. + +--*/ +{ + if (PciPolicy == NULL) { + return EFI_INVALID_PARAMETER; + } + + return EFI_UNSUPPORTED; +} + +EFI_STATUS +GetRawImage ( + IN EFI_GUID *NameGuid, + IN OUT VOID **Buffer, + IN OUT UINTN *Size + ) +/*++ + +Routine Description: + + Get an indicated image in raw sections. + +Arguments: + + NameGuid - NameGuid of the image to get. + Buffer - Buffer to store the image get. + Size - size of the image get. + +Returns: + + EFI_NOT_FOUND - Could not find the image. + EFI_LOAD_ERROR - Error occurred during image loading. + EFI_SUCCESS - Image has been successfully loaded. + +--*/ +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + UINTN HandleCount; + UINTN Index; + EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv; + UINT32 AuthenticationStatus; + + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiFirmwareVolume2ProtocolGuid, + NULL, + &HandleCount, + &HandleBuffer + ); + if (EFI_ERROR (Status) || HandleCount == 0) { + return EFI_NOT_FOUND; + } + // + // Find desired image in all Fvs + // + for (Index = 0; Index < HandleCount; Index++) { + Status = gBS->HandleProtocol ( + HandleBuffer[Index], + &gEfiFirmwareVolume2ProtocolGuid, + (VOID **)&Fv + ); + if (EFI_ERROR (Status)) { + return EFI_LOAD_ERROR; + } + // + // Try a raw file + // + *Buffer = NULL; + *Size = 0; + Status = Fv->ReadSection ( + Fv, + NameGuid, + EFI_SECTION_RAW, + 0, + Buffer, + Size, + &AuthenticationStatus + ); + + if (!EFI_ERROR (Status)) { + break; + } + } + + if (Index >= HandleCount) { + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +GetPciRom ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE PciHandle, + OUT VOID **RomImage, + OUT UINTN *RomSize + ) +/*++ + +Routine Description: + + Return a PCI ROM image for the onboard device represented by PciHandle. + +Arguments: + + This - Protocol instance pointer. + PciHandle - PCI device to return the ROM image for. + RomImage - PCI Rom Image for onboard device. + RomSize - Size of RomImage in bytes. + +Returns: + + EFI_SUCCESS - RomImage is valid. + EFI_NOT_FOUND - No RomImage. + +--*/ +{ + EFI_STATUS Status; + EFI_PCI_IO_PROTOCOL *PciIo; + UINT16 VendorId; + UINT16 DeviceId; + UINTN TableIndex; + UINTN RomImageNumber; + OPTION_ROM_INFO OptionRominfo[MAX_ROM_NUMBER]; + + Status = gBS->HandleProtocol ( + PciHandle, + &gEfiPciIoProtocolGuid, + (VOID **) &PciIo + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + (VOID)PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_VENDOR_ID_OFFSET, 1, &VendorId); + (VOID)PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_DEVICE_ID_OFFSET, 1, &DeviceId); + + // + // Loop through table of video option rom descriptions + // + RomImageNumber = 0; + for (TableIndex = 0; mPciOptionRomTable[TableIndex].VendorId != 0xffff; TableIndex++) { + // + // See if the PCI device specified by PciHandle matches at device in mPciOptionRomTable + // + if ((VendorId != mPciOptionRomTable[TableIndex].VendorId) + || (DeviceId != mPciOptionRomTable[TableIndex].DeviceId) + ) + { + continue; + } + + Status = GetRawImage ( + &mPciOptionRomTable[TableIndex].FileName, + &(OptionRominfo[RomImageNumber].RomBase), + &(OptionRominfo[RomImageNumber].RomSize) + ); + + if (EFI_ERROR (Status)) { + continue; + } else { + RomImageNumber++; + if (RomImageNumber == MAX_ROM_NUMBER) { + break; + } + } + } + + if (RomImageNumber == 0) { + + return EFI_NOT_FOUND; + + } else { + *RomImage = OptionRominfo[RomImageNumber - 1].RomBase; + *RomSize = OptionRominfo[RomImageNumber - 1].RomSize; + + if (RomImageNumber > 1) { + // + // More than one OPROM have been found! + // + + } + + return EFI_SUCCESS; + } +} + +EFI_STATUS +EFIAPI +PlatformPrepController ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_HANDLE RootBridge, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ) +/*++ + +Routine Description: + + The PlatformPrepController() function can be used to notify the platform driver so that + it can perform platform-specific actions. No specific actions are required. + Several notification points are defined at this time. More synchronization points may be + added as required in the future. The PCI bus driver calls the platform driver twice for + every PCI controller-once before the PCI Host Bridge Resource Allocation Protocol driver + is notified, and once after the PCI Host Bridge Resource Allocation Protocol driver has + been notified. + This member function may not perform any error checking on the input parameters. It also + does not return any error codes. If this member function detects any error condition, it + needs to handle those errors on its own because there is no way to surface any errors to + the caller. + +Arguments: + + This - Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance. + HostBridge - The associated PCI host bridge handle. + RootBridge - The associated PCI root bridge handle. + PciAddress - The address of the PCI device on the PCI bus. + Phase - The phase of the PCI controller enumeration. + ChipsetPhase - Defines the execution phase of the PCI chipset driver. + +Returns: + + EFI_SUCCESS - The function completed successfully. + EFI_UNSUPPORTED - Not supported. + +--*/ +{ + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +PhaseNotify ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ) +/*++ + +Routine Description: + + Perform initialization by the phase indicated. + +Arguments: + + This - Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance. + HostBridge - The associated PCI host bridge handle. + Phase - The phase of the PCI controller enumeration. + ChipsetPhase - Defines the execution phase of the PCI chipset driver. + +Returns: + + EFI_SUCCESS - Must return with success. + +--*/ +{ + + return EFI_SUCCESS; +} + +EFI_STATUS +PciPlatformDriverEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +/*++ + +Routine Description: + Main Entry point of the Pci Platform Driver. + +Arguments: + + ImageHandle - Handle to the image. + SystemTable - Handle to System Table. + +Returns: + + EFI_STATUS - Status of the function calling. + +--*/ +{ + EFI_STATUS Status; + PCI_PLATFORM_PRIVATE_DATA *PciPrivateData; + + PciPrivateData = AllocateZeroPool (sizeof (PCI_PLATFORM_PRIVATE_DATA)); + mPciPrivateData = PciPrivateData; + + mPciPrivateData->PciPlatform.PlatformNotify = PhaseNotify; + mPciPrivateData->PciPlatform.PlatformPrepController = PlatformPrepController; + mPciPrivateData->PciPlatform.GetPlatformPolicy = GetPlatformPolicy; + mPciPrivateData->PciPlatform.GetPciRom = GetPciRom; + + // + // Install on a new handle + // + Status = gBS->InstallMultipleProtocolInterfaces ( + &mPciPrivateData->PciPlatformHandle, + &gEfiPciPlatformProtocolGuid, + &mPciPrivateData->PciPlatform, + NULL + ); + + return Status; +} diff --git a/Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.h b/Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.h new file mode 100644 index 0000000000..a89f7c61b6 --- /dev/null +++ b/Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.h @@ -0,0 +1,180 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef PCI_PLATFORM_H_ +#define PCI_PLATFORM_H_ + +#include +#include +#include +#include + + +// +// Global variables for Option ROMs +// +#define NULL_ROM_FILE_GUID \ + { \ + 0x00000000, 0x0000, 0x0000, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 \ + } + + +typedef struct { + EFI_GUID FileName; + UINTN Segment; + UINTN Bus; + UINTN Device; + UINTN Function; + UINT16 VendorId; + UINT16 DeviceId; +} PCI_OPTION_ROM_TABLE; + +#define INVALID 0xBD + + +typedef struct { + EFI_HANDLE PciPlatformHandle; + EFI_PCI_PLATFORM_PROTOCOL PciPlatform; +} PCI_PLATFORM_PRIVATE_DATA; + + + +extern PCI_PLATFORM_PRIVATE_DATA mPciPrivateData; + +EFI_STATUS +EFIAPI +PhaseNotify ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ) +/*++ + +Routine Description: + + Perform initialization by the phase indicated. + +Arguments: + + This - Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance. + HostBridge - The associated PCI host bridge handle. + Phase - The phase of the PCI controller enumeration. + ChipsetPhase - Defines the execution phase of the PCI chipset driver. + +Returns: + + EFI_SUCCESS - Must return with success. + +--*/ +; + +EFI_STATUS +EFIAPI +PlatformPrepController ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_HANDLE RootBridge, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ) +/*++ + +Routine Description: + + The PlatformPrepController() function can be used to notify the platform driver so that + it can perform platform-specific actions. No specific actions are required. + Several notification points are defined at this time. More synchronization points may be + added as required in the future. The PCI bus driver calls the platform driver twice for + every PCI controller-once before the PCI Host Bridge Resource Allocation Protocol driver + is notified, and once after the PCI Host Bridge Resource Allocation Protocol driver has + been notified. + This member function may not perform any error checking on the input parameters. It also + does not return any error codes. If this member function detects any error condition, it + needs to handle those errors on its own because there is no way to surface any errors to + the caller. + +Arguments: + + This - Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance. + HostBridge - The associated PCI host bridge handle. + RootBridge - The associated PCI root bridge handle. + PciAddress - The address of the PCI device on the PCI bus. + Phase - The phase of the PCI controller enumeration. + ChipsetPhase - Defines the execution phase of the PCI chipset driver. + +Returns: + + EFI_SUCCESS - The function completed successfully. + +--*/ +; + +EFI_STATUS +EFIAPI +GetPlatformPolicy ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + OUT EFI_PCI_PLATFORM_POLICY *PciPolicy + ) +/*++ + +Routine Description: + + Set the PciPolicy as EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_NO_ALIAS. + +Arguments: + + This - The pointer to the Protocol itself. + PciPolicy - the returned Policy. + +Returns: + + EFI_UNSUPPORTED - Function not supported. + EFI_INVALID_PARAMETER - Invalid PciPolicy value. + +--*/ +; + +EFI_STATUS +EFIAPI +GetPciRom ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE PciHandle, + OUT VOID **RomImage, + OUT UINTN *RomSize + ) +/*++ + +Routine Description: + + Return a PCI ROM image for the onboard device represented by PciHandle. + +Arguments: + + This - Protocol instance pointer. + PciHandle - PCI device to return the ROM image for. + RomImage - PCI Rom Image for onboard device. + RomSize - Size of RomImage in bytes. + +Returns: + + EFI_SUCCESS - RomImage is valid. + EFI_NOT_FOUND - No RomImage. + +--*/ +; + +#endif diff --git a/Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf b/Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf new file mode 100644 index 0000000000..8b170d2654 --- /dev/null +++ b/Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf @@ -0,0 +1,53 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[defines] + INF_VERSION = 0x00010005 + BASE_NAME = PciPlatform + FILE_GUID = E2441B64-7EF4-41fe-B3A3-8CAA7F8D3017 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = PciPlatformDriverEntry + +[sources.common] + PciPlatform.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + ArmPkg/ArmPkg.dec + Silicon/Hisilicon/HisiPkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + UefiLib + BaseLib + DebugLib + ArmLib + IoLib + MemoryAllocationLib + +[Protocols] + gEfiPciPlatformProtocolGuid + gEfiFirmwareVolume2ProtocolGuid + gEfiPciIoProtocolGuid + +[Pcd] + +[FixedPcd] + +[Depex] + TRUE + diff --git a/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c b/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c new file mode 100644 index 0000000000..97cf6b8d87 --- /dev/null +++ b/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.c @@ -0,0 +1,180 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#define PERI_SUBCTRL_BASE (0x40000000) +#define MDIO_SUBCTRL_BASE (0x60000000) +#define PCIE2_SUBCTRL_BASE (0xA0000000) +#define PCIE0_SUBCTRL_BASE (0xB0000000) +#define ALG_BASE (0xD0000000) + +#define SC_BROADCAST_EN_REG (0x16220) +#define SC_BROADCAST_SCL1_ADDR0_REG (0x16230) +#define SC_BROADCAST_SCL1_ADDR1_REG (0x16234) +#define SC_BROADCAST_SCL2_ADDR0_REG (0x16238) +#define SC_BROADCAST_SCL2_ADDR1_REG (0x1623C) +#define SC_BROADCAST_SCL3_ADDR0_REG (0x16240) +#define SC_BROADCAST_SCL3_ADDR1_REG (0x16244) +#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG (0x1000) +#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG (0x1010) +#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG (0x1014) +#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG (0x1018) +#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG (0x101C) +#define PCIE_SUBCTRL_SC_REMAP_CTRL_REG (0x1200) +#define SC_ITS_M3_INT_MUX_SEL_REG (0x21F0) +#define SC_TM_CLKEN0_REG (0x2050) + +#define SC_TM_CLKEN0_REG_VALUE (0x3) +#define SC_BROADCAST_EN_REG_VALUE (0x7) +#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE0 (0x0) +#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE1 (0x40016260) +#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE2 (0x60016260) +#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE3 (0x400) +#define SC_ITS_M3_INT_MUX_SEL_REG_VALUE (0x7) +#define PCIE_SUBCTRL_SC_REMAP_CTRL_REG_VALUE0 (0x0) +#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE0 (0x27) +#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE1 (0x2F) +#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE2 (0x77) +#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG_VALUE0 (0x178033) +#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG_VALUE0 (0x17003c) +#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE0 (0x15003d) +#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE1 (0x170035) +#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG_VALUE0 (0x16003e) + +VOID PlatformTimerStart (VOID) +{ + // Timer0 clock enable + MmioWrite32 (PERI_SUBCTRL_BASE + SC_TM_CLKEN0_REG, SC_TM_CLKEN0_REG_VALUE); +} + +void QResetAp(VOID) +{ + MmioWrite64(FixedPcdGet64(PcdMailBoxAddress), 0x0); + (void)WriteBackInvalidateDataCacheRange((VOID *) FixedPcdGet64(PcdMailBoxAddress), 8); + ArmDataSynchronizationBarrier (); + ArmInstructionSynchronizationBarrier (); + + //SCCL A + if (!PcdGet64 (PcdTrustedFirmwareEnable)) + { + StartupAp(); + } +} + + +EFI_STATUS +EFIAPI +EarlyConfigEntry ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + DEBUG((EFI_D_INFO,"SMMU CONFIG.........")); + (VOID)SmmuConfigForOS(); + DEBUG((EFI_D_INFO,"Done\n")); + + + DEBUG((EFI_D_INFO,"AP CONFIG.........")); + (VOID)QResetAp(); + DEBUG((EFI_D_INFO,"Done\n")); + + DEBUG((EFI_D_INFO,"MN CONFIG.........")); + (VOID)MN_CONFIG(); + DEBUG((EFI_D_INFO,"Done\n")); + + if(OemIsMpBoot()) + { + DEBUG((EFI_D_INFO,"Event Broadcast CONFIG.........")); + //EVENT broadcast + MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE); + MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1); + MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0); + MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2); + MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3); + MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1); + MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3); + + MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE); + MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2); + MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0); + MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2); + MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3); + MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1); + MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3); + + MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE); + MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1); + MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0); + MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2); + MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0); + MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1); + MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3); + + MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE); + MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2); + MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0); + MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2); + MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3); + MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1); + MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0); + + DEBUG((EFI_D_INFO,"Done\n")); + } + + DEBUG((EFI_D_INFO,"PCIE RAM Address CONFIG.........")); + + if(OemIsMpBoot()) + { + MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISP_DAW_EN_REG, PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE0); + MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE0); + MmioWrite32 (PCIE0_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISP_DAW_EN_REG, PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE1); + MmioWrite32 (PCIE0_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG_VALUE0); + MmioWrite32 (PCIE0_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE1); + } + + else + { + MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_REMAP_CTRL_REG, PCIE_SUBCTRL_SC_REMAP_CTRL_REG_VALUE0); + MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISP_DAW_EN_REG, PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE2); + MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG_VALUE0); + MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE0); + MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG_VALUE0); + } + + DEBUG((EFI_D_INFO,"Done\n")); + + MmioWrite32(ALG_BASE + SC_ITS_M3_INT_MUX_SEL_REG, SC_ITS_M3_INT_MUX_SEL_REG_VALUE); + + DEBUG((EFI_D_INFO,"Timer CONFIG.........")); + PlatformTimerStart (); + DEBUG((EFI_D_INFO,"Done\n")); + + return EFI_SUCCESS; +} + diff --git a/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf b/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf new file mode 100644 index 0000000000..c65cf7b6dd --- /dev/null +++ b/Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf @@ -0,0 +1,55 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = EarlyConfigPeimD03 + FILE_GUID = A181AD33-E64A-4084-A54A-A69DF1FB0ABF + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = EarlyConfigEntry + +[Sources.common] + EarlyConfigPeimD03.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + + ArmPkg/ArmPkg.dec + Silicon/Hisilicon/HisiPkg.dec + +[LibraryClasses] + PeimEntryPoint + PcdLib + DebugLib + IoLib + CacheMaintenanceLib + + PlatformSysCtrlLib + ArmLib + +[Pcd] + gHisiTokenSpaceGuid.PcdMailBoxAddress + gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable + gHisiTokenSpaceGuid.PcdPeriSubctrlAddress + +[Depex] +## As we will clean mailbox in this module, need to wait memory init complete + gEfiPeiMemoryDiscoveredPpiGuid + +[BuildOptions] + diff --git a/Platform/Hisilicon/D03/Include/Library/CpldD03.h b/Platform/Hisilicon/D03/Include/Library/CpldD03.h new file mode 100644 index 0000000000..456bf4b5c9 --- /dev/null +++ b/Platform/Hisilicon/D03/Include/Library/CpldD03.h @@ -0,0 +1,25 @@ +/** @file +* +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __CPLD_D03_H__ +#define __CPLD_D03_H__ + +#define CPLD_BIOSINDICATE_FLAG 0x09 +#define CPLD_I2C_SWITCH_FLAG 0x17 +#define CPU_GET_I2C_CONTROL BIT2 +#define BMC_I2C_STATUS BIT3 + + +#endif diff --git a/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClock.h b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClock.h new file mode 100644 index 0000000000..d1e6c41dd7 --- /dev/null +++ b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClock.h @@ -0,0 +1,178 @@ +/** @file +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Based on the files under ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf +**/ + + +#ifndef __DS3231_REAL_TIME_CLOCK_H__ +#define __DS3231_REAL_TIME_CLOCK_H__ + +#define DS3231_REGADDR_SECONDS 0x00 +#define DS3231_REGADDR_MIUTES 0x01 +#define DS3231_REGADDR_HOURS 0x02 +#define DS3231_REGADDR_DAY 0x03 +#define DS3231_REGADDR_DATE 0x04 +#define DS3231_REGADDR_MONTH 0x05 +#define DS3231_REGADDR_YEAR 0x06 +#define DS3231_REGADDR_ALARM1SEC 0x07 +#define DS3231_REGADDR_ALARM1MIN 0x08 +#define DS3231_REGADDR_ALARM1HOUR 0x09 +#define DS3231_REGADDR_ALARM1DAY 0x0A +#define DS3231_REGADDR_ALARM2MIN 0x0B +#define DS3231_REGADDR_ALARM2HOUR 0x0C +#define DS3231_REGADDR_ALARM2DAY 0x0D +#define DS3231_REGADDR_CONTROL 0x0E +#define DS3231_REGADDR_STATUS 0x0F +#define DS3231_REGADDR_AGOFFSET 0x10 +#define DS3231_REGADDR_TEMPMSB 0x11 +#define DS3231_REGADDR_TEMPLSB 0x12 + + +typedef union { + struct{ + UINT8 A1IE:1; + UINT8 A2IE:1; + UINT8 INTCN:1; + UINT8 RSV:2; + UINT8 CONV:1; + UINT8 BBSQW:1; + UINT8 EOSC_N:1; + }bits; + UINT8 u8; +}RTC_DS3231_CONTROL; + +typedef union { + struct{ + UINT8 A1F:1; + UINT8 A2F:1; + UINT8 BSY:1; + UINT8 EN32KHZ:2; + UINT8 Rsv:3; + UINT8 OSF:1; + }bits; + UINT8 u8; +}RTC_DS3231_STATUS; + + +typedef union { + struct{ + UINT8 Data:7; + UINT8 Sign:1; + }bits; + UINT8 u8; +}RTC_DS3231_AGOFFSET; + +typedef union { + struct{ + UINT8 Data:7; + UINT8 Sign:1; + }bits; + UINT8 u8; +}RTC_DS3231_TEMPMSB; + + +typedef union { + struct{ + UINT8 Rsv:6; + UINT8 Data:2; + }bits; + UINT8 u8; +}RTC_DS3231_TEMPLSB; + +typedef union { + struct{ + UINT8 Seconds:4; + UINT8 Seconds10:3; + UINT8 Rsv:1; + }bits; + UINT8 u8; +}RTC_DS3231_SECONDS; + +typedef union { + struct{ + UINT8 Minutes:4; + UINT8 Minutes10:3; + UINT8 Rsv:1; + }bits; + UINT8 u8; +}RTC_DS3231_MINUTES; + +typedef union { + struct{ + UINT8 Hour:4; + UINT8 Hours10:1; + UINT8 PM_20Hours:1; + UINT8 Hour24_n:1; + UINT8 Rsv:1; + }bits; + UINT8 u8; +}RTC_DS3231_HOURS; + +typedef union { + struct{ + UINT8 Day:3; + UINT8 Rsv:5; + }bits; + UINT8 u8; +}RTC_DS3231_DAY; + +typedef union { + struct{ + UINT8 Month:4; + UINT8 Month10:1; + UINT8 Rsv:2; + UINT8 Century:1; + }bits; + UINT8 u8; +}RTC_DS3231_MONTH; + +typedef union { + struct{ + UINT8 Year:4; + UINT8 Year10:4; + }bits; + UINT8 u8; +}RTC_DS3231_YEAR; + +typedef union { + struct{ + UINT8 Seconds:4; + UINT8 Seconds10:3; + UINT8 A1M1:1; + }bits; + UINT8 u8; +}RTC_DS3231_ALARM1SEC; + +typedef union { + struct{ + UINT8 Minutes:4; + UINT8 Minutes10:3; + UINT8 A1M2:1; + }bits; + UINT8 u8; +}RTC_DS3231_ALARM1MIN; + +typedef union { + struct{ + UINT8 Hour:4; + UINT8 Hours10:1; + UINT8 PM_20Hours:1; + UINT8 Hours24:1; + UINT8 A1M3:1; + }bits; + UINT8 u8; +}RTC_DS3231_ALARM1HOUR; + +#endif diff --git a/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c new file mode 100644 index 0000000000..07fa52aa78 --- /dev/null +++ b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c @@ -0,0 +1,504 @@ +/** @file + Implement EFI RealTimeClock runtime services via RTC Lib. + + Currently this driver does not support runtime virtual calling. + + Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
+ Copyright (c) 2011-2013, ARM Ltd. All rights reserved.
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2015, Linaro Limited. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + Based on the files under ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf + +**/ + +#include +#include +#include +#include +#include +#include +// Use EfiAtRuntime to check stage +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "DS3231RealTimeClock.h" +#include +#include + +extern I2C_DEVICE gDS3231RtcDevice; + +STATIC BOOLEAN mDS3231Initialized = FALSE; + +EFI_STATUS +IdentifyDS3231 ( + VOID + ) +{ + EFI_STATUS Status; + + Status = EFI_SUCCESS; + return Status; +} + +EFI_STATUS +SwitchRtcI2cChannelAndLock ( + VOID + ) +{ + UINT8 Temp; + UINT8 Count; + + for (Count = 0; Count < 20; Count++) { + Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG); + + if ((Temp & BMC_I2C_STATUS) != 0) { + //The I2C channel is shared with BMC, + //Check if BMC has taken ownership of I2C. + //If so, wait 30ms, then try again. + //If not, start using I2C. + //And the CPLD_I2C_SWITCH_FLAG will be set to CPU_GET_I2C_CONTROL + //BMC will check this flag to decide to use I2C or not. + MicroSecondDelay (30000); + continue; + } + + Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG); + Temp = Temp | CPU_GET_I2C_CONTROL; + WriteCpldReg (CPLD_I2C_SWITCH_FLAG, Temp); + + //This is empirical value,give cpld some time to make sure the + //value is wrote in + MicroSecondDelay (2); + Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG); + + if ((Temp & CPU_GET_I2C_CONTROL) == CPU_GET_I2C_CONTROL) { + return EFI_SUCCESS; + } + + //There need 30ms to keep consistent with the previous loops if the CPU failed + //to get control of I2C + MicroSecondDelay (30000); + } + + Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG); + Temp = Temp & ~CPU_GET_I2C_CONTROL; + WriteCpldReg (CPLD_I2C_SWITCH_FLAG, Temp); + + return EFI_NOT_READY; +} + + +EFI_STATUS +InitializeDS3231 ( + VOID + ) +{ + EFI_STATUS Status; + I2C_DEVICE Dev; + RTC_DS3231_CONTROL Temp; + RTC_DS3231_HOURS Hours; + + // Prepare the hardware + (VOID)IdentifyDS3231(); + + (VOID) CopyMem(&Dev, &gDS3231RtcDevice, sizeof(Dev)); + + Status = I2CInit(Dev.Socket,Dev.Port,Normal); + if (EFI_ERROR (Status)) { + goto EXIT; + } + // Ensure interrupts are masked. We do not want RTC interrupts in UEFI + Status = I2CRead(&Dev,DS3231_REGADDR_CONTROL,1,&Temp.u8); + if (EFI_ERROR (Status)) { + goto EXIT; + } + Temp.bits.INTCN = 0; + Status = I2CWrite(&Dev,DS3231_REGADDR_CONTROL,1,&Temp.u8); + if (EFI_ERROR (Status)) { + goto EXIT; + } + + MicroSecondDelay(2000); + Status = I2CRead(&Dev,DS3231_REGADDR_HOURS,1,&Hours.u8); + if (EFI_ERROR (Status)) { + goto EXIT; + } + Hours.bits.Hour24_n = 0; + Status = I2CWrite(&Dev,DS3231_REGADDR_HOURS,1,&Hours.u8); + if (EFI_ERROR (Status)) { + goto EXIT; + } + + + mDS3231Initialized = TRUE; + + EXIT: + return Status; +} + +/** + Returns the current time and date information, and the time-keeping capabilities + of the hardware platform. + + @param Time A pointer to storage to receive a snapshot of the current time. + @param Capabilities An optional pointer to a buffer to receive the real time clock + device's capabilities. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER Time is NULL. + @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error. + @retval EFI_SECURITY_VIOLATION The time could not be retrieved due to an authentication failure. +**/ +EFI_STATUS +EFIAPI +LibGetTime ( + OUT EFI_TIME *Time, + OUT EFI_TIME_CAPABILITIES *Capabilities + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINT8 Temp; + UINT8 BaseHour = 0; + + UINT16 BaseYear = 1900; + + I2C_DEVICE Dev; + + // Ensure Time is a valid pointer + if (NULL == Time) { + return EFI_INVALID_PARAMETER; + } + + Status = SwitchRtcI2cChannelAndLock(); + if(EFI_ERROR (Status)) { + return Status; + } + + // Initialize the hardware if not already done + if (!mDS3231Initialized) { + Status = InitializeDS3231 (); + if (EFI_ERROR (Status)) { + Status = EFI_NOT_READY; + goto GExit; + } + } + + (VOID) CopyMem(&Dev, &gDS3231RtcDevice, sizeof(Dev)); + + Status |= I2CRead(&Dev,DS3231_REGADDR_MONTH,1,&Temp); + + Time->Month = ((Temp>>4)&1)*10+(Temp&0x0F); + + + if(Temp&0x80){ + BaseYear = 2000; + } + + Status |= I2CRead(&Dev,DS3231_REGADDR_YEAR,1,&Temp); + + Time->Year = BaseYear+(Temp>>4) *10 + (Temp&0x0F); + + Status |= I2CRead(&Dev,DS3231_REGADDR_DATE,1,&Temp); + + Time->Day = ((Temp>>4)&3) *10 + (Temp&0x0F); + + Status |= I2CRead(&Dev,DS3231_REGADDR_HOURS,1,&Temp); + + BaseHour = 0; + if((Temp&0x30) == 0x30){ + Status = EFI_DEVICE_ERROR; + goto GExit; + }else if(Temp&0x20){ + BaseHour = 20; + }else if(Temp&0x10){ + BaseHour = 10; + } + Time->Hour = BaseHour + (Temp&0x0F); + + Status |= I2CRead(&Dev,DS3231_REGADDR_MIUTES,1,&Temp); + + Time->Minute = ((Temp>>4)&7) * 10 + (Temp&0x0F); + + Status |= I2CRead(&Dev,DS3231_REGADDR_SECONDS,1,&Temp); + + Time->Second = (Temp>>4) * 10 + (Temp&0x0F); + + Time->Nanosecond = 0; + Time->Daylight = 0; + Time->TimeZone = EFI_UNSPECIFIED_TIMEZONE; + + if((EFI_ERROR(Status)) || (!IsTimeValid(Time)) || ((Time->Year - BaseYear) > 99)) { + Status = EFI_UNSUPPORTED; + } + +GExit: + Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG); + Temp = Temp & ~CPU_GET_I2C_CONTROL; + WriteCpldReg (CPLD_I2C_SWITCH_FLAG, Temp); + + return Status; + +} + + +/** + Sets the current local time and date information. + + @param Time A pointer to the current time. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER A time field is out of range. + @retval EFI_DEVICE_ERROR The time could not be set due due to hardware error. + +**/ +EFI_STATUS +EFIAPI +LibSetTime ( + IN EFI_TIME *Time + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + I2C_DEVICE Dev; + UINT8 Temp; + + UINT16 BaseYear = 1900; + + + + // Check the input parameters are within the range specified by UEFI + if(!IsTimeValid(Time)){ + return EFI_INVALID_PARAMETER; + } + + Status = SwitchRtcI2cChannelAndLock(); + if(EFI_ERROR (Status)) { + return Status; + } + + // Initialize the hardware if not already done + if (!mDS3231Initialized) { + Status = InitializeDS3231 (); + if (EFI_ERROR (Status)) { + goto EXIT; + } + } + + (VOID) CopyMem(&Dev, &gDS3231RtcDevice, sizeof(Dev)); + + Temp = ((Time->Second/10)<<4) | (Time->Second%10); + MicroSecondDelay(1000); + Status = I2CWrite(&Dev,DS3231_REGADDR_SECONDS,1,&Temp); + if(EFI_ERROR (Status)){ + goto EXIT; + } + + Temp = ((Time->Minute/10)<<4) | (Time->Minute%10); + MicroSecondDelay(1000); + Status = I2CWrite(&Dev,DS3231_REGADDR_MIUTES,1,&Temp); + if(EFI_ERROR (Status)){ + goto EXIT; + } + + Temp = 0; + if(Time->Hour > 19){ + Temp = 2; + } else if(Time->Hour > 9){ + Temp = 1; + } + + Temp = (Temp << 4) | (Time->Hour%10); + MicroSecondDelay(1000); + Status = I2CWrite(&Dev,DS3231_REGADDR_HOURS,1,&Temp); + if(EFI_ERROR (Status)){ + goto EXIT; + } + + Temp = ((Time->Day/10)<<4) | (Time->Day%10); + MicroSecondDelay(1000); + Status = I2CWrite(&Dev,DS3231_REGADDR_DATE,1,&Temp); + if(EFI_ERROR (Status)){ + goto EXIT; + } + + + Temp = 0; + if(Time->Year >= 2000){ + Temp = 0x8; + BaseYear = 2000; + } + + if(Time->Month > 9){ + Temp |= 0x1; + } + Temp = (Temp<<4) | (Time->Month%10); + MicroSecondDelay(1000); + Status = I2CWrite(&Dev,DS3231_REGADDR_MONTH,1,&Temp); + if(EFI_ERROR (Status)){ + goto EXIT; + } + + Temp = (((Time->Year-BaseYear)/10)<<4) | (Time->Year%10); + MicroSecondDelay(1000); + Status = I2CWrite(&Dev,DS3231_REGADDR_YEAR,1,&Temp); + if(EFI_ERROR (Status)){ + goto EXIT; + } + + EXIT: + + Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG); + Temp = Temp & ~CPU_GET_I2C_CONTROL; + WriteCpldReg (CPLD_I2C_SWITCH_FLAG, Temp); + + return Status; +} + + +/** + Returns the current wakeup alarm clock setting. + + @param Enabled Indicates if the alarm is currently enabled or disabled. + @param Pending Indicates if the alarm signal is pending and requires acknowledgement. + @param Time The current alarm setting. + + @retval EFI_SUCCESS The alarm settings were returned. + @retval EFI_INVALID_PARAMETER Any parameter is NULL. + @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error. + +**/ +EFI_STATUS +EFIAPI +LibGetWakeupTime ( + OUT BOOLEAN *Enabled, + OUT BOOLEAN *Pending, + OUT EFI_TIME *Time + ) +{ + // Not a required feature + return EFI_UNSUPPORTED; +} + + +/** + Sets the system wakeup alarm clock time. + + @param Enabled Enable or disable the wakeup alarm. + @param Time If Enable is TRUE, the time to set the wakeup alarm for. + + @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If + Enable is FALSE, then the wakeup alarm was disabled. + @retval EFI_INVALID_PARAMETER A time field is out of range. + @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error. + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform. + +**/ +EFI_STATUS +EFIAPI +LibSetWakeupTime ( + IN BOOLEAN Enabled, + OUT EFI_TIME *Time + ) +{ + // Not a required feature + return EFI_UNSUPPORTED; +} + + + +/** + This is the declaration of an EFI image entry point. This can be the entry point to an application + written to this specification, an EFI boot service driver, or an EFI runtime driver. + + @param ImageHandle Handle that identifies the loaded image. + @param SystemTable System Table for this image. + + @retval EFI_SUCCESS The operation completed successfully. + +**/ +EFI_STATUS +EFIAPI +LibRtcInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + + + EFI_TIME EfiTime; + + // Setup the setters and getters + gRT->GetTime = LibGetTime; + gRT->SetTime = LibSetTime; + gRT->GetWakeupTime = LibGetWakeupTime; + gRT->SetWakeupTime = LibSetWakeupTime; + + + (VOID)gRT->GetTime (&EfiTime, NULL); + if((EfiTime.Year < 2015) || (EfiTime.Year > 2099)){ + EfiTime.Year = 2015; + EfiTime.Month = 1; + EfiTime.Day = 1; + EfiTime.Hour = 0; + EfiTime.Minute = 0; + EfiTime.Second = 0; + EfiTime.Nanosecond = 0; + Status = gRT->SetTime(&EfiTime); + if (EFI_ERROR(Status)) + { + DEBUG((EFI_D_ERROR, "[%a]:[%dL] Status : %r\n", __FUNCTION__, __LINE__, Status)); + } + } + + // Install the protocol + Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gEfiRealTimeClockArchProtocolGuid, NULL, + NULL + ); + + return Status; +} + + +/** + Fixup internal data so that EFI can be call in virtual mode. + Call the passed in Child Notify event and convert any pointers in + lib to virtual mode. + + @param[in] Event The Event that is being processed + @param[in] Context Event Context +**/ +VOID +EFIAPI +LibRtcVirtualNotifyEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + // + // Only needed if you are going to support the OS calling RTC functions in virtual mode. + // You will need to call EfiConvertPointer (). To convert any stored physical addresses + // to virtual address. After the OS transitions to calling in virtual mode, all future + // runtime calls will be made in virtual mode. + // + return; +} diff --git a/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf new file mode 100644 index 0000000000..319c35c724 --- /dev/null +++ b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf @@ -0,0 +1,48 @@ +#/** @file +# +# Copyright (c) 2006, Intel Corporation. All rights reserved.
+# Copyright (c) 2011-2013, ARM Ltd. All rights reserved.
+# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = DS3231RealTimeClockLib + FILE_GUID = 470DFB96-E205-4515-A75E-2E60F853E79D + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RealTimeClockLib + +[Sources.common] + DS3231RealTimeClockLib.c + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Platform/Hisilicon/D03/D03.dec + Silicon/Hisilicon/HisiPkg.dec + +[LibraryClasses] + IoLib + UefiLib + DebugLib + PcdLib + I2CLib + TimeBaseLib + TimerLib +# Use EFiAtRuntime to check stage + UefiRuntimeLib + CpldIoLib + +[Pcd] + diff --git a/Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.c b/Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.c new file mode 100755 index 0000000000..d00cb9b2ab --- /dev/null +++ b/Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.c @@ -0,0 +1,487 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef union AA_DAW +{ + /* Define the struct bits */ + struct + { + unsigned int sysdaw_id : 7 ; /* [6:0] */ + unsigned int interleave_en : 1 ; /* [7] */ + unsigned int sysdaw_size : 4 ; /* [11:8] */ + unsigned int reserved : 4 ; /* [15:12] */ + unsigned int sysdaw_addr : 16 ; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + unsigned int u32; + +} AA_DAW_U; + + + +MAC_ADDRESS gMacAddress[1]; + + +CHAR8 *EthName[8]= +{ + "ethernet@0","ethernet@1", + "ethernet@2","ethernet@3", + "ethernet@4","ethernet@5", + "ethernet@6","ethernet@7" +}; + +UINT8 DawNum[4] = {0, 0, 0, 0}; +PHY_MEM_REGION *NodemRegion[4] = {NULL, NULL, NULL, NULL}; +UINTN NumaPages[4] = {0, 0, 0, 0}; + +CHAR8 *NumaNodeName[4]= +{ + "p0-ta","p0-tc", + "p1-ta","p1-tc", +}; + +STATIC +BOOLEAN +IsMemMapRegion ( + IN EFI_MEMORY_TYPE MemoryType + ) +{ + switch(MemoryType) + { + case EfiRuntimeServicesCode: + case EfiRuntimeServicesData: + case EfiConventionalMemory: + case EfiACPIReclaimMemory: + case EfiACPIMemoryNVS: + case EfiLoaderCode: + case EfiLoaderData: + case EfiBootServicesCode: + case EfiBootServicesData: + case EfiPalCode: + return TRUE; + default: + return FALSE; + } +} + + +EFI_STATUS +GetMacAddress (UINT32 Port) +{ + EFI_MAC_ADDRESS Mac; + EFI_STATUS Status; + HISI_BOARD_NIC_PROTOCOL *OemNic = NULL; + + Status = gBS->LocateProtocol(&gHisiBoardNicProtocolGuid, NULL, (VOID **)&OemNic); + if(EFI_ERROR(Status)) + { + DEBUG((EFI_D_ERROR, "[%a]:[%dL] LocateProtocol failed %r\n", __FUNCTION__, __LINE__, Status)); + return Status; + } + + Status = OemNic->GetMac(&Mac, Port); + if(EFI_ERROR(Status)) + { + DEBUG((EFI_D_ERROR, "[%a]:[%dL] GetMac failed %r\n", __FUNCTION__, __LINE__, Status)); + return Status; + } + + gMacAddress[0].data0=Mac.Addr[0]; + gMacAddress[0].data1=Mac.Addr[1]; + gMacAddress[0].data2=Mac.Addr[2]; + gMacAddress[0].data3=Mac.Addr[3]; + gMacAddress[0].data4=Mac.Addr[4]; + gMacAddress[0].data5=Mac.Addr[5]; + DEBUG((EFI_D_INFO, "Port%d:0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", + Port,gMacAddress[0].data0,gMacAddress[0].data1,gMacAddress[0].data2, + gMacAddress[0].data3,gMacAddress[0].data4,gMacAddress[0].data5)); + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +DelPhyhandleUpdateMacAddress(IN VOID* Fdt) +{ + UINT8 port; + INTN ethernetnode; + INTN node; + INTN Error; + struct fdt_property *m_prop; + int m_oldlen; + EFI_STATUS Status = EFI_SUCCESS; + EFI_STATUS GetMacStatus = EFI_SUCCESS; + + node = fdt_subnode_offset(Fdt, 0, "soc"); + if (node < 0) + { + DEBUG ((EFI_D_ERROR, "can not find soc root node\n")); + return EFI_INVALID_PARAMETER; + } + else + { + for( port=0; port<8; port++ ) + { + GetMacStatus= GetMacAddress(port); + ethernetnode = fdt_subnode_offset(Fdt, node,EthName[port]); + if(!EFI_ERROR(GetMacStatus)) + { + + if (ethernetnode < 0) + { + DEBUG ((EFI_D_WARN, "Can not find ethernet@%d node\n",port)); + DEBUG ((EFI_D_WARN, "Suppose port %d is not enabled.\n", port)); + continue; + } + m_prop = fdt_get_property_w(Fdt, ethernetnode, "local-mac-address", &m_oldlen); + if(m_prop) + { + Error = fdt_delprop(Fdt, ethernetnode, "local-mac-address"); + if (Error) + { + DEBUG ((EFI_D_ERROR, "ERROR:fdt_delprop() Local-mac-address: %a\n", fdt_strerror (Error))); + Status = EFI_INVALID_PARAMETER; + } + Error = fdt_setprop(Fdt, ethernetnode, "local-mac-address",gMacAddress,sizeof(MAC_ADDRESS)); + if (Error) + { + DEBUG ((EFI_D_ERROR, "ERROR:fdt_setprop():local-mac-address %a\n", fdt_strerror (Error))); + Status = EFI_INVALID_PARAMETER; + } + } + } + } + } + return Status; +} + +STATIC +EFI_STATUS +UpdateRefClk (IN VOID* Fdt) +{ + INTN node; + INTN Error; + struct fdt_property *m_prop; + int m_oldlen; + UINTN ArchTimerFreq = 0; + UINT32 Data; + CONST CHAR8 *Property = "clock-frequency"; + + ArmArchTimerReadReg (CntFrq, &ArchTimerFreq); + if (!ArchTimerFreq) { + DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Get timer frequency failed!\n", __FUNCTION__, __LINE__)); + return EFI_INVALID_PARAMETER; + } + + node = fdt_subnode_offset(Fdt, 0, "soc"); + if (node < 0) { + DEBUG ((DEBUG_ERROR, "can not find soc node\n")); + return EFI_INVALID_PARAMETER; + } + + node = fdt_subnode_offset(Fdt, node, "refclk"); + if (node < 0) { + DEBUG ((DEBUG_ERROR, "can not find refclk node\n")); + return EFI_INVALID_PARAMETER; + } + + m_prop = fdt_get_property_w(Fdt, node, Property, &m_oldlen); + if(!m_prop) { + DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Can't find property %a\n", __FUNCTION__, __LINE__, Property)); + return EFI_INVALID_PARAMETER; + } + + Error = fdt_delprop(Fdt, node, Property); + if (Error) { + DEBUG ((DEBUG_ERROR, "ERROR: fdt_delprop() %a: %a\n", Property, fdt_strerror (Error))); + return EFI_INVALID_PARAMETER; + } + + // UINT32 is enough for refclk data length + Data = (UINT32) ArchTimerFreq; + Data = cpu_to_fdt32 (Data); + Error = fdt_setprop(Fdt, node, Property, &Data, sizeof(Data)); + if (Error) { + DEBUG ((DEBUG_ERROR, "ERROR:fdt_setprop() %a: %a\n", Property, fdt_strerror (Error))); + return EFI_INVALID_PARAMETER; + } + + DEBUG ((DEBUG_INFO, "Update refclk successfully.\n")); + return EFI_SUCCESS; +} + +INTN +GetMemoryNode(VOID* Fdt) +{ + INTN node; + int m_oldlen; + struct fdt_property *m_prop; + INTN Error = 0; + + + node = fdt_subnode_offset(Fdt, 0, "memory"); + if (node < 0) + { + // Create the memory node + node = fdt_add_subnode(Fdt, 0, "memory"); + + if(node < 0) + { + DEBUG((EFI_D_ERROR, "[%a]:[%dL] fdt add subnode error\n", __FUNCTION__, __LINE__)); + + return node; + } + + } + //find the memory node property + m_prop = fdt_get_property_w(Fdt, node, "memory", &m_oldlen); + if(m_prop) + { + Error = fdt_delprop(Fdt, node, "reg"); + + if (Error) + { + DEBUG ((EFI_D_ERROR, "ERROR:fdt_delprop(): %a\n", fdt_strerror (Error))); + node = -1; + return node; + } + } + + return node; +} + + +EFI_STATUS UpdateMemoryNode(VOID* Fdt) +{ + INTN Error = 0; + EFI_STATUS Status = EFI_SUCCESS; + UINT32 Index = 0; + UINT32 MemIndex; + INTN node; + EFI_MEMORY_DESCRIPTOR *MemoryMap; + EFI_MEMORY_DESCRIPTOR *MemoryMapPtr; + EFI_MEMORY_DESCRIPTOR *MemoryMapPtrCurrent; + UINTN MemoryMapSize; + UINTN Pages0 = 0; + UINTN Pages1 = 0; + UINTN MapKey; + UINTN DescriptorSize; + UINT32 DescriptorVersion; + PHY_MEM_REGION *mRegion; + UINTN MemoryMapLastEndAddress ; + UINTN MemoryMapcontinuousStartAddress ; + UINTN MemoryMapCurrentStartAddress; + BOOLEAN FindMemoryRegionFlag = FALSE; + + node = GetMemoryNode(Fdt); + if (node < 0) + { + DEBUG((EFI_D_ERROR, "Can not find memory node\n")); + return EFI_NOT_FOUND; + } + MemoryMap = NULL; + MemoryMapSize = 0; + MemIndex = 0; + + Status = gBS->GetMemoryMap (&MemoryMapSize, MemoryMap, &MapKey, &DescriptorSize, &DescriptorVersion); + if (Status == EFI_BUFFER_TOO_SMALL) + { + // The UEFI specification advises to allocate more memory for the MemoryMap buffer between successive + // calls to GetMemoryMap(), since allocation of the new buffer may potentially increase memory map size. + Pages0 = EFI_SIZE_TO_PAGES (MemoryMapSize) + 1; + MemoryMap = AllocatePages (Pages0); + if (MemoryMap == NULL) + { + Status = EFI_OUT_OF_RESOURCES; + return Status; + } + Status = gBS->GetMemoryMap (&MemoryMapSize, MemoryMap, &MapKey, &DescriptorSize, &DescriptorVersion); + + if (EFI_ERROR(Status)) + { + DEBUG ((EFI_D_ERROR, "FdtUpdateLib GetMemoryMap Error\n")); + FreePages (MemoryMap, Pages0); + return Status; + } + } + else + { + DEBUG ((EFI_D_ERROR, "FdtUpdateLib GetmemoryMap Status: %r\n",Status)); + return EFI_ABORTED; + } + + mRegion = NULL; + Pages1 = EFI_SIZE_TO_PAGES (sizeof(PHY_MEM_REGION) *( MemoryMapSize / DescriptorSize)); + + mRegion = (PHY_MEM_REGION*)AllocatePool(Pages1); + if (mRegion == NULL) + { + Status = EFI_OUT_OF_RESOURCES; + FreePages (MemoryMap, Pages0); + return Status; + } + + + MemoryMapPtr = MemoryMap; + MemoryMapPtrCurrent = MemoryMapPtr; + MemoryMapLastEndAddress = 0; + MemoryMapcontinuousStartAddress = 0; + MemoryMapCurrentStartAddress = 0; + for (Index = 0; Index < (MemoryMapSize / DescriptorSize); Index++) + { + MemoryMapPtrCurrent = (EFI_MEMORY_DESCRIPTOR*)((UINTN)MemoryMapPtr + Index*DescriptorSize); + MemoryMapCurrentStartAddress = (UINTN)MemoryMapPtrCurrent->PhysicalStart; + + if (!IsMemMapRegion ((EFI_MEMORY_TYPE)MemoryMapPtrCurrent->Type)) + { + continue; + } + else + { + FindMemoryRegionFlag = TRUE; + if(MemoryMapCurrentStartAddress != MemoryMapLastEndAddress) + { + mRegion[MemIndex].BaseHigh= cpu_to_fdt32(MemoryMapcontinuousStartAddress>>32); + mRegion[MemIndex].BaseLow=cpu_to_fdt32(MemoryMapcontinuousStartAddress); + mRegion[MemIndex].LengthHigh= cpu_to_fdt32((MemoryMapLastEndAddress-MemoryMapcontinuousStartAddress)>>32); + mRegion[MemIndex].LengthLow=cpu_to_fdt32(MemoryMapLastEndAddress-MemoryMapcontinuousStartAddress); + MemIndex+=1; + MemoryMapcontinuousStartAddress=MemoryMapCurrentStartAddress; + } + } + MemoryMapLastEndAddress = (UINTN)(MemoryMapPtrCurrent->PhysicalStart + MemoryMapPtrCurrent->NumberOfPages * EFI_PAGE_SIZE); + } + if (FindMemoryRegionFlag) + { + mRegion[MemIndex].BaseHigh = cpu_to_fdt32(MemoryMapcontinuousStartAddress>>32); + mRegion[MemIndex].BaseLow = cpu_to_fdt32(MemoryMapcontinuousStartAddress); + mRegion[MemIndex].LengthHigh = cpu_to_fdt32((MemoryMapLastEndAddress-MemoryMapcontinuousStartAddress)>>32); + mRegion[MemIndex].LengthLow = cpu_to_fdt32(MemoryMapLastEndAddress-MemoryMapcontinuousStartAddress); + } + + Error = fdt_setprop(Fdt, node, "reg",mRegion,sizeof(PHY_MEM_REGION) *(MemIndex+1)); + + FreePool (mRegion); + FreePages (MemoryMap, Pages0); + if (Error) + { + DEBUG ((EFI_D_ERROR, "ERROR:fdt_setprop(): %a\n", fdt_strerror (Error))); + Status = EFI_INVALID_PARAMETER; + return Status; + } + + return Status; +} + + +EFI_STATUS +UpdateNumaNode(VOID* Fdt) +{ + //TODO: Need to update numa node + return EFI_SUCCESS; +} +/* + * Entry point for fdtupdate lib. + */ + +EFI_STATUS EFIFdtUpdate(UINTN FdtFileAddr) +{ + INTN Error; + VOID* Fdt; + UINT32 Size; + UINTN NewFdtBlobSize; + UINTN NewFdtBlobBase; + EFI_STATUS Status = EFI_SUCCESS; + EFI_STATUS UpdateNumaStatus = EFI_SUCCESS; + + + Error = fdt_check_header ((VOID*)(FdtFileAddr)); + if (0 != Error) + { + DEBUG ((EFI_D_ERROR,"ERROR: Device Tree header not valid (%a)\n", fdt_strerror(Error))); + return EFI_INVALID_PARAMETER; + } + + Size = (UINTN)fdt_totalsize ((VOID*)(UINTN)(FdtFileAddr)); + NewFdtBlobSize = Size + ADD_FILE_LENGTH; + Fdt = (VOID*)(UINTN)FdtFileAddr; + + Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, EFI_SIZE_TO_PAGES(NewFdtBlobSize), &NewFdtBlobBase); + if (EFI_ERROR (Status)) + { + return EFI_OUT_OF_RESOURCES; + } + + + Error = fdt_open_into(Fdt,(VOID*)(UINTN)(NewFdtBlobBase), (NewFdtBlobSize)); + if (Error) { + DEBUG ((EFI_D_ERROR, "ERROR:fdt_open_into(): %a\n", fdt_strerror (Error))); + Status = EFI_INVALID_PARAMETER; + goto EXIT; + } + + Fdt = (VOID*)(UINTN)NewFdtBlobBase; + Status = DelPhyhandleUpdateMacAddress(Fdt); + if (EFI_ERROR (Status)) + { + DEBUG ((EFI_D_ERROR, "DelPhyhandleUpdateMacAddress fail:\n")); + Status = EFI_SUCCESS; + } + + Status = UpdateRefClk (Fdt); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "UpdateiRefClk fail.\n")); + } + + Status = UpdateMemoryNode(Fdt); + if (EFI_ERROR (Status)) + { + DEBUG ((EFI_D_ERROR, "UpdateMemoryNode Error\n")); + goto EXIT; + } + + UpdateNumaStatus = UpdateNumaNode(Fdt); + if (EFI_ERROR (UpdateNumaStatus)) + { + DEBUG ((EFI_D_ERROR, "Update NumaNode fail\n")); + } + + gBS->CopyMem(((VOID*)(UINTN)(FdtFileAddr)),((VOID*)(UINTN)(NewFdtBlobBase)),NewFdtBlobSize); + +EXIT: + gBS->FreePages(NewFdtBlobBase,EFI_SIZE_TO_PAGES(NewFdtBlobSize)); + + return Status; + + + +} diff --git a/Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf b/Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf new file mode 100755 index 0000000000..9569b918b2 --- /dev/null +++ b/Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf @@ -0,0 +1,50 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = FdtUpdateLib + FILE_GUID = 02CF1727-E697-47fc-8CC2-5DCB81B26DD9 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = FdtUpdateLib + + +[Sources.common] + FdtUpdateLib.c + + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec + +[LibraryClasses] + ArmLib + FdtLib + PlatformSysCtrlLib + OemMiscLib + +[Protocols] + gHisiBoardNicProtocolGuid + +[Guids] + +[Pcd] + gHisiTokenSpaceGuid.PcdNumaEnable + + diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c b/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c new file mode 100644 index 0000000000..66d62895a6 --- /dev/null +++ b/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c @@ -0,0 +1,197 @@ +/** @file +* +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +I2C_DEVICE gDS3231RtcDevice = { + .Socket = 0, + .Port = 6, + .DeviceType = DEVICE_TYPE_SPD, + .SlaveDeviceAddress = 0x68 +}; + +SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[] = +{ + {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM} +}; + +SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[] = +{ + {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM} +}; + +SERDES_PARAM gSerdesParam = { + .Hilink0Mode = EmHilink0Pcie1X8, + .Hilink1Mode = EmHilink1Pcie0X8, + .Hilink2Mode = EmHilink2Pcie2X8, + .Hilink3Mode = 0x0, + .Hilink4Mode = 0xF, + .Hilink5Mode = EmHilink5Sas1X4, + .Hilink6Mode = 0x0, + .UseSsc = 0, +}; + +SERDES_PARAM gSerdesParam0 = { + .Hilink0Mode = EmHilink0Hccs1X8Width16, + .Hilink1Mode = EmHilink1Hccs0X8Width16, + .Hilink2Mode = EmHilink2Pcie2X8, + .Hilink3Mode = 0x0, + .Hilink4Mode = 0xF, + .Hilink5Mode = EmHilink5Sas1X4, + .Hilink6Mode = 0x0, + .UseSsc = 0, +}; + +SERDES_PARAM gSerdesParam1 = { + .Hilink0Mode = EmHilink0Hccs1X8Width16, + .Hilink1Mode = EmHilink1Hccs0X8Width16, + .Hilink2Mode = EmHilink2Pcie2X8, + .Hilink3Mode = 0x0, + .Hilink4Mode = 0xF, + .Hilink5Mode = EmHilink5Pcie3X4, + .Hilink6Mode = 0xF, + .UseSsc = 0, +}; + +EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId) +{ + if (ParamA == NULL) { + DEBUG((EFI_D_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__)); + return EFI_INVALID_PARAMETER; + } + + (VOID) CopyMem(ParamA, &gSerdesParam, sizeof(*ParamA)); + return EFI_SUCCESS; +} + + +VOID OemPcieResetAndOffReset(void) + { + return; + } + +SMBIOS_TABLE_TYPE9 gPcieSlotInfo[] = { + // PCIe0 Slot 1 + { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, + 0, // Length, + 0 // Handle + }, + 1, // SlotDesignation + SlotTypePciExpressX8, // SlotType + SlotDataBusWidth8X, // SlotDataBusWidth + SlotUsageAvailable, // SlotUsage + SlotLengthOther, // SlotLength + 0x0001, // SlotId + { // SlotCharacteristics1 + 0, // CharacteristicsUnknown :1; + 0, // Provides50Volts :1; + 0, // Provides33Volts :1; + 0, // SharedSlot :1; + 0, // PcCard16Supported :1; + 0, // CardBusSupported :1; + 0, // ZoomVideoSupported :1; + 0 // ModemRingResumeSupported:1; + }, + { // SlotCharacteristics2 + 0, // PmeSignalSupported :1; + 0, // HotPlugDevicesSupported :1; + 0, // SmbusSignalSupported :1; + 0 // Reserved :5; + }, + 0x00, // SegmentGroupNum + 0x00, // BusNum + 0 // DevFuncNum + }, + + // PCIe0 Slot 4 + { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, + 0, // Length, + 0 // Handle + }, + 1, // SlotDesignation + SlotTypePciExpressX8, // SlotType + SlotDataBusWidth8X, // SlotDataBusWidth + SlotUsageAvailable, // SlotUsage + SlotLengthOther, // SlotLength + 0x0004, // SlotId + { // SlotCharacteristics1 + 0, // CharacteristicsUnknown :1; + 0, // Provides50Volts :1; + 0, // Provides33Volts :1; + 0, // SharedSlot :1; + 0, // PcCard16Supported :1; + 0, // CardBusSupported :1; + 0, // ZoomVideoSupported :1; + 0 // ModemRingResumeSupported:1; + }, + { // SlotCharacteristics2 + 0, // PmeSignalSupported :1; + 0, // HotPlugDevicesSupported :1; + 0, // SmbusSignalSupported :1; + 0 // Reserved :5; + }, + 0x00, // SegmentGroupNum + 0x00, // BusNum + 0 // DevFuncNum + } +}; + + +UINT8 OemGetPcieSlotNumber () +{ + return sizeof (gPcieSlotInfo) / sizeof (SMBIOS_TABLE_TYPE9); +} + +EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM] = { + {{STRING_TOKEN(STR_LEMON_C10_DIMM_000), STRING_TOKEN(STR_LEMON_C10_DIMM_001), STRING_TOKEN(STR_LEMON_C10_DIMM_002)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_010), STRING_TOKEN(STR_LEMON_C10_DIMM_011), STRING_TOKEN(STR_LEMON_C10_DIMM_012)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_020), STRING_TOKEN(STR_LEMON_C10_DIMM_021), STRING_TOKEN(STR_LEMON_C10_DIMM_022)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_030), STRING_TOKEN(STR_LEMON_C10_DIMM_031), STRING_TOKEN(STR_LEMON_C10_DIMM_032)}}, + + {{STRING_TOKEN(STR_LEMON_C10_DIMM_100), STRING_TOKEN(STR_LEMON_C10_DIMM_101), STRING_TOKEN(STR_LEMON_C10_DIMM_102)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_110), STRING_TOKEN(STR_LEMON_C10_DIMM_111), STRING_TOKEN(STR_LEMON_C10_DIMM_112)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_120), STRING_TOKEN(STR_LEMON_C10_DIMM_121), STRING_TOKEN(STR_LEMON_C10_DIMM_122)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_130), STRING_TOKEN(STR_LEMON_C10_DIMM_131), STRING_TOKEN(STR_LEMON_C10_DIMM_132)}} +}; + +EFI_HII_HANDLE +EFIAPI +OemGetPackages ( + ) +{ + return HiiAddPackages ( + &gEfiCallerIdGuid, + NULL, + OemMiscLib2PStrings, + NULL, + NULL + ); +} + + diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610Strings.uni b/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610Strings.uni new file mode 100644 index 0000000000..38def406b9 Binary files /dev/null and b/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610Strings.uni differ diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c new file mode 100644 index 0000000000..fa1039bda1 --- /dev/null +++ b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c @@ -0,0 +1,141 @@ +/** @file +* +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = { + {67,0,0,0}, + {225,0,0,3}, + {0xFFFF,0xFFFF,0xFFFF,0xFFFF}, + {0xFFFF,0xFFFF,0xFFFF,0xFFFF} +}; + +// Right now we only support 1P +BOOLEAN OemIsSocketPresent (UINTN Socket) +{ + if (0 == Socket) + { + return TRUE; + } + + if(1 == Socket) + { + return TRUE; + } + + return FALSE; +} + + +UINTN OemGetSocketNumber (VOID) +{ + + if(!OemIsMpBoot()) + { + return 1; + } + + return 2; + +} + + +UINTN OemGetDdrChannel (VOID) +{ + return 4; +} + + +UINTN OemGetDimmSlot(UINTN Socket, UINTN Channel) +{ + return 2; +} + + +// Nothing to do for EVB +VOID OemPostEndIndicator (VOID) +{ + + DEBUG((EFI_D_ERROR,"M3 release reset CONFIG.........")); + + MmioWrite32(0xd0002180, 0x3); + MmioWrite32(0xd0002194, 0xa4); + MmioWrite32(0xd0000a54, 0x1); + + MicroSecondDelay(10000); + + MmioWrite32(0xd0002108, 0x1); + MmioWrite32(0xd0002114, 0x1); + MmioWrite32(0xd0002120, 0x1); + MmioWrite32(0xd0003108, 0x1); + + MicroSecondDelay(500000); + DEBUG((EFI_D_ERROR,"Done\n")); + +} + + + +VOID CoreSelectBoot(VOID) +{ + if (!PcdGet64 (PcdTrustedFirmwareEnable)) + { + StartupAp (); + } + + return; +} + +BOOLEAN OemIsMpBoot() +{ + UINT32 Tmp; + + Tmp = MmioRead32(0x602E0050); + if ( ((Tmp >> 10) & 0xF) == 0x3) + return TRUE; + else + return FALSE; +} + +VOID OemLpcInit(VOID) +{ + LpcInit(); + return; +} + +UINT32 OemIsWarmBoot(VOID) +{ + return 0; +} + +VOID OemBiosSwitch(UINT32 Master) +{ + (VOID)Master; + return; +} + +BOOLEAN OemIsNeedDisableExpanderBuffer(VOID) +{ + return TRUE; +} diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf new file mode 100644 index 0000000000..310bbaea84 --- /dev/null +++ b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf @@ -0,0 +1,54 @@ +#/** @file +# +# Copyright (c) 2015, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = OemMiscLib2P + FILE_GUID = B9CE7465-21A2-4ecd-B347-BBDDBD098CEE + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = OemMiscLib + +[Sources.common] + BoardFeature2PHi1610.c + OemMiscLib2PHi1610.c + BoardFeature2PHi1610Strings.uni + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + ArmPkg/ArmPkg.dec + + Silicon/Hisilicon/HisiPkg.dec + +[LibraryClasses] + PcdLib + TimerLib + +[BuildOptions] + +[Ppis] + gEfiPeiReadOnlyVariable2PpiGuid ## SOMETIMES_CONSUMES + +[Pcd] + gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz + +[FixedPcd.common] + +[Guids] + +[Protocols] + diff --git a/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c b/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c new file mode 100644 index 0000000000..c58118fe5e --- /dev/null +++ b/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c @@ -0,0 +1,156 @@ +/** @file + + Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2016, Linaro Limited. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +UINT64 pcie_subctrl_base_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0000000, 0xa0000000,0xa0000000,0xa0000000,0xa0000000,0xa0000000,0xa0000000,0xa0000000}, + {0xb0000000,0xb0000000,0xb0000000,0xb0000000, 0xb0000000,0xb0000000,0xb0000000,0xb0000000}}; +UINT64 PCIE_APB_SLAVE_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000}, + {0xb0090000, 0xb0200000, 0xb00a0000, 0xb00b0000}}; +UINT64 PCIE_PHY_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000}, + {0xb00c0000,0xb00d0000, 0xb00e0000, 0xb00f0000}}; +UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040}, + {0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040}}; + +PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = { + {// HostBridge 0 + /* Port 0 */ + { + PCI_HB0RB0_ECAM_BASE, //ecam + 0, //BusBase + 31, //BusLimit + PCI_HB0RB0_PCIREGION_BASE, //Membase + PCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //Memlimit + PCI_HB0RB0_IO_BASE, //IoBase + (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + PCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB0RB0_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB0RB0_PCI_BASE), //RbPciBar + PCI_HB0RB0_PCIREGION_BASE, //PciRegionBase + PCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //PciRegionLimit + + }, + /* Port 1 */ + { + PCI_HB0RB1_ECAM_BASE,//ecam + 224, //BusBase + 254, //BusLimit + PCI_HB0RB1_PCIREGION_BASE, //Membase + PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //MemLimit + (PCI_HB0RB1_IO_BASE), //IoBase + (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimit + PCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB0RB1_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB0RB1_PCI_BASE), //RbPciBar + PCI_HB0RB1_PCIREGION_BASE, //PciRegionBase + PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //PciRegionLimit + }, + /* Port 2 */ + { + PCI_HB0RB2_ECAM_BASE, + 128, //BusBase + 159, //BusLimit + PCI_HB0RB2_PCIREGION_BASE ,//MemBase + PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit + (PCI_HB0RB2_IO_BASE), //IOBase + (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimit + PCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB0RB2_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB0RB2_PCI_BASE), //RbPciBar + PCI_HB0RB2_PCIREGION_BASE, //PciRegionBase + PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //PciRegionLimit + }, + + /* Port 3 */ + { + PCI_HB0RB3_ECAM_BASE, + 96, //BusBase + 127, //BusLimit + (PCI_HB0RB3_ECAM_BASE), //MemBase + (PCI_HB0RB3_ECAM_BASE + PCI_HB0RB3_ECAM_SIZE - 1), //MemLimit + (0), //IoBase + (0), //IoLimit + 0, + 0, + (PCI_HB0RB3_PCI_BASE), //RbPciBar + 0, + 0 + } + }, +{// HostBridge 1 + /* Port 0 */ + { + PCI_HB1RB0_ECAM_BASE, + 128, //BusBase + 159, //BusLimit + (PCI_HB1RB0_ECAM_BASE), //MemBase + (PCI_HB1RB0_ECAM_BASE + PCI_HB1RB0_ECAM_SIZE - 1), //MemLimit + (0), //IoBase + (0), //IoLimit + 0, + 0, + (PCI_HB1RB0_PCI_BASE), //RbPciBar + 0, + 0 + }, + /* Port 1 */ + { + PCI_HB1RB1_ECAM_BASE, + 160, //BusBase + 191, //BusLimit + (PCI_HB1RB1_ECAM_BASE), //MemBase + (PCI_HB1RB1_ECAM_BASE + PCI_HB1RB1_ECAM_SIZE - 1), //MemLimit + (0), //IoBase + (0), //IoLimit + 0, + 0, + (PCI_HB1RB1_PCI_BASE), //RbPciBar + 0, + 0 + }, + /* Port 2 */ + { + PCI_HB1RB2_ECAM_BASE, + 192, //BusBase + 223, //BusLimit + (PCI_HB1RB2_ECAM_BASE), //MemBase + (PCI_HB1RB2_ECAM_BASE + PCI_HB1RB2_ECAM_SIZE - 1), //MemLimit + (0), //IoBase + (0), //IoLimit + 0, + 0, + (PCI_HB1RB2_PCI_BASE), //RbPciBar + 0, + 0 + }, + + /* Port 3 */ + { + PCI_HB1RB3_ECAM_BASE, + 224, //BusBase + 255, //BusLimit + (PCI_HB1RB3_ECAM_BASE), //MemBase + (PCI_HB1RB3_ECAM_BASE + PCI_HB1RB3_ECAM_SIZE - 1), //MemLimit + (0), //IoBase + (0), //IoLimit + 0, + 0, + (PCI_HB1RB3_PCI_BASE), //RbPciBar + 0, + 0 + } + } +}; + diff --git a/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf b/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf new file mode 100644 index 0000000000..4d2dbbaf0d --- /dev/null +++ b/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf @@ -0,0 +1,182 @@ +## @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformPciLib + FILE_GUID = 61b7276a-fc67-11e5-82fd-47ea9896dd5d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + +[Sources] + PlatformPciLib.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/Hisilicon/HisiPkg.dec + +[LibraryClasses] + PcdLib + +[FixedPcd] + gHisiTokenSpaceGuid.PcdHb1BaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PciHb0Rb0Base + gHisiTokenSpaceGuid.PciHb0Rb1Base + gHisiTokenSpaceGuid.PciHb0Rb2Base + gHisiTokenSpaceGuid.PciHb0Rb3Base + gHisiTokenSpaceGuid.PciHb0Rb4Base + gHisiTokenSpaceGuid.PciHb0Rb5Base + gHisiTokenSpaceGuid.PciHb0Rb6Base + gHisiTokenSpaceGuid.PciHb0Rb7Base + gHisiTokenSpaceGuid.PciHb1Rb0Base + gHisiTokenSpaceGuid.PciHb1Rb1Base + gHisiTokenSpaceGuid.PciHb1Rb2Base + gHisiTokenSpaceGuid.PciHb1Rb3Base + gHisiTokenSpaceGuid.PciHb1Rb4Base + gHisiTokenSpaceGuid.PciHb1Rb5Base + gHisiTokenSpaceGuid.PciHb1Rb6Base + gHisiTokenSpaceGuid.PciHb1Rb7Base + gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress + + gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize + + gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase + + gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase + + gHisiTokenSpaceGuid.PcdHb0Rb0IoBase + gHisiTokenSpaceGuid.PcdHb0Rb0IoSize + gHisiTokenSpaceGuid.PcdHb0Rb1IoBase + gHisiTokenSpaceGuid.PcdHb0Rb1IoSize + gHisiTokenSpaceGuid.PcdHb0Rb2IoBase + gHisiTokenSpaceGuid.PcdHb0Rb2IoSize + gHisiTokenSpaceGuid.PcdHb0Rb3IoBase + gHisiTokenSpaceGuid.PcdHb0Rb3IoSize + gHisiTokenSpaceGuid.PcdHb0Rb4IoBase + gHisiTokenSpaceGuid.PcdHb0Rb4IoSize + gHisiTokenSpaceGuid.PcdHb0Rb5IoBase + gHisiTokenSpaceGuid.PcdHb0Rb5IoSize + gHisiTokenSpaceGuid.PcdHb0Rb6IoBase + gHisiTokenSpaceGuid.PcdHb0Rb6IoSize + gHisiTokenSpaceGuid.PcdHb0Rb7IoBase + gHisiTokenSpaceGuid.PcdHb0Rb7IoSize + gHisiTokenSpaceGuid.PcdHb1Rb0IoBase + gHisiTokenSpaceGuid.PcdHb1Rb0IoSize + gHisiTokenSpaceGuid.PcdHb1Rb1IoBase + gHisiTokenSpaceGuid.PcdHb1Rb1IoSize + gHisiTokenSpaceGuid.PcdHb1Rb2IoBase + gHisiTokenSpaceGuid.PcdHb1Rb2IoSize + gHisiTokenSpaceGuid.PcdHb1Rb3IoBase + gHisiTokenSpaceGuid.PcdHb1Rb3IoSize + gHisiTokenSpaceGuid.PcdHb1Rb4IoBase + gHisiTokenSpaceGuid.PcdHb1Rb4IoSize + gHisiTokenSpaceGuid.PcdHb1Rb5IoBase + gHisiTokenSpaceGuid.PcdHb1Rb5IoSize + gHisiTokenSpaceGuid.PcdHb1Rb6IoBase + gHisiTokenSpaceGuid.PcdHb1Rb6IoSize + gHisiTokenSpaceGuid.PcdHb1Rb7IoBase + gHisiTokenSpaceGuid.PcdHb1Rb7IoSize diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc new file mode 100644 index 0000000000..603cf34b84 --- /dev/null +++ b/Platform/Hisilicon/D05/D05.dsc @@ -0,0 +1,663 @@ +# +# Copyright (c) 2011-2012, ARM Limited. All rights reserved. +# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015-2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = D05 + PLATFORM_GUID = D0D445F1-B2CA-4101-9986-1B23525CBEA6 + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/Hisilicon/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf + DEFINE EDK2_SKIP_PEICORE=0 + DEFINE INCLUDE_TFTP_COMMAND=1 + DEFINE NETWORK_IP6_ENABLE = FALSE + DEFINE HTTP_BOOT_ENABLE = FALSE + +!include Silicon/Hisilicon/Hisilicon.dsc.inc + +[LibraryClasses.common] + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf + ArmPlatformLib|Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf + ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf + NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf + LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf + + + I2CLib|Silicon/Hisilicon/Library/I2CLib/I2CLib.inf + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf + + IpmiCmdLib|Silicon/Hisilicon/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.inf + + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf + DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf + UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf + IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf + OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + +!if $(NETWORK_IP6_ENABLE) == TRUE + TcpIoLib|MdeModulePkg/Library/DxeTcpIoLib/DxeTcpIoLib.inf +!endif + +!if $(HTTP_BOOT_ENABLE) == TRUE + HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf +!endif + +!ifdef $(FDT_ENABLE) + #FDTUpdateLib + FdtUpdateLib|Platform/Hisilicon/D05/Library/FdtUpdateLib/FdtUpdateLib.inf +!endif #$(FDT_ENABLE) + + CpldIoLib|Silicon/Hisilicon/Library/CpldIoLib/CpldIoLib.inf + + SerdesLib|Silicon/Hisilicon/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.inf + + TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf + #D05 RTC hardware is same as D03 + RealTimeClockLib|Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf + + OemMiscLib|Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf + OemAddressMapLib|Platform/Hisilicon/D05/Library/OemAddressMapD05/OemAddressMapD05.inf + PlatformSysCtrlLib|Silicon/Hisilicon/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.inf + + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf + PlatformBdsLib|Silicon/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf + + # USB Requirements + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + + LpcLib|Silicon/Hisilicon/Hi1610/Library/LpcLib/LpcLib.inf + SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf + +[LibraryClasses.common.SEC] + ArmPlatformLib|Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf + + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + I2CLib|Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf + SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf + +[BuildOptions] + GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/Silicon/Hisilicon/Hi1616/Include + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + +[PcdsFeatureFlag.common] + +!if $(EDK2_SKIP_PEICORE) == 1 + gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE + gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE +!endif + + ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. + # It could be set FALSE to save size. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE + +[PcdsFixedAtBuild.common] + gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"D05" + + gArmPlatformTokenSpaceGuid.PcdCoreCount|8 + + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 + + # Stacks for MPCores in Secure World + gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0xE1000000 + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000 + + # Stacks for MPCores in Monitor Mode + gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0xE100FF00 + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100 + + # Stacks for MPCores in Normal World + gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0xE1000000 + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0xFF00 + + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000 + + + gArmTokenSpaceGuid.PcdSystemMemorySize|0x3FC00000 + + + # Size of the region used by UEFI in permanent memory (Reserved 64MB) + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x10000000 + + gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|1 + gHisiTokenSpaceGuid.PcdSlotPerChannelNum|0x2 + + + gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0x94 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7 + # bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15 + ## enable all the pcie device, because it is ok for bios + gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P|0x34F4 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7 + # bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15 + + ## SP805 Watchdog - Motherboard Watchdog + gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x601e0000 + + ## Serial Terminal + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x602B0000 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + + gArmPlatformTokenSpaceGuid.PL011UartClkInHz|200000000 + + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1 + # use the TTY terminal type (which has a working backspace) + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4 + + + gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0xa0040000 + gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000 + gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000 + gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000 + + + gHisiTokenSpaceGuid.PcdIsMPBoot|1 + gHisiTokenSpaceGuid.PcdSocketMask|0x3 + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D05 UEFI 16.12 Release" + + gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18" + + gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L"1.12" + + gHisiTokenSpaceGuid.PcdSystemProductName|L"D05" + gHisiTokenSpaceGuid.PcdSystemVersion|L"Estuary" + gHisiTokenSpaceGuid.PcdBaseBoardProductName|L"D05" + gHisiTokenSpaceGuid.PcdBaseBoardVersion|L"Estuary" + + gHisiTokenSpaceGuid.PcdCPUInfo|L"Hi1616" + + + gArmTokenSpaceGuid.PcdGicDistributorBase|0x4D000000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x4D100000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xFE000000 + + + # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut) + gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)" + gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()" + + # + # ARM Architectual Timer Frequency + # + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|50000000 + + + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE + gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 } + + gHisiTokenSpaceGuid.PcdSysControlBaseAddress|0x40010000 + gHisiTokenSpaceGuid.PcdMailBoxAddress|0x0000FFF8 + + gHisiTokenSpaceGuid.PcdCpldBaseAddress|0x78000000 + + gHisiTokenSpaceGuid.PcdSFCCFGBaseAddress|0xA6000000 + gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress|0xA4000000 + + + gHisiTokenSpaceGuid.PcdPeriSubctrlAddress|0x40000000 + + + gHisiTokenSpaceGuid.PcdMdioSubctrlAddress|0x60000000 + + ## DTB address at spi flash + gHisiTokenSpaceGuid.FdtFileAddress|0xA47A0000 + + gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType|0x1 + + gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x80010000 + + gHisiTokenSpaceGuid.PcdTopOfLowMemory|0x40000000 + + gHisiTokenSpaceGuid.PcdBottomOfHighMemory|0x1000000000 + + gHisiTokenSpaceGuid.PcdNORFlashBase|0x70000000 + gHisiTokenSpaceGuid.PcdNORFlashCachableSize|0x8000000 + + gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x1 + gHisiTokenSpaceGuid.PcdNumaEnable|1 + gHisiTokenSpaceGuid.PcdMacAddress|0xA47E0000 + + gHisiTokenSpaceGuid.PcdHb1BaseAddress|0x40000000000 + + + gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress|0xA0000000 + gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress|0xA0000000 + gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress|0xA0000000 + gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress|0xA0000000 + gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress|0x8A0000000 + gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress|0x8B0000000 + gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize|0x8000000 + gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress|0x8A0000000 + gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress|0x8B0000000 + gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress|0x400A0000000 + gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress|0x400A0000000 + gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress|0x64000000000 + gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize|0x400000000 + gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress|0x400A0000000 + gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress|0x74000000000 + gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize|0x400000000 + gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress|0x78000000000 + gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize|0x400000000 + gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress|0x408A0000000 + gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize|0x10000000 + gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress|0x408A0000000 + gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize|0x10000000 + + gHisiTokenSpaceGuid.PciHb0Rb0Base|0xa0090000 + gHisiTokenSpaceGuid.PciHb0Rb1Base|0xa0200000 + gHisiTokenSpaceGuid.PciHb0Rb2Base|0xa00a0000 + gHisiTokenSpaceGuid.PciHb0Rb3Base|0xa00b0000 + gHisiTokenSpaceGuid.PciHb0Rb4Base|0x8a0090000 + gHisiTokenSpaceGuid.PciHb0Rb5Base|0x8a0200000 + gHisiTokenSpaceGuid.PciHb0Rb6Base|0x8a00a0000 + gHisiTokenSpaceGuid.PciHb0Rb7Base|0x8a00b0000 + gHisiTokenSpaceGuid.PciHb1Rb0Base|0x600a0090000 + gHisiTokenSpaceGuid.PciHb1Rb1Base|0x600a0200000 + gHisiTokenSpaceGuid.PciHb1Rb2Base|0x600a00a0000 + gHisiTokenSpaceGuid.PciHb1Rb3Base|0x600a00b0000 + gHisiTokenSpaceGuid.PciHb1Rb4Base|0x700a0090000 + gHisiTokenSpaceGuid.PciHb1Rb5Base|0x700a0200000 + gHisiTokenSpaceGuid.PciHb1Rb6Base|0x700a00a0000 + gHisiTokenSpaceGuid.PciHb1Rb7Base|0x700a00b0000 + + gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress|0xa8400000 + gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xa9400000 + gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8800000 + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77effff + gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0xab400000 + gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0xa9000000 + gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2feffff + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0800000 + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77effff + gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0xac900000 + gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36effff + gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress|0xb9800000 + gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize|0x67effff + gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress|0x400a8400000 + gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000 + gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x20000000 + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xcfffffff + gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000 + gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x30000000 + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xbfffffff + gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000 + gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xafffffff + gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000 + gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress|0x408ab400000 + gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize|0xbeffff + + gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xA8400000 + gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xA9400000 + gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8800000 + gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase|0xAB400000 + gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase|0x8A9000000 + gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0800000 + gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase|0x8AC900000 + gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000 + gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000 + gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase|0x400A9400000 + gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65020000000 + gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase|0x400AB400000 + gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75030000000 + gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase|0x79040000000 + gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase|0x408AA400000 + gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase|0x408AB400000 + + gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0xa8ff0000 + gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0xa9ff0000 + gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xafff0000 + gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0xabff0000 + gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase|0x8abff0000 + gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b7ff0000 + gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase|0x8afff0000 + gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase|0x8bfff0000 + gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase|0x400a8ff0000 + gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase|0x400a9ff0000 + gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase|0x67fffff0000 + gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase|0x400abff0000 + gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase|0x77fffff0000 + gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase|0x7bfffff0000 + gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase|0x408aaff0000 + gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase|0x408abff0000 + + gHisiTokenSpaceGuid.PcdHb0Rb0IoBase|0 + gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0 + gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0 + gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb0Rb3IoBase|0 + gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb0Rb4IoBase|0 + gHisiTokenSpaceGuid.PcdHb0Rb4IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb0Rb5IoBase|0 + gHisiTokenSpaceGuid.PcdHb0Rb5IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb0Rb6IoBase|0 + gHisiTokenSpaceGuid.PcdHb0Rb6IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb0Rb7IoBase|0 + gHisiTokenSpaceGuid.PcdHb0Rb7IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb1Rb0IoBase|0 + gHisiTokenSpaceGuid.PcdHb1Rb0IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb1Rb1IoBase|0 + gHisiTokenSpaceGuid.PcdHb1Rb1IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb1Rb2IoBase|0 + gHisiTokenSpaceGuid.PcdHb1Rb2IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb1Rb3IoBase|0 + gHisiTokenSpaceGuid.PcdHb1Rb3IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb1Rb4IoBase|0 + gHisiTokenSpaceGuid.PcdHb1Rb4IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb1Rb5IoBase|0 + gHisiTokenSpaceGuid.PcdHb1Rb5IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb1Rb6IoBase|0 + gHisiTokenSpaceGuid.PcdHb1Rb6IoSize|0xffff #64K + + gHisiTokenSpaceGuid.PcdHb1Rb7IoBase|0 + gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0xffff #64K + + gHisiTokenSpaceGuid.Pcdsoctype|0x1610 + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ +[Components.common] + + # + # SEC + # + + # + # PEI Phase modules + # + ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + MdeModulePkg/Core/Pei/PeiMain.inf + MdeModulePkg/Universal/PCD/Pei/Pcd.inf + Platform/Hisilicon/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf + + ArmPlatformPkg/PlatformPei/PlatformPeim.inf + + Platform/Hisilicon/D05/MemoryInitPei/MemoryInitPeim.inf + ArmPkg/Drivers/CpuPei/CpuPei.inf + IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf + MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + + Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf + Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf + + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { + + NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf + } + + # + # DXE + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf + } + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf + + # + # Architectural Protocols + # + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + + Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf + + Platform/Hisilicon/D05/Drivers/SFC/SfcDxeDriver.inf + + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + # Sometimes we can use EmuVariableRuntimeDxe instead of real flash variable store for debug. + #MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf + Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + } + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf { + + CpldIoLib|Silicon/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.inf + } + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + # Simple TextIn/TextOut for UEFI Terminal + EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf + + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + + ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf + IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf + # + #ACPI + # + Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + + Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf + Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf + + # + # Usb Support + # + Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + Platform/Hisilicon/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf + + # + #network + # + Platform/Hisilicon/D05/Drivers/Net/SnpPV660Dxe/SnpPV600Dxe.inf + + MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf + MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf + MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf + MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf + MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf + MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf + MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf +!if $(NETWORK_IP6_ENABLE) == TRUE + NetworkPkg/Ip6Dxe/Ip6Dxe.inf + NetworkPkg/TcpDxe/TcpDxe.inf + NetworkPkg/Udp6Dxe/Udp6Dxe.inf + NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf + NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf + NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf +!else + MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf + MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf +!endif + MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf +!if $(HTTP_BOOT_ENABLE) == TRUE + NetworkPkg/DnsDxe/DnsDxe.inf + NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf + NetworkPkg/HttpDxe/HttpDxe.inf + NetworkPkg/HttpBootDxe/HttpBootDxe.inf +!endif + + + Platform/Hisilicon/D05/Drivers/Sas/SasDxeDriver.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + + Platform/Hisilicon/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf + Platform/Hisilicon/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf + Platform/Hisilicon/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf + + Platform/Hisilicon/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf + + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf + +!ifdef $(FDT_ENABLE) + Silicon/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf { + + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + } +!endif #$(FDT_ENABLE) + + #PCIe Support + Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf { + + NULL|Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf + } + Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf + Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf { + + NULL|Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf + } + + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + + Platform/Hisilicon/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf + Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf + Platform/Hisilicon/D05/Drivers/Sm750Dxe/UefiSmi.inf + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf + + + Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf + + # + # Memory test + # + MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf + # + # UEFI application (Shell Embedded Boot Loader) + # + ShellPkg/Application/Shell/Shell.inf { + + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf +!if $(NETWORK_IP6_ENABLE) == TRUE + NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2CommandsLib.inf +!endif + +!ifdef $(INCLUDE_DP) + NULL|ShellPkg/Library/UefiDpLib/UefiDpLib.inf +!endif #$(INCLUDE_DP) +!ifdef $(INCLUDE_TFTP_COMMAND) + NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf +!endif #$(INCLUDE_TFTP_COMMAND) + + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 + } diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf new file mode 100644 index 0000000000..6cd7239d94 --- /dev/null +++ b/Platform/Hisilicon/D05/D05.fdf @@ -0,0 +1,358 @@ +# +# Copyright (c) 2011, 2012, ARM Limited. All rights reserved. +# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015-2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[DEFINES] + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ +[FD.D05] + +BaseAddress = 0xA4800000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. + +Size = 0x00300000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +ErasePolarity = 1 + +# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x00010000 +NumBlocks = 0x30 + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +################################################################################ + +0x00000000|0x00040000 +gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize +FILE = Platform/Hisilicon/D05/Sec/FVMAIN_SEC.Fv + +0x00040000|0x00240000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT + +0x00280000|0x00020000 +gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base +FILE = Platform/Hisilicon/D05/bl1.bin +0x002A0000|0x00020000 +FILE = Platform/Hisilicon/D05/fip.bin + +0x002D0000|0x0000E000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +DATA = { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid = + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0x20000 + 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + #Signature "_FVH" #Attributes + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, + #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0x36, 0x09, 0x00, 0x00, 0x00, 0x02, + #Blockmap[0]: 2 Blocks * 0x10000 Bytes / Block + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, + #Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER gEfiVariableGuid + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, + #Size: 0xe000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xdFB8 + 0xB8, 0xdF, 0x00, 0x00, + #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +0x002DE000|0x00002000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +#NV_FTW_WORKING +DATA = { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid = + 0x2B, 0x29, 0x58, 0x9E, 0x68, 0x7C, 0x7D, 0x49, + 0xA0, 0xCE, 0x65, 0x0 , 0xFD, 0x9F, 0x1B, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved + 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0 + 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +0x002E0000|0x00010000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + +0x002F0000|0x00010000 +FILE = Platform/Hisilicon/D03/CustomData.Fv + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +[FV.FvMain] +BlockSize = 0x40 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 16 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + APRIORI DXE { + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + } + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + INF Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF Platform/Hisilicon/D05/Drivers/SFC/SfcDxeDriver.inf + + INF Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf + + + INF Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + # Simple TextIn/TextOut for UEFI Terminal + + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatBinPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + INF IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf + + # + # Usb Support + # + + INF Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf + INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + INF Platform/Hisilicon/D05/Drivers/OhciDxe/OhciDxe.inf + INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + INF Platform/Hisilicon/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf + INF Platform/Hisilicon/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + INF Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf + + INF Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf + INF Platform/Hisilicon/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf + INF Platform/Hisilicon/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf + + INF Platform/Hisilicon/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf + + + INF Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf + + INF Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf + + # + #ACPI + # + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + INF Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf + + INF RuleOverride=ACPITABLE Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf + INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf + + # + #Network + # + + INF Platform/Hisilicon/D05/Drivers/Net/SnpPV660Dxe/SnpPV600Dxe.inf + + INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf + INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf + INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf + INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf + INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf + INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf + INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf +!if $(NETWORK_IP6_ENABLE) == TRUE + INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf + INF NetworkPkg/TcpDxe/TcpDxe.inf + INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf + INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf + INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf + INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf +!else + INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf + INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf +!endif + INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf +!if $(HTTP_BOOT_ENABLE) == TRUE + INF NetworkPkg/DnsDxe/DnsDxe.inf + INF NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf + INF NetworkPkg/HttpDxe/HttpDxe.inf + INF NetworkPkg/HttpBootDxe/HttpBootDxe.inf +!endif + +!ifdef $(FDT_ENABLE) + INF Silicon/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf +!endif #$(FDT_ENABLE) + + # + # PCI Support + # + INF Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf + INF Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf + INF Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + + INF Platform/Hisilicon/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf + # VGA Driver + # + INF Platform/Hisilicon/D05/Drivers/Sm750Dxe/UefiSmi.inf + INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + INF Platform/Hisilicon/D05/Drivers/Sas/SasDxeDriver.inf + + # + # Build Shell from latest source code instead of prebuilt binary + # + INF ShellPkg/Application/Shell/Shell.inf + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + + INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf + +[FV.FVMAIN_COMPACT] +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + APRIORI PEI { + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + } + INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + INF MdeModulePkg/Core/Pei/PeiMain.inf + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf + + INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + + INF Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf + + INF Platform/Hisilicon/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf + INF Platform/Hisilicon/D05/MemoryInitPei/MemoryInitPeim.inf + INF ArmPkg/Drivers/CpuPei/CpuPei.inf + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf + INF Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf + + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } + } + + +!include Silicon/Hisilicon/Hisilicon.fdf.inc + diff --git a/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c b/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c new file mode 100644 index 0000000000..76a055cbe9 --- /dev/null +++ b/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c @@ -0,0 +1,64 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +VOID +QResetAp ( + VOID + ) +{ + MmioWrite64(FixedPcdGet64(PcdMailBoxAddress), 0x0); + (VOID)WriteBackInvalidateDataCacheRange((VOID *) FixedPcdGet64(PcdMailBoxAddress), 8); + + if (!PcdGet64 (PcdTrustedFirmwareEnable)) { + StartupAp(); + } +} + + +EFI_STATUS +EFIAPI +EarlyConfigEntry ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + DEBUG((DEBUG_INFO,"SMMU CONFIG.........")); + (VOID)SmmuConfigForBios(); + DEBUG((DEBUG_INFO,"Done\n")); + + DEBUG((DEBUG_INFO,"AP CONFIG.........")); + (VOID)QResetAp(); + DEBUG((DEBUG_INFO,"Done\n")); + + DEBUG((DEBUG_INFO,"MN CONFIG.........")); + (VOID)MN_CONFIG(); + DEBUG((DEBUG_INFO,"Done\n")); + + return EFI_SUCCESS; +} + diff --git a/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf b/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf new file mode 100644 index 0000000000..9d8ea7e047 --- /dev/null +++ b/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf @@ -0,0 +1,53 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = EarlyConfigPeimD05 + FILE_GUID = A181AD33-E64A-4084-A54A-A69DF1FB0ABF + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = EarlyConfigEntry + +[Sources.common] + EarlyConfigPeimD05.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Hisilicon/HisiPkg.dec + +[LibraryClasses] + ArmLib + CacheMaintenanceLib + DebugLib + IoLib + PcdLib + PeimEntryPoint + PlatformSysCtrlLib + +[Pcd] + gHisiTokenSpaceGuid.PcdMailBoxAddress + gHisiTokenSpaceGuid.PcdPeriSubctrlAddress + gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable + +[Depex] +## As we will clean mailbox in this module, need to wait memory init complete + gEfiPeiMemoryDiscoveredPpiGuid + +[BuildOptions] + diff --git a/Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c b/Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c new file mode 100644 index 0000000000..15a509be5d --- /dev/null +++ b/Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c @@ -0,0 +1,225 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +I2C_DEVICE gDS3231RtcDevice = { + .Socket = 0, + .Port = 4, + .DeviceType = DEVICE_TYPE_SPD, + .SlaveDeviceAddress = 0x68 +}; + +SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[] = { + {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM} +}; + +SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[] = { + {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM} +}; + +SERDES_PARAM gSerdesParamNA = { + .Hilink0Mode = EmHilink0Hccs1X8Width16, + .Hilink1Mode = EmHilink1Hccs0X8Width16, + .Hilink2Mode = EmHilink2Pcie2X8, + .Hilink3Mode = 0x0, + .Hilink4Mode = 0xF, + .Hilink5Mode = EmHilink5Sas1X4, + .Hilink6Mode = 0x0, + .UseSsc = 0, +}; + +SERDES_PARAM gSerdesParamNB = { + .Hilink0Mode = EmHilink0Pcie1X8, + .Hilink1Mode = EmHilink1Pcie0X8, + .Hilink2Mode = EmHilink2Sas0X8, + .Hilink3Mode = 0x0, + .Hilink4Mode = 0xF, + .Hilink5Mode = EmHilink5Pcie2X2Pcie3X2, + .Hilink6Mode = 0xF, + .UseSsc = 0, +}; + +SERDES_PARAM gSerdesParamS1NA = { + .Hilink0Mode = EmHilink0Hccs1X8Width16, + .Hilink1Mode = EmHilink1Hccs0X8Width16, + .Hilink2Mode = EmHilink2Pcie2X8, + .Hilink3Mode = 0x0, + .Hilink4Mode = 0xF, + .Hilink5Mode = EmHilink5Sas1X4, + .Hilink6Mode = 0x0, + .UseSsc = 0, +}; + +SERDES_PARAM gSerdesParamS1NB = { + .Hilink0Mode = EmHilink0Pcie1X8, + .Hilink1Mode = EmHilink1Pcie0X8, + .Hilink2Mode = EmHilink2Sas0X8, + .Hilink3Mode = 0x0, + .Hilink4Mode = 0xF, + .Hilink5Mode = EmHilink5Pcie2X2Pcie3X2, + .Hilink6Mode = 0xF, + .UseSsc = 0, +}; + + +EFI_STATUS +OemGetSerdesParam ( + OUT SERDES_PARAM *ParamA, + OUT SERDES_PARAM *ParamB, + IN UINT32 SocketId + ) +{ + if (ParamA == NULL || ParamB == NULL) { + DEBUG((DEBUG_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__)); + return EFI_INVALID_PARAMETER; + } + + if (SocketId == 0) { + (VOID) CopyMem(ParamA, &gSerdesParamNA, sizeof(*ParamA)); + (VOID) CopyMem(ParamB, &gSerdesParamNB, sizeof(*ParamB)); + } else { + (VOID) CopyMem(ParamA, &gSerdesParamS1NA, sizeof(*ParamA)); + (VOID) CopyMem(ParamB, &gSerdesParamS1NB, sizeof(*ParamB)); + } + + return EFI_SUCCESS; +} + +VOID +OemPcieResetAndOffReset ( + VOID + ) +{ + return; +} + +SMBIOS_TABLE_TYPE9 gPcieSlotInfo[] = { + // PCIe0 Slot 1 + { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, + 0, // Length, + 0 // Handle + }, + 1, // SlotDesignation + SlotTypePciExpressX8, // SlotType + SlotDataBusWidth8X, // SlotDataBusWidth + SlotUsageAvailable, // SlotUsage + SlotLengthOther, // SlotLength + 0x0001, // SlotId + { // SlotCharacteristics1 + 0, // CharacteristicsUnknown :1; + 0, // Provides50Volts :1; + 0, // Provides33Volts :1; + 0, // SharedSlot :1; + 0, // PcCard16Supported :1; + 0, // CardBusSupported :1; + 0, // ZoomVideoSupported :1; + 0 // ModemRingResumeSupported:1; + }, + { // SlotCharacteristics2 + 0, // PmeSignalSupported :1; + 0, // HotPlugDevicesSupported :1; + 0, // SmbusSignalSupported :1; + 0 // Reserved :5; + }, + 0x00, // SegmentGroupNum + 0x00, // BusNum + 0 // DevFuncNum + }, + + // PCIe0 Slot 4 + { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, + 0, // Length, + 0 // Handle + }, + 1, // SlotDesignation + SlotTypePciExpressX8, // SlotType + SlotDataBusWidth8X, // SlotDataBusWidth + SlotUsageAvailable, // SlotUsage + SlotLengthOther, // SlotLength + 0x0004, // SlotId + { // SlotCharacteristics1 + 0, // CharacteristicsUnknown :1; + 0, // Provides50Volts :1; + 0, // Provides33Volts :1; + 0, // SharedSlot :1; + 0, // PcCard16Supported :1; + 0, // CardBusSupported :1; + 0, // ZoomVideoSupported :1; + 0 // ModemRingResumeSupported:1; + }, + { // SlotCharacteristics2 + 0, // PmeSignalSupported :1; + 0, // HotPlugDevicesSupported :1; + 0, // SmbusSignalSupported :1; + 0 // Reserved :5; + }, + 0x00, // SegmentGroupNum + 0x00, // BusNum + 0 // DevFuncNum + } +}; + + +UINT8 +OemGetPcieSlotNumber ( + VOID + ) +{ + return sizeof (gPcieSlotInfo) / sizeof (SMBIOS_TABLE_TYPE9); +} + +EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM] = { + {{STRING_TOKEN(STR_LEMON_C10_DIMM_000), STRING_TOKEN(STR_LEMON_C10_DIMM_001), STRING_TOKEN(STR_LEMON_C10_DIMM_002)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_010), STRING_TOKEN(STR_LEMON_C10_DIMM_011), STRING_TOKEN(STR_LEMON_C10_DIMM_012)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_020), STRING_TOKEN(STR_LEMON_C10_DIMM_021), STRING_TOKEN(STR_LEMON_C10_DIMM_022)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_030), STRING_TOKEN(STR_LEMON_C10_DIMM_031), STRING_TOKEN(STR_LEMON_C10_DIMM_032)}}, + + {{STRING_TOKEN(STR_LEMON_C10_DIMM_100), STRING_TOKEN(STR_LEMON_C10_DIMM_101), STRING_TOKEN(STR_LEMON_C10_DIMM_102)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_110), STRING_TOKEN(STR_LEMON_C10_DIMM_111), STRING_TOKEN(STR_LEMON_C10_DIMM_112)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_120), STRING_TOKEN(STR_LEMON_C10_DIMM_121), STRING_TOKEN(STR_LEMON_C10_DIMM_122)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_130), STRING_TOKEN(STR_LEMON_C10_DIMM_131), STRING_TOKEN(STR_LEMON_C10_DIMM_132)}} +}; + +EFI_HII_HANDLE +EFIAPI +OemGetPackages ( + ) +{ + return HiiAddPackages ( + &gEfiCallerIdGuid, + NULL, + OemMiscLibHi1616EvbStrings, + NULL, + NULL + ); +} + + diff --git a/Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni b/Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni new file mode 100644 index 0000000000..9f5be02d8a --- /dev/null +++ b/Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni @@ -0,0 +1,56 @@ +// *++ +// +// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+// Copyright (c) 2016, Hisilicon Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// --*/ + +/=# + +#langdef en-US "English" + +// +// Begin English Language Strings +// +#string STR_MEMORY_SUBCLASS_UNKNOWN #language en-US "Unknown" + +// +// DIMM Device Locator strings + +#string STR_LEMON_C10_DIMM_000 #language en-US "J5" +#string STR_LEMON_C10_DIMM_001 #language en-US "J6" +#string STR_LEMON_C10_DIMM_002 #language en-US "J7" +#string STR_LEMON_C10_DIMM_010 #language en-US "J8" +#string STR_LEMON_C10_DIMM_011 #language en-US "J9" +#string STR_LEMON_C10_DIMM_012 #language en-US "J10" +#string STR_LEMON_C10_DIMM_020 #language en-US "J11" +#string STR_LEMON_C10_DIMM_021 #language en-US "J12" +#string STR_LEMON_C10_DIMM_022 #language en-US "J13" +#string STR_LEMON_C10_DIMM_030 #language en-US "J14" +#string STR_LEMON_C10_DIMM_031 #language en-US "J15" +#string STR_LEMON_C10_DIMM_032 #language en-US "J16" +#string STR_LEMON_C10_DIMM_100 #language en-US "J17" +#string STR_LEMON_C10_DIMM_101 #language en-US "J18" +#string STR_LEMON_C10_DIMM_102 #language en-US "J19" +#string STR_LEMON_C10_DIMM_110 #language en-US "J20" +#string STR_LEMON_C10_DIMM_111 #language en-US "J21" +#string STR_LEMON_C10_DIMM_112 #language en-US "J22" +#string STR_LEMON_C10_DIMM_120 #language en-US "J23" +#string STR_LEMON_C10_DIMM_121 #language en-US "J24" +#string STR_LEMON_C10_DIMM_122 #language en-US "J25" +#string STR_LEMON_C10_DIMM_130 #language en-US "J26" +#string STR_LEMON_C10_DIMM_131 #language en-US "J27" +#string STR_LEMON_C10_DIMM_132 #language en-US "J28" + +// +// End English Language Strings +// + diff --git a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c new file mode 100644 index 0000000000..b17eeada16 --- /dev/null +++ b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c @@ -0,0 +1,107 @@ +/** @file +* +* Copyright (c) 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define OEM_SINGLE_SOCKET 1 +#define OEM_DUAL_SOCKET 2 + +REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = { + {67,0,0,0}, + {225,0,0,3}, + {0xFFFF,0xFFFF,0xFFFF,0xFFFF}, + {0xFFFF,0xFFFF,0xFFFF,0xFFFF} +}; + + +BOOLEAN OemIsSocketPresent (UINTN Socket) +{ + if (PcdGet32(PcdSocketMask) & (1 << Socket)) { + return TRUE; + } else { + return FALSE; + } +} + + +UINTN OemGetSocketNumber (VOID) +{ + + if(!OemIsMpBoot()) { + return OEM_SINGLE_SOCKET; + } + + return OEM_DUAL_SOCKET; +} + + +UINTN OemGetDdrChannel (VOID) +{ + return 4; +} + + +UINTN OemGetDimmSlot(UINTN Socket, UINTN Channel) +{ + return 2; +} + +VOID CoreSelectBoot(VOID) +{ + if (!PcdGet64 (PcdTrustedFirmwareEnable)) { + StartupAp (); + } + + return; +} + +BOOLEAN OemIsMpBoot() +{ + return PcdGet32(PcdIsMPBoot); +} + +VOID OemLpcInit(VOID) +{ + LpcInit(); + return; +} + +UINT32 OemIsWarmBoot(VOID) +{ + return 0; +} + +VOID OemBiosSwitch(UINT32 Master) +{ + (VOID)Master; + return; +} + +BOOLEAN OemIsNeedDisableExpanderBuffer(VOID) +{ + return TRUE; +} diff --git a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf new file mode 100644 index 0000000000..4fe7ac6ac6 --- /dev/null +++ b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf @@ -0,0 +1,55 @@ +#/** @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = OemMiscLibHi1616Evb + FILE_GUID = B9CE7465-21A2-4ecd-B347-BBDDBD098CEE + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = OemMiscLib + +[Sources.common] + BoardFeatureD05.c + BoardFeatureD05Strings.uni + OemMiscLibD05.c + +[Packages] + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Hisilicon/HisiPkg.dec + +[LibraryClasses] + PcdLib + TimerLib + +[BuildOptions] + +[Ppis] + gEfiPeiReadOnlyVariable2PpiGuid ## SOMETIMES_CONSUMES + +[Pcd] + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz + gHisiTokenSpaceGuid.PcdIsMPBoot + gHisiTokenSpaceGuid.PcdSocketMask + gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable + +[FixedPcd.common] + +[Guids] + +[Protocols] + diff --git a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c new file mode 100644 index 0000000000..57283a1053 --- /dev/null +++ b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c @@ -0,0 +1,279 @@ +/** @file + + Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2016, Linaro Limited. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include + +UINT64 pcie_subctrl_base_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0000000, 0xa0000000,0xa0000000,0xa0000000,0x8a0000000,0x8a0000000,0x8a0000000,0x8a0000000}, + {0x600a0000000,0x600a0000000,0x600a0000000,0x600a0000000, 0x700a0000000,0x700a0000000,0x700a0000000,0x700a0000000}}; +UINT64 PCIE_APB_SLAVE_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000, 0x8a0090000, 0x8a0200000, 0x8a00a0000, 0x8a00b0000}, + {0x600a0090000, 0x600a0200000, 0x600a00a0000, 0x600a00b0000, 0x700a0090000, 0x700a0200000, 0x700a00a0000, 0x700a00b0000}}; +UINT64 PCIE_PHY_BASE_1610 [PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000, 0x8a00c0000, 0x8a00d0000, 0x8a00e0000, 0x8a00f0000}, + {0x600a00c0000, 0x600a00d0000, 0x600a00e0000, 0x600a00f0000, 0x700a00c0000, 0x700a00d0000, 0x700a00e0000, 0x700a00f0000}}; +UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040}, + {0x400C6010040, 0x400C6010040, 0x400C6010040, 0x400C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040}}; + +PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = { + {// HostBridge 0 + /* Port 0 */ + { + PCI_HB0RB0_ECAM_BASE, //ecam + 0x80, //BusBase + 0x87, //BusLimit + PCI_HB0RB0_PCIREGION_BASE, //Membase + PCI_HB0RB0_CPUMEMREGIONBASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //Memlimit + PCI_HB0RB0_IO_BASE, //IoBase + (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + PCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB0RB0_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB0RB0_PCI_BASE),//RbPciBar + PCI_HB0RB0_PCIREGION_BASE, //PciRegionbase + PCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1 //PciRegionlimit + }, + /* Port 1 */ + { + PCI_HB0RB1_ECAM_BASE,//ecam + 0x90, //BusBase + 0x97, //BusLimit + PCI_HB0RB1_PCIREGION_BASE, //Membase + PCI_HB0RB1_CPUMEMREGIONBASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //MemLimit + (PCI_HB0RB1_IO_BASE), //IoBase + (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimit + PCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB0RB1_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB0RB1_PCI_BASE), //RbPciBar + PCI_HB0RB1_PCIREGION_BASE, //PciRegionbase + PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1 //PciRegionlimit + }, + /* Port 2 */ + { + PCI_HB0RB2_ECAM_BASE, + 0x80, //BusBase + 0x87, //BusLimit + PCI_HB0RB2_CPUMEMREGIONBASE ,//MemBase + PCI_HB0RB2_CPUMEMREGIONBASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit + (PCI_HB0RB2_IO_BASE), //IOBase + (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimit + PCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB0RB2_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB0RB2_PCI_BASE), //RbPciBar + PCI_HB0RB2_PCIREGION_BASE, //PciRegionbase + PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1 //PciRegionlimit + }, + + /* Port 3 */ + { + PCI_HB0RB3_ECAM_BASE, + 0xb0, //BusBase + 0xb7, //BusLimit + (PCI_HB0RB3_ECAM_BASE), //MemBase + (PCI_HB0RB3_CPUMEMREGIONBASE + PCI_HB0RB3_PCIREGION_SIZE - 1), //MemLimit + (PCI_HB0RB3_IO_BASE), //IoBase + (PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB3_IO_SIZE - 1), //IoLimit + PCI_HB0RB3_CPUMEMREGIONBASE, + PCI_HB0RB3_CPUIOREGIONBASE, + (PCI_HB0RB3_PCI_BASE), //RbPciBar + PCI_HB0RB3_PCIREGION_BASE, //PciRegionbase + PCI_HB0RB3_PCIREGION_BASE + PCI_HB0RB3_PCIREGION_SIZE - 1 //PciRegionlimit + }, + /* Port 4 */ + { + PCI_HB0RB4_ECAM_BASE, //ecam + 0x88, //BusBase + 0x8f, //BusLimit + PCI_HB0RB4_CPUMEMREGIONBASE, //Membase + PCI_HB0RB4_CPUMEMREGIONBASE + PCI_HB0RB4_PCIREGION_SIZE - 1, //Memlimit + PCI_HB0RB4_IO_BASE, //IoBase + (PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB4_IO_SIZE - 1), //IoLimit + PCI_HB0RB4_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB0RB4_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB0RB4_PCI_BASE), //RbPciBar + PCI_HB0RB4_PCIREGION_BASE, //PciRegionbase + PCI_HB0RB4_PCIREGION_BASE + PCI_HB0RB4_PCIREGION_SIZE - 1 //PciRegionlimit + }, + /* Port 5 */ + { + PCI_HB0RB5_ECAM_BASE,//ecam + 0x0, //BusBase + 0x7, //BusLimit + PCI_HB0RB5_CPUMEMREGIONBASE, //Membase + PCI_HB0RB5_CPUMEMREGIONBASE + PCI_HB0RB5_PCIREGION_SIZE - 1, //MemLimit + (PCI_HB0RB5_IO_BASE), //IoBase + (PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB5_IO_SIZE - 1), //IoLimit + PCI_HB0RB5_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB0RB5_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB0RB5_PCI_BASE), //RbPciBar + PCI_HB0RB5_PCIREGION_BASE, //PciRegionbase + PCI_HB0RB5_PCIREGION_BASE + PCI_HB0RB5_PCIREGION_SIZE - 1 //PciRegionlimit + }, + /* Port 6 */ + { + PCI_HB0RB6_ECAM_BASE, + 0xC0, //BusBase + 0xC7, //BusLimit + PCI_HB0RB6_PCIREGION_BASE ,//MemBase + PCI_HB0RB6_CPUMEMREGIONBASE + PCI_HB0RB6_PCIREGION_SIZE - 1, //MemLimit + (PCI_HB0RB6_IO_BASE), //IOBase + (PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB6_IO_SIZE - 1), //IoLimit + PCI_HB0RB6_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB0RB6_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB0RB6_PCI_BASE), //RbPciBar + PCI_HB0RB6_PCIREGION_BASE, //PciRegionbase + PCI_HB0RB6_PCIREGION_BASE + PCI_HB0RB6_PCIREGION_SIZE - 1 //PciRegionlimit + }, + + /* Port 7 */ + { + PCI_HB0RB7_ECAM_BASE, + 0x90, //BusBase + 0x97, //BusLimit + PCI_HB0RB7_CPUMEMREGIONBASE, //MemBase + PCI_HB0RB7_CPUMEMREGIONBASE + PCI_HB0RB7_PCIREGION_SIZE - 1, //MemLimit + (PCI_HB0RB7_IO_BASE), //IoBase + (PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB7_IO_SIZE - 1), //IoLimit + PCI_HB0RB7_CPUMEMREGIONBASE, + PCI_HB0RB7_CPUIOREGIONBASE, + (PCI_HB0RB7_PCI_BASE), //RbPciBar + PCI_HB0RB7_PCIREGION_BASE, //PciRegionbase + PCI_HB0RB7_PCIREGION_BASE + PCI_HB0RB7_PCIREGION_SIZE - 1 //PciRegionlimit + } + }, +{// HostBridge 1 + /* Port 0 */ + { + PCI_HB1RB0_ECAM_BASE, + 0x80, //BusBase + 0x87, //BusLimit + (PCI_HB1RB0_ECAM_BASE), //MemBase + (PCI_HB1RB0_CPUMEMREGIONBASE + PCI_HB1RB0_PCIREGION_SIZE - 1), //MemLimit + PCI_HB1RB0_IO_BASE, //IoBase + (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + PCI_HB1RB0_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB1RB0_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB1RB0_PCI_BASE), //RbPciBar + PCI_HB1RB0_PCIREGION_BASE, //PciRegionbase + PCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit + }, + /* Port 1 */ + { + PCI_HB1RB1_ECAM_BASE, + 0x90, //BusBase + 0x97, //BusLimit + (PCI_HB1RB1_ECAM_BASE), //MemBase + (PCI_HB1RB1_CPUMEMREGIONBASE + PCI_HB1RB1_PCIREGION_SIZE - 1), //MemLimit + PCI_HB1RB1_IO_BASE, //IoBase + (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + PCI_HB1RB1_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB1RB1_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB1RB1_PCI_BASE), //RbPciBar + PCI_HB1RB1_PCIREGION_BASE, //PciRegionbase + PCI_HB1RB1_PCIREGION_BASE + PCI_HB1RB1_PCIREGION_SIZE - 1 //PciRegionlimit + }, + /* Port 2 */ + { + PCI_HB1RB2_ECAM_BASE, + 0x10, //BusBase + 0x1f, //BusLimit + PCI_HB1RB2_CPUMEMREGIONBASE, //MemBase + PCI_HB1RB2_CPUMEMREGIONBASE + PCI_HB1RB2_PCIREGION_SIZE - 1, //MemLimit + PCI_HB1RB2_IO_BASE, //IoBase + (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + PCI_HB1RB2_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB1RB2_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB1RB2_PCI_BASE), //RbPciBar + PCI_HB1RB2_PCIREGION_BASE, //PciRegionbase + PCI_HB1RB2_PCIREGION_BASE + PCI_HB1RB2_PCIREGION_SIZE - 1 //PciRegionlimit + }, + + /* Port 3 */ + { + PCI_HB1RB3_ECAM_BASE, + 0xb0, //BusBase + 0xb7, //BusLimit + (PCI_HB1RB3_ECAM_BASE), //MemBase + (PCI_HB1RB3_CPUMEMREGIONBASE + PCI_HB1RB3_PCIREGION_SIZE - 1), //MemLimit + PCI_HB1RB3_IO_BASE, //IoBase + (PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + PCI_HB1RB3_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB1RB3_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB1RB3_PCI_BASE), //RbPciBar + PCI_HB1RB3_PCIREGION_BASE, //PciRegionbase + PCI_HB1RB3_PCIREGION_BASE + PCI_HB1RB3_PCIREGION_SIZE - 1 //PciRegionlimit + }, + /* Port 4 */ + { + PCI_HB1RB4_ECAM_BASE, + 0x20, //BusBase + 0x2f, //BusLimit + PCI_HB1RB4_CPUMEMREGIONBASE, //MemBase + PCI_HB1RB4_CPUMEMREGIONBASE + PCI_HB1RB4_PCIREGION_SIZE - 1, //MemLimit + PCI_HB1RB4_IO_BASE, //IoBase + (PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + PCI_HB1RB4_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB1RB4_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB1RB4_PCI_BASE), //RbPciBar + PCI_HB1RB4_PCIREGION_BASE, //PciRegionbase + PCI_HB1RB4_PCIREGION_BASE + PCI_HB1RB4_PCIREGION_SIZE - 1 //PciRegionlimit + }, + /* Port 5 */ + { + PCI_HB1RB5_ECAM_BASE, + 0x30, //BusBase + 0x3f, //BusLimit + PCI_HB1RB5_CPUMEMREGIONBASE, //MemBase + PCI_HB1RB5_CPUMEMREGIONBASE + PCI_HB1RB5_PCIREGION_SIZE - 1, //MemLimit + PCI_HB1RB5_IO_BASE, //IoBase + (PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + PCI_HB1RB5_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB1RB5_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB1RB5_PCI_BASE), //RbPciBar + PCI_HB1RB5_PCIREGION_BASE, //PciRegionbase + PCI_HB1RB5_PCIREGION_BASE + PCI_HB1RB5_PCIREGION_SIZE - 1 //PciRegionlimit + }, + /* Port 6 */ + { + PCI_HB1RB6_ECAM_BASE, + 0xa8, //BusBase + 0xaf, //BusLimit + (PCI_HB1RB6_ECAM_BASE), //MemBase + PCI_HB1RB6_CPUMEMREGIONBASE + PCI_HB1RB6_PCIREGION_SIZE - 1, //MemLimit + PCI_HB1RB6_IO_BASE, //IoBase + (PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + PCI_HB1RB6_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB1RB6_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB1RB6_PCI_BASE), //RbPciBar + PCI_HB1RB6_PCIREGION_BASE, //PciRegionbase + PCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit + }, + + /* Port 7 */ + { + PCI_HB1RB7_ECAM_BASE, + 0xb8, //BusBase + 0xbf, //BusLimit + (PCI_HB1RB7_ECAM_BASE), //MemBase + PCI_HB1RB7_CPUMEMREGIONBASE + PCI_HB1RB7_PCIREGION_SIZE - 1, //MemLimit + PCI_HB1RB7_IO_BASE, //IoBase + (PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + PCI_HB1RB7_CPUMEMREGIONBASE, //CpuMemRegionBase + PCI_HB1RB7_CPUIOREGIONBASE, //CpuIoRegionBase + (PCI_HB1RB7_PCI_BASE), //RbPciBar + PCI_HB1RB7_PCIREGION_BASE, //PciRegionbase + PCI_HB1RB7_PCIREGION_BASE + PCI_HB1RB7_PCIREGION_SIZE - 1 //PciRegionlimit + } + + } +}; + diff --git a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf new file mode 100644 index 0000000000..cd64193635 --- /dev/null +++ b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf @@ -0,0 +1,183 @@ +## @file +# +# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2016, Linaro Limited. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +## + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = PlatformPciLib + FILE_GUID = 61b7276a-fc67-11e5-82fd-47ea9896dd5d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + +[Sources] + PlatformPciLib.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/Hisilicon/HisiPkg.dec + +[LibraryClasses] + PcdLib + +[FixedPcd] + gHisiTokenSpaceGuid.PcdHb1BaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize + gHisiTokenSpaceGuid.PciHb0Rb0Base + gHisiTokenSpaceGuid.PciHb0Rb1Base + gHisiTokenSpaceGuid.PciHb0Rb2Base + gHisiTokenSpaceGuid.PciHb0Rb3Base + gHisiTokenSpaceGuid.PciHb0Rb4Base + gHisiTokenSpaceGuid.PciHb0Rb5Base + gHisiTokenSpaceGuid.PciHb0Rb6Base + gHisiTokenSpaceGuid.PciHb0Rb7Base + gHisiTokenSpaceGuid.PciHb1Rb0Base + gHisiTokenSpaceGuid.PciHb1Rb1Base + gHisiTokenSpaceGuid.PciHb1Rb2Base + gHisiTokenSpaceGuid.PciHb1Rb3Base + gHisiTokenSpaceGuid.PciHb1Rb4Base + gHisiTokenSpaceGuid.PciHb1Rb5Base + gHisiTokenSpaceGuid.PciHb1Rb6Base + gHisiTokenSpaceGuid.PciHb1Rb7Base + gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress + gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress + + gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize + gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize + gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize + + gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase + + gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase + gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase + + gHisiTokenSpaceGuid.PcdHb0Rb0IoBase + gHisiTokenSpaceGuid.PcdHb0Rb0IoSize + gHisiTokenSpaceGuid.PcdHb0Rb1IoBase + gHisiTokenSpaceGuid.PcdHb0Rb1IoSize + gHisiTokenSpaceGuid.PcdHb0Rb2IoBase + gHisiTokenSpaceGuid.PcdHb0Rb2IoSize + gHisiTokenSpaceGuid.PcdHb0Rb3IoBase + gHisiTokenSpaceGuid.PcdHb0Rb3IoSize + gHisiTokenSpaceGuid.PcdHb0Rb4IoBase + gHisiTokenSpaceGuid.PcdHb0Rb4IoSize + gHisiTokenSpaceGuid.PcdHb0Rb5IoBase + gHisiTokenSpaceGuid.PcdHb0Rb5IoSize + gHisiTokenSpaceGuid.PcdHb0Rb6IoBase + gHisiTokenSpaceGuid.PcdHb0Rb6IoSize + gHisiTokenSpaceGuid.PcdHb0Rb7IoBase + gHisiTokenSpaceGuid.PcdHb0Rb7IoSize + gHisiTokenSpaceGuid.PcdHb1Rb0IoBase + gHisiTokenSpaceGuid.PcdHb1Rb0IoSize + gHisiTokenSpaceGuid.PcdHb1Rb1IoBase + gHisiTokenSpaceGuid.PcdHb1Rb1IoSize + gHisiTokenSpaceGuid.PcdHb1Rb2IoBase + gHisiTokenSpaceGuid.PcdHb1Rb2IoSize + gHisiTokenSpaceGuid.PcdHb1Rb3IoBase + gHisiTokenSpaceGuid.PcdHb1Rb3IoSize + gHisiTokenSpaceGuid.PcdHb1Rb4IoBase + gHisiTokenSpaceGuid.PcdHb1Rb4IoSize + gHisiTokenSpaceGuid.PcdHb1Rb5IoBase + gHisiTokenSpaceGuid.PcdHb1Rb5IoSize + gHisiTokenSpaceGuid.PcdHb1Rb6IoBase + gHisiTokenSpaceGuid.PcdHb1Rb6IoSize + gHisiTokenSpaceGuid.PcdHb1Rb7IoBase + gHisiTokenSpaceGuid.PcdHb1Rb7IoSize + diff --git a/Platform/Hisilicon/HiKey/HiKey.dec b/Platform/Hisilicon/HiKey/HiKey.dec new file mode 100644 index 0000000000..537138eb45 --- /dev/null +++ b/Platform/Hisilicon/HiKey/HiKey.dec @@ -0,0 +1,36 @@ +# +# Copyright (c) 2014-2017, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[Defines] + DEC_SPECIFICATION = 0x00010019 + PACKAGE_NAME = HiKey + PACKAGE_GUID = d6db414d-ea67-4312-94d5-9c9e5b224d25 + PACKAGE_VERSION = 0.1 + +################################################################################ +# +# Include Section - list of Include Paths that are provided by this package. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +################################################################################ +[Includes.common] + Include # Root include for the package + +[Guids.common] + gHiKeyTokenSpaceGuid = { 0x91148425, 0xcdd2, 0x4830, { 0x8b, 0xd0, 0xc6, 0x1c, 0x6d, 0xea, 0x36, 0x21 } } + +[PcdsFixedAtBuild.common] + gHiKeyTokenSpaceGuid.PcdAndroidFastbootNvmDevicePath|L""|VOID*|0x00000001 + gHiKeyTokenSpaceGuid.PcdArmFastbootFlashLimit|L""|VOID*|0x00000002 diff --git a/Platform/Hisilicon/HiKey/HiKey.dsc b/Platform/Hisilicon/HiKey/HiKey.dsc new file mode 100644 index 0000000000..1bc8ae4ce8 --- /dev/null +++ b/Platform/Hisilicon/HiKey/HiKey.dsc @@ -0,0 +1,482 @@ +# +# Copyright (c) 2014-2017, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = HiKey + PLATFORM_GUID = 8edf1480-da5c-4857-bc02-7530bd8e7b7a + PLATFORM_VERSION = 0.2 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/HiKey + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/Hisilicon/HiKey/HiKey.fdf + +[LibraryClasses.common] +!if $(TARGET) == RELEASE + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!endif + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf + + ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf + ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf + ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf + ArmHvcLib|ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf + + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf + ArmPlatformLib|Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf + ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf + ArmPlatformSysConfigLib|ArmPlatformPkg/Library/ArmPlatformSysConfigLibNull/ArmPlatformSysConfigLibNull.inf + + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf + CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf + ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf + + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf + PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf + + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + + # UiApp dependencies + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf + + PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf + SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf + RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf + TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf + + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf + + # + # Assume everything is fixed at build + # + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf + + # USB Requirements + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf + + UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf + + # Network Libraries + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf + DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf + IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf + UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf + + # It is not possible to prevent compilers from generating calls to generic + # intrinsic functions. This library provides the intrinsic functions + # generated by a given compiler. + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf + + # Add support for GCC stack protector + NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf + +[LibraryClasses.common.SEC] + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf + ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf + LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf + PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf + PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf + MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf + ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLibBase.inf + +[LibraryClasses.common.DXE_CORE] + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf + +[LibraryClasses.common.UEFI_DRIVER] + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf + +[LibraryClasses.common.DXE_DRIVER] + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf + +[BuildOptions] + GCC:*_*_*_PLATFORM_FLAGS = -I$(WORKSPACE)/Silicon/Hisilicon/Hi6220/Include -I$(WORKSPACE)/Platform/Hisilicon/HiKey/Include + +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000 + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + +[PcdsFeatureFlag.common] + # + # Control what commands are supported from the UI + # Turn these on and off to add features or save size + # + gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|TRUE + gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE + gEmbeddedTokenSpaceGuid.PcdEmbeddedHobCmd|TRUE + gEmbeddedTokenSpaceGuid.PcdEmbeddedHwDebugCmd|TRUE + gEmbeddedTokenSpaceGuid.PcdEmbeddedPciDebugCmd|TRUE + gEmbeddedTokenSpaceGuid.PcdEmbeddedIoEnable|FALSE + gEmbeddedTokenSpaceGuid.PcdEmbeddedScriptCmd|FALSE + + gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE + + # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress + gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE + + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE + + gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE + + ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. + # It could be set FALSE to save size. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|FALSE + + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE + +[PcdsFixedAtBuild.common] + gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000 + gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1 + gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0 + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 + + # DEBUG_ASSERT_ENABLED 0x01 + # DEBUG_PRINT_ENABLED 0x02 + # DEBUG_CODE_ENABLED 0x04 + # CLEAR_MEMORY_ENABLED 0x08 + # ASSERT_BREAKPOINT_ENABLED 0x10 + # ASSERT_DEADLOOP_ENABLED 0x20 +!if $(TARGET) == RELEASE + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f +!endif + + # DEBUG_INIT 0x00000001 // Initialization + # DEBUG_WARN 0x00000002 // Warnings + # DEBUG_LOAD 0x00000004 // Load events + # DEBUG_FS 0x00000008 // EFI File system + # DEBUG_POOL 0x00000010 // Alloc & Free's + # DEBUG_PAGE 0x00000020 // Alloc & Free's + # DEBUG_INFO 0x00000040 // Verbose + # DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers + # DEBUG_VARIABLE 0x00000100 // Variable + # DEBUG_BM 0x00000400 // Boot Manager + # DEBUG_BLKIO 0x00001000 // BlkIo Driver + # DEBUG_NET 0x00004000 // SNI Driver + # DEBUG_UNDI 0x00010000 // UNDI Driver + # DEBUG_LOADFILE 0x00020000 // Load File + # DEBUG_EVENT 0x00080000 // Event messages + # DEBUG_GCD 0x00100000 // Global Coherency Database changes + # DEBUG_CACHE 0x00200000 // Memory range cachability changes + # DEBUG_ERROR 0x80000000 // Error + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F + + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + + # + # Optional feature to help prevent EFI memory map fragments + # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob + # Values are in EFI Pages (4K). DXE Core will make sure that + # at least this much of each type of memory can be allocated + # from a single memory range. This way you only end up with + # maximum of two fragements for each type in the memory map + # (the memory used, and the free memory that was prereserved + # but not used). + # + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|65 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0 + + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4 + + gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|"" + gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07 + gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000 + + gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"hikey" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Alpha" + gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"HiKey" + + # + # NV Storage PCDs. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x30000000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x30010000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x30020000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000 + + # System Memory (1GB) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x3E000000 + + # HiKey Dual-Cluster profile + gArmPlatformTokenSpaceGuid.PcdCoreCount|8 + gArmPlatformTokenSpaceGuid.PcdClusterCount|2 + + gArmTokenSpaceGuid.PcdVFPEnabled|1 + + # + # ARM PrimeCell + # + + ## PL011 - Serial Terminal + DEFINE SERIAL_BASE = 0xF7113000 # UART3 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|$(SERIAL_BASE) + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + gArmPlatformTokenSpaceGuid.PL011UartInteger|10 + gArmPlatformTokenSpaceGuid.PL011UartFractional|26 + + ## PL031 RealTimeClock + gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0xF8003000 + + # + # ARM General Interrupt Controller + # + gArmTokenSpaceGuid.PcdGicDistributorBase|0xF6801000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xF6802000 + + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|10 + + # GUID of the UI app + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 } + + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE + + gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000 + + # + # DW MMC/SD card controller + # + gEmbeddedTokenSpaceGuid.PcdDwEmmcDxeBaseAddress|0xF723D000 + gEmbeddedTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz|100000000 + + # + # + # Fastboot + # + gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbVendorId|0x18d1 + gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbProductId|0xd00d + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ +[Components.common] + # + # PEI Phase modules + # + ArmPlatformPkg/PrePi/PeiUniCore.inf + + # + # DXE + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf + } + + # + # Architectural Protocols + # + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf + + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + # + # GPIO + # + ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf + + # + # MMC/SD + # + EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf + EmbeddedPkg/Drivers/DwEmmcDxe/DwEmmcDxe.inf + + # + # USB Host Support + # + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + + # + # USB Mass Storage Support + # + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # + # USB Peripheral Support + # + EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf + + # + # Fastboot + # + EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf { + + BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf + } + + + # + # UEFI Network Stack + # + MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf + MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf + MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf + MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf + MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf + MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf + MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf + MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf + MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf + + # + # AX88772 Ethernet Driver + # + OptionRomPkg/Bus/Usb/UsbNetworking/Ax88772b/Ax88772b.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Application/UiApp/UiApp.inf { + + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + } + ShellPkg/Application/Shell/Shell.inf { + + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 + } diff --git a/Platform/Hisilicon/HiKey/HiKey.fdf b/Platform/Hisilicon/HiKey/HiKey.fdf new file mode 100644 index 0000000000..d277bd6ce3 --- /dev/null +++ b/Platform/Hisilicon/HiKey/HiKey.fdf @@ -0,0 +1,351 @@ +# +# Copyright (c) 2014-2017, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ + +[FD.BL33_AP_UEFI] +BaseAddress = 0x35000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. +Size = 0x000F0000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +ErasePolarity = 1 + +# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x00001000 +NumBlocks = 0xF0 + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +################################################################################ + +0x00000000|0x000F0000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT + + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +[FV.FvMain] +FvNameGuid = 69b7d469-55a2-49d8-a426-42bfb22f5b9d +BlockSize = 0x40 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 8 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + # + # GPIO + # + INF ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf + + # + # Multimedia Card Interface + # + INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf + INF EmbeddedPkg/Drivers/DwEmmcDxe/DwEmmcDxe.inf + + # + # USB Host Support + # + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + + # + # USB Mass Storage Support + # + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # + # USB Peripheral Support + # + INF EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf + + # + # Fastboot + # + INF EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf + + # + # UEFI Network Stack + # + INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf + INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf + INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf + INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf + INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf + INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf + INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf + INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf + INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf + + # + # AX88772 Ethernet Driver for Apple Ethernet Adapter + # + INF OptionRomPkg/Bus/Usb/UsbNetworking/Ax88772b/Ax88772b.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatBinPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf + + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # + # UEFI applications + # + INF ShellPkg/Application/Shell/Shell.inf + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Application/UiApp/UiApp.inf + +[FV.FVMAIN_COMPACT] +FvAlignment = 8 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF ArmPlatformPkg/PrePi/PeiUniCore.inf + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } + } + + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ + + +############################################################################ +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section # +############################################################################ +# +#[Rule.Common.DXE_DRIVER] +# FILE DRIVER = $(NAMED_GUID) { +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex +# COMPRESS PI_STD { +# GUIDED { +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi +# UI STRING="$(MODULE_NAME)" Optional +# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) +# } +# } +# } +# +############################################################################ + +# +# These SEC rules are used for ArmPlatformPkg/PrePi module. +# ArmPlatformPkg/PrePi is declared as a SEC module to make GenFv patch the +# UEFI Firmware to jump to ArmPlatformPkg/PrePi entrypoint +# +[Rule.ARM.SEC] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { + TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.AARCH64.SEC] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { + TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +# A shim specific rule is required to ensure the alignment is 4K. +# Otherwise BaseTools pick up the AArch32 alignment (ie: 32) +[Rule.ARM.SEC.SHIM] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { + TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE = $(NAMED_GUID) { + TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING ="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM] + FILE PEIM = $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.TIANOCOMPRESSED] + FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE = $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_DRIVER.BINARY] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION = $(NAMED_GUID) { + UI STRING ="$(MODULE_NAME)" Optional + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION = $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM = $(NAMED_GUID) { + RAW ACPI |.acpi + RAW ASL |.aml + } diff --git a/Platform/Hisilicon/HiKey/Include/ArmPlatform.h b/Platform/Hisilicon/HiKey/Include/ArmPlatform.h new file mode 100644 index 0000000000..e60478f6b7 --- /dev/null +++ b/Platform/Hisilicon/HiKey/Include/ArmPlatform.h @@ -0,0 +1,26 @@ +/** @file +* +* Copyright (c) 2014-2017, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __PLATFORM_H__ +#define __PLATFORM_H__ + +// +// We don't care about this value, but the PL031 driver depends on the macro +// to exist: it will pass it on to our ArmPlatformSysConfigLib:ConfigGet() +// function, which just returns EFI_UNSUPPORTED. +// +// +#define SYS_CFG_RTC 0 + +#endif /* __PLATFORM_H__ */ diff --git a/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKey.c b/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKey.c new file mode 100644 index 0000000000..f4a47b2849 --- /dev/null +++ b/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKey.c @@ -0,0 +1,159 @@ +/** @file +* +* Copyright (c) 2014-2017, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include +#include + +#include + +#include + +ARM_CORE_INFO mHiKeyInfoTable[] = { + { + // Cluster 0, Core 0 + 0x0, 0x0, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (UINT64)0xFFFFFFFF + }, + { + // Cluster 0, Core 1 + 0x0, 0x1, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (UINT64)0xFFFFFFFF + }, + { + // Cluster 0, Core 2 + 0x0, 0x2, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (UINT64)0xFFFFFFFF + }, + { + // Cluster 0, Core 3 + 0x0, 0x3, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (UINT64)0xFFFFFFFF + }, + { + // Cluster 1, Core 0 + 0x1, 0x0, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (UINT64)0xFFFFFFFF + }, + { + // Cluster 1, Core 1 + 0x1, 0x1, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (UINT64)0xFFFFFFFF + }, + { + // Cluster 1, Core 2 + 0x1, 0x2, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (UINT64)0xFFFFFFFF + }, + { + // Cluster 1, Core 3 + 0x1, 0x3, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (UINT64)0xFFFFFFFF + } +}; + +/** + Return the current Boot Mode + + This function returns the boot reason on the platform + + @return Return the current Boot Mode of the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +/** + Initialize controllers that must setup in the normal world + + This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim + in the PEI phase. + +**/ +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + return RETURN_SUCCESS; +} + +/** + Initialize the system (or sometimes called permanent) memory + + This memory is generally represented by the DRAM. + +**/ +VOID +ArmPlatformInitializeSystemMemory ( + VOID + ) +{ +} + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + // Only support one cluster + *CoreCount = sizeof(mHiKeyInfoTable) / sizeof(ARM_CORE_INFO); + *ArmCoreTable = mHiKeyInfoTable; + return EFI_SUCCESS; +} + +// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore +EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID; +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo }; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &mArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize = sizeof(gPlatformPpiTable); + *PpiList = gPlatformPpiTable; +} diff --git a/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyHelper.S b/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyHelper.S new file mode 100644 index 0000000000..0e8f1bbacd --- /dev/null +++ b/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyHelper.S @@ -0,0 +1,49 @@ +# +# Copyright (c) 2014-2017, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# + +#include +#include + +ASM_FUNC(ArmPlatformPeiBootAction) + ret + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +// With this function: CorePos = (ClusterId * 4) + CoreId +ASM_FUNC(ArmPlatformGetCorePosition) + and x1, x0, #ARM_CORE_MASK + and x0, x0, #ARM_CLUSTER_MASK + add x0, x1, x0, LSR #6 + ret + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId) + MOV32 (w0, FixedPcdGet32(PcdArmPrimaryCore)) + ret + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_FUNC(ArmPlatformIsPrimaryCore) + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCoreMask)) + and x0, x0, x1 + MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCore)) + cmp w0, w1 + cset x0, eq + ret diff --git a/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf b/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf new file mode 100644 index 0000000000..79723d3b17 --- /dev/null +++ b/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyLib.inf @@ -0,0 +1,51 @@ +# +# Copyright (c) 2014-2017, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = HiKeyLib + FILE_GUID = 1f6c5192-f35c-462d-877c-8ee3227fff01 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmPlatformLib + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Platform/Hisilicon/HiKey/HiKey.dec + Silicon/Hisilicon/Hi6220/Hi6220.dec + +[LibraryClasses] + ArmLib + HobLib + IoLib + MemoryAllocationLib + SerialPortLib + +[Sources.common] + HiKey.c + HiKeyMem.c + +[Sources.AARCH64] + HiKeyHelper.S + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdCacheEnable + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmPrimaryCore + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize diff --git a/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyMem.c b/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyMem.c new file mode 100644 index 0000000000..c388a7a5ab --- /dev/null +++ b/Platform/Hisilicon/HiKey/Library/HiKeyLib/HiKeyMem.c @@ -0,0 +1,204 @@ +/** @file +* +* Copyright (c) 2014-2017, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include +#include +#include +#include + +#include + +// The total number of descriptors, including the final "end-of-table" descriptor. +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 12 + +// DDR attributes +#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK +#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED + +#define HIKEY_EXTRA_SYSTEM_MEMORY_BASE 0x40000000 +#define HIKEY_EXTRA_SYSTEM_MEMORY_SIZE 0x40000000 + +STATIC struct HiKeyReservedMemory { + EFI_PHYSICAL_ADDRESS Offset; + EFI_PHYSICAL_ADDRESS Size; +} HiKeyReservedMemoryBuffer [] = { + { 0x05E00000, 0x00100000 }, // MCU + { 0x05F01000, 0x00001000 }, // ADB REBOOT "REASON" + { 0x06DFF000, 0x00001000 }, // MAILBOX + { 0x0740F000, 0x00001000 }, // MAILBOX + { 0x21F00000, 0x00100000 }, // PSTORE/RAMOOPS + { 0x3E000000, 0x02000000 } // TEE OS +}; + +STATIC +UINT64 +EFIAPI +HiKeyInitMemorySize ( + IN VOID + ) +{ + UINT32 Data; + UINT64 MemorySize; + + Data = MmioRead32 (MDDRC_AXI_BASE + AXI_REGION_MAP); + MemorySize = HIKEY_REGION_SIZE(Data); + return MemorySize; +} + +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to- + Virtual Memory mapping. This array must be ended by a zero-filled + entry + +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap + ) +{ + ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes; + UINTN Index = 0, Count, ReservedTop; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + EFI_PEI_HOB_POINTERS NextHob; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; + UINT64 ResourceLength; + EFI_PHYSICAL_ADDRESS ResourceTop; + UINT64 MemorySize, AdditionalMemorySize; + + MemorySize = HiKeyInitMemorySize (); + if (MemorySize == 0) { + MemorySize = PcdGet64 (PcdSystemMemorySize); + } + + ResourceAttributes = ( + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED + ); + + // Create initial Base Hob for system memory. + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + PcdGet64 (PcdSystemMemoryBase), + PcdGet64 (PcdSystemMemorySize) + ); + + NextHob.Raw = GetHobList (); + Count = sizeof (HiKeyReservedMemoryBuffer) / sizeof (struct HiKeyReservedMemory); + while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) { + if (Index >= Count) { + break; + } + if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) && + (HiKeyReservedMemoryBuffer[Index].Offset >= NextHob.ResourceDescriptor->PhysicalStart) && + ((HiKeyReservedMemoryBuffer[Index].Offset + HiKeyReservedMemoryBuffer[Index].Size) <= + NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDescriptor->ResourceLength)) { + ResourceAttributes = NextHob.ResourceDescriptor->ResourceAttribute; + ResourceLength = NextHob.ResourceDescriptor->ResourceLength; + ResourceTop = NextHob.ResourceDescriptor->PhysicalStart + ResourceLength; + ReservedTop = HiKeyReservedMemoryBuffer[Index].Offset + HiKeyReservedMemoryBuffer[Index].Size; + + // Create the System Memory HOB for the reserved buffer + BuildResourceDescriptorHob (EFI_RESOURCE_MEMORY_RESERVED, + EFI_RESOURCE_ATTRIBUTE_PRESENT, + HiKeyReservedMemoryBuffer[Index].Offset, + HiKeyReservedMemoryBuffer[Index].Size); + // Update the HOB + NextHob.ResourceDescriptor->ResourceLength = HiKeyReservedMemoryBuffer[Index].Offset - NextHob.ResourceDescriptor->PhysicalStart; + + // If there is some memory available on the top of the reserved memory then create a HOB + if (ReservedTop < ResourceTop) { + BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + ReservedTop, + ResourceTop - ReservedTop); + } + Index++; + } + NextHob.Raw = GET_NEXT_HOB (NextHob); + } + + AdditionalMemorySize = MemorySize - PcdGet64 (PcdSystemMemorySize); + if (AdditionalMemorySize >= SIZE_1GB) { + // Declared the additional memory + ResourceAttributes = + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED; + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + HIKEY_EXTRA_SYSTEM_MEMORY_BASE, + HIKEY_EXTRA_SYSTEM_MEMORY_SIZE); + } + + ASSERT (VirtualMemoryMap != NULL); + + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); + if (VirtualMemoryTable == NULL) { + return; + } + + if (FeaturePcdGet(PcdCacheEnable) == TRUE) { + CacheAttributes = DDR_ATTRIBUTES_CACHED; + } else { + CacheAttributes = DDR_ATTRIBUTES_UNCACHED; + } + + Index = 0; + + // Hi6220 SOC peripherals + VirtualMemoryTable[Index].PhysicalBase = HI6220_PERIPH_BASE; + VirtualMemoryTable[Index].VirtualBase = HI6220_PERIPH_BASE; + VirtualMemoryTable[Index].Length = HI6220_PERIPH_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // DDR - predefined 1GB size + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase); + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase); + VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize); + VirtualMemoryTable[Index].Attributes = CacheAttributes; + + // If DDR capacity is 2GB size, append a new entry to fill the gap. + if (AdditionalMemorySize >= SIZE_1GB) { + VirtualMemoryTable[++Index].PhysicalBase = HIKEY_EXTRA_SYSTEM_MEMORY_BASE; + VirtualMemoryTable[Index].VirtualBase = HIKEY_EXTRA_SYSTEM_MEMORY_BASE; + VirtualMemoryTable[Index].Length = HIKEY_EXTRA_SYSTEM_MEMORY_SIZE; + VirtualMemoryTable[Index].Attributes = CacheAttributes; + } + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase = 0; + VirtualMemoryTable[Index].VirtualBase = 0; + VirtualMemoryTable[Index].Length = 0; + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; + + ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + + *VirtualMemoryMap = VirtualMemoryTable; +} -- cgit v1.2.3