From 8b2982cd59533486c31f6effae45cdf7899209b8 Mon Sep 17 00:00:00 2001
From: Jiewen Yao <jiewen.yao@intel.com>
Date: Sat, 17 Mar 2018 07:41:44 +0800
Subject: PurleyOpenBoardPkg: Initial version.

Cc: Isaac W Oram <isaac.w.oram@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Isaac W Oram <isaac.w.oram@intel.com>
---
 .../Acpi/BoardAcpiDxe/Dsdt/PlatformGpe.asi         | 84 ++++++++++++++++++++++
 1 file changed, 84 insertions(+)
 create mode 100644 Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGpe.asi

(limited to 'Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGpe.asi')

diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGpe.asi b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGpe.asi
new file mode 100644
index 0000000000..ec7c3e3315
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGpe.asi
@@ -0,0 +1,84 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+//  General Purpose Event
+#include "MaxSocket.h"
+
+Scope (\_GPE) {
+
+  //
+  // ME HECI2 SCI handler
+  // Note: This SCI from HECI2 is routed to ICH9 over the DMI and it
+  // sets the DMISCI status bit in TCO block. From there it is routed
+  // to bit6 GPE0 status register.
+  //
+  OperationRegion (TCOS, SystemIO, 0x464, 2) // ICH_ACPI_BASE_ADDRESS + TCO_BASE + R_TCO1_STS
+  Field (TCOS, ByteAcc, NoLock, WriteAsZeros) {
+         Offset (0x1),
+         , 1,
+         DSCI, 1,
+  }
+
+  Method(NTFI, 2){
+    If(And(Arg0, 0x01)){
+      Notify(\_SB.PC06, Arg1)
+      Notify(\_SB.PC07, Arg1)
+      Notify(\_SB.PC08, Arg1)
+      Notify(\_SB.PC09, Arg1)
+      Notify(\_SB.PC10, Arg1)
+      Notify(\_SB.PC11, Arg1)   
+    }
+    If(And(Arg0, 0x02)){
+      Notify(\_SB.PC12, Arg1)
+      Notify(\_SB.PC13, Arg1)
+      Notify(\_SB.PC14, Arg1)
+      Notify(\_SB.PC15, Arg1)
+      Notify(\_SB.PC16, Arg1)
+      Notify(\_SB.PC17, Arg1)  
+    }
+    If(And(Arg0, 0x04)){
+      Notify(\_SB.PC18, Arg1)
+      Notify(\_SB.PC19, Arg1)
+      Notify(\_SB.PC20, Arg1)
+      Notify(\_SB.PC21, Arg1)
+      Notify(\_SB.PC22, Arg1)
+      Notify(\_SB.PC23, Arg1)   
+    }
+  } //End Method NTFI
+
+  // Tell OS to run thru the new status of this device (Software SCI generated from SMM for all Hot plug events)
+  Method (_L62, 0x0, NotSerialized) {
+    if(LEqual(SCI0, 3)) { // Device ejection (Invoked with _EJ0 method called)
+      Store (0, SCI0)
+    } else {              // Device check (OS can still reject online request based on resources and capability)
+      NTFI (IIOP, 0)
+      Store (0, MEBC)
+      Store (0, CPHP)
+      Store (0, IIOP)
+    }
+    Store (0, SGPC)
+    Store (1, SGPS)
+
+  }
+
+  // PME supported for Slots, use GPE 9 for PME
+  // Hot plug on all slots for now, change later.
+  // Slot numbers on silk screen might be different than the port number, currently use port numbers.
+  //
+  // IIO PCI_E Slot Hotplug GPE Event
+  //
+  Method (_L61, 0, NotSerialized) {
+    #include "IioPcieHotPlugGpeHandler.asl"
+  }// end of _L01 GPE Method
+
+}// end of _GPE scope.
-- 
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